update Makefile
diff --git a/Makefile b/Makefile
index e318397..f7a9fba 100644
--- a/Makefile
+++ b/Makefile
@@ -20,19 +20,25 @@
MCW_ROOT?=$(PWD)/mgmt_core_wrapper
SIM?=RTL
-export SKYWATER_COMMIT=f70d8ca46961ff92719d8870a18a076370b85f6c
-export OPEN_PDKS_COMMIT?=41c0908b47130d5675ff8484255b43f66463a7d6
-export OPENLANE_TAG=2022.07.02_01.38.08
+#export SKYWATER_COMMIT=f70d8ca46961ff92719d8870a18a076370b85f6c
+#export OPEN_PDKS_COMMIT?=41c0908b47130d5675ff8484255b43f66463a7d6
+#export OPENLANE_TAG=2022.07.02_01.38.08
# Install lite version of caravel, (1): caravel-lite, (0): caravel
CARAVEL_LITE?=1
# PDK switch varient
export PDK?=sky130B
+#export PDK?=gf180mcu
export PDKPATH?=$(PDK_ROOT)/$(PDK)
+
MPW_TAG ?= mpw-7a
+ifeq ($(PDK),sky130B)
+ SKYWATER_COMMIT=f70d8ca46961ff92719d8870a18a076370b85f6c
+ OPEN_PDKS_COMMIT?=41c0908b47130d5675ff8484255b43f66463a7d6
+ OPENLANE_TAG=2022.07.02_01.38.08
ifeq ($(CARAVEL_LITE),1)
CARAVEL_NAME := caravel-lite
@@ -44,6 +50,8 @@
CARAVEL_TAG := $(MPW_TAG)
endif
+endif
+
# Include Caravel Makefile Targets
.PHONY: % : check-caravel
%:
diff --git a/openlane/user_proj_example/config.json b/openlane/user_proj_example/config.json
new file mode 100644
index 0000000..80cc773
--- /dev/null
+++ b/openlane/user_proj_example/config.json
@@ -0,0 +1,39 @@
+{
+ "DESIGN_NAME": "user_proj_example",
+ "VERILOG_FILES": "::env(CARAVEL_ROOT)/verilog/rtl/defines.v \\\n\t$script_dir/../../verilog/rtl/user_proj_example.v",
+
+ "CLOCK_PERIOD": 10,
+ "CLOCK_PORT": "wb_clk_i",
+ "CLOCK_NET": "counter.clk",
+ "FP_SIZING": "absolute",
+ "DIE_AREA": "0 0 900 600",
+ "FP_PIN_ORDER_CFG": "pin_order.cfg",
+ "PL_BASIC_PLACEMENT": 0,
+ "PL_TARGET_DENSITY": 0.55,
+ "RT_MAX_LAYER": "{met4}",
+ "pdk::sky130*": {
+ "FP_CORE_UTIL": 45,
+ "scl::sky130_fd_sc_hd": {
+ "CLOCK_PERIOD": 10
+ },
+ "scl::sky130_fd_sc_hdll": {
+ "CLOCK_PERIOD": 10
+ },
+ "scl::sky130_fd_sc_hs": {
+ "CLOCK_PERIOD": 8
+ },
+ "scl::sky130_fd_sc_ls": {
+ "CLOCK_PERIOD": 10,
+ "SYNTH_MAX_FANOUT": 5
+ },
+ "scl::sky130_fd_sc_ms": {
+ "CLOCK_PERIOD": 10
+ }
+ },
+ "pdk::gf180mcuC": {
+ "CLOCK_PERIOD": 24.0,
+ "FP_CORE_UTIL": 40,
+ "SYNTH_MAX_FANOUT": 4,
+ "PL_TARGET_DENSITY": 0.45
+ }
+}
\ No newline at end of file
