)]}' { "commit": "a1996978920cad104541477ea15a355743bb68b5", "tree": "fd6649fc1dd52f2d72b9adbd25f2cad97abfae86", "parents": [ "7fecf2d77ea90315b4a1d5b0fa38fa6140eddcde" ], "author": { "name": "Kareem Farid", "email": "karimmhany@gmail.com", "time": "Mon Nov 14 20:19:36 2022 +0200" }, "committer": { "name": "Kareem Farid", "email": "karimmhany@gmail.com", "time": "Mon Nov 14 20:19:36 2022 +0200" }, "message": "feat: add extract-parasitics target that\n\nfetches the macros and extract parasitics for them\n~ suppress makefile shell commands\n\ndiff --git a/Makefile b/Makefile\nindex 42b616a..4e2176a 100644\n--- a/Makefile\n+++ b/Makefile\n@@ -262,36 +262,50 @@ help:\n\n export CUP_ROOT\u003d$(shell pwd)\n-export TIMING_ROOT\u003d$(shell pwd)/deps/timing-scripts\n-export CURRENT_PROJECT\u003d$(CUP_ROOT)\n+export TIMING_ROOT?\u003d$(shell pwd)/deps/timing-scripts\n+export PROJECT_ROOT\u003d$(CUP_ROOT)\n timing-scripts-repo\u003dgit@github.com:efabless/timing-scripts.git\n\n $(TIMING_ROOT):\n-\tgit clone $(timing-scripts-repo) $(TIMING_ROOT)\n+\t@git clone $(timing-scripts-repo) $(TIMING_ROOT)\n\n .PHONY: setup-timing-scripts\n setup-timing-scripts: $(TIMING_ROOT)\n-\t( cd $(TIMING_ROOT) \u0026\u0026 git pull )\n+\t@( cd $(TIMING_ROOT) \u0026\u0026 git pull )\n \t#( cd $(TIMING_ROOT) \u0026\u0026 git fetch \u0026\u0026 git checkout $(MPW_TAG); )\n-\tpython3 -m venv ./venv\n-\t. ./venv/bin/activate \u0026\u0026 \\\n-\tpython3 -m pip install --upgrade pip \u0026\u0026 \\\n-\tpython3 -m pip install -r $(TIMING_ROOT)/requirements.txt \u0026\u0026 \\\n-\tdeactivate\n+\t@python3 -m venv ./venv\n+\t\t. ./venv/bin/activate \u0026\u0026 \\\n+\t\tpython3 -m pip install --upgrade pip \u0026\u0026 \\\n+\t\tpython3 -m pip install -r $(TIMING_ROOT)/requirements.txt \u0026\u0026 \\\n+\t\tdeactivate\n\n ./verilog/gl/user_project_wrapper.v:\n \t$(error you don\u0027t have $@)\n\n-./env/spef-mapping.tcl: $(setup-timing-scripts) ./verilog/gl/user_project_wrapper.v\n-\t. ./venv/bin/activate \u0026\u0026 \\\n-\tpython3 $(TIMING_ROOT)/scripts/generate_spef_mapping.py \\\n-\t\t-i ./verilog/gl/user_project_wrapper.v \\\n-\t\t-o ./env/spef-mapping.tcl \\\n-\t\t--pdk $(PDK) \\\n-\t\t--pdk-root $(PDK_ROOT) \\\n-\t\t--project-root \u0027$$::env(CUP_ROOT)\u0027 \u0026\u0026 \\\n+./env/spef-mapping.tcl: $(TIMING_ROOT) ./verilog/gl/user_project_wrapper.v\n+\t@. ./venv/bin/activate \u0026\u0026 \\\n+\t\tpython3 $(TIMING_ROOT)/scripts/generate_spef_mapping.py \\\n+\t\t\t-i ./verilog/gl/user_project_wrapper.v \\\n+\t\t\t-o ./env/spef-mapping.tcl \\\n+\t\t\t--pdk-path $(PDK_ROOT)/$(PDK) \\\n+\t\t\t--project-root \"$(CUP_ROOT)\" \u0026\u0026 \\\n+\t\tdeactivate\n+\n+.PHONY: extract-parasitics\n+extract-parasitics: $(TIMING_ROOT) ./verilog/gl/user_project_wrapper.v\n+\t@. ./venv/bin/activate \u0026\u0026 \\\n+\tpython3 $(TIMING_ROOT)/scripts/get_macros.py \\\n+\t-i ./verilog/gl/user_project_wrapper.v \\\n+\t-o ./tmp-macros-list \\\n+\t--pdk-path $(PDK_ROOT)/$(PDK) \u0026\u0026 \\\n \tdeactivate\n+\t@cat ./tmp-macros-list | cut -d \" \" -f2 \\\n+\t\t| xargs -I % bash -c \"$(MAKE) -C $(TIMING_ROOT) \\\n+\t\t\t-f $(TIMING_ROOT)/timing.mk rcx-% || echo \u0027Cannot extract %. Probably no def for this macro\u0027\"\n+\n\n .PHONY: caravel-sta\n caravel-sta: ./env/spef-mapping.tcl\n-\t$(MAKE) -C $(TIMING_ROOT) -f $(TIMING_ROOT)/timing.mk caravel-timing-typ-nom\n+\t@$(MAKE) -C $(TIMING_ROOT) -f $(TIMING_ROOT)/timing.mk caravel-timing-nom\n+\t@$(MAKE) -C $(TIMING_ROOT) -f $(TIMING_ROOT)/timing.mk caravel-timing-fast\n+\t@$(MAKE) -C $(TIMING_ROOT) -f $(TIMING_ROOT)/timing.mk caravel-timing-slow\n", "tree_diff": [ { "type": "modify", "old_id": "42b616ad703ec291ab0d6e53079a3e3401b4eb8c", "old_mode": 33188, "old_path": "Makefile", "new_id": "4e2176aa3088e9b7bef4bc47140d84c326713486", "new_mode": 33188, "new_path": "Makefile" } ] }