diff --git a/Makefile b/Makefile
index b8cb5c7..02b4bd2 100644
--- a/Makefile
+++ b/Makefile
@@ -24,7 +24,7 @@
 CARAVEL_LITE?=1
 
 # PDK switch varient
-export PDK?=sky130B
+export PDK?=sky130A
 #export PDK?=gf180mcuC
 export PDKPATH?=$(PDK_ROOT)/$(PDK)
 
@@ -98,7 +98,7 @@
 	docker pull efabless/dv:latest
 
 .PHONY: setup
-setup: install check-env install_mcw openlane pdk-with-volare
+setup: install check-env install_mcw openlane pdk-with-volare setup-timing-scripts
 
 # Openlane
 blocks=$(shell cd openlane && find * -maxdepth 0 -type d)
@@ -261,3 +261,64 @@
 	@$(MAKE) -pRrq -f $(lastword $(MAKEFILE_LIST)) : 2>/dev/null | awk -v RS= -F: '/^# File/,/^# Finished Make data base/ {if ($$1 !~ "^[#.]") {print $$1}}' | sort | egrep -v -e '^[^[:alnum:]]' -e '^$@$$'
 
 
+export CUP_ROOT=$(shell pwd)
+export TIMING_ROOT?=$(shell pwd)/deps/timing-scripts
+export PROJECT_ROOT=$(CUP_ROOT)
+timing-scripts-repo=git@github.com:efabless/timing-scripts.git
+
+$(TIMING_ROOT):
+	@mkdir -p $(CUP_ROOT)/deps
+	@git clone $(timing-scripts-repo) $(TIMING_ROOT)
+
+.PHONY: setup-timing-scripts
+setup-timing-scripts: $(TIMING_ROOT)
+	@( cd $(TIMING_ROOT) && git pull )
+	@#( cd $(TIMING_ROOT) && git fetch && git checkout $(MPW_TAG); )
+	@python3 -m venv ./venv 
+		. ./venv/bin/activate && \
+		python3 -m pip install --upgrade pip && \
+		python3 -m pip install -r $(TIMING_ROOT)/requirements.txt && \
+		deactivate
+
+./verilog/gl/user_project_wrapper.v:
+	$(error you don't have $@)
+
+./env/spef-mapping.tcl: 
+	@echo "run the following:"
+	@echo "make extract-parasitics"
+	@echo "make create-spef-mapping"
+	exit 1
+
+.PHONY: create-spef-mapping
+create-spef-mapping: ./verilog/gl/user_project_wrapper.v
+	@. ./venv/bin/activate && \
+		python3 $(TIMING_ROOT)/scripts/generate_spef_mapping.py \
+			-i ./verilog/gl/user_project_wrapper.v \
+			-o ./env/spef-mapping.tcl \
+			--pdk-path $(PDK_ROOT)/$(PDK) \
+			--macro-parent mprj \
+			--project-root "$(CUP_ROOT)" && \
+		deactivate
+
+.PHONY: extract-parasitics
+extract-parasitics: ./verilog/gl/user_project_wrapper.v
+	@. ./venv/bin/activate && \
+		python3 $(TIMING_ROOT)/scripts/get_macros.py \
+		-i ./verilog/gl/user_project_wrapper.v \
+		-o ./tmp-macros-list \
+		--project-root "$(CUP_ROOT)" \
+		--pdk-path $(PDK_ROOT)/$(PDK) && \
+		deactivate
+		@cat ./tmp-macros-list | cut -d " " -f2 \
+			| xargs -I % bash -c "$(MAKE) -C $(TIMING_ROOT) \
+				-f $(TIMING_ROOT)/timing.mk rcx-% || echo 'Cannot extract %. Probably no def for this macro'"
+	@$(MAKE) -C $(TIMING_ROOT) -f $(TIMING_ROOT)/timing.mk rcx-user_project_wrapper
+	@cat ./tmp-macros-list
+	@rm ./tmp-macros-list
+	
+.PHONY: caravel-sta
+caravel-sta: ./env/spef-mapping.tcl
+	@$(MAKE) -C $(TIMING_ROOT) -f $(TIMING_ROOT)/timing.mk caravel-timing-typ
+	@$(MAKE) -C $(TIMING_ROOT) -f $(TIMING_ROOT)/timing.mk caravel-timing-fast
+	@$(MAKE) -C $(TIMING_ROOT) -f $(TIMING_ROOT)/timing.mk caravel-timing-slow
+	@echo "You can find results for all corners in $(CUP_ROOT)/signoff/caravel/openlane-signoff/timing/"
diff --git a/docs/source/index.rst b/docs/source/index.rst
index 332dad6..36127a7 100644
--- a/docs/source/index.rst
+++ b/docs/source/index.rst
@@ -72,9 +72,9 @@
    *   Follow https://github.com/efabless/caravel_user_project/generate to create a new repository.
    *   Clone the reposity using the following command:
    
-   .. code:: bash
-    
-	git clone <your github repo URL>
+       .. code:: bash
+        
+    	git clone <your github repo URL>
 	
 #.  To setup your local environment run:
 
@@ -100,12 +100,12 @@
 
         make setup
 
-*   This command will setup your environment by installing the following:
+*   This command will setup your environment by installing the following
     
-        - caravel_lite (a lite version of caravel)
-        - management core for simulation
-        - openlane to harden your design 
-        - pdk
+    - caravel_lite (a lite version of caravel)
+    - management core for simulation
+    - openlane to harden your design 
+    - pdk
 
 	
 #.  Now you can start hardening your design
@@ -114,12 +114,12 @@
         - RTL verilog model for your design for OpenLane to harden
         - A subdirectory for each macro in your project under ``openlane/`` directory, each subdirectory should include openlane configuration files for the macro
 
-	.. code:: bash
+        .. code:: bash
 
-		make <module_name>	
-	..
+           make <module_name>	
+        ..
 
-		For an example of hardening a project please refer to :ref:`Hardening the User Project using OpenLane`.
+		For an example of hardening a project please refer to `Hardening the User Project using OpenLane`_. .
 	
 #.  Integrate modules into the user_project_wrapper
 
@@ -151,6 +151,28 @@
 
             # for example
             make verify-io_ports-rtl
+
+#.  Run opensta on your design
+
+    *   Extract spefs for ``user_project_wrapper`` and macros inside it:
+
+        .. code:: bash
+
+            make extract-parasitics
+
+    *   Create spef mapping file that maps instance names to spef files:
+
+        .. code:: bash
+
+            make create-spef-mapping
+
+    *   Run opensta:
+
+        .. code:: bash
+
+            make caravel-sta
+
+        **NOTE:** To update timing scripts run ``make setup-timing-scripts``
 	
 #.  Run the precheck locally 
 
@@ -165,6 +187,7 @@
 Caravel Integration
 ===================
 
+----------------
 Repo Integration
 ----------------
 
@@ -189,6 +212,7 @@
 
 The symbolic links are automatically set when you run ``make install``.
 
+-------------------
 Verilog Integration
 -------------------
 
@@ -224,6 +248,7 @@
    </p>
 
 
+-------------------
 Layout Integration
 -------------------
 
@@ -323,6 +348,7 @@
 Hardening the User Project using OpenLane
 ==========================================
 
+---------------------
 OpenLane Installation 
 ---------------------
 
@@ -342,6 +368,7 @@
 to
 `README <https://github.com/The-OpenROAD-Project/OpenLane#setting-up-openlane>`__.
 
+-----------------
 Hardening Options 
 -----------------
 
@@ -376,7 +403,7 @@
 
 For more details on hardening macros using openlane, refer to `README <https://github.com/The-OpenROAD-Project/OpenLane/blob/master/docs/source/hardening_macros.md>`__.
 
-
+-----------------
 Running OpenLane 
 -----------------
 
diff --git a/docs/source/quickstart.rst b/docs/source/quickstart.rst
index f8a9b73..d0770bd 100644
--- a/docs/source/quickstart.rst
+++ b/docs/source/quickstart.rst
@@ -117,6 +117,28 @@
 
             # for example
             make verify-io_ports-rtl
+
+#.  Run opensta on your design
+
+    *   Extract spefs for ``user_project_wrapper`` and macros inside it:
+
+        .. code:: bash
+
+            make extract-parasitics
+
+    *   Create spef mapping file that maps instance names to spef files:
+
+        .. code:: bash
+
+            make create-spef-mapping
+
+    *   Run opensta:
+
+        .. code:: bash
+
+            make caravel-sta
+
+	
 	
 #.  Run the precheck locally