fix: hardening configuration
hardens successfully, just with a single inverter for now. Using SkullFET revision 36d391f2741e4f666a19a1a3bb4d9ac9e1b3c146
diff --git a/gds/skullfet_inverter.gds b/gds/skullfet_inverter.gds
index 7e953d7..3eb9154 100755
--- a/gds/skullfet_inverter.gds
+++ b/gds/skullfet_inverter.gds
Binary files differ
diff --git a/lef/skullfet_inverter.lef b/lef/skullfet_inverter.lef
index db823fc..869efae 100755
--- a/lef/skullfet_inverter.lef
+++ b/lef/skullfet_inverter.lef
@@ -5,9 +5,9 @@
MACRO skullfet_inverter
CLASS BLOCK ;
FOREIGN skullfet_inverter ;
- ORIGIN 0.000 0.000 ;
- SIZE 53.500 BY 72.000 ;
- PIN VSS
+ ORIGIN 4.000 0.000 ;
+ SIZE 61.000 BY 72.000 ;
+ PIN vss
DIRECTION INOUT ;
USE GROUND ;
SHAPE ABUTMENT ;
@@ -15,9 +15,22 @@
LAYER Metal1 ;
RECT 0.000 70.000 53.500 72.000 ;
RECT 12.500 62.000 14.500 70.000 ;
+ LAYER Via1 ;
+ RECT 0.500 70.500 1.500 71.500 ;
+ LAYER Metal2 ;
+ RECT 0.000 70.000 2.000 72.000 ;
+ LAYER Via2 ;
+ RECT 0.500 70.500 1.500 71.500 ;
+ LAYER Metal3 ;
+ RECT 0.000 70.000 2.000 72.000 ;
+ LAYER Via3 ;
+ RECT 0.500 70.500 1.500 71.500 ;
+ LAYER Metal4 ;
+ RECT 0.000 70.000 57.000 72.000 ;
+ RECT 55.000 0.000 57.000 70.000 ;
END
- END VSS
- PIN VDD
+ END vss
+ PIN vdd
DIRECTION INOUT ;
USE POWER ;
SHAPE ABUTMENT ;
@@ -25,8 +38,21 @@
LAYER Metal1 ;
RECT 13.000 2.000 15.200 12.000 ;
RECT 0.000 0.000 53.500 2.000 ;
+ LAYER Via1 ;
+ RECT 0.500 0.500 1.500 1.500 ;
+ LAYER Metal2 ;
+ RECT 0.000 0.000 2.000 2.000 ;
+ LAYER Via2 ;
+ RECT 0.500 0.500 1.500 1.500 ;
+ LAYER Metal3 ;
+ RECT 0.000 0.000 2.000 2.000 ;
+ LAYER Via3 ;
+ RECT 0.500 0.500 1.500 1.500 ;
+ LAYER Metal4 ;
+ RECT -4.000 2.000 -2.000 72.000 ;
+ RECT -4.000 0.000 53.500 2.000 ;
END
- END VDD
+ END vdd
PIN Y
DIRECTION OUTPUT ;
USE SIGNAL ;
diff --git a/openlane/user_project_wrapper/config.tcl b/openlane/user_project_wrapper/config.tcl
index fda25e1..addbc85 100644
--- a/openlane/user_project_wrapper/config.tcl
+++ b/openlane/user_project_wrapper/config.tcl
@@ -41,7 +41,7 @@
## Internal Macros
### Macro PDN Connections
set ::env(FP_PDN_MACRO_HOOKS) "\
- mprj vdd vss vdd vss"
+ inv1 vdd vss vdd vss"
### Macro Placement
set ::env(MACRO_PLACEMENT_CFG) $::env(DESIGN_DIR)/macro.cfg
@@ -62,8 +62,8 @@
set ::env(FP_PDN_CHECK_NODES) 0
# The following is because there are no std cells in the example wrapper project.
-#set ::env(SYNTH_ELABORATE_ONLY) 1
-#set ::env(PL_RANDOM_GLB_PLACEMENT) 1
+set ::env(SYNTH_ELABORATE_ONLY) 1
+set ::env(PL_RANDOM_GLB_PLACEMENT) 1
set ::env(PL_RESIZER_DESIGN_OPTIMIZATIONS) 0
set ::env(PL_RESIZER_TIMING_OPTIMIZATIONS) 0
diff --git a/openlane/user_project_wrapper/macro.cfg b/openlane/user_project_wrapper/macro.cfg
index 568caba..dd4f574 100644
--- a/openlane/user_project_wrapper/macro.cfg
+++ b/openlane/user_project_wrapper/macro.cfg
@@ -1 +1 @@
-inv1 1125 1690 N
+inv1 1125 1720 N
diff --git a/verilog/rtl/skullfet.v b/verilog/rtl/skullfet.v
index a4dd35e..12b684a 100644
--- a/verilog/rtl/skullfet.v
+++ b/verilog/rtl/skullfet.v
@@ -1,8 +1,8 @@
(* blackbox *)
module skullfet_inverter (
`ifdef USE_POWER_PINS
- input VSS,
- input VDD,
+ input vss,
+ input vdd,
`endif // USE_POWER_PINS
input A,
output Y
@@ -12,8 +12,8 @@
(* blackbox *)
module skullfet_nand (
`ifdef USE_POWER_PINS
- input VSS,
- input VDD,
+ input vss,
+ input vdd,
`endif // USE_POWER_PINS
input A,
input B,
diff --git a/verilog/rtl/user_project_wrapper.v b/verilog/rtl/user_project_wrapper.v
index f213bf7..2852adf 100644
--- a/verilog/rtl/user_project_wrapper.v
+++ b/verilog/rtl/user_project_wrapper.v
@@ -72,8 +72,8 @@
skullfet_inverter inv1 (
`ifdef USE_POWER_PINS
- .VDD(vdd), // User area 1 5V power
- .VSS(vss), // User area 1 digital ground
+ .vdd(vdd), // User area 1 5V power
+ .vss(vss), // User area 1 digital ground
`endif
.A(io_in[8]),
