blob: 667c79533cd1870b2b1b9a15d9d9aa12056470bd [file] [log] [blame]
Project Chip ID is: 402681723
Setting Project Chip ID to: 18006f7b
Step 1: Modify Layout of the user_id_programming subcell
Done!
Step 2: Add user project ID parameter to source verilog.
Done!
Step 3: Add user project ID parameter to gate-level verilog.
Done!
Step 4: Add user project ID text to top level layout.
Done!