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foss-eda-tools / third_party / shuttle / gf180mcu / mpw-000 / slot-009 / 5e94b04ea74b01284668cef9afcde4611d6b3b6c / . / mpw_precheck / outputs / reports / klayout_feol_check.xml
blob: 46e9d888c28a77bd967a59c165ac5048e4aff7a1 [file] [log] [blame]
<?xml version="1.0" encoding="utf-8"?>
<report-database>
<description>DRC Run Report at</description>
<original-file/>
<generator>drc: script='/opt/checks/tech-files/gf180mcuC_mr.drc'</generator>
<top-cell>user_project_wrapper</top-cell>
<tags>
</tags>
<categories>
<category>
<name>DN.1</name>
<description>DN.1 : Min. DNWELL Width : 1.7µm</description>
<categories>
</categories>
</category>
<category>
<name>DN.2a</name>
<description>DN.2a : Min. DNWELL Space (Equi-potential), Merge if the space is less than : 2.5µm</description>
<categories>
</categories>
</category>
<category>
<name>DN.2b</name>
<description>DN.2b : Min. DNWELL Space (Different potential) : 5.42µm</description>
<categories>
</categories>
</category>
<category>
<name>DN.3</name>
<description>DN.3 : Each DNWELL shall be directly surrounded by PCOMP guard ring tied to the P-substrate potential.</description>
<categories>
</categories>
</category>
<category>
<name>LPW.1_3.3V</name>
<description>LPW.1_3.3V : Min. LVPWELL Width. : 0.6µm</description>
<categories>
</categories>
</category>
<category>
<name>LPW.1_5V</name>
<description>LPW.1_5V : Min. LVPWELL Width. : 0.74µm</description>
<categories>
</categories>
</category>
<category>
<name>LPW.2a_3.3V</name>
<description>LPW.2a_3.3V : Min. LVPWELL to LVWELL Space (Inside DNWELL) [Different potential]. : 1.4µm</description>
<categories>
</categories>
</category>
<category>
<name>LPW.2a_5V</name>
<description>LPW.2a_5V : Min. LVPWELL to LVPWELL Space (Inside DNWELL) [Different potential]. : 1.7µm</description>
<categories>
</categories>
</category>
<category>
<name>LPW.2b_3.3V</name>
<description>LPW.2b_3.3V : Min. LVPWELL to LVPWELL Space [Equi potential]. : 0.86µm</description>
<categories>
</categories>
</category>
<category>
<name>LPW.2b_5V</name>
<description>LPW.2b_5V : Min. LVPWELL to LVPWELL Space [Equi potential]. : 0.86µm</description>
<categories>
</categories>
</category>
<category>
<name>LPW.3_3.3V</name>
<description>LPW.3_3.3V : Min. DNWELL enclose LVPWELL. : 2.5µm</description>
<categories>
</categories>
</category>
<category>
<name>LPW.3_5V</name>
<description>LPW.3_5V : Min. DNWELL enclose LVPWELL. : 2.5µm</description>
<categories>
</categories>
</category>
<category>
<name>LPW.5_3.3V</name>
<description>LPW.5_3.3V : LVPWELL resistors must be enclosed by DNWELL.</description>
<categories>
</categories>
</category>
<category>
<name>LPW.5_5V</name>
<description>LPW.5_5V : LVPWELL resistors must be enclosed by DNWELL.</description>
<categories>
</categories>
</category>
<category>
<name>LPW.11</name>
<description>LPW.11 : Min. (LVPWELL outside DNWELL) space to DNWELL. : 1.5µm</description>
<categories>
</categories>
</category>
<category>
<name>LPW.12</name>
<description>LPW.12 : LVPWELL cannot overlap with Nwell.</description>
<categories>
</categories>
</category>
<category>
<name>NW.1a_3.3V</name>
<description>NW.1a_3.3V : Min. Nwell Width (This is only for litho purpose on the generated area). : 0.86µm</description>
<categories>
</categories>
</category>
<category>
<name>NW.1a_5V</name>
<description>NW.1a_5V : Min. Nwell Width (This is only for litho purpose on the generated area). : 0.86µm</description>
<categories>
</categories>
</category>
<category>
<name>NW.1b_3.3V</name>
<description>NW.1b_3.3V : Min. Nwell Width as a resistor (Outside DNWELL only). : 2µm</description>
<categories>
</categories>
</category>
<category>
<name>NW.1b_5V</name>
<description>NW.1b_5V : Min. Nwell Width as a resistor (Outside DNWELL only). : 2µm</description>
<categories>
</categories>
</category>
<category>
<name>NW.2a_3.3V</name>
<description>NW.2a_3.3V : Min. Nwell Space (Outside DNWELL) [Equi-potential], Merge if the space is less than. : 0.6µm</description>
<categories>
</categories>
</category>
<category>
<name>NW.2a_5V</name>
<description>NW.2a_5V : Min. Nwell Space (Outside DNWELL) [Equi-potential], Merge if the space is less than. : 0.74µm</description>
<categories>
</categories>
</category>
<category>
<name>NW.2b_3.3V</name>
<description>NW.2b_3.3V : Min. Nwell Space (Outside DNWELL) [Different potential]. : 1.4µm</description>
<categories>
</categories>
</category>
<category>
<name>NW.2b_5V</name>
<description>NW.2b_5V : Min. Nwell Space (Outside DNWELL) [Different potential]. : 1.7µm</description>
<categories>
</categories>
</category>
<category>
<name>NW.3_3.3V</name>
<description>NW.3_3.3V : Min. Nwell to DNWELL space. : 3.1µm</description>
<categories>
</categories>
</category>
<category>
<name>NW.3_5V</name>
<description>NW.3_5V : Min. Nwell to DNWELL space. : 3.1µm</description>
<categories>
</categories>
</category>
<category>
<name>NW.4_3.3V</name>
<description>NW.4_3.3V : Min. Nwell to LVPWELL space.</description>
<categories>
</categories>
</category>
<category>
<name>NW.4_5V</name>
<description>NW.4_5V : Min. Nwell to LVPWELL space.</description>
<categories>
</categories>
</category>
<category>
<name>NW.5_3.3V</name>
<description>NW.5_3.3V : Min. DNWELL enclose Nwell. : 0.5µm</description>
<categories>
</categories>
</category>
<category>
<name>NW.5_5V</name>
<description>NW.5_5V : Min. DNWELL enclose Nwell. : 0.5µm</description>
<categories>
</categories>
</category>
<category>
<name>NW.6</name>
<description>NW.6 : Nwell resistors can only exist outside DNWELL.</description>
<categories>
</categories>
</category>
<category>
<name>DF.1a_3.3V</name>
<description>DF.1a_3.3V : Min. COMP Width. : 0.22µm</description>
<categories>
</categories>
</category>
<category>
<name>DF.1a_5V</name>
<description>DF.1a_5V : Min. COMP Width. : 0.3µm</description>
<categories>
</categories>
</category>
<category>
<name>DF.1c_3.3V</name>
<description>DF.1c_3.3V : Min. COMP Width for MOSCAP. : 1µm</description>
<categories>
</categories>
</category>
<category>
<name>DF.1c_5V</name>
<description>DF.1c_5V : Min. COMP Width for MOSCAP. : 1µm</description>
<categories>
</categories>
</category>
<category>
<name>DF.2a_3.3V</name>
<description>DF.2a_3.3V : Min Channel Width. : nil,0.22µm</description>
<categories>
</categories>
</category>
<category>
<name>DF.2a_5V</name>
<description>DF.2a_5V : Min Channel Width. : nil,0.3µm</description>
<categories>
</categories>
</category>
<category>
<name>DF.2b_3.3V</name>
<description>DF.2b_3.3V : Max. COMP width for all cases except those used for capacitors, marked by ‘MOS_CAP_MK’ layer.</description>
<categories>
</categories>
</category>
<category>
<name>DF.2b_5V</name>
<description>DF.2b_5V : Max. COMP width for all cases except those used for capacitors, marked by ‘MOS_CAP_MK’ layer.</description>
<categories>
</categories>
</category>
<category>
<name>DF.3a_3.3V</name>
<description>DF.3a_3.3V : Min. COMP Space P-substrate tap (PCOMP outside NWELL and DNWELL) can be butted for different voltage devices as the potential is same. : 0.28µm</description>
<categories>
</categories>
</category>
<category>
<name>DF.3a_5V</name>
<description>DF.3a_5V : Min. COMP Space P-substrate tap (PCOMP outside NWELL and DNWELL) can be butted for different voltage devices as the potential is same. : 0.36µm</description>
<categories>
</categories>
</category>
<category>
<name>DF.3b_3.3V</name>
<description>DF.3b_3.3V : Min./Max. NCOMP Space to PCOMP in the same well for butted COMP (MOSCAP butting is not allowed).</description>
<categories>
</categories>
</category>
<category>
<name>DF.3b_5V</name>
<description>DF.3b_5V : Min./Max. NCOMP Space to PCOMP in the same well for butted COMP(MOSCAP butting is not allowed).</description>
<categories>
</categories>
</category>
<category>
<name>DF.3c_3.3V</name>
<description>DF.3c_3.3V : Min. COMP Space in BJT area (area marked by DRC_BJT layer). : 0.32µm</description>
<categories>
</categories>
</category>
<category>
<name>DF.3c_5V</name>
<description>DF.3c_5V : Min. COMP Space in BJT area (area marked by DRC_BJT layer) hasn’t been assessed.</description>
<categories>
</categories>
</category>
<category>
<name>DF.4a_3.3V</name>
<description>DF.4a_3.3V : Min. (LVPWELL Space to NCOMP well tap) inside DNWELL. : 0.12µm</description>
<categories>
</categories>
</category>
<category>
<name>DF.4a_5V</name>
<description>DF.4a_5V : Min. (LVPWELL Space to NCOMP well tap) inside DNWELL. : 0.16µm</description>
<categories>
</categories>
</category>
<category>
<name>DF.4b_3.3V</name>
<description>DF.4b_3.3V : Min. DNWELL overlap of NCOMP well tap. : 0.62µm</description>
<categories>
</categories>
</category>
<category>
<name>DF.4b_5V</name>
<description>DF.4b_5V : Min. DNWELL overlap of NCOMP well tap. : 0.66µm</description>
<categories>
</categories>
</category>
<category>
<name>DF.4c_3.3V</name>
<description>DF.4c_3.3V : Min. (Nwell overlap of PCOMP) outside DNWELL. : 0.43µm</description>
<categories>
</categories>
</category>
<category>
<name>DF.4c_5V</name>
<description>DF.4c_5V : Min. (Nwell overlap of PCOMP) outside DNWELL. : 0.6µm</description>
<categories>
</categories>
</category>
<category>
<name>DF.4d_3.3V</name>
<description>DF.4d_3.3V : Min. (Nwell overlap of NCOMP) outside DNWELL. : 0.12µm</description>
<categories>
</categories>
</category>
<category>
<name>DF.4d_5V</name>
<description>DF.4d_5V : Min. (Nwell overlap of NCOMP) outside DNWELL. : 0.16µm</description>
<categories>
</categories>
</category>
<category>
<name>DF.4e_3.3V</name>
<description>DF.4e_3.3V : Min. DNWELL overlap of PCOMP. : 0.93µm</description>
<categories>
</categories>
</category>
<category>
<name>DF.4e_5V</name>
<description>DF.4e_5V : Min. DNWELL overlap of PCOMP. : 1.1µm</description>
<categories>
</categories>
</category>
<category>
<name>DF.5_3.3V</name>
<description>DF.5_3.3V : Min. (LVPWELL overlap of PCOMP well tap) inside DNWELL. : 0.12µm</description>
<categories>
</categories>
</category>
<category>
<name>DF.5_5V</name>
<description>DF.5_5V : Min. (LVPWELL overlap of PCOMP well tap) inside DNWELL. : 0.16µm</description>
<categories>
</categories>
</category>
<category>
<name>DF.6_3.3V</name>
<description>DF.6_3.3V : Min. COMP extend beyond gate (it also means source/drain overhang). : 0.24µm</description>
<categories>
</categories>
</category>
<category>
<name>DF.6_5V</name>
<description>DF.6_5V : Min. COMP extend beyond gate (it also means source/drain overhang). : 0.4µm</description>
<categories>
</categories>
</category>
<category>
<name>DF.7_3.3V</name>
<description>DF.7_3.3V : Min. (LVPWELL Spacer to PCOMP) inside DNWELL. : 0.43µm</description>
<categories>
</categories>
</category>
<category>
<name>DF.7_5V</name>
<description>DF.7_5V : Min. (LVPWELL Spacer to PCOMP) inside DNWELL. : 0.6µm</description>
<categories>
</categories>
</category>
<category>
<name>DF.8_3.3V</name>
<description>DF.8_3.3V : Min. (LVPWELL overlap of NCOMP) Inside DNWELL. : 0.43µm</description>
<categories>
</categories>
</category>
<category>
<name>DF.8_5V</name>
<description>DF.8_5V : Min. (LVPWELL overlap of NCOMP) Inside DNWELL. : 0.6µm</description>
<categories>
</categories>
</category>
<category>
<name>DF.9_3.3V</name>
<description>DF.9_3.3V : Min. COMP area (um2). : 0.2025µm²</description>
<categories>
</categories>
</category>
<category>
<name>DF.9_5V</name>
<description>DF.9_5V : Min. COMP area (um2). : 0.2025µm²</description>
<categories>
</categories>
</category>
<category>
<name>DF.10_3.3V</name>
<description>DF.10_3.3V : Min. field area (um2). : 0.26µm²</description>
<categories>
</categories>
</category>
<category>
<name>DF.10_5V</name>
<description>DF.10_5V : Min. field area (um2). : 0.26µm²</description>
<categories>
</categories>
</category>
<category>
<name>DF.11_3.3V</name>
<description>DF.11_3.3V : Min. Length of butting COMP edge. : 0.3µm</description>
<categories>
</categories>
</category>
<category>
<name>DF.11_5V</name>
<description>DF.11_5V : Min. Length of butting COMP edge. : 0.3µm</description>
<categories>
</categories>
</category>
<category>
<name>DF.12_3.3V</name>
<description>DF.12_3.3V : COMP not covered by Nplus or Pplus is forbidden (except those COMP under marking).</description>
<categories>
</categories>
</category>
<category>
<name>DF.12_5V</name>
<description>DF.12_5V : COMP not covered by Nplus or Pplus is forbidden (except those COMP under marking).</description>
<categories>
</categories>
</category>
<category>
<name>DF.13_3.3V</name>
<description>DF.13_3.3V : Max distance of Nwell tap (NCOMP inside Nwell) from (PCOMP inside Nwell).</description>
<categories>
</categories>
</category>
<category>
<name>DF.13_5V</name>
<description>DF.13_5V : Max distance of Nwell tap (NCOMP inside Nwell) from (PCOMP inside Nwell).</description>
<categories>
</categories>
</category>
<category>
<name>DF.14_3.3V</name>
<description>DF.14_3.3V : Max distance of substrate tap (PCOMP outside Nwell) from (NCOMP outside Nwell).</description>
<categories>
</categories>
</category>
<category>
<name>DF.14_5V</name>
<description>DF.14_5V : Max distance of substrate tap (PCOMP outside Nwell) from (NCOMP outside Nwell).</description>
<categories>
</categories>
</category>
<category>
<name>DF.16_3.3V</name>
<description>DF.16_3.3V : Min. space from (Nwell outside DNWELL) to (NCOMP outside Nwell and DNWELL). : 0.43µm</description>
<categories>
</categories>
</category>
<category>
<name>DF.16_5V</name>
<description>DF.16_5V : Min. space from (Nwell outside DNWELL) to (NCOMP outside Nwell and DNWELL). : 0.6µm</description>
<categories>
</categories>
</category>
<category>
<name>DF.17_3.3V</name>
<description>DF.17_3.3V : Min. space from (Nwell Outside DNWELL) to (PCOMP outside Nwell and DNWELL). : 0.12µm</description>
<categories>
</categories>
</category>
<category>
<name>DF.17_5V</name>
<description>DF.17_5V : Min. space from (Nwell Outside DNWELL) to (PCOMP outside Nwell and DNWELL). : 0.16µm</description>
<categories>
</categories>
</category>
<category>
<name>DF.18_3.3V</name>
<description>DF.18_3.3V : Min. DNWELL space to (PCOMP outside Nwell and DNWELL). : 2.5µm</description>
<categories>
</categories>
</category>
<category>
<name>DF.18_5V</name>
<description>DF.18_5V : Min. DNWELL space to (PCOMP outside Nwell and DNWELL). : 2.5µm</description>
<categories>
</categories>
</category>
<category>
<name>DF.19_3.3V</name>
<description>DF.19_3.3V : Min. DNWELL space to (NCOMP outside Nwell and DNWELL). : 3.2µm</description>
<categories>
</categories>
</category>
<category>
<name>DF.19_5V</name>
<description>DF.19_5V : Min. DNWELL space to (NCOMP outside Nwell and DNWELL). : 3.28µm</description>
<categories>
</categories>
</category>
<category>
<name>DV.1</name>
<description>DV.1 : Min. Dualgate enclose DNWELL. : 0.5µm</description>
<categories>
</categories>
</category>
<category>
<name>DV.2</name>
<description>DV.2 : Min. Dualgate Space. Merge if Space is less than this design rule. : 0.44µm</description>
<categories>
</categories>
</category>
<category>
<name>DV.3</name>
<description>DV.3 : Min. Dualgate to COMP space [unrelated]. : 0.24µm</description>
<categories>
</categories>
</category>
<category>
<name>DV.5</name>
<description>DV.5 : Min. Dualgate width. : 0.7µm</description>
<categories>
</categories>
</category>
<category>
<name>DV.6</name>
<description>DV.6 : Min. Dualgate enclose COMP (except substrate tap). : 0.24µm</description>
<categories>
</categories>
</category>
<category>
<name>DV.7</name>
<description>DV.7 : COMP (except substrate tap) can not be partially overlapped by Dualgate.</description>
<categories>
</categories>
</category>
<category>
<name>DV.8</name>
<description>DV.8 : Min Dualgate enclose Poly2. : 0.4µm</description>
<categories>
</categories>
</category>
<category>
<name>DV.9</name>
<description>DV.9 : 3.3V and 5V/6V PMOS cannot be sitting inside same NWELL.</description>
<categories>
</categories>
</category>
<category>
<name>PL.1_3.3V</name>
<description>PL.1_3.3V : Interconnect Width (outside PLFUSE). : 0.18µm</description>
<categories>
</categories>
</category>
<category>
<name>PL.1_5V</name>
<description>PL.1_5V : Interconnect Width (outside PLFUSE). : 0.2µm</description>
<categories>
</categories>
</category>
<category>
<name>PL.1a_3.3V</name>
<description>PL.1a_3.3V : Interconnect Width (inside PLFUSE). : 0.18µm</description>
<categories>
</categories>
</category>
<category>
<name>PL.1a_5V</name>
<description>PL.1a_5V : Interconnect Width (inside PLFUSE). : 0.18µm</description>
<categories>
</categories>
</category>
<category>
<name>PL.2_3.3V</name>
<description>PL.2_3.3V : Gate Width (Channel Length). : 0.28µm</description>
<categories>
</categories>
</category>
<category>
<name>PL.2_5V</name>
<description>PL.2_5V : Gate Width (Channel Length).</description>
<categories>
</categories>
</category>
<category>
<name>PL.3a_3.3V</name>
<description>PL.3a_3.3V : Space on COMP/Field. : 0.24µm</description>
<categories>
</categories>
</category>
<category>
<name>PL.3a_5V</name>
<description>PL.3a_5V : Space on COMP/Field. : 0.24µm</description>
<categories>
</categories>
</category>
<category>
<name>PL.4_3.3V</name>
<description>PL.4_3.3V : Extension beyond COMP to form Poly2 end cap. : 0.22µm</description>
<categories>
</categories>
</category>
<category>
<name>PL.4_5V</name>
<description>PL.4_5V : Extension beyond COMP to form Poly2 end cap. : 0.22µm</description>
<categories>
</categories>
</category>
<category>
<name>PL.5a_3.3V</name>
<description>PL.5a_3.3V : Space from field Poly2 to unrelated COMP Spacer from field Poly2 to Guard-ring. : 0.1µm</description>
<categories>
</categories>
</category>
<category>
<name>PL.5a_5V</name>
<description>PL.5a_5V : Space from field Poly2 to unrelated COMP Spacer from field Poly2 to Guard-ring. : 0.3µm</description>
<categories>
</categories>
</category>
<category>
<name>PL.5b_3.3V</name>
<description>PL.5b_3.3V : Space from field Poly2 to related COMP. : 0.1µm</description>
<categories>
</categories>
</category>
<category>
<name>PL.5b_5V</name>
<description>PL.5b_5V : Space from field Poly2 to related COMP. : 0.3µm</description>
<categories>
</categories>
</category>
<category>
<name>PL.6</name>
<description>PL.6 : 90 degree bends on the COMP are not allowed.</description>
<categories>
</categories>
</category>
<category>
<name>PL.7_3.3V</name>
<description>PL.7_3.3V : 45 degree bent gate width : 0.3µm</description>
<categories>
</categories>
</category>
<category>
<name>PL.7_5V</name>
<description>PL.7_5V : 45 degree bent gate width : 0.7µm</description>
<categories>
</categories>
</category>
<category>
<name>PL.9</name>
<description>PL.9 : Poly2 inter connect connecting 3.3V and 5V areas (area inside and outside Dualgate) are not allowed. They shall be done though metal lines only.</description>
<categories>
</categories>
</category>
<category>
<name>PL.11</name>
<description>PL.11 : V5_Xtor must enclose 5V device.</description>
<categories>
</categories>
</category>
<category>
<name>PL.12</name>
<description>PL.12 : V5_Xtor enclose 5V Comp.</description>
<categories>
</categories>
</category>
<category>
<name>NP.1</name>
<description>NP.1 : min. nplus width : 0.4µm</description>
<categories>
</categories>
</category>
<category>
<name>NP.2</name>
<description>NP.2 : min. nplus spacing : 0.4µm</description>
<categories>
</categories>
</category>
<category>
<name>NP.3a</name>
<description>NP.3a : Space to PCOMP for PCOMP: (1) Inside Nwell (2) Outside LVPWELL but inside DNWELL. : 0.16µm</description>
<categories>
</categories>
</category>
<category>
<name>NP.3bi</name>
<description>NP.3bi : Space to PCOMP: For Inside DNWELL, inside LVPWELL:(i) For PCOMP overlap by LVPWELL &lt; 0.43um. : 0.16µm</description>
<categories>
</categories>
</category>
<category>
<name>NP.3bii</name>
<description>NP.3bii : Space to PCOMP: For Inside DNWELL, inside LVPWELL:(ii) For PCOMP overlap by LVPWELL &gt;= 0.43um. : 0.08µm</description>
<categories>
</categories>
</category>
<category>
<name>NP.3ci</name>
<description>NP.3ci : Space to PCOMP: For Outside DNWELL:(i) For PCOMP space to Nwell &lt; 0.43um. : 0.16µm</description>
<categories>
</categories>
</category>
<category>
<name>NP.3cii</name>
<description>NP.3cii : Space to PCOMP: For Outside DNWELL:(ii) For PCOMP space to Nwell &gt;= 0.43um. : 0.08µm</description>
<categories>
</categories>
</category>
<category>
<name>NP.3d</name>
<description>NP.3d : Min/max space to a butted PCOMP.</description>
<categories>
</categories>
</category>
<category>
<name>NP.3e</name>
<description>NP.3e : Space to related PCOMP edge adjacent to a butting edge.</description>
<categories>
</categories>
</category>
<category>
<name>NP.4a</name>
<description>NP.4a : Space to related P-channel gate at a butting edge parallel to gate. : 0.32µm</description>
<categories>
</categories>
</category>
<category>
<name>NP.4b</name>
<description>NP.4b : Within 0.32um of channel, space to P-channel gate extension perpendicular to the direction of Poly2.</description>
<categories>
</categories>
</category>
<category>
<name>NP.5a</name>
<description>NP.5a : Overlap of N-channel gate. : 0.23µm</description>
<categories>
</categories>
</category>
<category>
<name>NP.5b</name>
<description>NP.5b : Extension beyond COMP for the COMP (1) inside LVPWELL (2) outside Nwell and DNWELL. : 0.16µm</description>
<categories>
</categories>
</category>
<category>
<name>NP.5ci</name>
<description>NP.5ci : Extension beyond COMP: For Inside DNWELL: (i)For Nplus &lt; 0.43um from LVPWELL edge for Nwell or DNWELL tap inside DNWELL. : 0.16µm</description>
<categories>
</categories>
</category>
<category>
<name>NP.5cii</name>
<description>NP.5cii : Extension beyond COMP: For Inside DNWELL: (ii) For Nplus &gt;= 0.43um from LVPWELL edge for Nwell or DNWELL tap inside DNWELL. : 0.02µm</description>
<categories>
</categories>
</category>
<category>
<name>NP.5di</name>
<description>NP.5di : Extension beyond COMP: For Outside DNWELL, inside Nwell: (i) For Nwell overlap of Nplus &lt; 0.43um. : 0.16µm</description>
<categories>
</categories>
</category>
<category>
<name>NP.5dii</name>
<description>NP.5dii : Extension beyond COMP: For Outside DNWELL, inside Nwell: (ii) For Nwell overlap of Nplus &gt;= 0.43um. : 0.02µm</description>
<categories>
</categories>
</category>
<category>
<name>NP.6</name>
<description>NP.6 : Overlap with NCOMP butted to PCOMP. : 0.22µm</description>
<categories>
</categories>
</category>
<category>
<name>NP.7</name>
<description>NP.7 : Space to unrelated unsalicided Poly2. : 0.18µm</description>
<categories>
</categories>
</category>
<category>
<name>NP.8a</name>
<description>NP.8a : Minimum Nplus area (um2). : 0.35µm²</description>
<categories>
</categories>
</category>
<category>
<name>NP.8b</name>
<description>NP.8b : Minimum area enclosed by Nplus (um2). : 0.35µm²</description>
<categories>
</categories>
</category>
<category>
<name>NP.9</name>
<description>NP.9 : Overlap of unsalicided Poly2. : 0.18µm</description>
<categories>
</categories>
</category>
<category>
<name>NP.10</name>
<description>NP.10 : Overlap of unsalicided COMP. : 0.18µm</description>
<categories>
</categories>
</category>
<category>
<name>NP.11</name>
<description>NP.11 : Butting Nplus and PCOMP is forbidden within 0.43um of Nwell edge (for outside DNWELL) and of LVPWELL edge (for inside DNWELL case).</description>
<categories>
</categories>
</category>
<category>
<name>NP.12</name>
<description>NP.12 : Overlap with P-channel poly2 gate extension is forbidden within 0.32um of P-channel gate.</description>
<categories>
</categories>
</category>
<category>
<name>PP.1</name>
<description>PP.1 : min. pplus width : 0.4µm</description>
<categories>
</categories>
</category>
<category>
<name>PP.2</name>
<description>PP.2 : min. pplus spacing : 0.4µm</description>
<categories>
</categories>
</category>
<category>
<name>PP.3a</name>
<description>PP.3a : Space to NCOMP for NCOMP (1) inside LVPWELL (2) outside NWELL and DNWELL. : 0.16µm</description>
<categories>
</categories>
</category>
<category>
<name>PP.3bi</name>
<description>PP.3bi : Space to NCOMP: For Inside DNWELL. (i) NCOMP space to LVPWELL &gt;= 0.43um. : 0.08µm</description>
<categories>
</categories>
</category>
<category>
<name>PP.3bii</name>
<description>PP.3bii : Space to NCOMP: For Inside DNWELL. (ii) NCOMP space to LVPWELL &lt; 0.43um. : 0.16µm</description>
<categories>
</categories>
</category>
<category>
<name>PP.3ci</name>
<description>PP.3ci : Space to NCOMP: For Outside DNWELL, inside Nwell: (i) NWELL Overlap of NCOMP &gt;= 0.43um. : 0.08µm</description>
<categories>
</categories>
</category>
<category>
<name>PP.3cii</name>
<description>PP.3cii : Space to NCOMP: For Outside DNWELL, inside Nwell: (ii) NWELL Overlap of NCOMP 0.43um. : 0.16µm</description>
<categories>
</categories>
</category>
<category>
<name>PP.3d</name>
<description>PP.3d : Min/max space to a butted NCOMP.</description>
<categories>
</categories>
</category>
<category>
<name>PP.3e</name>
<description>PP.3e : Space to NCOMP edge adjacent to a butting edge.</description>
<categories>
</categories>
</category>
<category>
<name>PP.4a</name>
<description>PP.4a : Space related to N-channel gate at a butting edge parallel to gate. : 0.32µm</description>
<categories>
</categories>
</category>
<category>
<name>PP.4b</name>
<description>PP.4b : Within 0.32um of channel, space to N-channel gate extension perpendicular to the direction of Poly2.</description>
<categories>
</categories>
</category>
<category>
<name>PP.5a</name>
<description>PP.5a : Overlap of P-channel gate. : 0.23µm</description>
<categories>
</categories>
</category>
<category>
<name>PP.5b</name>
<description>PP.5b : Extension beyond COMP for COMP (1) Inside NWELL (2) outside LVPWELL but inside DNWELL. : 0.16µm</description>
<categories>
</categories>
</category>
<category>
<name>PP.5ci</name>
<description>PP.5ci : Extension beyond COMP: For Inside DNWELL, inside LVPWELL: (i) For LVPWELL overlap of Pplus &gt;= 0.43um for LVPWELL tap. : 0.02µm</description>
<categories>
</categories>
</category>
<category>
<name>PP.5cii</name>
<description>PP.5cii : Extension beyond COMP: For Inside DNWELL, inside LVPWELL: (ii) For LVPWELL overlap of Pplus &lt; 0.43um for the LVPWELL tap. : 0.16µm</description>
<categories>
</categories>
</category>
<category>
<name>PP.5di</name>
<description>PP.5di : Extension beyond COMP: For Outside DNWELL (i) For Pplus to NWELL space &gt;= 0.43um for Pfield or LVPWELL tap. : 0.02µm</description>
<categories>
</categories>
</category>
<category>
<name>PP.5dii</name>
<description>PP.5dii : Extension beyond COMP: For Outside DNWELL (ii) For Pplus to NWELL space &lt; 0.43um for Pfield or LVPWELL tap. : 0.16µm</description>
<categories>
</categories>
</category>
<category>
<name>PP.6</name>
<description>PP.6 : Overlap with PCOMP butted to NCOMP. : 0.22µm</description>
<categories>
</categories>
</category>
<category>
<name>PP.7</name>
<description>PP.7 : Space to unrelated unsalicided Poly2. : 0.18µm</description>
<categories>
</categories>
</category>
<category>
<name>PP.8a</name>
<description>PP.8a : Minimum Pplus area (um2). : 0.35µm²</description>
<categories>
</categories>
</category>
<category>
<name>PP.8b</name>
<description>PP.8b : Minimum area enclosed by Pplus (um2). : 0.35µm²</description>
<categories>
</categories>
</category>
<category>
<name>PP.9</name>
<description>PP.9 : Overlap of unsalicided Poly2. : 0.18µm</description>
<categories>
</categories>
</category>
<category>
<name>PP.10</name>
<description>PP.10 : Overlap of unsalicided COMP. : 0.18µm</description>
<categories>
</categories>
</category>
<category>
<name>PP.11</name>
<description>PP.11 : Butting Pplus and NCOMP is forbidden within 0.43um of Nwell edge (for outside DNWELL) and of LVPWELL edge (for inside DNWELL case).</description>
<categories>
</categories>
</category>
<category>
<name>PP.12</name>
<description>PP.12 : Overlap with N-channel Poly2 gate extension is forbidden within 0.32um of N-channel gate.</description>
<categories>
</categories>
</category>
<category>
<name>SB.1</name>
<description>SB.1 : min. sab width : 0.42µm</description>
<categories>
</categories>
</category>
<category>
<name>SB.2</name>
<description>SB.2 : min. sab spacing : 0.42µm</description>
<categories>
</categories>
</category>
<category>
<name>SB.3</name>
<description>SB.3 : Space from salicide block to unrelated COMP. : 0.22µm</description>
<categories>
</categories>
</category>
<category>
<name>SB.4</name>
<description>SB.4 : Space from salicide block to contact.</description>
<categories>
</categories>
</category>
<category>
<name>SB.5a</name>
<description>SB.5a : Space from salicide block to unrelated Poly2 on field. : 0.3µm</description>
<categories>
</categories>
</category>
<category>
<name>SB.5b</name>
<description>SB.5b : Space from salicide block to unrelated Poly2 on COMP. : 0.28µm</description>
<categories>
</categories>
</category>
<category>
<name>SB.6</name>
<description>SB.6 : Salicide block extension beyond related COMP. : 0.22µm</description>
<categories>
</categories>
</category>
<category>
<name>SB.7</name>
<description>SB.7 : COMP extension beyond related salicide block. : 0.22µm</description>
<categories>
</categories>
</category>
<category>
<name>SB.8</name>
<description>SB.8 : Non-salicided contacts are forbidden.</description>
<categories>
</categories>
</category>
<category>
<name>SB.9</name>
<description>SB.9 : Salicide block extension beyond unsalicided Poly2. : 0.22µm</description>
<categories>
</categories>
</category>
<category>
<name>SB.10</name>
<description>SB.10 : Poly2 extension beyond related salicide block. : 0.22µm</description>
<categories>
</categories>
</category>
<category>
<name>SB.11</name>
<description>SB.11 : Overlap with COMP. : 0.22µm</description>
<categories>
</categories>
</category>
<category>
<name>SB.12</name>
<description>SB.12 : Overlap with Poly2 outside ESD_MK. : 0.22µm</description>
<categories>
</categories>
</category>
<category>
<name>SB.13</name>
<description>SB.13 : Min. area (um2). : 2µm²</description>
<categories>
</categories>
</category>
<category>
<name>SB.14a</name>
<description>SB.14a : Space from unsalicided Nplus Poly2 to unsalicided Pplus Poly2. (Unsalicided Nplus Poly2 must not fall within a square of 0.56um x 0.56um at unsalicided Pplus Poly2 corners). : 0.56µm</description>
<categories>
</categories>
</category>
<category>
<name>SB.14b</name>
<description>SB.14b : Space from unsalicided Nplus Poly2 to P-channel gate. (Unsalicided Nplus Poly2 must not fall within a square of 0.56um x 0.56um at P-channel gate corners). : 0.56µm</description>
<categories>
</categories>
</category>
<category>
<name>SB.15a</name>
<description>SB.15a : Space from unsalicided Poly2 to unrelated Nplus/Pplus. : 0.18µm</description>
<categories>
</categories>
</category>
<category>
<name>SB.15b</name>
<description>SB.15b : Space from unsalicided Poly2 to unrelated Nplus/Pplus along Poly2 line. : 0.32µm</description>
<categories>
</categories>
</category>
<category>
<name>SB.16</name>
<description>SB.16 : SAB layer cannot exist on 3.3V and 5V/6V CMOS transistors' Poly and COMP area of the core circuit (Excluding the transistors used for ESD purpose). It can only exist on CMOS transistors marked by LVS_IO, OTP_MK, ESD_MK layers.</description>
<categories>
</categories>
</category>
<category>
<name>ESD.1</name>
<description>ESD.1 : Minimum width of an ESD implant area. : 0.6µm</description>
<categories>
</categories>
</category>
<category>
<name>ESD.2</name>
<description>ESD.2 : Minimum space between two ESD implant areas. (Merge if the space is less than 0.6um). : 0.6µm</description>
<categories>
</categories>
</category>
<category>
<name>ESD.3a</name>
<description>ESD.3a : Minimum space to NCOMP. : 0.6µm</description>
<categories>
</categories>
</category>
<category>
<name>ESD.3b</name>
<description>ESD.3b : Min/max space to a butted PCOMP.</description>
<categories>
</categories>
</category>
<category>
<name>ESD.4a</name>
<description>ESD.4a : Extension beyond NCOMP. : 0.24µm</description>
<categories>
</categories>
</category>
<category>
<name>ESD.4b</name>
<description>ESD.4b : Minimum overlap of an ESD implant edge to a COMP. : 0.45µm</description>
<categories>
</categories>
</category>
<category>
<name>ESD.5a</name>
<description>ESD.5a : Minimum ESD area (um2). : 0.49µm²</description>
<categories>
</categories>
</category>
<category>
<name>ESD.5b</name>
<description>ESD.5b : Minimum field area enclosed by ESD implant (um2). : 0.49µm²</description>
<categories>
</categories>
</category>
<category>
<name>ESD.6</name>
<description>ESD.6 : Extension perpendicular to Poly2 gate. : 0.45µm</description>
<categories>
</categories>
</category>
<category>
<name>ESD.7</name>
<description>ESD.7 : No ESD implant inside PCOMP.</description>
<categories>
</categories>
</category>
<category>
<name>ESD.8</name>
<description>ESD.8 : Minimum space to Nplus/Pplus. : 0.3µm</description>
<categories>
</categories>
</category>
<category>
<name>ESD.pl</name>
<description>ESD.pl : Minimum gate length of 5V/6V gate NMOS. : 0.8µm</description>
<categories>
</categories>
</category>
<category>
<name>ESD.9</name>
<description>ESD.9 : ESD implant layer must be overlapped by Dualgate layer (as ESD implant option is only for 5V/6V devices).</description>
<categories>
</categories>
</category>
<category>
<name>ESD.10</name>
<description>ESD.10 : LVS_IO shall be drawn covering I/O MOS active area by minimum overlap.</description>
<categories>
</categories>
</category>
<category>
<name>CO.1</name>
<description>CO.1 : Min/max contact size. : 0.22µm</description>
<categories>
</categories>
</category>
<category>
<name>CO.2a</name>
<description>CO.2a : min. contact spacing : 0.25µm</description>
<categories>
</categories>
</category>
<category>
<name>CO.2b</name>
<description>CO.2b : Space in 4x4 or larger contact array. : 0.28µm</description>
<categories>
</categories>
</category>
<category>
<name>CO.3</name>
<description>CO.3 : Poly2 overlap of contact. : 0.07µm</description>
<categories>
</categories>
</category>
<category>
<name>CO.4</name>
<description>CO.4 : COMP overlap of contact. : 0.07µm</description>
<categories>
</categories>
</category>
<category>
<name>CO.5a</name>
<description>CO.5a : Nplus overlap of contact on COMP (Only for contacts to butted Nplus and Pplus COMP areas). : 0.1µm</description>
<categories>
</categories>
</category>
<category>
<name>CO.5b</name>
<description>CO.5b : Pplus overlap of contact on COMP (Only for contacts to butted Nplus and Pplus COMP areas). : 0.1µm</description>
<categories>
</categories>
</category>
<category>
<name>CO.6</name>
<description>CO.6 : Metal1 overlap of contact.</description>
<categories>
</categories>
</category>
<category>
<name>CO.6a</name>
<description>CO.6a : (i) Metal1 (&lt; 0.34um) end-of-line overlap. : 0.06µm</description>
<categories>
</categories>
</category>
<category>
<name>CO.6b</name>
<description>CO.6b : (ii) If Metal1 overlaps contact by &lt; 0.04um on one side, adjacent metal1 edges overlap : 0.06µm</description>
<categories>
</categories>
</category>
<category>
<name>CO.7</name>
<description>CO.7 : Space from COMP contact to Poly2 on COMP. : 0.15µm</description>
<categories>
</categories>
</category>
<category>
<name>CO.8</name>
<description>CO.8 : Space from Poly2 contact to COMP. : 0.17µm</description>
<categories>
</categories>
</category>
<category>
<name>CO.9</name>
<description>CO.9 : Contact on NCOMP to PCOMP butting edge is forbidden (contact must not straddle butting edge).</description>
<categories>
</categories>
</category>
<category>
<name>CO.10</name>
<description>CO.10 : Contact on Poly2 gate over COMP is forbidden.</description>
<categories>
</categories>
</category>
<category>
<name>CO.11</name>
<description>CO.11 : Contact on field oxide is forbidden.</description>
<categories>
</categories>
</category>
<category>
<name>MC.1</name>
<description>MC.1 : min. mcell width : 0.4µm</description>
<categories>
</categories>
</category>
<category>
<name>MC.2</name>
<description>MC.2 : min. mcell spacing : 0.4µm</description>
<categories>
</categories>
</category>
<category>
<name>MC.3</name>
<description>MC.3 : Minimum Mcell area : 0.35µm²</description>
<categories>
</categories>
</category>
<category>
<name>MC.4</name>
<description>MC.4 : Minimum area enclosed by Mcell : 0.35µm²</description>
<categories>
</categories>
</category>
<category>
<name>PRES.1</name>
<description>PRES.1 : Minimum width of Poly2 resistor. : 0.8µm</description>
<categories>
</categories>
</category>
<category>
<name>PRES.2</name>
<description>PRES.2 : Minimum space between Poly2 resistors. : 0.4µm</description>
<categories>
</categories>
</category>
<category>
<name>PRES.3</name>
<description>PRES.3 : Minimum space from Poly2 resistor to COMP.</description>
<categories>
</categories>
</category>
<category>
<name>PRES.4</name>
<description>PRES.4 : Minimum space from Poly2 resistor to unrelated Poly2. : 0.6µm</description>
<categories>
</categories>
</category>
<category>
<name>PRES.5</name>
<description>PRES.5 : Minimum Plus implant overlap of Poly2 resistor. : 0.3µm</description>
<categories>
</categories>
</category>
<category>
<name>PRES.6</name>
<description>PRES.6 : Minimum salicide block overlap of Poly2 resistor in width direction. : 0.28µm</description>
<categories>
</categories>
</category>
<category>
<name>PRES.7</name>
<description>PRES.7 : Space from salicide block to contact on Poly2 resistor.</description>
<categories>
</categories>
</category>
<category>
<name>PRES.9a</name>
<description>PRES.9a : Pplus Poly2 resistor shall be covered by RES_MK marking. RES_MK length shall be coincide with resistor length (Defined by SAB length) and width covering the width of Poly2.</description>
<categories>
</categories>
</category>
<category>
<name>PRES.9b</name>
<description>PRES.9b : If the size of single RES_MK mark layer is greater than 15000um2 and both side (X and Y) are greater than 80um. then the minimum spacing to adjacent RES_MK layer. : 20µm</description>
<categories>
</categories>
</category>
<category>
<name>LRES.1</name>
<description>LRES.1 : Minimum width of Poly2 resistor. : 0.8µm</description>
<categories>
</categories>
</category>
<category>
<name>LRES.2</name>
<description>LRES.2 : Minimum space between Poly2 resistors. : 0.4µm</description>
<categories>
</categories>
</category>
<category>
<name>LRES.3</name>
<description>LRES.3 : Minimum space from Poly2 resistor to COMP.</description>
<categories>
</categories>
</category>
<category>
<name>LRES.4</name>
<description>LRES.4 : Minimum space from Poly2 resistor to unrelated Poly2. : 0.6µm</description>
<categories>
</categories>
</category>
<category>
<name>LRES.5</name>
<description>LRES.5 : Minimum Nplus implant overlap of Poly2 resistor. : 0.3µm</description>
<categories>
</categories>
</category>
<category>
<name>LRES.6</name>
<description>LRES.6 : Minimum salicide block overlap of Poly2 resistor in width direction. : 0.28µm</description>
<categories>
</categories>
</category>
<category>
<name>LRES.7</name>
<description>LRES.7 : Space from salicide block to contact on Poly2 resistor.</description>
<categories>
</categories>
</category>
<category>
<name>LRES.9a</name>
<description>LRES.9a : Nplus Poly2 resistor shall be covered by RES_MK marking. RES_MK length shall be coincide with resistor length (Defined by SAB length) and width covering the width of Poly2. </description>
<categories>
</categories>
</category>
<category>
<name>LRES.9b</name>
<description>LRES.9b : If the size of single RES_MK mark layer is greater than 15000um2 and both side (X and Y) are greater than 80um. then the minimum spacing to adjacent RES_MK layer. : 20µm</description>
<categories>
</categories>
</category>
<category>
<name>HRES.1</name>
<description>HRES.1 : Minimum space. Note : Merge if the spacing is less than 0.4 um. : 0.4µm</description>
<categories>
</categories>
</category>
<category>
<name>HRES.2</name>
<description>HRES.2 : Minimum width of Poly2 resistor. : 1µm</description>
<categories>
</categories>
</category>
<category>
<name>HRES.3</name>
<description>HRES.3 : Minimum space between Poly2 resistors. : 0.4µm</description>
<categories>
</categories>
</category>
<category>
<name>HRES.4</name>
<description>HRES.4 : Minimum RESISTOR overlap of Poly2 resistor. : 0.4µm</description>
<categories>
</categories>
</category>
<category>
<name>HRES.5</name>
<description>HRES.5 : Minimum RESISTOR space to unrelated Poly2. : 0.3µm</description>
<categories>
</categories>
</category>
<category>
<name>HRES.6</name>
<description>HRES.6 : Minimum RESISTOR space to COMP.</description>
<categories>
</categories>
</category>
<category>
<name>HRES.7</name>
<description>HRES.7 : Minimum Pplus overlap of contact on Poly2 resistor. : 0.2µm</description>
<categories>
</categories>
</category>
<category>
<name>HRES.8</name>
<description>HRES.8 : Space from salicide block to contact on Poly2 resistor.</description>
<categories>
</categories>
</category>
<category>
<name>HRES.9</name>
<description>HRES.9 : Minimum salicide block overlap of Poly2 resistor in width direction.</description>
<categories>
</categories>
</category>
<category>
<name>HRES.10</name>
<description>HRES.10 : Minimum &amp; maximum Pplus overlap of SAB.</description>
<categories>
</categories>
</category>
<category>
<name>HRES.12a</name>
<description>HRES.12a : P type Poly2 resistor (high sheet rho) shall be covered by RES_MK marking. RES_MK length shall be coincide with resistor length (Defined by Pplus space) and width covering the width of Poly2. </description>
<categories>
</categories>
</category>
<category>
<name>HRES.12b</name>
<description>HRES.12b : If the size of single RES_MK mark layer is greater than 15000 um2 and both side (X and Y) are greater than 80 um. Then the minimum spacing to adjacent RES_MK layer. : 20µm</description>
<categories>
</categories>
</category>
<category>
<name>MIMTM.1</name>
<description>MIMTM.1 : Minimum MiM bottom plate spacing to the bottom plate metal (whether adjacent MiM or routing metal). : 1.2µm</description>
<categories>
</categories>
</category>
<category>
<name>MIMTM.2</name>
<description>MIMTM.2 : Minimum MiM bottom plate overlap of Vian-1 layer. [This is applicable for Vian-1 within 1.06um oversize of FuseTop layer (referenced to virtual bottom plate)]. : 0.4µm</description>
<categories>
</categories>
</category>
<category>
<name>MIMTM.3</name>
<description>MIMTM.3 : Minimum MiM bottom plate overlap of Top plate.</description>
<categories>
</categories>
</category>
<category>
<name>MIMTM.4</name>
<description>MIMTM.4 : Minimum MiM top plate (FuseTop) overlap of Vian-1. : 0.4µm</description>
<categories>
</categories>
</category>
<category>
<name>MIMTM.5</name>
<description>MIMTM.5 : Minimum spacing between top plate and the Vian-1 connecting to the bottom plate. : 0.4µm</description>
<categories>
</categories>
</category>
<category>
<name>MIMTM.6</name>
<description>MIMTM.6 : Minimum spacing between unrelated top plates. : 0.6µm</description>
<categories>
</categories>
</category>
<category>
<name>MIMTM.7</name>
<description>MIMTM.7 : Min FuseTop enclosure by CAP_MK.</description>
<categories>
</categories>
</category>
<category>
<name>MIMTM.8a</name>
<description>MIMTM.8a : Minimum MIM cap area (defined by FuseTop area) (um2). : 25µm²</description>
<categories>
</categories>
</category>
<category>
<name>MIMTM.8b</name>
<description>MIMTM.8b : Maximum single MIM Cap area (Use multiple MIM caps in parallel connection if bigger capacitors are required) (um2). : 10000µm</description>
<categories>
</categories>
</category>
<category>
<name>MIMTM.9</name>
<description>MIMTM.9 : Min. Via (Vian-1) spacing for sea of Via on MIM top plate. : 0.5µm</description>
<categories>
</categories>
</category>
<category>
<name>MIMTM.10</name>
<description>MIMTM.10 : (a) There cannot be any Vian-2 touching MIM bottom plate Metaln-1. (b) MIM bottom plate Metaln-1 can only be connected through the higher Via (Vian-1).</description>
<categories>
</categories>
</category>
<category>
<name>MIMTM.11</name>
<description>MIMTM.11 : Bottom plate of multiple MIM caps can be shared (for common nodes) as long as total MIM area with that single common plate does not exceed MIMTM.8b rule. : -µm</description>
<categories>
</categories>
</category>
<category>
<name>NAT.1</name>
<description>NAT.1 : Min. NAT Overlap of COMP of Native Vt NMOS. : 2µm</description>
<categories>
</categories>
</category>
<category>
<name>NAT.2</name>
<description>NAT.2 : Space to unrelated COMP (outside NAT). : 0.3µm</description>
<categories>
</categories>
</category>
<category>
<name>NAT.3</name>
<description>NAT.3 : Space to NWell edge. : 0.5µm</description>
<categories>
</categories>
</category>
<category>
<name>NAT.4</name>
<description>NAT.4 : Minimum channel length for 3.3V Native Vt NMOS (For smaller L Ioff will be higher than Spec). : 1.8µm</description>
<categories>
</categories>
</category>
<category>
<name>NAT.5</name>
<description>NAT.5 : Minimum channel length for 6.0V Native Vt NMOS (For smaller L Ioff will be higher than Spec). : 1.8µm</description>
<categories>
</categories>
</category>
<category>
<name>NAT.6</name>
<description>NAT.6 : Two or more COMPs if connected to different potential are not allowed under same NAT layer.</description>
<categories>
</categories>
</category>
<category>
<name>NAT.7</name>
<description>NAT.7 : Minimum NAT to NAT spacing. : 0.74µm</description>
<categories>
</categories>
</category>
<category>
<name>NAT.8</name>
<description>NAT.8 : Min. Dualgate overlap of NAT (for 5V/6V) native VT NMOS only.</description>
<categories>
</categories>
</category>
<category>
<name>NAT.9</name>
<description>NAT.9 : Poly interconnect under NAT layer is not allowed, minimum spacing of un-related poly from the NAT layer.</description>
<categories>
</categories>
</category>
<category>
<name>NAT.10</name>
<description>NAT.10 : Nwell, inside NAT layer are not allowed.</description>
<categories>
</categories>
</category>
<category>
<name>NAT.11</name>
<description>NAT.11 : NCOMP not intersecting to Poly2, is not allowed inside NAT layer.</description>
<categories>
</categories>
</category>
<category>
<name>NAT.12</name>
<description>NAT.12 : Poly2 not intersecting with COMP is not allowed inside NAT (Poly2 resistor is not allowed inside NAT).</description>
<categories>
</categories>
</category>
<category>
<name>BJT.1</name>
<description>BJT.1 : Min. DRC_BJT overlap of DNWELL for NPN BJT.</description>
<categories>
</categories>
</category>
<category>
<name>BJT.2</name>
<description>BJT.2 : Min. DRC_BJT overlap of PCOM in Psub.</description>
<categories>
</categories>
</category>
<category>
<name>BJT.3</name>
<description>BJT.3 : Minimum space of DRC_BJT layer to unrelated COMP. : 0.1µm</description>
<categories>
</categories>
</category>
<category>
<name>DE.2</name>
<description>DE.2 : Minimum NDMY or PMNDMY size (x or y dimension in um). : 0.8µm</description>
<categories>
</categories>
</category>
<category>
<name>DE.3</name>
<description>DE.3 : If size greater than 15000 um2 then two sides should not be greater than (um).</description>
<categories>
</categories>
</category>
<category>
<name>DE.4</name>
<description>DE.4 : Minimum NDMY to NDMY space (Merge if space is less). : 20µm</description>
<categories>
</categories>
</category>
<category>
<name>LVS_BJT.1</name>
<description>LVS_BJT.1 : Minimum LVS_BJT enclosure of NPN or PNP Emitter COMP layers</description>
<categories>
</categories>
</category>
<category>
<name>O.DF.3a</name>
<description>O.DF.3a : Min. COMP Space. P-substrate tap (PCOMP outside NWELL) can be butted for different voltage devices as the potential is same. : 0.24µm</description>
<categories>
</categories>
</category>
<category>
<name>O.DF.6</name>
<description>O.DF.6 : Min. COMP extend beyond poly2 (it also means source/drain overhang). : 0.22µm</description>
<categories>
</categories>
</category>
<category>
<name>O.DF.9</name>
<description>O.DF.9 : Min. COMP area (um2). : 0.1444µm²</description>
<categories>
</categories>
</category>
<category>
<name>O.PL.2</name>
<description>O.PL.2 : Min. poly2 width. : 0.22µm</description>
<categories>
</categories>
</category>
<category>
<name>O.PL.3a</name>
<description>O.PL.3a : Min. poly2 Space on COMP. : 0.18µm</description>
<categories>
</categories>
</category>
<category>
<name>O.PL.4</name>
<description>O.PL.4 : Min. extension beyond COMP to form Poly2 end cap. : 0.14µm</description>
<categories>
</categories>
</category>
<category>
<name>O.SB.2</name>
<description>O.SB.2 : Min. salicide Block Space. : 0.28µm</description>
<categories>
</categories>
</category>
<category>
<name>O.SB.3</name>
<description>O.SB.3 : Min. space from salicide block to unrelated COMP. : 0.09µm</description>
<categories>
</categories>
</category>
<category>
<name>O.SB.4</name>
<description>O.SB.4 : Min. space from salicide block to contact.</description>
<categories>
</categories>
</category>
<category>
<name>O.SB.5b_3.3V</name>
<description>O.SB.5b_3.3V : Min. space from salicide block to unrelated Poly2 on COMP. : 0.1µm</description>
<categories>
</categories>
</category>
<category>
<name>O.SB.9</name>
<description>O.SB.9 : Min. salicide block extension beyond unsalicided Poly2. : 0.1µm</description>
<categories>
</categories>
</category>
<category>
<name>O.SB.11</name>
<description>O.SB.11 : Min. salicide block overlap with COMP. : 0.04µm</description>
<categories>
</categories>
</category>
<category>
<name>O.SB.13_3.3V</name>
<description>O.SB.13_3.3V : Min. area of silicide block (um2). : 1.488µm²</description>
<categories>
</categories>
</category>
<category>
<name>O.SB.13_5V</name>
<description>O.SB.13_5V : Min. area of silicide block (um2). : 2µm²</description>
<categories>
</categories>
</category>
<category>
<name>O.CO.7</name>
<description>O.CO.7 : Min. space from COMP contact to Poly2 on COMP. : 0.13µm</description>
<categories>
</categories>
</category>
<category>
<name>O.PL.ORT</name>
<description>O.PL.ORT : Orientation-restricted gates must have the gate width aligned along the X-axis (poly line running horizontally) in reference to wafer notch down. : 0µm</description>
<categories>
</categories>
</category>
<category>
<name>EF.01</name>
<description>EF.01 : Min. (Poly2 butt PLFUSE) within EFUSE_MK and Pplus.</description>
<categories>
</categories>
</category>
<category>
<name>EF.02</name>
<description>EF.02 : Min. Max. PLFUSE width. : 0.18µm</description>
<categories>
</categories>
</category>
<category>
<name>EF.03</name>
<description>EF.03 : Min. Max. PLFUSE length. : 1.26µm</description>
<categories>
</categories>
</category>
<category>
<name>EF.04a</name>
<description>EF.04a : Min. Max. PLFUSE overlap Poly2 (coinciding permitted) and touch cathode and anode.</description>
<categories>
</categories>
</category>
<category>
<name>EF.04b</name>
<description>EF.04b : PLFUSE must be rectangular. : -µm</description>
<categories>
</categories>
</category>
<category>
<name>EF.04c</name>
<description>EF.04c : Cathode Poly2 must be rectangular. : -µm</description>
<categories>
</categories>
</category>
<category>
<name>EF.04d</name>
<description>EF.04d : Anode Poly2 must be rectangular. : -µm</description>
<categories>
</categories>
</category>
<category>
<name>EF.05</name>
<description>EF.05 : Min./Max. LVS_Source overlap Poly2 (at Anode).</description>
<categories>
</categories>
</category>
<category>
<name>EF.06</name>
<description>EF.06 : Min./Max. Cathode Poly2 width. : 2.26µm</description>
<categories>
</categories>
</category>
<category>
<name>EF.07</name>
<description>EF.07 : Min./Max. Cathode Poly2 length. : 1.84µm</description>
<categories>
</categories>
</category>
<category>
<name>EF.08</name>
<description>EF.08 : Min./Max. Anode Poly2 width. : 1.06µm</description>
<categories>
</categories>
</category>
<category>
<name>EF.09</name>
<description>EF.09 : Min./Max. Anode Poly2 length. : 2.43µm</description>
<categories>
</categories>
</category>
<category>
<name>EF.10</name>
<description>EF.10 : Min. Cathode Poly2 to Poly2 space. : 0.26µm</description>
<categories>
</categories>
</category>
<category>
<name>EF.11</name>
<description>EF.11 : Min. Anode Poly2 to Poly2 space. : 0.26µm</description>
<categories>
</categories>
</category>
<category>
<name>EF.12</name>
<description>EF.12 : Min. Space of Cathode Contact to PLFUSE end.</description>
<categories>
</categories>
</category>
<category>
<name>EF.13</name>
<description>EF.13 : Min. Space of Anode Contact to PLFUSE end.</description>
<categories>
</categories>
</category>
<category>
<name>EF.14</name>
<description>EF.14 : Min. EFUSE_MK enclose LVS_Source.</description>
<categories>
</categories>
</category>
<category>
<name>EF.15</name>
<description>EF.15 : NO Contact is allowed to touch PLFUSE.</description>
<categories>
</categories>
</category>
<category>
<name>EF.16a</name>
<description>EF.16a : Cathode must contain exact number of Contacts at each ends. : 4µm</description>
<categories>
</categories>
</category>
<category>
<name>EF.16b</name>
<description>EF.16b : Anode must contain exact number of Contacts at each ends. : 4µm</description>
<categories>
</categories>
</category>
<category>
<name>EF.17</name>
<description>EF.17 : Min. Space of EFUSE_MK to EFUSE_MK. : 0.26µm</description>
<categories>
</categories>
</category>
<category>
<name>EF.18</name>
<description>EF.18 : PLFUSE must sit on field oxide (NOT COMP), no cross with any COMP, Nplus, Pplus, ESD, SAB, Resistor, Metal1, Metal2.</description>
<categories>
</categories>
</category>
<category>
<name>EF.19</name>
<description>EF.19 : Min. PLFUSE space to Metal1, Metal2.</description>
<categories>
</categories>
</category>
<category>
<name>EF.20</name>
<description>EF.20 : Min. PLFUSE space to COMP, Nplus, Pplus, Resistor, ESD, SAB. : 2.73µm</description>
<categories>
</categories>
</category>
<category>
<name>EF.21</name>
<description>EF.21 : Min./Max. eFUSE Poly2 length. : 5.53µm</description>
<categories>
</categories>
</category>
<category>
<name>EF.22a</name>
<description>EF.22a : Min./Max. Cathode Poly2 overlap with PLFUSE in width direction. : 1.04µm</description>
<categories>
</categories>
</category>
<category>
<name>EF.22b</name>
<description>EF.22b : Min./Max. Anode Poly2 overlap with PLFUSE in width direction. : 0.44µm</description>
<categories>
</categories>
</category>
<category>
<name>MDN.1</name>
<description>MDN.1 : Min MVSD width (for litho purpose). : 1µm</description>
<categories>
</categories>
</category>
<category>
<name>MDN.2a</name>
<description>MDN.2a : Min MVSD space [Same Potential]. : 1µm</description>
<categories>
</categories>
</category>
<category>
<name>MDN.2b</name>
<description>MDN.2b : Min MVSD space [Diff Potential]. : 2µm</description>
<categories>
</categories>
</category>
<category>
<name>MDN.3a</name>
<description>MDN.3a : Min transistor channel length. : 0.6µm</description>
<categories>
</categories>
</category>
<category>
<name>MDN.3b</name>
<description>MDN.3b : Max transistor channel length: 20 um</description>
<categories>
</categories>
</category>
<category>
<name>MDN.4a</name>
<description>MDN.4a : Min transistor channel width. : 4 µm</description>
<categories>
</categories>
</category>
<category>
<name>MDN.4b</name>
<description>MDN.4b : Max transistor channel width. : 50 um </description>
<categories>
</categories>
</category>
<category>
<name>MDN.5ai</name>
<description>MDN.5ai : Min PCOMP (Pplus AND COMP) space to LDNMOS Drain MVSD (source and body tap non-butted). PCOMP (Pplus AND COMP) intercept with LDNMOS Drain MVSD is not allowed.</description>
<categories>
</categories>
</category>
<category>
<name>MDN.5aii</name>
<description>MDN.5aii : Min PCOMP (Pplus AND COMP) space to LDNMOS Drain MVSD (source and body tap butted). PCOMP (Pplus AND COMP) intercept with LDNMOS Drain MVSD is not allowed. : 0.92µm</description>
<categories>
</categories>
</category>
<category>
<name>MDN.5b</name>
<description>MDN.5b : Min PCOMP (Pplus AND COMP) space to LDNMOS Source (Nplus AND COMP). Use butted source and p-substrate tab otherwise and that is good for Latch-up immunity as well.</description>
<categories>
</categories>
</category>
<category>
<name>MDN.5c</name>
<description>MDN.5c : Maximum distance of the nearest edge of the substrate tab from NCOMP edge. : 15µm</description>
<categories>
</categories>
</category>
<category>
<name>MDN.6</name>
<description>MDN.6 : ALL LDNMOS shall be covered by Dualgate layer.</description>
<categories>
</categories>
</category>
<category>
<name>MDN.6a</name>
<description>MDN.6a : Min Dualgate enclose NCOMP.</description>
<categories>
</categories>
</category>
<category>
<name>MDN.7</name>
<description>MDN.7 : Each LDNMOS shall be covered by LDMOS_XTOR (GDS#226) mark layer.</description>
<categories>
</categories>
</category>
<category>
<name>MDN.7a</name>
<description>MDN.7a : Min LDMOS_XTOR enclose Dualgate.</description>
<categories>
</categories>
</category>
<category>
<name>MDN.8a</name>
<description>MDN.8a : Min LDNMOS drain MVSD space to any other equal potential Nwell space.</description>
<categories>
</categories>
</category>
<category>
<name>MDN.8b</name>
<description>MDN.8b : Min LDNMOS drain MVSD space to any other different potential Nwell space.</description>
<categories>
</categories>
</category>
<category>
<name>MDN.9</name>
<description>MDN.9 : Min LDNMOS drain MVSD space to NCOMP (Nplus AND COMP) outside LDNMOS drain MVSD. : 4µm</description>
<categories>
</categories>
</category>
<category>
<name>MDN.10a</name>
<description>MDN.10a : Min LDNMOS POLY2 width. : 1.2µm</description>
<categories>
</categories>
</category>
<category>
<name>MDN.10b</name>
<description>MDN.10b : Min POLY2 extension beyond COMP in the width direction of the transistor (other than the LDNMOS drain direction). : 0.4µm</description>
<categories>
</categories>
</category>
<category>
<name>MDN.10c</name>
<description>MDN.10c : Min/Max POLY2 extension beyond COMP on the field towards LDNMOS drain COMP direction.</description>
<categories>
</categories>
</category>
<category>
<name>MDN.10d</name>
<description>MDN.10d : Min/Max POLY2 on field space to LDNMOS drain COMP.</description>
<categories>
</categories>
</category>
<category>
<name>MDN.10ei</name>
<description>MDN.10ei : Min POLY2 space to Psub tap (source and body tap non-butted).</description>
<categories>
</categories>
</category>
<category>
<name>MDN.10eii</name>
<description>MDN.10eii : Min POLY2 space to Psub tap (source and body tap butted). : 0.32µm</description>
<categories>
</categories>
</category>
<category>
<name>MDN.10f</name>
<description>MDN.10f : Poly2 interconnect in HV region (LDMOS_XTOR marked region) not allowed. Also, any Poly2 interconnect with poly2 to substrate potential greater than 6V is not allowed.</description>
<categories>
</categories>
</category>
<category>
<name>MDN.11</name>
<description>MDN.11 : Min/Max MVSD overlap channel COMP ((((LDMOS_XTOR AND MVSD) AND COMP) AND POLY2) AND NPlus).</description>
<categories>
</categories>
</category>
<category>
<name>MDN.12</name>
<description>MDN.12 : Min MVSD enclose NCOMP in the LDNMOS drain and in the direction along the transistor width.</description>
<categories>
</categories>
</category>
<category>
<name>MDN.13a</name>
<description>MDN.13a : Max single finger width. : 50µm</description>
<categories>
</categories>
</category>
<category>
<name>MDN.13b</name>
<description>MDN.13b : Layout shall have alternative source &amp; drain.</description>
<categories>
</categories>
</category>
<category>
<name>MDN.13c</name>
<description>MDN.13c : Both sides of the transistor shall be terminated by source.</description>
<categories>
</categories>
</category>
<category>
<name>MDN.13d</name>
<description>MDN.13d : Every two poly fingers shall be surrounded by a P-sub guard ring. (Exclude the case when each LDNMOS transistor have full width butting to well tap).</description>
<categories>
</categories>
</category>
<category>
<name>MDN.14</name>
<description>MDN.14 : Min MVSD space to any DNWELL.</description>
<categories>
</categories>
</category>
<category>
<name>MDN.15a</name>
<description>MDN.15a : Min LDNMOS drain COMP width. : 0.22µm</description>
<categories>
</categories>
</category>
<category>
<name>MDN.15b</name>
<description>MDN.15b : Min LDNMOS drain COMP enclose contact. : 0µm</description>
<categories>
</categories>
</category>
<category>
<name>MDN.17</name>
<description>MDN.17 : It is recommended to surround the LDNMOS transistor with non-broken Psub guard ring to improve the latch up immunity. Guideline to improve the latch up immunity.</description>
<categories>
</categories>
</category>
<category>
<name>MDP.1</name>
<description>MDP.1 : Minimum transistor channel length. : 0.6µm</description>
<categories>
</categories>
</category>
<category>
<name>MDP.1a</name>
<description>MDP.1a : Max transistor channel length.</description>
<categories>
</categories>
</category>
<category>
<name>MDP.2</name>
<description>MDP.2 : Minimum transistor channel width. : 4µm</description>
<categories>
</categories>
</category>
<category>
<name>MDP.3</name>
<description>MDP.3 : Each LDPMOS shall be surrounded by non-broken Nplus guard ring inside DNWELL</description>
<categories>
</categories>
</category>
<category>
<name>MDP.3ai</name>
<description>MDP.3ai : Min NCOMP (Nplus AND COMP) space to MVPSD (source and body tap non-butted). NCOMP (Nplus AND COMP) intercept with MVPSD is not allowed.</description>
<categories>
</categories>
</category>
<category>
<name>MDP.3aii</name>
<description>MDP.3aii : Min NCOMP (Nplus AND COMP) space to MVPSD (source and body tap butted). NCOMP (Nplus AND COMP) intercept with MVPSD is not allowed.</description>
<categories>
</categories>
</category>
<category>
<name>MDP.3b</name>
<description>MDP.3b : Min NCOMP (Nplus AND COMP) space to PCOMP in DNWELL (Pplus AND COMP AND DNWELL). Use butted source and DNWELL contacts otherwise and that is best for Latch-up immunity as well. : 0.4µm</description>
<categories>
</categories>
</category>
<category>
<name>MDP.3c</name>
<description>MDP.3c : Maximum distance of the nearest edge of the DNWELL tab (NCOMP inside DNWELL) from PCOMP edge (PCOMP inside DNWELL). : 15µm</description>
<categories>
</categories>
</category>
<category>
<name>MDP.3d</name>
<description>MDP.3d : The metal connection for the Nplus guard ring recommended to be continuous. The maximum gap between this metal if broken. Note: To put maximum number of contact under metal for better manufacturability and reliability. : 10µm</description>
<categories>
</categories>
</category>
<category>
<name>MDP.4</name>
<description>MDP.4 : DNWELL covering LDPMOS shall be surrounded by non broken Pplus guard. The metal connection for the Pplus guard ring recommended to be continuous, The maximum gap between this metal if broken. Note: To put maximum number of contact under metal for better manufacturability and reliability.</description>
<categories>
</categories>
</category>
<category>
<name>MDP.4a</name>
<description>MDP.4a : Min PCOMP (Pplus AND COMP) space to DNWELL. : 2.5µm</description>
<categories>
</categories>
</category>
<category>
<name>MDP.4b</name>
<description>MDP.4b : Maximum distance of the nearest edge of the DNWELL from the PCOMP Guard ring outside DNWELL. : 15µm</description>
<categories>
</categories>
</category>
<category>
<name>MDP.5</name>
<description>MDP.5 : Each LDPMOS shall be covered by Dualgate layer.</description>
<categories>
</categories>
</category>
<category>
<name>MDP.5a</name>
<description>MDP.5a : Minimum Dualgate enclose Plus guarding ring PCOMP (Pplus AND COMP). : 0.5µm</description>
<categories>
</categories>
</category>
<category>
<name>MDP.6</name>
<description>MDP.6 : Each LDPMOS shall be covered by LDMOS_XTOR (GDS#226) layer.</description>
<categories>
</categories>
</category>
<category>
<name>MDP.6a</name>
<description>MDP.6a : Minimum LDMOS_XTOR enclose Dualgate.</description>
<categories>
</categories>
</category>
<category>
<name>MDP.7</name>
<description>MDP.7 : Minimum LDMOS_XTOR layer space to Nwell outside LDMOS_XTOR. : 2µm</description>
<categories>
</categories>
</category>
<category>
<name>MDP.8</name>
<description>MDP.8 : Minimum LDMOS_XTOR layer space to NCOMP outside LDMOS_XTOR. : 1.5µm</description>
<categories>
</categories>
</category>
<category>
<name>MDP.9a</name>
<description>MDP.9a : Min LDPMOS POLY2 width. : 1.2µm</description>
<categories>
</categories>
</category>
<category>
<name>MDP.9b</name>
<description>MDP.9b : Min POLY2 extension beyond COMP in the width direction of the transistor (other than the LDMOS drain direction). : 0.4µm</description>
<categories>
</categories>
</category>
<category>
<name>MDP.9c</name>
<description>MDP.9c : Min/Max POLY2 extension beyond COMP on the field towards LDPMOS drain (MVPSD AND COMP AND Pplus NOT POLY2) direction.</description>
<categories>
</categories>
</category>
<category>
<name>MDP.9d</name>
<description>MDP.9d : Min/Max POLY2 on field to LDPMOS drain COMP (MVPSD AND COMP AND Pplus NOT POLY2) space.</description>
<categories>
</categories>
</category>
<category>
<name>MDP.9ei</name>
<description>MDP.9ei : Min LDMPOS gate Poly2 space to Nplus guardring (source and body tap non-butted).</description>
<categories>
</categories>
</category>
<category>
<name>MDP.9eii</name>
<description>MDP.9eii : Min LDMPOS gate Poly2 space to Nplus guardring (source and body tap butted).</description>
<categories>
</categories>
</category>
<category>
<name>MDP.9f</name>
<description>MDP.9f : Poly2 interconnect is not allowed in LDPMOS region (LDMOS_XTOR marked region). : -µm</description>
<categories>
</categories>
</category>
<category>
<name>MDP.10</name>
<description>MDP.10 : Min/Max MVPSD overlap onto the channel (LDMOS_XTOR AND COMP AND POLY2 AND Pplus).</description>
<categories>
</categories>
</category>
<category>
<name>MDP.10a</name>
<description>MDP.10a : Min MVPSD space within LDMOS_XTOR marking [diff potential]. : 2µm</description>
<categories>
</categories>
</category>
<category>
<name>MDP.10b</name>
<description>MDP.10b : Min MVPSD space [same potential]. Merge if space less than 1um. : 1µm</description>
<categories>
</categories>
</category>
<category>
<name>MDP.11</name>
<description>MDP.11 : Min MVPSD enclosing PCOMP in the drain (MVPSD AND COMP NOT POLY2) direction and in the direction along the transistor width.</description>
<categories>
</categories>
</category>
<category>
<name>MDP.12</name>
<description>MDP.12 : Min DNWELL enclose Nplus guard ring (NCOMP). : 0.66µm</description>
<categories>
</categories>
</category>
<category>
<name>MDP.13a</name>
<description>MDP.13a : Max single finger width. : 50µm</description>
<categories>
</categories>
</category>
<category>
<name>MDP.13b</name>
<description>MDP.13b : Layout shall have alternative source &amp; drain.</description>
<categories>
</categories>
</category>
<category>
<name>MDP.13c</name>
<description>MDP.13c : Both sides of the transistor shall be terminated by source.</description>
<categories>
</categories>
</category>
<category>
<name>MDP.15</name>
<description>MDP.15 : Min DNWELL enclosing MVPSD to any DNWELL spacing. : 6µm</description>
<categories>
</categories>
</category>
<category>
<name>MDP.16a</name>
<description>MDP.16a : Min LDPMOS drain COMP width. : 0.22µm</description>
<categories>
</categories>
</category>
<category>
<name>MDP.16b</name>
<description>MDP.16b : Min LDPMOS drain COMP enclose contact. : 0µm</description>
<categories>
</categories>
</category>
<category>
<name>MDP.17a</name>
<description>MDP.17a : For better latch up immunity, it is necessary to put DNWELL guard ring between MVPSD Inside DNWELL covered by LDMOS_XTOR and NCOMP (outside DNWELL and outside Nwell) when spacing between them is less than 40um.</description>
<categories>
</categories>
</category>
<category>
<name>MDP.17c</name>
<description>MDP.17c : DNWELL guard ring shall have NCOMP tab to be connected to highest potential</description>
<categories>
</categories>
</category>
<category>
<name>Y.NW.2b_3.3V</name>
<description>Y.NW.2b_3.3V : Min. Nwell Space (Outside DNWELL, Inside YMTP_MK) [Different potential]. : 1µm</description>
<categories>
</categories>
</category>
<category>
<name>Y.NW.2b_5V</name>
<description>Y.NW.2b_5V : Min. Nwell Space (Outside DNWELL, Inside YMTP_MK) [Different potential]. : 1µm</description>
<categories>
</categories>
</category>
<category>
<name>Y.DF.6_5V</name>
<description>Y.DF.6_5V : Min. COMP extend beyond gate (it also means source/drain overhang) inside YMTP_MK. : 0.15µm</description>
<categories>
</categories>
</category>
<category>
<name>Y.DF.16_3.3V</name>
<description>Y.DF.16_3.3V : Min. space from (Nwell outside DNWELL) to (unrelated NCOMP outside Nwell and DNWELL) (inside YMTP_MK). : 0.27µm</description>
<categories>
</categories>
</category>
<category>
<name>Y.DF.16_5V</name>
<description>Y.DF.16_5V : Min. space from (Nwell outside DNWELL) to (unrelated NCOMP outside Nwell and DNWELL) (inside YMTP_MK). : 0.23µm</description>
<categories>
</categories>
</category>
<category>
<name>Y.PL.1_3.3V</name>
<description>Y.PL.1_3.3V : Interconnect Width (inside YMTP_MK). : 0.13µm</description>
<categories>
</categories>
</category>
<category>
<name>Y.PL.1_5V</name>
<description>Y.PL.1_5V : Interconnect Width (inside YMTP_MK). This rule is currently not applicable for 5V.</description>
<categories>
</categories>
</category>
<category>
<name>Y.PL.2_3.3V</name>
<description>Y.PL.2_3.3V : Gate Width (Channel Length) (inside YMTP_MK). : 0.13µm</description>
<categories>
</categories>
</category>
<category>
<name>Y.PL.2_5V</name>
<description>Y.PL.2_5V : Gate Width (Channel Length) (inside YMTP_MK). : 0.47µm</description>
<categories>
</categories>
</category>
<category>
<name>Y.PL.4_5V</name>
<description>Y.PL.4_5V : Poly2 extension beyond COMP to form Poly2 end cap (inside YMTP_MK). : 0.16µm</description>
<categories>
</categories>
</category>
<category>
<name>Y.PL.5a_3.3V</name>
<description>Y.PL.5a_3.3V : Space from field Poly2 to unrelated COMP (inside YMTP_MK). Space from field Poly2 to Guard-ring (inside YMTP_MK). : 0.04µm</description>
<categories>
</categories>
</category>
<category>
<name>Y.PL.5a_5V</name>
<description>Y.PL.5a_5V : Space from field Poly2 to unrelated COMP (inside YMTP_MK). Space from field Poly2 to Guard-ring (inside YMTP_MK). : 0.2µm</description>
<categories>
</categories>
</category>
<category>
<name>Y.PL.5b_3.3V</name>
<description>Y.PL.5b_3.3V : Space from field Poly2 to related COMP (inside YMTP_MK). : 0.04µm</description>
<categories>
</categories>
</category>
<category>
<name>Y.PL.5b_5V</name>
<description>Y.PL.5b_5V : Space from field Poly2 to related COMP (inside YMTP_MK). : 0.2µm</description>
<categories>
</categories>
</category>
<category>
<name>S.DF.4c_MV</name>
<description>S.DF.4c_MV : Min. (Nwell overlap of PCOMP) outside DNWELL. : 0.45µm</description>
<categories>
</categories>
</category>
<category>
<name>S.DF.6_MV</name>
<description>S.DF.6_MV : Min. COMP extend beyond gate (it also means source/drain overhang). : 0.32µm</description>
<categories>
</categories>
</category>
<category>
<name>S.DF.7_MV</name>
<description>S.DF.7_MV : Min. (LVPWELL Spacer to PCOMP) inside DNWELL. : 0.45µm</description>
<categories>
</categories>
</category>
<category>
<name>S.DF.8_MV</name>
<description>S.DF.8_MV : Min. (LVPWELL overlap of NCOMP) Inside DNWELL. : 0.45µm</description>
<categories>
</categories>
</category>
<category>
<name>S.DF.16_MV</name>
<description>S.DF.16_MV : Min. space from (Nwell outside DNWELL) to (NCOMP outside Nwell and DNWELL). : 0.45µm</description>
<categories>
</categories>
</category>
<category>
<name>S.PL.5a_MV</name>
<description>S.PL.5a_MV : Space from field Poly2 to unrelated COMP Spacer from field Poly2 to Guard-ring. : 0.12µm</description>
<categories>
</categories>
</category>
<category>
<name>S.PL.5b_MV</name>
<description>S.PL.5b_MV : Space from field Poly2 to related COMP. : 0.12µm</description>
<categories>
</categories>
</category>
<category>
<name>S.CO.4_MV</name>
<description>S.CO.4_MV : COMP overlap of contact. : 0.04µm</description>
<categories>
</categories>
</category>
<category>
<name>S.DF.4c_LV</name>
<description>S.DF.4c_LV : Min. (Nwell overlap of PCOMP) outside DNWELL. : 0.4µm</description>
<categories>
</categories>
</category>
<category>
<name>S.DF.16_LV</name>
<description>S.DF.16_LV : Min. space from (Nwell outside DNWELL) to (NCOMP outside Nwell and DNWELL). : 0.4µm</description>
<categories>
</categories>
</category>
<category>
<name>S.CO.3_LV</name>
<description>S.CO.3_LV : Poly2 overlap of contact. : 0.04µm</description>
<categories>
</categories>
</category>
<category>
<name>S.CO.4_LV</name>
<description>S.CO.4_LV : COMP overlap of contact. : 0.03µm</description>
<categories>
</categories>
</category>
<category>
<name>S.CO.6_ii_LV</name>
<description>S.CO.6_ii_LV : (ii) If Metal1 overlaps contact by &lt; 0.04um on one side, adjacent metal1 edges overlap</description>
<categories>
</categories>
</category>
<category>
<name>S.M1.1_LV</name>
<description>S.M1.1_LV : min. metal1 width : 0.22µm</description>
<categories>
</categories>
</category>
<category>
<name>comp_OFFGRID</name>
<description>OFFGRID : OFFGRID vertex on comp</description>
<categories>
</categories>
</category>
<category>
<name>comp_angle</name>
<description>ACUTE : non 45 degree angle comp</description>
<categories>
</categories>
</category>
<category>
<name>dnwell_OFFGRID</name>
<description>OFFGRID : OFFGRID vertex on dnwell</description>
<categories>
</categories>
</category>
<category>
<name>dnwell_angle</name>
<description>ACUTE : non 45 degree angle dnwell</description>
<categories>
</categories>
</category>
<category>
<name>nwell_OFFGRID</name>
<description>OFFGRID : OFFGRID vertex on nwell</description>
<categories>
</categories>
</category>
<category>
<name>nwell_angle</name>
<description>ACUTE : non 45 degree angle nwell</description>
<categories>
</categories>
</category>
<category>
<name>lvpwell_OFFGRID</name>
<description>OFFGRID : OFFGRID vertex on lvpwell</description>
<categories>
</categories>
</category>
<category>
<name>lvpwell_angle</name>
<description>ACUTE : non 45 degree angle lvpwell</description>
<categories>
</categories>
</category>
<category>
<name>dualgate_OFFGRID</name>
<description>OFFGRID : OFFGRID vertex on dualgate</description>
<categories>
</categories>
</category>
<category>
<name>dualgate_angle</name>
<description>ACUTE : non 45 degree angle dualgate</description>
<categories>
</categories>
</category>
<category>
<name>poly2_OFFGRID</name>
<description>OFFGRID : OFFGRID vertex on poly2</description>
<categories>
</categories>
</category>
<category>
<name>poly2_angle</name>
<description>ACUTE : non 45 degree angle poly2</description>
<categories>
</categories>
</category>
<category>
<name>nplus_OFFGRID</name>
<description>OFFGRID : OFFGRID vertex on nplus</description>
<categories>
</categories>
</category>
<category>
<name>nplus_angle</name>
<description>ACUTE : non 45 degree angle nplus</description>
<categories>
</categories>
</category>
<category>
<name>pplus_OFFGRID</name>
<description>OFFGRID : OFFGRID vertex on pplus</description>
<categories>
</categories>
</category>
<category>
<name>pplus_angle</name>
<description>ACUTE : non 45 degree angle pplus</description>
<categories>
</categories>
</category>
<category>
<name>sab_OFFGRID</name>
<description>OFFGRID : OFFGRID vertex on sab</description>
<categories>
</categories>
</category>
<category>
<name>sab_angle</name>
<description>ACUTE : non 45 degree angle sab</description>
<categories>
</categories>
</category>
<category>
<name>esd_OFFGRID</name>
<description>OFFGRID : OFFGRID vertex on esd</description>
<categories>
</categories>
</category>
<category>
<name>esd_angle</name>
<description>ACUTE : non 45 degree angle esd</description>
<categories>
</categories>
</category>
<category>
<name>contact_OFFGRID</name>
<description>OFFGRID : OFFGRID vertex on contact</description>
<categories>
</categories>
</category>
<category>
<name>contact_angle</name>
<description>ACUTE : non 45 degree angle contact</description>
<categories>
</categories>
</category>
<category>
<name>metal1_OFFGRID</name>
<description>OFFGRID : OFFGRID vertex on metal1</description>
<categories>
</categories>
</category>
<category>
<name>metal1_angle</name>
<description>ACUTE : non 45 degree angle metal1</description>
<categories>
</categories>
</category>
<category>
<name>via1_OFFGRID</name>
<description>OFFGRID : OFFGRID vertex on via1</description>
<categories>
</categories>
</category>
<category>
<name>via1_angle</name>
<description>ACUTE : non 45 degree angle via1</description>
<categories>
</categories>
</category>
<category>
<name>metal2_OFFGRID</name>
<description>OFFGRID : OFFGRID vertex on metal2</description>
<categories>
</categories>
</category>
<category>
<name>metal2_angle</name>
<description>ACUTE : non 45 degree angle metal2</description>
<categories>
</categories>
</category>
<category>
<name>via2_OFFGRID</name>
<description>OFFGRID : OFFGRID vertex on via2</description>
<categories>
</categories>
</category>
<category>
<name>via2_angle</name>
<description>ACUTE : non 45 degree angle via2</description>
<categories>
</categories>
</category>
<category>
<name>metal3_OFFGRID</name>
<description>OFFGRID : OFFGRID vertex on metal3</description>
<categories>
</categories>
</category>
<category>
<name>metal3_angle</name>
<description>ACUTE : non 45 degree angle metal3</description>
<categories>
</categories>
</category>
<category>
<name>via3_OFFGRID</name>
<description>OFFGRID : OFFGRID vertex on via3</description>
<categories>
</categories>
</category>
<category>
<name>via3_angle</name>
<description>ACUTE : non 45 degree angle via3</description>
<categories>
</categories>
</category>
<category>
<name>metal4_OFFGRID</name>
<description>OFFGRID : OFFGRID vertex on metal4</description>
<categories>
</categories>
</category>
<category>
<name>metal4_angle</name>
<description>ACUTE : non 45 degree angle metal4</description>
<categories>
</categories>
</category>
<category>
<name>via4_OFFGRID</name>
<description>OFFGRID : OFFGRID vertex on via4</description>
<categories>
</categories>
</category>
<category>
<name>via4_angle</name>
<description>ACUTE : non 45 degree angle via4</description>
<categories>
</categories>
</category>
<category>
<name>metal5_OFFGRID</name>
<description>OFFGRID : OFFGRID vertex on metal5</description>
<categories>
</categories>
</category>
<category>
<name>metal5_angle</name>
<description>ACUTE : non 45 degree angle metal5</description>
<categories>
</categories>
</category>
<category>
<name>via5_OFFGRID</name>
<description>OFFGRID : OFFGRID vertex on via5</description>
<categories>
</categories>
</category>
<category>
<name>via5_angle</name>
<description>ACUTE : non 45 degree angle via5</description>
<categories>
</categories>
</category>
<category>
<name>metaltop_OFFGRID</name>
<description>OFFGRID : OFFGRID vertex on metaltop</description>
<categories>
</categories>
</category>
<category>
<name>metaltop_angle</name>
<description>ACUTE : non 45 degree angle metaltop</description>
<categories>
</categories>
</category>
<category>
<name>pad_OFFGRID</name>
<description>OFFGRID : OFFGRID vertex on pad</description>
<categories>
</categories>
</category>
<category>
<name>pad_angle</name>
<description>ACUTE : non 45 degree angle pad</description>
<categories>
</categories>
</category>
<category>
<name>resistor_OFFGRID</name>
<description>OFFGRID : OFFGRID vertex on resistor</description>
<categories>
</categories>
</category>
<category>
<name>resistor_angle</name>
<description>ACUTE : non 45 degree angle resistor</description>
<categories>
</categories>
</category>
<category>
<name>fhres_OFFGRID</name>
<description>OFFGRID : OFFGRID vertex on fhres</description>
<categories>
</categories>
</category>
<category>
<name>fhres_angle</name>
<description>ACUTE : non 45 degree angle fhres</description>
<categories>
</categories>
</category>
<category>
<name>fusetop_OFFGRID</name>
<description>OFFGRID : OFFGRID vertex on fusetop</description>
<categories>
</categories>
</category>
<category>
<name>fusetop_angle</name>
<description>ACUTE : non 45 degree angle fusetop</description>
<categories>
</categories>
</category>
<category>
<name>fusewindow_d_OFFGRID</name>
<description>OFFGRID : OFFGRID vertex on fusewindow_d</description>
<categories>
</categories>
</category>
<category>
<name>fusewindow_d_angle</name>
<description>ACUTE : non 45 degree angle fusewindow_d</description>
<categories>
</categories>
</category>
<category>
<name>polyfuse_OFFGRID</name>
<description>OFFGRID : OFFGRID vertex on polyfuse</description>
<categories>
</categories>
</category>
<category>
<name>polyfuse_angle</name>
<description>ACUTE : non 45 degree angle polyfuse</description>
<categories>
</categories>
</category>
<category>
<name>mvsd_OFFGRID</name>
<description>OFFGRID : OFFGRID vertex on mvsd</description>
<categories>
</categories>
</category>
<category>
<name>mvsd_angle</name>
<description>ACUTE : non 45 degree angle mvsd</description>
<categories>
</categories>
</category>
<category>
<name>mvpsd_OFFGRID</name>
<description>OFFGRID : OFFGRID vertex on mvpsd</description>
<categories>
</categories>
</category>
<category>
<name>mvpsd_angle</name>
<description>ACUTE : non 45 degree angle mvpsd</description>
<categories>
</categories>
</category>
<category>
<name>nat_OFFGRID</name>
<description>OFFGRID : OFFGRID vertex on nat</description>
<categories>
</categories>
</category>
<category>
<name>nat_angle</name>
<description>ACUTE : non 45 degree angle nat</description>
<categories>
</categories>
</category>
<category>
<name>comp_dummy_OFFGRID</name>
<description>OFFGRID : OFFGRID vertex on comp_dummy</description>
<categories>
</categories>
</category>
<category>
<name>comp_dummy_angle</name>
<description>ACUTE : non 45 degree angle comp_dummy</description>
<categories>
</categories>
</category>
<category>
<name>poly2_dummy_OFFGRID</name>
<description>OFFGRID : OFFGRID vertex on poly2_dummy</description>
<categories>
</categories>
</category>
<category>
<name>poly2_dummy_angle</name>
<description>ACUTE : non 45 degree angle poly2_dummy</description>
<categories>
</categories>
</category>
<category>
<name>metal1_dummy_OFFGRID</name>
<description>OFFGRID : OFFGRID vertex on metal1_dummy</description>
<categories>
</categories>
</category>
<category>
<name>metal1_dummy_angle</name>
<description>ACUTE : non 45 degree angle metal1_dummy</description>
<categories>
</categories>
</category>
<category>
<name>metal2_dummy_OFFGRID</name>
<description>OFFGRID : OFFGRID vertex on metal2_dummy</description>
<categories>
</categories>
</category>
<category>
<name>metal2_dummy_angle</name>
<description>ACUTE : non 45 degree angle metal2_dummy</description>
<categories>
</categories>
</category>
<category>
<name>metal3_dummy_OFFGRID</name>
<description>OFFGRID : OFFGRID vertex on metal3_dummy</description>
<categories>
</categories>
</category>
<category>
<name>metal3_dummy_angle</name>
<description>ACUTE : non 45 degree angle metal3_dummy</description>
<categories>
</categories>
</category>
<category>
<name>metal4_dummy_OFFGRID</name>
<description>OFFGRID : OFFGRID vertex on metal4_dummy</description>
<categories>
</categories>
</category>
<category>
<name>metal4_dummy_angle</name>
<description>ACUTE : non 45 degree angle metal4_dummy</description>
<categories>
</categories>
</category>
<category>
<name>metal5_dummy_OFFGRID</name>
<description>OFFGRID : OFFGRID vertex on metal5_dummy</description>
<categories>
</categories>
</category>
<category>
<name>metal5_dummy_angle</name>
<description>ACUTE : non 45 degree angle metal5_dummy</description>
<categories>
</categories>
</category>
<category>
<name>metaltop_dummy_OFFGRID</name>
<description>OFFGRID : OFFGRID vertex on metaltop_dummy</description>
<categories>
</categories>
</category>
<category>
<name>metaltop_dummy_angle</name>
<description>ACUTE : non 45 degree angle metaltop_dummy</description>
<categories>
</categories>
</category>
<category>
<name>comp_label_OFFGRID</name>
<description>OFFGRID : OFFGRID vertex on comp_label</description>
<categories>
</categories>
</category>
<category>
<name>comp_label_angle</name>
<description>ACUTE : non 45 degree angle comp_label</description>
<categories>
</categories>
</category>
<category>
<name>poly2_label_OFFGRID</name>
<description>OFFGRID : OFFGRID vertex on poly2_label</description>
<categories>
</categories>
</category>
<category>
<name>poly2_label_angle</name>
<description>ACUTE : non 45 degree angle poly2_label</description>
<categories>
</categories>
</category>
<category>
<name>metal1_label_OFFGRID</name>
<description>OFFGRID : OFFGRID vertex on metal1_label</description>
<categories>
</categories>
</category>
<category>
<name>metal1_label_angle</name>
<description>ACUTE : non 45 degree angle metal1_label</description>
<categories>
</categories>
</category>
<category>
<name>metal2_label_OFFGRID</name>
<description>OFFGRID : OFFGRID vertex on metal2_label</description>
<categories>
</categories>
</category>
<category>
<name>metal2_label_angle</name>
<description>ACUTE : non 45 degree angle metal2_label</description>
<categories>
</categories>
</category>
<category>
<name>metal3_label_OFFGRID</name>
<description>OFFGRID : OFFGRID vertex on metal3_label</description>
<categories>
</categories>
</category>
<category>
<name>metal3_label_angle</name>
<description>ACUTE : non 45 degree angle metal3_label</description>
<categories>
</categories>
</category>
<category>
<name>metal4_label_OFFGRID</name>
<description>OFFGRID : OFFGRID vertex on metal4_label</description>
<categories>
</categories>
</category>
<category>
<name>metal4_label_angle</name>
<description>ACUTE : non 45 degree angle metal4_label</description>
<categories>
</categories>
</category>
<category>
<name>metal5_label_OFFGRID</name>
<description>OFFGRID : OFFGRID vertex on metal5_label</description>
<categories>
</categories>
</category>
<category>
<name>metal5_label_angle</name>
<description>ACUTE : non 45 degree angle metal5_label</description>
<categories>
</categories>
</category>
<category>
<name>metaltop_label_OFFGRID</name>
<description>OFFGRID : OFFGRID vertex on metaltop_label</description>
<categories>
</categories>
</category>
<category>
<name>metaltop_label_angle</name>
<description>ACUTE : non 45 degree angle metaltop_label</description>
<categories>
</categories>
</category>
<category>
<name>metal1_slot_OFFGRID</name>
<description>OFFGRID : OFFGRID vertex on metal1_slot</description>
<categories>
</categories>
</category>
<category>
<name>metal1_slot_angle</name>
<description>ACUTE : non 45 degree angle metal1_slot</description>
<categories>
</categories>
</category>
<category>
<name>metal2_slot_OFFGRID</name>
<description>OFFGRID : OFFGRID vertex on metal2_slot</description>
<categories>
</categories>
</category>
<category>
<name>metal2_slot_angle</name>
<description>ACUTE : non 45 degree angle metal2_slot</description>
<categories>
</categories>
</category>
<category>
<name>metal3_slot_OFFGRID</name>
<description>OFFGRID : OFFGRID vertex on metal3_slot</description>
<categories>
</categories>
</category>
<category>
<name>metal3_slot_angle</name>
<description>ACUTE : non 45 degree angle metal3_slot</description>
<categories>
</categories>
</category>
<category>
<name>metal4_slot_OFFGRID</name>
<description>OFFGRID : OFFGRID vertex on metal4_slot</description>
<categories>
</categories>
</category>
<category>
<name>metal4_slot_angle</name>
<description>ACUTE : non 45 degree angle metal4_slot</description>
<categories>
</categories>
</category>
<category>
<name>metal5_slot_OFFGRID</name>
<description>OFFGRID : OFFGRID vertex on metal5_slot</description>
<categories>
</categories>
</category>
<category>
<name>metal5_slot_angle</name>
<description>ACUTE : non 45 degree angle metal5_slot</description>
<categories>
</categories>
</category>
<category>
<name>metaltop_slot_OFFGRID</name>
<description>OFFGRID : OFFGRID vertex on metaltop_slot</description>
<categories>
</categories>
</category>
<category>
<name>metaltop_slot_angle</name>
<description>ACUTE : non 45 degree angle metaltop_slot</description>
<categories>
</categories>
</category>
<category>
<name>ubmpperi_OFFGRID</name>
<description>OFFGRID : OFFGRID vertex on ubmpperi</description>
<categories>
</categories>
</category>
<category>
<name>ubmpperi_angle</name>
<description>ACUTE : non 45 degree angle ubmpperi</description>
<categories>
</categories>
</category>
<category>
<name>ubmparray_OFFGRID</name>
<description>OFFGRID : OFFGRID vertex on ubmparray</description>
<categories>
</categories>
</category>
<category>
<name>ubmparray_angle</name>
<description>ACUTE : non 45 degree angle ubmparray</description>
<categories>
</categories>
</category>
<category>
<name>ubmeplate_OFFGRID</name>
<description>OFFGRID : OFFGRID vertex on ubmeplate</description>
<categories>
</categories>
</category>
<category>
<name>ubmeplate_angle</name>
<description>ACUTE : non 45 degree angle ubmeplate</description>
<categories>
</categories>
</category>
<category>
<name>schottky_diode_OFFGRID</name>
<description>OFFGRID : OFFGRID vertex on schottky_diode</description>
<categories>
</categories>
</category>
<category>
<name>schottky_diode_angle</name>
<description>ACUTE : non 45 degree angle schottky_diode</description>
<categories>
</categories>
</category>
<category>
<name>zener_OFFGRID</name>
<description>OFFGRID : OFFGRID vertex on zener</description>
<categories>
</categories>
</category>
<category>
<name>zener_angle</name>
<description>ACUTE : non 45 degree angle zener</description>
<categories>
</categories>
</category>
<category>
<name>res_mk_OFFGRID</name>
<description>OFFGRID : OFFGRID vertex on res_mk</description>
<categories>
</categories>
</category>
<category>
<name>res_mk_angle</name>
<description>ACUTE : non 45 degree angle res_mk</description>
<categories>
</categories>
</category>
<category>
<name>opc_drc_OFFGRID</name>
<description>OFFGRID : OFFGRID vertex on opc_drc</description>
<categories>
</categories>
</category>
<category>
<name>opc_drc_angle</name>
<description>ACUTE : non 45 degree angle opc_drc</description>
<categories>
</categories>
</category>
<category>
<name>ndmy_OFFGRID</name>
<description>OFFGRID : OFFGRID vertex on ndmy</description>
<categories>
</categories>
</category>
<category>
<name>ndmy_angle</name>
<description>ACUTE : non 45 degree angle ndmy</description>
<categories>
</categories>
</category>
<category>
<name>pmndmy_OFFGRID</name>
<description>OFFGRID : OFFGRID vertex on pmndmy</description>
<categories>
</categories>
</category>
<category>
<name>pmndmy_angle</name>
<description>ACUTE : non 45 degree angle pmndmy</description>
<categories>
</categories>
</category>
<category>
<name>v5_xtor_OFFGRID</name>
<description>OFFGRID : OFFGRID vertex on v5_xtor</description>
<categories>
</categories>
</category>
<category>
<name>v5_xtor_angle</name>
<description>ACUTE : non 45 degree angle v5_xtor</description>
<categories>
</categories>
</category>
<category>
<name>cap_mk_OFFGRID</name>
<description>OFFGRID : OFFGRID vertex on cap_mk</description>
<categories>
</categories>
</category>
<category>
<name>cap_mk_angle</name>
<description>ACUTE : non 45 degree angle cap_mk</description>
<categories>
</categories>
</category>
<category>
<name>mos_cap_mk_OFFGRID</name>
<description>OFFGRID : OFFGRID vertex on mos_cap_mk</description>
<categories>
</categories>
</category>
<category>
<name>mos_cap_mk_angle</name>
<description>ACUTE : non 45 degree angle mos_cap_mk</description>
<categories>
</categories>
</category>
<category>
<name>ind_mk_OFFGRID</name>
<description>OFFGRID : OFFGRID vertex on ind_mk</description>
<categories>
</categories>
</category>
<category>
<name>ind_mk_angle</name>
<description>ACUTE : non 45 degree angle ind_mk</description>
<categories>
</categories>
</category>
<category>
<name>diode_mk_OFFGRID</name>
<description>OFFGRID : OFFGRID vertex on diode_mk</description>
<categories>
</categories>
</category>
<category>
<name>diode_mk_angle</name>
<description>ACUTE : non 45 degree angle diode_mk</description>
<categories>
</categories>
</category>
<category>
<name>drc_bjt_OFFGRID</name>
<description>OFFGRID : OFFGRID vertex on drc_bjt</description>
<categories>
</categories>
</category>
<category>
<name>drc_bjt_angle</name>
<description>ACUTE : non 45 degree angle drc_bjt</description>
<categories>
</categories>
</category>
<category>
<name>lvs_bjt_OFFGRID</name>
<description>OFFGRID : OFFGRID vertex on lvs_bjt</description>
<categories>
</categories>
</category>
<category>
<name>lvs_bjt_angle</name>
<description>ACUTE : non 45 degree angle lvs_bjt</description>
<categories>
</categories>
</category>
<category>
<name>mim_l_mk_OFFGRID</name>
<description>OFFGRID : OFFGRID vertex on mim_l_mk</description>
<categories>
</categories>
</category>
<category>
<name>mim_l_mk_angle</name>
<description>ACUTE : non 45 degree angle mim_l_mk</description>
<categories>
</categories>
</category>
<category>
<name>latchup_mk_OFFGRID</name>
<description>OFFGRID : OFFGRID vertex on latchup_mk</description>
<categories>
</categories>
</category>
<category>
<name>latchup_mk_angle</name>
<description>ACUTE : non 45 degree angle latchup_mk</description>
<categories>
</categories>
</category>
<category>
<name>guard_ring_mk_OFFGRID</name>
<description>OFFGRID : OFFGRID vertex on guard_ring_mk</description>
<categories>
</categories>
</category>
<category>
<name>guard_ring_mk_angle</name>
<description>ACUTE : non 45 degree angle guard_ring_mk</description>
<categories>
</categories>
</category>
<category>
<name>otp_mk_OFFGRID</name>
<description>OFFGRID : OFFGRID vertex on otp_mk</description>
<categories>
</categories>
</category>
<category>
<name>otp_mk_angle</name>
<description>ACUTE : non 45 degree angle otp_mk</description>
<categories>
</categories>
</category>
<category>
<name>mtpmark_OFFGRID</name>
<description>OFFGRID : OFFGRID vertex on mtpmark</description>
<categories>
</categories>
</category>
<category>
<name>mtpmark_angle</name>
<description>ACUTE : non 45 degree angle mtpmark</description>
<categories>
</categories>
</category>
<category>
<name>neo_ee_mk_OFFGRID</name>
<description>OFFGRID : OFFGRID vertex on neo_ee_mk</description>
<categories>
</categories>
</category>
<category>
<name>neo_ee_mk_angle</name>
<description>ACUTE : non 45 degree angle neo_ee_mk</description>
<categories>
</categories>
</category>
<category>
<name>sramcore_OFFGRID</name>
<description>OFFGRID : OFFGRID vertex on sramcore</description>
<categories>
</categories>
</category>
<category>
<name>sramcore_angle</name>
<description>ACUTE : non 45 degree angle sramcore</description>
<categories>
</categories>
</category>
<category>
<name>lvs_rf_OFFGRID</name>
<description>OFFGRID : OFFGRID vertex on lvs_rf</description>
<categories>
</categories>
</category>
<category>
<name>lvs_rf_angle</name>
<description>ACUTE : non 45 degree angle lvs_rf</description>
<categories>
</categories>
</category>
<category>
<name>lvs_drain_OFFGRID</name>
<description>OFFGRID : OFFGRID vertex on lvs_drain</description>
<categories>
</categories>
</category>
<category>
<name>lvs_drain_angle</name>
<description>ACUTE : non 45 degree angle lvs_drain</description>
<categories>
</categories>
</category>
<category>
<name>hvpolyrs_OFFGRID</name>
<description>OFFGRID : OFFGRID vertex on hvpolyrs</description>
<categories>
</categories>
</category>
<category>
<name>hvpolyrs_angle</name>
<description>ACUTE : non 45 degree angle hvpolyrs</description>
<categories>
</categories>
</category>
<category>
<name>lvs_io_OFFGRID</name>
<description>OFFGRID : OFFGRID vertex on lvs_io</description>
<categories>
</categories>
</category>
<category>
<name>lvs_io_angle</name>
<description>ACUTE : non 45 degree angle lvs_io</description>
<categories>
</categories>
</category>
<category>
<name>probe_mk_OFFGRID</name>
<description>OFFGRID : OFFGRID vertex on probe_mk</description>
<categories>
</categories>
</category>
<category>
<name>probe_mk_angle</name>
<description>ACUTE : non 45 degree angle probe_mk</description>
<categories>
</categories>
</category>
<category>
<name>esd_mk_OFFGRID</name>
<description>OFFGRID : OFFGRID vertex on esd_mk</description>
<categories>
</categories>
</category>
<category>
<name>esd_mk_angle</name>
<description>ACUTE : non 45 degree angle esd_mk</description>
<categories>
</categories>
</category>
<category>
<name>lvs_source_OFFGRID</name>
<description>OFFGRID : OFFGRID vertex on lvs_source</description>
<categories>
</categories>
</category>
<category>
<name>lvs_source_angle</name>
<description>ACUTE : non 45 degree angle lvs_source</description>
<categories>
</categories>
</category>
<category>
<name>well_diode_mk_OFFGRID</name>
<description>OFFGRID : OFFGRID vertex on well_diode_mk</description>
<categories>
</categories>
</category>
<category>
<name>well_diode_mk_angle</name>
<description>ACUTE : non 45 degree angle well_diode_mk</description>
<categories>
</categories>
</category>
<category>
<name>ldmos_xtor_OFFGRID</name>
<description>OFFGRID : OFFGRID vertex on ldmos_xtor</description>
<categories>
</categories>
</category>
<category>
<name>ldmos_xtor_angle</name>
<description>ACUTE : non 45 degree angle ldmos_xtor</description>
<categories>
</categories>
</category>
<category>
<name>plfuse_OFFGRID</name>
<description>OFFGRID : OFFGRID vertex on plfuse</description>
<categories>
</categories>
</category>
<category>
<name>plfuse_angle</name>
<description>ACUTE : non 45 degree angle plfuse</description>
<categories>
</categories>
</category>
<category>
<name>efuse_mk_OFFGRID</name>
<description>OFFGRID : OFFGRID vertex on efuse_mk</description>
<categories>
</categories>
</category>
<category>
<name>efuse_mk_angle</name>
<description>ACUTE : non 45 degree angle efuse_mk</description>
<categories>
</categories>
</category>
<category>
<name>mcell_feol_mk_OFFGRID</name>
<description>OFFGRID : OFFGRID vertex on mcell_feol_mk</description>
<categories>
</categories>
</category>
<category>
<name>mcell_feol_mk_angle</name>
<description>ACUTE : non 45 degree angle mcell_feol_mk</description>
<categories>
</categories>
</category>
<category>
<name>ymtp_mk_OFFGRID</name>
<description>OFFGRID : OFFGRID vertex on ymtp_mk</description>
<categories>
</categories>
</category>
<category>
<name>ymtp_mk_angle</name>
<description>ACUTE : non 45 degree angle ymtp_mk</description>
<categories>
</categories>
</category>
<category>
<name>dev_wf_mk_OFFGRID</name>
<description>OFFGRID : OFFGRID vertex on dev_wf_mk</description>
<categories>
</categories>
</category>
<category>
<name>dev_wf_mk_angle</name>
<description>ACUTE : non 45 degree angle dev_wf_mk</description>
<categories>
</categories>
</category>
<category>
<name>metal1_blk_OFFGRID</name>
<description>OFFGRID : OFFGRID vertex on metal1_blk</description>
<categories>
</categories>
</category>
<category>
<name>metal1_blk_angle</name>
<description>ACUTE : non 45 degree angle metal1_blk</description>
<categories>
</categories>
</category>
<category>
<name>metal2_blk_OFFGRID</name>
<description>OFFGRID : OFFGRID vertex on metal2_blk</description>
<categories>
</categories>
</category>
<category>
<name>metal2_blk_angle</name>
<description>ACUTE : non 45 degree angle metal2_blk</description>
<categories>
</categories>
</category>
<category>
<name>metal3_blk_OFFGRID</name>
<description>OFFGRID : OFFGRID vertex on metal3_blk</description>
<categories>
</categories>
</category>
<category>
<name>metal3_blk_angle</name>
<description>ACUTE : non 45 degree angle metal3_blk</description>
<categories>
</categories>
</category>
<category>
<name>metal4_blk_OFFGRID</name>
<description>OFFGRID : OFFGRID vertex on metal4_blk</description>
<categories>
</categories>
</category>
<category>
<name>metal4_blk_angle</name>
<description>ACUTE : non 45 degree angle metal4_blk</description>
<categories>
</categories>
</category>
<category>
<name>metal5_blk_OFFGRID</name>
<description>OFFGRID : OFFGRID vertex on metal5_blk</description>
<categories>
</categories>
</category>
<category>
<name>metal5_blk_angle</name>
<description>ACUTE : non 45 degree angle metal5_blk</description>
<categories>
</categories>
</category>
<category>
<name>metalt_blk_OFFGRID</name>
<description>OFFGRID : OFFGRID vertex on metalt_blk</description>
<categories>
</categories>
</category>
<category>
<name>metalt_blk_angle</name>
<description>ACUTE : non 45 degree angle metalt_blk</description>
<categories>
</categories>
</category>
<category>
<name>pr_bndry_OFFGRID</name>
<description>OFFGRID : OFFGRID vertex on pr_bndry</description>
<categories>
</categories>
</category>
<category>
<name>pr_bndry_angle</name>
<description>ACUTE : non 45 degree angle pr_bndry</description>
<categories>
</categories>
</category>
<category>
<name>mdiode_OFFGRID</name>
<description>OFFGRID : OFFGRID vertex on mdiode</description>
<categories>
</categories>
</category>
<category>
<name>mdiode_angle</name>
<description>ACUTE : non 45 degree angle mdiode</description>
<categories>
</categories>
</category>
<category>
<name>metal1_res_OFFGRID</name>
<description>OFFGRID : OFFGRID vertex on metal1_res</description>
<categories>
</categories>
</category>
<category>
<name>metal1_res_angle</name>
<description>ACUTE : non 45 degree angle metal1_res</description>
<categories>
</categories>
</category>
<category>
<name>metal2_res_OFFGRID</name>
<description>OFFGRID : OFFGRID vertex on metal2_res</description>
<categories>
</categories>
</category>
<category>
<name>metal2_res_angle</name>
<description>ACUTE : non 45 degree angle metal2_res</description>
<categories>
</categories>
</category>
<category>
<name>metal3_res_OFFGRID</name>
<description>OFFGRID : OFFGRID vertex on metal3_res</description>
<categories>
</categories>
</category>
<category>
<name>metal3_res_angle</name>
<description>ACUTE : non 45 degree angle metal3_res</description>
<categories>
</categories>
</category>
<category>
<name>metal4_res_OFFGRID</name>
<description>OFFGRID : OFFGRID vertex on metal4_res</description>
<categories>
</categories>
</category>
<category>
<name>metal4_res_angle</name>
<description>ACUTE : non 45 degree angle metal4_res</description>
<categories>
</categories>
</category>
<category>
<name>metal5_res_OFFGRID</name>
<description>OFFGRID : OFFGRID vertex on metal5_res</description>
<categories>
</categories>
</category>
<category>
<name>metal5_res_angle</name>
<description>ACUTE : non 45 degree angle metal5_res</description>
<categories>
</categories>
</category>
<category>
<name>metal6_res_OFFGRID</name>
<description>OFFGRID : OFFGRID vertex on metal6_res</description>
<categories>
</categories>
</category>
<category>
<name>metal6_res_angle</name>
<description>ACUTE : non 45 degree angle metal6_res</description>
<categories>
</categories>
</category>
<category>
<name>border_OFFGRID</name>
<description>OFFGRID : OFFGRID vertex on border</description>
<categories>
</categories>
</category>
<category>
<name>border_angle</name>
<description>ACUTE : non 45 degree angle border</description>
<categories>
</categories>
</category>
</categories>
<cells>
<cell>
<name>user_project_wrapper</name>
<variant/>
<references>
</references>
</cell>
</cells>
<items>
</items>
</report-database>