2022-12-04 20:12:25 - [INFO] - {{Project Git Info}} Repository: https://github.com/gatecat/one_hot_fpga_gf180.git | Branch: main | Commit: bf540bcdad01a15ea399a3befdc74785cf367e59
2022-12-04 20:12:25 - [INFO] - {{EXTRACTING FILES}} Extracting compressed files in: onehot_fabulous_fpga_on_gf180
2022-12-04 20:12:25 - [INFO] - {{Project Type Info}} digital
2022-12-04 20:12:25 - [INFO] - {{Project GDS Info}} user_project_wrapper: f5097859db9d723bf127e622d2cd5c813b4a5825
2022-12-04 20:12:25 - [INFO] - {{Tools Info}} KLayout: v0.27.12 | Magic: v8.3.340
2022-12-04 20:12:25 - [INFO] - {{PDKs Info}} GF180MCUC: a897aa30369d3bcec87d9d50ce9b01f320f854ef | Open PDKs: 120b0bd69c745825a0b8b76f364043a1cd08bb6a
2022-12-04 20:12:25 - [INFO] - {{START}} Precheck Started, the full log 'precheck.log' will be located in 'onehot_fabulous_fpga_on_gf180/jobs/mpw_precheck/12e8e678-0573-4d23-b8b7-fcdc785777a8/logs'
2022-12-04 20:12:25 - [INFO] - {{PRECHECK SEQUENCE}} Precheck will run the following checks: [License, GPIO-Defines, XOR, Klayout FEOL, Klayout BEOL, Klayout Offgrid, Klayout Metal Minimum Clear Area Density]
2022-12-04 20:12:25 - [INFO] - {{STEP UPDATE}} Executing Check 1 of 7: License
2022-12-04 20:12:26 - [INFO] - An approved LICENSE (Apache-2.0) was found in onehot_fabulous_fpga_on_gf180.
2022-12-04 20:12:26 - [INFO] - {{MAIN LICENSE CHECK PASSED}} An approved LICENSE was found in project root.
2022-12-04 20:12:27 - [INFO] - An approved LICENSE (Apache-2.0) was found in onehot_fabulous_fpga_on_gf180.
2022-12-04 20:12:27 - [INFO] - {{SUBMODULES LICENSE CHECK PASSED}} No prohibited LICENSE file(s) was found in project submodules
2022-12-04 20:12:27 - [WARNING] - {{SPDX COMPLIANCE CHECK FAILED}} Found 20 non-compliant file(s) with the SPDX Standard.
2022-12-04 20:12:27 - [INFO] - SPDX COMPLIANCE: NON-COMPLIANT FILE(S) PREVIEW: ['onehot_fabulous_fpga_on_gf180/lib/user_proj_example.lib', 'onehot_fabulous_fpga_on_gf180/lib/user_project_wrapper.lib', 'onehot_fabulous_fpga_on_gf180/openlane/user_project_wrapper/macros/verilog/E_IO_tile.v', 'onehot_fabulous_fpga_on_gf180/openlane/user_project_wrapper/macros/verilog/LUT4AB_tile.v', 'onehot_fabulous_fpga_on_gf180/openlane/user_project_wrapper/macros/verilog/N_term_single_tile.v', 'onehot_fabulous_fpga_on_gf180/openlane/user_project_wrapper/macros/verilog/S_term_single_tile.v', 'onehot_fabulous_fpga_on_gf180/openlane/user_project_wrapper/macros/verilog/W_IO_tile.v', 'onehot_fabulous_fpga_on_gf180/sdc/user_proj_example.sdc', 'onehot_fabulous_fpga_on_gf180/sdc/user_project_wrapper.sdc', 'onehot_fabulous_fpga_on_gf180/sdf/user_proj_example.sdf', 'onehot_fabulous_fpga_on_gf180/sdf/user_project_wrapper.sdf', 'onehot_fabulous_fpga_on_gf180/sdf/multicorner/nom/user_project_wrapper.ff.sdf', 'onehot_fabulous_fpga_on_gf180/sdf/multicorner/nom/user_project_wrapper.ss.sdf', 'onehot_fabulous_fpga_on_gf180/sdf/multicorner/nom/user_project_wrapper.tt.sdf', 'onehot_fabulous_fpga_on_gf180/spef/user_proj_example.spef']
2022-12-04 20:12:27 - [INFO] - For the full SPDX compliance report check: onehot_fabulous_fpga_on_gf180/jobs/mpw_precheck/12e8e678-0573-4d23-b8b7-fcdc785777a8/logs/spdx_compliance_report.log
2022-12-04 20:12:27 - [INFO] - {{STEP UPDATE}} Executing Check 2 of 7: GPIO-Defines
2022-12-04 20:12:27 - [INFO] - GPIO-DEFINES: Checking verilog/rtl/user_defines.v, parsing files: ['/opt/checks/gpio_defines_check/verilog_assets/gpio_modes_base.v', 'onehot_fabulous_fpga_on_gf180/verilog/rtl/user_defines.v', '/opt/checks/gpio_defines_check/verilog_assets/gpio_modes_observe.v']
2022-12-04 20:12:28 - [INFO] - GPIO-DEFINES report path: onehot_fabulous_fpga_on_gf180/jobs/mpw_precheck/12e8e678-0573-4d23-b8b7-fcdc785777a8/outputs/reports/gpio_defines.report
2022-12-04 20:12:28 - [INFO] - {{GPIO-DEFINES CHECK PASSED}} The user verilog/rtl/user_defines.v is valid.
2022-12-04 20:12:28 - [INFO] - {{STEP UPDATE}} Executing Check 3 of 7: XOR
2022-12-04 20:13:07 - [INFO] - {{XOR CHECK UPDATE}} Total XOR differences: 0, for more details view onehot_fabulous_fpga_on_gf180/jobs/mpw_precheck/12e8e678-0573-4d23-b8b7-fcdc785777a8/outputs/user_project_wrapper.xor.gds
2022-12-04 20:13:07 - [INFO] - {{XOR CHECK PASSED}} The GDS file has no XOR violations.
2022-12-04 20:13:07 - [INFO] - {{STEP UPDATE}} Executing Check 4 of 7: Klayout FEOL
2022-12-04 20:13:07 - [INFO] - in CUSTOM klayout_gds_drc_check
2022-12-04 20:13:07 - [INFO] - run: klayout -b -r /opt/checks/tech-files/gf180mcuC_mr.drc -rd input=onehot_fabulous_fpga_on_gf180/gds/user_project_wrapper.gds -rd topcell=user_project_wrapper -rd report=onehot_fabulous_fpga_on_gf180/jobs/mpw_precheck/12e8e678-0573-4d23-b8b7-fcdc785777a8/outputs/reports/klayout_feol_check.xml -rd feol=true -rd metal_top=9K -rd mim_option=B -rd metal_level=5LM -rd conn_drc=true >& onehot_fabulous_fpga_on_gf180/jobs/mpw_precheck/12e8e678-0573-4d23-b8b7-fcdc785777a8/logs/klayout_feol_check.log
2022-12-04 20:57:54 - [ERROR] - ERROR klayout_feol FAILED, stat=-9, see onehot_fabulous_fpga_on_gf180/jobs/mpw_precheck/12e8e678-0573-4d23-b8b7-fcdc785777a8/logs/klayout_feol_check.log
2022-12-04 20:57:54 - [WARNING] - {{Klayout FEOL CHECK FAILED}} The GDS file, user_project_wrapper.gds, has DRC violations.
2022-12-04 20:57:54 - [INFO] - {{STEP UPDATE}} Executing Check 5 of 7: Klayout BEOL
2022-12-04 20:57:54 - [INFO] - in CUSTOM klayout_gds_drc_check
2022-12-04 20:57:54 - [INFO] - run: klayout -b -r /opt/checks/tech-files/gf180mcuC_mr.drc -rd input=onehot_fabulous_fpga_on_gf180/gds/user_project_wrapper.gds -rd topcell=user_project_wrapper -rd report=onehot_fabulous_fpga_on_gf180/jobs/mpw_precheck/12e8e678-0573-4d23-b8b7-fcdc785777a8/outputs/reports/klayout_beol_check.xml -rd beol=true -rd metal_top=9K -rd mim_option=B -rd metal_level=5LM -rd conn_drc=true >& onehot_fabulous_fpga_on_gf180/jobs/mpw_precheck/12e8e678-0573-4d23-b8b7-fcdc785777a8/logs/klayout_beol_check.log
2022-12-04 23:05:44 - [INFO] - No DRC Violations found
2022-12-04 23:05:44 - [INFO] - {{Klayout BEOL CHECK PASSED}} The GDS file, user_project_wrapper.gds, has no DRC violations.
2022-12-04 23:05:44 - [INFO] - {{STEP UPDATE}} Executing Check 6 of 7: Klayout Offgrid
2022-12-04 23:05:44 - [INFO] - in CUSTOM klayout_gds_drc_check
2022-12-04 23:05:44 - [INFO] - run: klayout -b -r /opt/checks/tech-files/gf180mcuC_mr.drc -rd input=onehot_fabulous_fpga_on_gf180/gds/user_project_wrapper.gds -rd topcell=user_project_wrapper -rd report=onehot_fabulous_fpga_on_gf180/jobs/mpw_precheck/12e8e678-0573-4d23-b8b7-fcdc785777a8/outputs/reports/klayout_offgrid_check.xml -rd offgrid=true -rd metal_top=9K -rd mim_option=B -rd metal_level=5LM -rd conn_drc=true >& onehot_fabulous_fpga_on_gf180/jobs/mpw_precheck/12e8e678-0573-4d23-b8b7-fcdc785777a8/logs/klayout_offgrid_check.log
2022-12-05 00:50:28 - [INFO] - No DRC Violations found
2022-12-05 00:50:28 - [INFO] - {{Klayout Offgrid CHECK PASSED}} The GDS file, user_project_wrapper.gds, has no DRC violations.
2022-12-05 00:50:28 - [INFO] - {{STEP UPDATE}} Executing Check 7 of 7: Klayout Metal Minimum Clear Area Density
2022-12-05 00:50:28 - [INFO] - in CUSTOM klayout_gds_drc_check
2022-12-05 00:50:28 - [INFO] - run: klayout -b -r /opt/checks/drc_checks/klayout/gf180mcu_density.lydrc -rd input=onehot_fabulous_fpga_on_gf180/gds/user_project_wrapper.gds -rd topcell=user_project_wrapper -rd report=onehot_fabulous_fpga_on_gf180/jobs/mpw_precheck/12e8e678-0573-4d23-b8b7-fcdc785777a8/outputs/reports/klayout_met_min_ca_density_check.xml >& onehot_fabulous_fpga_on_gf180/jobs/mpw_precheck/12e8e678-0573-4d23-b8b7-fcdc785777a8/logs/klayout_met_min_ca_density_check.log
2022-12-05 00:50:30 - [INFO] - No DRC Violations found
2022-12-05 00:50:30 - [INFO] - {{Klayout Metal Minimum Clear Area Density CHECK PASSED}} The GDS file, user_project_wrapper.gds, has no DRC violations.
2022-12-05 00:50:30 - [INFO] - {{FINISH}} Executing Finished, the full log 'precheck.log' can be found in 'onehot_fabulous_fpga_on_gf180/jobs/mpw_precheck/12e8e678-0573-4d23-b8b7-fcdc785777a8/logs'
2022-12-05 00:50:30 - [CRITICAL] - {{FAILURE}} 1 Check(s) Failed: ['Klayout FEOL'] !!!