baseline
Signed-off-by: gatecat <gatecat@ds0.me>
diff --git a/do_copy.py b/do_copy.py
new file mode 100644
index 0000000..bd2fd7a
--- /dev/null
+++ b/do_copy.py
@@ -0,0 +1,67 @@
+# SPDX-FileCopyrightText: 2022 Myrtle Shah
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# SPDX-License-Identifier: Apache-2.0
+
+import sys, os, shutil
+import pathlib
+
+spdx_header = """// SPDX-FileCopyrightText:
+// 2022 Nguyen Dao
+// 2022 Myrtle Shah
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+//
+// SPDX-License-Identifier: Apache-2.0
+"""
+
+def copy_verilog(src):
+ with open(src, "r") as input_f:
+ with open(f"./verilog/rtl/{os.path.basename(src)}", "w") as output_f:
+ print(spdx_header, file=output_f)
+ output_f.write(input_f.read())
+
+def main():
+ fab_root = f"{os.environ['HOME']}/fabulous-onehot"
+ build_dir = f"{os.environ['HOME']}/test/build/gf180_onehot"
+
+ fab_verilog = ["fabric.v", "eFPGA_top.v", "models_pack.v"]
+
+ for v in fab_verilog:
+ copy_verilog(f"{fab_root}/fabric_generator/verilog_output/{v}")
+ copy_verilog(f"{fab_root}/fabric_generator/fabulous_top_wrapper_temp/wrapper_gf180.v")
+
+ pathlib.Path("openlane/user_project_wrapper/macros/lef").mkdir(parents=True, exist_ok=True)
+ pathlib.Path("openlane/user_project_wrapper/macros/gds").mkdir(parents=True, exist_ok=True)
+ pathlib.Path("openlane/user_project_wrapper/macros/verilog").mkdir(parents=True, exist_ok=True)
+
+ for tile in os.listdir(build_dir):
+ if not os.path.isdir(f"{build_dir}/{tile}"):
+ continue
+ shutil.copy(f"{build_dir}/{tile}/runs/build_tile/results/final/lef/{tile}.lef", "openlane/user_project_wrapper/macros/lef")
+ shutil.copy(f"{build_dir}/{tile}/runs/build_tile/results/final/gds/{tile}.gds", "openlane/user_project_wrapper/macros/gds")
+ shutil.copy(f"{build_dir}/{tile}/src/{tile}_tile.v", "openlane/user_project_wrapper/macros/verilog")
+
+if __name__ == '__main__':
+ main()
diff --git a/openlane/user_project_wrapper/config.tcl b/openlane/user_project_wrapper/config.tcl
index df19160..57b9f17 100644
--- a/openlane/user_project_wrapper/config.tcl
+++ b/openlane/user_project_wrapper/config.tcl
@@ -29,11 +29,14 @@
## Source Verilog Files
set ::env(VERILOG_FILES) "\
- $::env(CARAVEL_ROOT)/verilog/rtl/defines.v \
- $::env(DESIGN_DIR)/../../verilog/rtl/user_project_wrapper.v"
+ $::env(DESIGN_DIR)/../../verilog/rtl/defines.v \
+ $::env(DESIGN_DIR)/../../verilog/rtl/eFPGA_top.v \
+ $::env(DESIGN_DIR)/../../verilog/rtl/fabric.v \
+ $::env(DESIGN_DIR)/../../verilog/rtl/models_pack.v \
+ $::env(DESIGN_DIR)/../../verilog/rtl/wrapper_gf180.v"
## Clock configurations
-set ::env(CLOCK_PORT) "user_clock2"
+set ::env(CLOCK_PORT) "io_in\[0\]"
set ::env(CLOCK_NET) "mprj.clk"
set ::env(CLOCK_PERIOD) "10"
@@ -41,21 +44,76 @@
## Internal Macros
### Macro PDN Connections
set ::env(FP_PDN_MACRO_HOOKS) "\
- mprj vdd vss vdd vss"
+ Inst_eFPGA_top.Inst_eFPGA.Tile_X1Y0_N_term_single vdd vss vdd vss, \
+ Inst_eFPGA_top.Inst_eFPGA.Tile_X2Y0_N_term_single vdd vss vdd vss, \
+ Inst_eFPGA_top.Inst_eFPGA.Tile_X3Y0_N_term_single vdd vss vdd vss, \
+ Inst_eFPGA_top.Inst_eFPGA.Tile_X4Y0_N_term_single vdd vss vdd vss, \
+ Inst_eFPGA_top.Inst_eFPGA.Tile_X5Y0_N_term_single vdd vss vdd vss, \
+ Inst_eFPGA_top.Inst_eFPGA.Tile_X6Y0_N_term_single vdd vss vdd vss, \
+ Inst_eFPGA_top.Inst_eFPGA.Tile_X0Y1_W_IO vdd vss vdd vss, \
+ Inst_eFPGA_top.Inst_eFPGA.Tile_X1Y1_LUT4AB vdd vss vdd vss, \
+ Inst_eFPGA_top.Inst_eFPGA.Tile_X2Y1_LUT4AB vdd vss vdd vss, \
+ Inst_eFPGA_top.Inst_eFPGA.Tile_X3Y1LUT4AB vdd vss vdd vss, \
+ Inst_eFPGA_top.Inst_eFPGA.Tile_X4Y1_LUT4AB vdd vss vdd vss, \
+ Inst_eFPGA_top.Inst_eFPGA.Tile_X5Y1_LUT4AB vdd vss vdd vss, \
+ Inst_eFPGA_top.Inst_eFPGA.Tile_X6Y1_LUT4AB vdd vss vdd vss, \
+ Inst_eFPGA_top.Inst_eFPGA.Tile_X7Y1_E_IO vdd vss vdd vss, \
+ Inst_eFPGA_top.Inst_eFPGA.Tile_X0Y2_W_IO vdd vss vdd vss, \
+ Inst_eFPGA_top.Inst_eFPGA.Tile_X1Y2_LUT4AB vdd vss vdd vss, \
+ Inst_eFPGA_top.Inst_eFPGA.Tile_X2Y2_LUT4AB vdd vss vdd vss, \
+ Inst_eFPGA_top.Inst_eFPGA.Tile_X3Y2LUT4AB vdd vss vdd vss, \
+ Inst_eFPGA_top.Inst_eFPGA.Tile_X4Y2_LUT4AB vdd vss vdd vss, \
+ Inst_eFPGA_top.Inst_eFPGA.Tile_X5Y2_LUT4AB vdd vss vdd vss, \
+ Inst_eFPGA_top.Inst_eFPGA.Tile_X6Y2_LUT4AB vdd vss vdd vss, \
+ Inst_eFPGA_top.Inst_eFPGA.Tile_X7Y2_E_IO vdd vss vdd vss, \
+ Inst_eFPGA_top.Inst_eFPGA.Tile_X0Y3_W_IO vdd vss vdd vss, \
+ Inst_eFPGA_top.Inst_eFPGA.Tile_X1Y3_LUT4AB vdd vss vdd vss, \
+ Inst_eFPGA_top.Inst_eFPGA.Tile_X2Y3_LUT4AB vdd vss vdd vss, \
+ Inst_eFPGA_top.Inst_eFPGA.Tile_X3Y3LUT4AB vdd vss vdd vss, \
+ Inst_eFPGA_top.Inst_eFPGA.Tile_X4Y3_LUT4AB vdd vss vdd vss, \
+ Inst_eFPGA_top.Inst_eFPGA.Tile_X5Y3_LUT4AB vdd vss vdd vss, \
+ Inst_eFPGA_top.Inst_eFPGA.Tile_X6Y3_LUT4AB vdd vss vdd vss, \
+ Inst_eFPGA_top.Inst_eFPGA.Tile_X7Y3_E_IO vdd vss vdd vss, \
+ Inst_eFPGA_top.Inst_eFPGA.Tile_X0Y4_W_IO vdd vss vdd vss, \
+ Inst_eFPGA_top.Inst_eFPGA.Tile_X1Y4_LUT4AB vdd vss vdd vss, \
+ Inst_eFPGA_top.Inst_eFPGA.Tile_X2Y4_LUT4AB vdd vss vdd vss, \
+ Inst_eFPGA_top.Inst_eFPGA.Tile_X3Y4LUT4AB vdd vss vdd vss, \
+ Inst_eFPGA_top.Inst_eFPGA.Tile_X4Y4_LUT4AB vdd vss vdd vss, \
+ Inst_eFPGA_top.Inst_eFPGA.Tile_X5Y4_LUT4AB vdd vss vdd vss, \
+ Inst_eFPGA_top.Inst_eFPGA.Tile_X6Y4_LUT4AB vdd vss vdd vss, \
+ Inst_eFPGA_top.Inst_eFPGA.Tile_X7Y4_E_IO vdd vss vdd vss, \
+ Inst_eFPGA_top.Inst_eFPGA.Tile_X0Y5_W_IO vdd vss vdd vss, \
+ Inst_eFPGA_top.Inst_eFPGA.Tile_X1Y5_LUT4AB vdd vss vdd vss, \
+ Inst_eFPGA_top.Inst_eFPGA.Tile_X2Y5_LUT4AB vdd vss vdd vss, \
+ Inst_eFPGA_top.Inst_eFPGA.Tile_X3Y5LUT4AB vdd vss vdd vss, \
+ Inst_eFPGA_top.Inst_eFPGA.Tile_X4Y5_LUT4AB vdd vss vdd vss, \
+ Inst_eFPGA_top.Inst_eFPGA.Tile_X5Y5_LUT4AB vdd vss vdd vss, \
+ Inst_eFPGA_top.Inst_eFPGA.Tile_X6Y5_LUT4AB vdd vss vdd vss, \
+ Inst_eFPGA_top.Inst_eFPGA.Tile_X7Y5_E_IO vdd vss vdd vss, \
+ Inst_eFPGA_top.Inst_eFPGA.Tile_X0Y6_W_IO vdd vss vdd vss, \
+ Inst_eFPGA_top.Inst_eFPGA.Tile_X1Y6_LUT4AB vdd vss vdd vss, \
+ Inst_eFPGA_top.Inst_eFPGA.Tile_X2Y6_LUT4AB vdd vss vdd vss, \
+ Inst_eFPGA_top.Inst_eFPGA.Tile_X3Y6LUT4AB vdd vss vdd vss, \
+ Inst_eFPGA_top.Inst_eFPGA.Tile_X4Y6_LUT4AB vdd vss vdd vss, \
+ Inst_eFPGA_top.Inst_eFPGA.Tile_X5Y6_LUT4AB vdd vss vdd vss, \
+ Inst_eFPGA_top.Inst_eFPGA.Tile_X6Y6_LUT4AB vdd vss vdd vss, \
+ Inst_eFPGA_top.Inst_eFPGA.Tile_X7Y6_E_IO vdd vss vdd vss, \
+ Inst_eFPGA_top.Inst_eFPGA.Tile_X1Y7_S_term_single vdd vss vdd vss, \
+ Inst_eFPGA_top.Inst_eFPGA.Tile_X2Y7_S_term_single vdd vss vdd vss, \
+ Inst_eFPGA_top.Inst_eFPGA.Tile_X3Y7_S_term_single vdd vss vdd vss, \
+ Inst_eFPGA_top.Inst_eFPGA.Tile_X4Y7_S_term_single vdd vss vdd vss, \
+ Inst_eFPGA_top.Inst_eFPGA.Tile_X5Y7_S_term_single vdd vss vdd vss, \
+ Inst_eFPGA_top.Inst_eFPGA.Tile_X6Y7_S_term_single vdd vss vdd vss"
### Macro Placement
set ::env(MACRO_PLACEMENT_CFG) $::env(DESIGN_DIR)/macro.cfg
### Black-box verilog and views
-set ::env(VERILOG_FILES_BLACKBOX) "\
- $::env(CARAVEL_ROOT)/verilog/rtl/defines.v \
- $::env(DESIGN_DIR)/../../verilog/rtl/user_proj_example.v"
+set ::env(VERILOG_FILES_BLACKBOX) [glob $::env(DESIGN_DIR)/macros/verilog/*.v]
-set ::env(EXTRA_LEFS) "\
- $::env(DESIGN_DIR)/../../lef/user_proj_example.lef"
+set ::env(EXTRA_LEFS) [glob $::env(DESIGN_DIR)/macros/lef/*.lef]
-set ::env(EXTRA_GDS_FILES) "\
- $::env(DESIGN_DIR)/../../gds/user_proj_example.gds"
+set ::env(EXTRA_GDS_FILES) [glob $::env(DESIGN_DIR)/macros/gds/*.gds]
set ::env(RT_MAX_LAYER) {Metal4}
@@ -63,21 +121,26 @@
# any issue with pdn connections will be flagged with LVS so it is not a critical check.
set ::env(FP_PDN_CHECK_NODES) 0
-# The following is because there are no std cells in the example wrapper project.
-set ::env(SYNTH_ELABORATE_ONLY) 1
-set ::env(PL_RANDOM_GLB_PLACEMENT) 1
+set ::env(DIODE_INSERTION_STRATEGY) 4
+set ::env(GRT_ALLOW_CONGESTION) 1
+set ::env(GLB_RESIZER_TIMING_OPTIMIZATIONS) 0
-set ::env(PL_RESIZER_DESIGN_OPTIMIZATIONS) 0
-set ::env(PL_RESIZER_TIMING_OPTIMIZATIONS) 0
-set ::env(PL_RESIZER_BUFFER_INPUT_PORTS) 0
-set ::env(PL_RESIZER_BUFFER_OUTPUT_PORTS) 0
+# set ::env(PL_MACRO_CHANNEL_WIDTH) 20
-set ::env(FP_PDN_ENABLE_RAILS) 0
+set ::env(PL_TARGET_DENSITY) 0.5
-set ::env(DIODE_INSERTION_STRATEGY) 0
-set ::env(RUN_FILL_INSERTION) 0
-set ::env(RUN_TAP_DECAP_INSERTION) 0
-set ::env(CLOCK_TREE_SYNTH) 0
+set ::env(CTS_TARGET_SKEW) 200
+set ::env(CTS_SINK_CLUSTERING_SIZE) 100
+
+set ::env(VDD_NETS) [list {vdd}]
+set ::env(GND_NETS) [list {vss}]
+
+set ::env(CLOCK_PORT) {io_in[5]}
+set ::env(CLOCK_NET) {io_in[5]}
+set ::env(CLOCK_PERIOD) 100
+
+set ::env(PL_MAX_DISPLACEMENT_X) 1000
+set ::env(PL_MAX_DISPLACEMENT_Y) 1000
# YOU ARE NOT ALLOWED TO CHANGE ANY VARIABLES DEFINED IN THE FIXED WRAPPER CFGS
-source $::env(DESIGN_DIR)/fixed_dont_change/fixed_wrapper_cfgs.tcl
\ No newline at end of file
+source $::env(DESIGN_DIR)/fixed_dont_change/fixed_wrapper_cfgs.tcl
diff --git a/openlane/user_project_wrapper/macro.cfg b/openlane/user_project_wrapper/macro.cfg
index a7365ab..19fe940 100644
--- a/openlane/user_project_wrapper/macro.cfg
+++ b/openlane/user_project_wrapper/macro.cfg
@@ -1 +1,60 @@
-mprj 1175 1690 N
+Inst_eFPGA_top.Inst_eFPGA.Tile_X1Y0_N_term_single 640 5340 N
+Inst_eFPGA_top.Inst_eFPGA.Tile_X2Y0_N_term_single 1440 5340 N
+Inst_eFPGA_top.Inst_eFPGA.Tile_X3Y0_N_term_single 2240 5340 N
+Inst_eFPGA_top.Inst_eFPGA.Tile_X4Y0_N_term_single 3040 5340 N
+Inst_eFPGA_top.Inst_eFPGA.Tile_X5Y0_N_term_single 3840 5340 N
+Inst_eFPGA_top.Inst_eFPGA.Tile_X6Y0_N_term_single 4640 5340 N
+Inst_eFPGA_top.Inst_eFPGA.Tile_X0Y1_W_IO 400 4540 N
+Inst_eFPGA_top.Inst_eFPGA.Tile_X1Y1_LUT4AB 640 4540 N
+Inst_eFPGA_top.Inst_eFPGA.Tile_X2Y1_LUT4AB 1440 4540 N
+Inst_eFPGA_top.Inst_eFPGA.Tile_X3Y1_LUT4AB 2240 4540 N
+Inst_eFPGA_top.Inst_eFPGA.Tile_X4Y1_LUT4AB 3040 4540 N
+Inst_eFPGA_top.Inst_eFPGA.Tile_X5Y1_LUT4AB 3840 4540 N
+Inst_eFPGA_top.Inst_eFPGA.Tile_X6Y1_LUT4AB 4640 4540 N
+Inst_eFPGA_top.Inst_eFPGA.Tile_X7Y1_E_IO 5440 4540 N
+Inst_eFPGA_top.Inst_eFPGA.Tile_X0Y2_W_IO 400 3740 N
+Inst_eFPGA_top.Inst_eFPGA.Tile_X1Y2_LUT4AB 640 3740 N
+Inst_eFPGA_top.Inst_eFPGA.Tile_X2Y2_LUT4AB 1440 3740 N
+Inst_eFPGA_top.Inst_eFPGA.Tile_X3Y2_LUT4AB 2240 3740 N
+Inst_eFPGA_top.Inst_eFPGA.Tile_X4Y2_LUT4AB 3040 3740 N
+Inst_eFPGA_top.Inst_eFPGA.Tile_X5Y2_LUT4AB 3840 3740 N
+Inst_eFPGA_top.Inst_eFPGA.Tile_X6Y2_LUT4AB 4640 3740 N
+Inst_eFPGA_top.Inst_eFPGA.Tile_X7Y2_E_IO 5440 3740 N
+Inst_eFPGA_top.Inst_eFPGA.Tile_X0Y3_W_IO 400 2940 N
+Inst_eFPGA_top.Inst_eFPGA.Tile_X1Y3_LUT4AB 640 2940 N
+Inst_eFPGA_top.Inst_eFPGA.Tile_X2Y3_LUT4AB 1440 2940 N
+Inst_eFPGA_top.Inst_eFPGA.Tile_X3Y3_LUT4AB 2240 2940 N
+Inst_eFPGA_top.Inst_eFPGA.Tile_X4Y3_LUT4AB 3040 2940 N
+Inst_eFPGA_top.Inst_eFPGA.Tile_X5Y3_LUT4AB 3840 2940 N
+Inst_eFPGA_top.Inst_eFPGA.Tile_X6Y3_LUT4AB 4640 2940 N
+Inst_eFPGA_top.Inst_eFPGA.Tile_X7Y3_E_IO 5440 2940 N
+Inst_eFPGA_top.Inst_eFPGA.Tile_X0Y4_W_IO 400 2140 N
+Inst_eFPGA_top.Inst_eFPGA.Tile_X1Y4_LUT4AB 640 2140 N
+Inst_eFPGA_top.Inst_eFPGA.Tile_X2Y4_LUT4AB 1440 2140 N
+Inst_eFPGA_top.Inst_eFPGA.Tile_X3Y4_LUT4AB 2240 2140 N
+Inst_eFPGA_top.Inst_eFPGA.Tile_X4Y4_LUT4AB 3040 2140 N
+Inst_eFPGA_top.Inst_eFPGA.Tile_X5Y4_LUT4AB 3840 2140 N
+Inst_eFPGA_top.Inst_eFPGA.Tile_X6Y4_LUT4AB 4640 2140 N
+Inst_eFPGA_top.Inst_eFPGA.Tile_X7Y4_E_IO 5440 2140 N
+Inst_eFPGA_top.Inst_eFPGA.Tile_X0Y5_W_IO 400 1340 N
+Inst_eFPGA_top.Inst_eFPGA.Tile_X1Y5_LUT4AB 640 1340 N
+Inst_eFPGA_top.Inst_eFPGA.Tile_X2Y5_LUT4AB 1440 1340 N
+Inst_eFPGA_top.Inst_eFPGA.Tile_X3Y5_LUT4AB 2240 1340 N
+Inst_eFPGA_top.Inst_eFPGA.Tile_X4Y5_LUT4AB 3040 1340 N
+Inst_eFPGA_top.Inst_eFPGA.Tile_X5Y5_LUT4AB 3840 1340 N
+Inst_eFPGA_top.Inst_eFPGA.Tile_X6Y5_LUT4AB 4640 1340 N
+Inst_eFPGA_top.Inst_eFPGA.Tile_X7Y5_E_IO 5440 1340 N
+Inst_eFPGA_top.Inst_eFPGA.Tile_X0Y6_W_IO 400 540 N
+Inst_eFPGA_top.Inst_eFPGA.Tile_X1Y6_LUT4AB 640 540 N
+Inst_eFPGA_top.Inst_eFPGA.Tile_X2Y6_LUT4AB 1440 540 N
+Inst_eFPGA_top.Inst_eFPGA.Tile_X3Y6_LUT4AB 2240 540 N
+Inst_eFPGA_top.Inst_eFPGA.Tile_X4Y6_LUT4AB 3040 540 N
+Inst_eFPGA_top.Inst_eFPGA.Tile_X5Y6_LUT4AB 3840 540 N
+Inst_eFPGA_top.Inst_eFPGA.Tile_X6Y6_LUT4AB 4640 540 N
+Inst_eFPGA_top.Inst_eFPGA.Tile_X7Y6_E_IO 5440 540 N
+Inst_eFPGA_top.Inst_eFPGA.Tile_X1Y7_S_term_single 640 160 N
+Inst_eFPGA_top.Inst_eFPGA.Tile_X2Y7_S_term_single 1440 160 N
+Inst_eFPGA_top.Inst_eFPGA.Tile_X3Y7_S_term_single 2240 160 N
+Inst_eFPGA_top.Inst_eFPGA.Tile_X4Y7_S_term_single 3040 160 N
+Inst_eFPGA_top.Inst_eFPGA.Tile_X5Y7_S_term_single 3840 160 N
+Inst_eFPGA_top.Inst_eFPGA.Tile_X6Y7_S_term_single 4640 160 N
