)]}'
{
  "commit": "51a109622b4580ce760a544cc2104ba5985dbf15",
  "tree": "2c7a5b3f53388902c19d317ffa8908f4caa5585c",
  "parents": [
    "a0cb6e01680a5936190439c86925c0a752ff0c25"
  ],
  "author": {
    "name": "Marwan Abbas",
    "email": "marwaneltoukhy@aucegypt.edu",
    "time": "Fri Feb 11 16:35:19 2022 +0200"
  },
  "committer": {
    "name": "Marwan Abbas",
    "email": "marwaneltoukhy@aucegypt.edu",
    "time": "Fri Feb 11 16:35:19 2022 +0200"
  },
  "message": "initial commit to integrating litex tb with caravel_user_project mprj\nand wb tests still wp\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "6de652c3f5f0eb78eab9cb6fab190435c7b136f7",
      "old_mode": 33188,
      "old_path": "Makefile",
      "new_id": "fa42afe2d8fef8e53203208e10355ce38af60071",
      "new_mode": 33188,
      "new_path": "Makefile"
    },
    {
      "type": "modify",
      "old_id": "d87238f0e5affdad2cdf0f2208e94beef2bb33bc",
      "old_mode": 33188,
      "old_path": "verilog/dv/Makefile",
      "new_id": "e14258deccfff255d88a505fe9de76333b70ca25",
      "new_mode": 33188,
      "new_path": "verilog/dv/Makefile"
    },
    {
      "type": "modify",
      "old_id": "5237a05a6ff7f5acfd0d9853ae8c6ea24f3736ac",
      "old_mode": 33188,
      "old_path": "verilog/dv/io_ports/Makefile",
      "new_id": "ea1b0e07334ab65aa0259a33463e07c203acacbc",
      "new_mode": 33188,
      "new_path": "verilog/dv/io_ports/Makefile"
    },
    {
      "type": "add",
      "old_id": "0000000000000000000000000000000000000000",
      "old_mode": 0,
      "old_path": "/dev/null",
      "new_id": "a85a5eda3799377a5796672edd62b032a9b8eb52",
      "new_mode": 33188,
      "new_path": "verilog/dv/io_ports/RTL-io_ports.vcd"
    },
    {
      "type": "modify",
      "old_id": "0b235710cb58060a9efbfcdce12888d227f23b14",
      "old_mode": 33188,
      "old_path": "verilog/dv/io_ports/io_ports.c",
      "new_id": "aa111ef633ac6e9c13386266c498ba43108737fa",
      "new_mode": 33188,
      "new_path": "verilog/dv/io_ports/io_ports.c"
    },
    {
      "type": "add",
      "old_id": "0000000000000000000000000000000000000000",
      "old_mode": 0,
      "old_path": "/dev/null",
      "new_id": "2515ebb46959a37dc7526b59f3eaae5fa2199ec0",
      "new_mode": 33261,
      "new_path": "verilog/dv/io_ports/io_ports.hex"
    },
    {
      "type": "add",
      "old_id": "0000000000000000000000000000000000000000",
      "old_mode": 0,
      "old_path": "/dev/null",
      "new_id": "66f66608388a9a4c9eac120b6bea6cbab442f0b2",
      "new_mode": 33261,
      "new_path": "verilog/dv/io_ports/io_ports.hexe"
    },
    {
      "type": "add",
      "old_id": "0000000000000000000000000000000000000000",
      "old_mode": 0,
      "old_path": "/dev/null",
      "new_id": "a7bd07394627598298a00f2737250557768a1c91",
      "new_mode": 33188,
      "new_path": "verilog/dv/io_ports/io_ports.lst"
    },
    {
      "type": "modify",
      "old_id": "f7628bc34c383145f2526b7e6c2773156ed6924e",
      "old_mode": 33188,
      "old_path": "verilog/dv/io_ports/io_ports_tb.v",
      "new_id": "8da4873b94914691cdc51b1f9c067c2c9d3b5862",
      "new_mode": 33188,
      "new_path": "verilog/dv/io_ports/io_ports_tb.v"
    },
    {
      "type": "modify",
      "old_id": "ba979f7a9ff6183fc0e0cbce245fa8ec9190fa78",
      "old_mode": 33188,
      "old_path": "verilog/dv/la_test1/Makefile",
      "new_id": "508ac7b8c87a608af0eadd2d54c054b9ed2f5b70",
      "new_mode": 33188,
      "new_path": "verilog/dv/la_test1/Makefile"
    },
    {
      "type": "modify",
      "old_id": "220bdfe3e258c752feb43b388a87c37771a5ddd5",
      "old_mode": 33188,
      "old_path": "verilog/dv/la_test1/la_test1.c",
      "new_id": "96b56bdc07397714713183c423d6b688ac750c01",
      "new_mode": 33188,
      "new_path": "verilog/dv/la_test1/la_test1.c"
    },
    {
      "type": "modify",
      "old_id": "626e390a7212fbc2a4121ecc693f86155208e6a8",
      "old_mode": 33188,
      "old_path": "verilog/dv/la_test1/la_test1_tb.v",
      "new_id": "93fafebb2c4fdd975d3c81cad98929d71b355448",
      "new_mode": 33188,
      "new_path": "verilog/dv/la_test1/la_test1_tb.v"
    },
    {
      "type": "modify",
      "old_id": "0435500a3e89bb3d2242890df799c4ed301c04e5",
      "old_mode": 33188,
      "old_path": "verilog/dv/la_test2/Makefile",
      "new_id": "508ac7b8c87a608af0eadd2d54c054b9ed2f5b70",
      "new_mode": 33188,
      "new_path": "verilog/dv/la_test2/Makefile"
    },
    {
      "type": "modify",
      "old_id": "5875432d2683bc04de3fd49f7c5a10cf0b2e6f5e",
      "old_mode": 33188,
      "old_path": "verilog/dv/la_test2/la_test2.c",
      "new_id": "25fad481e188bd9c186b9706f140fff0f4ad9764",
      "new_mode": 33188,
      "new_path": "verilog/dv/la_test2/la_test2.c"
    },
    {
      "type": "modify",
      "old_id": "e09905e603055e7d0a9fb905cf94d7ad1b867f66",
      "old_mode": 33188,
      "old_path": "verilog/dv/la_test2/la_test2_tb.v",
      "new_id": "2acf43d610c0f08dee912e70e3af58daf394d83a",
      "new_mode": 33188,
      "new_path": "verilog/dv/la_test2/la_test2_tb.v"
    },
    {
      "type": "modify",
      "old_id": "b0e40519ce5314a629a276f055ea9d40ebfe4f06",
      "old_mode": 33188,
      "old_path": "verilog/dv/mprj_stimulus/Makefile",
      "new_id": "508ac7b8c87a608af0eadd2d54c054b9ed2f5b70",
      "new_mode": 33188,
      "new_path": "verilog/dv/mprj_stimulus/Makefile"
    },
    {
      "type": "modify",
      "old_id": "7d2c29afde8cc300566727d552c6cc042d82865b",
      "old_mode": 33188,
      "old_path": "verilog/dv/mprj_stimulus/mprj_stimulus.c",
      "new_id": "65633bce759b2042fcbd226a5163134b51eb5358",
      "new_mode": 33188,
      "new_path": "verilog/dv/mprj_stimulus/mprj_stimulus.c"
    },
    {
      "type": "modify",
      "old_id": "0ac0b42fcd7275e75c4cf1aaa5e9b4d506e6df59",
      "old_mode": 33188,
      "old_path": "verilog/dv/mprj_stimulus/mprj_stimulus_tb.v",
      "new_id": "15d7849d31b37a95a4ddd141404ff225390ee9ad",
      "new_mode": 33188,
      "new_path": "verilog/dv/mprj_stimulus/mprj_stimulus_tb.v"
    },
    {
      "type": "modify",
      "old_id": "1c784c6d7c5e2a9fb157d670649e53f2f80a033b",
      "old_mode": 33188,
      "old_path": "verilog/dv/wb_port/Makefile",
      "new_id": "508ac7b8c87a608af0eadd2d54c054b9ed2f5b70",
      "new_mode": 33188,
      "new_path": "verilog/dv/wb_port/Makefile"
    }
  ]
}
