| /root/caravel_jacaranda-8_gf180/openlane/computer/config.tcl |
| /root/caravel_jacaranda-8_gf180/verilog/includes/includes.gl+sdf.caravel_user_project |
| /root/caravel_jacaranda-8_gf180/verilog/includes/includes.gl.caravel_user_project |
| /root/caravel_jacaranda-8_gf180/verilog/includes/includes.rtl.caravel_user_project |
| /root/caravel_jacaranda-8_gf180/verilog/rtl/jacaranda-8/alu.v |
| /root/caravel_jacaranda-8_gf180/verilog/rtl/jacaranda-8/alu_controller.v |
| /root/caravel_jacaranda-8_gf180/verilog/rtl/jacaranda-8/computer.v |
| /root/caravel_jacaranda-8_gf180/verilog/rtl/jacaranda-8/cpu.v |
| /root/caravel_jacaranda-8_gf180/verilog/rtl/jacaranda-8/data_mem.v |
| /root/caravel_jacaranda-8_gf180/verilog/rtl/jacaranda-8/decoder.v |
| /root/caravel_jacaranda-8_gf180/verilog/rtl/jacaranda-8/instr_mem.v |
| /root/caravel_jacaranda-8_gf180/verilog/rtl/jacaranda-8/main_controller.v |
| /root/caravel_jacaranda-8_gf180/verilog/rtl/jacaranda-8/regfile.v |
| /root/caravel_jacaranda-8_gf180/verilog/rtl/jacaranda-8/wishbone.v |
| /root/caravel_jacaranda-8_gf180/verilog/rtl/jacaranda-8/UART/UART.v |
| /root/caravel_jacaranda-8_gf180/verilog/rtl/jacaranda-8/UART/rx.v |
| /root/caravel_jacaranda-8_gf180/verilog/rtl/jacaranda-8/UART/tx.v |
