diff --git a/info.yaml b/info.yaml
index e390bc8..3b00768 100644
--- a/info.yaml
+++ b/info.yaml
@@ -4,6 +4,12 @@
   wokwi_id: 0
   source_files:        # If using an HDL, set wokwi_id as 0 and uncomment and list your source files here
     - verilog/rtl/user_module.v
+    - verilog/rtl/pdm.v
+    - verilog/rtl/dice.v
+    - verilog/rtl/dtype_synth.v
+    - verilog/rtl/encoder.v
+    - verilog/rtl/control.v
+    - verilog/rtl/random.v
   top_module:  "user_module"      # put the name of your top module here, make it unique by prepending your github username
 
 # As everyone will have access to all designs, try to make it easy for someone new to your design to know what
diff --git a/verilog/rtl/cells.v b/verilog/rtl/cells.v
deleted file mode 100644
index fb6db62..0000000
--- a/verilog/rtl/cells.v
+++ /dev/null
@@ -1,96 +0,0 @@
-`define default_netname none
-
-module buffer_cell (
-    input wire in,
-    output wire out
-    );
-    assign out = in;
-endmodule
-
-module and_cell (
-    input wire a,
-    input wire b,
-    output wire out
-    );
-
-    assign out = a & b;
-endmodule
-
-module or_cell (
-    input wire a,
-    input wire b,
-    output wire out
-    );
-
-    assign out = a | b;
-endmodule
-
-module xor_cell (
-    input wire a,
-    input wire b,
-    output wire out
-    );
-
-    assign out = a ^ b;
-endmodule
-
-module nand_cell (
-    input wire a,
-    input wire b,
-    output wire out
-    );
-
-    assign out = !(a&b);
-endmodule
-
-module not_cell (
-    input wire in,
-    output wire out
-    );
-
-    assign out = !in;
-endmodule
-
-module mux_cell (
-    input wire a,
-    input wire b,
-    input wire sel,
-    output wire out
-    );
-
-    assign out = sel ? b : a;
-endmodule
-
-module dff_cell (
-    input wire clk,
-    input wire d,
-    output reg q,
-    output wire notq
-    );
-
-    assign notq = !q;
-    always @(posedge clk)
-        q <= d;
-
-endmodule
-
-module dffsr_cell (
-    input wire clk,
-    input wire d,
-    input wire s,
-    input wire r,
-    output reg q,
-    output wire notq
-    );
-
-    assign notq = !q;
-
-    always @(posedge clk or posedge s or posedge r) begin
-        if (r)
-            q <= '0;
-        else if (s)
-            q <= '1;
-        else
-            q <= d;
-    end
-endmodule
diff --git a/verilog/rtl/fast_control.v b/verilog/rtl/control.v
similarity index 98%
rename from verilog/rtl/fast_control.v
rename to verilog/rtl/control.v
index 8746c54..c414c41 100644
--- a/verilog/rtl/fast_control.v
+++ b/verilog/rtl/control.v
@@ -2,7 +2,7 @@
 
 timeunit 1ns; timeprecision 10ps;
 
-module fast_control(
+module control(
     input wire Clock, nReset,
     input wire [1:0] Ran,
     output wire [2:0] DiceValue
diff --git a/verilog/rtl/encoder.sv b/verilog/rtl/encoder.v
similarity index 100%
rename from verilog/rtl/encoder.sv
rename to verilog/rtl/encoder.v
diff --git a/verilog/rtl/pdm.v b/verilog/rtl/pdm.v
new file mode 100644
index 0000000..68ba105
--- /dev/null
+++ b/verilog/rtl/pdm.v
@@ -0,0 +1,28 @@
+// 8-bit PDM driver
+
+module pdm(
+    input [4:0] pdm_input,
+    input       write_en,
+    input       clk, reset,    
+    output      pdm_out
+);
+
+reg [4:0] accumulator;
+reg [4:0] input_reg;
+
+wire [5:0] sum;
+
+assign sum = input_reg + accumulator;
+assign pdm_out = sum[5];
+
+always @(posedge clk or posedge reset) begin
+    if (reset) begin 
+        input_reg <= 5'h00 ;
+        accumulator <= 5'h00;
+    end else begin
+        accumulator <= sum[4:0];
+        if (write_en) input_reg <= pdm_input ;
+    end
+end
+
+endmodule
\ No newline at end of file
diff --git a/verilog/rtl/user_module.v b/verilog/rtl/user_module.v
index 714c20a..c9d1608 100644
--- a/verilog/rtl/user_module.v
+++ b/verilog/rtl/user_module.v
@@ -1,12 +1,12 @@
 `default_nettype none
 
-//  Top level io for this module should stay the same to fit into the scan_wrapper.
-//  The pin connections within the user_module are up to you,
-//  although (if one is present) it is recommended to place a clock on io_in[0].
+//  Top level io for this module uses all available GPIO
+//  The pin connections within the user_module can change
 //  This allows use of the internal clock divider if you wish.
 module user_module(
-  input [7:0] io_in, 
-  output [7:0] io_out
+  input user_clock2,
+  input [18:0] io_in, 
+  output [18:0] io_out
 );
 
   wire pdm_out;
@@ -23,34 +23,3 @@
   );
 
 endmodule
-
-//  Any submodules should be included in this file,
-//  so they are copied into the main TinyTapeout repo.
-//  Appending your ID to any submodules you create 
-//  ensures there are no clashes in full-chip simulation.
-module pdm(
-    input [4:0] pdm_input,
-    input       write_en,
-    input       clk, reset,    
-    output      pdm_out
-);
-
-reg [4:0] accumulator;
-reg [4:0] input_reg;
-
-wire [5:0] sum;
-
-assign sum = input_reg + accumulator;
-assign pdm_out = sum[5];
-
-always @(posedge clk or posedge reset) begin
-    if (reset) begin 
-        input_reg <= 5'h00 ;
-        accumulator <= 5'h00;
-    end else begin
-        accumulator <= sum[4:0];
-        if (write_en) input_reg <= pdm_input ;
-    end
-end
-
-endmodule
\ No newline at end of file