diff --git a/.github/workflows/user_project_ci.yml b/.github/workflows/user_project_ci.yml
index ac74674..351da05 100644
--- a/.github/workflows/user_project_ci.yml
+++ b/.github/workflows/user_project_ci.yml
@@ -17,7 +17,7 @@
   OPENLANE_ROOT: '/home/runner/work/openlane'
   PDK: 'gf180mcuC'
   PDK_TECH: 'gf180mcu'
-  SETUP_CACHE_KEY: 'gfmpw-0b'
+  SETUP_CACHE_KEY: 'gfmpw-0d'
 
 concurrency: ${{ github.workflow }}-${{ github.ref_name }}
 
diff --git a/Makefile b/Makefile
index 2a6f25f..7561bf2 100644
--- a/Makefile
+++ b/Makefile
@@ -67,11 +67,14 @@
 endif
 
 ifeq ($(PDK),gf180mcuC)
-	MPW_TAG ?= gfmpw-0b
+	MPW_TAG ?= gfmpw-0d
 	CARAVEL_NAME := caravel
 	CARAVEL_REPO := https://github.com/efabless/caravel-gf180mcu
 	CARAVEL_TAG := $(MPW_TAG)
-	export OPENLANE_TAG?=2022.11.17
+	#OPENLANE_TAG=ddfeab57e3e8769ea3d40dda12be0460e09bb6d9
+	#export OPEN_PDKS_COMMIT?=0059588eebfc704681dc2368bd1d33d96281d10f
+	export OPEN_PDKS_COMMIT?=35c7265f51749ad8d9fdbb575af22c7c8fab974e
+	export OPENLANE_TAG?=2022.11.29
 endif
 
 # Include Caravel Makefile Targets
diff --git a/openlane/Makefile b/openlane/Makefile
index d38080d..87ca551 100644
--- a/openlane/Makefile
+++ b/openlane/Makefile
@@ -16,7 +16,7 @@
 MAKEFLAGS+=--warn-undefined-variables
 
 export OPENLANE_RUN_TAG = $(shell date '+%y_%m_%d_%H_%M')
-OPENLANE_TAG ?= 2022.10.20
+OPENLANE_TAG ?= 2022.11.29
 OPENLANE_IMAGE_NAME ?= efabless/openlane:$(OPENLANE_TAG)
 designs = $(shell find * -maxdepth 0 -type d)
 current_design = null
diff --git a/openlane/tiny_user_project/config.json b/openlane/tiny_user_project/config.json
index 4ff98be..bca3c25 100644
--- a/openlane/tiny_user_project/config.json
+++ b/openlane/tiny_user_project/config.json
@@ -3,7 +3,12 @@
     "DESIGN_IS_CORE": 0,
     "VERILOG_FILES": [
         "dir::../../verilog/rtl/user_module.v",
-        "dir::../../verilog/rtl/cells.v",
+        "dir::../../verilog/rtl/pdm.v",
+        "dir::../../verilog/rtl/dice.v",
+        "dir::../../verilog/rtl/dtype_synth.v",
+        "dir::../../verilog/rtl/encoder.v",
+        "dir::../../verilog/rtl/control.v",
+        "dir::../../verilog/rtl/random.v",
         "dir::../../verilog/rtl/defines.v",
         "dir::../../verilog/rtl/tiny_user_project.v"
     ],
@@ -13,7 +18,7 @@
     "FP_SIZING": "absolute",
     "DIE_AREA": "0 0 600 680",
     "PL_BASIC_PLACEMENT": 1,
-    "PL_TARGET_DENSITY": 0.70,
+    "PL_TARGET_DENSITY": 0.7,
     "SYNTH_USE_PG_PINS_DEFINES": "USE_POWER_PINS",
     "VDD_NETS": [
         "vdd"
@@ -40,4 +45,4 @@
         "RT_MAX_LAYER": "Metal4",
         "SYNTH_MAX_FANOUT": 4
     }
-}
+}
\ No newline at end of file
diff --git a/openlane/user_project_wrapper/fixed_dont_change/fixed_wrapper_cfgs.tcl b/openlane/user_project_wrapper/fixed_dont_change/fixed_wrapper_cfgs.tcl
index 78c72f1..636e68b 100644
--- a/openlane/user_project_wrapper/fixed_dont_change/fixed_wrapper_cfgs.tcl
+++ b/openlane/user_project_wrapper/fixed_dont_change/fixed_wrapper_cfgs.tcl
@@ -19,15 +19,16 @@
 # of your block.
 set ::env(MAGIC_ZEROIZE_ORIGIN) 0
 
-set ::env(FP_DEF_TEMPLATE) $::env(DESIGN_DIR)/fixed_dont_change/user_project_wrapper_gf180mcu.def
-
 # Area Configurations. DON'T TOUCH.
 set ::env(FP_SIZING) absolute
-set ::env(DIE_AREA) "0 0 3000 3000"
-set ::env(CORE_AREA) "21.5 21.5 2978.5 2978.5"
+set ::env(DIE_AREA) "0 0 2980.2 2980.2"
+set ::env(CORE_AREA) "12 12 2968.2 2968.2"
 
 set ::env(RUN_CVC) 0
 
+# Pin Configurations. DON'T TOUCH
+set ::env(FP_PIN_ORDER_CFG) $::env(DESIGN_DIR)/pin_order.cfg
+
 set ::unit 2.4
 set ::env(FP_IO_VEXTEND) [expr 2*$::unit]
 set ::env(FP_IO_HEXTEND) [expr 2*$::unit]
@@ -42,7 +43,7 @@
 set ::env(FP_PDN_CORE_RING_VWIDTH) 3.1
 set ::env(FP_PDN_CORE_RING_HWIDTH) 3.1
 set ::env(FP_PDN_CORE_RING_VOFFSET) 14
-set ::env(FP_PDN_CORE_RING_HOFFSET) $::env(FP_PDN_CORE_RING_VOFFSET)
+set ::env(FP_PDN_CORE_RING_HOFFSET) 16
 set ::env(FP_PDN_CORE_RING_VSPACING) 1.7
 set ::env(FP_PDN_CORE_RING_HSPACING) $::env(FP_PDN_CORE_RING_VSPACING)
 set ::env(FP_PDN_HOFFSET) 5
diff --git a/verilog/rtl/user_defines.v b/verilog/rtl/user_defines.v
index a407569..dad6ddb 100644
--- a/verilog/rtl/user_defines.v
+++ b/verilog/rtl/user_defines.v
@@ -25,20 +25,18 @@
 // Authoritive source of these MODE defs is: caravel/verilog/rtl/user_defines.v
 // Useful GPIO mode values.  These match the names used in defs.h.
 //
-`define GPIO_MODE_MGMT_STD_INPUT_NOPULL    13'h0403
-`define GPIO_MODE_MGMT_STD_INPUT_PULLDOWN  13'h0c01
-`define GPIO_MODE_MGMT_STD_INPUT_PULLUP    13'h0801
-`define GPIO_MODE_MGMT_STD_OUTPUT          13'h1809
-`define GPIO_MODE_MGMT_STD_BIDIRECTIONAL   13'h1801
-`define GPIO_MODE_MGMT_STD_ANALOG          13'h000b
 
-`define GPIO_MODE_USER_STD_INPUT_NOPULL    13'h0402
-`define GPIO_MODE_USER_STD_INPUT_PULLDOWN  13'h0c00
-`define GPIO_MODE_USER_STD_INPUT_PULLUP    13'h0800
-`define GPIO_MODE_USER_STD_OUTPUT          13'h1808
-`define GPIO_MODE_USER_STD_BIDIRECTIONAL   13'h1800
-`define GPIO_MODE_USER_STD_OUT_MONITORED   13'h1802
-`define GPIO_MODE_USER_STD_ANALOG          13'h000a
+`define GPIO_MODE_MGMT_STD_INPUT_NOPULL    10'h007
+`define GPIO_MODE_MGMT_STD_INPUT_PULLDOWN  10'h047
+`define GPIO_MODE_MGMT_STD_INPUT_PULLUP    10'h087
+`define GPIO_MODE_MGMT_STD_OUTPUT          10'h00b
+`define GPIO_MODE_MGMT_STD_BIDIRECTIONAL   10'h009
+
+`define GPIO_MODE_USER_STD_INPUT_NOPULL    10'h006
+`define GPIO_MODE_USER_STD_INPUT_PULLDOWN  10'h046
+`define GPIO_MODE_USER_STD_INPUT_PULLUP    10'h086
+`define GPIO_MODE_USER_STD_OUTPUT          10'h00a
+`define GPIO_MODE_USER_STD_BIDIRECTIONAL   10'h008
 
 // The power-on configuration for GPIO 0 to 4 is fixed and cannot be
 // modified (allowing the SPI and debug to always be accessible unless
@@ -55,10 +53,9 @@
 // tiny_user_project i/o
 // generated by configure.py
 
-
-`define USER_CONFIG_GPIO_5_INIT `GPIO_MODE_INVALID
-`define USER_CONFIG_GPIO_6_INIT `GPIO_MODE_INVALID
-`define USER_CONFIG_GPIO_7_INIT `GPIO_MODE_INVALID
+`define USER_CONFIG_GPIO_5_INIT `GPIO_MODE_USER_STD_INPUT_PULLDOWN
+`define USER_CONFIG_GPIO_6_INIT `GPIO_MODE_USER_STD_INPUT_PULLDOWN
+`define USER_CONFIG_GPIO_7_INIT `GPIO_MODE_USER_STD_INPUT_PULLDOWN
 `define USER_CONFIG_GPIO_8_INIT `GPIO_MODE_USER_STD_INPUT_NOPULL
 `define USER_CONFIG_GPIO_9_INIT `GPIO_MODE_USER_STD_INPUT_NOPULL
 `define USER_CONFIG_GPIO_10_INIT `GPIO_MODE_USER_STD_INPUT_NOPULL
@@ -78,16 +75,16 @@
 `define USER_CONFIG_GPIO_24_INIT `GPIO_MODE_USER_STD_OUTPUT
 `define USER_CONFIG_GPIO_25_INIT `GPIO_MODE_USER_STD_OUTPUT
 `define USER_CONFIG_GPIO_26_INIT `GPIO_MODE_USER_STD_OUTPUT
-`define USER_CONFIG_GPIO_27_INIT `GPIO_MODE_INVALID
-`define USER_CONFIG_GPIO_28_INIT `GPIO_MODE_INVALID
-`define USER_CONFIG_GPIO_29_INIT `GPIO_MODE_INVALID
-`define USER_CONFIG_GPIO_30_INIT `GPIO_MODE_INVALID
-`define USER_CONFIG_GPIO_31_INIT `GPIO_MODE_INVALID
-`define USER_CONFIG_GPIO_32_INIT `GPIO_MODE_INVALID
-`define USER_CONFIG_GPIO_33_INIT `GPIO_MODE_INVALID
-`define USER_CONFIG_GPIO_34_INIT `GPIO_MODE_INVALID
-`define USER_CONFIG_GPIO_35_INIT `GPIO_MODE_INVALID
-`define USER_CONFIG_GPIO_36_INIT `GPIO_MODE_INVALID
-`define USER_CONFIG_GPIO_37_INIT `GPIO_MODE_INVALID
+`define USER_CONFIG_GPIO_27_INIT `GPIO_MODE_USER_STD_INPUT_PULLDOWN
+`define USER_CONFIG_GPIO_28_INIT `GPIO_MODE_USER_STD_INPUT_PULLDOWN
+`define USER_CONFIG_GPIO_29_INIT `GPIO_MODE_USER_STD_INPUT_PULLDOWN
+`define USER_CONFIG_GPIO_30_INIT `GPIO_MODE_USER_STD_INPUT_PULLDOWN
+`define USER_CONFIG_GPIO_31_INIT `GPIO_MODE_USER_STD_INPUT_PULLDOWN
+`define USER_CONFIG_GPIO_32_INIT `GPIO_MODE_USER_STD_INPUT_PULLDOWN
+`define USER_CONFIG_GPIO_33_INIT `GPIO_MODE_USER_STD_INPUT_PULLDOWN
+`define USER_CONFIG_GPIO_34_INIT `GPIO_MODE_USER_STD_INPUT_PULLDOWN
+`define USER_CONFIG_GPIO_35_INIT `GPIO_MODE_USER_STD_INPUT_PULLDOWN
+`define USER_CONFIG_GPIO_36_INIT `GPIO_MODE_USER_STD_INPUT_PULLDOWN
+`define USER_CONFIG_GPIO_37_INIT `GPIO_MODE_USER_STD_INPUT_PULLDOWN
 
 `endif // __USER_DEFINES_H
\ No newline at end of file
diff --git a/verilog/rtl/user_defines.v.jinja2 b/verilog/rtl/user_defines.v.jinja2
index c935c87..811643c 100644
--- a/verilog/rtl/user_defines.v.jinja2
+++ b/verilog/rtl/user_defines.v.jinja2
@@ -25,20 +25,18 @@
 // Authoritive source of these MODE defs is: caravel/verilog/rtl/user_defines.v
 // Useful GPIO mode values.  These match the names used in defs.h.
 //
-`define GPIO_MODE_MGMT_STD_INPUT_NOPULL    13'h0403
-`define GPIO_MODE_MGMT_STD_INPUT_PULLDOWN  13'h0c01
-`define GPIO_MODE_MGMT_STD_INPUT_PULLUP    13'h0801
-`define GPIO_MODE_MGMT_STD_OUTPUT          13'h1809
-`define GPIO_MODE_MGMT_STD_BIDIRECTIONAL   13'h1801
-`define GPIO_MODE_MGMT_STD_ANALOG          13'h000b
 
-`define GPIO_MODE_USER_STD_INPUT_NOPULL    13'h0402
-`define GPIO_MODE_USER_STD_INPUT_PULLDOWN  13'h0c00
-`define GPIO_MODE_USER_STD_INPUT_PULLUP    13'h0800
-`define GPIO_MODE_USER_STD_OUTPUT          13'h1808
-`define GPIO_MODE_USER_STD_BIDIRECTIONAL   13'h1800
-`define GPIO_MODE_USER_STD_OUT_MONITORED   13'h1802
-`define GPIO_MODE_USER_STD_ANALOG          13'h000a
+`define GPIO_MODE_MGMT_STD_INPUT_NOPULL    10'h007
+`define GPIO_MODE_MGMT_STD_INPUT_PULLDOWN  10'h047
+`define GPIO_MODE_MGMT_STD_INPUT_PULLUP    10'h087
+`define GPIO_MODE_MGMT_STD_OUTPUT          10'h00b
+`define GPIO_MODE_MGMT_STD_BIDIRECTIONAL   10'h009
+
+`define GPIO_MODE_USER_STD_INPUT_NOPULL    10'h006
+`define GPIO_MODE_USER_STD_INPUT_PULLDOWN  10'h046
+`define GPIO_MODE_USER_STD_INPUT_PULLUP    10'h086
+`define GPIO_MODE_USER_STD_OUTPUT          10'h00a
+`define GPIO_MODE_USER_STD_BIDIRECTIONAL   10'h008
 
 // The power-on configuration for GPIO 0 to 4 is fixed and cannot be
 // modified (allowing the SPI and debug to always be accessible unless
@@ -54,14 +52,13 @@
 
 // tiny_user_project i/o
 // generated by configure.py
-
 {% for n in range(5, 38) -%}
 {%- if io_in_range[0] <= n < io_in_range[1] %}
 `define USER_CONFIG_GPIO_{{ n }}_INIT `GPIO_MODE_USER_STD_INPUT_NOPULL
 {%- elif io_out_range[0] <= n < io_out_range[1] %}
 `define USER_CONFIG_GPIO_{{ n }}_INIT `GPIO_MODE_USER_STD_OUTPUT
 {%- else %}
-`define USER_CONFIG_GPIO_{{ n }}_INIT `GPIO_MODE_INVALID
+`define USER_CONFIG_GPIO_{{ n }}_INIT `GPIO_MODE_USER_STD_INPUT_PULLDOWN
 {%- endif -%}
 {% endfor %}