diff --git a/verilog/rtl/control.v b/verilog/rtl/control.v
index c414c41..e899831 100644
--- a/verilog/rtl/control.v
+++ b/verilog/rtl/control.v
@@ -1,7 +1,5 @@
 // control module. Can't get out of error states except with reset
 
-timeunit 1ns; timeprecision 10ps;
-
 module control(
     input wire Clock, nReset,
     input wire [1:0] Ran,
@@ -36,7 +34,7 @@
 
 assign next_dice_value = gated[0] | gated[1] | gated[2] | gated[3] | gated[4] | gated[5];
 
-always_ff @(posedge Clock, negedge nReset) begin
+always@(posedge Clock, negedge nReset) begin
   if (!nReset) begin
     enable_reg <= 1'b0;
     dice_val <= 3'd1;
diff --git a/verilog/rtl/dice.v b/verilog/rtl/dice.v
index 5ee6d59..997958e 100644
--- a/verilog/rtl/dice.v
+++ b/verilog/rtl/dice.v
@@ -1,7 +1,5 @@
 // Structural top-level module of dice
 
-timeunit 1ns; timeprecision 10ps;
-
 module dice(
   input wire Clock, nReset,
   output wire TL, ML, BL, MC, TR, MR, BR
diff --git a/verilog/rtl/dtype_synth.v b/verilog/rtl/dtype_synth.v
index efeab9a..62f2d77 100644
--- a/verilog/rtl/dtype_synth.v
+++ b/verilog/rtl/dtype_synth.v
@@ -5,9 +5,8 @@
   input wire D, Clk, nRst
   );
 
-timeunit 1ns; timeprecision 10ps;
 
-always_ff @(posedge Clk, negedge nRst) begin
+always@(posedge Clk, negedge nRst) begin
   if(~nRst) begin
     Q  <= 1'b0;
     nQ <= 1'b1;
diff --git a/verilog/rtl/encoder.v b/verilog/rtl/encoder.v
index 33f0d5c..55f81a4 100644
--- a/verilog/rtl/encoder.v
+++ b/verilog/rtl/encoder.v
@@ -1,7 +1,5 @@
 // Behavioural model of LED encoder
 
-timeunit 1ns; timeprecision 10ps;
-
 module encoder(
   input wire [2:0] DiceValue,
   output wire L11, L12, L13, L21, L22, L23, L31, L32, L33
@@ -11,7 +9,7 @@
    // Reading left to right then down
    assign {L11, L21, L31, L12, L22, L32, L13, L23, L33} = output_leds;
    
-   always_comb begin
+   always@(*) begin
      case (DiceValue)
        3'd0: output_leds = 9'b000_000_000;
        3'd1: output_leds = 9'b000_010_000;
diff --git a/verilog/rtl/user_module.v b/verilog/rtl/user_module.v
index c9d1608..a6dad2d 100644
--- a/verilog/rtl/user_module.v
+++ b/verilog/rtl/user_module.v
@@ -22,4 +22,13 @@
     .pdm_out(pdm_out)
   );
 
+  wire [6:0] leds;
+  assign io_out[8:2] = leds;
+
+  dice dice0(
+  .Clock(io_in[8]), .nReset(io_in[9]),
+  .TL(leds[0]), .ML(leds[1]), .BL(leds[2]), .MC(leds[3]),
+  .TR(leds[4]), .MR(leds[5]), .BR(leds[6])
+);
+
 endmodule