blob: f026da438498cf02638eb26f33cd827b80b74ee8 [file] [log] [blame]
/root/pdm_and_dice_gf180-mpw0/configure.py
/root/pdm_and_dice_gf180-mpw0/openlane/tiny_user_project/config.json
/root/pdm_and_dice_gf180-mpw0/sdc/tiny_user_project.sdc
/root/pdm_and_dice_gf180-mpw0/sdc/user_module.sdc
/root/pdm_and_dice_gf180-mpw0/sdc/user_project_wrapper.sdc
/root/pdm_and_dice_gf180-mpw0/sdf/tiny_user_project.sdf
/root/pdm_and_dice_gf180-mpw0/sdf/user_module.sdf
/root/pdm_and_dice_gf180-mpw0/sdf/user_project_wrapper.sdf
/root/pdm_and_dice_gf180-mpw0/sdf/multicorner/nom/user_project_wrapper.ff.sdf
/root/pdm_and_dice_gf180-mpw0/sdf/multicorner/nom/user_project_wrapper.ss.sdf
/root/pdm_and_dice_gf180-mpw0/sdf/multicorner/nom/user_project_wrapper.tt.sdf
/root/pdm_and_dice_gf180-mpw0/spef/tiny_user_project.spef
/root/pdm_and_dice_gf180-mpw0/spef/user_module.spef
/root/pdm_and_dice_gf180-mpw0/spef/user_project_wrapper.spef
/root/pdm_and_dice_gf180-mpw0/spef/multicorner/user_project_wrapper.nom.spef
/root/pdm_and_dice_gf180-mpw0/verilog/includes/includes.gl+sdf.caravel_user_project
/root/pdm_and_dice_gf180-mpw0/verilog/includes/includes.gl.caravel_user_project
/root/pdm_and_dice_gf180-mpw0/verilog/includes/includes.rtl.caravel_user_project
/root/pdm_and_dice_gf180-mpw0/verilog/rtl/control.v
/root/pdm_and_dice_gf180-mpw0/verilog/rtl/dice.v
/root/pdm_and_dice_gf180-mpw0/verilog/rtl/dice_stim.v
/root/pdm_and_dice_gf180-mpw0/verilog/rtl/dtype_synth.v
/root/pdm_and_dice_gf180-mpw0/verilog/rtl/encoder.v
/root/pdm_and_dice_gf180-mpw0/verilog/rtl/pdm.v
/root/pdm_and_dice_gf180-mpw0/verilog/rtl/random.v
/root/pdm_and_dice_gf180-mpw0/verilog/rtl/tb_encoder.v
/root/pdm_and_dice_gf180-mpw0/verilog/rtl/tb_random.v
/root/pdm_and_dice_gf180-mpw0/verilog/rtl/tiny_user_project.v
/root/pdm_and_dice_gf180-mpw0/verilog/rtl/tiny_user_project.v.jinja2
/root/pdm_and_dice_gf180-mpw0/verilog/rtl/user_module.v
/root/pdm_and_dice_gf180-mpw0/verilog/rtl/user_module_tb.v