)]}'
{
  "commit": "037481c6604cbce4e31b53a360e5d62c29bc5159",
  "tree": "77c916848f19ba298b4e83f1ab00268dec61042b",
  "parents": [
    "5e6b0eaf7beddea09950fa4cb843eed92437a984"
  ],
  "author": {
    "name": "H-S-S-11",
    "email": "harry.saxon.snell@gmail.com",
    "time": "Sat Dec 03 01:46:20 2022 +0000"
  },
  "committer": {
    "name": "H-S-S-11",
    "email": "harry.saxon.snell@gmail.com",
    "time": "Sat Dec 03 01:46:20 2022 +0000"
  },
  "message": "change logic to reg\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "e899831594e4dd6d81f472ae0da5b7ae56c90225",
      "old_mode": 33188,
      "old_path": "verilog/rtl/control.v",
      "new_id": "5b39602b0c9d3b501f3c6ab0e07896554da45013",
      "new_mode": 33188,
      "new_path": "verilog/rtl/control.v"
    },
    {
      "type": "modify",
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      "old_mode": 33188,
      "old_path": "verilog/rtl/dtype_synth.v",
      "new_id": "2f8587328e91ba72f765d1cdae0265d49380cd7c",
      "new_mode": 33188,
      "new_path": "verilog/rtl/dtype_synth.v"
    },
    {
      "type": "modify",
      "old_id": "55f81a47baae1944e64ba631281f8dcf191a006c",
      "old_mode": 33188,
      "old_path": "verilog/rtl/encoder.v",
      "new_id": "92075933a0e02387eb7231b6606202fc391c7f4c",
      "new_mode": 33188,
      "new_path": "verilog/rtl/encoder.v"
    }
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}