change logic to reg
diff --git a/verilog/rtl/control.v b/verilog/rtl/control.v
index e899831..5b39602 100644
--- a/verilog/rtl/control.v
+++ b/verilog/rtl/control.v
@@ -6,10 +6,10 @@
output wire [2:0] DiceValue
);
-logic [2:0] dice_val, next_dice_value;
-logic n_1_or_6, n_2_or_5, n_3_or_4, enable_reg;
+reg [2:0] dice_val, next_dice_value;
+reg n_1_or_6, n_2_or_5, n_3_or_4, enable_reg;
-logic [2:0] gated[0:5];
+reg [2:0] gated[0:5];
assign n_1_or_6 = !((dice_val==3'd1) | (dice_val==3'd6));
assign n_2_or_5 = !((dice_val==3'd2) | (dice_val==3'd5));
diff --git a/verilog/rtl/dtype_synth.v b/verilog/rtl/dtype_synth.v
index 62f2d77..2f85873 100644
--- a/verilog/rtl/dtype_synth.v
+++ b/verilog/rtl/dtype_synth.v
@@ -1,7 +1,7 @@
// structural model of edge triggered D type
module dtype(
- output logic Q, nQ,
+ output reg Q, nQ,
input wire D, Clk, nRst
);
diff --git a/verilog/rtl/encoder.v b/verilog/rtl/encoder.v
index 55f81a4..9207593 100644
--- a/verilog/rtl/encoder.v
+++ b/verilog/rtl/encoder.v
@@ -4,7 +4,7 @@
input wire [2:0] DiceValue,
output wire L11, L12, L13, L21, L22, L23, L31, L32, L33
);
- logic [8:0] output_leds;
+ reg [8:0] output_leds;
// Reading left to right then down
assign {L11, L21, L31, L12, L22, L32, L13, L23, L33} = output_leds;
