Update to coincide with the most recent commit to the caravel
project. Added C code to control the input enable lines for
inputs coming from the user project. Since the example code assumes
one-way traffic, the output enable is just the inverse of the input
enable.
diff --git a/verilog/rtl/user_project_wrapper.v b/verilog/rtl/user_project_wrapper.v
index 17c2511..2a3462b 100644
--- a/verilog/rtl/user_project_wrapper.v
+++ b/verilog/rtl/user_project_wrapper.v
@@ -58,7 +58,7 @@
// Logic Analyzer Signals
input [127:0] la_data_in,
output [127:0] la_data_out,
- input [127:0] la_oen,
+ input [127:0] la_oenb,
// IOs
input [`MPRJ_IO_PADS-1:0] io_in,
@@ -112,7 +112,7 @@
.la_data_in(la_data_in),
.la_data_out(la_data_out),
- .la_oen (la_oen),
+ .la_oenb (la_oenb),
// IO Pads
