[DATA] Update macros (hardened with latest openlane)
diff --git a/verilog/rtl/user_proj_example.v b/verilog/rtl/user_proj_example.v
index b33e032..26081e9 100644
--- a/verilog/rtl/user_proj_example.v
+++ b/verilog/rtl/user_proj_example.v
@@ -39,14 +39,8 @@
parameter BITS = 32
)(
`ifdef USE_POWER_PINS
- inout vdda1, // User area 1 3.3V supply
- inout vdda2, // User area 2 3.3V supply
- inout vssa1, // User area 1 analog ground
- inout vssa2, // User area 2 analog ground
inout vccd1, // User area 1 1.8V supply
- inout vccd2, // User area 2 1.8v supply
inout vssd1, // User area 1 digital ground
- inout vssd2, // User area 2 digital ground
`endif
// Wishbone Slave ports (WB MI A)
diff --git a/verilog/rtl/user_project_wrapper.v b/verilog/rtl/user_project_wrapper.v
index 2a3462b..5ee1cee 100644
--- a/verilog/rtl/user_project_wrapper.v
+++ b/verilog/rtl/user_project_wrapper.v
@@ -83,16 +83,10 @@
/*--------------------------------------*/
user_proj_example mprj (
- `ifdef USE_POWER_PINS
- .vdda1(vdda1), // User area 1 3.3V power
- .vdda2(vdda2), // User area 2 3.3V power
- .vssa1(vssa1), // User area 1 analog ground
- .vssa2(vssa2), // User area 2 analog ground
+`ifdef USE_POWER_PINS
.vccd1(vccd1), // User area 1 1.8V power
- .vccd2(vccd2), // User area 2 1.8V power
.vssd1(vssd1), // User area 1 digital ground
- .vssd2(vssd2), // User area 2 digital ground
- `endif
+`endif
.wb_clk_i(wb_clk_i),
.wb_rst_i(wb_rst_i),
