commit 609ec9853f5276f9999e88fdb953ded5c12c300d
author manarabdelaty <manarabdelatty@aucegypt.edu> Wed Apr 21 17:00:06 2021 +0200
committer manarabdelaty <manarabdelatty@aucegypt.edu> Wed Apr 21 17:00:06 2021 +0200
tree 16573c7af62b5aa59d19804c16918adc9eeddd0c
parent 65049f1a20db4ac62025f26e7e1e4a121c74e440

[DATA] Update views

verilog/gl/user_project_wrapper.v

diff --git a/verilog/gl/user_project_wrapper.v b/verilog/gl/user_project_wrapper.v
index c58b91a..423c7b0 100644
--- a/verilog/gl/user_project_wrapper.v
+++ b/verilog/gl/user_project_wrapper.v
@@ -39,7 +39,7 @@
  input vssa1;
  input vdda2;
  input vssa2;
- inout [30:0] analog_io;
+ inout [28:0] analog_io;
  input [37:0] io_in;
  output [37:0] io_oeb;
  output [37:0] io_out;