diff --git a/info.yaml b/info.yaml
index 65e82e8..51ee710 100644
--- a/info.yaml
+++ b/info.yaml
@@ -1,11 +1,10 @@
 --- 
 # TinyTapeout project information
 project:
-  wokwi_id:    334445762078310996        # If using wokwi, set this to your project's ID
-#  source_files:        # If using an HDL, set wokwi_id as 0 and uncomment and list your source files here
-#    - verilog/rtl/counter.v
-#    - verilog/rtl/decoder.v
-#  top_module:  "seven_segment_seconds"      # put the name of your top module here, make it unique by prepending your github username
+  wokwi_id:    0        # If using wokwi, set this to your project's ID
+  source_files:        # If using an HDL, set wokwi_id as 0 and uncomment and list your source files here
+    - verilog/rtl/beepboop.v
+  top_module:  "beepboop"      # put the name of your top module here, make it unique by prepending your github username
 
 # As everyone will have access to all designs, try to make it easy for someone new to your design to know what
 # it does and how to operate it.
@@ -14,33 +13,33 @@
 #
 # This info will be automatically collected and used to make a datasheet for the chip.
 documentation: 
-  author:       ""      # Your name
+  author:       "Anish Singhani"      # Your name
   discord:      ""      # Your discord handle - make sure to include the # part as well
-  title:        ""      # Project title
-  description:  ""      # Short description of what your project does
-  how_it_works: ""      # Longer description of how the project works
-  how_to_test:  ""      # Instructions on how someone could test your project, include things like what buttons do what and how to set the clock if needed
-  external_hw:  ""      # Describe any external hardware needed
-  language:     "wokwi" # other examples include Verilog, Amaranth, VHDL, etc
+  title:        "Beep Boop Traffic Light Controller"      # Project title
+  description:  "Sequencer for a traffic light with a walk button, with timings tuned to match the iconic 'beep boop' streetlight formerly installed in front of Carnegie Mellon University"      # Short description of what your project does
+  how_it_works: "Press the walk button and the traffic light will turn red, then the walk signal and 'beep boop' will begin"      # Longer description of how the project works
+  how_to_test:  "See inputs and outputs"      # Instructions on how someone could test your project, include things like what buttons do what and how to set the clock if needed
+  external_hw:  "LEDs, noisemaker, button"      # Describe any external hardware needed
+  language:     "SystemVerilog" # other examples include Verilog, Amaranth, VHDL, etc
   doc_link:     ""      # URL to longer form documentation, eg the README.md in your repository
   clock_hz:     0       # Clock frequency in Hz (if required) we are expecting max clock frequency to be ~6khz. Provided on input 0.
   picture:      ""      # relative path to a picture in your repository
+
   inputs:               # a description of what the inputs do
     - clock
     - reset
-    - none
+    - walk button
     - none
     - none
     - none
     - none
     - none
   outputs:
-    - segment a         # a description of what the outputs do
-    - segment b
-    - segment c
-    - segment d
-    - segment e
-    - segment f
-    - segment g
+    - red
+    - yellow
+    - green
+    - walk
+    - no walk
+    - noisemaker
     - none
-
+    - none
diff --git a/verilog/rtl/beepboop.v b/verilog/rtl/beepboop.v
new file mode 100644
index 0000000..9e97576
--- /dev/null
+++ b/verilog/rtl/beepboop.v
@@ -0,0 +1,37 @@
+module beepboop (
+        io_in,
+        io_out
+);
+        input [7:0] io_in;
+        output wire [7:0] io_out;
+        wire clock = io_in[0];
+        wire reset = io_in[1];
+        wire btn = io_in[2];
+        reg red;
+        reg yellow;
+        reg green;
+        reg walk;
+        reg no_walk;
+        reg the_beepbooper;
+        assign io_out = {2'b00, the_beepbooper, no_walk, walk, green, yellow, red};
+        reg [15:0] counter;
+        always @(posedge clock)
+                if (reset)
+                        counter <= 0;
+                else begin
+                        if (counter != 0)
+                                counter <= counter + 1;
+                        if (counter >= 2200)
+                                counter <= 0;
+                        if ((counter == 0) && btn)
+                                counter <= 1;
+                end
+        always @(*) begin
+                green = (counter == 0) || (counter >= 2200);
+                yellow = (counter > 0) && (counter < 200);
+                red = (counter >= 200) && (counter < 2200);
+                walk = (counter > 300) && (counter < 1500);
+                the_beepbooper = walk;
+                no_walk = (((((counter >= 1500) && (counter < 1600)) || ((counter >= 1700) && (counter < 1800))) || ((counter >= 1900) && (counter < 2000))) || (counter >= 2100)) || (counter <= 300);
+        end
+endmodule
diff --git a/verilog/rtl/user_module.v b/verilog/rtl/user_module.v
deleted file mode 100644
index aea8267..0000000
--- a/verilog/rtl/user_module.v
+++ /dev/null
@@ -1,88 +0,0 @@
-/* Automatically generated from https://wokwi.com/projects/334445762078310996 */
-
-`default_nettype none
-
-module user_module_334445762078310996(
-  input [7:0] io_in,
-  output [7:0] io_out
-);
-  wire net1 = 1'b1;
-  wire net2 = 1'b0;
-  wire net3;
-  wire net4;
-  wire net5;
-  wire net6;
-  wire net7;
-  wire net8 = 1'b1;
-  wire net9 = 1'b0;
-  wire net10;
-  wire net11;
-  wire net12 = 1'b1;
-  wire net13 = 1'b0;
-  wire net14;
-  wire net15 = 1'b1;
-  wire net16 = 1'b0;
-  wire net17;
-  wire net18 = 1'b0;
-  wire net19 = 1'b1;
-  wire net20;
-  wire net21 = 1'b1;
-  wire net22;
-  wire net23;
-  wire net24 = 1'b0;
-  wire net25 = 1'b0;
-
-  and_cell gate1 (
-    .a (net3)
-  );
-  or_cell gate2 (
-
-  );
-  xor_cell gate3 (
-
-  );
-  nand_cell gate4 (
-    .a (net4),
-    .b (net5),
-    .out (net6)
-  );
-  not_cell gate5 (
-    .in (net7),
-    .out (net5)
-  );
-  buffer_cell gate6 (
-
-  );
-  mux_cell mux1 (
-    .a (net8),
-    .b (net9),
-    .sel (net10),
-    .out (net11)
-  );
-  dff_cell flipflop1 (
-
-  );
-  mux_cell mux2 (
-    .a (net12),
-    .b (net13),
-    .sel (net10),
-    .out (net14)
-  );
-  mux_cell mux3 (
-    .a (net15),
-    .b (net16),
-    .sel (net10),
-    .out (net17)
-  );
-  mux_cell mux4 (
-    .a (net18),
-    .b (net19),
-    .sel (net10),
-    .out (net20)
-  );
-  and_cell gate7 (
-    .a (net22),
-    .b (net23),
-    .out (net4)
-  );
-endmodule