| commit | 90e5d115575c99913c33b9bbb6b32de3c6e0f379 | [log] [tgz] |
|---|---|---|
| author | Russell L Friesenhahn <russellf@utexas.edu> | Mon Dec 05 23:41:16 2022 -0600 |
| committer | Russell L Friesenhahn <russellf@utexas.edu> | Mon Dec 05 23:41:16 2022 -0600 |
| tree | a7727dbfca4c6c1bf844dcd9ebe5eb7c2e79c0c8 | |
| parent | 062feae2e92178185752a69ef433f88d955fa49e [diff] |
Update submodule url
diff --git a/.gitmodules b/.gitmodules index db39e02..04b4e37 100644 --- a/.gitmodules +++ b/.gitmodules
@@ -1,3 +1,3 @@ [submodule "verilog/rtl/vga-clock"] path = verilog/rtl/vga-clock - url = https://github.com/mattvenn/vga-clock + url = https://github.com/russellfriesenhahn/vga-clock