)]}'
{
  "commit": "61203772a69ed3e69cc0e43e330ef352f89a5ad7",
  "tree": "52d1674c3cb959ff036a4582df8d7ad47283656d",
  "parents": [
    "2756f5c7e7f99c6effb4dd675a5653c17851d65a"
  ],
  "author": {
    "name": "Matt Venn",
    "email": "matt@mattvenn.net",
    "time": "Tue Nov 29 10:52:05 2022 +0100"
  },
  "committer": {
    "name": "Matt Venn",
    "email": "matt@mattvenn.net",
    "time": "Tue Nov 29 10:52:05 2022 +0100"
  },
  "message": "improve name\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "83d2a6ea1337d1bf4a9a24bb1a6ba5f3d62c304b",
      "old_mode": 33188,
      "old_path": "verilog/rtl/wrapped_vga_clock.v",
      "new_id": "ef750499a36e80449f7b1762e30fef9edf554901",
      "new_mode": 33188,
      "new_path": "verilog/rtl/wrapped_vga_clock.v"
    }
  ]
}