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foss-eda-tools
/
third_party
/
shuttle
/
gf180mcu
/
mpw-000
/
slot-002
/
2bd7875d0d0cef2514e957814b3bc93e1a098e24
commit
2bd7875d0d0cef2514e957814b3bc93e1a098e24
[
log
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author
Russell L Friesenhahn <russellf@utexas.edu>
Tue Dec 06 01:08:46 2022 -0600
committer
Russell L Friesenhahn <russellf@utexas.edu>
Tue Dec 06 01:08:46 2022 -0600
tree
88a003dc826349b37b5906f9bc715c9960d4cf83
parent
3cd2964c3cab6c25f37191347649e1e704d5542e
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Building and working
def/user_project_wrapper.def
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def/wrapped_vga_clock.def
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gds/user_project_wrapper.gds.gz
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gds/wrapped_vga_clock.gds.gz
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lef/user_project_wrapper.lef
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lef/wrapped_vga_clock.lef
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lib/user_project_wrapper.lib
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mag/user_project_wrapper.mag
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maglef/user_project_wrapper.mag
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openlane/wrapped_vga_clock/config.tcl
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sdc/user_project_wrapper.sdc
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sdf/multicorner/nom/user_project_wrapper.ff.sdf
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sdf/multicorner/nom/user_project_wrapper.ss.sdf
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sdf/multicorner/nom/user_project_wrapper.tt.sdf
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sdf/user_project_wrapper.sdf
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signoff/user_project_wrapper/PDK_SOURCES
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signoff/user_project_wrapper/metrics.csv
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spef/multicorner/user_project_wrapper.nom.spef
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spef/user_project_wrapper.spef
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verilog/gl/wrapped_vga_clock.v
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verilog/rtl/wrapped_vga_clock.v
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21 files changed
tree: 88a003dc826349b37b5906f9bc715c9960d4cf83
.github/
def/
docs/
gds/
lef/
lib/
mag/
maglef/
openlane/
sdc/
sdf/
signoff/
spef/
spi/
verilog/
.gitignore
.gitmodules
LICENSE
Makefile
README.md
README.md
VGA Clock for GF180
VGA clock info:
https://www.zerotoasiccourse.com/post/vga_clock/
VGA clock RTL:
https://github.com/mattvenn/vga-clock
PCB
https://github.com/mattvenn/vga_clock_pcb
