ready for submission
diff --git a/.gitmodules b/.gitmodules
new file mode 100644
index 0000000..db39e02
--- /dev/null
+++ b/.gitmodules
@@ -0,0 +1,3 @@
+[submodule "verilog/rtl/vga-clock"]
+ path = verilog/rtl/vga-clock
+ url = https://github.com/mattvenn/vga-clock
diff --git a/def/user_project_wrapper.def b/def/user_project_wrapper.def
index dd6263e..fc72f79 100644
--- a/def/user_project_wrapper.def
+++ b/def/user_project_wrapper.def
@@ -769,12 +769,13 @@
TRACKS Y 560 DO 5357 STEP 1120 LAYER Metal5 ;
GCELLGRID X 0 DO 357 STEP 16800 ;
GCELLGRID Y 0 DO 357 STEP 16800 ;
-VIAS 2 ;
+VIAS 3 ;
- via4_5_6200_6200_4_4_1240_1240 + VIARULE Via4_GEN_HH + CUTSIZE 520 520 + LAYERS Metal4 Via4 Metal5 + CUTSPACING 720 720 + ENCLOSURE 360 120 120 360 + ROWCOL 4 4 ;
+ - via4_5_6200_4500_4_4_1240_1240 + VIARULE Via4_GEN_HH + CUTSIZE 520 520 + LAYERS Metal4 Via4 Metal5 + CUTSPACING 720 720 + ENCLOSURE 360 120 120 130 + ROWCOL 4 4 ;
- via4_5_3200_6200_4_2_1240_1240 + VIARULE Via4_GEN_HH + CUTSIZE 520 520 + LAYERS Metal4 Via4 Metal5 + CUTSPACING 720 720 + ENCLOSURE 720 360 120 360 + ROWCOL 4 2 ;
END VIAS
COMPONENTS 1 ;
- - mprj user_proj_example + FIXED ( 1175000 1690000 ) N ;
+ - wrapped_vga_clock wrapped_vga_clock + FIXED ( 1175000 1690000 ) N ;
END COMPONENTS
PINS 418 ;
- io_in[0] + NET io_in[0] + DIRECTION INPUT + USE SIGNAL
@@ -2069,21 +2070,17 @@
+ LAYER Metal4 ( 290660 -5813800 ) ( 296860 177320 )
+ LAYER Metal4 ( 110660 -5813800 ) ( 116860 177320 )
+ LAYER Metal4 ( -69340 -5813800 ) ( -63140 177320 )
- + LAYER Metal4 ( -249340 -2937720 ) ( -243140 177320 )
- + LAYER Metal4 ( -249340 -5813800 ) ( -243140 -4116840 )
- + LAYER Metal4 ( -429340 -2944100 ) ( -423140 177320 )
- + LAYER Metal4 ( -429340 -5813800 ) ( -423140 -4118300 )
- + LAYER Metal4 ( -609340 -2944100 ) ( -603140 177320 )
- + LAYER Metal4 ( -609340 -5813800 ) ( -603140 -4118300 )
- + LAYER Metal4 ( -789340 -2944100 ) ( -783140 177320 )
- + LAYER Metal4 ( -789340 -5813800 ) ( -783140 -4118300 )
- + LAYER Metal4 ( -969340 -2944100 ) ( -963140 177320 )
- + LAYER Metal4 ( -969340 -5813800 ) ( -963140 -4118300 )
- + LAYER Metal4 ( -1149340 -2944100 ) ( -1143140 177320 )
- + LAYER Metal4 ( -1149340 -5813800 ) ( -1143140 -4118300 )
+ + LAYER Metal4 ( -249340 -5813800 ) ( -243140 177320 )
+ + LAYER Metal4 ( -429340 -5813800 ) ( -423140 177320 )
+ + LAYER Metal4 ( -609340 -5813800 ) ( -603140 177320 )
+ + LAYER Metal4 ( -789340 -5813800 ) ( -783140 177320 )
+ + LAYER Metal4 ( -969340 -5813800 ) ( -963140 177320 )
+ + LAYER Metal4 ( -1149340 -5813800 ) ( -1143140 177320 )
+ LAYER Metal4 ( -1329340 -5813800 ) ( -1323140 177320 )
- + LAYER Metal4 ( -1509340 -5813800 ) ( -1503140 177320 )
- + LAYER Metal4 ( -1689340 -5813800 ) ( -1683140 177320 )
+ + LAYER Metal4 ( -1509340 -3670980 ) ( -1503140 177320 )
+ + LAYER Metal4 ( -1509340 -5813800 ) ( -1503140 -3934620 )
+ + LAYER Metal4 ( -1689340 -3670980 ) ( -1683140 177320 )
+ + LAYER Metal4 ( -1689340 -5813800 ) ( -1683140 -3934620 )
+ LAYER Metal4 ( -1869340 -5813800 ) ( -1863140 177320 )
+ LAYER Metal4 ( -2049340 -5813800 ) ( -2043140 177320 )
+ LAYER Metal4 ( -2229340 -5813800 ) ( -2223140 177320 )
@@ -2150,18 +2147,15 @@
+ LAYER Metal4 ( -32140 -5873800 ) ( -25940 117320 )
+ LAYER Metal4 ( -212140 -5873800 ) ( -205940 117320 )
+ LAYER Metal4 ( -392140 -5873800 ) ( -385940 117320 )
- + LAYER Metal4 ( -572140 -3004100 ) ( -565940 117320 )
- + LAYER Metal4 ( -572140 -5873800 ) ( -565940 -4178300 )
- + LAYER Metal4 ( -752140 -3004100 ) ( -745940 117320 )
- + LAYER Metal4 ( -752140 -5873800 ) ( -745940 -4178300 )
- + LAYER Metal4 ( -932140 -3004100 ) ( -925940 117320 )
- + LAYER Metal4 ( -932140 -5873800 ) ( -925940 -4178300 )
- + LAYER Metal4 ( -1112140 -3004100 ) ( -1105940 117320 )
- + LAYER Metal4 ( -1112140 -5873800 ) ( -1105940 -4178300 )
+ + LAYER Metal4 ( -572140 -5873800 ) ( -565940 117320 )
+ + LAYER Metal4 ( -752140 -5873800 ) ( -745940 117320 )
+ + LAYER Metal4 ( -932140 -5873800 ) ( -925940 117320 )
+ + LAYER Metal4 ( -1112140 -5873800 ) ( -1105940 117320 )
+ LAYER Metal4 ( -1292140 -5873800 ) ( -1285940 117320 )
- + LAYER Metal4 ( -1472140 -2997720 ) ( -1465940 117320 )
+ + LAYER Metal4 ( -1472140 -3601400 ) ( -1465940 117320 )
+ LAYER Metal4 ( -1472140 -5873800 ) ( -1465940 -4176840 )
- + LAYER Metal4 ( -1652140 -5873800 ) ( -1645940 117320 )
+ + LAYER Metal4 ( -1652140 -3730980 ) ( -1645940 117320 )
+ + LAYER Metal4 ( -1652140 -5873800 ) ( -1645940 -3994620 )
+ LAYER Metal4 ( -1832140 -5873800 ) ( -1825940 117320 )
+ LAYER Metal4 ( -2012140 -5873800 ) ( -2005940 117320 )
+ LAYER Metal4 ( -2192140 -5873800 ) ( -2185940 117320 )
@@ -2601,63 +2595,16 @@
END PINS
SPECIALNETS 2 ;
- vdd ( PIN vdd ) ( * vdd ) + USE POWER
- + ROUTED Metal4 0 + SHAPE STRIPE ( 2933680 2757040 ) via4_5_6200_6200_4_4_1240_1240
- NEW Metal4 0 + SHAPE STRIPE ( 2933680 2577040 ) via4_5_6200_6200_4_4_1240_1240
- NEW Metal4 0 + SHAPE STRIPE ( 2933680 2397040 ) via4_5_6200_6200_4_4_1240_1240
- NEW Metal4 0 + SHAPE STRIPE ( 2933680 2217040 ) via4_5_6200_6200_4_4_1240_1240
- NEW Metal4 0 + SHAPE STRIPE ( 2933680 2037040 ) via4_5_6200_6200_4_4_1240_1240
- NEW Metal4 0 + SHAPE STRIPE ( 2933680 1857040 ) via4_5_6200_6200_4_4_1240_1240
- NEW Metal4 0 + SHAPE STRIPE ( 2757080 2757040 ) via4_5_3200_6200_4_2_1240_1240
- NEW Metal4 0 + SHAPE STRIPE ( 2757080 2577040 ) via4_5_3200_6200_4_2_1240_1240
- NEW Metal4 0 + SHAPE STRIPE ( 2757080 2397040 ) via4_5_3200_6200_4_2_1240_1240
- NEW Metal4 0 + SHAPE STRIPE ( 2757080 2217040 ) via4_5_3200_6200_4_2_1240_1240
- NEW Metal4 0 + SHAPE STRIPE ( 2757080 2037040 ) via4_5_3200_6200_4_2_1240_1240
- NEW Metal4 0 + SHAPE STRIPE ( 2757080 1857040 ) via4_5_3200_6200_4_2_1240_1240
- NEW Metal4 0 + SHAPE STRIPE ( 2449880 2757040 ) via4_5_3200_6200_4_2_1240_1240
- NEW Metal4 0 + SHAPE STRIPE ( 2449880 2577040 ) via4_5_3200_6200_4_2_1240_1240
- NEW Metal4 0 + SHAPE STRIPE ( 2449880 2397040 ) via4_5_3200_6200_4_2_1240_1240
- NEW Metal4 0 + SHAPE STRIPE ( 2449880 2217040 ) via4_5_3200_6200_4_2_1240_1240
- NEW Metal4 0 + SHAPE STRIPE ( 2449880 2037040 ) via4_5_3200_6200_4_2_1240_1240
- NEW Metal4 0 + SHAPE STRIPE ( 2449880 1857040 ) via4_5_3200_6200_4_2_1240_1240
- NEW Metal4 0 + SHAPE STRIPE ( 2142680 2757040 ) via4_5_3200_6200_4_2_1240_1240
- NEW Metal4 0 + SHAPE STRIPE ( 2142680 2577040 ) via4_5_3200_6200_4_2_1240_1240
- NEW Metal4 0 + SHAPE STRIPE ( 2142680 2397040 ) via4_5_3200_6200_4_2_1240_1240
- NEW Metal4 0 + SHAPE STRIPE ( 2142680 2217040 ) via4_5_3200_6200_4_2_1240_1240
- NEW Metal4 0 + SHAPE STRIPE ( 2142680 2037040 ) via4_5_3200_6200_4_2_1240_1240
- NEW Metal4 0 + SHAPE STRIPE ( 2142680 1857040 ) via4_5_3200_6200_4_2_1240_1240
- NEW Metal4 0 + SHAPE STRIPE ( 1835480 2757040 ) via4_5_3200_6200_4_2_1240_1240
- NEW Metal4 0 + SHAPE STRIPE ( 1835480 2577040 ) via4_5_3200_6200_4_2_1240_1240
- NEW Metal4 0 + SHAPE STRIPE ( 1835480 2397040 ) via4_5_3200_6200_4_2_1240_1240
- NEW Metal4 0 + SHAPE STRIPE ( 1835480 2217040 ) via4_5_3200_6200_4_2_1240_1240
- NEW Metal4 0 + SHAPE STRIPE ( 1835480 2037040 ) via4_5_3200_6200_4_2_1240_1240
- NEW Metal4 0 + SHAPE STRIPE ( 1835480 1857040 ) via4_5_3200_6200_4_2_1240_1240
- NEW Metal4 0 + SHAPE STRIPE ( 1673680 2757040 ) via4_5_6200_6200_4_4_1240_1240
- NEW Metal4 0 + SHAPE STRIPE ( 1673680 2577040 ) via4_5_6200_6200_4_4_1240_1240
- NEW Metal4 0 + SHAPE STRIPE ( 1673680 2397040 ) via4_5_6200_6200_4_4_1240_1240
- NEW Metal4 0 + SHAPE STRIPE ( 1673680 2217040 ) via4_5_6200_6200_4_4_1240_1240
+ + ROUTED Metal4 0 + SHAPE STRIPE ( 1673680 2217040 ) via4_5_6200_6200_4_4_1240_1240
NEW Metal4 0 + SHAPE STRIPE ( 1673680 2037040 ) via4_5_6200_6200_4_4_1240_1240
NEW Metal4 0 + SHAPE STRIPE ( 1673680 1857040 ) via4_5_6200_6200_4_4_1240_1240
- NEW Metal4 0 + SHAPE STRIPE ( 1528280 2757040 ) via4_5_3200_6200_4_2_1240_1240
- NEW Metal4 0 + SHAPE STRIPE ( 1528280 2577040 ) via4_5_3200_6200_4_2_1240_1240
- NEW Metal4 0 + SHAPE STRIPE ( 1528280 2397040 ) via4_5_3200_6200_4_2_1240_1240
NEW Metal4 0 + SHAPE STRIPE ( 1528280 2217040 ) via4_5_3200_6200_4_2_1240_1240
NEW Metal4 0 + SHAPE STRIPE ( 1528280 2037040 ) via4_5_3200_6200_4_2_1240_1240
NEW Metal4 0 + SHAPE STRIPE ( 1528280 1857040 ) via4_5_3200_6200_4_2_1240_1240
- NEW Metal4 0 + SHAPE STRIPE ( 1493680 2757040 ) via4_5_6200_6200_4_4_1240_1240
- NEW Metal4 0 + SHAPE STRIPE ( 1493680 2577040 ) via4_5_6200_6200_4_4_1240_1240
- NEW Metal4 0 + SHAPE STRIPE ( 1493680 2397040 ) via4_5_6200_6200_4_4_1240_1240
NEW Metal4 0 + SHAPE STRIPE ( 1493680 2217040 ) via4_5_6200_6200_4_4_1240_1240
- NEW Metal4 0 + SHAPE STRIPE ( 1493680 2037040 ) via4_5_6200_6200_4_4_1240_1240
NEW Metal4 0 + SHAPE STRIPE ( 1493680 1857040 ) via4_5_6200_6200_4_4_1240_1240
- NEW Metal4 0 + SHAPE STRIPE ( 1313680 2757040 ) via4_5_6200_6200_4_4_1240_1240
- NEW Metal4 0 + SHAPE STRIPE ( 1313680 2577040 ) via4_5_6200_6200_4_4_1240_1240
- NEW Metal4 0 + SHAPE STRIPE ( 1313680 2397040 ) via4_5_6200_6200_4_4_1240_1240
NEW Metal4 0 + SHAPE STRIPE ( 1313680 2217040 ) via4_5_6200_6200_4_4_1240_1240
- NEW Metal4 0 + SHAPE STRIPE ( 1313680 2037040 ) via4_5_6200_6200_4_4_1240_1240
NEW Metal4 0 + SHAPE STRIPE ( 1313680 1857040 ) via4_5_6200_6200_4_4_1240_1240
- NEW Metal4 0 + SHAPE STRIPE ( 1221080 2757040 ) via4_5_3200_6200_4_2_1240_1240
- NEW Metal4 0 + SHAPE STRIPE ( 1221080 2577040 ) via4_5_3200_6200_4_2_1240_1240
- NEW Metal4 0 + SHAPE STRIPE ( 1221080 2397040 ) via4_5_3200_6200_4_2_1240_1240
NEW Metal4 0 + SHAPE STRIPE ( 1221080 2217040 ) via4_5_3200_6200_4_2_1240_1240
NEW Metal4 0 + SHAPE STRIPE ( 1221080 2037040 ) via4_5_3200_6200_4_2_1240_1240
NEW Metal4 0 + SHAPE STRIPE ( 1221080 1857040 ) via4_5_3200_6200_4_2_1240_1240
@@ -2711,21 +2658,17 @@
NEW Metal4 6200 + SHAPE STRIPE ( 3293680 3240 ) ( 3293680 5994360 )
NEW Metal4 6200 + SHAPE STRIPE ( 3113680 3240 ) ( 3113680 5994360 )
NEW Metal4 6200 + SHAPE STRIPE ( 2933680 3240 ) ( 2933680 5994360 )
- NEW Metal4 6200 + SHAPE STRIPE ( 2753680 2879320 ) ( 2753680 5994360 )
- NEW Metal4 6200 + SHAPE STRIPE ( 2753680 3240 ) ( 2753680 1700200 )
- NEW Metal4 6200 + SHAPE STRIPE ( 2573680 2872940 ) ( 2573680 5994360 )
- NEW Metal4 6200 + SHAPE STRIPE ( 2573680 3240 ) ( 2573680 1698740 )
- NEW Metal4 6200 + SHAPE STRIPE ( 2393680 2872940 ) ( 2393680 5994360 )
- NEW Metal4 6200 + SHAPE STRIPE ( 2393680 3240 ) ( 2393680 1698740 )
- NEW Metal4 6200 + SHAPE STRIPE ( 2213680 2872940 ) ( 2213680 5994360 )
- NEW Metal4 6200 + SHAPE STRIPE ( 2213680 3240 ) ( 2213680 1698740 )
- NEW Metal4 6200 + SHAPE STRIPE ( 2033680 2872940 ) ( 2033680 5994360 )
- NEW Metal4 6200 + SHAPE STRIPE ( 2033680 3240 ) ( 2033680 1698740 )
- NEW Metal4 6200 + SHAPE STRIPE ( 1853680 2872940 ) ( 1853680 5994360 )
- NEW Metal4 6200 + SHAPE STRIPE ( 1853680 3240 ) ( 1853680 1698740 )
+ NEW Metal4 6200 + SHAPE STRIPE ( 2753680 3240 ) ( 2753680 5994360 )
+ NEW Metal4 6200 + SHAPE STRIPE ( 2573680 3240 ) ( 2573680 5994360 )
+ NEW Metal4 6200 + SHAPE STRIPE ( 2393680 3240 ) ( 2393680 5994360 )
+ NEW Metal4 6200 + SHAPE STRIPE ( 2213680 3240 ) ( 2213680 5994360 )
+ NEW Metal4 6200 + SHAPE STRIPE ( 2033680 3240 ) ( 2033680 5994360 )
+ NEW Metal4 6200 + SHAPE STRIPE ( 1853680 3240 ) ( 1853680 5994360 )
NEW Metal4 6200 + SHAPE STRIPE ( 1673680 3240 ) ( 1673680 5994360 )
- NEW Metal4 6200 + SHAPE STRIPE ( 1493680 3240 ) ( 1493680 5994360 )
- NEW Metal4 6200 + SHAPE STRIPE ( 1313680 3240 ) ( 1313680 5994360 )
+ NEW Metal4 6200 + SHAPE STRIPE ( 1493680 2146060 ) ( 1493680 5994360 )
+ NEW Metal4 6200 + SHAPE STRIPE ( 1493680 3240 ) ( 1493680 1882420 )
+ NEW Metal4 6200 + SHAPE STRIPE ( 1313680 2146060 ) ( 1313680 5994360 )
+ NEW Metal4 6200 + SHAPE STRIPE ( 1313680 3240 ) ( 1313680 1882420 )
NEW Metal4 6200 + SHAPE STRIPE ( 1133680 3240 ) ( 1133680 5994360 )
NEW Metal4 6200 + SHAPE STRIPE ( 953680 3240 ) ( 953680 5994360 )
NEW Metal4 6200 + SHAPE STRIPE ( 773680 3240 ) ( 773680 5994360 )
@@ -3385,6 +3328,12 @@
NEW Metal4 0 + SHAPE STRIPE ( 2753680 3297040 ) via4_5_6200_6200_4_4_1240_1240
NEW Metal4 0 + SHAPE STRIPE ( 2753680 3117040 ) via4_5_6200_6200_4_4_1240_1240
NEW Metal4 0 + SHAPE STRIPE ( 2753680 2937040 ) via4_5_6200_6200_4_4_1240_1240
+ NEW Metal4 0 + SHAPE STRIPE ( 2753680 2757040 ) via4_5_6200_6200_4_4_1240_1240
+ NEW Metal4 0 + SHAPE STRIPE ( 2753680 2577040 ) via4_5_6200_6200_4_4_1240_1240
+ NEW Metal4 0 + SHAPE STRIPE ( 2753680 2397040 ) via4_5_6200_6200_4_4_1240_1240
+ NEW Metal4 0 + SHAPE STRIPE ( 2753680 2217040 ) via4_5_6200_6200_4_4_1240_1240
+ NEW Metal4 0 + SHAPE STRIPE ( 2753680 2037040 ) via4_5_6200_6200_4_4_1240_1240
+ NEW Metal4 0 + SHAPE STRIPE ( 2753680 1857040 ) via4_5_6200_6200_4_4_1240_1240
NEW Metal4 0 + SHAPE STRIPE ( 2753680 1677040 ) via4_5_6200_6200_4_4_1240_1240
NEW Metal4 0 + SHAPE STRIPE ( 2753680 1497040 ) via4_5_6200_6200_4_4_1240_1240
NEW Metal4 0 + SHAPE STRIPE ( 2753680 1317040 ) via4_5_6200_6200_4_4_1240_1240
@@ -3414,6 +3363,12 @@
NEW Metal4 0 + SHAPE STRIPE ( 2573680 3297040 ) via4_5_6200_6200_4_4_1240_1240
NEW Metal4 0 + SHAPE STRIPE ( 2573680 3117040 ) via4_5_6200_6200_4_4_1240_1240
NEW Metal4 0 + SHAPE STRIPE ( 2573680 2937040 ) via4_5_6200_6200_4_4_1240_1240
+ NEW Metal4 0 + SHAPE STRIPE ( 2573680 2757040 ) via4_5_6200_6200_4_4_1240_1240
+ NEW Metal4 0 + SHAPE STRIPE ( 2573680 2577040 ) via4_5_6200_6200_4_4_1240_1240
+ NEW Metal4 0 + SHAPE STRIPE ( 2573680 2397040 ) via4_5_6200_6200_4_4_1240_1240
+ NEW Metal4 0 + SHAPE STRIPE ( 2573680 2217040 ) via4_5_6200_6200_4_4_1240_1240
+ NEW Metal4 0 + SHAPE STRIPE ( 2573680 2037040 ) via4_5_6200_6200_4_4_1240_1240
+ NEW Metal4 0 + SHAPE STRIPE ( 2573680 1857040 ) via4_5_6200_6200_4_4_1240_1240
NEW Metal4 0 + SHAPE STRIPE ( 2573680 1677040 ) via4_5_6200_6200_4_4_1240_1240
NEW Metal4 0 + SHAPE STRIPE ( 2573680 1497040 ) via4_5_6200_6200_4_4_1240_1240
NEW Metal4 0 + SHAPE STRIPE ( 2573680 1317040 ) via4_5_6200_6200_4_4_1240_1240
@@ -3443,6 +3398,12 @@
NEW Metal4 0 + SHAPE STRIPE ( 2393680 3297040 ) via4_5_6200_6200_4_4_1240_1240
NEW Metal4 0 + SHAPE STRIPE ( 2393680 3117040 ) via4_5_6200_6200_4_4_1240_1240
NEW Metal4 0 + SHAPE STRIPE ( 2393680 2937040 ) via4_5_6200_6200_4_4_1240_1240
+ NEW Metal4 0 + SHAPE STRIPE ( 2393680 2757040 ) via4_5_6200_6200_4_4_1240_1240
+ NEW Metal4 0 + SHAPE STRIPE ( 2393680 2577040 ) via4_5_6200_6200_4_4_1240_1240
+ NEW Metal4 0 + SHAPE STRIPE ( 2393680 2397040 ) via4_5_6200_6200_4_4_1240_1240
+ NEW Metal4 0 + SHAPE STRIPE ( 2393680 2217040 ) via4_5_6200_6200_4_4_1240_1240
+ NEW Metal4 0 + SHAPE STRIPE ( 2393680 2037040 ) via4_5_6200_6200_4_4_1240_1240
+ NEW Metal4 0 + SHAPE STRIPE ( 2393680 1857040 ) via4_5_6200_6200_4_4_1240_1240
NEW Metal4 0 + SHAPE STRIPE ( 2393680 1677040 ) via4_5_6200_6200_4_4_1240_1240
NEW Metal4 0 + SHAPE STRIPE ( 2393680 1497040 ) via4_5_6200_6200_4_4_1240_1240
NEW Metal4 0 + SHAPE STRIPE ( 2393680 1317040 ) via4_5_6200_6200_4_4_1240_1240
@@ -3472,6 +3433,12 @@
NEW Metal4 0 + SHAPE STRIPE ( 2213680 3297040 ) via4_5_6200_6200_4_4_1240_1240
NEW Metal4 0 + SHAPE STRIPE ( 2213680 3117040 ) via4_5_6200_6200_4_4_1240_1240
NEW Metal4 0 + SHAPE STRIPE ( 2213680 2937040 ) via4_5_6200_6200_4_4_1240_1240
+ NEW Metal4 0 + SHAPE STRIPE ( 2213680 2757040 ) via4_5_6200_6200_4_4_1240_1240
+ NEW Metal4 0 + SHAPE STRIPE ( 2213680 2577040 ) via4_5_6200_6200_4_4_1240_1240
+ NEW Metal4 0 + SHAPE STRIPE ( 2213680 2397040 ) via4_5_6200_6200_4_4_1240_1240
+ NEW Metal4 0 + SHAPE STRIPE ( 2213680 2217040 ) via4_5_6200_6200_4_4_1240_1240
+ NEW Metal4 0 + SHAPE STRIPE ( 2213680 2037040 ) via4_5_6200_6200_4_4_1240_1240
+ NEW Metal4 0 + SHAPE STRIPE ( 2213680 1857040 ) via4_5_6200_6200_4_4_1240_1240
NEW Metal4 0 + SHAPE STRIPE ( 2213680 1677040 ) via4_5_6200_6200_4_4_1240_1240
NEW Metal4 0 + SHAPE STRIPE ( 2213680 1497040 ) via4_5_6200_6200_4_4_1240_1240
NEW Metal4 0 + SHAPE STRIPE ( 2213680 1317040 ) via4_5_6200_6200_4_4_1240_1240
@@ -3501,6 +3468,12 @@
NEW Metal4 0 + SHAPE STRIPE ( 2033680 3297040 ) via4_5_6200_6200_4_4_1240_1240
NEW Metal4 0 + SHAPE STRIPE ( 2033680 3117040 ) via4_5_6200_6200_4_4_1240_1240
NEW Metal4 0 + SHAPE STRIPE ( 2033680 2937040 ) via4_5_6200_6200_4_4_1240_1240
+ NEW Metal4 0 + SHAPE STRIPE ( 2033680 2757040 ) via4_5_6200_6200_4_4_1240_1240
+ NEW Metal4 0 + SHAPE STRIPE ( 2033680 2577040 ) via4_5_6200_6200_4_4_1240_1240
+ NEW Metal4 0 + SHAPE STRIPE ( 2033680 2397040 ) via4_5_6200_6200_4_4_1240_1240
+ NEW Metal4 0 + SHAPE STRIPE ( 2033680 2217040 ) via4_5_6200_6200_4_4_1240_1240
+ NEW Metal4 0 + SHAPE STRIPE ( 2033680 2037040 ) via4_5_6200_6200_4_4_1240_1240
+ NEW Metal4 0 + SHAPE STRIPE ( 2033680 1857040 ) via4_5_6200_6200_4_4_1240_1240
NEW Metal4 0 + SHAPE STRIPE ( 2033680 1677040 ) via4_5_6200_6200_4_4_1240_1240
NEW Metal4 0 + SHAPE STRIPE ( 2033680 1497040 ) via4_5_6200_6200_4_4_1240_1240
NEW Metal4 0 + SHAPE STRIPE ( 2033680 1317040 ) via4_5_6200_6200_4_4_1240_1240
@@ -3530,6 +3503,12 @@
NEW Metal4 0 + SHAPE STRIPE ( 1853680 3297040 ) via4_5_6200_6200_4_4_1240_1240
NEW Metal4 0 + SHAPE STRIPE ( 1853680 3117040 ) via4_5_6200_6200_4_4_1240_1240
NEW Metal4 0 + SHAPE STRIPE ( 1853680 2937040 ) via4_5_6200_6200_4_4_1240_1240
+ NEW Metal4 0 + SHAPE STRIPE ( 1853680 2757040 ) via4_5_6200_6200_4_4_1240_1240
+ NEW Metal4 0 + SHAPE STRIPE ( 1853680 2577040 ) via4_5_6200_6200_4_4_1240_1240
+ NEW Metal4 0 + SHAPE STRIPE ( 1853680 2397040 ) via4_5_6200_6200_4_4_1240_1240
+ NEW Metal4 0 + SHAPE STRIPE ( 1853680 2217040 ) via4_5_6200_6200_4_4_1240_1240
+ NEW Metal4 0 + SHAPE STRIPE ( 1853680 2037040 ) via4_5_6200_6200_4_4_1240_1240
+ NEW Metal4 0 + SHAPE STRIPE ( 1853680 1857040 ) via4_5_6200_6200_4_4_1240_1240
NEW Metal4 0 + SHAPE STRIPE ( 1853680 1677040 ) via4_5_6200_6200_4_4_1240_1240
NEW Metal4 0 + SHAPE STRIPE ( 1853680 1497040 ) via4_5_6200_6200_4_4_1240_1240
NEW Metal4 0 + SHAPE STRIPE ( 1853680 1317040 ) via4_5_6200_6200_4_4_1240_1240
@@ -3598,7 +3577,6 @@
NEW Metal4 0 + SHAPE STRIPE ( 1493680 2577040 ) via4_5_6200_6200_4_4_1240_1240
NEW Metal4 0 + SHAPE STRIPE ( 1493680 2397040 ) via4_5_6200_6200_4_4_1240_1240
NEW Metal4 0 + SHAPE STRIPE ( 1493680 2217040 ) via4_5_6200_6200_4_4_1240_1240
- NEW Metal4 0 + SHAPE STRIPE ( 1493680 2037040 ) via4_5_6200_6200_4_4_1240_1240
NEW Metal4 0 + SHAPE STRIPE ( 1493680 1857040 ) via4_5_6200_6200_4_4_1240_1240
NEW Metal4 0 + SHAPE STRIPE ( 1493680 1677040 ) via4_5_6200_6200_4_4_1240_1240
NEW Metal4 0 + SHAPE STRIPE ( 1493680 1497040 ) via4_5_6200_6200_4_4_1240_1240
@@ -3633,7 +3611,6 @@
NEW Metal4 0 + SHAPE STRIPE ( 1313680 2577040 ) via4_5_6200_6200_4_4_1240_1240
NEW Metal4 0 + SHAPE STRIPE ( 1313680 2397040 ) via4_5_6200_6200_4_4_1240_1240
NEW Metal4 0 + SHAPE STRIPE ( 1313680 2217040 ) via4_5_6200_6200_4_4_1240_1240
- NEW Metal4 0 + SHAPE STRIPE ( 1313680 2037040 ) via4_5_6200_6200_4_4_1240_1240
NEW Metal4 0 + SHAPE STRIPE ( 1313680 1857040 ) via4_5_6200_6200_4_4_1240_1240
NEW Metal4 0 + SHAPE STRIPE ( 1313680 1677040 ) via4_5_6200_6200_4_4_1240_1240
NEW Metal4 0 + SHAPE STRIPE ( 1313680 1497040 ) via4_5_6200_6200_4_4_1240_1240
@@ -3927,82 +3904,18 @@
NEW Metal4 0 + SHAPE STRIPE ( 12580 57040 ) via4_5_6200_6200_4_4_1240_1240
NEW Metal4 0 + SHAPE RING ( 12580 15940 ) via4_5_6200_6200_4_4_1240_1240 ;
- vss ( PIN vss ) ( * vss ) + USE GROUND
- + ROUTED Metal4 0 + SHAPE STRIPE ( 2970880 2817040 ) via4_5_6200_6200_4_4_1240_1240
- NEW Metal4 0 + SHAPE STRIPE ( 2970880 2637040 ) via4_5_6200_6200_4_4_1240_1240
- NEW Metal4 0 + SHAPE STRIPE ( 2970880 2457040 ) via4_5_6200_6200_4_4_1240_1240
- NEW Metal4 0 + SHAPE STRIPE ( 2970880 2277040 ) via4_5_6200_6200_4_4_1240_1240
- NEW Metal4 0 + SHAPE STRIPE ( 2970880 2097040 ) via4_5_6200_6200_4_4_1240_1240
- NEW Metal4 0 + SHAPE STRIPE ( 2970880 1917040 ) via4_5_6200_6200_4_4_1240_1240
- NEW Metal4 0 + SHAPE STRIPE ( 2970880 1737040 ) via4_5_6200_6200_4_4_1240_1240
- NEW Metal4 0 + SHAPE STRIPE ( 2910680 2817040 ) via4_5_3200_6200_4_2_1240_1240
- NEW Metal4 0 + SHAPE STRIPE ( 2910680 2637040 ) via4_5_3200_6200_4_2_1240_1240
- NEW Metal4 0 + SHAPE STRIPE ( 2910680 2457040 ) via4_5_3200_6200_4_2_1240_1240
- NEW Metal4 0 + SHAPE STRIPE ( 2910680 2277040 ) via4_5_3200_6200_4_2_1240_1240
- NEW Metal4 0 + SHAPE STRIPE ( 2910680 2097040 ) via4_5_3200_6200_4_2_1240_1240
- NEW Metal4 0 + SHAPE STRIPE ( 2910680 1917040 ) via4_5_3200_6200_4_2_1240_1240
- NEW Metal4 0 + SHAPE STRIPE ( 2910680 1737040 ) via4_5_3200_6200_4_2_1240_1240
- NEW Metal4 0 + SHAPE STRIPE ( 2790880 2817040 ) via4_5_6200_6200_4_4_1240_1240
- NEW Metal4 0 + SHAPE STRIPE ( 2790880 2637040 ) via4_5_6200_6200_4_4_1240_1240
- NEW Metal4 0 + SHAPE STRIPE ( 2790880 2457040 ) via4_5_6200_6200_4_4_1240_1240
- NEW Metal4 0 + SHAPE STRIPE ( 2790880 2277040 ) via4_5_6200_6200_4_4_1240_1240
- NEW Metal4 0 + SHAPE STRIPE ( 2790880 2097040 ) via4_5_6200_6200_4_4_1240_1240
- NEW Metal4 0 + SHAPE STRIPE ( 2790880 1917040 ) via4_5_6200_6200_4_4_1240_1240
- NEW Metal4 0 + SHAPE STRIPE ( 2790880 1737040 ) via4_5_6200_6200_4_4_1240_1240
- NEW Metal4 0 + SHAPE STRIPE ( 2610880 2817040 ) via4_5_6200_6200_4_4_1240_1240
- NEW Metal4 0 + SHAPE STRIPE ( 2610880 2637040 ) via4_5_6200_6200_4_4_1240_1240
- NEW Metal4 0 + SHAPE STRIPE ( 2610880 2457040 ) via4_5_6200_6200_4_4_1240_1240
- NEW Metal4 0 + SHAPE STRIPE ( 2610880 2277040 ) via4_5_6200_6200_4_4_1240_1240
- NEW Metal4 0 + SHAPE STRIPE ( 2610880 2097040 ) via4_5_6200_6200_4_4_1240_1240
- NEW Metal4 0 + SHAPE STRIPE ( 2610880 1917040 ) via4_5_6200_6200_4_4_1240_1240
- NEW Metal4 0 + SHAPE STRIPE ( 2610880 1737040 ) via4_5_6200_6200_4_4_1240_1240
- NEW Metal4 0 + SHAPE STRIPE ( 2603480 2817040 ) via4_5_3200_6200_4_2_1240_1240
- NEW Metal4 0 + SHAPE STRIPE ( 2603480 2637040 ) via4_5_3200_6200_4_2_1240_1240
- NEW Metal4 0 + SHAPE STRIPE ( 2603480 2457040 ) via4_5_3200_6200_4_2_1240_1240
- NEW Metal4 0 + SHAPE STRIPE ( 2603480 2277040 ) via4_5_3200_6200_4_2_1240_1240
- NEW Metal4 0 + SHAPE STRIPE ( 2603480 2097040 ) via4_5_3200_6200_4_2_1240_1240
- NEW Metal4 0 + SHAPE STRIPE ( 2603480 1917040 ) via4_5_3200_6200_4_2_1240_1240
- NEW Metal4 0 + SHAPE STRIPE ( 2603480 1737040 ) via4_5_3200_6200_4_2_1240_1240
- NEW Metal4 0 + SHAPE STRIPE ( 2296280 2817040 ) via4_5_3200_6200_4_2_1240_1240
- NEW Metal4 0 + SHAPE STRIPE ( 2296280 2637040 ) via4_5_3200_6200_4_2_1240_1240
- NEW Metal4 0 + SHAPE STRIPE ( 2296280 2457040 ) via4_5_3200_6200_4_2_1240_1240
- NEW Metal4 0 + SHAPE STRIPE ( 2296280 2277040 ) via4_5_3200_6200_4_2_1240_1240
- NEW Metal4 0 + SHAPE STRIPE ( 2296280 2097040 ) via4_5_3200_6200_4_2_1240_1240
- NEW Metal4 0 + SHAPE STRIPE ( 2296280 1917040 ) via4_5_3200_6200_4_2_1240_1240
- NEW Metal4 0 + SHAPE STRIPE ( 2296280 1737040 ) via4_5_3200_6200_4_2_1240_1240
- NEW Metal4 0 + SHAPE STRIPE ( 1989080 2817040 ) via4_5_3200_6200_4_2_1240_1240
- NEW Metal4 0 + SHAPE STRIPE ( 1989080 2637040 ) via4_5_3200_6200_4_2_1240_1240
- NEW Metal4 0 + SHAPE STRIPE ( 1989080 2457040 ) via4_5_3200_6200_4_2_1240_1240
- NEW Metal4 0 + SHAPE STRIPE ( 1989080 2277040 ) via4_5_3200_6200_4_2_1240_1240
- NEW Metal4 0 + SHAPE STRIPE ( 1989080 2097040 ) via4_5_3200_6200_4_2_1240_1240
- NEW Metal4 0 + SHAPE STRIPE ( 1989080 1917040 ) via4_5_3200_6200_4_2_1240_1240
- NEW Metal4 0 + SHAPE STRIPE ( 1989080 1737040 ) via4_5_3200_6200_4_2_1240_1240
- NEW Metal4 0 + SHAPE STRIPE ( 1710880 2817040 ) via4_5_6200_6200_4_4_1240_1240
- NEW Metal4 0 + SHAPE STRIPE ( 1710880 2637040 ) via4_5_6200_6200_4_4_1240_1240
- NEW Metal4 0 + SHAPE STRIPE ( 1710880 2457040 ) via4_5_6200_6200_4_4_1240_1240
- NEW Metal4 0 + SHAPE STRIPE ( 1710880 2277040 ) via4_5_6200_6200_4_4_1240_1240
+ + ROUTED Metal4 0 + SHAPE STRIPE ( 1710880 2277040 ) via4_5_6200_6200_4_4_1240_1240
NEW Metal4 0 + SHAPE STRIPE ( 1710880 2097040 ) via4_5_6200_6200_4_4_1240_1240
NEW Metal4 0 + SHAPE STRIPE ( 1710880 1917040 ) via4_5_6200_6200_4_4_1240_1240
NEW Metal4 0 + SHAPE STRIPE ( 1710880 1737040 ) via4_5_6200_6200_4_4_1240_1240
- NEW Metal4 0 + SHAPE STRIPE ( 1681880 2817040 ) via4_5_3200_6200_4_2_1240_1240
- NEW Metal4 0 + SHAPE STRIPE ( 1681880 2637040 ) via4_5_3200_6200_4_2_1240_1240
- NEW Metal4 0 + SHAPE STRIPE ( 1681880 2457040 ) via4_5_3200_6200_4_2_1240_1240
- NEW Metal4 0 + SHAPE STRIPE ( 1681880 2277040 ) via4_5_3200_6200_4_2_1240_1240
NEW Metal4 0 + SHAPE STRIPE ( 1681880 2097040 ) via4_5_3200_6200_4_2_1240_1240
NEW Metal4 0 + SHAPE STRIPE ( 1681880 1917040 ) via4_5_3200_6200_4_2_1240_1240
NEW Metal4 0 + SHAPE STRIPE ( 1681880 1737040 ) via4_5_3200_6200_4_2_1240_1240
- NEW Metal4 0 + SHAPE STRIPE ( 1374680 2817040 ) via4_5_3200_6200_4_2_1240_1240
- NEW Metal4 0 + SHAPE STRIPE ( 1374680 2637040 ) via4_5_3200_6200_4_2_1240_1240
- NEW Metal4 0 + SHAPE STRIPE ( 1374680 2457040 ) via4_5_3200_6200_4_2_1240_1240
- NEW Metal4 0 + SHAPE STRIPE ( 1374680 2277040 ) via4_5_3200_6200_4_2_1240_1240
+ NEW Metal4 0 + SHAPE STRIPE ( 1530880 2277890 ) via4_5_6200_4500_4_4_1240_1240
NEW Metal4 0 + SHAPE STRIPE ( 1374680 2097040 ) via4_5_3200_6200_4_2_1240_1240
NEW Metal4 0 + SHAPE STRIPE ( 1374680 1917040 ) via4_5_3200_6200_4_2_1240_1240
NEW Metal4 0 + SHAPE STRIPE ( 1374680 1737040 ) via4_5_3200_6200_4_2_1240_1240
- NEW Metal4 0 + SHAPE STRIPE ( 1350880 2817040 ) via4_5_6200_6200_4_4_1240_1240
- NEW Metal4 0 + SHAPE STRIPE ( 1350880 2637040 ) via4_5_6200_6200_4_4_1240_1240
- NEW Metal4 0 + SHAPE STRIPE ( 1350880 2457040 ) via4_5_6200_6200_4_4_1240_1240
NEW Metal4 0 + SHAPE STRIPE ( 1350880 2277040 ) via4_5_6200_6200_4_4_1240_1240
- NEW Metal4 0 + SHAPE STRIPE ( 1350880 2097040 ) via4_5_6200_6200_4_4_1240_1240
- NEW Metal4 0 + SHAPE STRIPE ( 1350880 1917040 ) via4_5_6200_6200_4_4_1240_1240
NEW Metal4 0 + SHAPE STRIPE ( 1350880 1737040 ) via4_5_6200_6200_4_4_1240_1240
NEW Metal5 6200 + SHAPE STRIPE ( -120 5877040 ) ( 5999960 5877040 )
NEW Metal5 6200 + SHAPE STRIPE ( -120 5697040 ) ( 5999960 5697040 )
@@ -4056,18 +3969,15 @@
NEW Metal4 6200 + SHAPE STRIPE ( 2970880 3240 ) ( 2970880 5994360 )
NEW Metal4 6200 + SHAPE STRIPE ( 2790880 3240 ) ( 2790880 5994360 )
NEW Metal4 6200 + SHAPE STRIPE ( 2610880 3240 ) ( 2610880 5994360 )
- NEW Metal4 6200 + SHAPE STRIPE ( 2430880 2872940 ) ( 2430880 5994360 )
- NEW Metal4 6200 + SHAPE STRIPE ( 2430880 3240 ) ( 2430880 1698740 )
- NEW Metal4 6200 + SHAPE STRIPE ( 2250880 2872940 ) ( 2250880 5994360 )
- NEW Metal4 6200 + SHAPE STRIPE ( 2250880 3240 ) ( 2250880 1698740 )
- NEW Metal4 6200 + SHAPE STRIPE ( 2070880 2872940 ) ( 2070880 5994360 )
- NEW Metal4 6200 + SHAPE STRIPE ( 2070880 3240 ) ( 2070880 1698740 )
- NEW Metal4 6200 + SHAPE STRIPE ( 1890880 2872940 ) ( 1890880 5994360 )
- NEW Metal4 6200 + SHAPE STRIPE ( 1890880 3240 ) ( 1890880 1698740 )
+ NEW Metal4 6200 + SHAPE STRIPE ( 2430880 3240 ) ( 2430880 5994360 )
+ NEW Metal4 6200 + SHAPE STRIPE ( 2250880 3240 ) ( 2250880 5994360 )
+ NEW Metal4 6200 + SHAPE STRIPE ( 2070880 3240 ) ( 2070880 5994360 )
+ NEW Metal4 6200 + SHAPE STRIPE ( 1890880 3240 ) ( 1890880 5994360 )
NEW Metal4 6200 + SHAPE STRIPE ( 1710880 3240 ) ( 1710880 5994360 )
- NEW Metal4 6200 + SHAPE STRIPE ( 1530880 2879320 ) ( 1530880 5994360 )
+ NEW Metal4 6200 + SHAPE STRIPE ( 1530880 2275640 ) ( 1530880 5994360 )
NEW Metal4 6200 + SHAPE STRIPE ( 1530880 3240 ) ( 1530880 1700200 )
- NEW Metal4 6200 + SHAPE STRIPE ( 1350880 3240 ) ( 1350880 5994360 )
+ NEW Metal4 6200 + SHAPE STRIPE ( 1350880 2146060 ) ( 1350880 5994360 )
+ NEW Metal4 6200 + SHAPE STRIPE ( 1350880 3240 ) ( 1350880 1882420 )
NEW Metal4 6200 + SHAPE STRIPE ( 1170880 3240 ) ( 1170880 5994360 )
NEW Metal4 6200 + SHAPE STRIPE ( 990880 3240 ) ( 990880 5994360 )
NEW Metal4 6200 + SHAPE STRIPE ( 810880 3240 ) ( 810880 5994360 )
@@ -4797,6 +4707,13 @@
NEW Metal4 0 + SHAPE STRIPE ( 2430880 3357040 ) via4_5_6200_6200_4_4_1240_1240
NEW Metal4 0 + SHAPE STRIPE ( 2430880 3177040 ) via4_5_6200_6200_4_4_1240_1240
NEW Metal4 0 + SHAPE STRIPE ( 2430880 2997040 ) via4_5_6200_6200_4_4_1240_1240
+ NEW Metal4 0 + SHAPE STRIPE ( 2430880 2817040 ) via4_5_6200_6200_4_4_1240_1240
+ NEW Metal4 0 + SHAPE STRIPE ( 2430880 2637040 ) via4_5_6200_6200_4_4_1240_1240
+ NEW Metal4 0 + SHAPE STRIPE ( 2430880 2457040 ) via4_5_6200_6200_4_4_1240_1240
+ NEW Metal4 0 + SHAPE STRIPE ( 2430880 2277040 ) via4_5_6200_6200_4_4_1240_1240
+ NEW Metal4 0 + SHAPE STRIPE ( 2430880 2097040 ) via4_5_6200_6200_4_4_1240_1240
+ NEW Metal4 0 + SHAPE STRIPE ( 2430880 1917040 ) via4_5_6200_6200_4_4_1240_1240
+ NEW Metal4 0 + SHAPE STRIPE ( 2430880 1737040 ) via4_5_6200_6200_4_4_1240_1240
NEW Metal4 0 + SHAPE STRIPE ( 2430880 1557040 ) via4_5_6200_6200_4_4_1240_1240
NEW Metal4 0 + SHAPE STRIPE ( 2430880 1377040 ) via4_5_6200_6200_4_4_1240_1240
NEW Metal4 0 + SHAPE STRIPE ( 2430880 1197040 ) via4_5_6200_6200_4_4_1240_1240
@@ -4825,6 +4742,13 @@
NEW Metal4 0 + SHAPE STRIPE ( 2250880 3357040 ) via4_5_6200_6200_4_4_1240_1240
NEW Metal4 0 + SHAPE STRIPE ( 2250880 3177040 ) via4_5_6200_6200_4_4_1240_1240
NEW Metal4 0 + SHAPE STRIPE ( 2250880 2997040 ) via4_5_6200_6200_4_4_1240_1240
+ NEW Metal4 0 + SHAPE STRIPE ( 2250880 2817040 ) via4_5_6200_6200_4_4_1240_1240
+ NEW Metal4 0 + SHAPE STRIPE ( 2250880 2637040 ) via4_5_6200_6200_4_4_1240_1240
+ NEW Metal4 0 + SHAPE STRIPE ( 2250880 2457040 ) via4_5_6200_6200_4_4_1240_1240
+ NEW Metal4 0 + SHAPE STRIPE ( 2250880 2277040 ) via4_5_6200_6200_4_4_1240_1240
+ NEW Metal4 0 + SHAPE STRIPE ( 2250880 2097040 ) via4_5_6200_6200_4_4_1240_1240
+ NEW Metal4 0 + SHAPE STRIPE ( 2250880 1917040 ) via4_5_6200_6200_4_4_1240_1240
+ NEW Metal4 0 + SHAPE STRIPE ( 2250880 1737040 ) via4_5_6200_6200_4_4_1240_1240
NEW Metal4 0 + SHAPE STRIPE ( 2250880 1557040 ) via4_5_6200_6200_4_4_1240_1240
NEW Metal4 0 + SHAPE STRIPE ( 2250880 1377040 ) via4_5_6200_6200_4_4_1240_1240
NEW Metal4 0 + SHAPE STRIPE ( 2250880 1197040 ) via4_5_6200_6200_4_4_1240_1240
@@ -4853,6 +4777,13 @@
NEW Metal4 0 + SHAPE STRIPE ( 2070880 3357040 ) via4_5_6200_6200_4_4_1240_1240
NEW Metal4 0 + SHAPE STRIPE ( 2070880 3177040 ) via4_5_6200_6200_4_4_1240_1240
NEW Metal4 0 + SHAPE STRIPE ( 2070880 2997040 ) via4_5_6200_6200_4_4_1240_1240
+ NEW Metal4 0 + SHAPE STRIPE ( 2070880 2817040 ) via4_5_6200_6200_4_4_1240_1240
+ NEW Metal4 0 + SHAPE STRIPE ( 2070880 2637040 ) via4_5_6200_6200_4_4_1240_1240
+ NEW Metal4 0 + SHAPE STRIPE ( 2070880 2457040 ) via4_5_6200_6200_4_4_1240_1240
+ NEW Metal4 0 + SHAPE STRIPE ( 2070880 2277040 ) via4_5_6200_6200_4_4_1240_1240
+ NEW Metal4 0 + SHAPE STRIPE ( 2070880 2097040 ) via4_5_6200_6200_4_4_1240_1240
+ NEW Metal4 0 + SHAPE STRIPE ( 2070880 1917040 ) via4_5_6200_6200_4_4_1240_1240
+ NEW Metal4 0 + SHAPE STRIPE ( 2070880 1737040 ) via4_5_6200_6200_4_4_1240_1240
NEW Metal4 0 + SHAPE STRIPE ( 2070880 1557040 ) via4_5_6200_6200_4_4_1240_1240
NEW Metal4 0 + SHAPE STRIPE ( 2070880 1377040 ) via4_5_6200_6200_4_4_1240_1240
NEW Metal4 0 + SHAPE STRIPE ( 2070880 1197040 ) via4_5_6200_6200_4_4_1240_1240
@@ -4881,6 +4812,13 @@
NEW Metal4 0 + SHAPE STRIPE ( 1890880 3357040 ) via4_5_6200_6200_4_4_1240_1240
NEW Metal4 0 + SHAPE STRIPE ( 1890880 3177040 ) via4_5_6200_6200_4_4_1240_1240
NEW Metal4 0 + SHAPE STRIPE ( 1890880 2997040 ) via4_5_6200_6200_4_4_1240_1240
+ NEW Metal4 0 + SHAPE STRIPE ( 1890880 2817040 ) via4_5_6200_6200_4_4_1240_1240
+ NEW Metal4 0 + SHAPE STRIPE ( 1890880 2637040 ) via4_5_6200_6200_4_4_1240_1240
+ NEW Metal4 0 + SHAPE STRIPE ( 1890880 2457040 ) via4_5_6200_6200_4_4_1240_1240
+ NEW Metal4 0 + SHAPE STRIPE ( 1890880 2277040 ) via4_5_6200_6200_4_4_1240_1240
+ NEW Metal4 0 + SHAPE STRIPE ( 1890880 2097040 ) via4_5_6200_6200_4_4_1240_1240
+ NEW Metal4 0 + SHAPE STRIPE ( 1890880 1917040 ) via4_5_6200_6200_4_4_1240_1240
+ NEW Metal4 0 + SHAPE STRIPE ( 1890880 1737040 ) via4_5_6200_6200_4_4_1240_1240
NEW Metal4 0 + SHAPE STRIPE ( 1890880 1557040 ) via4_5_6200_6200_4_4_1240_1240
NEW Metal4 0 + SHAPE STRIPE ( 1890880 1377040 ) via4_5_6200_6200_4_4_1240_1240
NEW Metal4 0 + SHAPE STRIPE ( 1890880 1197040 ) via4_5_6200_6200_4_4_1240_1240
@@ -4944,6 +4882,10 @@
NEW Metal4 0 + SHAPE STRIPE ( 1530880 3357040 ) via4_5_6200_6200_4_4_1240_1240
NEW Metal4 0 + SHAPE STRIPE ( 1530880 3177040 ) via4_5_6200_6200_4_4_1240_1240
NEW Metal4 0 + SHAPE STRIPE ( 1530880 2997040 ) via4_5_6200_6200_4_4_1240_1240
+ NEW Metal4 0 + SHAPE STRIPE ( 1530880 2817040 ) via4_5_6200_6200_4_4_1240_1240
+ NEW Metal4 0 + SHAPE STRIPE ( 1530880 2637040 ) via4_5_6200_6200_4_4_1240_1240
+ NEW Metal4 0 + SHAPE STRIPE ( 1530880 2457040 ) via4_5_6200_6200_4_4_1240_1240
+ NEW Metal4 0 + SHAPE STRIPE ( 1530880 2277890 ) via4_5_6200_4500_4_4_1240_1240
NEW Metal4 0 + SHAPE STRIPE ( 1530880 1557040 ) via4_5_6200_6200_4_4_1240_1240
NEW Metal4 0 + SHAPE STRIPE ( 1530880 1377040 ) via4_5_6200_6200_4_4_1240_1240
NEW Metal4 0 + SHAPE STRIPE ( 1530880 1197040 ) via4_5_6200_6200_4_4_1240_1240
@@ -4976,8 +4918,6 @@
NEW Metal4 0 + SHAPE STRIPE ( 1350880 2637040 ) via4_5_6200_6200_4_4_1240_1240
NEW Metal4 0 + SHAPE STRIPE ( 1350880 2457040 ) via4_5_6200_6200_4_4_1240_1240
NEW Metal4 0 + SHAPE STRIPE ( 1350880 2277040 ) via4_5_6200_6200_4_4_1240_1240
- NEW Metal4 0 + SHAPE STRIPE ( 1350880 2097040 ) via4_5_6200_6200_4_4_1240_1240
- NEW Metal4 0 + SHAPE STRIPE ( 1350880 1917040 ) via4_5_6200_6200_4_4_1240_1240
NEW Metal4 0 + SHAPE STRIPE ( 1350880 1737040 ) via4_5_6200_6200_4_4_1240_1240
NEW Metal4 0 + SHAPE STRIPE ( 1350880 1557040 ) via4_5_6200_6200_4_4_1240_1240
NEW Metal4 0 + SHAPE STRIPE ( 1350880 1377040 ) via4_5_6200_6200_4_4_1240_1240
@@ -5271,4758 +5211,1586 @@
NEW Metal4 0 + SHAPE RING ( 2980 6340 ) via4_5_6200_6200_4_4_1240_1240 ;
END SPECIALNETS
NETS 416 ;
- - io_in[0] ( PIN io_in[0] ) ( mprj io_in[0] ) + USE SIGNAL
- + ROUTED Metal3 ( 1176560 2882320 ) ( 1188880 * )
- NEW Metal2 ( 1176560 478800 ) ( * 2882320 )
- NEW Metal2 ( 5888400 68880 ) ( * 478800 )
- NEW Metal3 ( 1176560 478800 ) ( 5888400 * )
- NEW Metal3 ( 5888400 68880 ) ( 5995920 * 0 )
- NEW Metal2 ( 1176560 478800 ) Via2_VH
- NEW Metal2 ( 1176560 2882320 ) Via2_VH
- NEW Metal2 ( 1188880 2882320 ) Via2_HH
- NEW Metal2 ( 5888400 68880 ) Via2_VH
- NEW Metal2 ( 5888400 478800 ) Via2_VH ;
- - io_in[10] ( PIN io_in[10] ) ( mprj io_in[10] ) + USE SIGNAL
- + ROUTED Metal2 ( 1651440 2889040 ) ( 1659280 * 0 )
- NEW Metal2 ( 1646960 3024000 ) ( * 3066000 )
- NEW Metal2 ( 1646960 3024000 ) ( 1651440 * )
- NEW Metal2 ( 1651440 2889040 ) ( * 3024000 )
- NEW Metal2 ( 5957840 3066000 ) ( * 4066160 )
- NEW Metal3 ( 1646960 3066000 ) ( 5957840 * )
- NEW Metal3 ( 5957840 4066160 ) ( 5995920 * 0 )
- NEW Metal2 ( 1646960 3066000 ) Via2_VH
- NEW Metal2 ( 5957840 3066000 ) Via2_VH
- NEW Metal2 ( 5957840 4066160 ) Via2_VH ;
- - io_in[11] ( PIN io_in[11] ) ( mprj io_in[11] ) + USE SIGNAL
- + ROUTED Metal2 ( 1698480 2889040 ) ( 1706320 * 0 )
- NEW Metal2 ( 1697360 3024000 ) ( 1698480 * )
- NEW Metal2 ( 1698480 2889040 ) ( * 3024000 )
- NEW Metal2 ( 1697360 3024000 ) ( * 4452560 )
+ - io_in[0] ( PIN io_in[0] ) ( wrapped_vga_clock io_in[0] ) + USE SIGNAL
+ + ROUTED Metal2 ( 3788400 67760 ) ( * 2268560 )
+ NEW Metal3 ( 3788400 67760 ) ( 5995920 * 0 )
+ NEW Metal3 ( 1772400 2268560 0 ) ( 3788400 * )
+ NEW Metal2 ( 3788400 67760 ) Via2_VH
+ NEW Metal2 ( 3788400 2268560 ) Via2_VH ;
+ - io_in[10] ( PIN io_in[10] ) ( wrapped_vga_clock io_in[10] ) + USE SIGNAL
+ + ROUTED Metal2 ( 5938800 1831760 ) ( * 4066160 )
+ NEW Metal3 ( 5938800 4066160 ) ( 5995920 * 0 )
+ NEW Metal3 ( 1772400 1831760 0 ) ( 5938800 * )
+ NEW Metal2 ( 5938800 4066160 ) Via2_VH
+ NEW Metal2 ( 5938800 1831760 ) Via2_VH ;
+ - io_in[11] ( PIN io_in[11] ) ( wrapped_vga_clock io_in[11] ) + USE SIGNAL
+ + ROUTED Metal1 ( 1235920 2287600 ) ( * 2290960 )
+ NEW Metal1 ( 1226960 2290960 ) ( 1235920 * )
+ NEW Metal2 ( 1226960 2290960 ) ( * 4452560 )
NEW Metal3 ( 5995920 4452560 ) ( * 4463760 )
NEW Metal3 ( 5994800 4463760 ) ( 5995920 * )
NEW Metal3 ( 5994800 4463760 ) ( * 4464880 )
NEW Metal3 ( 5994800 4464880 ) ( 5995920 * 0 )
- NEW Metal3 ( 1697360 4452560 ) ( 5995920 * )
- NEW Metal2 ( 1697360 4452560 ) Via2_VH ;
- - io_in[12] ( PIN io_in[12] ) ( mprj io_in[12] ) + USE SIGNAL
- + ROUTED Metal2 ( 1747760 2889040 ) ( 1753360 * 0 )
- NEW Metal2 ( 1747760 2889040 ) ( * 4855760 )
+ NEW Metal3 ( 1226960 4452560 ) ( 5995920 * )
+ NEW Metal2 ( 1226960 4452560 ) Via2_VH
+ NEW Metal1 ( 1235920 2287600 ) Via1_HV
+ NEW Metal1 ( 1226960 2290960 ) Via1_HV ;
+ - io_in[12] ( PIN io_in[12] ) ( wrapped_vga_clock io_in[12] ) + USE SIGNAL
+ + ROUTED Metal3 ( 1125040 2019920 ) ( 1177680 * 0 )
+ NEW Metal2 ( 1125040 2019920 ) ( * 4855760 )
NEW Metal3 ( 5995920 4855760 ) ( * 4863600 )
NEW Metal3 ( 5994800 4863600 ) ( 5995920 * )
NEW Metal3 ( 5994800 4863600 ) ( * 4864720 )
NEW Metal3 ( 5994800 4864720 ) ( 5995920 * 0 )
- NEW Metal3 ( 1747760 4855760 ) ( 5995920 * )
- NEW Metal2 ( 1747760 4855760 ) Via2_VH ;
- - io_in[13] ( PIN io_in[13] ) ( mprj io_in[13] ) + USE SIGNAL
- + ROUTED Metal2 ( 1923600 2999920 ) ( * 5258960 )
- NEW Metal2 ( 1798160 2889040 ) ( 1800400 * 0 )
- NEW Metal2 ( 1798160 2889040 ) ( * 2999920 )
- NEW Metal3 ( 1798160 2999920 ) ( 1923600 * )
+ NEW Metal3 ( 1125040 4855760 ) ( 5995920 * )
+ NEW Metal2 ( 1125040 2019920 ) Via2_VH
+ NEW Metal2 ( 1125040 4855760 ) Via2_VH ;
+ - io_in[13] ( PIN io_in[13] ) ( wrapped_vga_clock io_in[13] ) + USE SIGNAL
+ + ROUTED Metal3 ( 1713040 2334640 ) ( 1722000 * )
+ NEW Metal1 ( 1713040 2287600 ) ( * 2290960 )
+ NEW Metal2 ( 1713040 2290960 ) ( * 2334640 )
+ NEW Metal2 ( 1722000 2334640 ) ( * 5258960 )
NEW Metal3 ( 5995920 5258960 ) ( * 5263440 )
NEW Metal3 ( 5994800 5263440 ) ( 5995920 * )
NEW Metal3 ( 5994800 5263440 ) ( * 5264560 )
NEW Metal3 ( 5994800 5264560 ) ( 5995920 * 0 )
- NEW Metal3 ( 1923600 5258960 ) ( 5995920 * )
- NEW Metal2 ( 1923600 2999920 ) Via2_VH
- NEW Metal2 ( 1923600 5258960 ) Via2_VH
- NEW Metal2 ( 1798160 2999920 ) Via2_VH ;
- - io_in[14] ( PIN io_in[14] ) ( mprj io_in[14] ) + USE SIGNAL
- + ROUTED Metal2 ( 1940400 2968560 ) ( * 5662160 )
- NEW Metal2 ( 1839600 2889040 ) ( 1847440 * 0 )
- NEW Metal3 ( 1940400 5662160 ) ( 5728800 * )
+ NEW Metal3 ( 1722000 5258960 ) ( 5995920 * )
+ NEW Metal2 ( 1713040 2334640 ) Via2_VH
+ NEW Metal2 ( 1722000 2334640 ) Via2_VH
+ NEW Metal1 ( 1713040 2287600 ) Via1_HV
+ NEW Metal1 ( 1713040 2290960 ) Via1_HV
+ NEW Metal2 ( 1722000 5258960 ) Via2_VH ;
+ - io_in[14] ( PIN io_in[14] ) ( wrapped_vga_clock io_in[14] ) + USE SIGNAL
+ + ROUTED Metal3 ( 1596560 5662160 ) ( 5728800 * )
NEW Metal3 ( 5728800 5662160 ) ( * 5664400 )
NEW Metal3 ( 5728800 5664400 ) ( 5995920 * 0 )
- NEW Metal2 ( 1839600 2889040 ) ( * 2968560 )
- NEW Metal3 ( 1839600 2968560 ) ( 1940400 * )
- NEW Metal2 ( 1940400 5662160 ) Via2_VH
- NEW Metal2 ( 1940400 2968560 ) Via2_VH
- NEW Metal2 ( 1839600 2968560 ) Via2_VH ;
- - io_in[15] ( PIN io_in[15] ) ( mprj io_in[15] ) + USE SIGNAL
- + ROUTED Metal2 ( 1886640 2889040 ) ( 1894480 * 0 )
- NEW Metal2 ( 1882160 3024000 ) ( 1886640 * )
- NEW Metal2 ( 1886640 2889040 ) ( * 3024000 )
- NEW Metal2 ( 1882160 3024000 ) ( * 5981360 )
- NEW Metal2 ( 5881680 5981360 ) ( * 5995920 0 )
- NEW Metal3 ( 1882160 5981360 ) ( 5881680 * )
- NEW Metal2 ( 1882160 5981360 ) Via2_VH
- NEW Metal2 ( 5881680 5981360 ) Via2_VH ;
- - io_in[16] ( PIN io_in[16] ) ( mprj io_in[16] ) + USE SIGNAL
- + ROUTED Metal2 ( 1933680 2889040 ) ( 1941520 * 0 )
- NEW Metal2 ( 1933680 2889040 ) ( * 3015600 )
- NEW Metal2 ( 5208560 5995920 ) ( 5215280 * )
+ NEW Metal1 ( 1596560 2287600 ) ( 1612240 * )
+ NEW Metal1 ( 1596560 2287600 ) ( * 2290960 )
+ NEW Metal2 ( 1596560 2290960 ) ( * 5662160 )
+ NEW Metal2 ( 1596560 5662160 ) Via2_VH
+ NEW Metal1 ( 1612240 2287600 ) Via1_HV
+ NEW Metal1 ( 1596560 2290960 ) Via1_HV ;
+ - io_in[15] ( PIN io_in[15] ) ( wrapped_vga_clock io_in[15] ) + USE SIGNAL
+ + ROUTED Metal2 ( 5880560 2310000 ) ( * 5728800 )
+ NEW Metal2 ( 5880560 5728800 ) ( 5881680 * )
+ NEW Metal2 ( 5881680 5728800 ) ( * 5995920 0 )
+ NEW Metal3 ( 1122800 2060240 ) ( 1177680 * 0 )
+ NEW Metal2 ( 1122800 2060240 ) ( * 2310000 )
+ NEW Metal3 ( 1122800 2310000 ) ( 5880560 * )
+ NEW Metal2 ( 5880560 2310000 ) Via2_VH
+ NEW Metal2 ( 1122800 2060240 ) Via2_VH
+ NEW Metal2 ( 1122800 2310000 ) Via2_VH ;
+ - io_in[16] ( PIN io_in[16] ) ( wrapped_vga_clock io_in[16] ) + USE SIGNAL
+ + ROUTED Metal2 ( 5208560 5995920 ) ( 5215280 * )
NEW Metal2 ( 5215280 5994800 ) ( * 5995920 )
NEW Metal2 ( 5215280 5994800 ) ( 5216400 * )
NEW Metal2 ( 5216400 5994800 ) ( * 5995920 0 )
- NEW Metal2 ( 5208560 3015600 ) ( * 5995920 )
- NEW Metal3 ( 1933680 3015600 ) ( 5208560 * )
- NEW Metal2 ( 1933680 3015600 ) Via2_VH
- NEW Metal2 ( 5208560 3015600 ) Via2_VH ;
- - io_in[17] ( PIN io_in[17] ) ( mprj io_in[17] ) + USE SIGNAL
- + ROUTED Metal2 ( 4536560 5995920 ) ( 4550000 * )
- NEW Metal2 ( 4550000 5994800 ) ( * 5995920 )
- NEW Metal2 ( 4550000 5994800 ) ( 4551120 * )
- NEW Metal2 ( 4551120 5994800 ) ( * 5995920 0 )
- NEW Metal2 ( 4536560 3116400 ) ( * 5995920 )
- NEW Metal2 ( 1982960 2889040 ) ( 1988560 * 0 )
- NEW Metal3 ( 1982960 3116400 ) ( 4536560 * )
- NEW Metal2 ( 1982960 2889040 ) ( * 3116400 )
- NEW Metal2 ( 4536560 3116400 ) Via2_VH
- NEW Metal2 ( 1982960 3116400 ) Via2_VH ;
- - io_in[18] ( PIN io_in[18] ) ( mprj io_in[18] ) + USE SIGNAL
- + ROUTED Metal2 ( 2035600 2889040 0 ) ( * 2920400 )
- NEW Metal3 ( 2035600 2920400 ) ( 3881360 * )
+ NEW Metal2 ( 5208560 2294320 ) ( * 5995920 )
+ NEW Metal3 ( 1123920 1791440 ) ( 1177680 * 0 )
+ NEW Metal2 ( 1123920 1791440 ) ( * 2294320 )
+ NEW Metal3 ( 1123920 2294320 ) ( 5208560 * )
+ NEW Metal2 ( 5208560 2294320 ) Via2_VH
+ NEW Metal2 ( 1123920 1791440 ) Via2_VH
+ NEW Metal2 ( 1123920 2294320 ) Via2_VH ;
+ - io_in[17] ( PIN io_in[17] ) ( wrapped_vga_clock io_in[17] ) + USE SIGNAL
+ + ROUTED Metal1 ( 1383760 2287600 ) ( * 2290960 )
+ NEW Metal1 ( 1378160 2290960 ) ( 1383760 * )
+ NEW Metal2 ( 1378160 2290960 ) ( * 2411920 )
+ NEW Metal2 ( 1957200 2411920 ) ( * 5955600 )
+ NEW Metal2 ( 4551120 5955600 ) ( * 5995920 0 )
+ NEW Metal3 ( 1378160 2411920 ) ( 1957200 * )
+ NEW Metal3 ( 1957200 5955600 ) ( 4551120 * )
+ NEW Metal2 ( 1378160 2411920 ) Via2_VH
+ NEW Metal2 ( 1957200 2411920 ) Via2_VH
+ NEW Metal2 ( 1957200 5955600 ) Via2_VH
+ NEW Metal2 ( 4551120 5955600 ) Via2_VH
+ NEW Metal1 ( 1383760 2287600 ) Via1_HV
+ NEW Metal1 ( 1378160 2290960 ) Via1_HV ;
+ - io_in[18] ( PIN io_in[18] ) ( wrapped_vga_clock io_in[18] ) + USE SIGNAL
+ + ROUTED Metal2 ( 1337840 1653680 ) ( * 1692880 0 )
+ NEW Metal2 ( 1780240 1653680 ) ( * 1690640 )
+ NEW Metal3 ( 1337840 1653680 ) ( 1780240 * )
+ NEW Metal3 ( 1780240 1690640 ) ( 3881360 * )
NEW Metal2 ( 3881360 5995920 ) ( 3884720 * )
NEW Metal2 ( 3884720 5994800 ) ( * 5995920 )
NEW Metal2 ( 3884720 5994800 ) ( 3885840 * )
NEW Metal2 ( 3885840 5994800 ) ( * 5995920 0 )
- NEW Metal2 ( 3881360 2920400 ) ( * 5995920 )
- NEW Metal2 ( 2035600 2920400 ) Via2_VH
- NEW Metal2 ( 3881360 2920400 ) Via2_VH ;
- - io_in[19] ( PIN io_in[19] ) ( mprj io_in[19] ) + USE SIGNAL
- + ROUTED Metal2 ( 2082640 2889040 0 ) ( * 2922640 )
- NEW Metal3 ( 2082640 2922640 ) ( 3209360 * )
- NEW Metal2 ( 3209360 5995920 ) ( 3219440 * )
- NEW Metal2 ( 3219440 5994800 ) ( * 5995920 )
- NEW Metal2 ( 3219440 5994800 ) ( 3220560 * )
- NEW Metal2 ( 3220560 5994800 ) ( * 5995920 0 )
- NEW Metal2 ( 3209360 2922640 ) ( * 5995920 )
- NEW Metal2 ( 2082640 2922640 ) Via2_VH
- NEW Metal2 ( 3209360 2922640 ) Via2_VH ;
- - io_in[1] ( PIN io_in[1] ) ( mprj io_in[1] ) + USE SIGNAL
- + ROUTED Metal3 ( 1192240 2880080 ) ( 1235920 * )
- NEW Metal3 ( 1235920 2880080 ) ( * 2882320 )
- NEW Metal2 ( 5947760 468720 ) ( * 512400 )
- NEW Metal2 ( 1192240 512400 ) ( * 2880080 )
- NEW Metal3 ( 1192240 512400 ) ( 5947760 * )
- NEW Metal3 ( 5947760 468720 ) ( 5995920 * 0 )
- NEW Metal2 ( 1192240 512400 ) Via2_VH
- NEW Metal2 ( 1192240 2880080 ) Via2_VH
- NEW Metal2 ( 1235920 2882320 ) Via2_HH
- NEW Metal2 ( 5947760 512400 ) Via2_VH
- NEW Metal2 ( 5947760 468720 ) Via2_VH ;
- - io_in[20] ( PIN io_in[20] ) ( mprj io_in[20] ) + USE SIGNAL
- + ROUTED Metal2 ( 2121840 2889040 ) ( 2129680 * 0 )
- NEW Metal2 ( 2117360 3024000 ) ( 2121840 * )
- NEW Metal2 ( 2121840 2889040 ) ( * 3024000 )
- NEW Metal2 ( 2117360 3024000 ) ( * 3519600 )
- NEW Metal2 ( 2554160 3519600 ) ( * 5728800 )
- NEW Metal2 ( 2554160 5728800 ) ( 2555280 * )
- NEW Metal2 ( 2555280 5728800 ) ( * 5995920 0 )
- NEW Metal3 ( 2117360 3519600 ) ( 2554160 * )
- NEW Metal2 ( 2117360 3519600 ) Via2_VH
- NEW Metal2 ( 2554160 3519600 ) Via2_VH ;
- - io_in[21] ( PIN io_in[21] ) ( mprj io_in[21] ) + USE SIGNAL
- + ROUTED Metal3 ( 1892240 5947760 ) ( 1906800 * )
- NEW Metal2 ( 2168880 2889040 ) ( 2176720 * 0 )
- NEW Metal2 ( 1906800 3183600 ) ( * 5947760 )
- NEW Metal2 ( 1892240 5947760 ) ( * 5995920 0 )
- NEW Metal2 ( 2167760 3024000 ) ( 2168880 * )
- NEW Metal2 ( 2168880 2889040 ) ( * 3024000 )
- NEW Metal2 ( 2167760 3024000 ) ( * 3183600 )
- NEW Metal3 ( 1906800 3183600 ) ( 2167760 * )
- NEW Metal2 ( 1892240 5947760 ) Via2_VH
- NEW Metal2 ( 1906800 5947760 ) Via2_VH
- NEW Metal2 ( 1906800 3183600 ) Via2_VH
- NEW Metal2 ( 2167760 3183600 ) Via2_VH ;
- - io_in[22] ( PIN io_in[22] ) ( mprj io_in[22] ) + USE SIGNAL
- + ROUTED Metal2 ( 1210160 5995920 ) ( 1223600 * )
+ NEW Metal2 ( 3881360 1690640 ) ( * 5995920 )
+ NEW Metal2 ( 1337840 1653680 ) Via2_VH
+ NEW Metal2 ( 1780240 1653680 ) Via2_VH
+ NEW Metal2 ( 1780240 1690640 ) Via2_VH
+ NEW Metal2 ( 3881360 1690640 ) Via2_VH ;
+ - io_in[19] ( PIN io_in[19] ) ( wrapped_vga_clock io_in[19] ) + USE SIGNAL
+ + ROUTED Metal3 ( 1108240 5938800 ) ( 3220560 * )
+ NEW Metal3 ( 1108240 1771280 ) ( 1177680 * 0 )
+ NEW Metal2 ( 1108240 1771280 ) ( * 5938800 )
+ NEW Metal2 ( 3220560 5938800 ) ( * 5995920 0 )
+ NEW Metal2 ( 1108240 5938800 ) Via2_VH
+ NEW Metal2 ( 3220560 5938800 ) Via2_VH
+ NEW Metal2 ( 1108240 1771280 ) Via2_VH ;
+ - io_in[1] ( PIN io_in[1] ) ( wrapped_vga_clock io_in[1] ) + USE SIGNAL
+ + ROUTED Metal3 ( 5995920 454160 ) ( * 465360 )
+ NEW Metal3 ( 5994800 465360 ) ( 5995920 * )
+ NEW Metal3 ( 5994800 465360 ) ( * 466480 )
+ NEW Metal3 ( 5994800 466480 ) ( 5995920 * 0 )
+ NEW Metal3 ( 4342800 454160 ) ( 5995920 * )
+ NEW Metal3 ( 1772400 2228240 0 ) ( 4342800 * )
+ NEW Metal2 ( 4342800 454160 ) ( * 2228240 )
+ NEW Metal2 ( 4342800 454160 ) Via2_VH
+ NEW Metal2 ( 4342800 2228240 ) Via2_VH ;
+ - io_in[20] ( PIN io_in[20] ) ( wrapped_vga_clock io_in[20] ) + USE SIGNAL
+ + ROUTED Metal2 ( 2555280 5947760 ) ( * 5995920 0 )
+ NEW Metal3 ( 1772400 1710800 0 ) ( 2545200 * )
+ NEW Metal3 ( 2545200 5947760 ) ( 2555280 * )
+ NEW Metal2 ( 2545200 1710800 ) ( * 5947760 )
+ NEW Metal2 ( 2555280 5947760 ) Via2_VH
+ NEW Metal2 ( 2545200 1710800 ) Via2_VH
+ NEW Metal2 ( 2545200 5947760 ) Via2_VH ;
+ - io_in[21] ( PIN io_in[21] ) ( wrapped_vga_clock io_in[21] ) + USE SIGNAL
+ + ROUTED Metal3 ( 1873200 5947760 ) ( 1890000 * )
+ NEW Metal1 ( 1692880 2287600 ) ( * 2290960 )
+ NEW Metal2 ( 1692880 2290960 ) ( * 2344720 )
+ NEW Metal2 ( 1873200 2344720 ) ( * 5947760 )
+ NEW Metal2 ( 1890000 5947760 ) ( * 5995920 0 )
+ NEW Metal3 ( 1692880 2344720 ) ( 1873200 * )
+ NEW Metal2 ( 1692880 2344720 ) Via2_VH
+ NEW Metal2 ( 1873200 2344720 ) Via2_VH
+ NEW Metal2 ( 1873200 5947760 ) Via2_VH
+ NEW Metal2 ( 1890000 5947760 ) Via2_VH
+ NEW Metal1 ( 1692880 2287600 ) Via1_HV
+ NEW Metal1 ( 1692880 2290960 ) Via1_HV ;
+ - io_in[22] ( PIN io_in[22] ) ( wrapped_vga_clock io_in[22] ) + USE SIGNAL
+ + ROUTED Metal3 ( 1155280 2107280 ) ( 1177680 * 0 )
+ NEW Metal3 ( 1155280 2296560 ) ( 1210160 * )
+ NEW Metal2 ( 1155280 2107280 ) ( * 2296560 )
+ NEW Metal2 ( 1210160 5995920 ) ( 1223600 * )
NEW Metal2 ( 1223600 5994800 ) ( * 5995920 )
NEW Metal2 ( 1223600 5994800 ) ( 1224720 * )
NEW Metal2 ( 1224720 5994800 ) ( * 5995920 0 )
- NEW Metal2 ( 1210160 3016720 ) ( * 5995920 )
- NEW Metal2 ( 2218160 2889040 ) ( 2223760 * 0 )
- NEW Metal3 ( 1210160 3016720 ) ( 2218160 * )
- NEW Metal2 ( 2218160 2889040 ) ( * 3016720 )
- NEW Metal2 ( 1210160 3016720 ) Via2_VH
- NEW Metal2 ( 2218160 3016720 ) Via2_VH ;
- - io_in[23] ( PIN io_in[23] ) ( mprj io_in[23] ) + USE SIGNAL
- + ROUTED Metal2 ( 2268560 2889040 ) ( 2270800 * 0 )
- NEW Metal2 ( 554960 5995920 ) ( 558320 * )
+ NEW Metal2 ( 1210160 2296560 ) ( * 5995920 )
+ NEW Metal2 ( 1155280 2107280 ) Via2_VH
+ NEW Metal2 ( 1155280 2296560 ) Via2_VH
+ NEW Metal2 ( 1210160 2296560 ) Via2_VH ;
+ - io_in[23] ( PIN io_in[23] ) ( wrapped_vga_clock io_in[23] ) + USE SIGNAL
+ + ROUTED Metal2 ( 554960 5995920 ) ( 558320 * )
NEW Metal2 ( 558320 5994800 ) ( * 5995920 )
NEW Metal2 ( 558320 5994800 ) ( 559440 * )
NEW Metal2 ( 559440 5994800 ) ( * 5995920 0 )
- NEW Metal2 ( 554960 3150000 ) ( * 5995920 )
- NEW Metal3 ( 554960 3150000 ) ( 2268560 * )
- NEW Metal2 ( 2268560 2889040 ) ( * 3150000 )
- NEW Metal2 ( 554960 3150000 ) Via2_VH
- NEW Metal2 ( 2268560 3150000 ) Via2_VH ;
- - io_in[24] ( PIN io_in[24] ) ( mprj io_in[24] ) + USE SIGNAL
- + ROUTED Metal3 ( 3920 5914160 0 ) ( 75600 * )
- NEW Metal2 ( 75600 3033520 ) ( * 5914160 )
- NEW Metal2 ( 2311120 2889040 ) ( 2317840 * 0 )
- NEW Metal3 ( 75600 3033520 ) ( 2302160 * )
- NEW Metal2 ( 2302160 3024000 ) ( * 3033520 )
- NEW Metal2 ( 2302160 3024000 ) ( 2311120 * )
- NEW Metal2 ( 2311120 2889040 ) ( * 3024000 )
- NEW Metal2 ( 75600 3033520 ) Via2_VH
- NEW Metal2 ( 75600 5914160 ) Via2_VH
- NEW Metal2 ( 2302160 3033520 ) Via2_VH ;
- - io_in[25] ( PIN io_in[25] ) ( mprj io_in[25] ) + USE SIGNAL
+ NEW Metal2 ( 554960 2228240 ) ( * 5995920 )
+ NEW Metal3 ( 554960 2228240 ) ( 1177680 * 0 )
+ NEW Metal2 ( 554960 2228240 ) Via2_VH ;
+ - io_in[24] ( PIN io_in[24] ) ( wrapped_vga_clock io_in[24] ) + USE SIGNAL
+ + ROUTED Metal3 ( 1772400 1959440 0 ) ( 1781360 * )
+ NEW Metal3 ( 3920 5914160 0 ) ( 1781360 * )
+ NEW Metal2 ( 1781360 1959440 ) ( * 5914160 )
+ NEW Metal2 ( 1781360 1959440 ) Via2_VH
+ NEW Metal2 ( 1781360 5914160 ) Via2_VH ;
+ - io_in[25] ( PIN io_in[25] ) ( wrapped_vga_clock io_in[25] ) + USE SIGNAL
+ ROUTED Metal3 ( 3920 5477360 ) ( * 5486320 )
NEW Metal3 ( 3920 5486320 ) ( 5040 * )
NEW Metal3 ( 5040 5486320 ) ( * 5487440 )
NEW Metal3 ( 3920 5487440 0 ) ( 5040 * )
- NEW Metal2 ( 2357040 2889040 ) ( 2364880 * 0 )
- NEW Metal2 ( 2357040 2889040 ) ( * 3016720 )
- NEW Metal3 ( 3920 5477360 ) ( 2226000 * )
- NEW Metal3 ( 2226000 3016720 ) ( 2357040 * )
- NEW Metal2 ( 2226000 3016720 ) ( * 5477360 )
- NEW Metal2 ( 2357040 3016720 ) Via2_VH
- NEW Metal2 ( 2226000 5477360 ) Via2_VH
- NEW Metal2 ( 2226000 3016720 ) Via2_VH ;
- - io_in[26] ( PIN io_in[26] ) ( mprj io_in[26] ) + USE SIGNAL
- + ROUTED Metal2 ( 2404080 2889040 ) ( 2411920 * 0 )
- NEW Metal3 ( 3920 5057360 ) ( * 5059600 )
+ NEW Metal2 ( 546000 1751120 ) ( * 5477360 )
+ NEW Metal3 ( 3920 5477360 ) ( 546000 * )
+ NEW Metal3 ( 546000 1751120 ) ( 1177680 * 0 )
+ NEW Metal2 ( 546000 5477360 ) Via2_VH
+ NEW Metal2 ( 546000 1751120 ) Via2_VH ;
+ - io_in[26] ( PIN io_in[26] ) ( wrapped_vga_clock io_in[26] ) + USE SIGNAL
+ + ROUTED Metal3 ( 3920 5057360 ) ( * 5059600 )
NEW Metal3 ( 3920 5059600 ) ( 5040 * )
NEW Metal3 ( 5040 5059600 ) ( * 5060720 )
NEW Metal3 ( 3920 5060720 0 ) ( 5040 * )
- NEW Metal2 ( 2402960 3024000 ) ( 2404080 * )
- NEW Metal2 ( 2404080 2889040 ) ( * 3024000 )
- NEW Metal2 ( 2402960 3024000 ) ( * 5057360 )
- NEW Metal3 ( 3920 5057360 ) ( 2402960 * )
- NEW Metal2 ( 2402960 5057360 ) Via2_VH ;
- - io_in[27] ( PIN io_in[27] ) ( mprj io_in[27] ) + USE SIGNAL
- + ROUTED Metal3 ( 3920 4620560 ) ( * 4632880 )
+ NEW Metal3 ( 1083600 2248400 ) ( 1177680 * 0 )
+ NEW Metal3 ( 3920 5057360 ) ( 1083600 * )
+ NEW Metal2 ( 1083600 2248400 ) ( * 5057360 )
+ NEW Metal2 ( 1083600 2248400 ) Via2_VH
+ NEW Metal2 ( 1083600 5057360 ) Via2_VH ;
+ - io_in[27] ( PIN io_in[27] ) ( wrapped_vga_clock io_in[27] ) + USE SIGNAL
+ + ROUTED Metal3 ( 1453200 2334640 ) ( 1464400 * )
+ NEW Metal3 ( 3920 4620560 ) ( * 4632880 )
NEW Metal3 ( 3920 4632880 ) ( 5040 * )
NEW Metal3 ( 5040 4632880 ) ( * 4634000 )
NEW Metal3 ( 3920 4634000 0 ) ( 5040 * )
- NEW Metal2 ( 2453360 2889040 ) ( 2458960 * 0 )
- NEW Metal3 ( 126000 3050320 ) ( 2453360 * )
- NEW Metal3 ( 3920 4620560 ) ( 126000 * )
- NEW Metal2 ( 126000 3050320 ) ( * 4620560 )
- NEW Metal2 ( 2453360 2889040 ) ( * 3050320 )
- NEW Metal2 ( 126000 3050320 ) Via2_VH
- NEW Metal2 ( 2453360 3050320 ) Via2_VH
- NEW Metal2 ( 126000 4620560 ) Via2_VH ;
- - io_in[28] ( PIN io_in[28] ) ( mprj io_in[28] ) + USE SIGNAL
+ NEW Metal1 ( 1464400 2287600 ) ( * 2290960 )
+ NEW Metal2 ( 1464400 2290960 ) ( * 2334640 )
+ NEW Metal2 ( 1453200 2334640 ) ( * 4620560 )
+ NEW Metal3 ( 3920 4620560 ) ( 1453200 * )
+ NEW Metal2 ( 1453200 2334640 ) Via2_VH
+ NEW Metal2 ( 1464400 2334640 ) Via2_VH
+ NEW Metal1 ( 1464400 2287600 ) Via1_HV
+ NEW Metal1 ( 1464400 2290960 ) Via1_HV
+ NEW Metal2 ( 1453200 4620560 ) Via2_VH ;
+ - io_in[28] ( PIN io_in[28] ) ( wrapped_vga_clock io_in[28] ) + USE SIGNAL
+ ROUTED Metal3 ( 3920 4200560 ) ( * 4206160 )
NEW Metal3 ( 3920 4206160 ) ( 5040 * )
NEW Metal3 ( 5040 4206160 ) ( * 4207280 )
NEW Metal3 ( 3920 4207280 0 ) ( 5040 * )
- NEW Metal2 ( 2503760 2889040 ) ( 2506000 * 0 )
- NEW Metal3 ( 3920 4200560 ) ( 2503760 * )
- NEW Metal2 ( 2503760 2889040 ) ( * 4200560 )
- NEW Metal2 ( 2503760 4200560 ) Via2_VH ;
- - io_in[29] ( PIN io_in[29] ) ( mprj io_in[29] ) + USE SIGNAL
- + ROUTED Metal2 ( 2360400 3016720 ) ( * 3780560 )
- NEW Metal3 ( 3920 3780560 0 ) ( 2360400 * )
- NEW Metal2 ( 2546320 2889040 ) ( 2553040 * 0 )
- NEW Metal3 ( 2360400 3016720 ) ( 2546320 * )
- NEW Metal2 ( 2546320 2889040 ) ( * 3016720 )
- NEW Metal2 ( 2360400 3780560 ) Via2_VH
- NEW Metal2 ( 2360400 3016720 ) Via2_VH
- NEW Metal2 ( 2546320 3016720 ) Via2_VH ;
- - io_in[2] ( PIN io_in[2] ) ( mprj io_in[2] ) + USE SIGNAL
- + ROUTED Metal2 ( 1282960 2889040 0 ) ( * 2924880 )
- NEW Metal3 ( 1282960 2924880 ) ( 3956400 * )
- NEW Metal2 ( 3956400 857360 ) ( * 2924880 )
+ NEW Metal3 ( 3920 4200560 ) ( 1782480 * )
+ NEW Metal3 ( 1772400 2248400 0 ) ( 1782480 * )
+ NEW Metal2 ( 1782480 2248400 ) ( * 4200560 )
+ NEW Metal2 ( 1782480 4200560 ) Via2_VH
+ NEW Metal2 ( 1782480 2248400 ) Via2_VH ;
+ - io_in[29] ( PIN io_in[29] ) ( wrapped_vga_clock io_in[29] ) + USE SIGNAL
+ + ROUTED Metal3 ( 3920 3780560 0 ) ( 1050000 * )
+ NEW Metal2 ( 1753360 1677200 ) ( * 1692880 0 )
+ NEW Metal3 ( 1050000 1677200 ) ( 1753360 * )
+ NEW Metal2 ( 1050000 1677200 ) ( * 3780560 )
+ NEW Metal2 ( 1050000 1677200 ) Via2_VH
+ NEW Metal2 ( 1050000 3780560 ) Via2_VH
+ NEW Metal2 ( 1753360 1677200 ) Via2_VH ;
+ - io_in[2] ( PIN io_in[2] ) ( wrapped_vga_clock io_in[2] ) + USE SIGNAL
+ + ROUTED Metal3 ( 1772400 1872080 0 ) ( 5115600 * )
+ NEW Metal2 ( 5115600 857360 ) ( * 1872080 )
NEW Metal3 ( 5995920 857360 ) ( * 865200 )
NEW Metal3 ( 5994800 865200 ) ( 5995920 * )
NEW Metal3 ( 5994800 865200 ) ( * 866320 )
NEW Metal3 ( 5994800 866320 ) ( 5995920 * 0 )
- NEW Metal3 ( 3956400 857360 ) ( 5995920 * )
- NEW Metal2 ( 1282960 2924880 ) Via2_VH
- NEW Metal2 ( 3956400 857360 ) Via2_VH
- NEW Metal2 ( 3956400 2924880 ) Via2_VH ;
- - io_in[30] ( PIN io_in[30] ) ( mprj io_in[30] ) + USE SIGNAL
+ NEW Metal3 ( 5115600 857360 ) ( 5995920 * )
+ NEW Metal2 ( 5115600 1872080 ) Via2_VH
+ NEW Metal2 ( 5115600 857360 ) Via2_VH ;
+ - io_in[30] ( PIN io_in[30] ) ( wrapped_vga_clock io_in[30] ) + USE SIGNAL
+ ROUTED Metal3 ( 3920 3343760 ) ( * 3352720 )
NEW Metal3 ( 3920 3352720 ) ( 5040 * )
NEW Metal3 ( 5040 3352720 ) ( * 3353840 )
NEW Metal3 ( 3920 3353840 0 ) ( 5040 * )
- NEW Metal2 ( 2592240 2889040 ) ( 2600080 * 0 )
- NEW Metal2 ( 2587760 3024000 ) ( 2592240 * )
- NEW Metal2 ( 2592240 2889040 ) ( * 3024000 )
- NEW Metal2 ( 2587760 3024000 ) ( * 3343760 )
- NEW Metal3 ( 3920 3343760 ) ( 2587760 * )
- NEW Metal2 ( 2587760 3343760 ) Via2_VH ;
- - io_in[31] ( PIN io_in[31] ) ( mprj io_in[31] ) + USE SIGNAL
+ NEW Metal3 ( 1419600 2334640 ) ( 1444240 * )
+ NEW Metal1 ( 1444240 2287600 ) ( * 2290960 )
+ NEW Metal2 ( 1444240 2290960 ) ( * 2334640 )
+ NEW Metal2 ( 1419600 2334640 ) ( * 3343760 )
+ NEW Metal3 ( 3920 3343760 ) ( 1419600 * )
+ NEW Metal2 ( 1419600 2334640 ) Via2_VH
+ NEW Metal2 ( 1444240 2334640 ) Via2_VH
+ NEW Metal2 ( 1419600 3343760 ) Via2_VH
+ NEW Metal1 ( 1444240 2287600 ) Via1_HV
+ NEW Metal1 ( 1444240 2290960 ) Via1_HV ;
+ - io_in[31] ( PIN io_in[31] ) ( wrapped_vga_clock io_in[31] ) + USE SIGNAL
+ ROUTED Metal3 ( 3920 2923760 ) ( * 2926000 )
NEW Metal3 ( 3920 2926000 ) ( 5040 * )
NEW Metal3 ( 5040 2926000 ) ( * 2927120 )
NEW Metal3 ( 3920 2927120 0 ) ( 5040 * )
- NEW Metal2 ( 2647120 2889040 0 ) ( * 2923760 )
- NEW Metal3 ( 3920 2923760 ) ( 2647120 * )
- NEW Metal2 ( 2647120 2923760 ) Via2_VH ;
- - io_in[32] ( PIN io_in[32] ) ( mprj io_in[32] ) + USE SIGNAL
+ NEW Metal2 ( 1545040 1660400 ) ( * 1692880 0 )
+ NEW Metal3 ( 1066800 1660400 ) ( 1545040 * )
+ NEW Metal3 ( 3920 2923760 ) ( 1066800 * )
+ NEW Metal2 ( 1066800 1660400 ) ( * 2923760 )
+ NEW Metal2 ( 1066800 1660400 ) Via2_VH
+ NEW Metal2 ( 1545040 1660400 ) Via2_VH
+ NEW Metal2 ( 1066800 2923760 ) Via2_VH ;
+ - io_in[32] ( PIN io_in[32] ) ( wrapped_vga_clock io_in[32] ) + USE SIGNAL
+ ROUTED Metal3 ( 3920 2486960 ) ( * 2499280 )
NEW Metal3 ( 3920 2499280 ) ( 5040 * )
NEW Metal3 ( 5040 2499280 ) ( * 2500400 )
NEW Metal3 ( 3920 2500400 0 ) ( 5040 * )
- NEW Metal3 ( 3920 2486960 ) ( 142800 * )
- NEW Metal2 ( 142800 2486960 ) ( * 2926000 )
- NEW Metal3 ( 142800 2926000 ) ( 2694160 * )
- NEW Metal2 ( 2694160 2889040 0 ) ( * 2926000 )
- NEW Metal2 ( 142800 2486960 ) Via2_VH
- NEW Metal2 ( 142800 2926000 ) Via2_VH
- NEW Metal2 ( 2694160 2926000 ) Via2_VH ;
- - io_in[33] ( PIN io_in[33] ) ( mprj io_in[33] ) + USE SIGNAL
- + ROUTED Metal3 ( 3920 2066960 ) ( * 2072560 )
- NEW Metal3 ( 3920 2072560 ) ( 5040 * )
- NEW Metal3 ( 5040 2072560 ) ( * 2073680 )
- NEW Metal3 ( 3920 2073680 0 ) ( 5040 * )
- NEW Metal3 ( 3920 2066960 ) ( 865200 * )
- NEW Metal2 ( 865200 2066960 ) ( * 2929360 )
- NEW Metal3 ( 865200 2929360 ) ( 2741200 * )
- NEW Metal2 ( 2741200 2889040 0 ) ( * 2929360 )
- NEW Metal2 ( 865200 2066960 ) Via2_VH
- NEW Metal2 ( 865200 2929360 ) Via2_VH
- NEW Metal2 ( 2741200 2929360 ) Via2_VH ;
- - io_in[34] ( PIN io_in[34] ) ( mprj io_in[34] ) + USE SIGNAL
- + ROUTED Metal3 ( 3920 1646960 0 ) ( 579600 * )
- NEW Metal2 ( 579600 1646960 ) ( * 2927120 )
- NEW Metal3 ( 579600 2927120 ) ( 2788240 * )
- NEW Metal2 ( 2788240 2889040 0 ) ( * 2927120 )
- NEW Metal2 ( 579600 1646960 ) Via2_VH
- NEW Metal2 ( 579600 2927120 ) Via2_VH
- NEW Metal2 ( 2788240 2927120 ) Via2_VH ;
- - io_in[35] ( PIN io_in[35] ) ( mprj io_in[35] ) + USE SIGNAL
+ NEW Metal3 ( 1772400 1999760 0 ) ( 1817200 * )
+ NEW Metal3 ( 3920 2486960 ) ( 1817200 * )
+ NEW Metal2 ( 1817200 1999760 ) ( * 2486960 )
+ NEW Metal2 ( 1817200 1999760 ) Via2_VH
+ NEW Metal2 ( 1817200 2486960 ) Via2_VH ;
+ - io_in[33] ( PIN io_in[33] ) ( wrapped_vga_clock io_in[33] ) + USE SIGNAL
+ + ROUTED Metal2 ( 67760 2040080 ) ( * 2073680 )
+ NEW Metal3 ( 3920 2073680 0 ) ( 67760 * )
+ NEW Metal3 ( 67760 2040080 ) ( 1177680 * 0 )
+ NEW Metal2 ( 67760 2040080 ) Via2_VH
+ NEW Metal2 ( 67760 2073680 ) Via2_VH ;
+ - io_in[34] ( PIN io_in[34] ) ( wrapped_vga_clock io_in[34] ) + USE SIGNAL
+ + ROUTED Metal2 ( 1316560 1646960 ) ( * 1692880 0 )
+ NEW Metal3 ( 3920 1646960 0 ) ( 1316560 * )
+ NEW Metal2 ( 1316560 1646960 ) Via2_VH ;
+ - io_in[35] ( PIN io_in[35] ) ( wrapped_vga_clock io_in[35] ) + USE SIGNAL
+ ROUTED Metal3 ( 3920 1210160 ) ( * 1219120 )
NEW Metal3 ( 3920 1219120 ) ( 5040 * )
NEW Metal3 ( 5040 1219120 ) ( * 1220240 )
NEW Metal3 ( 3920 1220240 0 ) ( 5040 * )
- NEW Metal2 ( 2827440 2889040 ) ( 2835280 * 0 )
- NEW Metal2 ( 2827440 2889040 ) ( * 2957360 )
- NEW Metal3 ( 3920 1210160 ) ( 1117200 * )
- NEW Metal2 ( 1117200 1210160 ) ( * 2957360 )
- NEW Metal3 ( 1117200 2957360 ) ( 2827440 * )
- NEW Metal2 ( 2827440 2957360 ) Via2_VH
- NEW Metal2 ( 1117200 1210160 ) Via2_VH
- NEW Metal2 ( 1117200 2957360 ) Via2_VH ;
- - io_in[36] ( PIN io_in[36] ) ( mprj io_in[36] ) + USE SIGNAL
- + ROUTED Metal2 ( 2874480 2889040 ) ( 2882320 * 0 )
- NEW Metal3 ( 3920 795760 0 ) ( 43120 * )
- NEW Metal2 ( 43120 795760 ) ( * 3007760 )
- NEW Metal2 ( 2874480 2889040 ) ( * 3007760 )
- NEW Metal3 ( 43120 3007760 ) ( 2874480 * )
- NEW Metal2 ( 43120 795760 ) Via2_VH
- NEW Metal2 ( 43120 3007760 ) Via2_VH
- NEW Metal2 ( 2874480 3007760 ) Via2_VH ;
- - io_in[37] ( PIN io_in[37] ) ( mprj io_in[37] ) + USE SIGNAL
+ NEW Metal2 ( 538160 1210160 ) ( * 1234800 )
+ NEW Metal2 ( 1394960 1692880 ) ( 1403920 * 0 )
+ NEW Metal2 ( 1394960 1234800 ) ( * 1692880 )
+ NEW Metal3 ( 3920 1210160 ) ( 538160 * )
+ NEW Metal3 ( 538160 1234800 ) ( 1394960 * )
+ NEW Metal2 ( 538160 1210160 ) Via2_VH
+ NEW Metal2 ( 538160 1234800 ) Via2_VH
+ NEW Metal2 ( 1394960 1234800 ) Via2_VH ;
+ - io_in[36] ( PIN io_in[36] ) ( wrapped_vga_clock io_in[36] ) + USE SIGNAL
+ + ROUTED Metal3 ( 3920 790160 ) ( * 792400 )
+ NEW Metal3 ( 3920 792400 ) ( 5040 * )
+ NEW Metal3 ( 5040 792400 ) ( * 793520 )
+ NEW Metal3 ( 3920 793520 0 ) ( 5040 * )
+ NEW Metal3 ( 3920 790160 ) ( 1781360 * )
+ NEW Metal3 ( 1772400 1751120 0 ) ( 1781360 * )
+ NEW Metal2 ( 1781360 790160 ) ( * 1751120 )
+ NEW Metal2 ( 1781360 790160 ) Via2_VH
+ NEW Metal2 ( 1781360 1751120 ) Via2_VH ;
+ - io_in[37] ( PIN io_in[37] ) ( wrapped_vga_clock io_in[37] ) + USE SIGNAL
+ ROUTED Metal3 ( 3920 353360 ) ( * 365680 )
NEW Metal3 ( 3920 365680 ) ( 5040 * )
NEW Metal3 ( 5040 365680 ) ( * 366800 )
NEW Metal3 ( 3920 366800 0 ) ( 5040 * )
- NEW Metal3 ( 3920 353360 ) ( 2990960 * )
- NEW Metal3 ( 2929360 2906960 ) ( 2990960 * )
- NEW Metal2 ( 2929360 2889040 0 ) ( * 2906960 )
- NEW Metal2 ( 2990960 353360 ) ( * 2906960 )
- NEW Metal2 ( 2990960 353360 ) Via2_VH
- NEW Metal2 ( 2929360 2906960 ) Via2_VH
- NEW Metal2 ( 2990960 2906960 ) Via2_VH ;
- - io_in[3] ( PIN io_in[3] ) ( mprj io_in[3] ) + USE SIGNAL
- + ROUTED Metal2 ( 5955600 1268400 ) ( * 3074960 )
- NEW Metal2 ( 1327760 2889040 ) ( 1330000 * 0 )
- NEW Metal3 ( 1327760 3074960 ) ( 5955600 * )
- NEW Metal2 ( 1327760 2889040 ) ( * 3074960 )
- NEW Metal3 ( 5955600 1268400 ) ( 5995920 * 0 )
- NEW Metal2 ( 5955600 3074960 ) Via2_VH
- NEW Metal2 ( 5955600 1268400 ) Via2_VH
- NEW Metal2 ( 1327760 3074960 ) Via2_VH ;
- - io_in[4] ( PIN io_in[4] ) ( mprj io_in[4] ) + USE SIGNAL
- + ROUTED Metal2 ( 4208400 1663760 ) ( * 2873360 )
- NEW Metal4 ( 1377040 2873360 ) ( * 2882320 )
- NEW Metal3 ( 1377040 2873360 ) ( 4208400 * )
- NEW Metal3 ( 4208400 1663760 ) ( 5728800 * )
+ NEW Metal3 ( 562800 2147600 ) ( 1177680 * 0 )
+ NEW Metal3 ( 3920 353360 ) ( 562800 * )
+ NEW Metal2 ( 562800 353360 ) ( * 2147600 )
+ NEW Metal2 ( 562800 2147600 ) Via2_VH
+ NEW Metal2 ( 562800 353360 ) Via2_VH ;
+ - io_in[3] ( PIN io_in[3] ) ( wrapped_vga_clock io_in[3] ) + USE SIGNAL
+ + ROUTED Metal3 ( 1356880 2320080 ) ( 3250800 * )
+ NEW Metal1 ( 1356880 2287600 ) ( * 2290960 )
+ NEW Metal2 ( 1356880 2290960 ) ( * 2320080 )
+ NEW Metal2 ( 3250800 1260560 ) ( * 2320080 )
+ NEW Metal3 ( 5995920 1260560 ) ( * 1265040 )
+ NEW Metal3 ( 5994800 1265040 ) ( 5995920 * )
+ NEW Metal3 ( 5994800 1265040 ) ( * 1266160 )
+ NEW Metal3 ( 5994800 1266160 ) ( 5995920 * 0 )
+ NEW Metal3 ( 3250800 1260560 ) ( 5995920 * )
+ NEW Metal2 ( 1356880 2320080 ) Via2_VH
+ NEW Metal2 ( 3250800 2320080 ) Via2_VH
+ NEW Metal1 ( 1356880 2287600 ) Via1_HV
+ NEW Metal1 ( 1356880 2290960 ) Via1_HV
+ NEW Metal2 ( 3250800 1260560 ) Via2_VH ;
+ - io_in[4] ( PIN io_in[4] ) ( wrapped_vga_clock io_in[4] ) + USE SIGNAL
+ + ROUTED Metal3 ( 1772400 1898960 0 ) ( 3704400 * )
+ NEW Metal3 ( 3704400 1663760 ) ( 5728800 * )
NEW Metal3 ( 5728800 1663760 ) ( * 1666000 )
NEW Metal3 ( 5728800 1666000 ) ( 5995920 * 0 )
- NEW Metal2 ( 4208400 1663760 ) Via2_VH
- NEW Metal2 ( 4208400 2873360 ) Via2_VH
- NEW Metal3 ( 1377040 2873360 ) Via3_HV
- NEW Metal2 ( 1377040 2882320 ) Via2_HH
- NEW Metal3 ( 1377040 2882320 ) Via3_HV
- NEW Metal3 ( 1377040 2882320 ) RECT ( -660 -280 0 280 ) ;
- - io_in[5] ( PIN io_in[5] ) ( mprj io_in[5] ) + USE SIGNAL
- + ROUTED Metal3 ( 1424080 2877840 ) ( * 2882320 )
- NEW Metal3 ( 1424080 2877840 ) ( 2982000 * )
- NEW Metal2 ( 2982000 2066960 ) ( * 2877840 )
- NEW Metal3 ( 2982000 2066960 ) ( 5995920 * 0 )
- NEW Metal2 ( 1424080 2882320 ) Via2_HH
- NEW Metal2 ( 2982000 2877840 ) Via2_VH
- NEW Metal2 ( 2982000 2066960 ) Via2_VH ;
- - io_in[6] ( PIN io_in[6] ) ( mprj io_in[6] ) + USE SIGNAL
- + ROUTED Metal4 ( 1554000 2882320 ) ( 1555120 * )
- NEW Metal4 ( 1555120 2878960 ) ( * 2882320 )
- NEW Metal3 ( 1471120 2882320 ) ( 1554000 * )
- NEW Metal3 ( 1555120 2878960 ) ( 3015600 * )
- NEW Metal2 ( 3015600 2453360 ) ( * 2878960 )
+ NEW Metal2 ( 3704400 1663760 ) ( * 1898960 )
+ NEW Metal2 ( 3704400 1663760 ) Via2_VH
+ NEW Metal2 ( 3704400 1898960 ) Via2_VH ;
+ - io_in[5] ( PIN io_in[5] ) ( wrapped_vga_clock io_in[5] ) + USE SIGNAL
+ + ROUTED Metal2 ( 1904560 2019920 ) ( * 2066960 )
+ NEW Metal3 ( 1772400 2019920 0 ) ( 1904560 * )
+ NEW Metal3 ( 1904560 2066960 ) ( 5995920 * 0 )
+ NEW Metal2 ( 1904560 2019920 ) Via2_VH
+ NEW Metal2 ( 1904560 2066960 ) Via2_VH ;
+ - io_in[6] ( PIN io_in[6] ) ( wrapped_vga_clock io_in[6] ) + USE SIGNAL
+ + ROUTED Metal3 ( 1495760 2360400 ) ( 3478160 * )
+ NEW Metal1 ( 1495760 2287600 ) ( 1504720 * )
+ NEW Metal1 ( 1495760 2287600 ) ( * 2290960 )
+ NEW Metal2 ( 1495760 2290960 ) ( * 2360400 )
+ NEW Metal2 ( 3478160 2360400 ) ( * 2453360 )
NEW Metal3 ( 5995920 2453360 ) ( * 2464560 )
NEW Metal3 ( 5994800 2464560 ) ( 5995920 * )
NEW Metal3 ( 5994800 2464560 ) ( * 2465680 )
NEW Metal3 ( 5994800 2465680 ) ( 5995920 * 0 )
- NEW Metal3 ( 3015600 2453360 ) ( 5995920 * )
- NEW Metal2 ( 1471120 2882320 ) Via2_HH
- NEW Metal3 ( 1554000 2882320 ) Via3_HV
- NEW Metal3 ( 1555120 2878960 ) Via3_HV
- NEW Metal2 ( 3015600 2878960 ) Via2_VH
- NEW Metal2 ( 3015600 2453360 ) Via2_VH ;
- - io_in[7] ( PIN io_in[7] ) ( mprj io_in[7] ) + USE SIGNAL
- + ROUTED Metal4 ( 1518160 2863280 ) ( * 2883440 )
- NEW Metal3 ( 1518160 2863280 ) ( 5728800 * )
- NEW Metal3 ( 5728800 2863280 ) ( * 2865520 )
- NEW Metal3 ( 5728800 2865520 ) ( 5995920 * 0 )
- NEW Metal3 ( 1518160 2863280 ) Via3_HV
- NEW Metal2 ( 1518160 2883440 ) Via2_VH
- NEW Metal3 ( 1518160 2883440 ) Via3_HV
- NEW Metal3 ( 1518160 2883440 ) RECT ( -660 -280 0 280 ) ;
- - io_in[8] ( PIN io_in[8] ) ( mprj io_in[8] ) + USE SIGNAL
- + ROUTED Metal2 ( 1562960 2889040 ) ( 1565200 * 0 )
+ NEW Metal3 ( 3478160 2453360 ) ( 5995920 * )
+ NEW Metal2 ( 1495760 2360400 ) Via2_VH
+ NEW Metal2 ( 3478160 2360400 ) Via2_VH
+ NEW Metal1 ( 1504720 2287600 ) Via1_HV
+ NEW Metal1 ( 1495760 2290960 ) Via1_HV
+ NEW Metal2 ( 3478160 2453360 ) Via2_VH ;
+ - io_in[7] ( PIN io_in[7] ) ( wrapped_vga_clock io_in[7] ) + USE SIGNAL
+ + ROUTED Metal2 ( 3805200 1939280 ) ( * 2856560 )
+ NEW Metal3 ( 1772400 1939280 0 ) ( 3805200 * )
+ NEW Metal3 ( 5995920 2856560 ) ( * 2864400 )
+ NEW Metal3 ( 5994800 2864400 ) ( 5995920 * )
+ NEW Metal3 ( 5994800 2864400 ) ( * 2865520 )
+ NEW Metal3 ( 5994800 2865520 ) ( 5995920 * 0 )
+ NEW Metal3 ( 3805200 2856560 ) ( 5995920 * )
+ NEW Metal2 ( 3805200 1939280 ) Via2_VH
+ NEW Metal2 ( 3805200 2856560 ) Via2_VH ;
+ - io_in[8] ( PIN io_in[8] ) ( wrapped_vga_clock io_in[8] ) + USE SIGNAL
+ + ROUTED Metal2 ( 3536400 2343600 ) ( * 3259760 )
+ NEW Metal3 ( 1524880 2343600 ) ( 3536400 * )
NEW Metal3 ( 5995920 3259760 ) ( * 3264240 )
NEW Metal3 ( 5994800 3264240 ) ( 5995920 * )
NEW Metal3 ( 5994800 3264240 ) ( * 3265360 )
NEW Metal3 ( 5994800 3265360 ) ( 5995920 * 0 )
- NEW Metal3 ( 1562960 3259760 ) ( 5995920 * )
- NEW Metal2 ( 1562960 2889040 ) ( * 3259760 )
- NEW Metal2 ( 1562960 3259760 ) Via2_VH ;
- - io_in[9] ( PIN io_in[9] ) ( mprj io_in[9] ) + USE SIGNAL
- + ROUTED Metal2 ( 2646000 2966320 ) ( * 3662960 )
- NEW Metal2 ( 1604400 2889040 ) ( 1612240 * 0 )
- NEW Metal2 ( 1604400 2889040 ) ( * 2966320 )
- NEW Metal3 ( 1604400 2966320 ) ( 2646000 * )
- NEW Metal3 ( 2646000 3662960 ) ( 5728800 * )
+ NEW Metal3 ( 3536400 3259760 ) ( 5995920 * )
+ NEW Metal1 ( 1524880 2287600 ) ( * 2290960 )
+ NEW Metal2 ( 1524880 2290960 ) ( * 2343600 )
+ NEW Metal2 ( 3536400 2343600 ) Via2_VH
+ NEW Metal2 ( 3536400 3259760 ) Via2_VH
+ NEW Metal2 ( 1524880 2343600 ) Via2_VH
+ NEW Metal1 ( 1524880 2287600 ) Via1_HV
+ NEW Metal1 ( 1524880 2290960 ) Via1_HV ;
+ - io_in[9] ( PIN io_in[9] ) ( wrapped_vga_clock io_in[9] ) + USE SIGNAL
+ + ROUTED Metal3 ( 1565200 2351440 ) ( 1587600 * )
+ NEW Metal1 ( 1565200 2287600 ) ( * 2290960 )
+ NEW Metal2 ( 1565200 2290960 ) ( * 2351440 )
+ NEW Metal2 ( 1587600 2351440 ) ( * 3662960 )
+ NEW Metal3 ( 1587600 3662960 ) ( 5728800 * )
NEW Metal3 ( 5728800 3662960 ) ( * 3665200 )
NEW Metal3 ( 5728800 3665200 ) ( 5995920 * 0 )
- NEW Metal2 ( 2646000 2966320 ) Via2_VH
- NEW Metal2 ( 2646000 3662960 ) Via2_VH
- NEW Metal2 ( 1604400 2966320 ) Via2_VH ;
- - io_oeb[0] ( PIN io_oeb[0] ) ( mprj io_oeb[0] ) + USE SIGNAL
- + ROUTED Metal2 ( 1191120 2882320 ) ( 1204560 * 0 )
- NEW Metal2 ( 1191120 1419600 ) ( * 2882320 )
- NEW Metal2 ( 5956720 335440 ) ( * 1419600 )
- NEW Metal3 ( 1191120 1419600 ) ( 5956720 * )
- NEW Metal3 ( 5956720 335440 ) ( 5995920 * 0 )
- NEW Metal2 ( 1191120 1419600 ) Via2_VH
- NEW Metal2 ( 5956720 1419600 ) Via2_VH
- NEW Metal2 ( 5956720 335440 ) Via2_VH ;
- - io_oeb[10] ( PIN io_oeb[10] ) ( mprj io_oeb[10] ) + USE SIGNAL
- + ROUTED Metal2 ( 1674960 2889040 0 ) ( * 2931600 )
- NEW Metal3 ( 1674960 2931600 ) ( 1806000 * )
- NEW Metal2 ( 1806000 2931600 ) ( * 4318160 )
+ NEW Metal2 ( 1565200 2351440 ) Via2_VH
+ NEW Metal2 ( 1587600 2351440 ) Via2_VH
+ NEW Metal1 ( 1565200 2287600 ) Via1_HV
+ NEW Metal1 ( 1565200 2290960 ) Via1_HV
+ NEW Metal2 ( 1587600 3662960 ) Via2_VH ;
+ - io_oeb[0] ( PIN io_oeb[0] ) ( wrapped_vga_clock io_oeb[0] ) + USE SIGNAL
+ + ROUTED Metal3 ( 1652560 2318960 ) ( 1710800 * )
+ NEW Metal1 ( 1652560 2287600 ) ( * 2290960 )
+ NEW Metal3 ( 1710800 2317840 ) ( 1724240 * )
+ NEW Metal2 ( 1652560 2290960 ) ( * 2318960 )
+ NEW Metal3 ( 1710800 2317840 ) ( * 2318960 )
+ NEW Metal3 ( 1724240 2317840 ) ( * 2318960 )
+ NEW Metal2 ( 1873200 319760 ) ( * 2318960 )
+ NEW Metal3 ( 1724240 2318960 ) ( 1873200 * )
+ NEW Metal3 ( 5995920 319760 ) ( * 332080 )
+ NEW Metal3 ( 5994800 332080 ) ( 5995920 * )
+ NEW Metal3 ( 5994800 332080 ) ( * 333200 )
+ NEW Metal3 ( 5994800 333200 ) ( 5995920 * 0 )
+ NEW Metal3 ( 1873200 319760 ) ( 5995920 * )
+ NEW Metal2 ( 1652560 2318960 ) Via2_VH
+ NEW Metal2 ( 1873200 2318960 ) Via2_VH
+ NEW Metal1 ( 1652560 2287600 ) Via1_HV
+ NEW Metal1 ( 1652560 2290960 ) Via1_HV
+ NEW Metal2 ( 1873200 319760 ) Via2_VH ;
+ - io_oeb[10] ( PIN io_oeb[10] ) ( wrapped_vga_clock io_oeb[10] ) + USE SIGNAL
+ + ROUTED Metal2 ( 1906800 2301040 ) ( * 4318160 )
+ NEW Metal2 ( 1774640 2287600 0 ) ( 1780240 * )
+ NEW Metal2 ( 1780240 2287600 ) ( * 2301040 )
+ NEW Metal3 ( 1780240 2301040 ) ( 1906800 * )
NEW Metal3 ( 5995920 4318160 ) ( * 4330480 )
NEW Metal3 ( 5994800 4330480 ) ( 5995920 * )
NEW Metal3 ( 5994800 4330480 ) ( * 4331600 )
NEW Metal3 ( 5994800 4331600 ) ( 5995920 * 0 )
- NEW Metal3 ( 1806000 4318160 ) ( 5995920 * )
- NEW Metal2 ( 1674960 2931600 ) Via2_VH
- NEW Metal2 ( 1806000 2931600 ) Via2_VH
- NEW Metal2 ( 1806000 4318160 ) Via2_VH ;
- - io_oeb[11] ( PIN io_oeb[11] ) ( mprj io_oeb[11] ) + USE SIGNAL
- + ROUTED Metal2 ( 1714160 2889040 ) ( 1722000 * 0 )
- NEW Metal2 ( 1714160 2889040 ) ( * 4721360 )
- NEW Metal3 ( 5995920 4721360 ) ( * 4730320 )
- NEW Metal3 ( 5994800 4730320 ) ( 5995920 * )
- NEW Metal3 ( 5994800 4730320 ) ( * 4731440 )
- NEW Metal3 ( 5994800 4731440 ) ( 5995920 * 0 )
- NEW Metal3 ( 1714160 4721360 ) ( 5995920 * )
- NEW Metal2 ( 1714160 4721360 ) Via2_VH ;
- - io_oeb[12] ( PIN io_oeb[12] ) ( mprj io_oeb[12] ) + USE SIGNAL
- + ROUTED Metal2 ( 1764560 2889040 ) ( 1769040 * 0 )
- NEW Metal3 ( 1764560 3100720 ) ( 2696400 * )
- NEW Metal2 ( 1764560 2889040 ) ( * 3100720 )
- NEW Metal2 ( 2696400 3100720 ) ( * 5124560 )
+ NEW Metal3 ( 1906800 4318160 ) ( 5995920 * )
+ NEW Metal2 ( 1906800 2301040 ) Via2_VH
+ NEW Metal2 ( 1906800 4318160 ) Via2_VH
+ NEW Metal2 ( 1780240 2301040 ) Via2_VH ;
+ - io_oeb[11] ( PIN io_oeb[11] ) ( wrapped_vga_clock io_oeb[11] ) + USE SIGNAL
+ + ROUTED Metal2 ( 5922000 2187920 ) ( * 4731440 )
+ NEW Metal3 ( 1772400 2187920 0 ) ( 5922000 * )
+ NEW Metal3 ( 5922000 4731440 ) ( 5995920 * 0 )
+ NEW Metal2 ( 5922000 2187920 ) Via2_VH
+ NEW Metal2 ( 5922000 4731440 ) Via2_VH ;
+ - io_oeb[12] ( PIN io_oeb[12] ) ( wrapped_vga_clock io_oeb[12] ) + USE SIGNAL
+ + ROUTED Metal2 ( 1257200 1676080 ) ( * 1692880 0 )
+ NEW Metal2 ( 1940400 1676080 ) ( * 5124560 )
+ NEW Metal3 ( 1257200 1676080 ) ( 1940400 * )
NEW Metal3 ( 5995920 5124560 ) ( * 5130160 )
NEW Metal3 ( 5994800 5130160 ) ( 5995920 * )
NEW Metal3 ( 5994800 5130160 ) ( * 5131280 )
NEW Metal3 ( 5994800 5131280 ) ( 5995920 * 0 )
- NEW Metal3 ( 2696400 5124560 ) ( 5995920 * )
- NEW Metal2 ( 1764560 3100720 ) Via2_VH
- NEW Metal2 ( 2696400 3100720 ) Via2_VH
- NEW Metal2 ( 2696400 5124560 ) Via2_VH ;
- - io_oeb[13] ( PIN io_oeb[13] ) ( mprj io_oeb[13] ) + USE SIGNAL
- + ROUTED Metal2 ( 1814960 3024000 ) ( 1816080 * )
- NEW Metal2 ( 1816080 2889040 0 ) ( * 3024000 )
- NEW Metal2 ( 1814960 3024000 ) ( * 5527760 )
+ NEW Metal3 ( 1940400 5124560 ) ( 5995920 * )
+ NEW Metal2 ( 1257200 1676080 ) Via2_VH
+ NEW Metal2 ( 1940400 1676080 ) Via2_VH
+ NEW Metal2 ( 1940400 5124560 ) Via2_VH ;
+ - io_oeb[13] ( PIN io_oeb[13] ) ( wrapped_vga_clock io_oeb[13] ) + USE SIGNAL
+ + ROUTED Metal1 ( 1276240 2287600 ) ( * 2290960 )
+ NEW Metal1 ( 1260560 2290960 ) ( 1276240 * )
+ NEW Metal2 ( 1260560 2290960 ) ( * 5527760 )
NEW Metal3 ( 5995920 5527760 ) ( * 5530000 )
NEW Metal3 ( 5994800 5530000 ) ( 5995920 * )
NEW Metal3 ( 5994800 5530000 ) ( * 5531120 )
NEW Metal3 ( 5994800 5531120 ) ( 5995920 * 0 )
- NEW Metal3 ( 1814960 5527760 ) ( 5995920 * )
- NEW Metal2 ( 1814960 5527760 ) Via2_VH ;
- - io_oeb[14] ( PIN io_oeb[14] ) ( mprj io_oeb[14] ) + USE SIGNAL
- + ROUTED Metal2 ( 1863120 2889040 0 ) ( * 2931600 )
- NEW Metal3 ( 2024400 5930960 ) ( 5995920 * 0 )
- NEW Metal3 ( 1863120 2931600 ) ( 2024400 * )
- NEW Metal2 ( 2024400 2931600 ) ( * 5930960 )
- NEW Metal2 ( 1863120 2931600 ) Via2_VH
- NEW Metal2 ( 2024400 5930960 ) Via2_VH
- NEW Metal2 ( 2024400 2931600 ) Via2_VH ;
- - io_oeb[15] ( PIN io_oeb[15] ) ( mprj io_oeb[15] ) + USE SIGNAL
- + ROUTED Metal2 ( 1902320 2889040 ) ( 1910160 * 0 )
- NEW Metal2 ( 1902320 2889040 ) ( * 2967440 )
- NEW Metal2 ( 2662800 2967440 ) ( * 5955600 )
- NEW Metal2 ( 5438160 5955600 ) ( * 5995920 0 )
- NEW Metal3 ( 2662800 5955600 ) ( 5438160 * )
- NEW Metal3 ( 1902320 2967440 ) ( 2662800 * )
- NEW Metal2 ( 2662800 5955600 ) Via2_VH
- NEW Metal2 ( 5438160 5955600 ) Via2_VH
- NEW Metal2 ( 1902320 2967440 ) Via2_VH
- NEW Metal2 ( 2662800 2967440 ) Via2_VH ;
- - io_oeb[16] ( PIN io_oeb[16] ) ( mprj io_oeb[16] ) + USE SIGNAL
- + ROUTED Metal2 ( 1949360 2889040 ) ( 1957200 * 0 )
- NEW Metal2 ( 1949360 2889040 ) ( * 3099600 )
- NEW Metal2 ( 3133200 3099600 ) ( * 5956720 )
- NEW Metal2 ( 4772880 5956720 ) ( * 5995920 0 )
- NEW Metal3 ( 1949360 3099600 ) ( 3133200 * )
- NEW Metal3 ( 3133200 5956720 ) ( 4772880 * )
- NEW Metal2 ( 1949360 3099600 ) Via2_VH
- NEW Metal2 ( 3133200 3099600 ) Via2_VH
- NEW Metal2 ( 3133200 5956720 ) Via2_VH
- NEW Metal2 ( 4772880 5956720 ) Via2_VH ;
- - io_oeb[17] ( PIN io_oeb[17] ) ( mprj io_oeb[17] ) + USE SIGNAL
- + ROUTED Metal2 ( 1999760 2889040 ) ( 2004240 * 0 )
- NEW Metal2 ( 1999760 2889040 ) ( * 3200400 )
- NEW Metal3 ( 1999760 3200400 ) ( 4099760 * )
+ NEW Metal3 ( 1260560 5527760 ) ( 5995920 * )
+ NEW Metal1 ( 1276240 2287600 ) Via1_HV
+ NEW Metal1 ( 1260560 2290960 ) Via1_HV
+ NEW Metal2 ( 1260560 5527760 ) Via2_VH ;
+ - io_oeb[14] ( PIN io_oeb[14] ) ( wrapped_vga_clock io_oeb[14] ) + USE SIGNAL
+ + ROUTED Metal2 ( 1444240 1674960 ) ( * 1692880 0 )
+ NEW Metal2 ( 2125200 1674960 ) ( * 5930960 )
+ NEW Metal3 ( 1444240 1674960 ) ( 2125200 * )
+ NEW Metal3 ( 2125200 5930960 ) ( 5995920 * 0 )
+ NEW Metal2 ( 1444240 1674960 ) Via2_VH
+ NEW Metal2 ( 2125200 1674960 ) Via2_VH
+ NEW Metal2 ( 2125200 5930960 ) Via2_VH ;
+ - io_oeb[15] ( PIN io_oeb[15] ) ( wrapped_vga_clock io_oeb[15] ) + USE SIGNAL
+ + ROUTED Metal2 ( 1680560 1662640 ) ( * 1688400 )
+ NEW Metal2 ( 5426960 5995920 ) ( 5437040 * )
+ NEW Metal2 ( 5437040 5994800 ) ( * 5995920 )
+ NEW Metal2 ( 5437040 5994800 ) ( 5438160 * )
+ NEW Metal2 ( 5438160 5994800 ) ( * 5995920 0 )
+ NEW Metal2 ( 5426960 1688400 ) ( * 5995920 )
+ NEW Metal2 ( 1526000 1662640 ) ( * 1692880 0 )
+ NEW Metal3 ( 1526000 1662640 ) ( 1680560 * )
+ NEW Metal3 ( 1680560 1688400 ) ( 5426960 * )
+ NEW Metal2 ( 1680560 1662640 ) Via2_VH
+ NEW Metal2 ( 1680560 1688400 ) Via2_VH
+ NEW Metal2 ( 5426960 1688400 ) Via2_VH
+ NEW Metal2 ( 1526000 1662640 ) Via2_VH ;
+ - io_oeb[16] ( PIN io_oeb[16] ) ( wrapped_vga_clock io_oeb[16] ) + USE SIGNAL
+ + ROUTED Metal2 ( 4772880 5956720 ) ( * 5995920 0 )
+ NEW Metal3 ( 4326000 5957840 ) ( 4435200 * )
+ NEW Metal3 ( 4435200 5956720 ) ( * 5957840 )
+ NEW Metal3 ( 4435200 5956720 ) ( 4772880 * )
+ NEW Metal3 ( 1772400 2208080 0 ) ( 4326000 * )
+ NEW Metal2 ( 4326000 2208080 ) ( * 5957840 )
+ NEW Metal2 ( 4772880 5956720 ) Via2_VH
+ NEW Metal2 ( 4326000 5957840 ) Via2_VH
+ NEW Metal2 ( 4326000 2208080 ) Via2_VH ;
+ - io_oeb[17] ( PIN io_oeb[17] ) ( wrapped_vga_clock io_oeb[17] ) + USE SIGNAL
+ + ROUTED Metal2 ( 1713040 1662640 ) ( * 1692880 0 )
+ NEW Metal3 ( 1713040 1662640 ) ( 1818320 * )
+ NEW Metal2 ( 1818320 1662640 ) ( * 1755600 )
+ NEW Metal3 ( 1818320 1755600 ) ( 4099760 * )
NEW Metal2 ( 4099760 5995920 ) ( 4106480 * )
NEW Metal2 ( 4106480 5994800 ) ( * 5995920 )
NEW Metal2 ( 4106480 5994800 ) ( 4107600 * )
NEW Metal2 ( 4107600 5994800 ) ( * 5995920 0 )
- NEW Metal2 ( 4099760 3200400 ) ( * 5995920 )
- NEW Metal2 ( 1999760 3200400 ) Via2_VH
- NEW Metal2 ( 4099760 3200400 ) Via2_VH ;
- - io_oeb[18] ( PIN io_oeb[18] ) ( mprj io_oeb[18] ) + USE SIGNAL
- + ROUTED Metal2 ( 2050160 3024000 ) ( 2051280 * )
- NEW Metal2 ( 2051280 2889040 0 ) ( * 3024000 )
- NEW Metal2 ( 2050160 3024000 ) ( * 3234000 )
- NEW Metal3 ( 2050160 3234000 ) ( 3427760 * )
- NEW Metal2 ( 3427760 5995920 ) ( 3441200 * )
- NEW Metal2 ( 3441200 5994800 ) ( * 5995920 )
- NEW Metal2 ( 3441200 5994800 ) ( 3442320 * )
- NEW Metal2 ( 3442320 5994800 ) ( * 5995920 0 )
- NEW Metal2 ( 3427760 3234000 ) ( * 5995920 )
- NEW Metal2 ( 2050160 3234000 ) Via2_VH
- NEW Metal2 ( 3427760 3234000 ) Via2_VH ;
- - io_oeb[19] ( PIN io_oeb[19] ) ( mprj io_oeb[19] ) + USE SIGNAL
- + ROUTED Metal2 ( 2090480 2889040 ) ( 2098320 * 0 )
- NEW Metal2 ( 2090480 2889040 ) ( * 2986480 )
- NEW Metal3 ( 2679600 5947760 ) ( 2777040 * )
- NEW Metal3 ( 2090480 2986480 ) ( 2679600 * )
- NEW Metal2 ( 2679600 2986480 ) ( * 5947760 )
- NEW Metal2 ( 2777040 5947760 ) ( * 5995920 0 )
- NEW Metal2 ( 2090480 2986480 ) Via2_VH
- NEW Metal2 ( 2679600 5947760 ) Via2_VH
- NEW Metal2 ( 2777040 5947760 ) Via2_VH
- NEW Metal2 ( 2679600 2986480 ) Via2_VH ;
- - io_oeb[1] ( PIN io_oeb[1] ) ( mprj io_oeb[1] ) + USE SIGNAL
- + ROUTED Metal2 ( 1243760 2889040 ) ( 1251600 * 0 )
- NEW Metal2 ( 1243760 2889040 ) ( * 2940560 )
- NEW Metal3 ( 5995920 722960 ) ( * 731920 )
+ NEW Metal2 ( 4099760 1755600 ) ( * 5995920 )
+ NEW Metal2 ( 1713040 1662640 ) Via2_VH
+ NEW Metal2 ( 1818320 1662640 ) Via2_VH
+ NEW Metal2 ( 1818320 1755600 ) Via2_VH
+ NEW Metal2 ( 4099760 1755600 ) Via2_VH ;
+ - io_oeb[18] ( PIN io_oeb[18] ) ( wrapped_vga_clock io_oeb[18] ) + USE SIGNAL
+ + ROUTED Metal3 ( 2713200 5957840 ) ( 3442320 * )
+ NEW Metal3 ( 1772400 2080400 0 ) ( 2713200 * )
+ NEW Metal2 ( 2713200 2080400 ) ( * 5957840 )
+ NEW Metal2 ( 3442320 5957840 ) ( * 5995920 0 )
+ NEW Metal2 ( 2713200 5957840 ) Via2_VH
+ NEW Metal2 ( 3442320 5957840 ) Via2_VH
+ NEW Metal2 ( 2713200 2080400 ) Via2_VH ;
+ - io_oeb[19] ( PIN io_oeb[19] ) ( wrapped_vga_clock io_oeb[19] ) + USE SIGNAL
+ + ROUTED Metal1 ( 1424080 2287600 ) ( * 2290960 )
+ NEW Metal2 ( 1424080 2290960 ) ( * 2326800 )
+ NEW Metal2 ( 1547280 2326800 ) ( * 2410800 )
+ NEW Metal3 ( 1424080 2326800 ) ( 1547280 * )
+ NEW Metal3 ( 1547280 2410800 ) ( 2772560 * )
+ NEW Metal2 ( 2772560 5995920 ) ( 2775920 * )
+ NEW Metal2 ( 2775920 5994800 ) ( * 5995920 )
+ NEW Metal2 ( 2775920 5994800 ) ( 2777040 * )
+ NEW Metal2 ( 2777040 5994800 ) ( * 5995920 0 )
+ NEW Metal2 ( 2772560 2410800 ) ( * 5995920 )
+ NEW Metal2 ( 1424080 2326800 ) Via2_VH
+ NEW Metal1 ( 1424080 2287600 ) Via1_HV
+ NEW Metal1 ( 1424080 2290960 ) Via1_HV
+ NEW Metal2 ( 1547280 2326800 ) Via2_VH
+ NEW Metal2 ( 1547280 2410800 ) Via2_VH
+ NEW Metal2 ( 2772560 2410800 ) Via2_VH ;
+ - io_oeb[1] ( PIN io_oeb[1] ) ( wrapped_vga_clock io_oeb[1] ) + USE SIGNAL
+ + ROUTED Metal3 ( 5995920 722960 ) ( * 731920 )
NEW Metal3 ( 5994800 731920 ) ( 5995920 * )
NEW Metal3 ( 5994800 731920 ) ( * 733040 )
NEW Metal3 ( 5994800 733040 ) ( 5995920 * 0 )
- NEW Metal3 ( 4426800 722960 ) ( 5995920 * )
- NEW Metal3 ( 1243760 2940560 ) ( 4426800 * )
- NEW Metal2 ( 4426800 722960 ) ( * 2940560 )
- NEW Metal2 ( 1243760 2940560 ) Via2_VH
- NEW Metal2 ( 4426800 722960 ) Via2_VH
- NEW Metal2 ( 4426800 2940560 ) Via2_VH ;
- - io_oeb[20] ( PIN io_oeb[20] ) ( mprj io_oeb[20] ) + USE SIGNAL
- + ROUTED Metal2 ( 2137520 2889040 ) ( 2145360 * 0 )
- NEW Metal3 ( 2114000 5947760 ) ( 2134160 * )
- NEW Metal2 ( 2134160 3024000 ) ( 2137520 * )
- NEW Metal2 ( 2137520 2889040 ) ( * 3024000 )
- NEW Metal2 ( 2134160 3024000 ) ( * 5947760 )
- NEW Metal2 ( 2114000 5947760 ) ( * 5995920 0 )
- NEW Metal2 ( 2114000 5947760 ) Via2_VH
- NEW Metal2 ( 2134160 5947760 ) Via2_VH ;
- - io_oeb[21] ( PIN io_oeb[21] ) ( mprj io_oeb[21] ) + USE SIGNAL
- + ROUTED Metal2 ( 2184560 2889040 ) ( 2192400 * 0 )
+ NEW Metal3 ( 1125040 722960 ) ( 5995920 * )
+ NEW Metal2 ( 1125040 722960 ) ( * 1979600 )
+ NEW Metal3 ( 1125040 1979600 ) ( 1177680 * 0 )
+ NEW Metal2 ( 1125040 722960 ) Via2_VH
+ NEW Metal2 ( 1125040 1979600 ) Via2_VH ;
+ - io_oeb[20] ( PIN io_oeb[20] ) ( wrapped_vga_clock io_oeb[20] ) + USE SIGNAL
+ + ROUTED Metal2 ( 2100560 5995920 ) ( 2110640 * )
+ NEW Metal2 ( 2110640 5994800 ) ( * 5995920 )
+ NEW Metal2 ( 2110640 5994800 ) ( 2111760 * )
+ NEW Metal2 ( 2111760 5994800 ) ( * 5995920 0 )
+ NEW Metal2 ( 2100560 2361520 ) ( * 5995920 )
+ NEW Metal3 ( 1316560 2327920 ) ( 1361360 * )
+ NEW Metal2 ( 1361360 2327920 ) ( * 2361520 )
+ NEW Metal3 ( 1361360 2361520 ) ( 2100560 * )
+ NEW Metal1 ( 1316560 2287600 ) ( * 2290960 )
+ NEW Metal2 ( 1316560 2290960 ) ( * 2327920 )
+ NEW Metal2 ( 2100560 2361520 ) Via2_VH
+ NEW Metal2 ( 1316560 2327920 ) Via2_VH
+ NEW Metal2 ( 1361360 2327920 ) Via2_VH
+ NEW Metal2 ( 1361360 2361520 ) Via2_VH
+ NEW Metal1 ( 1316560 2287600 ) Via1_HV
+ NEW Metal1 ( 1316560 2290960 ) Via1_HV ;
+ - io_oeb[21] ( PIN io_oeb[21] ) ( wrapped_vga_clock io_oeb[21] ) + USE SIGNAL
+ + ROUTED Metal3 ( 1470000 2334640 ) ( 1484560 * )
+ NEW Metal3 ( 1448720 5947760 ) ( 1470000 * )
+ NEW Metal1 ( 1484560 2287600 ) ( * 2290960 )
+ NEW Metal2 ( 1484560 2290960 ) ( * 2334640 )
+ NEW Metal2 ( 1470000 2334640 ) ( * 5947760 )
NEW Metal2 ( 1448720 5947760 ) ( * 5995920 0 )
- NEW Metal2 ( 2184560 2889040 ) ( * 2985360 )
- NEW Metal3 ( 1448720 5947760 ) ( 1520400 * )
- NEW Metal2 ( 1520400 2985360 ) ( * 5947760 )
- NEW Metal3 ( 1520400 2985360 ) ( 2184560 * )
+ NEW Metal2 ( 1470000 2334640 ) Via2_VH
+ NEW Metal2 ( 1484560 2334640 ) Via2_VH
NEW Metal2 ( 1448720 5947760 ) Via2_VH
- NEW Metal2 ( 2184560 2985360 ) Via2_VH
- NEW Metal2 ( 1520400 5947760 ) Via2_VH
- NEW Metal2 ( 1520400 2985360 ) Via2_VH ;
- - io_oeb[22] ( PIN io_oeb[22] ) ( mprj io_oeb[22] ) + USE SIGNAL
- + ROUTED Metal2 ( 783440 5955600 ) ( * 5995920 0 )
- NEW Metal2 ( 1470000 2948400 ) ( * 5955600 )
- NEW Metal3 ( 783440 5955600 ) ( 1470000 * )
- NEW Metal2 ( 2234960 2889040 ) ( 2239440 * 0 )
- NEW Metal3 ( 1470000 2948400 ) ( 2234960 * )
- NEW Metal2 ( 2234960 2889040 ) ( * 2948400 )
+ NEW Metal2 ( 1470000 5947760 ) Via2_VH
+ NEW Metal1 ( 1484560 2287600 ) Via1_HV
+ NEW Metal1 ( 1484560 2290960 ) Via1_HV ;
+ - io_oeb[22] ( PIN io_oeb[22] ) ( wrapped_vga_clock io_oeb[22] ) + USE SIGNAL
+ + ROUTED Metal2 ( 1652560 1673840 ) ( * 1692880 0 )
+ NEW Metal2 ( 783440 5955600 ) ( * 5995920 0 )
+ NEW Metal3 ( 783440 5955600 ) ( 1033200 * )
+ NEW Metal3 ( 1033200 1673840 ) ( 1652560 * )
+ NEW Metal2 ( 1033200 1673840 ) ( * 5955600 )
NEW Metal2 ( 783440 5955600 ) Via2_VH
- NEW Metal2 ( 1470000 5955600 ) Via2_VH
- NEW Metal2 ( 1470000 2948400 ) Via2_VH
- NEW Metal2 ( 2234960 2948400 ) Via2_VH ;
- - io_oeb[23] ( PIN io_oeb[23] ) ( mprj io_oeb[23] ) + USE SIGNAL
- + ROUTED Metal2 ( 101360 5995920 ) ( 114800 * )
+ NEW Metal2 ( 1652560 1673840 ) Via2_VH
+ NEW Metal2 ( 1033200 1673840 ) Via2_VH
+ NEW Metal2 ( 1033200 5955600 ) Via2_VH ;
+ - io_oeb[23] ( PIN io_oeb[23] ) ( wrapped_vga_clock io_oeb[23] ) + USE SIGNAL
+ + ROUTED Metal2 ( 966000 1659280 ) ( * 5569200 )
+ NEW Metal2 ( 1356880 1659280 ) ( * 1692880 0 )
+ NEW Metal3 ( 966000 1659280 ) ( 1356880 * )
+ NEW Metal2 ( 101360 5995920 ) ( 114800 * )
NEW Metal2 ( 114800 5994800 ) ( * 5995920 )
NEW Metal2 ( 114800 5994800 ) ( 115920 * )
NEW Metal2 ( 115920 5994800 ) ( * 5995920 0 )
- NEW Metal2 ( 101360 3250800 ) ( * 5995920 )
- NEW Metal2 ( 2285360 3024000 ) ( 2286480 * )
- NEW Metal2 ( 2286480 2889040 0 ) ( * 3024000 )
- NEW Metal3 ( 101360 3250800 ) ( 2285360 * )
- NEW Metal2 ( 2285360 3024000 ) ( * 3250800 )
- NEW Metal2 ( 101360 3250800 ) Via2_VH
- NEW Metal2 ( 2285360 3250800 ) Via2_VH ;
- - io_oeb[24] ( PIN io_oeb[24] ) ( mprj io_oeb[24] ) + USE SIGNAL
- + ROUTED Metal2 ( 2325680 2889040 ) ( 2333520 * 0 )
- NEW Metal2 ( 2318960 3024000 ) ( 2325680 * )
- NEW Metal2 ( 2325680 2889040 ) ( * 3024000 )
- NEW Metal2 ( 2318960 3024000 ) ( * 5628560 )
- NEW Metal3 ( 3920 5629680 0 ) ( 84000 * )
+ NEW Metal2 ( 101360 5569200 ) ( * 5995920 )
+ NEW Metal3 ( 101360 5569200 ) ( 966000 * )
+ NEW Metal2 ( 966000 1659280 ) Via2_VH
+ NEW Metal2 ( 966000 5569200 ) Via2_VH
+ NEW Metal2 ( 1356880 1659280 ) Via2_VH
+ NEW Metal2 ( 101360 5569200 ) Via2_VH ;
+ - io_oeb[24] ( PIN io_oeb[24] ) ( wrapped_vga_clock io_oeb[24] ) + USE SIGNAL
+ + ROUTED Metal3 ( 3920 5629680 0 ) ( 84000 * )
NEW Metal3 ( 84000 5628560 ) ( * 5629680 )
- NEW Metal3 ( 84000 5628560 ) ( 2318960 * )
- NEW Metal2 ( 2318960 5628560 ) Via2_VH ;
- - io_oeb[25] ( PIN io_oeb[25] ) ( mprj io_oeb[25] ) + USE SIGNAL
+ NEW Metal3 ( 1772400 1851920 0 ) ( 1800400 * )
+ NEW Metal3 ( 84000 5628560 ) ( 1772400 * )
+ NEW Metal3 ( 1772400 2292080 ) ( 1800400 * )
+ NEW Metal2 ( 1800400 1851920 ) ( * 2292080 )
+ NEW Metal2 ( 1772400 2292080 ) ( * 5628560 )
+ NEW Metal2 ( 1800400 1851920 ) Via2_VH
+ NEW Metal2 ( 1772400 5628560 ) Via2_VH
+ NEW Metal2 ( 1772400 2292080 ) Via2_VH
+ NEW Metal2 ( 1800400 2292080 ) Via2_VH ;
+ - io_oeb[25] ( PIN io_oeb[25] ) ( wrapped_vga_clock io_oeb[25] ) + USE SIGNAL
+ ROUTED Metal3 ( 3920 5191760 ) ( * 5201840 )
NEW Metal3 ( 3920 5201840 ) ( 5040 * )
NEW Metal3 ( 5040 5201840 ) ( * 5202960 )
NEW Metal3 ( 3920 5202960 0 ) ( 5040 * )
- NEW Metal2 ( 2372720 2889040 ) ( 2380560 * 0 )
- NEW Metal2 ( 2369360 3024000 ) ( 2372720 * )
- NEW Metal2 ( 2372720 2889040 ) ( * 3024000 )
- NEW Metal2 ( 2369360 3024000 ) ( * 5191760 )
- NEW Metal3 ( 3920 5191760 ) ( 2369360 * )
- NEW Metal2 ( 2369360 5191760 ) Via2_VH ;
- - io_oeb[26] ( PIN io_oeb[26] ) ( mprj io_oeb[26] ) + USE SIGNAL
- + ROUTED Metal3 ( 3920 4776240 0 ) ( 44240 * )
- NEW Metal2 ( 44240 2918160 ) ( * 4776240 )
- NEW Metal2 ( 2427600 2889040 0 ) ( * 2918160 )
- NEW Metal3 ( 44240 2918160 ) ( 2427600 * )
- NEW Metal2 ( 44240 4776240 ) Via2_VH
- NEW Metal2 ( 44240 2918160 ) Via2_VH
- NEW Metal2 ( 2427600 2918160 ) Via2_VH ;
- - io_oeb[27] ( PIN io_oeb[27] ) ( mprj io_oeb[27] ) + USE SIGNAL
- + ROUTED Metal3 ( 3920 4349520 0 ) ( 43120 * )
- NEW Metal2 ( 43120 3049200 ) ( * 4349520 )
- NEW Metal2 ( 2470160 2889040 ) ( 2474640 * 0 )
- NEW Metal3 ( 43120 3049200 ) ( 2470160 * )
- NEW Metal2 ( 2470160 2889040 ) ( * 3049200 )
- NEW Metal2 ( 43120 3049200 ) Via2_VH
- NEW Metal2 ( 43120 4349520 ) Via2_VH
- NEW Metal2 ( 2470160 3049200 ) Via2_VH ;
- - io_oeb[28] ( PIN io_oeb[28] ) ( mprj io_oeb[28] ) + USE SIGNAL
+ NEW Metal3 ( 3920 5191760 ) ( 579600 * )
+ NEW Metal3 ( 579600 2343600 ) ( 1336720 * )
+ NEW Metal2 ( 579600 2343600 ) ( * 5191760 )
+ NEW Metal1 ( 1336720 2287600 ) ( * 2290960 )
+ NEW Metal2 ( 1336720 2290960 ) ( * 2343600 )
+ NEW Metal2 ( 579600 2343600 ) Via2_VH
+ NEW Metal2 ( 579600 5191760 ) Via2_VH
+ NEW Metal2 ( 1336720 2343600 ) Via2_VH
+ NEW Metal1 ( 1336720 2287600 ) Via1_HV
+ NEW Metal1 ( 1336720 2290960 ) Via1_HV ;
+ - io_oeb[26] ( PIN io_oeb[26] ) ( wrapped_vga_clock io_oeb[26] ) + USE SIGNAL
+ + ROUTED Metal3 ( 3920 4771760 ) ( * 4775120 )
+ NEW Metal3 ( 3920 4775120 ) ( 5040 * )
+ NEW Metal3 ( 5040 4775120 ) ( * 4776240 )
+ NEW Metal3 ( 3920 4776240 0 ) ( 5040 * )
+ NEW Metal3 ( 1772400 2107280 0 ) ( 1814960 * )
+ NEW Metal3 ( 3920 4771760 ) ( 1814960 * )
+ NEW Metal2 ( 1814960 2107280 ) ( * 4771760 )
+ NEW Metal2 ( 1814960 2107280 ) Via2_VH
+ NEW Metal2 ( 1814960 4771760 ) Via2_VH ;
+ - io_oeb[27] ( PIN io_oeb[27] ) ( wrapped_vga_clock io_oeb[27] ) + USE SIGNAL
+ + ROUTED Metal2 ( 1215760 1679440 ) ( * 1692880 0 )
+ NEW Metal3 ( 3920 4334960 ) ( * 4348400 )
+ NEW Metal3 ( 3920 4348400 ) ( 5040 * )
+ NEW Metal3 ( 5040 4348400 ) ( * 4349520 )
+ NEW Metal3 ( 3920 4349520 0 ) ( 5040 * )
+ NEW Metal2 ( 915600 1679440 ) ( * 4334960 )
+ NEW Metal3 ( 915600 1679440 ) ( 1215760 * )
+ NEW Metal3 ( 3920 4334960 ) ( 915600 * )
+ NEW Metal2 ( 915600 1679440 ) Via2_VH
+ NEW Metal2 ( 1215760 1679440 ) Via2_VH
+ NEW Metal2 ( 915600 4334960 ) Via2_VH ;
+ - io_oeb[28] ( PIN io_oeb[28] ) ( wrapped_vga_clock io_oeb[28] ) + USE SIGNAL
+ ROUTED Metal3 ( 3920 3914960 ) ( * 3921680 )
NEW Metal3 ( 3920 3921680 ) ( 5040 * )
NEW Metal3 ( 5040 3921680 ) ( * 3922800 )
NEW Metal3 ( 3920 3922800 0 ) ( 5040 * )
- NEW Metal2 ( 2520560 3024000 ) ( 2521680 * )
- NEW Metal2 ( 2521680 2889040 0 ) ( * 3024000 )
- NEW Metal3 ( 3920 3914960 ) ( 2520560 * )
- NEW Metal2 ( 2520560 3024000 ) ( * 3914960 )
- NEW Metal2 ( 2520560 3914960 ) Via2_VH ;
- - io_oeb[29] ( PIN io_oeb[29] ) ( mprj io_oeb[29] ) + USE SIGNAL
- + ROUTED Metal2 ( 2560880 2889040 ) ( 2568720 * 0 )
- NEW Metal2 ( 2554160 3024000 ) ( 2560880 * )
- NEW Metal2 ( 2560880 2889040 ) ( * 3024000 )
- NEW Metal2 ( 2554160 3024000 ) ( * 3494960 )
- NEW Metal3 ( 3920 3496080 0 ) ( 84000 * )
+ NEW Metal2 ( 932400 1654800 ) ( * 3914960 )
+ NEW Metal2 ( 1733200 1654800 ) ( * 1692880 0 )
+ NEW Metal3 ( 932400 1654800 ) ( 1733200 * )
+ NEW Metal3 ( 3920 3914960 ) ( 932400 * )
+ NEW Metal2 ( 932400 1654800 ) Via2_VH
+ NEW Metal2 ( 932400 3914960 ) Via2_VH
+ NEW Metal2 ( 1733200 1654800 ) Via2_VH ;
+ - io_oeb[29] ( PIN io_oeb[29] ) ( wrapped_vga_clock io_oeb[29] ) + USE SIGNAL
+ + ROUTED Metal3 ( 3920 3496080 0 ) ( 84000 * )
NEW Metal3 ( 84000 3494960 ) ( * 3496080 )
- NEW Metal3 ( 84000 3494960 ) ( 2554160 * )
- NEW Metal2 ( 2554160 3494960 ) Via2_VH ;
- - io_oeb[2] ( PIN io_oeb[2] ) ( mprj io_oeb[2] ) + USE SIGNAL
- + ROUTED Metal2 ( 4477200 1126160 ) ( * 2941680 )
- NEW Metal2 ( 1294160 2889040 ) ( 1298640 * 0 )
- NEW Metal2 ( 1294160 2889040 ) ( * 2941680 )
- NEW Metal3 ( 1294160 2941680 ) ( 4477200 * )
+ NEW Metal3 ( 84000 3494960 ) ( 1816080 * )
+ NEW Metal3 ( 1772400 1811600 0 ) ( 1816080 * )
+ NEW Metal2 ( 1816080 1811600 ) ( * 3494960 )
+ NEW Metal2 ( 1816080 3494960 ) Via2_VH
+ NEW Metal2 ( 1816080 1811600 ) Via2_VH ;
+ - io_oeb[2] ( PIN io_oeb[2] ) ( wrapped_vga_clock io_oeb[2] ) + USE SIGNAL
+ + ROUTED Metal1 ( 1753360 2287600 ) ( * 2290960 )
+ NEW Metal2 ( 1753360 2290960 ) ( * 2302160 )
+ NEW Metal3 ( 1753360 2302160 ) ( 3721200 * )
+ NEW Metal2 ( 3721200 1126160 ) ( * 2302160 )
NEW Metal3 ( 5995920 1126160 ) ( * 1131760 )
NEW Metal3 ( 5994800 1131760 ) ( 5995920 * )
NEW Metal3 ( 5994800 1131760 ) ( * 1132880 )
NEW Metal3 ( 5994800 1132880 ) ( 5995920 * 0 )
- NEW Metal3 ( 4477200 1126160 ) ( 5995920 * )
- NEW Metal2 ( 4477200 1126160 ) Via2_VH
- NEW Metal2 ( 4477200 2941680 ) Via2_VH
- NEW Metal2 ( 1294160 2941680 ) Via2_VH ;
- - io_oeb[30] ( PIN io_oeb[30] ) ( mprj io_oeb[30] ) + USE SIGNAL
- + ROUTED Metal3 ( 3920 3069360 0 ) ( 48720 * )
- NEW Metal2 ( 48720 2915920 ) ( * 3069360 )
- NEW Metal2 ( 2615760 2889040 0 ) ( * 2915920 )
- NEW Metal3 ( 48720 2915920 ) ( 2615760 * )
- NEW Metal2 ( 48720 3069360 ) Via2_VH
- NEW Metal2 ( 48720 2915920 ) Via2_VH
- NEW Metal2 ( 2615760 2915920 ) Via2_VH ;
- - io_oeb[31] ( PIN io_oeb[31] ) ( mprj io_oeb[31] ) + USE SIGNAL
+ NEW Metal3 ( 3721200 1126160 ) ( 5995920 * )
+ NEW Metal1 ( 1753360 2287600 ) Via1_HV
+ NEW Metal1 ( 1753360 2290960 ) Via1_HV
+ NEW Metal2 ( 1753360 2302160 ) Via2_VH
+ NEW Metal2 ( 3721200 1126160 ) Via2_VH
+ NEW Metal2 ( 3721200 2302160 ) Via2_VH ;
+ - io_oeb[30] ( PIN io_oeb[30] ) ( wrapped_vga_clock io_oeb[30] ) + USE SIGNAL
+ + ROUTED Metal3 ( 3920 3069360 0 ) ( 75600 * )
+ NEW Metal2 ( 75600 2187920 ) ( * 3069360 )
+ NEW Metal3 ( 75600 2187920 ) ( 1177680 * 0 )
+ NEW Metal2 ( 75600 2187920 ) Via2_VH
+ NEW Metal2 ( 75600 3069360 ) Via2_VH ;
+ - io_oeb[31] ( PIN io_oeb[31] ) ( wrapped_vga_clock io_oeb[31] ) + USE SIGNAL
+ ROUTED Metal3 ( 3920 2638160 ) ( * 2641520 )
NEW Metal3 ( 3920 2641520 ) ( 5040 * )
NEW Metal3 ( 5040 2641520 ) ( * 2642640 )
NEW Metal3 ( 3920 2642640 0 ) ( 5040 * )
- NEW Metal3 ( 1421840 2880080 ) ( * 2883440 )
- NEW Metal3 ( 1421840 2883440 ) ( 1426320 * )
- NEW Metal3 ( 1426320 2881200 ) ( * 2883440 )
- NEW Metal2 ( 1150800 2638160 ) ( * 2878960 )
- NEW Metal3 ( 3920 2638160 ) ( 1150800 * )
- NEW Metal3 ( 1150800 2878960 ) ( 1260000 * )
- NEW Metal3 ( 1260000 2878960 ) ( * 2880080 )
- NEW Metal3 ( 1260000 2880080 ) ( 1421840 * )
- NEW Metal3 ( 1556240 2880080 ) ( * 2881200 )
- NEW Metal3 ( 1426320 2881200 ) ( 1556240 * )
- NEW Metal3 ( 1556240 2880080 ) ( 2436000 * )
- NEW Metal3 ( 2436000 2880080 ) ( * 2882320 )
- NEW Metal3 ( 2436000 2882320 ) ( 2662800 * )
- NEW Metal2 ( 1150800 2638160 ) Via2_VH
- NEW Metal2 ( 1150800 2878960 ) Via2_VH
- NEW Metal2 ( 2662800 2882320 ) Via2_HH ;
- - io_oeb[32] ( PIN io_oeb[32] ) ( mprj io_oeb[32] ) + USE SIGNAL
- + ROUTED Metal3 ( 3920 2217040 0 ) ( 75600 * )
- NEW Metal2 ( 75600 2217040 ) ( * 2942800 )
- NEW Metal2 ( 2705360 2889040 ) ( 2709840 * 0 )
- NEW Metal3 ( 75600 2942800 ) ( 2705360 * )
- NEW Metal2 ( 2705360 2889040 ) ( * 2942800 )
- NEW Metal2 ( 75600 2217040 ) Via2_VH
- NEW Metal2 ( 75600 2942800 ) Via2_VH
- NEW Metal2 ( 2705360 2942800 ) Via2_VH ;
- - io_oeb[33] ( PIN io_oeb[33] ) ( mprj io_oeb[33] ) + USE SIGNAL
+ NEW Metal2 ( 1672720 1661520 ) ( * 1692880 0 )
+ NEW Metal2 ( 210000 1661520 ) ( * 2638160 )
+ NEW Metal3 ( 3920 2638160 ) ( 210000 * )
+ NEW Metal3 ( 210000 1661520 ) ( 1672720 * )
+ NEW Metal2 ( 210000 1661520 ) Via2_VH
+ NEW Metal2 ( 210000 2638160 ) Via2_VH
+ NEW Metal2 ( 1672720 1661520 ) Via2_VH ;
+ - io_oeb[32] ( PIN io_oeb[32] ) ( wrapped_vga_clock io_oeb[32] ) + USE SIGNAL
+ + ROUTED Metal2 ( 1424080 1674960 ) ( * 1692880 0 )
+ NEW Metal3 ( 3920 2201360 ) ( * 2214800 )
+ NEW Metal3 ( 3920 2214800 ) ( 5040 * )
+ NEW Metal3 ( 5040 2214800 ) ( * 2215920 )
+ NEW Metal3 ( 3920 2215920 0 ) ( 5040 * )
+ NEW Metal3 ( 1083600 1674960 ) ( 1424080 * )
+ NEW Metal3 ( 3920 2201360 ) ( 1083600 * )
+ NEW Metal2 ( 1083600 1674960 ) ( * 2201360 )
+ NEW Metal2 ( 1424080 1674960 ) Via2_VH
+ NEW Metal2 ( 1083600 1674960 ) Via2_VH
+ NEW Metal2 ( 1083600 2201360 ) Via2_VH ;
+ - io_oeb[33] ( PIN io_oeb[33] ) ( wrapped_vga_clock io_oeb[33] ) + USE SIGNAL
+ ROUTED Metal3 ( 3920 1781360 ) ( * 1788080 )
NEW Metal3 ( 3920 1788080 ) ( 5040 * )
NEW Metal3 ( 5040 1788080 ) ( * 1789200 )
NEW Metal3 ( 3920 1789200 0 ) ( 5040 * )
- NEW Metal3 ( 3920 1781360 ) ( 159600 * )
- NEW Metal2 ( 159600 1781360 ) ( * 2943920 )
- NEW Metal3 ( 159600 2943920 ) ( 2756880 * )
- NEW Metal2 ( 2756880 2889040 0 ) ( * 2943920 )
- NEW Metal2 ( 159600 1781360 ) Via2_VH
- NEW Metal2 ( 159600 2943920 ) Via2_VH
- NEW Metal2 ( 2756880 2943920 ) Via2_VH ;
- - io_oeb[34] ( PIN io_oeb[34] ) ( mprj io_oeb[34] ) + USE SIGNAL
- + ROUTED Metal2 ( 2796080 2889040 ) ( 2803920 * 0 )
- NEW Metal2 ( 1184400 1361360 ) ( * 2992080 )
- NEW Metal2 ( 2796080 2889040 ) ( * 2992080 )
+ NEW Metal3 ( 579600 2167760 ) ( 1177680 * 0 )
+ NEW Metal3 ( 3920 1781360 ) ( 579600 * )
+ NEW Metal2 ( 579600 1781360 ) ( * 2167760 )
+ NEW Metal2 ( 579600 2167760 ) Via2_VH
+ NEW Metal2 ( 579600 1781360 ) Via2_VH ;
+ - io_oeb[34] ( PIN io_oeb[34] ) ( wrapped_vga_clock io_oeb[34] ) + USE SIGNAL
+ + ROUTED Metal3 ( 1772400 2147600 0 ) ( 1782480 * )
NEW Metal3 ( 3920 1362480 0 ) ( 84000 * )
NEW Metal3 ( 84000 1361360 ) ( * 1362480 )
- NEW Metal3 ( 84000 1361360 ) ( 1184400 * )
- NEW Metal3 ( 1184400 2992080 ) ( 2796080 * )
- NEW Metal2 ( 1184400 1361360 ) Via2_VH
- NEW Metal2 ( 1184400 2992080 ) Via2_VH
- NEW Metal2 ( 2796080 2992080 ) Via2_VH ;
- - io_oeb[35] ( PIN io_oeb[35] ) ( mprj io_oeb[35] ) + USE SIGNAL
+ NEW Metal3 ( 84000 1361360 ) ( 1782480 * )
+ NEW Metal2 ( 1782480 1361360 ) ( * 2147600 )
+ NEW Metal2 ( 1782480 2147600 ) Via2_VH
+ NEW Metal2 ( 1782480 1361360 ) Via2_VH ;
+ - io_oeb[35] ( PIN io_oeb[35] ) ( wrapped_vga_clock io_oeb[35] ) + USE SIGNAL
+ ROUTED Metal3 ( 3920 924560 ) ( * 934640 )
NEW Metal3 ( 3920 934640 ) ( 5040 * )
NEW Metal3 ( 5040 934640 ) ( * 935760 )
NEW Metal3 ( 3920 935760 0 ) ( 5040 * )
- NEW Metal2 ( 2850960 2889040 0 ) ( * 2894640 )
- NEW Metal3 ( 3920 924560 ) ( 1033200 * )
- NEW Metal3 ( 1033200 2894640 ) ( 2850960 * )
- NEW Metal2 ( 1033200 924560 ) ( * 2894640 )
- NEW Metal2 ( 2850960 2894640 ) Via2_VH
- NEW Metal2 ( 1033200 924560 ) Via2_VH
- NEW Metal2 ( 1033200 2894640 ) Via2_VH ;
- - io_oeb[36] ( PIN io_oeb[36] ) ( mprj io_oeb[36] ) + USE SIGNAL
+ NEW Metal3 ( 3920 924560 ) ( 613200 * )
+ NEW Metal3 ( 613200 1959440 ) ( 1177680 * 0 )
+ NEW Metal2 ( 613200 924560 ) ( * 1959440 )
+ NEW Metal2 ( 613200 924560 ) Via2_VH
+ NEW Metal2 ( 613200 1959440 ) Via2_VH ;
+ - io_oeb[36] ( PIN io_oeb[36] ) ( wrapped_vga_clock io_oeb[36] ) + USE SIGNAL
+ ROUTED Metal3 ( 3920 504560 ) ( * 507920 )
NEW Metal3 ( 3920 507920 ) ( 5040 * )
NEW Metal3 ( 5040 507920 ) ( * 509040 )
NEW Metal3 ( 3920 509040 0 ) ( 5040 * )
- NEW Metal2 ( 2898000 2889040 0 ) ( * 2892400 )
- NEW Metal3 ( 3920 504560 ) ( 176400 * )
- NEW Metal3 ( 176400 2892400 ) ( 2898000 * )
- NEW Metal2 ( 176400 504560 ) ( * 2892400 )
- NEW Metal2 ( 2898000 2892400 ) Via2_VH
- NEW Metal2 ( 176400 504560 ) Via2_VH
- NEW Metal2 ( 176400 2892400 ) Via2_VH ;
- - io_oeb[37] ( PIN io_oeb[37] ) ( mprj io_oeb[37] ) + USE SIGNAL
- + ROUTED Metal3 ( 3920 83440 0 ) ( 109200 * )
- NEW Metal2 ( 2945040 2889040 0 ) ( * 2891280 )
- NEW Metal3 ( 109200 2891280 ) ( 2945040 * )
- NEW Metal2 ( 109200 83440 ) ( * 2891280 )
- NEW Metal2 ( 109200 83440 ) Via2_VH
- NEW Metal2 ( 109200 2891280 ) Via2_VH
- NEW Metal2 ( 2945040 2891280 ) Via2_VH ;
- - io_oeb[3] ( PIN io_oeb[3] ) ( mprj io_oeb[3] ) + USE SIGNAL
- + ROUTED Metal2 ( 5956720 1534960 ) ( * 3125360 )
- NEW Metal3 ( 1344560 3125360 ) ( 5956720 * )
- NEW Metal2 ( 1344560 3024000 ) ( * 3125360 )
- NEW Metal2 ( 1344560 3024000 ) ( 1345680 * )
- NEW Metal2 ( 1345680 2889040 0 ) ( * 3024000 )
- NEW Metal3 ( 5956720 1534960 ) ( 5995920 * 0 )
- NEW Metal2 ( 5956720 3125360 ) Via2_VH
- NEW Metal2 ( 5956720 1534960 ) Via2_VH
- NEW Metal2 ( 1344560 3125360 ) Via2_VH ;
- - io_oeb[4] ( PIN io_oeb[4] ) ( mprj io_oeb[4] ) + USE SIGNAL
- + ROUTED Metal4 ( 1392720 2876720 ) ( * 2882320 )
- NEW Metal2 ( 3032400 1932560 ) ( * 2876720 )
- NEW Metal3 ( 1392720 2876720 ) ( 3032400 * )
- NEW Metal3 ( 3032400 1932560 ) ( 5995920 * 0 )
- NEW Metal3 ( 1392720 2876720 ) Via3_HV
- NEW Metal2 ( 1392720 2882320 ) Via2_HH
- NEW Metal3 ( 1392720 2882320 ) Via3_HV
- NEW Metal2 ( 3032400 1932560 ) Via2_VH
- NEW Metal2 ( 3032400 2876720 ) Via2_VH
- NEW Metal3 ( 1392720 2882320 ) RECT ( -660 -280 0 280 ) ;
- - io_oeb[5] ( PIN io_oeb[5] ) ( mprj io_oeb[5] ) + USE SIGNAL
- + ROUTED Metal2 ( 1439760 2889040 0 ) ( * 2895760 )
- NEW Metal2 ( 3049200 2318960 ) ( * 2895760 )
- NEW Metal3 ( 1439760 2895760 ) ( 3049200 * )
+ NEW Metal3 ( 3920 504560 ) ( 1772400 * )
+ NEW Metal2 ( 1772400 504560 ) ( * 1495200 )
+ NEW Metal2 ( 1772400 1495200 ) ( 1774640 * )
+ NEW Metal3 ( 1772400 1730960 0 ) ( 1774640 * )
+ NEW Metal2 ( 1774640 1495200 ) ( * 1730960 )
+ NEW Metal2 ( 1772400 504560 ) Via2_VH
+ NEW Metal2 ( 1774640 1730960 ) Via2_VH ;
+ - io_oeb[37] ( PIN io_oeb[37] ) ( wrapped_vga_clock io_oeb[37] ) + USE SIGNAL
+ + ROUTED Metal3 ( 3920 67760 ) ( * 81200 )
+ NEW Metal3 ( 3920 81200 ) ( 5040 * )
+ NEW Metal3 ( 5040 81200 ) ( * 82320 )
+ NEW Metal3 ( 3920 82320 0 ) ( 5040 * )
+ NEW Metal3 ( 1177680 2288720 0 ) ( * 2289840 )
+ NEW Metal3 ( 3920 67760 ) ( 646800 * )
+ NEW Metal2 ( 646800 67760 ) ( * 2289840 )
+ NEW Metal3 ( 646800 2289840 ) ( 1177680 * )
+ NEW Metal2 ( 646800 67760 ) Via2_VH
+ NEW Metal2 ( 646800 2289840 ) Via2_VH ;
+ - io_oeb[3] ( PIN io_oeb[3] ) ( wrapped_vga_clock io_oeb[3] ) + USE SIGNAL
+ + ROUTED Metal1 ( 1256080 2287600 ) ( * 2290960 )
+ NEW Metal2 ( 1256080 2290960 ) ( * 2303280 )
+ NEW Metal2 ( 1923600 1529360 ) ( * 2303280 )
+ NEW Metal3 ( 1256080 2303280 ) ( 1923600 * )
+ NEW Metal3 ( 5995920 1529360 ) ( * 1531600 )
+ NEW Metal3 ( 5994800 1531600 ) ( 5995920 * )
+ NEW Metal3 ( 5994800 1531600 ) ( * 1532720 )
+ NEW Metal3 ( 5994800 1532720 ) ( 5995920 * 0 )
+ NEW Metal3 ( 1923600 1529360 ) ( 5995920 * )
+ NEW Metal1 ( 1256080 2287600 ) Via1_HV
+ NEW Metal1 ( 1256080 2290960 ) Via1_HV
+ NEW Metal2 ( 1256080 2303280 ) Via2_VH
+ NEW Metal2 ( 1923600 1529360 ) Via2_VH
+ NEW Metal2 ( 1923600 2303280 ) Via2_VH ;
+ - io_oeb[4] ( PIN io_oeb[4] ) ( wrapped_vga_clock io_oeb[4] ) + USE SIGNAL
+ + ROUTED Metal2 ( 5957840 1934800 ) ( * 2290960 )
+ NEW Metal3 ( 5957840 1934800 ) ( 5995920 * 0 )
+ NEW Metal3 ( 1106000 2080400 ) ( 1177680 * 0 )
+ NEW Metal2 ( 1106000 2080400 ) ( * 2290960 )
+ NEW Metal3 ( 1106000 2290960 ) ( 5957840 * )
+ NEW Metal2 ( 5957840 1934800 ) Via2_VH
+ NEW Metal2 ( 5957840 2290960 ) Via2_VH
+ NEW Metal2 ( 1106000 2080400 ) Via2_VH
+ NEW Metal2 ( 1106000 2290960 ) Via2_VH ;
+ - io_oeb[5] ( PIN io_oeb[5] ) ( wrapped_vga_clock io_oeb[5] ) + USE SIGNAL
+ + ROUTED Metal2 ( 1957200 1658160 ) ( * 2318960 )
+ NEW Metal2 ( 1612240 1658160 ) ( * 1692880 0 )
+ NEW Metal3 ( 1612240 1658160 ) ( 1957200 * )
NEW Metal3 ( 5995920 2318960 ) ( * 2331280 )
NEW Metal3 ( 5994800 2331280 ) ( 5995920 * )
NEW Metal3 ( 5994800 2331280 ) ( * 2332400 )
NEW Metal3 ( 5994800 2332400 ) ( 5995920 * 0 )
- NEW Metal3 ( 3049200 2318960 ) ( 5995920 * )
- NEW Metal2 ( 1439760 2895760 ) Via2_VH
- NEW Metal2 ( 3049200 2318960 ) Via2_VH
- NEW Metal2 ( 3049200 2895760 ) Via2_VH ;
- - io_oeb[6] ( PIN io_oeb[6] ) ( mprj io_oeb[6] ) + USE SIGNAL
- + ROUTED Metal2 ( 1486800 2889040 0 ) ( 1491280 * )
- NEW Metal2 ( 1491280 2889040 ) ( * 2890160 )
- NEW Metal2 ( 5720400 2722160 ) ( * 2890160 )
- NEW Metal3 ( 1491280 2890160 ) ( 5720400 * )
+ NEW Metal3 ( 1957200 2318960 ) ( 5995920 * )
+ NEW Metal2 ( 1957200 1658160 ) Via2_VH
+ NEW Metal2 ( 1957200 2318960 ) Via2_VH
+ NEW Metal2 ( 1612240 1658160 ) Via2_VH ;
+ - io_oeb[6] ( PIN io_oeb[6] ) ( wrapped_vga_clock io_oeb[6] ) + USE SIGNAL
+ + ROUTED Metal2 ( 1237040 1678320 ) ( * 1692880 0 )
+ NEW Metal3 ( 1237040 1678320 ) ( 1974000 * )
+ NEW Metal2 ( 1974000 1678320 ) ( * 2722160 )
NEW Metal3 ( 5995920 2722160 ) ( * 2731120 )
NEW Metal3 ( 5994800 2731120 ) ( 5995920 * )
NEW Metal3 ( 5994800 2731120 ) ( * 2732240 )
NEW Metal3 ( 5994800 2732240 ) ( 5995920 * 0 )
- NEW Metal3 ( 5720400 2722160 ) ( 5995920 * )
- NEW Metal2 ( 1491280 2890160 ) Via2_VH
- NEW Metal2 ( 5720400 2890160 ) Via2_VH
- NEW Metal2 ( 5720400 2722160 ) Via2_VH ;
- - io_oeb[7] ( PIN io_oeb[7] ) ( mprj io_oeb[7] ) + USE SIGNAL
- + ROUTED Metal2 ( 5961200 2914800 ) ( * 3132080 )
- NEW Metal3 ( 5961200 3132080 ) ( 5995920 * 0 )
- NEW Metal2 ( 1533840 2889040 0 ) ( * 2914800 )
- NEW Metal3 ( 1533840 2914800 ) ( 5961200 * )
- NEW Metal2 ( 5961200 3132080 ) Via2_VH
- NEW Metal2 ( 5961200 2914800 ) Via2_VH
- NEW Metal2 ( 1533840 2914800 ) Via2_VH ;
- - io_oeb[8] ( PIN io_oeb[8] ) ( mprj io_oeb[8] ) + USE SIGNAL
- + ROUTED Metal3 ( 5995920 3528560 ) ( * 3530800 )
+ NEW Metal3 ( 1974000 2722160 ) ( 5995920 * )
+ NEW Metal2 ( 1237040 1678320 ) Via2_VH
+ NEW Metal2 ( 1974000 1678320 ) Via2_VH
+ NEW Metal2 ( 1974000 2722160 ) Via2_VH ;
+ - io_oeb[7] ( PIN io_oeb[7] ) ( wrapped_vga_clock io_oeb[7] ) + USE SIGNAL
+ + ROUTED Metal2 ( 5956720 2394000 ) ( * 3132080 )
+ NEW Metal3 ( 1107120 1939280 ) ( 1177680 * 0 )
+ NEW Metal3 ( 1107120 2394000 ) ( 5956720 * )
+ NEW Metal3 ( 5956720 3132080 ) ( 5995920 * 0 )
+ NEW Metal2 ( 1107120 1939280 ) ( * 2394000 )
+ NEW Metal2 ( 5956720 2394000 ) Via2_VH
+ NEW Metal2 ( 5956720 3132080 ) Via2_VH
+ NEW Metal2 ( 1107120 1939280 ) Via2_VH
+ NEW Metal2 ( 1107120 2394000 ) Via2_VH ;
+ - io_oeb[8] ( PIN io_oeb[8] ) ( wrapped_vga_clock io_oeb[8] ) + USE SIGNAL
+ + ROUTED Metal2 ( 3738000 1661520 ) ( * 3528560 )
+ NEW Metal4 ( 1780240 1661520 ) ( * 1689520 )
+ NEW Metal3 ( 1772400 1689520 0 ) ( 1780240 * )
+ NEW Metal3 ( 1780240 1661520 ) ( 3738000 * )
+ NEW Metal3 ( 5995920 3528560 ) ( * 3530800 )
NEW Metal3 ( 5994800 3530800 ) ( 5995920 * )
NEW Metal3 ( 5994800 3530800 ) ( * 3531920 )
NEW Metal3 ( 5994800 3531920 ) ( 5995920 * 0 )
- NEW Metal3 ( 1579760 3528560 ) ( 5995920 * )
- NEW Metal2 ( 1579760 3024000 ) ( 1580880 * )
- NEW Metal2 ( 1580880 2889040 0 ) ( * 3024000 )
- NEW Metal2 ( 1579760 3024000 ) ( * 3528560 )
- NEW Metal2 ( 1579760 3528560 ) Via2_VH ;
- - io_oeb[9] ( PIN io_oeb[9] ) ( mprj io_oeb[9] ) + USE SIGNAL
- + ROUTED Metal2 ( 1620080 2889040 ) ( 1627920 * 0 )
- NEW Metal2 ( 1613360 3024000 ) ( 1620080 * )
- NEW Metal2 ( 1620080 2889040 ) ( * 3024000 )
- NEW Metal2 ( 1613360 3024000 ) ( * 3931760 )
- NEW Metal3 ( 1613360 3931760 ) ( 5995920 * 0 )
- NEW Metal2 ( 1613360 3931760 ) Via2_VH ;
- - io_out[0] ( PIN io_out[0] ) ( mprj io_out[0] ) + USE SIGNAL
- + ROUTED Metal4 ( 1220240 2864400 ) ( * 2882320 )
- NEW Metal2 ( 4981200 185360 ) ( * 2864400 )
- NEW Metal3 ( 1220240 2864400 ) ( 4981200 * )
+ NEW Metal3 ( 3738000 3528560 ) ( 5995920 * )
+ NEW Metal2 ( 3738000 1661520 ) Via2_VH
+ NEW Metal2 ( 3738000 3528560 ) Via2_VH
+ NEW Metal3 ( 1780240 1661520 ) Via3_HV
+ NEW Metal3 ( 1780240 1689520 ) Via3_HV ;
+ - io_oeb[9] ( PIN io_oeb[9] ) ( wrapped_vga_clock io_oeb[9] ) + USE SIGNAL
+ + ROUTED Metal3 ( 1772400 2040080 0 ) ( 3922800 * )
+ NEW Metal2 ( 3922800 2040080 ) ( * 3931760 )
+ NEW Metal3 ( 3922800 3931760 ) ( 5995920 * 0 )
+ NEW Metal2 ( 3922800 2040080 ) Via2_VH
+ NEW Metal2 ( 3922800 3931760 ) Via2_VH ;
+ - io_out[0] ( PIN io_out[0] ) ( wrapped_vga_clock io_out[0] ) + USE SIGNAL
+ + ROUTED Metal3 ( 1772400 1919120 0 ) ( 4393200 * )
+ NEW Metal2 ( 4393200 185360 ) ( * 1919120 )
NEW Metal3 ( 5995920 185360 ) ( * 198800 )
NEW Metal3 ( 5994800 198800 ) ( 5995920 * )
NEW Metal3 ( 5994800 198800 ) ( * 199920 )
NEW Metal3 ( 5994800 199920 ) ( 5995920 * 0 )
- NEW Metal3 ( 4981200 185360 ) ( 5995920 * )
- NEW Metal3 ( 1220240 2864400 ) Via3_HV
- NEW Metal2 ( 1220240 2882320 ) Via2_HH
- NEW Metal3 ( 1220240 2882320 ) Via3_HV
- NEW Metal2 ( 4981200 2864400 ) Via2_VH
- NEW Metal2 ( 4981200 185360 ) Via2_VH
- NEW Metal3 ( 1220240 2882320 ) RECT ( -660 -280 0 280 ) ;
- - io_out[10] ( PIN io_out[10] ) ( mprj io_out[10] ) + USE SIGNAL
- + ROUTED Metal2 ( 1682800 2889040 ) ( 1690640 * 0 )
- NEW Metal2 ( 1680560 3024000 ) ( 1682800 * )
- NEW Metal2 ( 1682800 2889040 ) ( * 3024000 )
- NEW Metal2 ( 1680560 3024000 ) ( * 4183760 )
+ NEW Metal3 ( 4393200 185360 ) ( 5995920 * )
+ NEW Metal2 ( 4393200 1919120 ) Via2_VH
+ NEW Metal2 ( 4393200 185360 ) Via2_VH ;
+ - io_out[10] ( PIN io_out[10] ) ( wrapped_vga_clock io_out[10] ) + USE SIGNAL
+ + ROUTED Metal2 ( 1633520 1679440 ) ( * 1692880 0 )
+ NEW Metal2 ( 5686800 1679440 ) ( * 4183760 )
+ NEW Metal3 ( 1633520 1679440 ) ( 5686800 * )
NEW Metal3 ( 5995920 4183760 ) ( * 4197200 )
NEW Metal3 ( 5994800 4197200 ) ( 5995920 * )
NEW Metal3 ( 5994800 4197200 ) ( * 4198320 )
NEW Metal3 ( 5994800 4198320 ) ( 5995920 * 0 )
- NEW Metal3 ( 1680560 4183760 ) ( 5995920 * )
- NEW Metal2 ( 1680560 4183760 ) Via2_VH ;
- - io_out[11] ( PIN io_out[11] ) ( mprj io_out[11] ) + USE SIGNAL
- + ROUTED Metal2 ( 1730960 2889040 ) ( 1737680 * 0 )
- NEW Metal3 ( 1730960 3973200 ) ( 2276400 * )
- NEW Metal2 ( 1730960 2889040 ) ( * 3973200 )
- NEW Metal2 ( 2276400 3973200 ) ( * 4586960 )
- NEW Metal3 ( 5995920 4586960 ) ( * 4597040 )
- NEW Metal3 ( 5994800 4597040 ) ( 5995920 * )
- NEW Metal3 ( 5994800 4597040 ) ( * 4598160 )
- NEW Metal3 ( 5994800 4598160 ) ( 5995920 * 0 )
- NEW Metal3 ( 2276400 4586960 ) ( 5995920 * )
- NEW Metal2 ( 1730960 3973200 ) Via2_VH
- NEW Metal2 ( 2276400 3973200 ) Via2_VH
- NEW Metal2 ( 2276400 4586960 ) Via2_VH ;
- - io_out[12] ( PIN io_out[12] ) ( mprj io_out[12] ) + USE SIGNAL
- + ROUTED Metal2 ( 1781360 2889040 ) ( 1784720 * 0 )
+ NEW Metal3 ( 5686800 4183760 ) ( 5995920 * )
+ NEW Metal2 ( 1633520 1679440 ) Via2_VH
+ NEW Metal2 ( 5686800 1679440 ) Via2_VH
+ NEW Metal2 ( 5686800 4183760 ) Via2_VH ;
+ - io_out[11] ( PIN io_out[11] ) ( wrapped_vga_clock io_out[11] ) + USE SIGNAL
+ + ROUTED Metal3 ( 1175440 2127440 ) ( 1177680 * 0 )
+ NEW Metal2 ( 1175440 2127440 ) ( * 2293200 )
+ NEW Metal2 ( 5955600 2293200 ) ( * 4598160 )
+ NEW Metal3 ( 1175440 2293200 ) ( 5955600 * )
+ NEW Metal3 ( 5955600 4598160 ) ( 5995920 * 0 )
+ NEW Metal2 ( 1175440 2127440 ) Via2_VH
+ NEW Metal2 ( 1175440 2293200 ) Via2_VH
+ NEW Metal2 ( 5955600 2293200 ) Via2_VH
+ NEW Metal2 ( 5955600 4598160 ) Via2_VH ;
+ - io_out[12] ( PIN io_out[12] ) ( wrapped_vga_clock io_out[12] ) + USE SIGNAL
+ + ROUTED Metal2 ( 4678800 1791440 ) ( * 4990160 )
NEW Metal3 ( 5995920 4990160 ) ( * 4996880 )
NEW Metal3 ( 5994800 4996880 ) ( 5995920 * )
NEW Metal3 ( 5994800 4996880 ) ( * 4998000 )
NEW Metal3 ( 5994800 4998000 ) ( 5995920 * 0 )
- NEW Metal3 ( 1781360 4990160 ) ( 5995920 * )
- NEW Metal2 ( 1781360 2889040 ) ( * 4990160 )
- NEW Metal2 ( 1781360 4990160 ) Via2_VH ;
- - io_out[13] ( PIN io_out[13] ) ( mprj io_out[13] ) + USE SIGNAL
- + ROUTED Metal3 ( 5995920 5393360 ) ( * 5396720 )
+ NEW Metal3 ( 4678800 4990160 ) ( 5995920 * )
+ NEW Metal3 ( 1772400 1791440 0 ) ( 4678800 * )
+ NEW Metal2 ( 4678800 4990160 ) Via2_VH
+ NEW Metal2 ( 4678800 1791440 ) Via2_VH ;
+ - io_out[13] ( PIN io_out[13] ) ( wrapped_vga_clock io_out[13] ) + USE SIGNAL
+ + ROUTED Metal3 ( 1157520 1999760 ) ( 1177680 * 0 )
+ NEW Metal3 ( 1157520 2292080 ) ( 1184400 * )
+ NEW Metal2 ( 1157520 1999760 ) ( * 2292080 )
+ NEW Metal2 ( 1184400 2292080 ) ( * 5393360 )
+ NEW Metal3 ( 5995920 5393360 ) ( * 5396720 )
NEW Metal3 ( 5994800 5396720 ) ( 5995920 * )
NEW Metal3 ( 5994800 5396720 ) ( * 5397840 )
NEW Metal3 ( 5994800 5397840 ) ( 5995920 * 0 )
- NEW Metal3 ( 1831760 5393360 ) ( 5995920 * )
- NEW Metal2 ( 1831760 2889040 0 ) ( * 5393360 )
- NEW Metal2 ( 1831760 5393360 ) Via2_VH ;
- - io_out[14] ( PIN io_out[14] ) ( mprj io_out[14] ) + USE SIGNAL
- + ROUTED Metal2 ( 1870960 2889040 ) ( 1878800 * 0 )
- NEW Metal2 ( 1865360 3024000 ) ( * 3032400 )
- NEW Metal2 ( 1865360 3024000 ) ( 1870960 * )
- NEW Metal2 ( 1870960 2889040 ) ( * 3024000 )
- NEW Metal3 ( 1865360 3032400 ) ( 5981360 * )
- NEW Metal3 ( 5981360 5797680 ) ( 5995920 * 0 )
- NEW Metal2 ( 5981360 3032400 ) ( * 5797680 )
- NEW Metal2 ( 1865360 3032400 ) Via2_VH
- NEW Metal2 ( 5981360 3032400 ) Via2_VH
- NEW Metal2 ( 5981360 5797680 ) Via2_VH ;
- - io_out[15] ( PIN io_out[15] ) ( mprj io_out[15] ) + USE SIGNAL
- + ROUTED Metal2 ( 1918000 2889040 ) ( 1925840 * 0 )
- NEW Metal2 ( 1918000 2889040 ) ( * 2982000 )
- NEW Metal2 ( 5645360 5995920 ) ( 5658800 * )
+ NEW Metal3 ( 1184400 5393360 ) ( 5995920 * )
+ NEW Metal2 ( 1184400 5393360 ) Via2_VH
+ NEW Metal2 ( 1157520 1999760 ) Via2_VH
+ NEW Metal2 ( 1157520 2292080 ) Via2_VH
+ NEW Metal2 ( 1184400 2292080 ) Via2_VH ;
+ - io_out[14] ( PIN io_out[14] ) ( wrapped_vga_clock io_out[14] ) + USE SIGNAL
+ + ROUTED Metal4 ( 1181040 1687280 ) ( * 1702960 )
+ NEW Metal3 ( 1181040 1702960 ) ( * 1709680 0 )
+ NEW Metal3 ( 1181040 1687280 ) ( 1990800 * )
+ NEW Metal2 ( 1990800 1687280 ) ( * 5796560 )
+ NEW Metal3 ( 1990800 5796560 ) ( 5728800 * )
+ NEW Metal3 ( 5728800 5796560 ) ( * 5797680 )
+ NEW Metal3 ( 5728800 5797680 ) ( 5995920 * 0 )
+ NEW Metal3 ( 1181040 1687280 ) Via3_HV
+ NEW Metal3 ( 1181040 1702960 ) Via3_HV
+ NEW Metal2 ( 1990800 1687280 ) Via2_VH
+ NEW Metal2 ( 1990800 5796560 ) Via2_VH ;
+ - io_out[15] ( PIN io_out[15] ) ( wrapped_vga_clock io_out[15] ) + USE SIGNAL
+ + ROUTED Metal2 ( 5645360 5995920 ) ( 5658800 * )
NEW Metal2 ( 5658800 5994800 ) ( * 5995920 )
NEW Metal2 ( 5658800 5994800 ) ( 5659920 * )
NEW Metal2 ( 5659920 5994800 ) ( * 5995920 0 )
- NEW Metal2 ( 5645360 2982000 ) ( * 5995920 )
- NEW Metal3 ( 1918000 2982000 ) ( 5645360 * )
- NEW Metal2 ( 1918000 2982000 ) Via2_VH
- NEW Metal2 ( 5645360 2982000 ) Via2_VH ;
- - io_out[16] ( PIN io_out[16] ) ( mprj io_out[16] ) + USE SIGNAL
- + ROUTED Metal2 ( 4990160 5995920 ) ( 4993520 * )
+ NEW Metal2 ( 5645360 2127440 ) ( * 5995920 )
+ NEW Metal3 ( 1772400 2127440 0 ) ( 5645360 * )
+ NEW Metal2 ( 5645360 2127440 ) Via2_VH ;
+ - io_out[16] ( PIN io_out[16] ) ( wrapped_vga_clock io_out[16] ) + USE SIGNAL
+ + ROUTED Metal2 ( 1694000 1660400 ) ( * 1692880 0 )
+ NEW Metal2 ( 1905680 1660400 ) ( * 1738800 )
+ NEW Metal2 ( 4990160 5995920 ) ( 4993520 * )
NEW Metal2 ( 4993520 5994800 ) ( * 5995920 )
NEW Metal2 ( 4993520 5994800 ) ( 4994640 * )
NEW Metal2 ( 4994640 5994800 ) ( * 5995920 0 )
- NEW Metal2 ( 4990160 3284400 ) ( * 5995920 )
- NEW Metal2 ( 1966160 2889040 ) ( 1972880 * 0 )
- NEW Metal3 ( 1966160 3284400 ) ( 4990160 * )
- NEW Metal2 ( 1966160 2889040 ) ( * 3284400 )
- NEW Metal2 ( 4990160 3284400 ) Via2_VH
- NEW Metal2 ( 1966160 3284400 ) Via2_VH ;
- - io_out[17] ( PIN io_out[17] ) ( mprj io_out[17] ) + USE SIGNAL
- + ROUTED Metal2 ( 2016560 2889040 ) ( 2019920 * 0 )
- NEW Metal2 ( 2016560 2889040 ) ( * 2983120 )
- NEW Metal3 ( 2016560 2983120 ) ( 4318160 * )
- NEW Metal2 ( 4318160 5995920 ) ( 4328240 * )
- NEW Metal2 ( 4328240 5994800 ) ( * 5995920 )
- NEW Metal2 ( 4328240 5994800 ) ( 4329360 * )
- NEW Metal2 ( 4329360 5994800 ) ( * 5995920 0 )
- NEW Metal2 ( 4318160 2983120 ) ( * 5995920 )
- NEW Metal2 ( 2016560 2983120 ) Via2_VH
- NEW Metal2 ( 4318160 2983120 ) Via2_VH ;
- - io_out[18] ( PIN io_out[18] ) ( mprj io_out[18] ) + USE SIGNAL
- + ROUTED Metal2 ( 2066960 2889040 0 ) ( * 2921520 )
- NEW Metal3 ( 2066960 2921520 ) ( 3662960 * )
- NEW Metal2 ( 3662960 2921520 ) ( * 5728800 )
+ NEW Metal2 ( 4990160 1738800 ) ( * 5995920 )
+ NEW Metal3 ( 1694000 1660400 ) ( 1905680 * )
+ NEW Metal3 ( 1905680 1738800 ) ( 4990160 * )
+ NEW Metal2 ( 1694000 1660400 ) Via2_VH
+ NEW Metal2 ( 1905680 1660400 ) Via2_VH
+ NEW Metal2 ( 1905680 1738800 ) Via2_VH
+ NEW Metal2 ( 4990160 1738800 ) Via2_VH ;
+ - io_out[17] ( PIN io_out[17] ) ( wrapped_vga_clock io_out[17] ) + USE SIGNAL
+ + ROUTED Metal2 ( 3822000 2167760 ) ( * 5956720 )
+ NEW Metal3 ( 1772400 2167760 0 ) ( 3822000 * )
+ NEW Metal3 ( 3822000 5956720 ) ( 4329360 * )
+ NEW Metal2 ( 4329360 5956720 ) ( * 5995920 0 )
+ NEW Metal2 ( 3822000 2167760 ) Via2_VH
+ NEW Metal2 ( 3822000 5956720 ) Via2_VH
+ NEW Metal2 ( 4329360 5956720 ) Via2_VH ;
+ - io_out[18] ( PIN io_out[18] ) ( wrapped_vga_clock io_out[18] ) + USE SIGNAL
+ + ROUTED Metal2 ( 1485680 1658160 ) ( * 1692880 0 )
+ NEW Metal2 ( 1562960 1658160 ) ( * 1671600 )
+ NEW Metal3 ( 1485680 1658160 ) ( 1562960 * )
+ NEW Metal3 ( 1562960 1671600 ) ( 3662960 * )
+ NEW Metal2 ( 3662960 1671600 ) ( * 5728800 )
NEW Metal2 ( 3662960 5728800 ) ( 3664080 * )
NEW Metal2 ( 3664080 5728800 ) ( * 5995920 0 )
- NEW Metal2 ( 2066960 2921520 ) Via2_VH
- NEW Metal2 ( 3662960 2921520 ) Via2_VH ;
- - io_out[19] ( PIN io_out[19] ) ( mprj io_out[19] ) + USE SIGNAL
- + ROUTED Metal2 ( 2106160 2889040 ) ( 2114000 * 0 )
- NEW Metal2 ( 2100560 3024000 ) ( * 3082800 )
- NEW Metal2 ( 2100560 3024000 ) ( 2106160 * )
- NEW Metal2 ( 2106160 2889040 ) ( * 3024000 )
- NEW Metal3 ( 2100560 3082800 ) ( 2461200 * )
- NEW Metal3 ( 2461200 5956720 ) ( 2998800 * )
- NEW Metal2 ( 2461200 3082800 ) ( * 5956720 )
+ NEW Metal2 ( 1485680 1658160 ) Via2_VH
+ NEW Metal2 ( 1562960 1658160 ) Via2_VH
+ NEW Metal2 ( 1562960 1671600 ) Via2_VH
+ NEW Metal2 ( 3662960 1671600 ) Via2_VH ;
+ - io_out[19] ( PIN io_out[19] ) ( wrapped_vga_clock io_out[19] ) + USE SIGNAL
+ + ROUTED Metal3 ( 1156400 1811600 ) ( 1177680 * 0 )
+ NEW Metal2 ( 1156400 1811600 ) ( * 2311120 )
+ NEW Metal3 ( 1285200 5956720 ) ( 2998800 * )
+ NEW Metal3 ( 1156400 2311120 ) ( 1285200 * )
+ NEW Metal2 ( 1285200 2311120 ) ( * 5956720 )
NEW Metal2 ( 2998800 5956720 ) ( * 5995920 0 )
- NEW Metal2 ( 2100560 3082800 ) Via2_VH
- NEW Metal2 ( 2461200 3082800 ) Via2_VH
- NEW Metal2 ( 2461200 5956720 ) Via2_VH
- NEW Metal2 ( 2998800 5956720 ) Via2_VH ;
- - io_out[1] ( PIN io_out[1] ) ( mprj io_out[1] ) + USE SIGNAL
- + ROUTED Metal4 ( 1267280 2865520 ) ( * 2882320 )
- NEW Metal3 ( 1267280 2865520 ) ( 3250800 * )
- NEW Metal2 ( 3250800 588560 ) ( * 2865520 )
+ NEW Metal2 ( 1156400 1811600 ) Via2_VH
+ NEW Metal2 ( 1156400 2311120 ) Via2_VH
+ NEW Metal2 ( 1285200 5956720 ) Via2_VH
+ NEW Metal2 ( 2998800 5956720 ) Via2_VH
+ NEW Metal2 ( 1285200 2311120 ) Via2_VH ;
+ - io_out[1] ( PIN io_out[1] ) ( wrapped_vga_clock io_out[1] ) + USE SIGNAL
+ + ROUTED Metal3 ( 1157520 1918000 ) ( 1177680 * 0 )
+ NEW Metal2 ( 1157520 588560 ) ( * 1918000 )
NEW Metal3 ( 5995920 588560 ) ( * 598640 )
NEW Metal3 ( 5994800 598640 ) ( 5995920 * )
NEW Metal3 ( 5994800 598640 ) ( * 599760 )
NEW Metal3 ( 5994800 599760 ) ( 5995920 * 0 )
- NEW Metal3 ( 3250800 588560 ) ( 5995920 * )
- NEW Metal3 ( 1267280 2865520 ) Via3_HV
- NEW Metal2 ( 1267280 2882320 ) Via2_HH
- NEW Metal3 ( 1267280 2882320 ) Via3_HV
- NEW Metal2 ( 3250800 2865520 ) Via2_VH
- NEW Metal2 ( 3250800 588560 ) Via2_VH
- NEW Metal3 ( 1267280 2882320 ) RECT ( -660 -280 0 280 ) ;
- - io_out[20] ( PIN io_out[20] ) ( mprj io_out[20] ) + USE SIGNAL
- + ROUTED Metal2 ( 2153200 2889040 ) ( 2161040 * 0 )
- NEW Metal3 ( 2150960 3079440 ) ( 2175600 * )
- NEW Metal2 ( 2150960 3024000 ) ( * 3079440 )
- NEW Metal2 ( 2150960 3024000 ) ( 2153200 * )
- NEW Metal2 ( 2153200 2889040 ) ( * 3024000 )
- NEW Metal2 ( 2175600 3079440 ) ( * 5955600 )
- NEW Metal2 ( 2333520 5955600 ) ( * 5995920 0 )
- NEW Metal3 ( 2175600 5955600 ) ( 2333520 * )
- NEW Metal2 ( 2150960 3079440 ) Via2_VH
- NEW Metal2 ( 2175600 3079440 ) Via2_VH
- NEW Metal2 ( 2175600 5955600 ) Via2_VH
- NEW Metal2 ( 2333520 5955600 ) Via2_VH ;
- - io_out[21] ( PIN io_out[21] ) ( mprj io_out[21] ) + USE SIGNAL
- + ROUTED Metal2 ( 1663760 5995920 ) ( 1667120 * )
- NEW Metal2 ( 1667120 5994800 ) ( * 5995920 )
- NEW Metal2 ( 1667120 5994800 ) ( 1668240 * )
- NEW Metal2 ( 1668240 5994800 ) ( * 5995920 0 )
- NEW Metal2 ( 1663760 2913680 ) ( * 5995920 )
- NEW Metal3 ( 1663760 2913680 ) ( 2208080 * )
- NEW Metal2 ( 2208080 2889040 0 ) ( * 2913680 )
- NEW Metal2 ( 1663760 2913680 ) Via2_VH
- NEW Metal2 ( 2208080 2913680 ) Via2_VH ;
- - io_out[22] ( PIN io_out[22] ) ( mprj io_out[22] ) + USE SIGNAL
+ NEW Metal3 ( 1157520 588560 ) ( 5995920 * )
+ NEW Metal2 ( 1157520 1918000 ) Via2_VH
+ NEW Metal2 ( 1157520 588560 ) Via2_VH ;
+ - io_out[20] ( PIN io_out[20] ) ( wrapped_vga_clock io_out[20] ) + USE SIGNAL
+ + ROUTED Metal2 ( 1175440 1681680 ) ( * 1692880 0 )
+ NEW Metal2 ( 2318960 5995920 ) ( 2332400 * )
+ NEW Metal2 ( 2332400 5994800 ) ( * 5995920 )
+ NEW Metal2 ( 2332400 5994800 ) ( 2333520 * )
+ NEW Metal2 ( 2333520 5994800 ) ( * 5995920 0 )
+ NEW Metal2 ( 2318960 1705200 ) ( * 5995920 )
+ NEW Metal2 ( 1831760 1681680 ) ( * 1705200 )
+ NEW Metal3 ( 1175440 1681680 ) ( 1831760 * )
+ NEW Metal3 ( 1831760 1705200 ) ( 2318960 * )
+ NEW Metal2 ( 1175440 1681680 ) Via2_VH
+ NEW Metal2 ( 2318960 1705200 ) Via2_VH
+ NEW Metal2 ( 1831760 1681680 ) Via2_VH
+ NEW Metal2 ( 1831760 1705200 ) Via2_VH ;
+ - io_out[21] ( PIN io_out[21] ) ( wrapped_vga_clock io_out[21] ) + USE SIGNAL
+ + ROUTED Metal2 ( 1670480 5955600 ) ( * 5995920 0 )
+ NEW Metal2 ( 1566320 1655920 ) ( * 1692880 0 )
+ NEW Metal3 ( 1566320 1655920 ) ( 1801520 * )
+ NEW Metal3 ( 1670480 5955600 ) ( 1801520 * )
+ NEW Metal2 ( 1801520 1655920 ) ( * 5955600 )
+ NEW Metal2 ( 1670480 5955600 ) Via2_VH
+ NEW Metal2 ( 1566320 1655920 ) Via2_VH
+ NEW Metal2 ( 1801520 1655920 ) Via2_VH
+ NEW Metal2 ( 1801520 5955600 ) Via2_VH ;
+ - io_out[22] ( PIN io_out[22] ) ( wrapped_vga_clock io_out[22] ) + USE SIGNAL
+ ROUTED Metal3 ( 1005200 5947760 ) ( 1016400 * )
- NEW Metal2 ( 1016400 2984240 ) ( * 5947760 )
+ NEW Metal2 ( 1016400 2327920 ) ( * 5947760 )
NEW Metal2 ( 1005200 5947760 ) ( * 5995920 0 )
- NEW Metal2 ( 2251760 2889040 ) ( 2255120 * 0 )
- NEW Metal3 ( 1016400 2984240 ) ( 2251760 * )
- NEW Metal2 ( 2251760 2889040 ) ( * 2984240 )
+ NEW Metal1 ( 1215760 2287600 ) ( * 2290960 )
+ NEW Metal2 ( 1215760 2290960 ) ( * 2327920 )
+ NEW Metal3 ( 1016400 2327920 ) ( 1215760 * )
+ NEW Metal2 ( 1016400 2327920 ) Via2_VH
NEW Metal2 ( 1005200 5947760 ) Via2_VH
NEW Metal2 ( 1016400 5947760 ) Via2_VH
- NEW Metal2 ( 1016400 2984240 ) Via2_VH
- NEW Metal2 ( 2251760 2984240 ) Via2_VH ;
- - io_out[23] ( PIN io_out[23] ) ( mprj io_out[23] ) + USE SIGNAL
- + ROUTED Metal2 ( 2302160 2887920 0 ) ( 2304400 * )
- NEW Metal2 ( 336560 2965200 ) ( * 5728800 )
- NEW Metal2 ( 336560 5728800 ) ( 337680 * )
- NEW Metal2 ( 337680 5728800 ) ( * 5995920 0 )
- NEW Metal3 ( 336560 2965200 ) ( 2304400 * )
- NEW Metal2 ( 2304400 2887920 ) ( * 2965200 )
- NEW Metal2 ( 336560 2965200 ) Via2_VH
- NEW Metal2 ( 2304400 2965200 ) Via2_VH ;
- - io_out[24] ( PIN io_out[24] ) ( mprj io_out[24] ) + USE SIGNAL
- + ROUTED Metal2 ( 2341360 2889040 ) ( 2349200 * 0 )
- NEW Metal3 ( 3920 5762960 ) ( * 5770800 )
+ NEW Metal2 ( 1215760 2327920 ) Via2_VH
+ NEW Metal1 ( 1215760 2287600 ) Via1_HV
+ NEW Metal1 ( 1215760 2290960 ) Via1_HV ;
+ - io_out[23] ( PIN io_out[23] ) ( wrapped_vga_clock io_out[23] ) + USE SIGNAL
+ + ROUTED Metal2 ( 714000 2326800 ) ( * 5955600 )
+ NEW Metal1 ( 1403920 2287600 ) ( * 2290960 )
+ NEW Metal2 ( 1403920 2290960 ) ( * 2326800 )
+ NEW Metal3 ( 339920 5955600 ) ( 714000 * )
+ NEW Metal3 ( 714000 2326800 ) ( 1403920 * )
+ NEW Metal2 ( 339920 5955600 ) ( * 5995920 0 )
+ NEW Metal2 ( 714000 2326800 ) Via2_VH
+ NEW Metal2 ( 714000 5955600 ) Via2_VH
+ NEW Metal2 ( 1403920 2326800 ) Via2_VH
+ NEW Metal1 ( 1403920 2287600 ) Via1_HV
+ NEW Metal1 ( 1403920 2290960 ) Via1_HV
+ NEW Metal2 ( 339920 5955600 ) Via2_VH ;
+ - io_out[24] ( PIN io_out[24] ) ( wrapped_vga_clock io_out[24] ) + USE SIGNAL
+ + ROUTED Metal3 ( 3920 5762960 ) ( * 5770800 )
NEW Metal3 ( 3920 5770800 ) ( 5040 * )
NEW Metal3 ( 5040 5770800 ) ( * 5771920 )
NEW Metal3 ( 3920 5771920 0 ) ( 5040 * )
- NEW Metal2 ( 2341360 2889040 ) ( * 2998800 )
- NEW Metal3 ( 3920 5762960 ) ( 1083600 * )
- NEW Metal2 ( 1083600 2998800 ) ( * 5762960 )
- NEW Metal3 ( 1083600 2998800 ) ( 2341360 * )
- NEW Metal2 ( 2341360 2998800 ) Via2_VH
- NEW Metal2 ( 1083600 2998800 ) Via2_VH
- NEW Metal2 ( 1083600 5762960 ) Via2_VH ;
- - io_out[25] ( PIN io_out[25] ) ( mprj io_out[25] ) + USE SIGNAL
- + ROUTED Metal3 ( 3920 5345200 0 ) ( 42000 * )
- NEW Metal2 ( 42000 2919280 ) ( * 5345200 )
- NEW Metal2 ( 2396240 2889040 0 ) ( * 2919280 )
- NEW Metal3 ( 42000 2919280 ) ( 2396240 * )
- NEW Metal2 ( 42000 2919280 ) Via2_VH
- NEW Metal2 ( 42000 5345200 ) Via2_VH
- NEW Metal2 ( 2396240 2919280 ) Via2_VH ;
- - io_out[26] ( PIN io_out[26] ) ( mprj io_out[26] ) + USE SIGNAL
+ NEW Metal3 ( 613200 2344720 ) ( 1592080 * )
+ NEW Metal3 ( 3920 5762960 ) ( 613200 * )
+ NEW Metal2 ( 613200 2344720 ) ( * 5762960 )
+ NEW Metal1 ( 1592080 2287600 ) ( * 2290960 )
+ NEW Metal2 ( 1592080 2290960 ) ( * 2344720 )
+ NEW Metal2 ( 613200 2344720 ) Via2_VH
+ NEW Metal2 ( 1592080 2344720 ) Via2_VH
+ NEW Metal2 ( 613200 5762960 ) Via2_VH
+ NEW Metal1 ( 1592080 2287600 ) Via1_HV
+ NEW Metal1 ( 1592080 2290960 ) Via1_HV ;
+ - io_out[25] ( PIN io_out[25] ) ( wrapped_vga_clock io_out[25] ) + USE SIGNAL
+ + ROUTED Metal3 ( 3920 5345200 0 ) ( 109200 * )
+ NEW Metal2 ( 109200 1730960 ) ( * 5345200 )
+ NEW Metal3 ( 109200 1730960 ) ( 1177680 * 0 )
+ NEW Metal2 ( 109200 1730960 ) Via2_VH
+ NEW Metal2 ( 109200 5345200 ) Via2_VH ;
+ - io_out[26] ( PIN io_out[26] ) ( wrapped_vga_clock io_out[26] ) + USE SIGNAL
+ ROUTED Metal3 ( 3920 4906160 ) ( * 4917360 )
NEW Metal3 ( 3920 4917360 ) ( 5040 * )
NEW Metal3 ( 5040 4917360 ) ( * 4918480 )
NEW Metal3 ( 3920 4918480 0 ) ( 5040 * )
- NEW Metal2 ( 1873200 3051440 ) ( * 4906160 )
- NEW Metal3 ( 3920 4906160 ) ( 1873200 * )
- NEW Metal2 ( 2436560 2889040 ) ( 2443280 * 0 )
- NEW Metal3 ( 1873200 3051440 ) ( 2436560 * )
- NEW Metal2 ( 2436560 2889040 ) ( * 3051440 )
- NEW Metal2 ( 1873200 3051440 ) Via2_VH
- NEW Metal2 ( 1873200 4906160 ) Via2_VH
- NEW Metal2 ( 2436560 3051440 ) Via2_VH ;
- - io_out[27] ( PIN io_out[27] ) ( mprj io_out[27] ) + USE SIGNAL
+ NEW Metal2 ( 697200 1672720 ) ( * 4906160 )
+ NEW Metal3 ( 3920 4906160 ) ( 697200 * )
+ NEW Metal2 ( 1276240 1672720 ) ( * 1692880 0 )
+ NEW Metal3 ( 697200 1672720 ) ( 1276240 * )
+ NEW Metal2 ( 697200 1672720 ) Via2_VH
+ NEW Metal2 ( 697200 4906160 ) Via2_VH
+ NEW Metal2 ( 1276240 1672720 ) Via2_VH ;
+ - io_out[27] ( PIN io_out[27] ) ( wrapped_vga_clock io_out[27] ) + USE SIGNAL
+ ROUTED Metal3 ( 3920 4486160 ) ( * 4490640 )
NEW Metal3 ( 3920 4490640 ) ( 5040 * )
NEW Metal3 ( 5040 4490640 ) ( * 4491760 )
NEW Metal3 ( 3920 4491760 0 ) ( 5040 * )
- NEW Metal2 ( 2486960 2889040 ) ( 2490320 * 0 )
- NEW Metal3 ( 2478000 3057040 ) ( 2486960 * )
- NEW Metal3 ( 3920 4486160 ) ( 2478000 * )
- NEW Metal2 ( 2486960 2889040 ) ( * 3057040 )
- NEW Metal2 ( 2478000 3057040 ) ( * 4486160 )
- NEW Metal2 ( 2478000 3057040 ) Via2_VH
- NEW Metal2 ( 2486960 3057040 ) Via2_VH
- NEW Metal2 ( 2478000 4486160 ) Via2_VH ;
- - io_out[28] ( PIN io_out[28] ) ( mprj io_out[28] ) + USE SIGNAL
- + ROUTED Metal2 ( 2537360 2887920 0 ) ( 2539600 * )
- NEW Metal3 ( 3920 4066160 0 ) ( 2494800 * )
- NEW Metal3 ( 2494800 2956240 ) ( 2539600 * )
- NEW Metal2 ( 2539600 2887920 ) ( * 2956240 )
- NEW Metal2 ( 2494800 2956240 ) ( * 4066160 )
- NEW Metal2 ( 2494800 4066160 ) Via2_VH
- NEW Metal2 ( 2494800 2956240 ) Via2_VH
- NEW Metal2 ( 2539600 2956240 ) Via2_VH ;
- - io_out[29] ( PIN io_out[29] ) ( mprj io_out[29] ) + USE SIGNAL
- + ROUTED Metal3 ( 3920 3638320 0 ) ( 46480 * )
- NEW Metal2 ( 46480 2917040 ) ( * 3638320 )
- NEW Metal2 ( 2584400 2889040 0 ) ( * 2917040 )
- NEW Metal3 ( 46480 2917040 ) ( 2584400 * )
- NEW Metal2 ( 46480 2917040 ) Via2_VH
- NEW Metal2 ( 46480 3638320 ) Via2_VH
- NEW Metal2 ( 2584400 2917040 ) Via2_VH ;
- - io_out[2] ( PIN io_out[2] ) ( mprj io_out[2] ) + USE SIGNAL
- + ROUTED Metal2 ( 3368400 991760 ) ( * 2893520 )
- NEW Metal2 ( 1314320 2889040 0 ) ( * 2893520 )
- NEW Metal3 ( 1314320 2893520 ) ( 3368400 * )
- NEW Metal3 ( 5995920 991760 ) ( * 998480 )
- NEW Metal3 ( 5994800 998480 ) ( 5995920 * )
- NEW Metal3 ( 5994800 998480 ) ( * 999600 )
- NEW Metal3 ( 5994800 999600 ) ( 5995920 * 0 )
- NEW Metal3 ( 3368400 991760 ) ( 5995920 * )
- NEW Metal2 ( 3368400 991760 ) Via2_VH
- NEW Metal2 ( 3368400 2893520 ) Via2_VH
- NEW Metal2 ( 1314320 2893520 ) Via2_VH ;
- - io_out[30] ( PIN io_out[30] ) ( mprj io_out[30] ) + USE SIGNAL
- + ROUTED Metal2 ( 2623600 2889040 ) ( 2631440 * 0 )
- NEW Metal2 ( 2621360 3024000 ) ( 2623600 * )
- NEW Metal2 ( 2623600 2889040 ) ( * 3024000 )
- NEW Metal2 ( 2621360 3024000 ) ( * 3209360 )
- NEW Metal3 ( 3920 3211600 0 ) ( 84000 * )
- NEW Metal3 ( 84000 3209360 ) ( * 3211600 )
- NEW Metal3 ( 84000 3209360 ) ( 2621360 * )
- NEW Metal2 ( 2621360 3209360 ) Via2_VH ;
- - io_out[31] ( PIN io_out[31] ) ( mprj io_out[31] ) + USE SIGNAL
- + ROUTED Metal3 ( 3920 2772560 ) ( * 2783760 )
- NEW Metal3 ( 3920 2783760 ) ( 5040 * )
- NEW Metal3 ( 5040 2783760 ) ( * 2784880 )
- NEW Metal3 ( 3920 2784880 0 ) ( 5040 * )
- NEW Metal2 ( 1183280 2772560 ) ( * 3058160 )
- NEW Metal2 ( 2671760 2889040 ) ( 2678480 * 0 )
- NEW Metal3 ( 1183280 3058160 ) ( 2671760 * )
- NEW Metal3 ( 3920 2772560 ) ( 1183280 * )
- NEW Metal2 ( 2671760 2889040 ) ( * 3058160 )
- NEW Metal2 ( 1183280 3058160 ) Via2_VH
- NEW Metal2 ( 1183280 2772560 ) Via2_VH
- NEW Metal2 ( 2671760 3058160 ) Via2_VH ;
- - io_out[32] ( PIN io_out[32] ) ( mprj io_out[32] ) + USE SIGNAL
+ NEW Metal2 ( 1195600 1676080 ) ( * 1692880 0 )
+ NEW Metal3 ( 3920 4486160 ) ( 663600 * )
+ NEW Metal3 ( 663600 1676080 ) ( 1195600 * )
+ NEW Metal2 ( 663600 1676080 ) ( * 4486160 )
+ NEW Metal2 ( 1195600 1676080 ) Via2_VH
+ NEW Metal2 ( 663600 1676080 ) Via2_VH
+ NEW Metal2 ( 663600 4486160 ) Via2_VH ;
+ - io_out[28] ( PIN io_out[28] ) ( wrapped_vga_clock io_out[28] ) + USE SIGNAL
+ + ROUTED Metal3 ( 1621200 2334640 ) ( 1672720 * )
+ NEW Metal1 ( 1672720 2287600 ) ( * 2290960 )
+ NEW Metal2 ( 1672720 2290960 ) ( * 2334640 )
+ NEW Metal2 ( 1621200 2334640 ) ( * 4066160 )
+ NEW Metal3 ( 3920 4066160 0 ) ( 1621200 * )
+ NEW Metal2 ( 1621200 2334640 ) Via2_VH
+ NEW Metal2 ( 1672720 2334640 ) Via2_VH
+ NEW Metal2 ( 1621200 4066160 ) Via2_VH
+ NEW Metal1 ( 1672720 2287600 ) Via1_HV
+ NEW Metal1 ( 1672720 2290960 ) Via1_HV ;
+ - io_out[29] ( PIN io_out[29] ) ( wrapped_vga_clock io_out[29] ) + USE SIGNAL
+ + ROUTED Metal3 ( 3920 3629360 ) ( * 3637200 )
+ NEW Metal3 ( 3920 3637200 ) ( 5040 * )
+ NEW Metal3 ( 5040 3637200 ) ( * 3638320 )
+ NEW Metal3 ( 3920 3638320 0 ) ( 5040 * )
+ NEW Metal2 ( 1436400 2327920 ) ( * 3629360 )
+ NEW Metal3 ( 1436400 2327920 ) ( 1545040 * )
+ NEW Metal3 ( 3920 3629360 ) ( 1436400 * )
+ NEW Metal1 ( 1545040 2287600 ) ( * 2290960 )
+ NEW Metal2 ( 1545040 2290960 ) ( * 2327920 )
+ NEW Metal2 ( 1436400 2327920 ) Via2_VH
+ NEW Metal2 ( 1436400 3629360 ) Via2_VH
+ NEW Metal2 ( 1545040 2327920 ) Via2_VH
+ NEW Metal1 ( 1545040 2287600 ) Via1_HV
+ NEW Metal1 ( 1545040 2290960 ) Via1_HV ;
+ - io_out[2] ( PIN io_out[2] ) ( wrapped_vga_clock io_out[2] ) + USE SIGNAL
+ + ROUTED Metal2 ( 1462160 1692880 ) ( 1464400 * 0 )
+ NEW Metal2 ( 5947760 1001840 ) ( * 1016400 )
+ NEW Metal2 ( 1462160 1016400 ) ( * 1692880 )
+ NEW Metal3 ( 1462160 1016400 ) ( 5947760 * )
+ NEW Metal3 ( 5947760 1001840 ) ( 5995920 * 0 )
+ NEW Metal2 ( 1462160 1016400 ) Via2_VH
+ NEW Metal2 ( 5947760 1016400 ) Via2_VH
+ NEW Metal2 ( 5947760 1001840 ) Via2_VH ;
+ - io_out[30] ( PIN io_out[30] ) ( wrapped_vga_clock io_out[30] ) + USE SIGNAL
+ + ROUTED Metal3 ( 126000 2377200 ) ( 1730960 * )
+ NEW Metal3 ( 3920 3211600 0 ) ( 126000 * )
+ NEW Metal2 ( 126000 2377200 ) ( * 3211600 )
+ NEW Metal1 ( 1733200 2287600 ) ( * 2290960 )
+ NEW Metal1 ( 1730960 2290960 ) ( 1733200 * )
+ NEW Metal2 ( 1730960 2290960 ) ( * 2377200 )
+ NEW Metal2 ( 126000 2377200 ) Via2_VH
+ NEW Metal2 ( 1730960 2377200 ) Via2_VH
+ NEW Metal2 ( 126000 3211600 ) Via2_VH
+ NEW Metal1 ( 1733200 2287600 ) Via1_HV
+ NEW Metal1 ( 1730960 2290960 ) Via1_HV ;
+ - io_out[31] ( PIN io_out[31] ) ( wrapped_vga_clock io_out[31] ) + USE SIGNAL
+ + ROUTED Metal3 ( 3920 2784880 0 ) ( 42000 * )
+ NEW Metal2 ( 42000 2295440 ) ( * 2784880 )
+ NEW Metal3 ( 1772400 1771280 0 ) ( 1783600 * )
+ NEW Metal3 ( 42000 2295440 ) ( 1783600 * )
+ NEW Metal2 ( 1783600 1771280 ) ( * 2295440 )
+ NEW Metal2 ( 42000 2295440 ) Via2_VH
+ NEW Metal2 ( 42000 2784880 ) Via2_VH
+ NEW Metal2 ( 1783600 1771280 ) Via2_VH
+ NEW Metal2 ( 1783600 2295440 ) Via2_VH ;
+ - io_out[32] ( PIN io_out[32] ) ( wrapped_vga_clock io_out[32] ) + USE SIGNAL
+ ROUTED Metal3 ( 3920 2352560 ) ( * 2357040 )
NEW Metal3 ( 3920 2357040 ) ( 5040 * )
NEW Metal3 ( 5040 2357040 ) ( * 2358160 )
NEW Metal3 ( 3920 2358160 0 ) ( 5040 * )
- NEW Metal2 ( 1185520 2352560 ) ( * 3024560 )
- NEW Metal3 ( 3920 2352560 ) ( 1185520 * )
- NEW Metal2 ( 2722160 2889040 ) ( 2725520 * 0 )
- NEW Metal3 ( 1185520 3024560 ) ( 2722160 * )
- NEW Metal2 ( 2722160 2889040 ) ( * 3024560 )
- NEW Metal2 ( 1185520 2352560 ) Via2_VH
- NEW Metal2 ( 1185520 3024560 ) Via2_VH
- NEW Metal2 ( 2722160 3024560 ) Via2_VH ;
- - io_out[33] ( PIN io_out[33] ) ( mprj io_out[33] ) + USE SIGNAL
- + ROUTED Metal2 ( 1186640 1932560 ) ( * 2993200 )
- NEW Metal3 ( 3920 1932560 0 ) ( 1186640 * )
- NEW Metal2 ( 2772560 2887920 0 ) ( 2774800 * )
- NEW Metal3 ( 1186640 2993200 ) ( 2774800 * )
- NEW Metal2 ( 2774800 2887920 ) ( * 2993200 )
- NEW Metal2 ( 1186640 1932560 ) Via2_VH
- NEW Metal2 ( 1186640 2993200 ) Via2_VH
- NEW Metal2 ( 2774800 2993200 ) Via2_VH ;
- - io_out[34] ( PIN io_out[34] ) ( mprj io_out[34] ) + USE SIGNAL
- + ROUTED Metal4 ( 2819600 2875600 ) ( * 2882320 )
- NEW Metal3 ( 3920 1495760 ) ( * 1503600 )
+ NEW Metal3 ( 3920 2352560 ) ( 126000 * )
+ NEW Metal2 ( 126000 2268560 ) ( * 2352560 )
+ NEW Metal3 ( 126000 2268560 ) ( 1177680 * 0 )
+ NEW Metal2 ( 126000 2352560 ) Via2_VH
+ NEW Metal2 ( 126000 2268560 ) Via2_VH ;
+ - io_out[33] ( PIN io_out[33] ) ( wrapped_vga_clock io_out[33] ) + USE SIGNAL
+ + ROUTED Metal2 ( 45360 1898960 ) ( * 1932560 )
+ NEW Metal3 ( 3920 1932560 0 ) ( 45360 * )
+ NEW Metal3 ( 45360 1898960 ) ( 1177680 * 0 )
+ NEW Metal2 ( 45360 1898960 ) Via2_VH
+ NEW Metal2 ( 45360 1932560 ) Via2_VH ;
+ - io_out[34] ( PIN io_out[34] ) ( wrapped_vga_clock io_out[34] ) + USE SIGNAL
+ + ROUTED Metal3 ( 3920 1495760 ) ( * 1503600 )
NEW Metal3 ( 3920 1503600 ) ( 5040 * )
NEW Metal3 ( 5040 1503600 ) ( * 1504720 )
NEW Metal3 ( 3920 1504720 0 ) ( 5040 * )
- NEW Metal2 ( 917840 1495760 ) ( * 2875600 )
- NEW Metal3 ( 917840 2875600 ) ( 2819600 * )
- NEW Metal3 ( 3920 1495760 ) ( 917840 * )
- NEW Metal2 ( 917840 2875600 ) Via2_VH
- NEW Metal3 ( 2819600 2875600 ) Via3_HV
- NEW Metal2 ( 2819600 2882320 ) Via2_HH
- NEW Metal3 ( 2819600 2882320 ) Via3_HV
- NEW Metal2 ( 917840 1495760 ) Via2_VH
- NEW Metal3 ( 2819600 2882320 ) RECT ( -660 -280 0 280 ) ;
- - io_out[35] ( PIN io_out[35] ) ( mprj io_out[35] ) + USE SIGNAL
- + ROUTED Metal4 ( 2866640 2874480 ) ( * 2882320 )
- NEW Metal3 ( 898800 2874480 ) ( 2866640 * )
- NEW Metal3 ( 3920 1078000 0 ) ( 84000 * )
- NEW Metal3 ( 84000 1075760 ) ( * 1078000 )
- NEW Metal3 ( 84000 1075760 ) ( 898800 * )
- NEW Metal2 ( 898800 1075760 ) ( * 2874480 )
- NEW Metal3 ( 2866640 2874480 ) Via3_HV
- NEW Metal2 ( 2866640 2882320 ) Via2_HH
- NEW Metal3 ( 2866640 2882320 ) Via3_HV
- NEW Metal2 ( 898800 2874480 ) Via2_VH
- NEW Metal2 ( 898800 1075760 ) Via2_VH
- NEW Metal3 ( 2866640 2882320 ) RECT ( -660 -280 0 280 ) ;
- - io_out[36] ( PIN io_out[36] ) ( mprj io_out[36] ) + USE SIGNAL
- + ROUTED Metal3 ( 3920 653520 0 ) ( 42000 * )
- NEW Metal2 ( 42000 653520 ) ( * 1302000 )
- NEW Metal3 ( 42000 1302000 ) ( 2974160 * )
- NEW Metal3 ( 2913680 2908080 ) ( 2974160 * )
- NEW Metal2 ( 2913680 2889040 0 ) ( * 2908080 )
- NEW Metal2 ( 2974160 1302000 ) ( * 2908080 )
- NEW Metal2 ( 42000 653520 ) Via2_VH
- NEW Metal2 ( 42000 1302000 ) Via2_VH
- NEW Metal2 ( 2974160 1302000 ) Via2_VH
- NEW Metal2 ( 2913680 2908080 ) Via2_VH
- NEW Metal2 ( 2974160 2908080 ) Via2_VH ;
- - io_out[37] ( PIN io_out[37] ) ( mprj io_out[37] ) + USE SIGNAL
- + ROUTED Metal3 ( 3920 218960 ) ( * 223440 )
- NEW Metal3 ( 3920 223440 ) ( 5040 * )
- NEW Metal3 ( 5040 223440 ) ( * 224560 )
- NEW Metal3 ( 3920 224560 0 ) ( 5040 * )
- NEW Metal3 ( 3920 218960 ) ( 2962960 * )
- NEW Metal2 ( 2960720 2882320 0 ) ( 2962960 * )
- NEW Metal2 ( 2962960 218960 ) ( * 2882320 )
- NEW Metal2 ( 2962960 218960 ) Via2_VH ;
- - io_out[3] ( PIN io_out[3] ) ( mprj io_out[3] ) + USE SIGNAL
- + ROUTED Metal3 ( 5995920 1394960 ) ( * 1398320 )
+ NEW Metal2 ( 1294160 1692880 ) ( 1296400 * 0 )
+ NEW Metal3 ( 3920 1495760 ) ( 1294160 * )
+ NEW Metal2 ( 1294160 1495760 ) ( * 1692880 )
+ NEW Metal2 ( 1294160 1495760 ) Via2_VH ;
+ - io_out[35] ( PIN io_out[35] ) ( wrapped_vga_clock io_out[35] ) + USE SIGNAL
+ + ROUTED Metal2 ( 1378160 1692880 ) ( 1383760 * 0 )
+ NEW Metal2 ( 1378160 1218000 ) ( * 1692880 )
+ NEW Metal3 ( 159600 1218000 ) ( 1378160 * )
+ NEW Metal3 ( 3920 1078000 0 ) ( 159600 * )
+ NEW Metal2 ( 159600 1078000 ) ( * 1218000 )
+ NEW Metal2 ( 1378160 1218000 ) Via2_VH
+ NEW Metal2 ( 159600 1218000 ) Via2_VH
+ NEW Metal2 ( 159600 1078000 ) Via2_VH ;
+ - io_out[36] ( PIN io_out[36] ) ( wrapped_vga_clock io_out[36] ) + USE SIGNAL
+ + ROUTED Metal3 ( 3920 638960 ) ( * 650160 )
+ NEW Metal3 ( 3920 650160 ) ( 5040 * )
+ NEW Metal3 ( 5040 650160 ) ( * 651280 )
+ NEW Metal3 ( 3920 651280 0 ) ( 5040 * )
+ NEW Metal2 ( 680400 638960 ) ( * 1872080 )
+ NEW Metal3 ( 680400 1872080 ) ( 1177680 * 0 )
+ NEW Metal3 ( 3920 638960 ) ( 680400 * )
+ NEW Metal2 ( 680400 1872080 ) Via2_VH
+ NEW Metal2 ( 680400 638960 ) Via2_VH ;
+ - io_out[37] ( PIN io_out[37] ) ( wrapped_vga_clock io_out[37] ) + USE SIGNAL
+ + ROUTED Metal3 ( 3920 226800 0 ) ( 42000 * )
+ NEW Metal2 ( 42000 226800 ) ( * 445200 )
+ NEW Metal3 ( 42000 445200 ) ( 1799280 * )
+ NEW Metal3 ( 1772400 2060240 0 ) ( 1799280 * )
+ NEW Metal2 ( 1799280 445200 ) ( * 2060240 )
+ NEW Metal2 ( 42000 226800 ) Via2_VH
+ NEW Metal2 ( 42000 445200 ) Via2_VH
+ NEW Metal2 ( 1799280 445200 ) Via2_VH
+ NEW Metal2 ( 1799280 2060240 ) Via2_VH ;
+ - io_out[3] ( PIN io_out[3] ) ( wrapped_vga_clock io_out[3] ) + USE SIGNAL
+ + ROUTED Metal2 ( 1495760 1692880 ) ( 1504720 * 0 )
+ NEW Metal3 ( 5995920 1394960 ) ( * 1398320 )
NEW Metal3 ( 5994800 1398320 ) ( 5995920 * )
NEW Metal3 ( 5994800 1398320 ) ( * 1399440 )
NEW Metal3 ( 5994800 1399440 ) ( 5995920 * 0 )
- NEW Metal3 ( 3385200 1394960 ) ( 5995920 * )
- NEW Metal2 ( 1361360 2889040 0 ) ( * 2928240 )
- NEW Metal3 ( 1361360 2928240 ) ( 3385200 * )
- NEW Metal2 ( 3385200 1394960 ) ( * 2928240 )
- NEW Metal2 ( 3385200 1394960 ) Via2_VH
- NEW Metal2 ( 1361360 2928240 ) Via2_VH
- NEW Metal2 ( 3385200 2928240 ) Via2_VH ;
- - io_out[4] ( PIN io_out[4] ) ( mprj io_out[4] ) + USE SIGNAL
- + ROUTED Metal2 ( 1400560 2889040 ) ( 1408400 * 0 )
- NEW Metal2 ( 1400560 2889040 ) ( * 2945040 )
- NEW Metal2 ( 3066000 1798160 ) ( * 2945040 )
- NEW Metal3 ( 1400560 2945040 ) ( 3066000 * )
- NEW Metal3 ( 3066000 1798160 ) ( 5728800 * )
- NEW Metal3 ( 5728800 1798160 ) ( * 1799280 )
- NEW Metal3 ( 5728800 1799280 ) ( 5995920 * 0 )
- NEW Metal2 ( 1400560 2945040 ) Via2_VH
- NEW Metal2 ( 3066000 1798160 ) Via2_VH
- NEW Metal2 ( 3066000 2945040 ) Via2_VH ;
- - io_out[5] ( PIN io_out[5] ) ( mprj io_out[5] ) + USE SIGNAL
- + ROUTED Metal2 ( 1447600 2889040 ) ( 1455440 * 0 )
- NEW Metal2 ( 1445360 3024000 ) ( 1447600 * )
- NEW Metal2 ( 1447600 2889040 ) ( * 3024000 )
- NEW Metal2 ( 1445360 3024000 ) ( * 3158960 )
- NEW Metal2 ( 5958960 2200240 ) ( * 3158960 )
- NEW Metal3 ( 5958960 2200240 ) ( 5995920 * 0 )
- NEW Metal3 ( 1445360 3158960 ) ( 5958960 * )
- NEW Metal2 ( 5958960 2200240 ) Via2_VH
- NEW Metal2 ( 1445360 3158960 ) Via2_VH
- NEW Metal2 ( 5958960 3158960 ) Via2_VH ;
- - io_out[6] ( PIN io_out[6] ) ( mprj io_out[6] ) + USE SIGNAL
- + ROUTED Metal2 ( 5960080 2601200 ) ( * 3142160 )
- NEW Metal2 ( 1495760 2889040 ) ( 1502480 * 0 )
- NEW Metal3 ( 5960080 2601200 ) ( 5995920 * 0 )
- NEW Metal2 ( 1495760 2889040 ) ( * 3142160 )
- NEW Metal3 ( 1495760 3142160 ) ( 5960080 * )
- NEW Metal2 ( 5960080 2601200 ) Via2_VH
- NEW Metal2 ( 5960080 3142160 ) Via2_VH
- NEW Metal2 ( 1495760 3142160 ) Via2_VH ;
- - io_out[7] ( PIN io_out[7] ) ( mprj io_out[7] ) + USE SIGNAL
- + ROUTED Metal2 ( 1915760 2983120 ) ( * 2990960 )
- NEW Metal2 ( 1546160 2889040 ) ( 1549520 * 0 )
- NEW Metal2 ( 1546160 2889040 ) ( * 2983120 )
- NEW Metal3 ( 1546160 2983120 ) ( 1915760 * )
+ NEW Metal3 ( 1495760 1394960 ) ( 5995920 * )
+ NEW Metal2 ( 1495760 1394960 ) ( * 1692880 )
+ NEW Metal2 ( 1495760 1394960 ) Via2_VH ;
+ - io_out[4] ( PIN io_out[4] ) ( wrapped_vga_clock io_out[4] ) + USE SIGNAL
+ + ROUTED Metal3 ( 1155280 1831760 ) ( 1177680 * 0 )
+ NEW Metal2 ( 1155280 1685040 ) ( * 1831760 )
+ NEW Metal2 ( 5955600 1685040 ) ( * 1799280 )
+ NEW Metal3 ( 1155280 1685040 ) ( 5955600 * )
+ NEW Metal3 ( 5955600 1799280 ) ( 5995920 * 0 )
+ NEW Metal2 ( 1155280 1685040 ) Via2_VH
+ NEW Metal2 ( 5955600 1685040 ) Via2_VH
+ NEW Metal2 ( 1155280 1831760 ) Via2_VH
+ NEW Metal2 ( 5955600 1799280 ) Via2_VH ;
+ - io_out[5] ( PIN io_out[5] ) ( wrapped_vga_clock io_out[5] ) + USE SIGNAL
+ + ROUTED Metal1 ( 1632400 2287600 ) ( * 2290960 )
+ NEW Metal2 ( 1632400 2290960 ) ( * 2321200 )
+ NEW Metal3 ( 1632400 2321200 ) ( 1839600 * )
+ NEW Metal3 ( 5995920 2184560 ) ( * 2198000 )
+ NEW Metal3 ( 5994800 2198000 ) ( 5995920 * )
+ NEW Metal3 ( 5994800 2198000 ) ( * 2199120 )
+ NEW Metal3 ( 5994800 2199120 ) ( 5995920 * 0 )
+ NEW Metal3 ( 1839600 2184560 ) ( 5995920 * )
+ NEW Metal2 ( 1839600 2184560 ) ( * 2321200 )
+ NEW Metal2 ( 1632400 2321200 ) Via2_VH
+ NEW Metal1 ( 1632400 2287600 ) Via1_HV
+ NEW Metal1 ( 1632400 2290960 ) Via1_HV
+ NEW Metal2 ( 1839600 2184560 ) Via2_VH
+ NEW Metal2 ( 1839600 2321200 ) Via2_VH ;
+ - io_out[6] ( PIN io_out[6] ) ( wrapped_vga_clock io_out[6] ) + USE SIGNAL
+ + ROUTED Metal1 ( 1195600 2287600 ) ( * 2290960 )
+ NEW Metal1 ( 1193360 2290960 ) ( 1195600 * )
+ NEW Metal2 ( 1193360 2290960 ) ( * 2378320 )
+ NEW Metal3 ( 1193360 2378320 ) ( 1839600 * )
+ NEW Metal3 ( 5995920 2587760 ) ( * 2597840 )
+ NEW Metal3 ( 5994800 2597840 ) ( 5995920 * )
+ NEW Metal3 ( 5994800 2597840 ) ( * 2598960 )
+ NEW Metal3 ( 5994800 2598960 ) ( 5995920 * 0 )
+ NEW Metal3 ( 1839600 2587760 ) ( 5995920 * )
+ NEW Metal2 ( 1839600 2378320 ) ( * 2587760 )
+ NEW Metal2 ( 1193360 2378320 ) Via2_VH
+ NEW Metal1 ( 1195600 2287600 ) Via1_HV
+ NEW Metal1 ( 1193360 2290960 ) Via1_HV
+ NEW Metal2 ( 1839600 2378320 ) Via2_VH
+ NEW Metal2 ( 1839600 2587760 ) Via2_VH ;
+ - io_out[7] ( PIN io_out[7] ) ( wrapped_vga_clock io_out[7] ) + USE SIGNAL
+ + ROUTED Metal2 ( 1923600 2395120 ) ( * 2990960 )
+ NEW Metal3 ( 1294160 2395120 ) ( 1923600 * )
+ NEW Metal1 ( 1294160 2287600 ) ( 1296400 * )
+ NEW Metal1 ( 1294160 2287600 ) ( * 2290960 )
+ NEW Metal2 ( 1294160 2290960 ) ( * 2395120 )
NEW Metal3 ( 5995920 2990960 ) ( * 2997680 )
NEW Metal3 ( 5994800 2997680 ) ( 5995920 * )
NEW Metal3 ( 5994800 2997680 ) ( * 2998800 )
NEW Metal3 ( 5994800 2998800 ) ( 5995920 * 0 )
- NEW Metal3 ( 1915760 2990960 ) ( 5995920 * )
- NEW Metal2 ( 1915760 2983120 ) Via2_VH
- NEW Metal2 ( 1915760 2990960 ) Via2_VH
- NEW Metal2 ( 1546160 2983120 ) Via2_VH ;
- - io_out[8] ( PIN io_out[8] ) ( mprj io_out[8] ) + USE SIGNAL
- + ROUTED Metal2 ( 1596560 2889040 0 ) ( * 3394160 )
+ NEW Metal3 ( 1923600 2990960 ) ( 5995920 * )
+ NEW Metal2 ( 1923600 2395120 ) Via2_VH
+ NEW Metal2 ( 1923600 2990960 ) Via2_VH
+ NEW Metal2 ( 1294160 2395120 ) Via2_VH
+ NEW Metal1 ( 1296400 2287600 ) Via1_HV
+ NEW Metal1 ( 1294160 2290960 ) Via1_HV ;
+ - io_out[8] ( PIN io_out[8] ) ( wrapped_vga_clock io_out[8] ) + USE SIGNAL
+ + ROUTED Metal2 ( 3553200 1657040 ) ( * 3394160 )
+ NEW Metal2 ( 1593200 1657040 ) ( * 1692880 0 )
+ NEW Metal3 ( 1593200 1657040 ) ( 3553200 * )
NEW Metal3 ( 5995920 3394160 ) ( * 3397520 )
NEW Metal3 ( 5994800 3397520 ) ( 5995920 * )
NEW Metal3 ( 5994800 3397520 ) ( * 3398640 )
NEW Metal3 ( 5994800 3398640 ) ( 5995920 * 0 )
- NEW Metal3 ( 1596560 3394160 ) ( 5995920 * )
- NEW Metal2 ( 1596560 3394160 ) Via2_VH ;
- - io_out[9] ( PIN io_out[9] ) ( mprj io_out[9] ) + USE SIGNAL
- + ROUTED Metal2 ( 1635760 2889040 ) ( 1643600 * 0 )
- NEW Metal3 ( 1630160 3108560 ) ( 1654800 * )
- NEW Metal2 ( 1630160 3024000 ) ( * 3108560 )
- NEW Metal2 ( 1630160 3024000 ) ( 1635760 * )
- NEW Metal2 ( 1635760 2889040 ) ( * 3024000 )
- NEW Metal2 ( 1654800 3108560 ) ( * 3797360 )
- NEW Metal3 ( 1654800 3797360 ) ( 5728800 * )
+ NEW Metal3 ( 3553200 3394160 ) ( 5995920 * )
+ NEW Metal2 ( 3553200 1657040 ) Via2_VH
+ NEW Metal2 ( 3553200 3394160 ) Via2_VH
+ NEW Metal2 ( 1593200 1657040 ) Via2_VH ;
+ - io_out[9] ( PIN io_out[9] ) ( wrapped_vga_clock io_out[9] ) + USE SIGNAL
+ + ROUTED Metal3 ( 1158640 1851920 ) ( 1177680 * 0 )
+ NEW Metal2 ( 1158640 1851920 ) ( * 3797360 )
+ NEW Metal3 ( 1158640 3797360 ) ( 5728800 * )
NEW Metal3 ( 5728800 3797360 ) ( * 3798480 )
NEW Metal3 ( 5728800 3798480 ) ( 5995920 * 0 )
- NEW Metal2 ( 1630160 3108560 ) Via2_VH
- NEW Metal2 ( 1654800 3108560 ) Via2_VH
- NEW Metal2 ( 1654800 3797360 ) Via2_VH ;
- - la_data_in[0] ( PIN la_data_in[0] ) ( mprj la_data_in[0] ) + USE SIGNAL
- + ROUTED Metal2 ( 2150960 3920 0 ) ( * 226800 )
- NEW Metal3 ( 1816080 226800 ) ( 2150960 * )
- NEW Metal1 ( 1816080 1593200 ) ( 1825040 * )
- NEW Metal2 ( 1816080 226800 ) ( * 1593200 )
- NEW Metal2 ( 1825040 1690640 ) ( 1828400 * 0 )
- NEW Metal2 ( 1825040 1593200 ) ( * 1690640 )
- NEW Metal2 ( 2150960 226800 ) Via2_VH
- NEW Metal2 ( 1816080 226800 ) Via2_VH
- NEW Metal1 ( 1816080 1593200 ) Via1_HV
- NEW Metal1 ( 1825040 1593200 ) Via1_HV ;
- - la_data_in[10] ( PIN la_data_in[10] ) ( mprj la_data_in[10] ) + USE SIGNAL
- + ROUTED Metal3 ( 1996400 1649200 ) ( 2041200 * )
- NEW Metal2 ( 2041200 1370320 ) ( * 1649200 )
- NEW Metal3 ( 2041200 1370320 ) ( 2722160 * )
- NEW Metal2 ( 2722160 3920 0 ) ( * 1370320 )
- NEW Metal2 ( 1996400 1649200 ) ( * 1690640 0 )
- NEW Metal2 ( 2041200 1649200 ) Via2_VH
- NEW Metal2 ( 1996400 1649200 ) Via2_VH
- NEW Metal2 ( 2041200 1370320 ) Via2_VH
- NEW Metal2 ( 2722160 1370320 ) Via2_VH ;
- - la_data_in[11] ( PIN la_data_in[11] ) ( mprj la_data_in[11] ) + USE SIGNAL
- + ROUTED Metal1 ( 1999760 1638000 ) ( 2009840 * )
- NEW Metal2 ( 2779280 3920 0 ) ( * 27440 )
- NEW Metal3 ( 1999760 27440 ) ( 2779280 * )
- NEW Metal2 ( 1999760 27440 ) ( * 1638000 )
- NEW Metal2 ( 2009840 1690640 ) ( 2013200 * 0 )
- NEW Metal2 ( 2009840 1638000 ) ( * 1690640 )
- NEW Metal2 ( 1999760 27440 ) Via2_VH
- NEW Metal1 ( 1999760 1638000 ) Via1_HV
- NEW Metal1 ( 2009840 1638000 ) Via1_HV
- NEW Metal2 ( 2779280 27440 ) Via2_VH ;
- - la_data_in[12] ( PIN la_data_in[12] ) ( mprj la_data_in[12] ) + USE SIGNAL
- + ROUTED Metal2 ( 2822960 3920 ) ( 2835280 * )
- NEW Metal2 ( 2835280 3920 ) ( * 5040 )
- NEW Metal2 ( 2835280 5040 ) ( 2836400 * )
- NEW Metal2 ( 2836400 3920 0 ) ( * 5040 )
- NEW Metal2 ( 2822960 3920 ) ( * 1352400 )
- NEW Metal3 ( 2030000 1651440 ) ( 2058000 * )
- NEW Metal2 ( 2058000 1352400 ) ( * 1651440 )
- NEW Metal3 ( 2058000 1352400 ) ( 2822960 * )
- NEW Metal2 ( 2030000 1651440 ) ( * 1690640 0 )
- NEW Metal2 ( 2822960 1352400 ) Via2_VH
- NEW Metal2 ( 2058000 1651440 ) Via2_VH
- NEW Metal2 ( 2030000 1651440 ) Via2_VH
- NEW Metal2 ( 2058000 1352400 ) Via2_VH ;
- - la_data_in[13] ( PIN la_data_in[13] ) ( mprj la_data_in[13] ) + USE SIGNAL
- + ROUTED Metal2 ( 2893520 3920 0 ) ( * 94640 )
- NEW Metal2 ( 2033360 1652560 ) ( 2043440 * )
- NEW Metal2 ( 2033360 94640 ) ( * 1652560 )
- NEW Metal3 ( 2033360 94640 ) ( 2893520 * )
- NEW Metal2 ( 2043440 1690640 ) ( 2046800 * 0 )
- NEW Metal2 ( 2043440 1652560 ) ( * 1690640 )
- NEW Metal2 ( 2893520 94640 ) Via2_VH
- NEW Metal2 ( 2033360 94640 ) Via2_VH ;
- - la_data_in[14] ( PIN la_data_in[14] ) ( mprj la_data_in[14] ) + USE SIGNAL
- + ROUTED Metal1 ( 2051280 1631280 ) ( 2060240 * )
- NEW Metal2 ( 2940560 3920 ) ( 2949520 * )
- NEW Metal2 ( 2949520 3920 ) ( * 5040 )
- NEW Metal2 ( 2949520 5040 ) ( 2950640 * )
- NEW Metal2 ( 2950640 3920 0 ) ( * 5040 )
- NEW Metal2 ( 2051280 127120 ) ( * 1631280 )
- NEW Metal3 ( 2051280 127120 ) ( 2940560 * )
- NEW Metal2 ( 2940560 3920 ) ( * 127120 )
- NEW Metal2 ( 2060240 1690640 ) ( 2063600 * 0 )
- NEW Metal2 ( 2060240 1631280 ) ( * 1690640 )
- NEW Metal1 ( 2051280 1631280 ) Via1_HV
- NEW Metal1 ( 2060240 1631280 ) Via1_HV
- NEW Metal2 ( 2051280 127120 ) Via2_VH
- NEW Metal2 ( 2940560 127120 ) Via2_VH ;
- - la_data_in[15] ( PIN la_data_in[15] ) ( mprj la_data_in[15] ) + USE SIGNAL
- + ROUTED Metal2 ( 3007760 3920 0 ) ( * 1639120 )
- NEW Metal2 ( 2080400 1639120 ) ( * 1690640 0 )
- NEW Metal3 ( 2080400 1639120 ) ( 3007760 * )
- NEW Metal2 ( 2080400 1639120 ) Via2_VH
- NEW Metal2 ( 3007760 1639120 ) Via2_VH ;
- - la_data_in[16] ( PIN la_data_in[16] ) ( mprj la_data_in[16] ) + USE SIGNAL
- + ROUTED Metal3 ( 2083760 1651440 ) ( 2093840 * )
- NEW Metal2 ( 3058160 3920 ) ( 3063760 * )
- NEW Metal2 ( 3063760 3920 ) ( * 5040 )
- NEW Metal2 ( 3063760 5040 ) ( 3064880 * )
- NEW Metal2 ( 3064880 3920 0 ) ( * 5040 )
- NEW Metal2 ( 2083760 178640 ) ( * 1651440 )
- NEW Metal2 ( 3058160 3920 ) ( * 178640 )
- NEW Metal3 ( 2083760 178640 ) ( 3058160 * )
- NEW Metal2 ( 2093840 1690640 ) ( 2097200 * 0 )
- NEW Metal2 ( 2093840 1651440 ) ( * 1690640 )
- NEW Metal2 ( 2083760 1651440 ) Via2_VH
- NEW Metal2 ( 2093840 1651440 ) Via2_VH
- NEW Metal2 ( 2083760 178640 ) Via2_VH
- NEW Metal2 ( 3058160 178640 ) Via2_VH ;
- - la_data_in[17] ( PIN la_data_in[17] ) ( mprj la_data_in[17] ) + USE SIGNAL
- + ROUTED Metal1 ( 2100560 1616720 ) ( 2110640 * )
- NEW Metal2 ( 3108560 3920 ) ( 3120880 * )
- NEW Metal2 ( 3120880 3920 ) ( * 5040 )
- NEW Metal2 ( 3120880 5040 ) ( 3122000 * )
- NEW Metal2 ( 3122000 3920 0 ) ( * 5040 )
- NEW Metal2 ( 2100560 177520 ) ( * 1616720 )
- NEW Metal2 ( 3108560 3920 ) ( * 177520 )
- NEW Metal3 ( 2100560 177520 ) ( 3108560 * )
- NEW Metal2 ( 2110640 1690640 ) ( 2114000 * 0 )
- NEW Metal2 ( 2110640 1616720 ) ( * 1690640 )
- NEW Metal1 ( 2100560 1616720 ) Via1_HV
- NEW Metal1 ( 2110640 1616720 ) Via1_HV
- NEW Metal2 ( 2100560 177520 ) Via2_VH
- NEW Metal2 ( 3108560 177520 ) Via2_VH ;
- - la_data_in[18] ( PIN la_data_in[18] ) ( mprj la_data_in[18] ) + USE SIGNAL
- + ROUTED Metal2 ( 2122960 1660400 ) ( 2127440 * )
- NEW Metal2 ( 2119600 261520 ) ( * 1495200 )
- NEW Metal2 ( 2119600 1495200 ) ( 2122960 * )
- NEW Metal2 ( 2122960 1495200 ) ( * 1660400 )
- NEW Metal2 ( 3175760 3920 ) ( 3178000 * )
- NEW Metal2 ( 3178000 3920 ) ( * 5040 )
- NEW Metal2 ( 3178000 5040 ) ( 3179120 * )
- NEW Metal2 ( 3179120 3920 0 ) ( * 5040 )
- NEW Metal3 ( 2119600 261520 ) ( 3175760 * )
- NEW Metal2 ( 3175760 3920 ) ( * 261520 )
- NEW Metal2 ( 2127440 1690640 ) ( 2130800 * 0 )
- NEW Metal2 ( 2127440 1660400 ) ( * 1690640 )
- NEW Metal2 ( 2119600 261520 ) Via2_VH
- NEW Metal2 ( 3175760 261520 ) Via2_VH ;
- - la_data_in[19] ( PIN la_data_in[19] ) ( mprj la_data_in[19] ) + USE SIGNAL
- + ROUTED Metal3 ( 2135280 1641360 ) ( 2144240 * )
- NEW Metal2 ( 2135280 295120 ) ( * 1641360 )
- NEW Metal2 ( 3226160 3920 ) ( 3235120 * )
- NEW Metal2 ( 3235120 3920 ) ( * 5040 )
- NEW Metal2 ( 3235120 5040 ) ( 3236240 * )
- NEW Metal2 ( 3236240 3920 0 ) ( * 5040 )
- NEW Metal3 ( 2135280 295120 ) ( 3226160 * )
- NEW Metal2 ( 3226160 3920 ) ( * 295120 )
- NEW Metal2 ( 2144240 1690640 ) ( 2147600 * 0 )
- NEW Metal2 ( 2144240 1641360 ) ( * 1690640 )
- NEW Metal2 ( 2135280 295120 ) Via2_VH
- NEW Metal2 ( 2135280 1641360 ) Via2_VH
- NEW Metal2 ( 2144240 1641360 ) Via2_VH
- NEW Metal2 ( 3226160 295120 ) Via2_VH ;
- - la_data_in[1] ( PIN la_data_in[1] ) ( mprj la_data_in[1] ) + USE SIGNAL
- + ROUTED Metal2 ( 2208080 3920 0 ) ( * 78960 )
- NEW Metal3 ( 1831760 78960 ) ( 2208080 * )
- NEW Metal3 ( 1831760 1621200 ) ( 1841840 * )
- NEW Metal2 ( 1831760 78960 ) ( * 1621200 )
- NEW Metal2 ( 1841840 1690640 ) ( 1845200 * 0 )
- NEW Metal2 ( 1841840 1621200 ) ( * 1690640 )
- NEW Metal2 ( 1831760 78960 ) Via2_VH
- NEW Metal2 ( 2208080 78960 ) Via2_VH
- NEW Metal2 ( 1831760 1621200 ) Via2_VH
- NEW Metal2 ( 1841840 1621200 ) Via2_VH ;
- - la_data_in[20] ( PIN la_data_in[20] ) ( mprj la_data_in[20] ) + USE SIGNAL
- + ROUTED Metal1 ( 2150960 1616720 ) ( 2161040 * )
- NEW Metal2 ( 2150960 344400 ) ( * 1616720 )
- NEW Metal2 ( 3293360 3920 0 ) ( * 344400 )
- NEW Metal3 ( 2150960 344400 ) ( 3293360 * )
- NEW Metal2 ( 2161040 1690640 ) ( 2164400 * 0 )
- NEW Metal2 ( 2161040 1616720 ) ( * 1690640 )
- NEW Metal1 ( 2150960 1616720 ) Via1_HV
- NEW Metal1 ( 2161040 1616720 ) Via1_HV
- NEW Metal2 ( 2150960 344400 ) Via2_VH
- NEW Metal2 ( 3293360 344400 ) Via2_VH ;
- - la_data_in[21] ( PIN la_data_in[21] ) ( mprj la_data_in[21] ) + USE SIGNAL
- + ROUTED Metal2 ( 2173360 1661520 ) ( 2177840 * )
- NEW Metal2 ( 3343760 3920 ) ( 3349360 * )
- NEW Metal2 ( 3349360 3920 ) ( * 5040 )
- NEW Metal2 ( 3349360 5040 ) ( 3350480 * )
- NEW Metal2 ( 3350480 3920 0 ) ( * 5040 )
- NEW Metal2 ( 2170000 328720 ) ( * 1495200 )
- NEW Metal2 ( 2170000 1495200 ) ( 2173360 * )
- NEW Metal2 ( 2173360 1495200 ) ( * 1661520 )
- NEW Metal2 ( 3343760 3920 ) ( * 328720 )
- NEW Metal3 ( 2170000 328720 ) ( 3343760 * )
- NEW Metal2 ( 2177840 1690640 ) ( 2181200 * 0 )
- NEW Metal2 ( 2177840 1661520 ) ( * 1690640 )
- NEW Metal2 ( 2170000 328720 ) Via2_VH
- NEW Metal2 ( 3343760 328720 ) Via2_VH ;
- - la_data_in[22] ( PIN la_data_in[22] ) ( mprj la_data_in[22] ) + USE SIGNAL
- + ROUTED Metal1 ( 2184560 1650320 ) ( 2194640 * )
- NEW Metal2 ( 2184560 277200 ) ( * 1650320 )
- NEW Metal2 ( 3394160 3920 ) ( 3406480 * )
- NEW Metal2 ( 3406480 3920 ) ( * 5040 )
- NEW Metal2 ( 3406480 5040 ) ( 3407600 * )
- NEW Metal2 ( 3407600 3920 0 ) ( * 5040 )
- NEW Metal3 ( 2184560 277200 ) ( 3394160 * )
- NEW Metal2 ( 3394160 3920 ) ( * 277200 )
- NEW Metal2 ( 2194640 1690640 ) ( 2198000 * 0 )
- NEW Metal2 ( 2194640 1650320 ) ( * 1690640 )
- NEW Metal2 ( 2184560 277200 ) Via2_VH
- NEW Metal1 ( 2184560 1650320 ) Via1_HV
- NEW Metal1 ( 2194640 1650320 ) Via1_HV
- NEW Metal2 ( 3394160 277200 ) Via2_VH ;
- - la_data_in[23] ( PIN la_data_in[23] ) ( mprj la_data_in[23] ) + USE SIGNAL
- + ROUTED Metal2 ( 3461360 3920 ) ( 3463600 * )
- NEW Metal2 ( 3463600 3920 ) ( * 5040 )
- NEW Metal2 ( 3463600 5040 ) ( 3464720 * )
- NEW Metal2 ( 3464720 3920 0 ) ( * 5040 )
- NEW Metal3 ( 2201360 244720 ) ( 3461360 * )
- NEW Metal2 ( 2201360 244720 ) ( * 1495200 )
- NEW Metal2 ( 2201360 1495200 ) ( 2211440 * )
- NEW Metal2 ( 3461360 3920 ) ( * 244720 )
- NEW Metal2 ( 2211440 1690640 ) ( 2214800 * 0 )
- NEW Metal2 ( 2211440 1495200 ) ( * 1690640 )
- NEW Metal2 ( 2201360 244720 ) Via2_VH
- NEW Metal2 ( 3461360 244720 ) Via2_VH ;
- - la_data_in[24] ( PIN la_data_in[24] ) ( mprj la_data_in[24] ) + USE SIGNAL
- + ROUTED Metal2 ( 3511760 3920 ) ( 3520720 * )
- NEW Metal2 ( 3520720 3920 ) ( * 5040 )
- NEW Metal2 ( 3520720 5040 ) ( 3521840 * )
- NEW Metal2 ( 3521840 3920 0 ) ( * 5040 )
- NEW Metal2 ( 3511760 3920 ) ( * 211120 )
- NEW Metal3 ( 2219280 1626800 ) ( 2228240 * )
- NEW Metal3 ( 2219280 211120 ) ( 3511760 * )
- NEW Metal2 ( 2219280 211120 ) ( * 1626800 )
- NEW Metal2 ( 2228240 1690640 ) ( 2231600 * 0 )
- NEW Metal2 ( 2228240 1626800 ) ( * 1690640 )
- NEW Metal2 ( 3511760 211120 ) Via2_VH
- NEW Metal2 ( 2219280 211120 ) Via2_VH
- NEW Metal2 ( 2219280 1626800 ) Via2_VH
- NEW Metal2 ( 2228240 1626800 ) Via2_VH ;
- - la_data_in[25] ( PIN la_data_in[25] ) ( mprj la_data_in[25] ) + USE SIGNAL
- + ROUTED Metal2 ( 3578960 3920 0 ) ( * 1624560 )
- NEW Metal2 ( 2251760 1624560 ) ( * 1646960 )
- NEW Metal2 ( 2250640 1646960 ) ( 2251760 * )
- NEW Metal3 ( 2251760 1624560 ) ( 3578960 * )
- NEW Metal2 ( 2248400 1690640 0 ) ( 2250640 * )
- NEW Metal2 ( 2250640 1646960 ) ( * 1690640 )
- NEW Metal2 ( 3578960 1624560 ) Via2_VH
- NEW Metal2 ( 2251760 1624560 ) Via2_VH ;
- - la_data_in[26] ( PIN la_data_in[26] ) ( mprj la_data_in[26] ) + USE SIGNAL
- + ROUTED Metal3 ( 2671200 1653680 ) ( * 1654800 )
- NEW Metal3 ( 2671200 1653680 ) ( 2765840 * )
- NEW Metal2 ( 3629360 3920 ) ( 3634960 * )
- NEW Metal2 ( 3634960 3920 ) ( * 5040 )
- NEW Metal2 ( 3634960 5040 ) ( 3636080 * )
- NEW Metal2 ( 3636080 3920 0 ) ( * 5040 )
- NEW Metal2 ( 2765840 1608880 ) ( * 1653680 )
- NEW Metal3 ( 2765840 1608880 ) ( 3629360 * )
- NEW Metal2 ( 3629360 3920 ) ( * 1608880 )
- NEW Metal3 ( 2265200 1654800 ) ( 2671200 * )
- NEW Metal2 ( 2265200 1654800 ) ( * 1690640 0 )
- NEW Metal2 ( 2265200 1654800 ) Via2_VH
- NEW Metal2 ( 2765840 1653680 ) Via2_VH
- NEW Metal2 ( 2765840 1608880 ) Via2_VH
- NEW Metal2 ( 3629360 1608880 ) Via2_VH ;
- - la_data_in[27] ( PIN la_data_in[27] ) ( mprj la_data_in[27] ) + USE SIGNAL
- + ROUTED Metal2 ( 3693200 3920 0 ) ( * 25200 )
- NEW Metal3 ( 2268560 25200 ) ( 3693200 * )
- NEW Metal3 ( 2268560 1621200 ) ( 2278640 * )
- NEW Metal2 ( 2268560 25200 ) ( * 1621200 )
- NEW Metal2 ( 2278640 1690640 ) ( 2282000 * 0 )
- NEW Metal2 ( 2278640 1621200 ) ( * 1690640 )
- NEW Metal2 ( 2268560 25200 ) Via2_VH
- NEW Metal2 ( 3693200 25200 ) Via2_VH
- NEW Metal2 ( 2268560 1621200 ) Via2_VH
- NEW Metal2 ( 2278640 1621200 ) Via2_VH ;
- - la_data_in[28] ( PIN la_data_in[28] ) ( mprj la_data_in[28] ) + USE SIGNAL
- + ROUTED Metal2 ( 3749200 560 ) ( * 5040 )
- NEW Metal2 ( 3749200 5040 ) ( 3750320 * )
- NEW Metal2 ( 3750320 3920 0 ) ( * 5040 )
- NEW Metal3 ( 2288720 560 ) ( 3749200 * )
- NEW Metal2 ( 2288720 560 ) ( * 1495200 )
- NEW Metal2 ( 2288720 1495200 ) ( 2295440 * )
- NEW Metal2 ( 2295440 1690640 ) ( 2298800 * 0 )
- NEW Metal2 ( 2295440 1495200 ) ( * 1690640 )
- NEW Metal2 ( 3749200 560 ) Via2_VH
- NEW Metal2 ( 2288720 560 ) Via2_VH ;
- - la_data_in[29] ( PIN la_data_in[29] ) ( mprj la_data_in[29] ) + USE SIGNAL
- + ROUTED Metal2 ( 3797360 3920 ) ( 3806320 * )
- NEW Metal2 ( 3806320 3920 ) ( * 5040 )
- NEW Metal2 ( 3806320 5040 ) ( 3807440 * )
- NEW Metal2 ( 3807440 3920 0 ) ( * 5040 )
- NEW Metal2 ( 3797360 3920 ) ( * 210000 )
- NEW Metal3 ( 2302160 210000 ) ( 3797360 * )
- NEW Metal3 ( 2302160 1621200 ) ( 2312240 * )
- NEW Metal2 ( 2302160 210000 ) ( * 1621200 )
- NEW Metal2 ( 2312240 1690640 ) ( 2315600 * 0 )
- NEW Metal2 ( 2312240 1621200 ) ( * 1690640 )
- NEW Metal2 ( 3797360 210000 ) Via2_VH
- NEW Metal2 ( 2302160 210000 ) Via2_VH
- NEW Metal2 ( 2302160 1621200 ) Via2_VH
- NEW Metal2 ( 2312240 1621200 ) Via2_VH ;
- - la_data_in[2] ( PIN la_data_in[2] ) ( mprj la_data_in[2] ) + USE SIGNAL
- + ROUTED Metal2 ( 2252880 3920 ) ( 2264080 * )
- NEW Metal2 ( 2264080 3920 ) ( * 5040 )
- NEW Metal2 ( 2264080 5040 ) ( 2265200 * )
- NEW Metal2 ( 2265200 3920 0 ) ( * 5040 )
- NEW Metal3 ( 1873200 1386000 ) ( 2252880 * )
- NEW Metal2 ( 2252880 3920 ) ( * 1386000 )
- NEW Metal3 ( 1862000 1648080 ) ( 1873200 * )
- NEW Metal2 ( 1873200 1386000 ) ( * 1648080 )
- NEW Metal2 ( 1862000 1648080 ) ( * 1690640 0 )
- NEW Metal2 ( 1873200 1386000 ) Via2_VH
- NEW Metal2 ( 2252880 1386000 ) Via2_VH
- NEW Metal2 ( 1862000 1648080 ) Via2_VH
- NEW Metal2 ( 1873200 1648080 ) Via2_VH ;
- - la_data_in[30] ( PIN la_data_in[30] ) ( mprj la_data_in[30] ) + USE SIGNAL
- + ROUTED Metal2 ( 2320080 243600 ) ( * 1495200 )
- NEW Metal2 ( 2320080 1495200 ) ( 2324560 * )
- NEW Metal3 ( 2320080 243600 ) ( 3864560 * )
- NEW Metal2 ( 3864560 3920 0 ) ( * 243600 )
- NEW Metal2 ( 2324560 1495200 ) ( * 1680000 )
- NEW Metal2 ( 2324560 1680000 ) ( 2329040 * )
- NEW Metal2 ( 2329040 1680000 ) ( * 1690640 )
- NEW Metal2 ( 2329040 1690640 ) ( 2332400 * 0 )
- NEW Metal2 ( 2320080 243600 ) Via2_VH
- NEW Metal2 ( 3864560 243600 ) Via2_VH ;
- - la_data_in[31] ( PIN la_data_in[31] ) ( mprj la_data_in[31] ) + USE SIGNAL
- + ROUTED Metal2 ( 3914960 3920 ) ( 3920560 * )
- NEW Metal2 ( 3920560 3920 ) ( * 5040 )
- NEW Metal2 ( 3920560 5040 ) ( 3921680 * )
- NEW Metal2 ( 3921680 3920 0 ) ( * 5040 )
- NEW Metal2 ( 3914960 3920 ) ( * 1606640 )
- NEW Metal2 ( 2345840 1690640 ) ( 2349200 * 0 )
- NEW Metal2 ( 2345840 1606640 ) ( * 1690640 )
- NEW Metal3 ( 2345840 1606640 ) ( 3914960 * )
- NEW Metal2 ( 3914960 1606640 ) Via2_VH
- NEW Metal2 ( 2345840 1606640 ) Via2_VH ;
- - la_data_in[32] ( PIN la_data_in[32] ) ( mprj la_data_in[32] ) + USE SIGNAL
- + ROUTED Metal2 ( 3965360 3920 ) ( 3977680 * )
- NEW Metal2 ( 3977680 3920 ) ( * 5040 )
- NEW Metal2 ( 3977680 5040 ) ( 3978800 * )
- NEW Metal2 ( 3978800 3920 0 ) ( * 5040 )
- NEW Metal2 ( 3965360 3920 ) ( * 1588720 )
- NEW Metal2 ( 2362640 1690640 ) ( 2366000 * 0 )
- NEW Metal2 ( 2362640 1588720 ) ( * 1690640 )
- NEW Metal3 ( 2362640 1588720 ) ( 3965360 * )
- NEW Metal2 ( 3965360 1588720 ) Via2_VH
- NEW Metal2 ( 2362640 1588720 ) Via2_VH ;
- - la_data_in[33] ( PIN la_data_in[33] ) ( mprj la_data_in[33] ) + USE SIGNAL
- + ROUTED Metal2 ( 4032560 3920 ) ( 4034800 * )
- NEW Metal2 ( 4034800 3920 ) ( * 5040 )
- NEW Metal2 ( 4034800 5040 ) ( 4035920 * )
- NEW Metal2 ( 4035920 3920 0 ) ( * 5040 )
- NEW Metal2 ( 4032560 3920 ) ( * 226800 )
- NEW Metal3 ( 2370480 226800 ) ( 4032560 * )
- NEW Metal1 ( 2370480 1621200 ) ( 2379440 * )
- NEW Metal2 ( 2370480 226800 ) ( * 1621200 )
- NEW Metal2 ( 2379440 1690640 ) ( 2382800 * 0 )
- NEW Metal2 ( 2379440 1621200 ) ( * 1690640 )
- NEW Metal2 ( 2370480 226800 ) Via2_VH
- NEW Metal2 ( 4032560 226800 ) Via2_VH
- NEW Metal1 ( 2370480 1621200 ) Via1_HV
- NEW Metal1 ( 2379440 1621200 ) Via1_HV ;
- - la_data_in[34] ( PIN la_data_in[34] ) ( mprj la_data_in[34] ) + USE SIGNAL
- + ROUTED Metal2 ( 4082960 3920 ) ( 4091920 * )
- NEW Metal2 ( 4091920 3920 ) ( * 5040 )
- NEW Metal2 ( 4091920 5040 ) ( 4093040 * )
- NEW Metal2 ( 4093040 3920 0 ) ( * 5040 )
- NEW Metal2 ( 2762480 1589840 ) ( * 1655920 )
- NEW Metal3 ( 2762480 1589840 ) ( 4082960 * )
- NEW Metal2 ( 4082960 3920 ) ( * 1589840 )
- NEW Metal2 ( 2399600 1655920 ) ( * 1690640 0 )
- NEW Metal3 ( 2399600 1655920 ) ( 2762480 * )
- NEW Metal2 ( 2762480 1655920 ) Via2_VH
- NEW Metal2 ( 2762480 1589840 ) Via2_VH
- NEW Metal2 ( 4082960 1589840 ) Via2_VH
- NEW Metal2 ( 2399600 1655920 ) Via2_VH ;
- - la_data_in[35] ( PIN la_data_in[35] ) ( mprj la_data_in[35] ) + USE SIGNAL
- + ROUTED Metal2 ( 2413040 1690640 ) ( 2416400 * 0 )
- NEW Metal3 ( 2404080 294000 ) ( 4150160 * )
- NEW Metal2 ( 4150160 3920 0 ) ( * 294000 )
- NEW Metal1 ( 2404080 1621200 ) ( 2413040 * )
- NEW Metal2 ( 2413040 1621200 ) ( * 1690640 )
- NEW Metal2 ( 2404080 294000 ) ( * 1621200 )
- NEW Metal2 ( 2404080 294000 ) Via2_VH
- NEW Metal2 ( 4150160 294000 ) Via2_VH
- NEW Metal1 ( 2404080 1621200 ) Via1_HV
- NEW Metal1 ( 2413040 1621200 ) Via1_HV ;
- - la_data_in[36] ( PIN la_data_in[36] ) ( mprj la_data_in[36] ) + USE SIGNAL
- + ROUTED Metal2 ( 2433200 1690640 0 ) ( 2435440 * )
- NEW Metal2 ( 4200560 3920 ) ( 4206160 * )
- NEW Metal2 ( 4206160 3920 ) ( * 5040 )
- NEW Metal2 ( 4206160 5040 ) ( 4207280 * )
- NEW Metal2 ( 4207280 3920 0 ) ( * 5040 )
- NEW Metal2 ( 4200560 3920 ) ( * 1663760 )
- NEW Metal2 ( 2435440 1663760 ) ( * 1690640 )
- NEW Metal3 ( 2435440 1663760 ) ( 4200560 * )
- NEW Metal2 ( 4200560 1663760 ) Via2_VH
- NEW Metal2 ( 2435440 1663760 ) Via2_VH ;
- - la_data_in[37] ( PIN la_data_in[37] ) ( mprj la_data_in[37] ) + USE SIGNAL
- + ROUTED Metal2 ( 4250960 3920 ) ( 4263280 * )
- NEW Metal2 ( 4263280 3920 ) ( * 5040 )
- NEW Metal2 ( 4263280 5040 ) ( 4264400 * )
- NEW Metal2 ( 4264400 3920 0 ) ( * 5040 )
- NEW Metal2 ( 4250960 3920 ) ( * 1574160 )
- NEW Metal2 ( 2446640 1690640 ) ( 2450000 * 0 )
- NEW Metal2 ( 2446640 1574160 ) ( * 1690640 )
- NEW Metal3 ( 2446640 1574160 ) ( 4250960 * )
- NEW Metal2 ( 4250960 1574160 ) Via2_VH
- NEW Metal2 ( 2446640 1574160 ) Via2_VH ;
- - la_data_in[38] ( PIN la_data_in[38] ) ( mprj la_data_in[38] ) + USE SIGNAL
- + ROUTED Metal2 ( 4318160 3920 ) ( 4320400 * )
- NEW Metal2 ( 4320400 3920 ) ( * 5040 )
- NEW Metal2 ( 4320400 5040 ) ( 4321520 * )
- NEW Metal2 ( 4321520 3920 0 ) ( * 5040 )
- NEW Metal2 ( 4318160 3920 ) ( * 1623440 )
- NEW Metal2 ( 2570960 1623440 ) ( * 1657040 )
- NEW Metal3 ( 2570960 1623440 ) ( 4318160 * )
- NEW Metal2 ( 2466800 1657040 ) ( * 1690640 0 )
- NEW Metal3 ( 2466800 1657040 ) ( 2570960 * )
- NEW Metal2 ( 4318160 1623440 ) Via2_VH
- NEW Metal2 ( 2570960 1657040 ) Via2_VH
- NEW Metal2 ( 2570960 1623440 ) Via2_VH
- NEW Metal2 ( 2466800 1657040 ) Via2_VH ;
- - la_data_in[39] ( PIN la_data_in[39] ) ( mprj la_data_in[39] ) + USE SIGNAL
- + ROUTED Metal2 ( 2480240 1690640 ) ( 2483600 * 0 )
- NEW Metal2 ( 4368560 3920 ) ( 4377520 * )
- NEW Metal2 ( 4377520 3920 ) ( * 5040 )
- NEW Metal2 ( 4377520 5040 ) ( 4378640 * )
- NEW Metal2 ( 4378640 3920 0 ) ( * 5040 )
- NEW Metal3 ( 2471280 327600 ) ( 4368560 * )
- NEW Metal2 ( 4368560 3920 ) ( * 327600 )
- NEW Metal3 ( 2471280 1620080 ) ( 2480240 * )
- NEW Metal2 ( 2480240 1620080 ) ( * 1690640 )
- NEW Metal2 ( 2471280 327600 ) ( * 1620080 )
- NEW Metal2 ( 2471280 327600 ) Via2_VH
- NEW Metal2 ( 4368560 327600 ) Via2_VH
- NEW Metal2 ( 2471280 1620080 ) Via2_VH
- NEW Metal2 ( 2480240 1620080 ) Via2_VH ;
- - la_data_in[3] ( PIN la_data_in[3] ) ( mprj la_data_in[3] ) + USE SIGNAL
- + ROUTED Metal2 ( 2321200 201600 ) ( * 310800 )
- NEW Metal2 ( 2321200 201600 ) ( 2322320 * )
- NEW Metal2 ( 2322320 3920 0 ) ( * 201600 )
- NEW Metal3 ( 1865360 310800 ) ( 2321200 * )
- NEW Metal3 ( 1865360 1621200 ) ( 1875440 * )
- NEW Metal2 ( 1865360 310800 ) ( * 1621200 )
- NEW Metal2 ( 1875440 1690640 ) ( 1878800 * 0 )
- NEW Metal2 ( 1875440 1621200 ) ( * 1690640 )
- NEW Metal2 ( 1865360 310800 ) Via2_VH
- NEW Metal2 ( 2321200 310800 ) Via2_VH
- NEW Metal2 ( 1865360 1621200 ) Via2_VH
- NEW Metal2 ( 1875440 1621200 ) Via2_VH ;
- - la_data_in[40] ( PIN la_data_in[40] ) ( mprj la_data_in[40] ) + USE SIGNAL
- + ROUTED Metal2 ( 4435760 3920 0 ) ( * 1573040 )
- NEW Metal2 ( 2497040 1690640 ) ( 2500400 * 0 )
- NEW Metal2 ( 2497040 1573040 ) ( * 1690640 )
- NEW Metal3 ( 2497040 1573040 ) ( 4435760 * )
- NEW Metal2 ( 4435760 1573040 ) Via2_VH
- NEW Metal2 ( 2497040 1573040 ) Via2_VH ;
- - la_data_in[41] ( PIN la_data_in[41] ) ( mprj la_data_in[41] ) + USE SIGNAL
- + ROUTED Metal2 ( 4486160 3920 ) ( 4491760 * )
- NEW Metal2 ( 4491760 3920 ) ( * 5040 )
- NEW Metal2 ( 4491760 5040 ) ( 4492880 * )
- NEW Metal2 ( 4492880 3920 0 ) ( * 5040 )
- NEW Metal2 ( 4486160 3920 ) ( * 1641360 )
- NEW Metal3 ( 2517200 1661520 ) ( 2604560 * )
- NEW Metal2 ( 2604560 1641360 ) ( * 1661520 )
- NEW Metal3 ( 2604560 1641360 ) ( 4486160 * )
- NEW Metal2 ( 2517200 1661520 ) ( * 1690640 0 )
- NEW Metal2 ( 4486160 1641360 ) Via2_VH
- NEW Metal2 ( 2517200 1661520 ) Via2_VH
- NEW Metal2 ( 2604560 1661520 ) Via2_VH
- NEW Metal2 ( 2604560 1641360 ) Via2_VH ;
- - la_data_in[42] ( PIN la_data_in[42] ) ( mprj la_data_in[42] ) + USE SIGNAL
- + ROUTED Metal2 ( 4536560 3920 ) ( 4548880 * )
- NEW Metal2 ( 4548880 3920 ) ( * 5040 )
- NEW Metal2 ( 4548880 5040 ) ( 4550000 * )
- NEW Metal2 ( 4550000 3920 0 ) ( * 5040 )
- NEW Metal2 ( 4536560 3920 ) ( * 1557360 )
- NEW Metal3 ( 2530640 1557360 ) ( 4536560 * )
- NEW Metal2 ( 2530640 1690640 ) ( 2534000 * 0 )
- NEW Metal2 ( 2530640 1557360 ) ( * 1690640 )
- NEW Metal2 ( 4536560 1557360 ) Via2_VH
- NEW Metal2 ( 2530640 1557360 ) Via2_VH ;
- - la_data_in[43] ( PIN la_data_in[43] ) ( mprj la_data_in[43] ) + USE SIGNAL
- + ROUTED Metal2 ( 4603760 3920 ) ( 4606000 * )
- NEW Metal2 ( 4606000 3920 ) ( * 5040 )
- NEW Metal2 ( 4606000 5040 ) ( 4607120 * )
- NEW Metal2 ( 4607120 3920 0 ) ( * 5040 )
- NEW Metal3 ( 2547440 1556240 ) ( 4603760 * )
- NEW Metal2 ( 4603760 3920 ) ( * 1556240 )
- NEW Metal2 ( 2547440 1690640 ) ( 2550800 * 0 )
- NEW Metal2 ( 2547440 1556240 ) ( * 1690640 )
- NEW Metal2 ( 2547440 1556240 ) Via2_VH
- NEW Metal2 ( 4603760 1556240 ) Via2_VH ;
- - la_data_in[44] ( PIN la_data_in[44] ) ( mprj la_data_in[44] ) + USE SIGNAL
- + ROUTED Metal2 ( 4654160 3920 ) ( 4663120 * )
- NEW Metal2 ( 4663120 3920 ) ( * 5040 )
- NEW Metal2 ( 4663120 5040 ) ( 4664240 * )
- NEW Metal2 ( 4664240 3920 0 ) ( * 5040 )
- NEW Metal2 ( 4654160 3920 ) ( * 1587600 )
- NEW Metal3 ( 2564240 1587600 ) ( 4654160 * )
- NEW Metal2 ( 2564240 1690640 ) ( 2567600 * 0 )
- NEW Metal2 ( 2564240 1587600 ) ( * 1690640 )
- NEW Metal2 ( 4654160 1587600 ) Via2_VH
- NEW Metal2 ( 2564240 1587600 ) Via2_VH ;
- - la_data_in[45] ( PIN la_data_in[45] ) ( mprj la_data_in[45] ) + USE SIGNAL
- + ROUTED Metal3 ( 4712400 40880 ) ( 4721360 * )
- NEW Metal2 ( 4721360 3920 0 ) ( * 40880 )
- NEW Metal2 ( 4712400 40880 ) ( * 1672720 )
- NEW Metal3 ( 2584400 1672720 ) ( 4712400 * )
- NEW Metal2 ( 2584400 1672720 ) ( * 1690640 0 )
- NEW Metal2 ( 4712400 40880 ) Via2_VH
- NEW Metal2 ( 4721360 40880 ) Via2_VH
- NEW Metal2 ( 4712400 1672720 ) Via2_VH
- NEW Metal2 ( 2584400 1672720 ) Via2_VH ;
- - la_data_in[46] ( PIN la_data_in[46] ) ( mprj la_data_in[46] ) + USE SIGNAL
- + ROUTED Metal2 ( 4771760 3920 ) ( 4777360 * )
- NEW Metal2 ( 4777360 3920 ) ( * 5040 )
- NEW Metal2 ( 4777360 5040 ) ( 4778480 * )
- NEW Metal2 ( 4778480 3920 0 ) ( * 5040 )
- NEW Metal2 ( 4771760 3920 ) ( * 310800 )
- NEW Metal3 ( 2588880 310800 ) ( 4771760 * )
- NEW Metal1 ( 2588880 1621200 ) ( 2597840 * )
- NEW Metal2 ( 2588880 310800 ) ( * 1621200 )
- NEW Metal2 ( 2597840 1690640 ) ( 2601200 * 0 )
- NEW Metal2 ( 2597840 1621200 ) ( * 1690640 )
- NEW Metal2 ( 2588880 310800 ) Via2_VH
- NEW Metal2 ( 4771760 310800 ) Via2_VH
- NEW Metal1 ( 2588880 1621200 ) Via1_HV
- NEW Metal1 ( 2597840 1621200 ) Via1_HV ;
- - la_data_in[47] ( PIN la_data_in[47] ) ( mprj la_data_in[47] ) + USE SIGNAL
- + ROUTED Metal2 ( 4822160 3920 ) ( 4834480 * )
- NEW Metal2 ( 4834480 3920 ) ( * 5040 )
- NEW Metal2 ( 4834480 5040 ) ( 4835600 * )
- NEW Metal2 ( 4835600 3920 0 ) ( * 5040 )
- NEW Metal2 ( 2679600 1555120 ) ( * 1660400 )
- NEW Metal3 ( 2679600 1555120 ) ( 4822160 * )
- NEW Metal2 ( 4822160 3920 ) ( * 1555120 )
- NEW Metal3 ( 2618000 1660400 ) ( 2679600 * )
- NEW Metal2 ( 2618000 1660400 ) ( * 1690640 0 )
- NEW Metal2 ( 2679600 1660400 ) Via2_VH
- NEW Metal2 ( 2679600 1555120 ) Via2_VH
- NEW Metal2 ( 4822160 1555120 ) Via2_VH
- NEW Metal2 ( 2618000 1660400 ) Via2_VH ;
- - la_data_in[48] ( PIN la_data_in[48] ) ( mprj la_data_in[48] ) + USE SIGNAL
- + ROUTED Metal2 ( 2631440 1690640 ) ( 2634800 * 0 )
- NEW Metal2 ( 2631440 1539440 ) ( * 1690640 )
- NEW Metal2 ( 4889360 3920 ) ( 4891600 * )
- NEW Metal2 ( 4891600 3920 ) ( * 5040 )
- NEW Metal2 ( 4891600 5040 ) ( 4892720 * )
- NEW Metal2 ( 4892720 3920 0 ) ( * 5040 )
- NEW Metal3 ( 2631440 1539440 ) ( 4889360 * )
- NEW Metal2 ( 4889360 3920 ) ( * 1539440 )
- NEW Metal2 ( 2631440 1539440 ) Via2_VH
- NEW Metal2 ( 4889360 1539440 ) Via2_VH ;
- - la_data_in[49] ( PIN la_data_in[49] ) ( mprj la_data_in[49] ) + USE SIGNAL
- + ROUTED Metal2 ( 2644880 1652560 ) ( 2648240 * )
- NEW Metal2 ( 2648240 1652560 ) ( * 1690640 )
- NEW Metal2 ( 2648240 1690640 ) ( 2651600 * 0 )
- NEW Metal2 ( 4949840 3920 0 ) ( * 46480 )
- NEW Metal2 ( 2644880 1605520 ) ( * 1652560 )
- NEW Metal3 ( 4361840 46480 ) ( 4949840 * )
- NEW Metal2 ( 4359600 201600 ) ( 4361840 * )
- NEW Metal2 ( 4361840 46480 ) ( * 201600 )
- NEW Metal3 ( 2644880 1605520 ) ( 4359600 * )
- NEW Metal2 ( 4359600 201600 ) ( * 1605520 )
- NEW Metal2 ( 4949840 46480 ) Via2_VH
- NEW Metal2 ( 2644880 1605520 ) Via2_VH
- NEW Metal2 ( 4361840 46480 ) Via2_VH
- NEW Metal2 ( 4359600 1605520 ) Via2_VH ;
- - la_data_in[4] ( PIN la_data_in[4] ) ( mprj la_data_in[4] ) + USE SIGNAL
- + ROUTED Metal2 ( 2379440 3920 0 ) ( * 28560 )
- NEW Metal3 ( 1882160 28560 ) ( 2379440 * )
- NEW Metal3 ( 1882160 1621200 ) ( 1892240 * )
- NEW Metal2 ( 1882160 28560 ) ( * 1621200 )
- NEW Metal2 ( 1892240 1690640 ) ( 1895600 * 0 )
- NEW Metal2 ( 1892240 1621200 ) ( * 1690640 )
- NEW Metal2 ( 1882160 28560 ) Via2_VH
- NEW Metal2 ( 2379440 28560 ) Via2_VH
- NEW Metal2 ( 1882160 1621200 ) Via2_VH
- NEW Metal2 ( 1892240 1621200 ) Via2_VH ;
- - la_data_in[50] ( PIN la_data_in[50] ) ( mprj la_data_in[50] ) + USE SIGNAL
- + ROUTED Metal1 ( 2654960 1646960 ) ( 2665040 * )
- NEW Metal2 ( 2665040 1646960 ) ( * 1690640 )
- NEW Metal2 ( 2665040 1690640 ) ( 2668400 * 0 )
- NEW Metal3 ( 4998000 40880 ) ( 5006960 * )
- NEW Metal2 ( 5006960 3920 0 ) ( * 40880 )
- NEW Metal2 ( 2654960 1522640 ) ( * 1646960 )
- NEW Metal2 ( 4998000 40880 ) ( * 1522640 )
- NEW Metal3 ( 2654960 1522640 ) ( 4998000 * )
- NEW Metal1 ( 2654960 1646960 ) Via1_HV
- NEW Metal1 ( 2665040 1646960 ) Via1_HV
- NEW Metal2 ( 4998000 40880 ) Via2_VH
- NEW Metal2 ( 5006960 40880 ) Via2_VH
- NEW Metal2 ( 2654960 1522640 ) Via2_VH
- NEW Metal2 ( 4998000 1522640 ) Via2_VH ;
- - la_data_in[51] ( PIN la_data_in[51] ) ( mprj la_data_in[51] ) + USE SIGNAL
- + ROUTED Metal1 ( 2672880 1617840 ) ( 2681840 * )
- NEW Metal2 ( 2681840 1617840 ) ( * 1690640 )
- NEW Metal2 ( 2681840 1690640 ) ( 2685200 * 0 )
- NEW Metal2 ( 5057360 3920 ) ( 5062960 * )
- NEW Metal2 ( 5062960 3920 ) ( * 5040 )
- NEW Metal2 ( 5062960 5040 ) ( 5064080 * )
- NEW Metal2 ( 5064080 3920 0 ) ( * 5040 )
- NEW Metal2 ( 2672880 1521520 ) ( * 1617840 )
- NEW Metal3 ( 2672880 1521520 ) ( 5057360 * )
- NEW Metal2 ( 5057360 3920 ) ( * 1521520 )
- NEW Metal1 ( 2672880 1617840 ) Via1_HV
- NEW Metal1 ( 2681840 1617840 ) Via1_HV
- NEW Metal2 ( 2672880 1521520 ) Via2_VH
- NEW Metal2 ( 5057360 1521520 ) Via2_VH ;
- - la_data_in[52] ( PIN la_data_in[52] ) ( mprj la_data_in[52] ) + USE SIGNAL
- + ROUTED Metal2 ( 2698640 1690640 ) ( 2702000 * 0 )
- NEW Metal2 ( 5107760 3920 ) ( 5120080 * )
- NEW Metal2 ( 5120080 3920 ) ( * 5040 )
- NEW Metal2 ( 5120080 5040 ) ( 5121200 * )
- NEW Metal2 ( 5121200 3920 0 ) ( * 5040 )
- NEW Metal2 ( 2698640 1538320 ) ( * 1690640 )
- NEW Metal3 ( 2698640 1538320 ) ( 5107760 * )
- NEW Metal2 ( 5107760 3920 ) ( * 1538320 )
- NEW Metal2 ( 2698640 1538320 ) Via2_VH
- NEW Metal2 ( 5107760 1538320 ) Via2_VH ;
- - la_data_in[53] ( PIN la_data_in[53] ) ( mprj la_data_in[53] ) + USE SIGNAL
- + ROUTED Metal2 ( 5174960 3920 ) ( 5177200 * )
- NEW Metal2 ( 5177200 3920 ) ( * 5040 )
- NEW Metal2 ( 5177200 5040 ) ( 5178320 * )
- NEW Metal2 ( 5178320 3920 0 ) ( * 5040 )
- NEW Metal2 ( 5174960 3920 ) ( * 1571920 )
- NEW Metal2 ( 2715440 1690640 ) ( 2718800 * 0 )
- NEW Metal2 ( 2715440 1571920 ) ( * 1690640 )
- NEW Metal3 ( 2715440 1571920 ) ( 5174960 * )
- NEW Metal2 ( 5174960 1571920 ) Via2_VH
- NEW Metal2 ( 2715440 1571920 ) Via2_VH ;
- - la_data_in[54] ( PIN la_data_in[54] ) ( mprj la_data_in[54] ) + USE SIGNAL
- + ROUTED Metal2 ( 5225360 3920 ) ( 5234320 * )
- NEW Metal2 ( 5234320 3920 ) ( * 5040 )
- NEW Metal2 ( 5234320 5040 ) ( 5235440 * )
- NEW Metal2 ( 5235440 3920 0 ) ( * 5040 )
- NEW Metal2 ( 5225360 3920 ) ( * 1503600 )
- NEW Metal1 ( 2722160 1643600 ) ( 2732240 * )
- NEW Metal2 ( 2732240 1643600 ) ( * 1690640 )
- NEW Metal2 ( 2732240 1690640 ) ( 2735600 * 0 )
- NEW Metal2 ( 2722160 1503600 ) ( * 1643600 )
- NEW Metal3 ( 2722160 1503600 ) ( 5225360 * )
- NEW Metal2 ( 5225360 1503600 ) Via2_VH
- NEW Metal1 ( 2722160 1643600 ) Via1_HV
- NEW Metal1 ( 2732240 1643600 ) Via1_HV
- NEW Metal2 ( 2722160 1503600 ) Via2_VH ;
- - la_data_in[55] ( PIN la_data_in[55] ) ( mprj la_data_in[55] ) + USE SIGNAL
- + ROUTED Metal1 ( 2740080 1618960 ) ( 2749040 * )
- NEW Metal2 ( 2740080 361200 ) ( * 1618960 )
- NEW Metal3 ( 2740080 361200 ) ( 5292560 * )
- NEW Metal2 ( 5292560 3920 0 ) ( * 361200 )
- NEW Metal2 ( 2749040 1690640 ) ( 2752400 * 0 )
- NEW Metal2 ( 2749040 1618960 ) ( * 1690640 )
- NEW Metal1 ( 2740080 1618960 ) Via1_HV
- NEW Metal1 ( 2749040 1618960 ) Via1_HV
- NEW Metal2 ( 2740080 361200 ) Via2_VH
- NEW Metal2 ( 5292560 361200 ) Via2_VH ;
- - la_data_in[56] ( PIN la_data_in[56] ) ( mprj la_data_in[56] ) + USE SIGNAL
- + ROUTED Metal2 ( 5342960 3920 ) ( 5348560 * )
- NEW Metal2 ( 5348560 3920 ) ( * 5040 )
- NEW Metal2 ( 5348560 5040 ) ( 5349680 * )
- NEW Metal2 ( 5349680 3920 0 ) ( * 5040 )
- NEW Metal3 ( 2769200 1640240 ) ( 5342960 * )
- NEW Metal2 ( 5342960 3920 ) ( * 1640240 )
- NEW Metal2 ( 2769200 1640240 ) ( * 1690640 0 )
- NEW Metal2 ( 2769200 1640240 ) Via2_VH
- NEW Metal2 ( 5342960 1640240 ) Via2_VH ;
- - la_data_in[57] ( PIN la_data_in[57] ) ( mprj la_data_in[57] ) + USE SIGNAL
- + ROUTED Metal2 ( 5393360 3920 ) ( 5405680 * )
- NEW Metal2 ( 5405680 3920 ) ( * 5040 )
- NEW Metal2 ( 5405680 5040 ) ( 5406800 * )
- NEW Metal2 ( 5406800 3920 0 ) ( * 5040 )
- NEW Metal2 ( 5393360 3920 ) ( * 1520400 )
- NEW Metal2 ( 2773680 1652560 ) ( 2782640 * )
- NEW Metal2 ( 2773680 1520400 ) ( * 1652560 )
- NEW Metal3 ( 2773680 1520400 ) ( 5393360 * )
- NEW Metal2 ( 2782640 1690640 ) ( 2786000 * 0 )
- NEW Metal2 ( 2782640 1652560 ) ( * 1690640 )
- NEW Metal2 ( 5393360 1520400 ) Via2_VH
- NEW Metal2 ( 2773680 1520400 ) Via2_VH ;
- - la_data_in[58] ( PIN la_data_in[58] ) ( mprj la_data_in[58] ) + USE SIGNAL
- + ROUTED Metal2 ( 5460560 3920 ) ( 5462800 * )
- NEW Metal2 ( 5462800 3920 ) ( * 5040 )
- NEW Metal2 ( 5462800 5040 ) ( 5463920 * )
- NEW Metal2 ( 5463920 3920 0 ) ( * 5040 )
- NEW Metal2 ( 5460560 3920 ) ( * 1671600 )
- NEW Metal3 ( 2802800 1671600 ) ( 5460560 * )
- NEW Metal2 ( 2802800 1671600 ) ( * 1690640 0 )
- NEW Metal2 ( 2802800 1671600 ) Via2_VH
- NEW Metal2 ( 5460560 1671600 ) Via2_VH ;
- - la_data_in[59] ( PIN la_data_in[59] ) ( mprj la_data_in[59] ) + USE SIGNAL
- + ROUTED Metal2 ( 5510960 3920 ) ( 5519920 * )
- NEW Metal2 ( 5519920 3920 ) ( * 5040 )
- NEW Metal2 ( 5519920 5040 ) ( 5521040 * )
- NEW Metal2 ( 5521040 3920 0 ) ( * 5040 )
- NEW Metal3 ( 2816240 1554000 ) ( 5510960 * )
- NEW Metal2 ( 5510960 3920 ) ( * 1554000 )
- NEW Metal2 ( 2816240 1690640 ) ( 2819600 * 0 )
- NEW Metal2 ( 2816240 1554000 ) ( * 1690640 )
- NEW Metal2 ( 2816240 1554000 ) Via2_VH
- NEW Metal2 ( 5510960 1554000 ) Via2_VH ;
- - la_data_in[5] ( PIN la_data_in[5] ) ( mprj la_data_in[5] ) + USE SIGNAL
- + ROUTED Metal2 ( 2436560 3920 0 ) ( * 75600 )
- NEW Metal3 ( 1898960 75600 ) ( 2436560 * )
- NEW Metal3 ( 1898960 1621200 ) ( 1909040 * )
- NEW Metal2 ( 1898960 75600 ) ( * 1621200 )
- NEW Metal2 ( 1909040 1690640 ) ( 1912400 * 0 )
- NEW Metal2 ( 1909040 1621200 ) ( * 1690640 )
- NEW Metal2 ( 1898960 75600 ) Via2_VH
- NEW Metal2 ( 2436560 75600 ) Via2_VH
- NEW Metal2 ( 1898960 1621200 ) Via2_VH
- NEW Metal2 ( 1909040 1621200 ) Via2_VH ;
- - la_data_in[60] ( PIN la_data_in[60] ) ( mprj la_data_in[60] ) + USE SIGNAL
- + ROUTED Metal3 ( 2824080 1651440 ) ( 2833040 * )
- NEW Metal2 ( 2824080 1570800 ) ( * 1651440 )
- NEW Metal3 ( 2824080 1570800 ) ( 5578160 * )
- NEW Metal2 ( 5578160 3920 0 ) ( * 1570800 )
- NEW Metal2 ( 2833040 1690640 ) ( 2836400 * 0 )
- NEW Metal2 ( 2833040 1651440 ) ( * 1690640 )
- NEW Metal2 ( 2824080 1651440 ) Via2_VH
- NEW Metal2 ( 2833040 1651440 ) Via2_VH
- NEW Metal2 ( 2824080 1570800 ) Via2_VH
- NEW Metal2 ( 5578160 1570800 ) Via2_VH ;
- - la_data_in[61] ( PIN la_data_in[61] ) ( mprj la_data_in[61] ) + USE SIGNAL
- + ROUTED Metal2 ( 2840880 1660400 ) ( 2849840 * )
- NEW Metal2 ( 5635280 3920 0 ) ( * 45360 )
- NEW Metal2 ( 2840880 1524880 ) ( * 1660400 )
- NEW Metal2 ( 5014800 45360 ) ( * 1524880 )
- NEW Metal3 ( 5014800 45360 ) ( 5635280 * )
- NEW Metal3 ( 2840880 1524880 ) ( 5014800 * )
- NEW Metal2 ( 2849840 1690640 ) ( 2853200 * 0 )
- NEW Metal2 ( 2849840 1660400 ) ( * 1690640 )
- NEW Metal2 ( 5014800 45360 ) Via2_VH
- NEW Metal2 ( 5635280 45360 ) Via2_VH
- NEW Metal2 ( 2840880 1524880 ) Via2_VH
- NEW Metal2 ( 5014800 1524880 ) Via2_VH ;
- - la_data_in[62] ( PIN la_data_in[62] ) ( mprj la_data_in[62] ) + USE SIGNAL
- + ROUTED Metal3 ( 2857680 1645840 ) ( 2866640 * )
- NEW Metal2 ( 5678960 3920 ) ( 5691280 * )
- NEW Metal2 ( 5691280 3920 ) ( * 5040 )
- NEW Metal2 ( 5691280 5040 ) ( 5692400 * )
- NEW Metal2 ( 5692400 3920 0 ) ( * 5040 )
- NEW Metal2 ( 2857680 1537200 ) ( * 1645840 )
- NEW Metal2 ( 5678960 3920 ) ( * 1537200 )
- NEW Metal3 ( 2857680 1537200 ) ( 5678960 * )
- NEW Metal2 ( 2866640 1690640 ) ( 2870000 * 0 )
- NEW Metal2 ( 2866640 1645840 ) ( * 1690640 )
- NEW Metal2 ( 2857680 1645840 ) Via2_VH
- NEW Metal2 ( 2866640 1645840 ) Via2_VH
- NEW Metal2 ( 2857680 1537200 ) Via2_VH
- NEW Metal2 ( 5678960 1537200 ) Via2_VH ;
- - la_data_in[63] ( PIN la_data_in[63] ) ( mprj la_data_in[63] ) + USE SIGNAL
- + ROUTED Metal2 ( 5746160 3920 ) ( 5748400 * )
- NEW Metal2 ( 5748400 3920 ) ( * 5040 )
- NEW Metal2 ( 5748400 5040 ) ( 5749520 * )
- NEW Metal2 ( 5749520 3920 0 ) ( * 5040 )
- NEW Metal3 ( 2886800 1621200 ) ( 5746160 * )
- NEW Metal2 ( 5746160 3920 ) ( * 1621200 )
- NEW Metal2 ( 2886800 1621200 ) ( * 1690640 0 )
- NEW Metal2 ( 2886800 1621200 ) Via2_VH
- NEW Metal2 ( 5746160 1621200 ) Via2_VH ;
- - la_data_in[6] ( PIN la_data_in[6] ) ( mprj la_data_in[6] ) + USE SIGNAL
- + ROUTED Metal2 ( 1918000 546000 ) ( * 1495200 )
- NEW Metal2 ( 1918000 1495200 ) ( 1925840 * )
- NEW Metal2 ( 2488080 3920 ) ( 2492560 * )
- NEW Metal2 ( 2492560 3920 ) ( * 5040 )
- NEW Metal2 ( 2492560 5040 ) ( 2493680 * )
- NEW Metal2 ( 2493680 3920 0 ) ( * 5040 )
- NEW Metal3 ( 1918000 546000 ) ( 2488080 * )
- NEW Metal2 ( 2488080 3920 ) ( * 546000 )
- NEW Metal2 ( 1925840 1690640 ) ( 1929200 * 0 )
- NEW Metal2 ( 1925840 1495200 ) ( * 1690640 )
- NEW Metal2 ( 1918000 546000 ) Via2_VH
- NEW Metal2 ( 2488080 546000 ) Via2_VH ;
- - la_data_in[7] ( PIN la_data_in[7] ) ( mprj la_data_in[7] ) + USE SIGNAL
- + ROUTED Metal1 ( 1933680 1617840 ) ( 1942640 * )
- NEW Metal2 ( 1933680 111440 ) ( * 1617840 )
- NEW Metal3 ( 1933680 111440 ) ( 2550800 * )
- NEW Metal2 ( 2550800 3920 0 ) ( * 111440 )
- NEW Metal2 ( 1942640 1690640 ) ( 1946000 * 0 )
- NEW Metal2 ( 1942640 1617840 ) ( * 1690640 )
- NEW Metal1 ( 1933680 1617840 ) Via1_HV
- NEW Metal1 ( 1942640 1617840 ) Via1_HV
- NEW Metal2 ( 1933680 111440 ) Via2_VH
- NEW Metal2 ( 2550800 111440 ) Via2_VH ;
- - la_data_in[8] ( PIN la_data_in[8] ) ( mprj la_data_in[8] ) + USE SIGNAL
- + ROUTED Metal3 ( 1950480 1636880 ) ( 1959440 * )
- NEW Metal2 ( 1950480 109200 ) ( * 1636880 )
- NEW Metal2 ( 2607920 3920 0 ) ( * 109200 )
- NEW Metal3 ( 1950480 109200 ) ( 2607920 * )
- NEW Metal2 ( 1959440 1690640 ) ( 1962800 * 0 )
- NEW Metal2 ( 1959440 1636880 ) ( * 1690640 )
- NEW Metal2 ( 1950480 1636880 ) Via2_VH
- NEW Metal2 ( 1959440 1636880 ) Via2_VH
- NEW Metal2 ( 1950480 109200 ) Via2_VH
- NEW Metal2 ( 2607920 109200 ) Via2_VH ;
- - la_data_in[9] ( PIN la_data_in[9] ) ( mprj la_data_in[9] ) + USE SIGNAL
- + ROUTED Metal2 ( 2654960 3920 ) ( 2663920 * )
- NEW Metal2 ( 2663920 3920 ) ( * 5040 )
- NEW Metal2 ( 2663920 5040 ) ( 2665040 * )
- NEW Metal2 ( 2665040 3920 0 ) ( * 5040 )
- NEW Metal2 ( 2654960 3920 ) ( * 1503600 )
- NEW Metal2 ( 1976240 1690640 ) ( 1979600 * 0 )
- NEW Metal2 ( 1976240 1503600 ) ( * 1690640 )
- NEW Metal3 ( 1976240 1503600 ) ( 2654960 * )
- NEW Metal2 ( 2654960 1503600 ) Via2_VH
- NEW Metal2 ( 1976240 1503600 ) Via2_VH ;
- - la_data_out[0] ( PIN la_data_out[0] ) ( mprj la_data_out[0] ) + USE SIGNAL
- + ROUTED Metal2 ( 2171120 3920 0 ) ( * 462000 )
- NEW Metal3 ( 1834000 462000 ) ( 2171120 * )
- NEW Metal2 ( 1834000 462000 ) ( * 1495200 )
- NEW Metal2 ( 1834000 1495200 ) ( 1835120 * )
- NEW Metal2 ( 1834000 1680000 ) ( 1835120 * )
- NEW Metal2 ( 1834000 1680000 ) ( * 1690640 0 )
- NEW Metal4 ( 1835120 1587600 ) ( * 1623440 )
- NEW Metal2 ( 1835120 1495200 ) ( * 1587600 )
- NEW Metal2 ( 1835120 1623440 ) ( * 1680000 )
- NEW Metal2 ( 2171120 462000 ) Via2_VH
- NEW Metal2 ( 1834000 462000 ) Via2_VH
- NEW Metal2 ( 1835120 1587600 ) Via2_VH
- NEW Metal3 ( 1835120 1587600 ) Via3_HV
- NEW Metal2 ( 1835120 1623440 ) Via2_VH
- NEW Metal3 ( 1835120 1623440 ) Via3_HV
- NEW Metal3 ( 1835120 1587600 ) RECT ( -660 -280 0 280 )
- NEW Metal3 ( 1835120 1623440 ) RECT ( -660 -280 0 280 ) ;
- - la_data_out[10] ( PIN la_data_out[10] ) ( mprj la_data_out[10] ) + USE SIGNAL
- + ROUTED Metal2 ( 2000880 1651440 ) ( 2002000 * )
- NEW Metal2 ( 2000880 161840 ) ( * 1651440 )
- NEW Metal3 ( 2000880 161840 ) ( 2741200 * )
- NEW Metal2 ( 2741200 3920 0 ) ( * 161840 )
- NEW Metal2 ( 2002000 1651440 ) ( * 1690640 0 )
- NEW Metal2 ( 2000880 161840 ) Via2_VH
- NEW Metal2 ( 2741200 161840 ) Via2_VH ;
- - la_data_out[11] ( PIN la_data_out[11] ) ( mprj la_data_out[11] ) + USE SIGNAL
- + ROUTED Metal2 ( 2790480 3920 ) ( 2797200 * )
- NEW Metal2 ( 2797200 3920 ) ( * 5040 )
- NEW Metal2 ( 2797200 5040 ) ( 2798320 * )
- NEW Metal2 ( 2798320 3920 0 ) ( * 5040 )
- NEW Metal2 ( 2790480 3920 ) ( * 160720 )
- NEW Metal3 ( 2016560 160720 ) ( 2790480 * )
- NEW Metal2 ( 2016560 1690640 ) ( 2018800 * 0 )
- NEW Metal2 ( 2016560 160720 ) ( * 1690640 )
- NEW Metal2 ( 2790480 160720 ) Via2_VH
- NEW Metal2 ( 2016560 160720 ) Via2_VH ;
- - la_data_out[12] ( PIN la_data_out[12] ) ( mprj la_data_out[12] ) + USE SIGNAL
- + ROUTED Metal2 ( 2175600 1369200 ) ( * 1659280 )
- NEW Metal2 ( 2857680 3920 0 ) ( * 1369200 )
- NEW Metal3 ( 2035600 1659280 ) ( 2175600 * )
- NEW Metal3 ( 2175600 1369200 ) ( 2857680 * )
- NEW Metal2 ( 2035600 1659280 ) ( * 1690640 0 )
- NEW Metal2 ( 2175600 1659280 ) Via2_VH
- NEW Metal2 ( 2175600 1369200 ) Via2_VH
- NEW Metal2 ( 2857680 1369200 ) Via2_VH
- NEW Metal2 ( 2035600 1659280 ) Via2_VH ;
- - la_data_out[13] ( PIN la_data_out[13] ) ( mprj la_data_out[13] ) + USE SIGNAL
- + ROUTED Metal2 ( 2906960 3920 ) ( 2911440 * )
- NEW Metal2 ( 2911440 3920 ) ( * 5040 )
- NEW Metal2 ( 2911440 5040 ) ( 2912560 * )
- NEW Metal2 ( 2912560 3920 0 ) ( * 5040 )
- NEW Metal3 ( 2052400 195440 ) ( 2906960 * )
- NEW Metal2 ( 2906960 3920 ) ( * 195440 )
- NEW Metal2 ( 2052400 195440 ) ( * 1690640 0 )
- NEW Metal2 ( 2052400 195440 ) Via2_VH
- NEW Metal2 ( 2906960 195440 ) Via2_VH ;
- - la_data_out[14] ( PIN la_data_out[14] ) ( mprj la_data_out[14] ) + USE SIGNAL
- + ROUTED Metal2 ( 2957360 3920 ) ( 2968560 * )
- NEW Metal2 ( 2968560 3920 ) ( * 5040 )
- NEW Metal2 ( 2968560 5040 ) ( 2969680 * )
- NEW Metal2 ( 2969680 3920 0 ) ( * 5040 )
- NEW Metal3 ( 2066960 145040 ) ( 2957360 * )
- NEW Metal2 ( 2957360 3920 ) ( * 145040 )
- NEW Metal2 ( 2066960 1690640 ) ( 2069200 * 0 )
- NEW Metal2 ( 2066960 145040 ) ( * 1690640 )
- NEW Metal2 ( 2066960 145040 ) Via2_VH
- NEW Metal2 ( 2957360 145040 ) Via2_VH ;
- - la_data_out[15] ( PIN la_data_out[15] ) ( mprj la_data_out[15] ) + USE SIGNAL
- + ROUTED Metal2 ( 2084880 1651440 ) ( 2086000 * )
- NEW Metal2 ( 2084880 278320 ) ( * 1651440 )
- NEW Metal2 ( 3024560 201600 ) ( * 278320 )
- NEW Metal2 ( 3024560 201600 ) ( 3026800 * )
- NEW Metal2 ( 3026800 3920 0 ) ( * 201600 )
- NEW Metal3 ( 2084880 278320 ) ( 3024560 * )
- NEW Metal2 ( 2086000 1651440 ) ( * 1690640 0 )
- NEW Metal2 ( 2084880 278320 ) Via2_VH
- NEW Metal2 ( 3024560 278320 ) Via2_VH ;
- - la_data_out[16] ( PIN la_data_out[16] ) ( mprj la_data_out[16] ) + USE SIGNAL
- + ROUTED Metal2 ( 3074960 3920 ) ( 3082800 * )
- NEW Metal2 ( 3082800 3920 ) ( * 5040 )
- NEW Metal2 ( 3082800 5040 ) ( 3083920 * )
- NEW Metal2 ( 3083920 3920 0 ) ( * 5040 )
- NEW Metal2 ( 3074960 3920 ) ( * 1542800 )
- NEW Metal2 ( 2102800 1542800 ) ( * 1690640 0 )
- NEW Metal3 ( 2102800 1542800 ) ( 3074960 * )
- NEW Metal2 ( 2102800 1542800 ) Via2_VH
- NEW Metal2 ( 3074960 1542800 ) Via2_VH ;
- - la_data_out[17] ( PIN la_data_out[17] ) ( mprj la_data_out[17] ) + USE SIGNAL
- + ROUTED Metal2 ( 2118480 1650320 ) ( 2120720 * )
- NEW Metal2 ( 2118480 76720 ) ( * 1650320 )
- NEW Metal2 ( 3142160 3920 0 ) ( * 76720 )
- NEW Metal3 ( 2118480 76720 ) ( 3142160 * )
- NEW Metal2 ( 2120720 1650320 ) ( * 1680000 )
- NEW Metal2 ( 2119600 1680000 ) ( 2120720 * )
- NEW Metal2 ( 2119600 1680000 ) ( * 1690640 0 )
- NEW Metal2 ( 2118480 76720 ) Via2_VH
- NEW Metal2 ( 3142160 76720 ) Via2_VH ;
- - la_data_out[18] ( PIN la_data_out[18] ) ( mprj la_data_out[18] ) + USE SIGNAL
- + ROUTED Metal2 ( 2136400 1614480 ) ( 2137520 * )
- NEW Metal2 ( 2137520 201600 ) ( 2140880 * )
- NEW Metal2 ( 2140880 1680 ) ( * 201600 )
- NEW Metal2 ( 2137520 201600 ) ( * 1614480 )
- NEW Metal2 ( 3197040 1680 ) ( * 5040 )
- NEW Metal2 ( 3197040 5040 ) ( 3198160 * )
- NEW Metal2 ( 3198160 3920 0 ) ( * 5040 )
- NEW Metal3 ( 2140880 1680 ) ( 3197040 * )
- NEW Metal2 ( 2136400 1614480 ) ( * 1690640 0 )
- NEW Metal2 ( 2140880 1680 ) Via2_VH
- NEW Metal2 ( 3197040 1680 ) Via2_VH ;
- - la_data_out[19] ( PIN la_data_out[19] ) ( mprj la_data_out[19] ) + USE SIGNAL
- + ROUTED Metal2 ( 2152080 1651440 ) ( 2153200 * )
- NEW Metal2 ( 2152080 596400 ) ( * 1651440 )
- NEW Metal2 ( 3242960 3920 ) ( 3254160 * )
- NEW Metal2 ( 3254160 3920 ) ( * 5040 )
- NEW Metal2 ( 3254160 5040 ) ( 3255280 * )
- NEW Metal2 ( 3255280 3920 0 ) ( * 5040 )
- NEW Metal3 ( 2152080 596400 ) ( 3242960 * )
- NEW Metal2 ( 3242960 3920 ) ( * 596400 )
- NEW Metal2 ( 2153200 1651440 ) ( * 1690640 0 )
- NEW Metal2 ( 2152080 596400 ) Via2_VH
- NEW Metal2 ( 3242960 596400 ) Via2_VH ;
- - la_data_out[1] ( PIN la_data_out[1] ) ( mprj la_data_out[1] ) + USE SIGNAL
- + ROUTED Metal3 ( 1848560 110320 ) ( 2227120 * )
- NEW Metal2 ( 2227120 3920 0 ) ( * 110320 )
- NEW Metal2 ( 1848560 1690640 ) ( 1850800 * 0 )
- NEW Metal2 ( 1848560 110320 ) ( * 1690640 )
- NEW Metal2 ( 1848560 110320 ) Via2_VH
- NEW Metal2 ( 2227120 110320 ) Via2_VH ;
- - la_data_out[20] ( PIN la_data_out[20] ) ( mprj la_data_out[20] ) + USE SIGNAL
- + ROUTED Metal2 ( 2168880 1650320 ) ( 2171120 * )
- NEW Metal2 ( 2168880 194320 ) ( * 1650320 )
- NEW Metal2 ( 3312400 3920 0 ) ( * 194320 )
- NEW Metal3 ( 2168880 194320 ) ( 3312400 * )
- NEW Metal2 ( 2171120 1650320 ) ( * 1680000 )
- NEW Metal2 ( 2170000 1680000 ) ( 2171120 * )
- NEW Metal2 ( 2170000 1680000 ) ( * 1690640 0 )
- NEW Metal2 ( 2168880 194320 ) Via2_VH
- NEW Metal2 ( 3312400 194320 ) Via2_VH ;
- - la_data_out[21] ( PIN la_data_out[21] ) ( mprj la_data_out[21] ) + USE SIGNAL
- + ROUTED Metal2 ( 2185680 1651440 ) ( 2186800 * )
- NEW Metal2 ( 3360560 3920 ) ( 3368400 * )
- NEW Metal2 ( 3368400 3920 ) ( * 5040 )
- NEW Metal2 ( 3368400 5040 ) ( 3369520 * )
- NEW Metal2 ( 3369520 3920 0 ) ( * 5040 )
- NEW Metal2 ( 2185680 999600 ) ( * 1651440 )
- NEW Metal2 ( 3360560 3920 ) ( * 999600 )
- NEW Metal3 ( 2185680 999600 ) ( 3360560 * )
- NEW Metal2 ( 2186800 1651440 ) ( * 1690640 0 )
- NEW Metal2 ( 2185680 999600 ) Via2_VH
- NEW Metal2 ( 3360560 999600 ) Via2_VH ;
- - la_data_out[22] ( PIN la_data_out[22] ) ( mprj la_data_out[22] ) + USE SIGNAL
- + ROUTED Metal3 ( 2233840 1662640 ) ( * 1666000 )
- NEW Metal3 ( 2203600 1662640 ) ( 2233840 * )
- NEW Metal2 ( 3427760 3920 0 ) ( * 1666000 )
- NEW Metal3 ( 2233840 1666000 ) ( 3427760 * )
- NEW Metal2 ( 2203600 1662640 ) ( * 1690640 0 )
- NEW Metal2 ( 2203600 1662640 ) Via2_VH
- NEW Metal2 ( 3427760 1666000 ) Via2_VH ;
- - la_data_out[23] ( PIN la_data_out[23] ) ( mprj la_data_out[23] ) + USE SIGNAL
- + ROUTED Metal2 ( 2219280 1651440 ) ( 2220400 * )
- NEW Metal2 ( 3478160 3920 ) ( 3482640 * )
- NEW Metal2 ( 3482640 3920 ) ( * 5040 )
- NEW Metal2 ( 3482640 5040 ) ( 3483760 * )
- NEW Metal2 ( 3483760 3920 0 ) ( * 5040 )
- NEW Metal2 ( 2220400 1508080 ) ( * 1651440 )
- NEW Metal2 ( 3478160 3920 ) ( * 1508080 )
- NEW Metal2 ( 2219280 1651440 ) ( * 1680000 )
- NEW Metal2 ( 2219280 1680000 ) ( 2220400 * )
- NEW Metal2 ( 2220400 1680000 ) ( * 1690640 0 )
- NEW Metal3 ( 2220400 1508080 ) ( 3478160 * )
- NEW Metal2 ( 2220400 1508080 ) Via2_VH
- NEW Metal2 ( 3478160 1508080 ) Via2_VH ;
- - la_data_out[24] ( PIN la_data_out[24] ) ( mprj la_data_out[24] ) + USE SIGNAL
- + ROUTED Metal2 ( 3528560 3920 ) ( 3539760 * )
- NEW Metal2 ( 3539760 3920 ) ( * 5040 )
- NEW Metal2 ( 3539760 5040 ) ( 3540880 * )
- NEW Metal2 ( 3540880 3920 0 ) ( * 5040 )
- NEW Metal2 ( 3528560 3920 ) ( * 1541680 )
- NEW Metal3 ( 2237200 1662640 ) ( 2343600 * )
- NEW Metal2 ( 2343600 1541680 ) ( * 1662640 )
- NEW Metal2 ( 2237200 1662640 ) ( * 1690640 0 )
- NEW Metal3 ( 2343600 1541680 ) ( 3528560 * )
- NEW Metal2 ( 2343600 1541680 ) Via2_VH
- NEW Metal2 ( 3528560 1541680 ) Via2_VH
- NEW Metal2 ( 2237200 1662640 ) Via2_VH
- NEW Metal2 ( 2343600 1662640 ) Via2_VH ;
- - la_data_out[25] ( PIN la_data_out[25] ) ( mprj la_data_out[25] ) + USE SIGNAL
- + ROUTED Metal2 ( 3595760 201600 ) ( 3598000 * )
- NEW Metal2 ( 3598000 3920 0 ) ( * 201600 )
- NEW Metal2 ( 3595760 201600 ) ( * 1526000 )
- NEW Metal2 ( 2252880 1526000 ) ( * 1680000 )
- NEW Metal2 ( 2252880 1680000 ) ( 2254000 * )
- NEW Metal2 ( 2254000 1680000 ) ( * 1690640 0 )
- NEW Metal3 ( 2252880 1526000 ) ( 3595760 * )
- NEW Metal2 ( 3595760 1526000 ) Via2_VH
- NEW Metal2 ( 2252880 1526000 ) Via2_VH ;
- - la_data_out[26] ( PIN la_data_out[26] ) ( mprj la_data_out[26] ) + USE SIGNAL
- + ROUTED Metal3 ( 3620400 40880 ) ( 3655120 * )
- NEW Metal2 ( 3655120 3920 0 ) ( * 40880 )
- NEW Metal2 ( 3620400 40880 ) ( * 1506960 )
- NEW Metal2 ( 2270800 1680000 ) ( 2271920 * )
- NEW Metal2 ( 2270800 1680000 ) ( * 1690640 0 )
- NEW Metal3 ( 2271920 1506960 ) ( 3620400 * )
- NEW Metal4 ( 2271920 1564080 ) ( * 1623440 )
- NEW Metal2 ( 2271920 1506960 ) ( * 1564080 )
- NEW Metal2 ( 2271920 1623440 ) ( * 1680000 )
- NEW Metal2 ( 3620400 40880 ) Via2_VH
- NEW Metal2 ( 3655120 40880 ) Via2_VH
- NEW Metal2 ( 2271920 1506960 ) Via2_VH
- NEW Metal2 ( 3620400 1506960 ) Via2_VH
- NEW Metal2 ( 2271920 1564080 ) Via2_VH
- NEW Metal3 ( 2271920 1564080 ) Via3_HV
- NEW Metal2 ( 2271920 1623440 ) Via2_VH
- NEW Metal3 ( 2271920 1623440 ) Via3_HV
- NEW Metal3 ( 2271920 1564080 ) RECT ( -660 -280 0 280 )
- NEW Metal3 ( 2271920 1623440 ) RECT ( -660 -280 0 280 ) ;
- - la_data_out[27] ( PIN la_data_out[27] ) ( mprj la_data_out[27] ) + USE SIGNAL
- + ROUTED Metal2 ( 3713360 3920 0 ) ( * 1491280 )
- NEW Metal2 ( 2286480 1491280 ) ( * 1680000 )
- NEW Metal2 ( 2286480 1680000 ) ( 2287600 * )
- NEW Metal2 ( 2287600 1680000 ) ( * 1690640 0 )
- NEW Metal3 ( 2286480 1491280 ) ( 3713360 * )
- NEW Metal2 ( 2286480 1491280 ) Via2_VH
- NEW Metal2 ( 3713360 1491280 ) Via2_VH ;
- - la_data_out[28] ( PIN la_data_out[28] ) ( mprj la_data_out[28] ) + USE SIGNAL
- + ROUTED Metal2 ( 3763760 3920 ) ( 3768240 * )
- NEW Metal2 ( 3768240 3920 ) ( * 5040 )
- NEW Metal2 ( 3768240 5040 ) ( 3769360 * )
- NEW Metal2 ( 3769360 3920 0 ) ( * 5040 )
- NEW Metal2 ( 3763760 3920 ) ( * 1490160 )
- NEW Metal2 ( 2304400 1490160 ) ( * 1495200 )
- NEW Metal2 ( 2304400 1495200 ) ( 2305520 * )
- NEW Metal2 ( 2304400 1680000 ) ( 2305520 * )
- NEW Metal2 ( 2304400 1680000 ) ( * 1690640 0 )
- NEW Metal3 ( 2304400 1490160 ) ( 3763760 * )
- NEW Metal4 ( 2305520 1564080 ) ( * 1623440 )
- NEW Metal2 ( 2305520 1495200 ) ( * 1564080 )
- NEW Metal2 ( 2305520 1623440 ) ( * 1680000 )
- NEW Metal2 ( 3763760 1490160 ) Via2_VH
- NEW Metal2 ( 2304400 1490160 ) Via2_VH
- NEW Metal2 ( 2305520 1564080 ) Via2_VH
- NEW Metal3 ( 2305520 1564080 ) Via3_HV
- NEW Metal2 ( 2305520 1623440 ) Via2_VH
- NEW Metal3 ( 2305520 1623440 ) Via3_HV
- NEW Metal3 ( 2305520 1564080 ) RECT ( -660 -280 0 280 )
- NEW Metal3 ( 2305520 1623440 ) RECT ( -660 -280 0 280 ) ;
- - la_data_out[29] ( PIN la_data_out[29] ) ( mprj la_data_out[29] ) + USE SIGNAL
- + ROUTED Metal2 ( 3814160 3920 ) ( 3825360 * )
- NEW Metal2 ( 3825360 3920 ) ( * 5040 )
- NEW Metal2 ( 3825360 5040 ) ( 3826480 * )
- NEW Metal2 ( 3826480 3920 0 ) ( * 5040 )
- NEW Metal2 ( 3814160 3920 ) ( * 1674960 )
- NEW Metal2 ( 2321200 1674960 ) ( * 1690640 0 )
- NEW Metal3 ( 2321200 1674960 ) ( 3814160 * )
- NEW Metal2 ( 3814160 1674960 ) Via2_VH
- NEW Metal2 ( 2321200 1674960 ) Via2_VH ;
- - la_data_out[2] ( PIN la_data_out[2] ) ( mprj la_data_out[2] ) + USE SIGNAL
- + ROUTED Metal2 ( 1866480 1470000 ) ( * 1495200 )
- NEW Metal2 ( 1866480 1495200 ) ( 1867600 * )
- NEW Metal3 ( 1866480 1470000 ) ( 2286480 * )
- NEW Metal2 ( 2286480 3920 0 ) ( * 1470000 )
- NEW Metal2 ( 1867600 1495200 ) ( * 1690640 0 )
- NEW Metal2 ( 1866480 1470000 ) Via2_VH
- NEW Metal2 ( 2286480 1470000 ) Via2_VH ;
- - la_data_out[30] ( PIN la_data_out[30] ) ( mprj la_data_out[30] ) + USE SIGNAL
- + ROUTED Metal2 ( 3881360 201600 ) ( 3883600 * )
- NEW Metal2 ( 3883600 3920 0 ) ( * 201600 )
- NEW Metal2 ( 3881360 201600 ) ( * 1505840 )
- NEW Metal2 ( 2336880 1505840 ) ( * 1562400 )
- NEW Metal2 ( 2336880 1562400 ) ( 2339120 * )
- NEW Metal2 ( 2339120 1562400 ) ( * 1680000 )
- NEW Metal2 ( 2338000 1680000 ) ( 2339120 * )
- NEW Metal2 ( 2338000 1680000 ) ( * 1690640 0 )
- NEW Metal3 ( 2336880 1505840 ) ( 3881360 * )
- NEW Metal2 ( 2336880 1505840 ) Via2_VH
- NEW Metal2 ( 3881360 1505840 ) Via2_VH ;
- - la_data_out[31] ( PIN la_data_out[31] ) ( mprj la_data_out[31] ) + USE SIGNAL
- + ROUTED Metal2 ( 3931760 3920 ) ( 3939600 * )
- NEW Metal2 ( 3939600 3920 ) ( * 5040 )
- NEW Metal2 ( 3939600 5040 ) ( 3940720 * )
- NEW Metal2 ( 3940720 3920 0 ) ( * 5040 )
- NEW Metal2 ( 3931760 3920 ) ( * 1475600 )
- NEW Metal2 ( 2353680 1623440 ) ( 2355920 * )
- NEW Metal2 ( 2353680 1475600 ) ( * 1623440 )
- NEW Metal2 ( 2355920 1623440 ) ( * 1680000 )
- NEW Metal2 ( 2354800 1680000 ) ( 2355920 * )
- NEW Metal2 ( 2354800 1680000 ) ( * 1690640 0 )
- NEW Metal3 ( 2353680 1475600 ) ( 3931760 * )
- NEW Metal2 ( 2353680 1475600 ) Via2_VH
- NEW Metal2 ( 3931760 1475600 ) Via2_VH ;
- - la_data_out[32] ( PIN la_data_out[32] ) ( mprj la_data_out[32] ) + USE SIGNAL
- + ROUTED Metal3 ( 3990000 40880 ) ( 3998960 * )
- NEW Metal2 ( 3998960 3920 0 ) ( * 40880 )
- NEW Metal2 ( 3990000 40880 ) ( * 1540560 )
- NEW Metal2 ( 2371600 1690640 0 ) ( 2374960 * )
- NEW Metal2 ( 2374960 1540560 ) ( * 1690640 )
- NEW Metal3 ( 2374960 1540560 ) ( 3990000 * )
- NEW Metal2 ( 3990000 40880 ) Via2_VH
- NEW Metal2 ( 3998960 40880 ) Via2_VH
- NEW Metal2 ( 2374960 1540560 ) Via2_VH
- NEW Metal2 ( 3990000 1540560 ) Via2_VH ;
- - la_data_out[33] ( PIN la_data_out[33] ) ( mprj la_data_out[33] ) + USE SIGNAL
- + ROUTED Metal3 ( 4023600 40880 ) ( 4054960 * )
- NEW Metal2 ( 4054960 3920 0 ) ( * 40880 )
- NEW Metal2 ( 4023600 40880 ) ( * 1673840 )
- NEW Metal2 ( 2388400 1673840 ) ( * 1690640 0 )
- NEW Metal3 ( 2388400 1673840 ) ( 4023600 * )
- NEW Metal2 ( 4023600 40880 ) Via2_VH
- NEW Metal2 ( 4054960 40880 ) Via2_VH
- NEW Metal2 ( 4023600 1673840 ) Via2_VH
- NEW Metal2 ( 2388400 1673840 ) Via2_VH ;
- - la_data_out[34] ( PIN la_data_out[34] ) ( mprj la_data_out[34] ) + USE SIGNAL
- + ROUTED Metal2 ( 2405200 1691760 0 ) ( 2408560 * )
- NEW Metal2 ( 4099760 3920 ) ( 4110960 * )
- NEW Metal2 ( 4110960 3920 ) ( * 5040 )
- NEW Metal2 ( 4110960 5040 ) ( 4112080 * )
- NEW Metal2 ( 4112080 3920 0 ) ( * 5040 )
- NEW Metal2 ( 4099760 3920 ) ( * 1474480 )
- NEW Metal2 ( 2408560 1474480 ) ( * 1691760 )
- NEW Metal3 ( 2408560 1474480 ) ( 4099760 * )
- NEW Metal2 ( 4099760 1474480 ) Via2_VH
- NEW Metal2 ( 2408560 1474480 ) Via2_VH ;
- - la_data_out[35] ( PIN la_data_out[35] ) ( mprj la_data_out[35] ) + USE SIGNAL
- + ROUTED Metal3 ( 2511600 1489040 ) ( 4166960 * )
- NEW Metal2 ( 4166960 201600 ) ( 4169200 * )
- NEW Metal2 ( 4169200 3920 0 ) ( * 201600 )
- NEW Metal2 ( 4166960 201600 ) ( * 1489040 )
- NEW Metal2 ( 2511600 1489040 ) ( * 1659280 )
- NEW Metal2 ( 2422000 1659280 ) ( * 1690640 0 )
- NEW Metal3 ( 2422000 1659280 ) ( 2511600 * )
- NEW Metal2 ( 2511600 1489040 ) Via2_VH
- NEW Metal2 ( 4166960 1489040 ) Via2_VH
- NEW Metal2 ( 2511600 1659280 ) Via2_VH
- NEW Metal2 ( 2422000 1659280 ) Via2_VH ;
- - la_data_out[36] ( PIN la_data_out[36] ) ( mprj la_data_out[36] ) + USE SIGNAL
- + ROUTED Metal2 ( 4217360 3920 ) ( 4225200 * )
- NEW Metal2 ( 4225200 3920 ) ( * 5040 )
- NEW Metal2 ( 4225200 5040 ) ( 4226320 * )
- NEW Metal2 ( 4226320 3920 0 ) ( * 5040 )
- NEW Metal2 ( 4217360 3920 ) ( * 411600 )
- NEW Metal2 ( 2438800 1691760 0 ) ( 2442160 * )
- NEW Metal3 ( 2437680 411600 ) ( 4217360 * )
- NEW Metal2 ( 2437680 411600 ) ( * 1444800 )
- NEW Metal2 ( 2437680 1444800 ) ( 2442160 * )
- NEW Metal2 ( 2442160 1444800 ) ( * 1691760 )
- NEW Metal2 ( 4217360 411600 ) Via2_VH
- NEW Metal2 ( 2437680 411600 ) Via2_VH ;
- - la_data_out[37] ( PIN la_data_out[37] ) ( mprj la_data_out[37] ) + USE SIGNAL
- + ROUTED Metal2 ( 4284560 3920 0 ) ( * 1456560 )
- NEW Metal2 ( 2454480 1623440 ) ( 2455600 * )
- NEW Metal2 ( 2455600 1623440 ) ( * 1690640 0 )
- NEW Metal2 ( 2454480 1456560 ) ( * 1623440 )
- NEW Metal3 ( 2454480 1456560 ) ( 4284560 * )
- NEW Metal2 ( 4284560 1456560 ) Via2_VH
- NEW Metal2 ( 2454480 1456560 ) Via2_VH ;
- - la_data_out[38] ( PIN la_data_out[38] ) ( mprj la_data_out[38] ) + USE SIGNAL
- + ROUTED Metal2 ( 4334960 3920 ) ( 4339440 * )
- NEW Metal2 ( 4339440 3920 ) ( * 5040 )
- NEW Metal2 ( 4339440 5040 ) ( 4340560 * )
- NEW Metal2 ( 4340560 3920 0 ) ( * 5040 )
- NEW Metal2 ( 4334960 3920 ) ( * 1455440 )
- NEW Metal3 ( 2473520 1455440 ) ( 4334960 * )
- NEW Metal1 ( 2472400 1623440 ) ( * 1627920 )
- NEW Metal1 ( 2472400 1623440 ) ( 2473520 * )
- NEW Metal2 ( 2472400 1627920 ) ( * 1690640 0 )
- NEW Metal2 ( 2473520 1455440 ) ( * 1623440 )
- NEW Metal2 ( 4334960 1455440 ) Via2_VH
- NEW Metal2 ( 2473520 1455440 ) Via2_VH
- NEW Metal1 ( 2472400 1627920 ) Via1_HV
- NEW Metal1 ( 2473520 1623440 ) Via1_HV ;
- - la_data_out[39] ( PIN la_data_out[39] ) ( mprj la_data_out[39] ) + USE SIGNAL
- + ROUTED Metal2 ( 2489200 1691760 0 ) ( 2492560 * )
- NEW Metal2 ( 4385360 3920 ) ( 4396560 * )
- NEW Metal2 ( 4396560 3920 ) ( * 5040 )
- NEW Metal2 ( 4396560 5040 ) ( 4397680 * )
- NEW Metal2 ( 4397680 3920 0 ) ( * 5040 )
- NEW Metal2 ( 4385360 3920 ) ( * 1473360 )
- NEW Metal2 ( 2492560 1473360 ) ( * 1691760 )
- NEW Metal3 ( 2492560 1473360 ) ( 4385360 * )
- NEW Metal2 ( 4385360 1473360 ) Via2_VH
- NEW Metal2 ( 2492560 1473360 ) Via2_VH ;
- - la_data_out[3] ( PIN la_data_out[3] ) ( mprj la_data_out[3] ) + USE SIGNAL
- + ROUTED Metal2 ( 1883280 92400 ) ( * 1495200 )
- NEW Metal2 ( 1883280 1495200 ) ( 1884400 * )
- NEW Metal2 ( 2341360 3920 0 ) ( * 92400 )
- NEW Metal3 ( 1883280 92400 ) ( 2341360 * )
- NEW Metal2 ( 1884400 1495200 ) ( * 1690640 0 )
- NEW Metal2 ( 1883280 92400 ) Via2_VH
- NEW Metal2 ( 2341360 92400 ) Via2_VH ;
- - la_data_out[40] ( PIN la_data_out[40] ) ( mprj la_data_out[40] ) + USE SIGNAL
- + ROUTED Metal2 ( 4452560 201600 ) ( 4454800 * )
- NEW Metal2 ( 4454800 3920 0 ) ( * 201600 )
- NEW Metal2 ( 4452560 201600 ) ( * 1440880 )
- NEW Metal3 ( 2504880 1440880 ) ( 4452560 * )
- NEW Metal2 ( 2504880 1623440 ) ( 2507120 * )
- NEW Metal2 ( 2504880 1440880 ) ( * 1623440 )
- NEW Metal2 ( 2507120 1623440 ) ( * 1680000 )
- NEW Metal2 ( 2506000 1680000 ) ( 2507120 * )
- NEW Metal2 ( 2506000 1680000 ) ( * 1690640 0 )
- NEW Metal2 ( 4452560 1440880 ) Via2_VH
- NEW Metal2 ( 2504880 1440880 ) Via2_VH ;
- - la_data_out[41] ( PIN la_data_out[41] ) ( mprj la_data_out[41] ) + USE SIGNAL
- + ROUTED Metal2 ( 4502960 3920 ) ( 4510800 * )
- NEW Metal2 ( 4510800 3920 ) ( * 5040 )
- NEW Metal2 ( 4510800 5040 ) ( 4511920 * )
- NEW Metal2 ( 4511920 3920 0 ) ( * 5040 )
- NEW Metal2 ( 4502960 3920 ) ( * 1487920 )
- NEW Metal3 ( 2521680 1487920 ) ( 4502960 * )
- NEW Metal2 ( 2521680 1487920 ) ( * 1562400 )
- NEW Metal2 ( 2521680 1562400 ) ( 2526160 * )
- NEW Metal2 ( 2522800 1690640 0 ) ( 2526160 * )
- NEW Metal2 ( 2526160 1562400 ) ( * 1690640 )
- NEW Metal2 ( 4502960 1487920 ) Via2_VH
- NEW Metal2 ( 2521680 1487920 ) Via2_VH ;
- - la_data_out[42] ( PIN la_data_out[42] ) ( mprj la_data_out[42] ) + USE SIGNAL
- + ROUTED Metal3 ( 2538480 1471120 ) ( 4570160 * )
- NEW Metal2 ( 4570160 3920 0 ) ( * 1471120 )
- NEW Metal2 ( 2538480 1471120 ) ( * 1562400 )
- NEW Metal2 ( 2538480 1562400 ) ( 2542960 * )
- NEW Metal2 ( 2539600 1690640 0 ) ( 2542960 * )
- NEW Metal2 ( 2542960 1562400 ) ( * 1690640 )
- NEW Metal2 ( 2538480 1471120 ) Via2_VH
- NEW Metal2 ( 4570160 1471120 ) Via2_VH ;
- - la_data_out[43] ( PIN la_data_out[43] ) ( mprj la_data_out[43] ) + USE SIGNAL
- + ROUTED Metal2 ( 4620560 3920 ) ( 4625040 * )
- NEW Metal2 ( 4625040 3920 ) ( * 5040 )
- NEW Metal2 ( 4625040 5040 ) ( 4626160 * )
- NEW Metal2 ( 4626160 3920 0 ) ( * 5040 )
- NEW Metal3 ( 2555280 1439760 ) ( 4620560 * )
- NEW Metal2 ( 4620560 3920 ) ( * 1439760 )
- NEW Metal2 ( 2555280 1439760 ) ( * 1562400 )
- NEW Metal2 ( 2555280 1562400 ) ( 2559760 * )
- NEW Metal2 ( 2556400 1690640 0 ) ( 2559760 * )
- NEW Metal2 ( 2559760 1562400 ) ( * 1690640 )
- NEW Metal2 ( 2555280 1439760 ) Via2_VH
- NEW Metal2 ( 4620560 1439760 ) Via2_VH ;
- - la_data_out[44] ( PIN la_data_out[44] ) ( mprj la_data_out[44] ) + USE SIGNAL
- + ROUTED Metal2 ( 4670960 3920 ) ( 4682160 * )
- NEW Metal2 ( 4682160 3920 ) ( * 5040 )
- NEW Metal2 ( 4682160 5040 ) ( 4683280 * )
- NEW Metal2 ( 4683280 3920 0 ) ( * 5040 )
- NEW Metal2 ( 4670960 3920 ) ( * 1664880 )
- NEW Metal3 ( 2573200 1662640 ) ( 2587760 * )
- NEW Metal2 ( 2587760 1662640 ) ( * 1664880 )
- NEW Metal3 ( 2587760 1664880 ) ( 4670960 * )
- NEW Metal2 ( 2573200 1662640 ) ( * 1690640 0 )
- NEW Metal2 ( 4670960 1664880 ) Via2_VH
- NEW Metal2 ( 2573200 1662640 ) Via2_VH
- NEW Metal2 ( 2587760 1662640 ) Via2_VH
- NEW Metal2 ( 2587760 1664880 ) Via2_VH ;
- - la_data_out[45] ( PIN la_data_out[45] ) ( mprj la_data_out[45] ) + USE SIGNAL
- + ROUTED Metal2 ( 2590000 445200 ) ( * 1495200 )
- NEW Metal2 ( 2590000 1495200 ) ( 2593360 * )
- NEW Metal2 ( 4738160 201600 ) ( 4740400 * )
- NEW Metal2 ( 4740400 3920 0 ) ( * 201600 )
- NEW Metal2 ( 4738160 201600 ) ( * 445200 )
- NEW Metal3 ( 2590000 445200 ) ( 4738160 * )
- NEW Metal2 ( 2590000 1690640 0 ) ( 2593360 * )
- NEW Metal2 ( 2593360 1495200 ) ( * 1690640 )
- NEW Metal2 ( 2590000 445200 ) Via2_VH
- NEW Metal2 ( 4738160 445200 ) Via2_VH ;
- - la_data_out[46] ( PIN la_data_out[46] ) ( mprj la_data_out[46] ) + USE SIGNAL
- + ROUTED Metal2 ( 2744560 1622320 ) ( * 1657040 )
- NEW Metal2 ( 4788560 3920 ) ( 4796400 * )
- NEW Metal2 ( 4796400 3920 ) ( * 5040 )
- NEW Metal2 ( 4796400 5040 ) ( 4797520 * )
- NEW Metal2 ( 4797520 3920 0 ) ( * 5040 )
- NEW Metal3 ( 2744560 1622320 ) ( 4788560 * )
- NEW Metal2 ( 4788560 3920 ) ( * 1622320 )
- NEW Metal3 ( 2606800 1657040 ) ( 2744560 * )
- NEW Metal2 ( 2606800 1657040 ) ( * 1690640 0 )
- NEW Metal2 ( 2744560 1657040 ) Via2_VH
- NEW Metal2 ( 2744560 1622320 ) Via2_VH
- NEW Metal2 ( 4788560 1622320 ) Via2_VH
- NEW Metal2 ( 2606800 1657040 ) Via2_VH ;
- - la_data_out[47] ( PIN la_data_out[47] ) ( mprj la_data_out[47] ) + USE SIGNAL
- + ROUTED Metal2 ( 2622480 1649200 ) ( 2626960 * )
- NEW Metal2 ( 2626960 1649200 ) ( * 1691760 )
- NEW Metal2 ( 2623600 1691760 0 ) ( 2626960 * )
- NEW Metal2 ( 2622480 1422960 ) ( * 1649200 )
- NEW Metal3 ( 2622480 1422960 ) ( 4855760 * )
- NEW Metal2 ( 4855760 3920 0 ) ( * 1422960 )
- NEW Metal2 ( 2622480 1422960 ) Via2_VH
- NEW Metal2 ( 4855760 1422960 ) Via2_VH ;
- - la_data_out[48] ( PIN la_data_out[48] ) ( mprj la_data_out[48] ) + USE SIGNAL
- + ROUTED Metal2 ( 2637040 1653680 ) ( 2639280 * )
- NEW Metal2 ( 2637040 1653680 ) ( * 1658160 )
- NEW Metal2 ( 2637040 1658160 ) ( 2638160 * )
- NEW Metal2 ( 2638160 1658160 ) ( * 1690640 )
- NEW Metal2 ( 2638160 1690640 ) ( 2640400 * 0 )
- NEW Metal2 ( 4911760 3920 0 ) ( * 49840 )
- NEW Metal2 ( 2639280 1523760 ) ( * 1653680 )
- NEW Metal3 ( 4880400 49840 ) ( 4911760 * )
- NEW Metal3 ( 2639280 1523760 ) ( 4880400 * )
- NEW Metal2 ( 4880400 49840 ) ( * 1523760 )
- NEW Metal2 ( 4911760 49840 ) Via2_VH
- NEW Metal2 ( 2639280 1523760 ) Via2_VH
- NEW Metal2 ( 4880400 49840 ) Via2_VH
- NEW Metal2 ( 4880400 1523760 ) Via2_VH ;
- - la_data_out[49] ( PIN la_data_out[49] ) ( mprj la_data_out[49] ) + USE SIGNAL
- + ROUTED Metal2 ( 4956560 3920 ) ( 4967760 * )
- NEW Metal2 ( 4967760 3920 ) ( * 5040 )
- NEW Metal2 ( 4967760 5040 ) ( 4968880 * )
- NEW Metal2 ( 4968880 3920 0 ) ( * 5040 )
- NEW Metal2 ( 2656080 1453200 ) ( * 1495200 )
- NEW Metal2 ( 2656080 1495200 ) ( 2657200 * )
- NEW Metal2 ( 2657200 1495200 ) ( * 1690640 0 )
- NEW Metal2 ( 4956560 3920 ) ( * 1453200 )
- NEW Metal3 ( 2656080 1453200 ) ( 4956560 * )
- NEW Metal2 ( 2656080 1453200 ) Via2_VH
- NEW Metal2 ( 4956560 1453200 ) Via2_VH ;
- - la_data_out[4] ( PIN la_data_out[4] ) ( mprj la_data_out[4] ) + USE SIGNAL
- + ROUTED Metal2 ( 2386160 3920 ) ( 2397360 * )
- NEW Metal2 ( 2397360 3920 ) ( * 5040 )
- NEW Metal2 ( 2397360 5040 ) ( 2398480 * )
- NEW Metal2 ( 2398480 3920 0 ) ( * 5040 )
- NEW Metal2 ( 1901200 143920 ) ( * 1495200 )
- NEW Metal2 ( 1901200 1495200 ) ( 1902320 * )
- NEW Metal2 ( 2386160 3920 ) ( * 143920 )
- NEW Metal3 ( 1901200 143920 ) ( 2386160 * )
- NEW Metal2 ( 1901200 1680000 ) ( 1902320 * )
- NEW Metal2 ( 1901200 1680000 ) ( * 1690640 0 )
- NEW Metal4 ( 1902320 1564080 ) ( * 1623440 )
- NEW Metal2 ( 1902320 1495200 ) ( * 1564080 )
- NEW Metal2 ( 1902320 1623440 ) ( * 1680000 )
- NEW Metal2 ( 1901200 143920 ) Via2_VH
- NEW Metal2 ( 2386160 143920 ) Via2_VH
- NEW Metal2 ( 1902320 1564080 ) Via2_VH
- NEW Metal3 ( 1902320 1564080 ) Via3_HV
- NEW Metal2 ( 1902320 1623440 ) Via2_VH
- NEW Metal3 ( 1902320 1623440 ) Via3_HV
- NEW Metal3 ( 1902320 1564080 ) RECT ( -660 -280 0 280 )
- NEW Metal3 ( 1902320 1623440 ) RECT ( -660 -280 0 280 ) ;
- - la_data_out[50] ( PIN la_data_out[50] ) ( mprj la_data_out[50] ) + USE SIGNAL
- + ROUTED Metal2 ( 2671760 1690640 ) ( 2674000 * 0 )
- NEW Metal3 ( 2671760 1421840 ) ( 5023760 * )
- NEW Metal2 ( 2671760 1421840 ) ( * 1690640 )
- NEW Metal2 ( 5023760 201600 ) ( 5026000 * )
- NEW Metal2 ( 5026000 3920 0 ) ( * 201600 )
- NEW Metal2 ( 5023760 201600 ) ( * 1421840 )
- NEW Metal2 ( 2671760 1421840 ) Via2_VH
- NEW Metal2 ( 5023760 1421840 ) Via2_VH ;
- - la_data_out[51] ( PIN la_data_out[51] ) ( mprj la_data_out[51] ) + USE SIGNAL
- + ROUTED Metal2 ( 2689680 1649200 ) ( 2694160 * )
- NEW Metal2 ( 2694160 1649200 ) ( * 1691760 )
- NEW Metal2 ( 2690800 1691760 0 ) ( 2694160 * )
- NEW Metal2 ( 5074160 3920 ) ( 5082000 * )
- NEW Metal2 ( 5082000 3920 ) ( * 5040 )
- NEW Metal2 ( 5082000 5040 ) ( 5083120 * )
- NEW Metal2 ( 5083120 3920 0 ) ( * 5040 )
- NEW Metal3 ( 2689680 1403920 ) ( 5074160 * )
- NEW Metal2 ( 2689680 1403920 ) ( * 1649200 )
- NEW Metal2 ( 5074160 3920 ) ( * 1403920 )
- NEW Metal2 ( 2689680 1403920 ) Via2_VH
- NEW Metal2 ( 5074160 1403920 ) Via2_VH ;
- - la_data_out[52] ( PIN la_data_out[52] ) ( mprj la_data_out[52] ) + USE SIGNAL
- + ROUTED Metal2 ( 5141360 3920 0 ) ( * 1388240 )
- NEW Metal2 ( 2705360 1690640 ) ( 2707600 * 0 )
- NEW Metal3 ( 2705360 1388240 ) ( 5141360 * )
- NEW Metal2 ( 2705360 1388240 ) ( * 1690640 )
- NEW Metal2 ( 5141360 1388240 ) Via2_VH
- NEW Metal2 ( 2705360 1388240 ) Via2_VH ;
- - la_data_out[53] ( PIN la_data_out[53] ) ( mprj la_data_out[53] ) + USE SIGNAL
- + ROUTED Metal2 ( 5191760 3920 ) ( 5196240 * )
- NEW Metal2 ( 5196240 3920 ) ( * 5040 )
- NEW Metal2 ( 5196240 5040 ) ( 5197360 * )
- NEW Metal2 ( 5197360 3920 0 ) ( * 5040 )
- NEW Metal2 ( 5191760 3920 ) ( * 1371440 )
- NEW Metal2 ( 2724400 1371440 ) ( * 1690640 0 )
- NEW Metal3 ( 2724400 1371440 ) ( 5191760 * )
- NEW Metal2 ( 5191760 1371440 ) Via2_VH
- NEW Metal2 ( 2724400 1371440 ) Via2_VH ;
- - la_data_out[54] ( PIN la_data_out[54] ) ( mprj la_data_out[54] ) + USE SIGNAL
- + ROUTED Metal2 ( 5242160 3920 ) ( 5253360 * )
- NEW Metal2 ( 5253360 3920 ) ( * 5040 )
- NEW Metal2 ( 5253360 5040 ) ( 5254480 * )
- NEW Metal2 ( 5254480 3920 0 ) ( * 5040 )
- NEW Metal2 ( 5242160 3920 ) ( * 1470000 )
- NEW Metal2 ( 2740080 1650320 ) ( 2741200 * )
- NEW Metal3 ( 2741200 1470000 ) ( 5242160 * )
- NEW Metal2 ( 2741200 1470000 ) ( * 1650320 )
- NEW Metal2 ( 2740080 1650320 ) ( * 1680000 )
- NEW Metal2 ( 2740080 1680000 ) ( 2741200 * )
- NEW Metal2 ( 2741200 1680000 ) ( * 1690640 0 )
- NEW Metal2 ( 5242160 1470000 ) Via2_VH
- NEW Metal2 ( 2741200 1470000 ) Via2_VH ;
- - la_data_out[55] ( PIN la_data_out[55] ) ( mprj la_data_out[55] ) + USE SIGNAL
- + ROUTED Metal3 ( 5283600 46480 ) ( 5311600 * )
- NEW Metal2 ( 5311600 3920 0 ) ( * 46480 )
- NEW Metal3 ( 2755760 1437520 ) ( 5283600 * )
- NEW Metal2 ( 5283600 46480 ) ( * 1437520 )
- NEW Metal2 ( 2755760 1690640 ) ( 2758000 * 0 )
- NEW Metal2 ( 2755760 1437520 ) ( * 1690640 )
- NEW Metal2 ( 2755760 1437520 ) Via2_VH
- NEW Metal2 ( 5283600 46480 ) Via2_VH
- NEW Metal2 ( 5311600 46480 ) Via2_VH
- NEW Metal2 ( 5283600 1437520 ) Via2_VH ;
- - la_data_out[56] ( PIN la_data_out[56] ) ( mprj la_data_out[56] ) + USE SIGNAL
- + ROUTED Metal2 ( 5359760 3920 ) ( 5367600 * )
- NEW Metal2 ( 5367600 3920 ) ( * 5040 )
- NEW Metal2 ( 5367600 5040 ) ( 5368720 * )
- NEW Metal2 ( 5368720 3920 0 ) ( * 5040 )
- NEW Metal3 ( 2772560 1370320 ) ( 5359760 * )
- NEW Metal2 ( 5359760 3920 ) ( * 1370320 )
- NEW Metal2 ( 2772560 1690640 ) ( 2774800 * 0 )
- NEW Metal2 ( 2772560 1370320 ) ( * 1690640 )
- NEW Metal2 ( 2772560 1370320 ) Via2_VH
- NEW Metal2 ( 5359760 1370320 ) Via2_VH ;
- - la_data_out[57] ( PIN la_data_out[57] ) ( mprj la_data_out[57] ) + USE SIGNAL
- + ROUTED Metal2 ( 2790480 1613360 ) ( 2792720 * )
- NEW Metal2 ( 2790480 1486800 ) ( * 1613360 )
- NEW Metal2 ( 5426960 3920 0 ) ( * 1486800 )
- NEW Metal3 ( 2790480 1486800 ) ( 5426960 * )
- NEW Metal2 ( 2792720 1613360 ) ( * 1680000 )
- NEW Metal2 ( 2791600 1680000 ) ( 2792720 * )
- NEW Metal2 ( 2791600 1680000 ) ( * 1690640 0 )
- NEW Metal2 ( 2790480 1486800 ) Via2_VH
- NEW Metal2 ( 5426960 1486800 ) Via2_VH ;
- - la_data_out[58] ( PIN la_data_out[58] ) ( mprj la_data_out[58] ) + USE SIGNAL
- + ROUTED Metal3 ( 5418000 43120 ) ( 5482960 * )
- NEW Metal2 ( 5482960 3920 0 ) ( * 43120 )
- NEW Metal2 ( 5418000 43120 ) ( * 1386000 )
- NEW Metal3 ( 2806160 1386000 ) ( 5418000 * )
- NEW Metal2 ( 2806160 1690640 ) ( 2808400 * 0 )
- NEW Metal2 ( 2806160 1386000 ) ( * 1690640 )
- NEW Metal2 ( 2806160 1386000 ) Via2_VH
- NEW Metal2 ( 5418000 43120 ) Via2_VH
- NEW Metal2 ( 5482960 43120 ) Via2_VH
- NEW Metal2 ( 5418000 1386000 ) Via2_VH ;
- - la_data_out[59] ( PIN la_data_out[59] ) ( mprj la_data_out[59] ) + USE SIGNAL
- + ROUTED Metal2 ( 5527760 3920 ) ( 5538960 * )
- NEW Metal2 ( 5538960 3920 ) ( * 5040 )
- NEW Metal2 ( 5538960 5040 ) ( 5540080 * )
- NEW Metal2 ( 5540080 3920 0 ) ( * 5040 )
- NEW Metal3 ( 2822960 1402800 ) ( 5527760 * )
- NEW Metal2 ( 5527760 3920 ) ( * 1402800 )
- NEW Metal2 ( 2822960 1690640 ) ( 2825200 * 0 )
- NEW Metal2 ( 2822960 1402800 ) ( * 1690640 )
- NEW Metal2 ( 2822960 1402800 ) Via2_VH
- NEW Metal2 ( 5527760 1402800 ) Via2_VH ;
- - la_data_out[5] ( PIN la_data_out[5] ) ( mprj la_data_out[5] ) + USE SIGNAL
- + ROUTED Metal2 ( 1916880 1649200 ) ( 1921360 * )
- NEW Metal2 ( 1916880 142800 ) ( * 1649200 )
- NEW Metal3 ( 1916880 142800 ) ( 2455600 * )
- NEW Metal2 ( 2455600 3920 0 ) ( * 142800 )
- NEW Metal2 ( 1918000 1690640 0 ) ( 1921360 * )
- NEW Metal2 ( 1921360 1649200 ) ( * 1690640 )
- NEW Metal2 ( 1916880 142800 ) Via2_VH
- NEW Metal2 ( 2455600 142800 ) Via2_VH ;
- - la_data_out[60] ( PIN la_data_out[60] ) ( mprj la_data_out[60] ) + USE SIGNAL
- + ROUTED Metal3 ( 2839760 1420720 ) ( 5594960 * )
- NEW Metal2 ( 5594960 201600 ) ( 5597200 * )
- NEW Metal2 ( 5597200 3920 0 ) ( * 201600 )
- NEW Metal2 ( 5594960 201600 ) ( * 1420720 )
- NEW Metal2 ( 2839760 1690640 ) ( 2842000 * 0 )
- NEW Metal2 ( 2839760 1420720 ) ( * 1690640 )
- NEW Metal2 ( 2839760 1420720 ) Via2_VH
- NEW Metal2 ( 5594960 1420720 ) Via2_VH ;
- - la_data_out[61] ( PIN la_data_out[61] ) ( mprj la_data_out[61] ) + USE SIGNAL
- + ROUTED Metal2 ( 2857680 1650320 ) ( 2858800 * )
- NEW Metal2 ( 5645360 3920 ) ( 5653200 * )
- NEW Metal2 ( 5653200 3920 ) ( * 5040 )
- NEW Metal2 ( 5653200 5040 ) ( 5654320 * )
- NEW Metal2 ( 5654320 3920 0 ) ( * 5040 )
- NEW Metal2 ( 2858800 1352400 ) ( * 1650320 )
- NEW Metal2 ( 5645360 3920 ) ( * 1352400 )
- NEW Metal3 ( 2858800 1352400 ) ( 5645360 * )
- NEW Metal2 ( 2857680 1650320 ) ( * 1680000 )
- NEW Metal2 ( 2857680 1680000 ) ( 2858800 * )
- NEW Metal2 ( 2858800 1680000 ) ( * 1690640 0 )
- NEW Metal2 ( 2858800 1352400 ) Via2_VH
- NEW Metal2 ( 5645360 1352400 ) Via2_VH ;
- - la_data_out[62] ( PIN la_data_out[62] ) ( mprj la_data_out[62] ) + USE SIGNAL
- + ROUTED Metal2 ( 5712560 3920 0 ) ( * 1369200 )
- NEW Metal3 ( 2873360 1369200 ) ( 5712560 * )
- NEW Metal2 ( 2873360 1690640 ) ( 2875600 * 0 )
- NEW Metal2 ( 2873360 1369200 ) ( * 1690640 )
- NEW Metal2 ( 2873360 1369200 ) Via2_VH
- NEW Metal2 ( 5712560 1369200 ) Via2_VH ;
- - la_data_out[63] ( PIN la_data_out[63] ) ( mprj la_data_out[63] ) + USE SIGNAL
- + ROUTED Metal2 ( 2922640 1638000 ) ( * 1662640 )
- NEW Metal3 ( 2892400 1662640 ) ( 2922640 * )
- NEW Metal2 ( 5762960 3920 ) ( 5767440 * )
- NEW Metal2 ( 5767440 3920 ) ( * 5040 )
- NEW Metal2 ( 5767440 5040 ) ( 5768560 * )
- NEW Metal2 ( 5768560 3920 0 ) ( * 5040 )
- NEW Metal3 ( 2922640 1638000 ) ( 5762960 * )
- NEW Metal2 ( 5762960 3920 ) ( * 1638000 )
- NEW Metal2 ( 2892400 1662640 ) ( * 1690640 0 )
- NEW Metal2 ( 2892400 1662640 ) Via2_VH
- NEW Metal2 ( 2922640 1662640 ) Via2_VH
- NEW Metal2 ( 2922640 1638000 ) Via2_VH
- NEW Metal2 ( 5762960 1638000 ) Via2_VH ;
- - la_data_out[6] ( PIN la_data_out[6] ) ( mprj la_data_out[6] ) + USE SIGNAL
- + ROUTED Metal2 ( 1933680 1651440 ) ( 1934800 * )
- NEW Metal2 ( 1934800 394800 ) ( * 1651440 )
- NEW Metal2 ( 2503760 3920 ) ( 2511600 * )
- NEW Metal2 ( 2511600 3920 ) ( * 5040 )
- NEW Metal2 ( 2511600 5040 ) ( 2512720 * )
- NEW Metal2 ( 2512720 3920 0 ) ( * 5040 )
- NEW Metal3 ( 1934800 394800 ) ( 2503760 * )
- NEW Metal2 ( 2503760 3920 ) ( * 394800 )
- NEW Metal2 ( 1933680 1651440 ) ( * 1680000 )
- NEW Metal2 ( 1933680 1680000 ) ( 1934800 * )
- NEW Metal2 ( 1934800 1680000 ) ( * 1690640 0 )
- NEW Metal2 ( 1934800 394800 ) Via2_VH
- NEW Metal2 ( 2503760 394800 ) Via2_VH ;
- - la_data_out[7] ( PIN la_data_out[7] ) ( mprj la_data_out[7] ) + USE SIGNAL
- + ROUTED Metal2 ( 2570960 3920 0 ) ( * 176400 )
- NEW Metal3 ( 1951600 176400 ) ( 2570960 * )
- NEW Metal2 ( 1951600 176400 ) ( * 1690640 0 )
- NEW Metal2 ( 1951600 176400 ) Via2_VH
- NEW Metal2 ( 2570960 176400 ) Via2_VH ;
- - la_data_out[8] ( PIN la_data_out[8] ) ( mprj la_data_out[8] ) + USE SIGNAL
- + ROUTED Metal2 ( 2622480 3920 ) ( 2625840 * )
- NEW Metal2 ( 2625840 3920 ) ( * 5040 )
- NEW Metal2 ( 2625840 5040 ) ( 2626960 * )
- NEW Metal2 ( 2626960 3920 0 ) ( * 5040 )
- NEW Metal2 ( 2622480 3920 ) ( * 412720 )
- NEW Metal2 ( 1967280 1646960 ) ( 1971760 * )
- NEW Metal2 ( 1967280 412720 ) ( * 1646960 )
- NEW Metal3 ( 1967280 412720 ) ( 2622480 * )
- NEW Metal2 ( 1968400 1690640 0 ) ( 1971760 * )
- NEW Metal2 ( 1971760 1646960 ) ( * 1690640 )
- NEW Metal2 ( 2622480 412720 ) Via2_VH
- NEW Metal2 ( 1967280 412720 ) Via2_VH ;
- - la_data_out[9] ( PIN la_data_out[9] ) ( mprj la_data_out[9] ) + USE SIGNAL
- + ROUTED Metal2 ( 1984080 1614480 ) ( 1986320 * )
- NEW Metal2 ( 2671760 3920 ) ( 2682960 * )
- NEW Metal2 ( 2682960 3920 ) ( * 5040 )
- NEW Metal2 ( 2682960 5040 ) ( 2684080 * )
- NEW Metal2 ( 2684080 3920 0 ) ( * 5040 )
- NEW Metal3 ( 1984080 227920 ) ( 2671760 * )
- NEW Metal2 ( 1984080 227920 ) ( * 1614480 )
- NEW Metal2 ( 2671760 3920 ) ( * 227920 )
- NEW Metal2 ( 1986320 1614480 ) ( * 1680000 )
- NEW Metal2 ( 1985200 1680000 ) ( 1986320 * )
- NEW Metal2 ( 1985200 1680000 ) ( * 1690640 0 )
- NEW Metal2 ( 1984080 227920 ) Via2_VH
- NEW Metal2 ( 2671760 227920 ) Via2_VH ;
- - la_oenb[0] ( PIN la_oenb[0] ) ( mprj la_oenb[0] ) + USE SIGNAL
- + ROUTED Metal2 ( 2184560 3920 ) ( 2187920 * )
- NEW Metal2 ( 2187920 3920 ) ( * 5040 )
- NEW Metal2 ( 2187920 5040 ) ( 2189040 * )
- NEW Metal2 ( 2189040 3920 0 ) ( * 5040 )
- NEW Metal2 ( 2184560 3920 ) ( * 179760 )
- NEW Metal3 ( 1832880 179760 ) ( 2184560 * )
- NEW Metal2 ( 1837360 1690640 ) ( 1839600 * 0 )
- NEW Metal2 ( 1832880 1589840 ) ( 1837360 * )
- NEW Metal2 ( 1832880 179760 ) ( * 1589840 )
- NEW Metal2 ( 1837360 1589840 ) ( * 1690640 )
- NEW Metal2 ( 2184560 179760 ) Via2_VH
- NEW Metal2 ( 1832880 179760 ) Via2_VH ;
- - la_oenb[10] ( PIN la_oenb[10] ) ( mprj la_oenb[10] ) + USE SIGNAL
- + ROUTED Metal2 ( 2755760 3920 ) ( 2759120 * )
- NEW Metal2 ( 2759120 3920 ) ( * 5040 )
- NEW Metal2 ( 2759120 5040 ) ( 2760240 * )
- NEW Metal2 ( 2760240 3920 0 ) ( * 5040 )
- NEW Metal3 ( 2002000 262640 ) ( 2755760 * )
- NEW Metal2 ( 2002000 262640 ) ( * 1495200 )
- NEW Metal2 ( 2002000 1495200 ) ( 2004240 * )
- NEW Metal2 ( 2755760 3920 ) ( * 262640 )
- NEW Metal2 ( 2004240 1690640 ) ( 2007600 * 0 )
- NEW Metal2 ( 2004240 1495200 ) ( * 1690640 )
- NEW Metal2 ( 2002000 262640 ) Via2_VH
- NEW Metal2 ( 2755760 262640 ) Via2_VH ;
- - la_oenb[11] ( PIN la_oenb[11] ) ( mprj la_oenb[11] ) + USE SIGNAL
- + ROUTED Metal2 ( 2806160 3920 ) ( 2816240 * )
- NEW Metal2 ( 2816240 3920 ) ( * 5040 )
- NEW Metal2 ( 2816240 5040 ) ( 2817360 * )
- NEW Metal2 ( 2817360 3920 0 ) ( * 5040 )
- NEW Metal2 ( 2806160 3920 ) ( * 245840 )
- NEW Metal3 ( 2017680 245840 ) ( 2806160 * )
- NEW Metal2 ( 2017680 245840 ) ( * 1495200 )
- NEW Metal2 ( 2017680 1495200 ) ( 2021040 * )
- NEW Metal2 ( 2021040 1690640 ) ( 2024400 * 0 )
- NEW Metal2 ( 2021040 1495200 ) ( * 1690640 )
- NEW Metal2 ( 2806160 245840 ) Via2_VH
- NEW Metal2 ( 2017680 245840 ) Via2_VH ;
- - la_oenb[12] ( PIN la_oenb[12] ) ( mprj la_oenb[12] ) + USE SIGNAL
- + ROUTED Metal2 ( 2874480 3920 0 ) ( * 61040 )
- NEW Metal3 ( 2276400 61040 ) ( 2874480 * )
- NEW Metal3 ( 2041200 1657040 ) ( 2276400 * )
- NEW Metal2 ( 2276400 61040 ) ( * 1657040 )
- NEW Metal2 ( 2041200 1657040 ) ( * 1690640 0 )
- NEW Metal2 ( 2874480 61040 ) Via2_VH
- NEW Metal2 ( 2041200 1657040 ) Via2_VH
- NEW Metal2 ( 2276400 61040 ) Via2_VH
- NEW Metal2 ( 2276400 1657040 ) Via2_VH ;
- - la_oenb[13] ( PIN la_oenb[13] ) ( mprj la_oenb[13] ) + USE SIGNAL
- + ROUTED Metal2 ( 2923760 3920 ) ( 2930480 * )
- NEW Metal2 ( 2930480 3920 ) ( * 5040 )
- NEW Metal2 ( 2930480 5040 ) ( 2931600 * )
- NEW Metal2 ( 2931600 3920 0 ) ( * 5040 )
- NEW Metal3 ( 2053520 212240 ) ( 2923760 * )
- NEW Metal2 ( 2053520 212240 ) ( * 1495200 )
- NEW Metal2 ( 2053520 1495200 ) ( 2054640 * )
- NEW Metal2 ( 2923760 3920 ) ( * 212240 )
- NEW Metal2 ( 2054640 1690640 ) ( 2058000 * 0 )
- NEW Metal2 ( 2054640 1495200 ) ( * 1690640 )
- NEW Metal2 ( 2053520 212240 ) Via2_VH
- NEW Metal2 ( 2923760 212240 ) Via2_VH ;
- - la_oenb[14] ( PIN la_oenb[14] ) ( mprj la_oenb[14] ) + USE SIGNAL
- + ROUTED Metal2 ( 2974160 3920 ) ( 2987600 * )
- NEW Metal2 ( 2987600 3920 ) ( * 5040 )
- NEW Metal2 ( 2987600 5040 ) ( 2988720 * )
- NEW Metal2 ( 2988720 3920 0 ) ( * 5040 )
- NEW Metal3 ( 2326800 311920 ) ( 2974160 * )
- NEW Metal2 ( 2974160 3920 ) ( * 311920 )
- NEW Metal3 ( 2074800 1655920 ) ( 2326800 * )
- NEW Metal2 ( 2326800 311920 ) ( * 1655920 )
- NEW Metal2 ( 2074800 1655920 ) ( * 1690640 0 )
- NEW Metal2 ( 2326800 311920 ) Via2_VH
- NEW Metal2 ( 2074800 1655920 ) Via2_VH
- NEW Metal2 ( 2974160 311920 ) Via2_VH
- NEW Metal2 ( 2326800 1655920 ) Via2_VH ;
- - la_oenb[15] ( PIN la_oenb[15] ) ( mprj la_oenb[15] ) + USE SIGNAL
- + ROUTED Metal2 ( 3041360 3920 ) ( 3044720 * )
- NEW Metal2 ( 3044720 3920 ) ( * 5040 )
- NEW Metal2 ( 3044720 5040 ) ( 3045840 * )
- NEW Metal2 ( 3045840 3920 0 ) ( * 5040 )
- NEW Metal2 ( 3041360 3920 ) ( * 1558480 )
- NEW Metal2 ( 2088240 1690640 ) ( 2091600 * 0 )
- NEW Metal2 ( 2088240 1558480 ) ( * 1690640 )
- NEW Metal3 ( 2088240 1558480 ) ( 3041360 * )
- NEW Metal2 ( 2088240 1558480 ) Via2_VH
- NEW Metal2 ( 3041360 1558480 ) Via2_VH ;
- - la_oenb[16] ( PIN la_oenb[16] ) ( mprj la_oenb[16] ) + USE SIGNAL
- + ROUTED Metal2 ( 3091760 3920 ) ( 3101840 * )
- NEW Metal2 ( 3101840 3920 ) ( * 5040 )
- NEW Metal2 ( 3101840 5040 ) ( 3102960 * )
- NEW Metal2 ( 3102960 3920 0 ) ( * 5040 )
- NEW Metal2 ( 2103920 1184400 ) ( * 1495200 )
- NEW Metal2 ( 2103920 1495200 ) ( 2105040 * )
- NEW Metal2 ( 3091760 3920 ) ( * 1184400 )
- NEW Metal3 ( 2103920 1184400 ) ( 3091760 * )
- NEW Metal2 ( 2105040 1690640 ) ( 2108400 * 0 )
- NEW Metal2 ( 2105040 1495200 ) ( * 1690640 )
- NEW Metal2 ( 2103920 1184400 ) Via2_VH
- NEW Metal2 ( 3091760 1184400 ) Via2_VH ;
- - la_oenb[17] ( PIN la_oenb[17] ) ( mprj la_oenb[17] ) + USE SIGNAL
- + ROUTED Metal3 ( 2117360 1652560 ) ( * 1653680 )
- NEW Metal3 ( 2117360 1653680 ) ( 2121840 * )
- NEW Metal2 ( 2117360 26320 ) ( * 1652560 )
- NEW Metal2 ( 3160080 3920 0 ) ( * 26320 )
- NEW Metal3 ( 2117360 26320 ) ( 3160080 * )
- NEW Metal2 ( 2121840 1690640 ) ( 2125200 * 0 )
- NEW Metal2 ( 2121840 1653680 ) ( * 1690640 )
- NEW Metal2 ( 2117360 26320 ) Via2_VH
- NEW Metal2 ( 2117360 1652560 ) Via2_VH
- NEW Metal2 ( 2121840 1653680 ) Via2_VH
- NEW Metal2 ( 3160080 26320 ) Via2_VH ;
- - la_oenb[18] ( PIN la_oenb[18] ) ( mprj la_oenb[18] ) + USE SIGNAL
- + ROUTED Metal3 ( 2136400 1613360 ) ( 2138640 * )
- NEW Metal2 ( 2136400 1424080 ) ( * 1612240 )
- NEW Metal3 ( 2136400 1612240 ) ( * 1613360 )
- NEW Metal2 ( 3209360 3920 ) ( 3216080 * )
- NEW Metal2 ( 3216080 3920 ) ( * 5040 )
- NEW Metal2 ( 3216080 5040 ) ( 3217200 * )
- NEW Metal2 ( 3217200 3920 0 ) ( * 5040 )
- NEW Metal3 ( 2136400 1424080 ) ( 3209360 * )
- NEW Metal2 ( 3209360 3920 ) ( * 1424080 )
- NEW Metal2 ( 2138640 1690640 ) ( 2142000 * 0 )
- NEW Metal2 ( 2138640 1613360 ) ( * 1690640 )
- NEW Metal2 ( 2136400 1424080 ) Via2_VH
- NEW Metal2 ( 2138640 1613360 ) Via2_VH
- NEW Metal2 ( 2136400 1612240 ) Via2_VH
- NEW Metal2 ( 3209360 1424080 ) Via2_VH ;
- - la_oenb[19] ( PIN la_oenb[19] ) ( mprj la_oenb[19] ) + USE SIGNAL
- + ROUTED Metal2 ( 3259760 3920 ) ( 3273200 * )
- NEW Metal2 ( 3273200 3920 ) ( * 5040 )
- NEW Metal2 ( 3273200 5040 ) ( 3274320 * )
- NEW Metal2 ( 3274320 3920 0 ) ( * 5040 )
- NEW Metal2 ( 3259760 3920 ) ( * 1527120 )
- NEW Metal2 ( 2155440 1690640 ) ( 2158800 * 0 )
- NEW Metal2 ( 2155440 1527120 ) ( * 1690640 )
- NEW Metal3 ( 2155440 1527120 ) ( 3259760 * )
- NEW Metal2 ( 2155440 1527120 ) Via2_VH
- NEW Metal2 ( 3259760 1527120 ) Via2_VH ;
- - la_oenb[1] ( PIN la_oenb[1] ) ( mprj la_oenb[1] ) + USE SIGNAL
- + ROUTED Metal2 ( 1849680 210000 ) ( * 1495200 )
- NEW Metal2 ( 1849680 1495200 ) ( 1853040 * )
- NEW Metal2 ( 2234960 3920 ) ( 2245040 * )
- NEW Metal2 ( 2245040 3920 ) ( * 5040 )
- NEW Metal2 ( 2245040 5040 ) ( 2246160 * )
- NEW Metal2 ( 2246160 3920 0 ) ( * 5040 )
- NEW Metal3 ( 1849680 210000 ) ( 2234960 * )
- NEW Metal2 ( 2234960 3920 ) ( * 210000 )
- NEW Metal2 ( 1853040 1690640 ) ( 1856400 * 0 )
- NEW Metal2 ( 1853040 1495200 ) ( * 1690640 )
- NEW Metal2 ( 1849680 210000 ) Via2_VH
- NEW Metal2 ( 2234960 210000 ) Via2_VH ;
- - la_oenb[20] ( PIN la_oenb[20] ) ( mprj la_oenb[20] ) + USE SIGNAL
- + ROUTED Metal3 ( 2167760 1652560 ) ( * 1653680 )
- NEW Metal3 ( 2167760 1653680 ) ( 2172240 * )
- NEW Metal2 ( 3331440 3920 0 ) ( * 40880 )
- NEW Metal2 ( 2167760 40880 ) ( * 1652560 )
- NEW Metal3 ( 2167760 40880 ) ( 3331440 * )
- NEW Metal2 ( 2172240 1690640 ) ( 2175600 * 0 )
- NEW Metal2 ( 2172240 1653680 ) ( * 1690640 )
- NEW Metal2 ( 2167760 40880 ) Via2_VH
- NEW Metal2 ( 2167760 1652560 ) Via2_VH
- NEW Metal2 ( 2172240 1653680 ) Via2_VH
- NEW Metal2 ( 3331440 40880 ) Via2_VH ;
- - la_oenb[21] ( PIN la_oenb[21] ) ( mprj la_oenb[21] ) + USE SIGNAL
- + ROUTED Metal2 ( 2186800 1406160 ) ( * 1495200 )
- NEW Metal2 ( 2186800 1495200 ) ( 2189040 * )
- NEW Metal2 ( 3377360 3920 ) ( 3387440 * )
- NEW Metal2 ( 3387440 3920 ) ( * 5040 )
- NEW Metal2 ( 3387440 5040 ) ( 3388560 * )
- NEW Metal2 ( 3388560 3920 0 ) ( * 5040 )
- NEW Metal3 ( 2186800 1406160 ) ( 3377360 * )
- NEW Metal2 ( 3377360 3920 ) ( * 1406160 )
- NEW Metal2 ( 2189040 1690640 ) ( 2192400 * 0 )
- NEW Metal2 ( 2189040 1495200 ) ( * 1690640 )
- NEW Metal2 ( 2186800 1406160 ) Via2_VH
- NEW Metal2 ( 3377360 1406160 ) Via2_VH ;
- - la_oenb[22] ( PIN la_oenb[22] ) ( mprj la_oenb[22] ) + USE SIGNAL
- + ROUTED Metal3 ( 2360400 982800 ) ( 3444560 * )
- NEW Metal2 ( 3444560 201600 ) ( 3445680 * )
- NEW Metal2 ( 3445680 3920 0 ) ( * 201600 )
- NEW Metal2 ( 3444560 201600 ) ( * 982800 )
- NEW Metal3 ( 2209200 1658160 ) ( 2360400 * )
- NEW Metal2 ( 2360400 982800 ) ( * 1658160 )
- NEW Metal2 ( 2209200 1658160 ) ( * 1690640 0 )
- NEW Metal2 ( 2360400 982800 ) Via2_VH
- NEW Metal2 ( 2209200 1658160 ) Via2_VH
- NEW Metal2 ( 3444560 982800 ) Via2_VH
- NEW Metal2 ( 2360400 1658160 ) Via2_VH ;
- - la_oenb[23] ( PIN la_oenb[23] ) ( mprj la_oenb[23] ) + USE SIGNAL
- + ROUTED Metal2 ( 3502800 3920 0 ) ( * 49840 )
- NEW Metal1 ( 2218160 1622320 ) ( 2223760 * )
- NEW Metal3 ( 2218160 49840 ) ( 3502800 * )
- NEW Metal2 ( 2218160 49840 ) ( * 1622320 )
- NEW Metal2 ( 2223760 1690640 ) ( 2226000 * 0 )
- NEW Metal2 ( 2223760 1622320 ) ( * 1690640 )
- NEW Metal2 ( 3502800 49840 ) Via2_VH
- NEW Metal2 ( 2218160 49840 ) Via2_VH
- NEW Metal1 ( 2218160 1622320 ) Via1_HV
- NEW Metal1 ( 2223760 1622320 ) Via1_HV ;
- - la_oenb[24] ( PIN la_oenb[24] ) ( mprj la_oenb[24] ) + USE SIGNAL
- + ROUTED Metal2 ( 3545360 3920 ) ( 3558800 * )
- NEW Metal2 ( 3558800 3920 ) ( * 5040 )
- NEW Metal2 ( 3558800 5040 ) ( 3559920 * )
- NEW Metal2 ( 3559920 3920 0 ) ( * 5040 )
- NEW Metal2 ( 3545360 3920 ) ( * 1607760 )
- NEW Metal3 ( 2239440 1607760 ) ( 3545360 * )
- NEW Metal2 ( 2239440 1690640 ) ( 2242800 * 0 )
- NEW Metal2 ( 2239440 1607760 ) ( * 1690640 )
- NEW Metal2 ( 3545360 1607760 ) Via2_VH
- NEW Metal2 ( 2239440 1607760 ) Via2_VH ;
- - la_oenb[25] ( PIN la_oenb[25] ) ( mprj la_oenb[25] ) + USE SIGNAL
- + ROUTED Metal1 ( 2251760 1613360 ) ( 2256240 * )
- NEW Metal2 ( 3617040 3920 0 ) ( * 48720 )
- NEW Metal3 ( 2251760 48720 ) ( 3617040 * )
- NEW Metal2 ( 2251760 48720 ) ( * 1613360 )
- NEW Metal2 ( 2256240 1690640 ) ( 2259600 * 0 )
- NEW Metal2 ( 2256240 1613360 ) ( * 1690640 )
- NEW Metal2 ( 2251760 48720 ) Via2_VH
- NEW Metal1 ( 2251760 1613360 ) Via1_HV
- NEW Metal1 ( 2256240 1613360 ) Via1_HV
- NEW Metal2 ( 3617040 48720 ) Via2_VH ;
- - la_oenb[26] ( PIN la_oenb[26] ) ( mprj la_oenb[26] ) + USE SIGNAL
- + ROUTED Metal3 ( 2269680 93520 ) ( 3674160 * )
- NEW Metal2 ( 3674160 3920 0 ) ( * 93520 )
- NEW Metal2 ( 2274160 1690640 ) ( 2276400 * 0 )
- NEW Metal2 ( 2269680 1587600 ) ( 2274160 * )
- NEW Metal2 ( 2269680 93520 ) ( * 1587600 )
- NEW Metal2 ( 2274160 1587600 ) ( * 1690640 )
- NEW Metal2 ( 2269680 93520 ) Via2_VH
- NEW Metal2 ( 3674160 93520 ) Via2_VH ;
- - la_oenb[27] ( PIN la_oenb[27] ) ( mprj la_oenb[27] ) + USE SIGNAL
- + ROUTED Metal2 ( 3730160 201600 ) ( 3731280 * )
- NEW Metal2 ( 3731280 3920 0 ) ( * 201600 )
- NEW Metal2 ( 3730160 201600 ) ( * 1353520 )
- NEW Metal3 ( 2287600 1353520 ) ( 3730160 * )
- NEW Metal2 ( 2287600 1353520 ) ( * 1562400 )
- NEW Metal2 ( 2287600 1562400 ) ( 2289840 * )
- NEW Metal2 ( 2289840 1690640 ) ( 2293200 * 0 )
- NEW Metal2 ( 2289840 1562400 ) ( * 1690640 )
- NEW Metal2 ( 3730160 1353520 ) Via2_VH
- NEW Metal2 ( 2287600 1353520 ) Via2_VH ;
- - la_oenb[28] ( PIN la_oenb[28] ) ( mprj la_oenb[28] ) + USE SIGNAL
- + ROUTED Metal2 ( 3780560 3920 ) ( 3787280 * )
- NEW Metal2 ( 3787280 3920 ) ( * 5040 )
- NEW Metal2 ( 3787280 5040 ) ( 3788400 * )
- NEW Metal2 ( 3788400 3920 0 ) ( * 5040 )
- NEW Metal2 ( 3780560 3920 ) ( * 1337840 )
- NEW Metal3 ( 2303280 1337840 ) ( 3780560 * )
- NEW Metal2 ( 2307760 1690640 ) ( 2310000 * 0 )
- NEW Metal2 ( 2303280 1587600 ) ( 2307760 * )
- NEW Metal2 ( 2303280 1337840 ) ( * 1587600 )
- NEW Metal2 ( 2307760 1587600 ) ( * 1690640 )
- NEW Metal2 ( 3780560 1337840 ) Via2_VH
- NEW Metal2 ( 2303280 1337840 ) Via2_VH ;
- - la_oenb[29] ( PIN la_oenb[29] ) ( mprj la_oenb[29] ) + USE SIGNAL
- + ROUTED Metal2 ( 3845520 3920 0 ) ( * 59920 )
- NEW Metal3 ( 2318960 59920 ) ( 3845520 * )
- NEW Metal2 ( 2318960 59920 ) ( * 1562400 )
- NEW Metal2 ( 2318960 1562400 ) ( 2323440 * )
- NEW Metal2 ( 2323440 1690640 ) ( 2326800 * 0 )
- NEW Metal2 ( 2323440 1562400 ) ( * 1690640 )
- NEW Metal2 ( 2318960 59920 ) Via2_VH
- NEW Metal2 ( 3845520 59920 ) Via2_VH ;
- - la_oenb[2] ( PIN la_oenb[2] ) ( mprj la_oenb[2] ) + USE SIGNAL
- + ROUTED Metal2 ( 2303280 3920 0 ) ( * 59920 )
- NEW Metal3 ( 1990800 59920 ) ( 2303280 * )
- NEW Metal2 ( 1990800 59920 ) ( * 1657040 )
- NEW Metal3 ( 1873200 1657040 ) ( 1990800 * )
- NEW Metal2 ( 1873200 1657040 ) ( * 1690640 0 )
- NEW Metal2 ( 1990800 59920 ) Via2_VH
- NEW Metal2 ( 1990800 1657040 ) Via2_VH
- NEW Metal2 ( 2303280 59920 ) Via2_VH
- NEW Metal2 ( 1873200 1657040 ) Via2_VH ;
- - la_oenb[30] ( PIN la_oenb[30] ) ( mprj la_oenb[30] ) + USE SIGNAL
- + ROUTED Metal2 ( 3898160 3920 ) ( 3901520 * )
- NEW Metal2 ( 3901520 3920 ) ( * 5040 )
- NEW Metal2 ( 3901520 5040 ) ( 3902640 * )
- NEW Metal2 ( 3902640 3920 0 ) ( * 5040 )
- NEW Metal3 ( 2335760 1336720 ) ( 3898160 * )
- NEW Metal2 ( 3898160 3920 ) ( * 1336720 )
- NEW Metal3 ( 2335760 1621200 ) ( 2341360 * )
- NEW Metal2 ( 2335760 1336720 ) ( * 1621200 )
- NEW Metal2 ( 2341360 1690640 ) ( 2343600 * 0 )
- NEW Metal2 ( 2341360 1621200 ) ( * 1690640 )
- NEW Metal2 ( 2335760 1336720 ) Via2_VH
- NEW Metal2 ( 3898160 1336720 ) Via2_VH
- NEW Metal2 ( 2335760 1621200 ) Via2_VH
- NEW Metal2 ( 2341360 1621200 ) Via2_VH ;
- - la_oenb[31] ( PIN la_oenb[31] ) ( mprj la_oenb[31] ) + USE SIGNAL
- + ROUTED Metal2 ( 3948560 3920 ) ( 3958640 * )
- NEW Metal2 ( 3958640 3920 ) ( * 5040 )
- NEW Metal2 ( 3958640 5040 ) ( 3959760 * )
- NEW Metal2 ( 3959760 3920 0 ) ( * 5040 )
- NEW Metal3 ( 2352560 529200 ) ( 3948560 * )
- NEW Metal2 ( 3948560 3920 ) ( * 529200 )
- NEW Metal1 ( 2352560 1621200 ) ( * 1622320 )
- NEW Metal1 ( 2352560 1622320 ) ( 2357040 * )
- NEW Metal2 ( 2352560 529200 ) ( * 1621200 )
- NEW Metal2 ( 2357040 1690640 ) ( 2360400 * 0 )
- NEW Metal2 ( 2357040 1622320 ) ( * 1690640 )
- NEW Metal2 ( 2352560 529200 ) Via2_VH
- NEW Metal2 ( 3948560 529200 ) Via2_VH
- NEW Metal1 ( 2352560 1621200 ) Via1_HV
- NEW Metal1 ( 2357040 1622320 ) Via1_HV ;
- - la_oenb[32] ( PIN la_oenb[32] ) ( mprj la_oenb[32] ) + USE SIGNAL
- + ROUTED Metal2 ( 4016880 3920 0 ) ( * 110320 )
- NEW Metal3 ( 2369360 110320 ) ( 4016880 * )
- NEW Metal3 ( 2369360 1621200 ) ( 2377200 * )
- NEW Metal2 ( 2369360 110320 ) ( * 1621200 )
- NEW Metal2 ( 2377200 1621200 ) ( * 1690640 0 )
- NEW Metal2 ( 2369360 110320 ) Via2_VH
- NEW Metal2 ( 4016880 110320 ) Via2_VH
- NEW Metal2 ( 2369360 1621200 ) Via2_VH
- NEW Metal2 ( 2377200 1621200 ) Via2_VH ;
- - la_oenb[33] ( PIN la_oenb[33] ) ( mprj la_oenb[33] ) + USE SIGNAL
- + ROUTED Metal2 ( 4066160 3920 ) ( 4072880 * )
- NEW Metal2 ( 4072880 3920 ) ( * 5040 )
- NEW Metal2 ( 4072880 5040 ) ( 4074000 * )
- NEW Metal2 ( 4074000 3920 0 ) ( * 5040 )
- NEW Metal2 ( 4066160 3920 ) ( * 1504720 )
- NEW Metal3 ( 2394000 1658160 ) ( 2461200 * )
- NEW Metal2 ( 2394000 1658160 ) ( * 1690640 0 )
- NEW Metal2 ( 2461200 1504720 ) ( * 1658160 )
- NEW Metal3 ( 2461200 1504720 ) ( 4066160 * )
- NEW Metal2 ( 4066160 1504720 ) Via2_VH
- NEW Metal2 ( 2394000 1658160 ) Via2_VH
- NEW Metal2 ( 2461200 1658160 ) Via2_VH
- NEW Metal2 ( 2461200 1504720 ) Via2_VH ;
- - la_oenb[34] ( PIN la_oenb[34] ) ( mprj la_oenb[34] ) + USE SIGNAL
- + ROUTED Metal2 ( 4116560 3920 ) ( 4130000 * )
- NEW Metal2 ( 4130000 3920 ) ( * 5040 )
- NEW Metal2 ( 4130000 5040 ) ( 4131120 * )
- NEW Metal2 ( 4131120 3920 0 ) ( * 5040 )
- NEW Metal3 ( 2402960 126000 ) ( 4116560 * )
- NEW Metal2 ( 4116560 3920 ) ( * 126000 )
- NEW Metal3 ( 2402960 1621200 ) ( 2410800 * )
- NEW Metal2 ( 2410800 1621200 ) ( * 1690640 0 )
- NEW Metal2 ( 2402960 126000 ) ( * 1621200 )
- NEW Metal2 ( 2402960 126000 ) Via2_VH
- NEW Metal2 ( 4116560 126000 ) Via2_VH
- NEW Metal2 ( 2402960 1621200 ) Via2_VH
- NEW Metal2 ( 2410800 1621200 ) Via2_VH ;
- - la_oenb[35] ( PIN la_oenb[35] ) ( mprj la_oenb[35] ) + USE SIGNAL
- + ROUTED Metal2 ( 2424240 1690640 ) ( 2427600 * 0 )
- NEW Metal2 ( 4188240 3920 0 ) ( * 47600 )
- NEW Metal3 ( 2419760 47600 ) ( 4188240 * )
- NEW Metal2 ( 2419760 47600 ) ( * 1444800 )
- NEW Metal2 ( 2419760 1444800 ) ( 2424240 * )
- NEW Metal2 ( 2424240 1444800 ) ( * 1690640 )
- NEW Metal2 ( 2419760 47600 ) Via2_VH
- NEW Metal2 ( 4188240 47600 ) Via2_VH ;
- - la_oenb[36] ( PIN la_oenb[36] ) ( mprj la_oenb[36] ) + USE SIGNAL
- + ROUTED Metal2 ( 4234160 3920 ) ( 4244240 * )
- NEW Metal2 ( 4244240 3920 ) ( * 5040 )
- NEW Metal2 ( 4244240 5040 ) ( 4245360 * )
- NEW Metal2 ( 4245360 3920 0 ) ( * 5040 )
- NEW Metal2 ( 4234160 3920 ) ( * 143920 )
- NEW Metal3 ( 2436560 143920 ) ( 4234160 * )
- NEW Metal3 ( 2436560 1621200 ) ( 2444400 * )
- NEW Metal2 ( 2444400 1621200 ) ( * 1690640 0 )
- NEW Metal2 ( 2436560 143920 ) ( * 1621200 )
- NEW Metal2 ( 4234160 143920 ) Via2_VH
- NEW Metal2 ( 2436560 143920 ) Via2_VH
- NEW Metal2 ( 2436560 1621200 ) Via2_VH
- NEW Metal2 ( 2444400 1621200 ) Via2_VH ;
- - la_oenb[37] ( PIN la_oenb[37] ) ( mprj la_oenb[37] ) + USE SIGNAL
- + ROUTED Metal2 ( 4302480 3920 0 ) ( * 193200 )
- NEW Metal2 ( 2457840 1690640 ) ( 2461200 * 0 )
- NEW Metal3 ( 2453360 193200 ) ( 4302480 * )
- NEW Metal2 ( 2453360 193200 ) ( * 1444800 )
- NEW Metal2 ( 2453360 1444800 ) ( 2457840 * )
- NEW Metal2 ( 2457840 1444800 ) ( * 1690640 )
- NEW Metal2 ( 4302480 193200 ) Via2_VH
- NEW Metal2 ( 2453360 193200 ) Via2_VH ;
- - la_oenb[38] ( PIN la_oenb[38] ) ( mprj la_oenb[38] ) + USE SIGNAL
- + ROUTED Metal2 ( 2474640 1690640 ) ( 2478000 * 0 )
- NEW Metal2 ( 4359600 3920 0 ) ( * 46480 )
- NEW Metal3 ( 2470160 46480 ) ( 4359600 * )
- NEW Metal1 ( 2470160 1537200 ) ( 2474640 * )
- NEW Metal2 ( 2470160 46480 ) ( * 1537200 )
- NEW Metal2 ( 2474640 1537200 ) ( * 1690640 )
- NEW Metal2 ( 2470160 46480 ) Via2_VH
- NEW Metal2 ( 4359600 46480 ) Via2_VH
- NEW Metal1 ( 2470160 1537200 ) Via1_HV
- NEW Metal1 ( 2474640 1537200 ) Via1_HV ;
- - la_oenb[39] ( PIN la_oenb[39] ) ( mprj la_oenb[39] ) + USE SIGNAL
- + ROUTED Metal2 ( 4416720 3920 0 ) ( * 45360 )
- NEW Metal3 ( 2486960 45360 ) ( 4416720 * )
- NEW Metal3 ( 2486960 1621200 ) ( 2494800 * )
- NEW Metal2 ( 2494800 1621200 ) ( * 1690640 0 )
- NEW Metal2 ( 2486960 45360 ) ( * 1621200 )
- NEW Metal2 ( 2486960 45360 ) Via2_VH
- NEW Metal2 ( 4416720 45360 ) Via2_VH
- NEW Metal2 ( 2486960 1621200 ) Via2_VH
- NEW Metal2 ( 2494800 1621200 ) Via2_VH ;
- - la_oenb[3] ( PIN la_oenb[3] ) ( mprj la_oenb[3] ) + USE SIGNAL
- + ROUTED Metal2 ( 2352560 3920 ) ( 2359280 * )
- NEW Metal2 ( 2359280 3920 ) ( * 5040 )
- NEW Metal2 ( 2359280 5040 ) ( 2360400 * )
- NEW Metal2 ( 2360400 3920 0 ) ( * 5040 )
- NEW Metal2 ( 2091600 146160 ) ( * 1654800 )
- NEW Metal2 ( 2352560 3920 ) ( * 146160 )
- NEW Metal3 ( 2091600 146160 ) ( 2352560 * )
- NEW Metal3 ( 1890000 1654800 ) ( 2091600 * )
- NEW Metal2 ( 1890000 1654800 ) ( * 1690640 0 )
- NEW Metal2 ( 2091600 1654800 ) Via2_VH
- NEW Metal2 ( 2091600 146160 ) Via2_VH
- NEW Metal2 ( 2352560 146160 ) Via2_VH
- NEW Metal2 ( 1890000 1654800 ) Via2_VH ;
- - la_oenb[40] ( PIN la_oenb[40] ) ( mprj la_oenb[40] ) + USE SIGNAL
- + ROUTED Metal2 ( 4469360 3920 ) ( 4472720 * )
- NEW Metal2 ( 4472720 3920 ) ( * 5040 )
- NEW Metal2 ( 4472720 5040 ) ( 4473840 * )
- NEW Metal2 ( 4473840 3920 0 ) ( * 5040 )
- NEW Metal2 ( 4469360 3920 ) ( * 462000 )
- NEW Metal3 ( 2503760 462000 ) ( 4469360 * )
- NEW Metal3 ( 2503760 1621200 ) ( * 1622320 )
- NEW Metal3 ( 2503760 1622320 ) ( 2508240 * )
- NEW Metal2 ( 2503760 462000 ) ( * 1621200 )
- NEW Metal2 ( 2508240 1690640 ) ( 2511600 * 0 )
- NEW Metal2 ( 2508240 1622320 ) ( * 1690640 )
- NEW Metal2 ( 4469360 462000 ) Via2_VH
- NEW Metal2 ( 2503760 462000 ) Via2_VH
- NEW Metal2 ( 2503760 1621200 ) Via2_VH
- NEW Metal2 ( 2508240 1622320 ) Via2_VH ;
- - la_oenb[41] ( PIN la_oenb[41] ) ( mprj la_oenb[41] ) + USE SIGNAL
- + ROUTED Metal2 ( 4519760 3920 ) ( 4529840 * )
- NEW Metal2 ( 4529840 3920 ) ( * 5040 )
- NEW Metal2 ( 4529840 5040 ) ( 4530960 * )
- NEW Metal2 ( 4530960 3920 0 ) ( * 5040 )
- NEW Metal2 ( 4519760 3920 ) ( * 1335600 )
- NEW Metal3 ( 2520560 1335600 ) ( 4519760 * )
- NEW Metal3 ( 2520560 1621200 ) ( 2528400 * )
- NEW Metal2 ( 2520560 1335600 ) ( * 1621200 )
- NEW Metal2 ( 2528400 1621200 ) ( * 1690640 0 )
- NEW Metal2 ( 4519760 1335600 ) Via2_VH
- NEW Metal2 ( 2520560 1335600 ) Via2_VH
- NEW Metal2 ( 2520560 1621200 ) Via2_VH
- NEW Metal2 ( 2528400 1621200 ) Via2_VH ;
- - la_oenb[42] ( PIN la_oenb[42] ) ( mprj la_oenb[42] ) + USE SIGNAL
- + ROUTED Metal2 ( 4588080 3920 0 ) ( * 75600 )
- NEW Metal3 ( 2537360 75600 ) ( 4588080 * )
- NEW Metal3 ( 2537360 1621200 ) ( 2545200 * )
- NEW Metal2 ( 2537360 75600 ) ( * 1621200 )
- NEW Metal2 ( 2545200 1621200 ) ( * 1690640 0 )
- NEW Metal2 ( 2537360 75600 ) Via2_VH
- NEW Metal2 ( 4588080 75600 ) Via2_VH
- NEW Metal2 ( 2537360 1621200 ) Via2_VH
- NEW Metal2 ( 2545200 1621200 ) Via2_VH ;
- - la_oenb[43] ( PIN la_oenb[43] ) ( mprj la_oenb[43] ) + USE SIGNAL
- + ROUTED Metal2 ( 4637360 3920 ) ( 4644080 * )
- NEW Metal2 ( 4644080 3920 ) ( * 5040 )
- NEW Metal2 ( 4644080 5040 ) ( 4645200 * )
- NEW Metal2 ( 4645200 3920 0 ) ( * 5040 )
- NEW Metal3 ( 2554160 378000 ) ( 4637360 * )
- NEW Metal2 ( 4637360 3920 ) ( * 378000 )
- NEW Metal3 ( 2554160 1621200 ) ( 2562000 * )
- NEW Metal2 ( 2554160 378000 ) ( * 1621200 )
- NEW Metal2 ( 2562000 1621200 ) ( * 1690640 0 )
- NEW Metal2 ( 2554160 378000 ) Via2_VH
- NEW Metal2 ( 4637360 378000 ) Via2_VH
- NEW Metal2 ( 2554160 1621200 ) Via2_VH
- NEW Metal2 ( 2562000 1621200 ) Via2_VH ;
- - la_oenb[44] ( PIN la_oenb[44] ) ( mprj la_oenb[44] ) + USE SIGNAL
- + ROUTED Metal2 ( 4687760 3920 ) ( 4701200 * )
- NEW Metal2 ( 4701200 3920 ) ( * 5040 )
- NEW Metal2 ( 4701200 5040 ) ( 4702320 * )
- NEW Metal2 ( 4702320 3920 0 ) ( * 5040 )
- NEW Metal2 ( 2662800 1472240 ) ( * 1651440 )
- NEW Metal2 ( 4687760 3920 ) ( * 1472240 )
- NEW Metal3 ( 2662800 1472240 ) ( 4687760 * )
- NEW Metal3 ( 2578800 1651440 ) ( 2662800 * )
- NEW Metal2 ( 2578800 1651440 ) ( * 1690640 0 )
- NEW Metal2 ( 2662800 1472240 ) Via2_VH
- NEW Metal2 ( 2662800 1651440 ) Via2_VH
- NEW Metal2 ( 4687760 1472240 ) Via2_VH
- NEW Metal2 ( 2578800 1651440 ) Via2_VH ;
- - la_oenb[45] ( PIN la_oenb[45] ) ( mprj la_oenb[45] ) + USE SIGNAL
- + ROUTED Metal2 ( 4759440 3920 0 ) ( * 92400 )
- NEW Metal3 ( 2587760 92400 ) ( 4759440 * )
- NEW Metal3 ( 2587760 1621200 ) ( 2595600 * )
- NEW Metal2 ( 2587760 92400 ) ( * 1621200 )
- NEW Metal2 ( 2595600 1621200 ) ( * 1690640 0 )
- NEW Metal2 ( 2587760 92400 ) Via2_VH
- NEW Metal2 ( 4759440 92400 ) Via2_VH
- NEW Metal2 ( 2587760 1621200 ) Via2_VH
- NEW Metal2 ( 2595600 1621200 ) Via2_VH ;
- - la_oenb[46] ( PIN la_oenb[46] ) ( mprj la_oenb[46] ) + USE SIGNAL
- + ROUTED Metal2 ( 2646000 1454320 ) ( * 1650320 )
- NEW Metal2 ( 4805360 3920 ) ( 4815440 * )
- NEW Metal2 ( 4815440 3920 ) ( * 5040 )
- NEW Metal2 ( 4815440 5040 ) ( 4816560 * )
- NEW Metal2 ( 4816560 3920 0 ) ( * 5040 )
- NEW Metal3 ( 2646000 1454320 ) ( 4805360 * )
- NEW Metal2 ( 4805360 3920 ) ( * 1454320 )
- NEW Metal3 ( 2615760 1650320 ) ( 2646000 * )
- NEW Metal2 ( 2612400 1690640 0 ) ( 2615760 * )
- NEW Metal2 ( 2615760 1650320 ) ( * 1690640 )
- NEW Metal2 ( 2646000 1454320 ) Via2_VH
- NEW Metal2 ( 2646000 1650320 ) Via2_VH
- NEW Metal2 ( 4805360 1454320 ) Via2_VH
- NEW Metal2 ( 2615760 1650320 ) Via2_VH ;
- - la_oenb[47] ( PIN la_oenb[47] ) ( mprj la_oenb[47] ) + USE SIGNAL
- + ROUTED Metal1 ( 2621360 1651440 ) ( 2629200 * )
- NEW Metal2 ( 2629200 1651440 ) ( * 1690640 0 )
- NEW Metal2 ( 2621360 159600 ) ( * 1651440 )
- NEW Metal3 ( 2621360 159600 ) ( 4873680 * )
- NEW Metal2 ( 4873680 3920 0 ) ( * 159600 )
- NEW Metal1 ( 2621360 1651440 ) Via1_HV
- NEW Metal1 ( 2629200 1651440 ) Via1_HV
- NEW Metal2 ( 2621360 159600 ) Via2_VH
- NEW Metal2 ( 4873680 159600 ) Via2_VH ;
- - la_oenb[48] ( PIN la_oenb[48] ) ( mprj la_oenb[48] ) + USE SIGNAL
- + ROUTED Metal1 ( 2638160 1650320 ) ( 2642640 * )
- NEW Metal2 ( 2642640 1650320 ) ( * 1690640 )
- NEW Metal2 ( 2642640 1690640 ) ( 2646000 * 0 )
- NEW Metal2 ( 4922960 3920 ) ( 4929680 * )
- NEW Metal2 ( 4929680 3920 ) ( * 5040 )
- NEW Metal2 ( 4929680 5040 ) ( 4930800 * )
- NEW Metal2 ( 4930800 3920 0 ) ( * 5040 )
- NEW Metal2 ( 2638160 260400 ) ( * 1650320 )
- NEW Metal2 ( 4922960 3920 ) ( * 260400 )
- NEW Metal3 ( 2638160 260400 ) ( 4922960 * )
- NEW Metal2 ( 2638160 260400 ) Via2_VH
- NEW Metal1 ( 2638160 1650320 ) Via1_HV
- NEW Metal1 ( 2642640 1650320 ) Via1_HV
- NEW Metal2 ( 4922960 260400 ) Via2_VH ;
- - la_oenb[49] ( PIN la_oenb[49] ) ( mprj la_oenb[49] ) + USE SIGNAL
- + ROUTED Metal2 ( 2662800 1658160 ) ( * 1690640 0 )
- NEW Metal2 ( 4973360 3920 ) ( 4986800 * )
- NEW Metal2 ( 4986800 3920 ) ( * 5040 )
- NEW Metal2 ( 4986800 5040 ) ( 4987920 * )
- NEW Metal2 ( 4987920 3920 0 ) ( * 5040 )
- NEW Metal2 ( 2847600 142800 ) ( * 1658160 )
- NEW Metal2 ( 4973360 3920 ) ( * 142800 )
- NEW Metal3 ( 2662800 1658160 ) ( 2847600 * )
- NEW Metal3 ( 2847600 142800 ) ( 4973360 * )
- NEW Metal2 ( 2662800 1658160 ) Via2_VH
- NEW Metal2 ( 2847600 1658160 ) Via2_VH
- NEW Metal2 ( 2847600 142800 ) Via2_VH
- NEW Metal2 ( 4973360 142800 ) Via2_VH ;
- - la_oenb[4] ( PIN la_oenb[4] ) ( mprj la_oenb[4] ) + USE SIGNAL
- + ROUTED Metal2 ( 2404080 3920 ) ( 2416400 * )
- NEW Metal2 ( 2416400 3920 ) ( * 5040 )
- NEW Metal2 ( 2416400 5040 ) ( 2417520 * )
- NEW Metal2 ( 2417520 3920 0 ) ( * 5040 )
- NEW Metal2 ( 2404080 3920 ) ( * 128240 )
- NEW Metal3 ( 1900080 128240 ) ( 2404080 * )
- NEW Metal2 ( 1904560 1690640 ) ( 1906800 * 0 )
- NEW Metal2 ( 1900080 1588720 ) ( 1904560 * )
- NEW Metal2 ( 1900080 128240 ) ( * 1588720 )
- NEW Metal2 ( 1904560 1588720 ) ( * 1690640 )
- NEW Metal2 ( 1900080 128240 ) Via2_VH
- NEW Metal2 ( 2404080 128240 ) Via2_VH ;
- - la_oenb[50] ( PIN la_oenb[50] ) ( mprj la_oenb[50] ) + USE SIGNAL
- + ROUTED Metal3 ( 2679600 1662640 ) ( 2728880 * )
- NEW Metal2 ( 2679600 1662640 ) ( * 1690640 0 )
- NEW Metal2 ( 5040560 3920 ) ( 5043920 * )
- NEW Metal2 ( 5043920 3920 ) ( * 5040 )
- NEW Metal2 ( 5043920 5040 ) ( 5045040 * )
- NEW Metal2 ( 5045040 3920 0 ) ( * 5040 )
- NEW Metal3 ( 2730000 1438640 ) ( 5040560 * )
- NEW Metal2 ( 2728880 1612800 ) ( * 1662640 )
- NEW Metal2 ( 2728880 1612800 ) ( 2730000 * )
- NEW Metal2 ( 2730000 1438640 ) ( * 1612800 )
- NEW Metal2 ( 5040560 3920 ) ( * 1438640 )
- NEW Metal2 ( 2730000 1438640 ) Via2_VH
- NEW Metal2 ( 2728880 1662640 ) Via2_VH
- NEW Metal2 ( 2679600 1662640 ) Via2_VH
- NEW Metal2 ( 5040560 1438640 ) Via2_VH ;
- - la_oenb[51] ( PIN la_oenb[51] ) ( mprj la_oenb[51] ) + USE SIGNAL
- + ROUTED Metal1 ( 2688560 1651440 ) ( 2696400 * )
- NEW Metal2 ( 2696400 1651440 ) ( * 1690640 0 )
- NEW Metal2 ( 5102160 3920 0 ) ( * 44240 )
- NEW Metal3 ( 2688560 44240 ) ( 5102160 * )
- NEW Metal2 ( 2688560 44240 ) ( * 1651440 )
- NEW Metal2 ( 2688560 44240 ) Via2_VH
- NEW Metal1 ( 2688560 1651440 ) Via1_HV
- NEW Metal1 ( 2696400 1651440 ) Via1_HV
- NEW Metal2 ( 5102160 44240 ) Via2_VH ;
- - la_oenb[52] ( PIN la_oenb[52] ) ( mprj la_oenb[52] ) + USE SIGNAL
- + ROUTED Metal2 ( 3032400 160720 ) ( * 1659280 )
- NEW Metal2 ( 5159280 3920 0 ) ( * 160720 )
- NEW Metal2 ( 2713200 1659280 ) ( * 1690640 0 )
- NEW Metal3 ( 2713200 1659280 ) ( 3032400 * )
- NEW Metal3 ( 3032400 160720 ) ( 5159280 * )
- NEW Metal2 ( 3032400 1659280 ) Via2_VH
- NEW Metal2 ( 3032400 160720 ) Via2_VH
- NEW Metal2 ( 5159280 160720 ) Via2_VH
- NEW Metal2 ( 2713200 1659280 ) Via2_VH ;
- - la_oenb[53] ( PIN la_oenb[53] ) ( mprj la_oenb[53] ) + USE SIGNAL
- + ROUTED Metal2 ( 5208560 3920 ) ( 5215280 * )
- NEW Metal2 ( 5215280 3920 ) ( * 5040 )
- NEW Metal2 ( 5215280 5040 ) ( 5216400 * )
- NEW Metal2 ( 5216400 3920 0 ) ( * 5040 )
- NEW Metal2 ( 2880080 1612800 ) ( * 1661520 )
- NEW Metal2 ( 2880080 1612800 ) ( 2881200 * )
- NEW Metal2 ( 2881200 1405040 ) ( * 1612800 )
- NEW Metal2 ( 5208560 3920 ) ( * 1405040 )
- NEW Metal2 ( 2730000 1661520 ) ( * 1690640 0 )
- NEW Metal3 ( 2730000 1661520 ) ( 2880080 * )
- NEW Metal3 ( 2881200 1405040 ) ( 5208560 * )
- NEW Metal2 ( 2881200 1405040 ) Via2_VH
- NEW Metal2 ( 2880080 1661520 ) Via2_VH
- NEW Metal2 ( 5208560 1405040 ) Via2_VH
- NEW Metal2 ( 2730000 1661520 ) Via2_VH ;
- - la_oenb[54] ( PIN la_oenb[54] ) ( mprj la_oenb[54] ) + USE SIGNAL
- + ROUTED Metal3 ( 2738960 1651440 ) ( 2746800 * )
- NEW Metal2 ( 5273520 3920 0 ) ( * 43120 )
- NEW Metal3 ( 2738960 43120 ) ( 5273520 * )
- NEW Metal2 ( 2738960 43120 ) ( * 1651440 )
- NEW Metal2 ( 2746800 1651440 ) ( * 1690640 0 )
- NEW Metal2 ( 2738960 43120 ) Via2_VH
- NEW Metal2 ( 2738960 1651440 ) Via2_VH
- NEW Metal2 ( 2746800 1651440 ) Via2_VH
- NEW Metal2 ( 5273520 43120 ) Via2_VH ;
- - la_oenb[55] ( PIN la_oenb[55] ) ( mprj la_oenb[55] ) + USE SIGNAL
- + ROUTED Metal3 ( 2763600 1650320 ) ( 2780400 * )
- NEW Metal2 ( 5326160 3920 ) ( 5329520 * )
- NEW Metal2 ( 5329520 3920 ) ( * 5040 )
- NEW Metal2 ( 5329520 5040 ) ( 5330640 * )
- NEW Metal2 ( 5330640 3920 0 ) ( * 5040 )
- NEW Metal3 ( 2780400 1387120 ) ( 5326160 * )
- NEW Metal2 ( 2780400 1387120 ) ( * 1650320 )
- NEW Metal2 ( 5326160 3920 ) ( * 1387120 )
- NEW Metal2 ( 2763600 1650320 ) ( * 1690640 0 )
- NEW Metal2 ( 2780400 1387120 ) Via2_VH
- NEW Metal2 ( 2780400 1650320 ) Via2_VH
- NEW Metal2 ( 2763600 1650320 ) Via2_VH
- NEW Metal2 ( 5326160 1387120 ) Via2_VH ;
- - la_oenb[56] ( PIN la_oenb[56] ) ( mprj la_oenb[56] ) + USE SIGNAL
- + ROUTED Metal2 ( 5376560 3920 ) ( 5386640 * )
- NEW Metal2 ( 5386640 3920 ) ( * 5040 )
- NEW Metal2 ( 5386640 5040 ) ( 5387760 * )
- NEW Metal2 ( 5387760 3920 0 ) ( * 5040 )
- NEW Metal2 ( 5376560 3920 ) ( * 1657040 )
- NEW Metal3 ( 2780400 1657040 ) ( 5376560 * )
- NEW Metal2 ( 2780400 1657040 ) ( * 1690640 0 )
- NEW Metal2 ( 5376560 1657040 ) Via2_VH
- NEW Metal2 ( 2780400 1657040 ) Via2_VH ;
- - la_oenb[57] ( PIN la_oenb[57] ) ( mprj la_oenb[57] ) + USE SIGNAL
- + ROUTED Metal3 ( 2789360 1638000 ) ( 2794960 * )
- NEW Metal2 ( 5444880 3920 0 ) ( * 42000 )
- NEW Metal2 ( 2789360 42000 ) ( * 1638000 )
- NEW Metal3 ( 2789360 42000 ) ( 5444880 * )
- NEW Metal2 ( 2794960 1690640 ) ( 2797200 * 0 )
- NEW Metal2 ( 2794960 1638000 ) ( * 1690640 )
- NEW Metal2 ( 2789360 42000 ) Via2_VH
- NEW Metal2 ( 2789360 1638000 ) Via2_VH
- NEW Metal2 ( 2794960 1638000 ) Via2_VH
- NEW Metal2 ( 5444880 42000 ) Via2_VH ;
- - la_oenb[58] ( PIN la_oenb[58] ) ( mprj la_oenb[58] ) + USE SIGNAL
- + ROUTED Metal2 ( 5494160 3920 ) ( 5500880 * )
- NEW Metal2 ( 5500880 3920 ) ( * 5040 )
- NEW Metal2 ( 5500880 5040 ) ( 5502000 * )
- NEW Metal2 ( 5502000 3920 0 ) ( * 5040 )
- NEW Metal3 ( 2814000 1655920 ) ( 5494160 * )
- NEW Metal2 ( 5494160 3920 ) ( * 1655920 )
- NEW Metal2 ( 2814000 1655920 ) ( * 1690640 0 )
- NEW Metal2 ( 2814000 1655920 ) Via2_VH
- NEW Metal2 ( 5494160 1655920 ) Via2_VH ;
- - la_oenb[59] ( PIN la_oenb[59] ) ( mprj la_oenb[59] ) + USE SIGNAL
- + ROUTED Metal2 ( 5544560 3920 ) ( 5558000 * )
- NEW Metal2 ( 5558000 3920 ) ( * 5040 )
- NEW Metal2 ( 5558000 5040 ) ( 5559120 * )
- NEW Metal2 ( 5559120 3920 0 ) ( * 5040 )
- NEW Metal3 ( 2827440 1604400 ) ( 5544560 * )
- NEW Metal2 ( 5544560 3920 ) ( * 1604400 )
- NEW Metal2 ( 2827440 1690640 ) ( 2830800 * 0 )
- NEW Metal2 ( 2827440 1604400 ) ( * 1690640 )
- NEW Metal2 ( 2827440 1604400 ) Via2_VH
- NEW Metal2 ( 5544560 1604400 ) Via2_VH ;
- - la_oenb[5] ( PIN la_oenb[5] ) ( mprj la_oenb[5] ) + USE SIGNAL
- + ROUTED Metal1 ( 1915760 1635760 ) ( 1923600 * )
- NEW Metal2 ( 1915760 44240 ) ( * 1635760 )
- NEW Metal2 ( 2474640 3920 0 ) ( * 44240 )
- NEW Metal3 ( 1915760 44240 ) ( 2474640 * )
- NEW Metal2 ( 1923600 1635760 ) ( * 1690640 0 )
- NEW Metal2 ( 1915760 44240 ) Via2_VH
- NEW Metal1 ( 1915760 1635760 ) Via1_HV
- NEW Metal1 ( 1923600 1635760 ) Via1_HV
- NEW Metal2 ( 2474640 44240 ) Via2_VH ;
- - la_oenb[60] ( PIN la_oenb[60] ) ( mprj la_oenb[60] ) + USE SIGNAL
- + ROUTED Metal2 ( 5616240 3920 0 ) ( * 49840 )
- NEW Metal3 ( 5569200 49840 ) ( 5616240 * )
- NEW Metal2 ( 5569200 49840 ) ( * 1680560 )
- NEW Metal2 ( 2847600 1680560 ) ( * 1690640 0 )
- NEW Metal3 ( 2847600 1680560 ) ( 5569200 * )
- NEW Metal2 ( 5616240 49840 ) Via2_VH
- NEW Metal2 ( 5569200 49840 ) Via2_VH
- NEW Metal2 ( 5569200 1680560 ) Via2_VH
- NEW Metal2 ( 2847600 1680560 ) Via2_VH ;
- - la_oenb[61] ( PIN la_oenb[61] ) ( mprj la_oenb[61] ) + USE SIGNAL
- + ROUTED Metal3 ( 2856560 1651440 ) ( 2862160 * )
- NEW Metal3 ( 5655440 44240 ) ( 5673360 * )
- NEW Metal2 ( 5673360 3920 0 ) ( * 44240 )
- NEW Metal2 ( 2856560 109200 ) ( * 1651440 )
- NEW Metal2 ( 5655440 44240 ) ( * 109200 )
- NEW Metal3 ( 2856560 109200 ) ( 5655440 * )
- NEW Metal2 ( 2862160 1690640 ) ( 2864400 * 0 )
- NEW Metal2 ( 2862160 1651440 ) ( * 1690640 )
- NEW Metal2 ( 2856560 1651440 ) Via2_VH
- NEW Metal2 ( 2862160 1651440 ) Via2_VH
- NEW Metal2 ( 5655440 44240 ) Via2_VH
- NEW Metal2 ( 5673360 44240 ) Via2_VH
- NEW Metal2 ( 2856560 109200 ) Via2_VH
- NEW Metal2 ( 5655440 109200 ) Via2_VH ;
- - la_oenb[62] ( PIN la_oenb[62] ) ( mprj la_oenb[62] ) + USE SIGNAL
- + ROUTED Metal2 ( 3064880 1639120 ) ( * 1660400 )
- NEW Metal3 ( 2881200 1660400 ) ( 3064880 * )
- NEW Metal3 ( 3064880 1639120 ) ( 5729360 * )
- NEW Metal2 ( 5729360 201600 ) ( 5730480 * )
- NEW Metal2 ( 5730480 3920 0 ) ( * 201600 )
- NEW Metal2 ( 5729360 201600 ) ( * 1639120 )
- NEW Metal2 ( 2881200 1660400 ) ( * 1690640 0 )
- NEW Metal2 ( 2881200 1660400 ) Via2_VH
- NEW Metal2 ( 3064880 1660400 ) Via2_VH
- NEW Metal2 ( 3064880 1639120 ) Via2_VH
- NEW Metal2 ( 5729360 1639120 ) Via2_VH ;
- - la_oenb[63] ( PIN la_oenb[63] ) ( mprj la_oenb[63] ) + USE SIGNAL
- + ROUTED Metal2 ( 2890160 176400 ) ( * 1495200 )
- NEW Metal2 ( 2890160 1495200 ) ( 2894640 * )
- NEW Metal2 ( 5779760 3920 ) ( 5786480 * )
- NEW Metal2 ( 5786480 3920 ) ( * 5040 )
- NEW Metal2 ( 5786480 5040 ) ( 5787600 * )
- NEW Metal2 ( 5787600 3920 0 ) ( * 5040 )
- NEW Metal3 ( 2890160 176400 ) ( 5779760 * )
- NEW Metal2 ( 5779760 3920 ) ( * 176400 )
- NEW Metal2 ( 2894640 1690640 ) ( 2898000 * 0 )
- NEW Metal2 ( 2894640 1495200 ) ( * 1690640 )
- NEW Metal2 ( 2890160 176400 ) Via2_VH
- NEW Metal2 ( 5779760 176400 ) Via2_VH ;
- - la_oenb[6] ( PIN la_oenb[6] ) ( mprj la_oenb[6] ) + USE SIGNAL
- + ROUTED Metal1 ( 1932560 1620080 ) ( 1938160 * )
- NEW Metal2 ( 1932560 43120 ) ( * 1620080 )
- NEW Metal2 ( 2531760 3920 0 ) ( * 43120 )
- NEW Metal3 ( 1932560 43120 ) ( 2531760 * )
- NEW Metal2 ( 1938160 1690640 ) ( 1940400 * 0 )
- NEW Metal2 ( 1938160 1620080 ) ( * 1690640 )
- NEW Metal2 ( 1932560 43120 ) Via2_VH
- NEW Metal1 ( 1932560 1620080 ) Via1_HV
- NEW Metal1 ( 1938160 1620080 ) Via1_HV
- NEW Metal2 ( 2531760 43120 ) Via2_VH ;
- - la_oenb[7] ( PIN la_oenb[7] ) ( mprj la_oenb[7] ) + USE SIGNAL
- + ROUTED Metal2 ( 2588880 3920 0 ) ( * 77840 )
- NEW Metal2 ( 2125200 77840 ) ( * 1658160 )
- NEW Metal3 ( 1957200 1658160 ) ( 2125200 * )
- NEW Metal3 ( 2125200 77840 ) ( 2588880 * )
- NEW Metal2 ( 1957200 1658160 ) ( * 1690640 0 )
- NEW Metal2 ( 1957200 1658160 ) Via2_VH
- NEW Metal2 ( 2125200 77840 ) Via2_VH
- NEW Metal2 ( 2125200 1658160 ) Via2_VH
- NEW Metal2 ( 2588880 77840 ) Via2_VH ;
- - la_oenb[8] ( PIN la_oenb[8] ) ( mprj la_oenb[8] ) + USE SIGNAL
- + ROUTED Metal2 ( 2646000 3920 0 ) ( * 58800 )
- NEW Metal3 ( 1966160 1651440 ) ( 1974000 * )
- NEW Metal3 ( 1966160 58800 ) ( 2646000 * )
- NEW Metal2 ( 1966160 58800 ) ( * 1651440 )
- NEW Metal2 ( 1974000 1651440 ) ( * 1690640 0 )
- NEW Metal2 ( 2646000 58800 ) Via2_VH
- NEW Metal2 ( 1966160 58800 ) Via2_VH
- NEW Metal2 ( 1966160 1651440 ) Via2_VH
- NEW Metal2 ( 1974000 1651440 ) Via2_VH ;
- - la_oenb[9] ( PIN la_oenb[9] ) ( mprj la_oenb[9] ) + USE SIGNAL
- + ROUTED Metal1 ( 1982960 1613360 ) ( 1988560 * )
- NEW Metal2 ( 2703120 3920 0 ) ( * 42000 )
- NEW Metal3 ( 1982960 42000 ) ( 2703120 * )
- NEW Metal2 ( 1982960 42000 ) ( * 1613360 )
- NEW Metal2 ( 1988560 1690640 ) ( 1990800 * 0 )
- NEW Metal2 ( 1988560 1613360 ) ( * 1690640 )
- NEW Metal2 ( 1982960 42000 ) Via2_VH
- NEW Metal1 ( 1982960 1613360 ) Via1_HV
- NEW Metal1 ( 1988560 1613360 ) Via1_HV
- NEW Metal2 ( 2703120 42000 ) Via2_VH ;
+ NEW Metal2 ( 1158640 1851920 ) Via2_VH
+ NEW Metal2 ( 1158640 3797360 ) Via2_VH ;
+ - la_data_in[0] ( PIN la_data_in[0] ) + USE SIGNAL ;
+ - la_data_in[10] ( PIN la_data_in[10] ) + USE SIGNAL ;
+ - la_data_in[11] ( PIN la_data_in[11] ) + USE SIGNAL ;
+ - la_data_in[12] ( PIN la_data_in[12] ) + USE SIGNAL ;
+ - la_data_in[13] ( PIN la_data_in[13] ) + USE SIGNAL ;
+ - la_data_in[14] ( PIN la_data_in[14] ) + USE SIGNAL ;
+ - la_data_in[15] ( PIN la_data_in[15] ) + USE SIGNAL ;
+ - la_data_in[16] ( PIN la_data_in[16] ) + USE SIGNAL ;
+ - la_data_in[17] ( PIN la_data_in[17] ) + USE SIGNAL ;
+ - la_data_in[18] ( PIN la_data_in[18] ) + USE SIGNAL ;
+ - la_data_in[19] ( PIN la_data_in[19] ) + USE SIGNAL ;
+ - la_data_in[1] ( PIN la_data_in[1] ) + USE SIGNAL ;
+ - la_data_in[20] ( PIN la_data_in[20] ) + USE SIGNAL ;
+ - la_data_in[21] ( PIN la_data_in[21] ) + USE SIGNAL ;
+ - la_data_in[22] ( PIN la_data_in[22] ) + USE SIGNAL ;
+ - la_data_in[23] ( PIN la_data_in[23] ) + USE SIGNAL ;
+ - la_data_in[24] ( PIN la_data_in[24] ) + USE SIGNAL ;
+ - la_data_in[25] ( PIN la_data_in[25] ) + USE SIGNAL ;
+ - la_data_in[26] ( PIN la_data_in[26] ) + USE SIGNAL ;
+ - la_data_in[27] ( PIN la_data_in[27] ) + USE SIGNAL ;
+ - la_data_in[28] ( PIN la_data_in[28] ) + USE SIGNAL ;
+ - la_data_in[29] ( PIN la_data_in[29] ) + USE SIGNAL ;
+ - la_data_in[2] ( PIN la_data_in[2] ) + USE SIGNAL ;
+ - la_data_in[30] ( PIN la_data_in[30] ) + USE SIGNAL ;
+ - la_data_in[31] ( PIN la_data_in[31] ) + USE SIGNAL ;
+ - la_data_in[32] ( PIN la_data_in[32] ) + USE SIGNAL ;
+ - la_data_in[33] ( PIN la_data_in[33] ) + USE SIGNAL ;
+ - la_data_in[34] ( PIN la_data_in[34] ) + USE SIGNAL ;
+ - la_data_in[35] ( PIN la_data_in[35] ) + USE SIGNAL ;
+ - la_data_in[36] ( PIN la_data_in[36] ) + USE SIGNAL ;
+ - la_data_in[37] ( PIN la_data_in[37] ) + USE SIGNAL ;
+ - la_data_in[38] ( PIN la_data_in[38] ) + USE SIGNAL ;
+ - la_data_in[39] ( PIN la_data_in[39] ) + USE SIGNAL ;
+ - la_data_in[3] ( PIN la_data_in[3] ) + USE SIGNAL ;
+ - la_data_in[40] ( PIN la_data_in[40] ) + USE SIGNAL ;
+ - la_data_in[41] ( PIN la_data_in[41] ) + USE SIGNAL ;
+ - la_data_in[42] ( PIN la_data_in[42] ) + USE SIGNAL ;
+ - la_data_in[43] ( PIN la_data_in[43] ) + USE SIGNAL ;
+ - la_data_in[44] ( PIN la_data_in[44] ) + USE SIGNAL ;
+ - la_data_in[45] ( PIN la_data_in[45] ) + USE SIGNAL ;
+ - la_data_in[46] ( PIN la_data_in[46] ) + USE SIGNAL ;
+ - la_data_in[47] ( PIN la_data_in[47] ) + USE SIGNAL ;
+ - la_data_in[48] ( PIN la_data_in[48] ) + USE SIGNAL ;
+ - la_data_in[49] ( PIN la_data_in[49] ) + USE SIGNAL ;
+ - la_data_in[4] ( PIN la_data_in[4] ) + USE SIGNAL ;
+ - la_data_in[50] ( PIN la_data_in[50] ) + USE SIGNAL ;
+ - la_data_in[51] ( PIN la_data_in[51] ) + USE SIGNAL ;
+ - la_data_in[52] ( PIN la_data_in[52] ) + USE SIGNAL ;
+ - la_data_in[53] ( PIN la_data_in[53] ) + USE SIGNAL ;
+ - la_data_in[54] ( PIN la_data_in[54] ) + USE SIGNAL ;
+ - la_data_in[55] ( PIN la_data_in[55] ) + USE SIGNAL ;
+ - la_data_in[56] ( PIN la_data_in[56] ) + USE SIGNAL ;
+ - la_data_in[57] ( PIN la_data_in[57] ) + USE SIGNAL ;
+ - la_data_in[58] ( PIN la_data_in[58] ) + USE SIGNAL ;
+ - la_data_in[59] ( PIN la_data_in[59] ) + USE SIGNAL ;
+ - la_data_in[5] ( PIN la_data_in[5] ) + USE SIGNAL ;
+ - la_data_in[60] ( PIN la_data_in[60] ) + USE SIGNAL ;
+ - la_data_in[61] ( PIN la_data_in[61] ) + USE SIGNAL ;
+ - la_data_in[62] ( PIN la_data_in[62] ) + USE SIGNAL ;
+ - la_data_in[63] ( PIN la_data_in[63] ) + USE SIGNAL ;
+ - la_data_in[6] ( PIN la_data_in[6] ) + USE SIGNAL ;
+ - la_data_in[7] ( PIN la_data_in[7] ) + USE SIGNAL ;
+ - la_data_in[8] ( PIN la_data_in[8] ) + USE SIGNAL ;
+ - la_data_in[9] ( PIN la_data_in[9] ) + USE SIGNAL ;
+ - la_data_out[0] ( PIN la_data_out[0] ) + USE SIGNAL ;
+ - la_data_out[10] ( PIN la_data_out[10] ) + USE SIGNAL ;
+ - la_data_out[11] ( PIN la_data_out[11] ) + USE SIGNAL ;
+ - la_data_out[12] ( PIN la_data_out[12] ) + USE SIGNAL ;
+ - la_data_out[13] ( PIN la_data_out[13] ) + USE SIGNAL ;
+ - la_data_out[14] ( PIN la_data_out[14] ) + USE SIGNAL ;
+ - la_data_out[15] ( PIN la_data_out[15] ) + USE SIGNAL ;
+ - la_data_out[16] ( PIN la_data_out[16] ) + USE SIGNAL ;
+ - la_data_out[17] ( PIN la_data_out[17] ) + USE SIGNAL ;
+ - la_data_out[18] ( PIN la_data_out[18] ) + USE SIGNAL ;
+ - la_data_out[19] ( PIN la_data_out[19] ) + USE SIGNAL ;
+ - la_data_out[1] ( PIN la_data_out[1] ) + USE SIGNAL ;
+ - la_data_out[20] ( PIN la_data_out[20] ) + USE SIGNAL ;
+ - la_data_out[21] ( PIN la_data_out[21] ) + USE SIGNAL ;
+ - la_data_out[22] ( PIN la_data_out[22] ) + USE SIGNAL ;
+ - la_data_out[23] ( PIN la_data_out[23] ) + USE SIGNAL ;
+ - la_data_out[24] ( PIN la_data_out[24] ) + USE SIGNAL ;
+ - la_data_out[25] ( PIN la_data_out[25] ) + USE SIGNAL ;
+ - la_data_out[26] ( PIN la_data_out[26] ) + USE SIGNAL ;
+ - la_data_out[27] ( PIN la_data_out[27] ) + USE SIGNAL ;
+ - la_data_out[28] ( PIN la_data_out[28] ) + USE SIGNAL ;
+ - la_data_out[29] ( PIN la_data_out[29] ) + USE SIGNAL ;
+ - la_data_out[2] ( PIN la_data_out[2] ) + USE SIGNAL ;
+ - la_data_out[30] ( PIN la_data_out[30] ) + USE SIGNAL ;
+ - la_data_out[31] ( PIN la_data_out[31] ) + USE SIGNAL ;
+ - la_data_out[32] ( PIN la_data_out[32] ) + USE SIGNAL ;
+ - la_data_out[33] ( PIN la_data_out[33] ) + USE SIGNAL ;
+ - la_data_out[34] ( PIN la_data_out[34] ) + USE SIGNAL ;
+ - la_data_out[35] ( PIN la_data_out[35] ) + USE SIGNAL ;
+ - la_data_out[36] ( PIN la_data_out[36] ) + USE SIGNAL ;
+ - la_data_out[37] ( PIN la_data_out[37] ) + USE SIGNAL ;
+ - la_data_out[38] ( PIN la_data_out[38] ) + USE SIGNAL ;
+ - la_data_out[39] ( PIN la_data_out[39] ) + USE SIGNAL ;
+ - la_data_out[3] ( PIN la_data_out[3] ) + USE SIGNAL ;
+ - la_data_out[40] ( PIN la_data_out[40] ) + USE SIGNAL ;
+ - la_data_out[41] ( PIN la_data_out[41] ) + USE SIGNAL ;
+ - la_data_out[42] ( PIN la_data_out[42] ) + USE SIGNAL ;
+ - la_data_out[43] ( PIN la_data_out[43] ) + USE SIGNAL ;
+ - la_data_out[44] ( PIN la_data_out[44] ) + USE SIGNAL ;
+ - la_data_out[45] ( PIN la_data_out[45] ) + USE SIGNAL ;
+ - la_data_out[46] ( PIN la_data_out[46] ) + USE SIGNAL ;
+ - la_data_out[47] ( PIN la_data_out[47] ) + USE SIGNAL ;
+ - la_data_out[48] ( PIN la_data_out[48] ) + USE SIGNAL ;
+ - la_data_out[49] ( PIN la_data_out[49] ) + USE SIGNAL ;
+ - la_data_out[4] ( PIN la_data_out[4] ) + USE SIGNAL ;
+ - la_data_out[50] ( PIN la_data_out[50] ) + USE SIGNAL ;
+ - la_data_out[51] ( PIN la_data_out[51] ) + USE SIGNAL ;
+ - la_data_out[52] ( PIN la_data_out[52] ) + USE SIGNAL ;
+ - la_data_out[53] ( PIN la_data_out[53] ) + USE SIGNAL ;
+ - la_data_out[54] ( PIN la_data_out[54] ) + USE SIGNAL ;
+ - la_data_out[55] ( PIN la_data_out[55] ) + USE SIGNAL ;
+ - la_data_out[56] ( PIN la_data_out[56] ) + USE SIGNAL ;
+ - la_data_out[57] ( PIN la_data_out[57] ) + USE SIGNAL ;
+ - la_data_out[58] ( PIN la_data_out[58] ) + USE SIGNAL ;
+ - la_data_out[59] ( PIN la_data_out[59] ) + USE SIGNAL ;
+ - la_data_out[5] ( PIN la_data_out[5] ) + USE SIGNAL ;
+ - la_data_out[60] ( PIN la_data_out[60] ) + USE SIGNAL ;
+ - la_data_out[61] ( PIN la_data_out[61] ) + USE SIGNAL ;
+ - la_data_out[62] ( PIN la_data_out[62] ) + USE SIGNAL ;
+ - la_data_out[63] ( PIN la_data_out[63] ) + USE SIGNAL ;
+ - la_data_out[6] ( PIN la_data_out[6] ) + USE SIGNAL ;
+ - la_data_out[7] ( PIN la_data_out[7] ) + USE SIGNAL ;
+ - la_data_out[8] ( PIN la_data_out[8] ) + USE SIGNAL ;
+ - la_data_out[9] ( PIN la_data_out[9] ) + USE SIGNAL ;
+ - la_oenb[0] ( PIN la_oenb[0] ) + USE SIGNAL ;
+ - la_oenb[10] ( PIN la_oenb[10] ) + USE SIGNAL ;
+ - la_oenb[11] ( PIN la_oenb[11] ) + USE SIGNAL ;
+ - la_oenb[12] ( PIN la_oenb[12] ) + USE SIGNAL ;
+ - la_oenb[13] ( PIN la_oenb[13] ) + USE SIGNAL ;
+ - la_oenb[14] ( PIN la_oenb[14] ) + USE SIGNAL ;
+ - la_oenb[15] ( PIN la_oenb[15] ) + USE SIGNAL ;
+ - la_oenb[16] ( PIN la_oenb[16] ) + USE SIGNAL ;
+ - la_oenb[17] ( PIN la_oenb[17] ) + USE SIGNAL ;
+ - la_oenb[18] ( PIN la_oenb[18] ) + USE SIGNAL ;
+ - la_oenb[19] ( PIN la_oenb[19] ) + USE SIGNAL ;
+ - la_oenb[1] ( PIN la_oenb[1] ) + USE SIGNAL ;
+ - la_oenb[20] ( PIN la_oenb[20] ) + USE SIGNAL ;
+ - la_oenb[21] ( PIN la_oenb[21] ) + USE SIGNAL ;
+ - la_oenb[22] ( PIN la_oenb[22] ) + USE SIGNAL ;
+ - la_oenb[23] ( PIN la_oenb[23] ) + USE SIGNAL ;
+ - la_oenb[24] ( PIN la_oenb[24] ) + USE SIGNAL ;
+ - la_oenb[25] ( PIN la_oenb[25] ) + USE SIGNAL ;
+ - la_oenb[26] ( PIN la_oenb[26] ) + USE SIGNAL ;
+ - la_oenb[27] ( PIN la_oenb[27] ) + USE SIGNAL ;
+ - la_oenb[28] ( PIN la_oenb[28] ) + USE SIGNAL ;
+ - la_oenb[29] ( PIN la_oenb[29] ) + USE SIGNAL ;
+ - la_oenb[2] ( PIN la_oenb[2] ) + USE SIGNAL ;
+ - la_oenb[30] ( PIN la_oenb[30] ) + USE SIGNAL ;
+ - la_oenb[31] ( PIN la_oenb[31] ) + USE SIGNAL ;
+ - la_oenb[32] ( PIN la_oenb[32] ) + USE SIGNAL ;
+ - la_oenb[33] ( PIN la_oenb[33] ) + USE SIGNAL ;
+ - la_oenb[34] ( PIN la_oenb[34] ) + USE SIGNAL ;
+ - la_oenb[35] ( PIN la_oenb[35] ) + USE SIGNAL ;
+ - la_oenb[36] ( PIN la_oenb[36] ) + USE SIGNAL ;
+ - la_oenb[37] ( PIN la_oenb[37] ) + USE SIGNAL ;
+ - la_oenb[38] ( PIN la_oenb[38] ) + USE SIGNAL ;
+ - la_oenb[39] ( PIN la_oenb[39] ) + USE SIGNAL ;
+ - la_oenb[3] ( PIN la_oenb[3] ) + USE SIGNAL ;
+ - la_oenb[40] ( PIN la_oenb[40] ) + USE SIGNAL ;
+ - la_oenb[41] ( PIN la_oenb[41] ) + USE SIGNAL ;
+ - la_oenb[42] ( PIN la_oenb[42] ) + USE SIGNAL ;
+ - la_oenb[43] ( PIN la_oenb[43] ) + USE SIGNAL ;
+ - la_oenb[44] ( PIN la_oenb[44] ) + USE SIGNAL ;
+ - la_oenb[45] ( PIN la_oenb[45] ) + USE SIGNAL ;
+ - la_oenb[46] ( PIN la_oenb[46] ) + USE SIGNAL ;
+ - la_oenb[47] ( PIN la_oenb[47] ) + USE SIGNAL ;
+ - la_oenb[48] ( PIN la_oenb[48] ) + USE SIGNAL ;
+ - la_oenb[49] ( PIN la_oenb[49] ) + USE SIGNAL ;
+ - la_oenb[4] ( PIN la_oenb[4] ) + USE SIGNAL ;
+ - la_oenb[50] ( PIN la_oenb[50] ) + USE SIGNAL ;
+ - la_oenb[51] ( PIN la_oenb[51] ) + USE SIGNAL ;
+ - la_oenb[52] ( PIN la_oenb[52] ) + USE SIGNAL ;
+ - la_oenb[53] ( PIN la_oenb[53] ) + USE SIGNAL ;
+ - la_oenb[54] ( PIN la_oenb[54] ) + USE SIGNAL ;
+ - la_oenb[55] ( PIN la_oenb[55] ) + USE SIGNAL ;
+ - la_oenb[56] ( PIN la_oenb[56] ) + USE SIGNAL ;
+ - la_oenb[57] ( PIN la_oenb[57] ) + USE SIGNAL ;
+ - la_oenb[58] ( PIN la_oenb[58] ) + USE SIGNAL ;
+ - la_oenb[59] ( PIN la_oenb[59] ) + USE SIGNAL ;
+ - la_oenb[5] ( PIN la_oenb[5] ) + USE SIGNAL ;
+ - la_oenb[60] ( PIN la_oenb[60] ) + USE SIGNAL ;
+ - la_oenb[61] ( PIN la_oenb[61] ) + USE SIGNAL ;
+ - la_oenb[62] ( PIN la_oenb[62] ) + USE SIGNAL ;
+ - la_oenb[63] ( PIN la_oenb[63] ) + USE SIGNAL ;
+ - la_oenb[6] ( PIN la_oenb[6] ) + USE SIGNAL ;
+ - la_oenb[7] ( PIN la_oenb[7] ) + USE SIGNAL ;
+ - la_oenb[8] ( PIN la_oenb[8] ) + USE SIGNAL ;
+ - la_oenb[9] ( PIN la_oenb[9] ) + USE SIGNAL ;
- user_clock2 ( PIN user_clock2 ) + USE SIGNAL ;
- - user_irq[0] ( PIN user_irq[0] ) ( mprj irq[0] ) + USE SIGNAL
- + ROUTED Metal2 ( 5619600 42000 ) ( * 1654800 )
- NEW Metal3 ( 2903600 1654800 ) ( 5619600 * )
- NEW Metal2 ( 5825680 3920 0 ) ( * 42000 )
- NEW Metal3 ( 5619600 42000 ) ( 5825680 * )
- NEW Metal2 ( 2903600 1654800 ) ( * 1690640 0 )
- NEW Metal2 ( 2903600 1654800 ) Via2_VH
- NEW Metal2 ( 5619600 42000 ) Via2_VH
- NEW Metal2 ( 5619600 1654800 ) Via2_VH
- NEW Metal2 ( 5825680 42000 ) Via2_VH ;
- - user_irq[1] ( PIN user_irq[1] ) ( mprj irq[1] ) + USE SIGNAL
- + ROUTED Metal2 ( 5830160 3920 ) ( 5843600 * )
- NEW Metal2 ( 5843600 3920 ) ( * 5040 )
- NEW Metal2 ( 5843600 5040 ) ( 5844720 * )
- NEW Metal2 ( 5844720 3920 0 ) ( * 5040 )
- NEW Metal3 ( 2906960 1436400 ) ( 5830160 * )
- NEW Metal2 ( 5830160 3920 ) ( * 1436400 )
- NEW Metal2 ( 2906960 1690640 ) ( 2909200 * 0 )
- NEW Metal2 ( 2906960 1436400 ) ( * 1690640 )
- NEW Metal2 ( 2906960 1436400 ) Via2_VH
- NEW Metal2 ( 5830160 1436400 ) Via2_VH ;
- - user_irq[2] ( PIN user_irq[2] ) ( mprj irq[2] ) + USE SIGNAL
- + ROUTED Metal2 ( 5863760 3920 0 ) ( * 58800 )
- NEW Metal3 ( 2914800 1658160 ) ( 3704400 * )
- NEW Metal3 ( 3704400 58800 ) ( 5863760 * )
- NEW Metal2 ( 3704400 58800 ) ( * 1658160 )
- NEW Metal2 ( 2914800 1658160 ) ( * 1690640 0 )
- NEW Metal2 ( 5863760 58800 ) Via2_VH
- NEW Metal2 ( 2914800 1658160 ) Via2_VH
- NEW Metal2 ( 3704400 58800 ) Via2_VH
- NEW Metal2 ( 3704400 1658160 ) Via2_VH ;
- - wb_clk_i ( PIN wb_clk_i ) ( mprj wb_clk_i ) + USE SIGNAL
- + ROUTED Metal2 ( 1229200 1690640 ) ( 1234800 * 0 )
- NEW Metal2 ( 1229200 1470000 ) ( * 1690640 )
- NEW Metal2 ( 118160 3920 ) ( 131600 * )
+ - user_irq[0] ( PIN user_irq[0] ) + USE SIGNAL ;
+ - user_irq[1] ( PIN user_irq[1] ) + USE SIGNAL ;
+ - user_irq[2] ( PIN user_irq[2] ) + USE SIGNAL ;
+ - wb_clk_i ( PIN wb_clk_i ) ( wrapped_vga_clock wb_clk_i ) + USE SIGNAL
+ + ROUTED Metal2 ( 118160 3920 ) ( 131600 * )
NEW Metal2 ( 131600 3920 ) ( * 5040 )
NEW Metal2 ( 131600 5040 ) ( 132720 * )
NEW Metal2 ( 132720 3920 0 ) ( * 5040 )
- NEW Metal3 ( 118160 1470000 ) ( 1229200 * )
- NEW Metal2 ( 118160 3920 ) ( * 1470000 )
- NEW Metal2 ( 1229200 1470000 ) Via2_VH
- NEW Metal2 ( 118160 1470000 ) Via2_VH ;
- - wb_rst_i ( PIN wb_rst_i ) ( mprj wb_rst_i ) + USE SIGNAL
- + ROUTED Metal3 ( 1228080 1690640 ) ( 1237040 * )
- NEW Metal2 ( 1237040 1690640 ) ( 1240400 * 0 )
- NEW Metal2 ( 1228080 159600 ) ( * 1690640 )
- NEW Metal2 ( 151760 3920 0 ) ( * 159600 )
- NEW Metal3 ( 151760 159600 ) ( 1228080 * )
- NEW Metal2 ( 1228080 1690640 ) Via2_VH
- NEW Metal2 ( 1237040 1690640 ) Via2_VH
- NEW Metal2 ( 1228080 159600 ) Via2_VH
- NEW Metal2 ( 151760 159600 ) Via2_VH ;
- - wbs_ack_o ( PIN wbs_ack_o ) ( mprj wbs_ack_o ) + USE SIGNAL
- + ROUTED Metal2 ( 1244880 1651440 ) ( 1246000 * )
- NEW Metal2 ( 1246000 1651440 ) ( * 1690640 0 )
- NEW Metal2 ( 1244880 1436400 ) ( * 1651440 )
- NEW Metal3 ( 168560 1436400 ) ( 1244880 * )
- NEW Metal2 ( 168560 201600 ) ( 170800 * )
- NEW Metal2 ( 170800 3920 0 ) ( * 201600 )
- NEW Metal2 ( 168560 201600 ) ( * 1436400 )
- NEW Metal2 ( 1244880 1436400 ) Via2_VH
- NEW Metal2 ( 168560 1436400 ) Via2_VH ;
- - wbs_adr_i[0] ( PIN wbs_adr_i[0] ) ( mprj wbs_adr_i[0] ) + USE SIGNAL
- + ROUTED Metal2 ( 235760 3920 ) ( 245840 * )
- NEW Metal2 ( 245840 3920 ) ( * 5040 )
- NEW Metal2 ( 245840 5040 ) ( 246960 * )
- NEW Metal2 ( 246960 3920 0 ) ( * 5040 )
- NEW Metal2 ( 235760 3920 ) ( * 1638000 )
- NEW Metal2 ( 1265040 1638000 ) ( * 1690640 )
- NEW Metal2 ( 1265040 1690640 ) ( 1268400 * 0 )
- NEW Metal3 ( 235760 1638000 ) ( 1265040 * )
- NEW Metal2 ( 235760 1638000 ) Via2_VH
- NEW Metal2 ( 1265040 1638000 ) Via2_VH ;
- - wbs_adr_i[10] ( PIN wbs_adr_i[10] ) ( mprj wbs_adr_i[10] ) + USE SIGNAL
- + ROUTED Metal2 ( 1452080 1652560 ) ( 1455440 * )
- NEW Metal2 ( 1455440 1652560 ) ( * 1690640 )
- NEW Metal2 ( 1455440 1690640 ) ( 1458800 * 0 )
- NEW Metal2 ( 915600 49840 ) ( * 1503600 )
- NEW Metal2 ( 1452080 1503600 ) ( * 1652560 )
- NEW Metal2 ( 896560 3920 0 ) ( * 49840 )
- NEW Metal3 ( 896560 49840 ) ( 915600 * )
- NEW Metal3 ( 915600 1503600 ) ( 1452080 * )
- NEW Metal2 ( 915600 49840 ) Via2_VH
- NEW Metal2 ( 915600 1503600 ) Via2_VH
- NEW Metal2 ( 1452080 1503600 ) Via2_VH
- NEW Metal2 ( 896560 49840 ) Via2_VH ;
- - wbs_adr_i[11] ( PIN wbs_adr_i[11] ) ( mprj wbs_adr_i[11] ) + USE SIGNAL
- + ROUTED Metal2 ( 953680 3920 0 ) ( * 40880 )
- NEW Metal3 ( 953680 40880 ) ( 1016400 * )
- NEW Metal2 ( 1475600 1641360 ) ( * 1690640 0 )
- NEW Metal2 ( 1016400 40880 ) ( * 1641360 )
- NEW Metal3 ( 1016400 1641360 ) ( 1475600 * )
- NEW Metal2 ( 953680 40880 ) Via2_VH
- NEW Metal2 ( 1016400 40880 ) Via2_VH
- NEW Metal2 ( 1016400 1641360 ) Via2_VH
- NEW Metal2 ( 1475600 1641360 ) Via2_VH ;
- - wbs_adr_i[12] ( PIN wbs_adr_i[12] ) ( mprj wbs_adr_i[12] ) + USE SIGNAL
- + ROUTED Metal2 ( 1010800 3920 0 ) ( * 47600 )
- NEW Metal2 ( 1492400 1642480 ) ( * 1690640 0 )
- NEW Metal3 ( 1010800 47600 ) ( 1083600 * )
- NEW Metal2 ( 1083600 47600 ) ( * 1642480 )
- NEW Metal3 ( 1083600 1642480 ) ( 1492400 * )
- NEW Metal2 ( 1010800 47600 ) Via2_VH
- NEW Metal2 ( 1492400 1642480 ) Via2_VH
- NEW Metal2 ( 1083600 47600 ) Via2_VH
- NEW Metal2 ( 1083600 1642480 ) Via2_VH ;
- - wbs_adr_i[13] ( PIN wbs_adr_i[13] ) ( mprj wbs_adr_i[13] ) + USE SIGNAL
- + ROUTED Metal2 ( 1058960 3920 ) ( 1064560 * )
- NEW Metal2 ( 1064560 3920 ) ( * 5040 )
- NEW Metal2 ( 1064560 5040 ) ( 1065680 * )
- NEW Metal2 ( 1065680 3920 0 ) ( * 5040 )
- NEW Metal3 ( 1058960 1471120 ) ( 1498000 * )
- NEW Metal2 ( 1505840 1690640 ) ( 1509200 * 0 )
- NEW Metal2 ( 1058960 3920 ) ( * 1471120 )
- NEW Metal2 ( 1498000 1471120 ) ( * 1495200 )
- NEW Metal2 ( 1498000 1495200 ) ( 1505840 * )
- NEW Metal2 ( 1505840 1495200 ) ( * 1690640 )
- NEW Metal2 ( 1058960 1471120 ) Via2_VH
- NEW Metal2 ( 1498000 1471120 ) Via2_VH ;
- - wbs_adr_i[14] ( PIN wbs_adr_i[14] ) ( mprj wbs_adr_i[14] ) + USE SIGNAL
- + ROUTED Metal2 ( 1109360 3920 ) ( 1121680 * )
- NEW Metal2 ( 1121680 3920 ) ( * 5040 )
- NEW Metal2 ( 1121680 5040 ) ( 1122800 * )
- NEW Metal2 ( 1122800 3920 0 ) ( * 5040 )
- NEW Metal2 ( 1526000 1623440 ) ( * 1690640 0 )
- NEW Metal2 ( 1109360 3920 ) ( * 1623440 )
- NEW Metal3 ( 1109360 1623440 ) ( 1526000 * )
- NEW Metal2 ( 1109360 1623440 ) Via2_VH
- NEW Metal2 ( 1526000 1623440 ) Via2_VH ;
- - wbs_adr_i[15] ( PIN wbs_adr_i[15] ) ( mprj wbs_adr_i[15] ) + USE SIGNAL
- + ROUTED Metal2 ( 1182160 3920 0 ) ( * 40880 )
- NEW Metal3 ( 1182160 40880 ) ( 1201200 * )
- NEW Metal2 ( 1201200 40880 ) ( * 1643600 )
- NEW Metal2 ( 1542800 1643600 ) ( * 1690640 0 )
- NEW Metal3 ( 1201200 1643600 ) ( 1542800 * )
- NEW Metal2 ( 1182160 40880 ) Via2_VH
- NEW Metal2 ( 1201200 40880 ) Via2_VH
- NEW Metal2 ( 1201200 1643600 ) Via2_VH
- NEW Metal2 ( 1542800 1643600 ) Via2_VH ;
- - wbs_adr_i[16] ( PIN wbs_adr_i[16] ) ( mprj wbs_adr_i[16] ) + USE SIGNAL
- + ROUTED Metal2 ( 1226960 3920 ) ( 1235920 * )
- NEW Metal2 ( 1235920 3920 ) ( * 5040 )
- NEW Metal2 ( 1235920 5040 ) ( 1237040 * )
- NEW Metal2 ( 1237040 3920 0 ) ( * 5040 )
- NEW Metal2 ( 1226960 3920 ) ( * 1644720 )
- NEW Metal2 ( 1559600 1644720 ) ( * 1690640 0 )
- NEW Metal3 ( 1226960 1644720 ) ( 1559600 * )
- NEW Metal2 ( 1226960 1644720 ) Via2_VH
- NEW Metal2 ( 1559600 1644720 ) Via2_VH ;
- - wbs_adr_i[17] ( PIN wbs_adr_i[17] ) ( mprj wbs_adr_i[17] ) + USE SIGNAL
- + ROUTED Metal3 ( 1564080 1618960 ) ( 1573040 * )
- NEW Metal2 ( 1295280 3920 0 ) ( * 1504720 )
- NEW Metal3 ( 1295280 1504720 ) ( 1564080 * )
- NEW Metal2 ( 1564080 1504720 ) ( * 1618960 )
- NEW Metal2 ( 1573040 1690640 ) ( 1576400 * 0 )
- NEW Metal2 ( 1573040 1618960 ) ( * 1690640 )
- NEW Metal2 ( 1564080 1618960 ) Via2_VH
- NEW Metal2 ( 1573040 1618960 ) Via2_VH
- NEW Metal2 ( 1295280 1504720 ) Via2_VH
- NEW Metal2 ( 1564080 1504720 ) Via2_VH ;
- - wbs_adr_i[18] ( PIN wbs_adr_i[18] ) ( mprj wbs_adr_i[18] ) + USE SIGNAL
- + ROUTED Metal2 ( 1353520 3920 0 ) ( * 42000 )
- NEW Metal3 ( 1353520 42000 ) ( 1370320 * )
- NEW Metal2 ( 1586480 1651440 ) ( 1589840 * )
- NEW Metal2 ( 1370320 42000 ) ( * 177520 )
- NEW Metal3 ( 1370320 177520 ) ( 1582000 * )
- NEW Metal2 ( 1582000 177520 ) ( * 1495200 )
- NEW Metal2 ( 1582000 1495200 ) ( 1586480 * )
- NEW Metal2 ( 1586480 1495200 ) ( * 1651440 )
- NEW Metal2 ( 1589840 1690640 ) ( 1593200 * 0 )
- NEW Metal2 ( 1589840 1651440 ) ( * 1690640 )
- NEW Metal2 ( 1353520 42000 ) Via2_VH
- NEW Metal2 ( 1370320 42000 ) Via2_VH
- NEW Metal2 ( 1370320 177520 ) Via2_VH
- NEW Metal2 ( 1582000 177520 ) Via2_VH ;
- - wbs_adr_i[19] ( PIN wbs_adr_i[19] ) ( mprj wbs_adr_i[19] ) + USE SIGNAL
- + ROUTED Metal2 ( 1394960 3920 ) ( 1407280 * )
- NEW Metal2 ( 1407280 3920 ) ( * 5040 )
- NEW Metal2 ( 1407280 5040 ) ( 1408400 * )
- NEW Metal2 ( 1408400 3920 0 ) ( * 5040 )
- NEW Metal2 ( 1394960 3920 ) ( * 1654800 )
- NEW Metal3 ( 1394960 1654800 ) ( 1610000 * )
- NEW Metal2 ( 1610000 1654800 ) ( * 1690640 0 )
- NEW Metal2 ( 1610000 1654800 ) Via2_VH
- NEW Metal2 ( 1394960 1654800 ) Via2_VH ;
- - wbs_adr_i[1] ( PIN wbs_adr_i[1] ) ( mprj wbs_adr_i[1] ) + USE SIGNAL
- + ROUTED Metal2 ( 319760 3920 ) ( 322000 * )
- NEW Metal2 ( 322000 3920 ) ( * 5040 )
- NEW Metal2 ( 322000 5040 ) ( 323120 * )
- NEW Metal2 ( 323120 3920 0 ) ( * 5040 )
- NEW Metal2 ( 1290800 1621200 ) ( * 1690640 0 )
- NEW Metal3 ( 319760 1621200 ) ( 1290800 * )
- NEW Metal2 ( 319760 3920 ) ( * 1621200 )
- NEW Metal2 ( 319760 1621200 ) Via2_VH
- NEW Metal2 ( 1290800 1621200 ) Via2_VH ;
- - wbs_adr_i[20] ( PIN wbs_adr_i[20] ) ( mprj wbs_adr_i[20] ) + USE SIGNAL
- + ROUTED Metal2 ( 1462160 3920 ) ( 1464400 * )
- NEW Metal2 ( 1464400 3920 ) ( * 5040 )
- NEW Metal2 ( 1464400 5040 ) ( 1465520 * )
- NEW Metal2 ( 1465520 3920 0 ) ( * 5040 )
- NEW Metal1 ( 1614480 1616720 ) ( 1623440 * )
- NEW Metal2 ( 1462160 3920 ) ( * 159600 )
- NEW Metal2 ( 1614480 159600 ) ( * 1616720 )
- NEW Metal3 ( 1462160 159600 ) ( 1614480 * )
- NEW Metal2 ( 1623440 1690640 ) ( 1626800 * 0 )
- NEW Metal2 ( 1623440 1616720 ) ( * 1690640 )
- NEW Metal1 ( 1614480 1616720 ) Via1_HV
- NEW Metal1 ( 1623440 1616720 ) Via1_HV
- NEW Metal2 ( 1462160 159600 ) Via2_VH
- NEW Metal2 ( 1614480 159600 ) Via2_VH ;
- - wbs_adr_i[21] ( PIN wbs_adr_i[21] ) ( mprj wbs_adr_i[21] ) + USE SIGNAL
- + ROUTED Metal3 ( 1631280 1651440 ) ( 1640240 * )
- NEW Metal2 ( 1631280 126000 ) ( * 1651440 )
- NEW Metal2 ( 1512560 3920 ) ( 1521520 * )
- NEW Metal2 ( 1521520 3920 ) ( * 5040 )
- NEW Metal2 ( 1521520 5040 ) ( 1522640 * )
- NEW Metal2 ( 1522640 3920 0 ) ( * 5040 )
- NEW Metal2 ( 1512560 3920 ) ( * 126000 )
- NEW Metal3 ( 1512560 126000 ) ( 1631280 * )
- NEW Metal2 ( 1640240 1690640 ) ( 1643600 * 0 )
- NEW Metal2 ( 1640240 1651440 ) ( * 1690640 )
- NEW Metal2 ( 1631280 1651440 ) Via2_VH
- NEW Metal2 ( 1640240 1651440 ) Via2_VH
- NEW Metal2 ( 1631280 126000 ) Via2_VH
- NEW Metal2 ( 1512560 126000 ) Via2_VH ;
- - wbs_adr_i[22] ( PIN wbs_adr_i[22] ) ( mprj wbs_adr_i[22] ) + USE SIGNAL
- + ROUTED Metal3 ( 1638000 133840 ) ( 1649200 * )
- NEW Metal2 ( 1638000 49840 ) ( * 133840 )
- NEW Metal2 ( 1649200 133840 ) ( * 1495200 )
- NEW Metal2 ( 1649200 1495200 ) ( 1657040 * )
- NEW Metal2 ( 1582000 3920 0 ) ( * 49840 )
- NEW Metal3 ( 1582000 49840 ) ( 1638000 * )
- NEW Metal2 ( 1657040 1690640 ) ( 1660400 * 0 )
- NEW Metal2 ( 1657040 1495200 ) ( * 1690640 )
- NEW Metal2 ( 1638000 49840 ) Via2_VH
- NEW Metal2 ( 1638000 133840 ) Via2_VH
- NEW Metal2 ( 1649200 133840 ) Via2_VH
- NEW Metal2 ( 1582000 49840 ) Via2_VH ;
- - wbs_adr_i[23] ( PIN wbs_adr_i[23] ) ( mprj wbs_adr_i[23] ) + USE SIGNAL
- + ROUTED Metal2 ( 1633520 3920 ) ( 1635760 * )
- NEW Metal2 ( 1635760 3920 ) ( * 5040 )
- NEW Metal2 ( 1635760 5040 ) ( 1636880 * )
- NEW Metal2 ( 1636880 3920 0 ) ( * 5040 )
- NEW Metal3 ( 1633520 1652560 ) ( 1677200 * )
- NEW Metal2 ( 1633520 3920 ) ( * 1652560 )
- NEW Metal2 ( 1677200 1652560 ) ( * 1690640 0 )
- NEW Metal2 ( 1633520 1652560 ) Via2_VH
- NEW Metal2 ( 1677200 1652560 ) Via2_VH ;
- - wbs_adr_i[24] ( PIN wbs_adr_i[24] ) ( mprj wbs_adr_i[24] ) + USE SIGNAL
- + ROUTED Metal3 ( 1680560 44240 ) ( 1687280 * )
- NEW Metal2 ( 1687280 3920 ) ( * 44240 )
- NEW Metal2 ( 1687280 3920 ) ( 1692880 * )
- NEW Metal2 ( 1692880 3920 ) ( * 5040 )
- NEW Metal2 ( 1692880 5040 ) ( 1694000 * )
- NEW Metal2 ( 1694000 3920 0 ) ( * 5040 )
- NEW Metal1 ( 1680560 1576400 ) ( 1690640 * )
- NEW Metal2 ( 1680560 44240 ) ( * 1576400 )
- NEW Metal2 ( 1690640 1690640 ) ( 1694000 * 0 )
- NEW Metal2 ( 1690640 1576400 ) ( * 1690640 )
- NEW Metal2 ( 1680560 44240 ) Via2_VH
- NEW Metal2 ( 1687280 44240 ) Via2_VH
- NEW Metal1 ( 1680560 1576400 ) Via1_HV
- NEW Metal1 ( 1690640 1576400 ) Via1_HV ;
- - wbs_adr_i[25] ( PIN wbs_adr_i[25] ) ( mprj wbs_adr_i[25] ) + USE SIGNAL
- + ROUTED Metal2 ( 1751120 3920 0 ) ( * 48720 )
- NEW Metal3 ( 1722000 48720 ) ( 1751120 * )
- NEW Metal3 ( 1710800 1648080 ) ( 1722000 * )
- NEW Metal2 ( 1722000 48720 ) ( * 1648080 )
- NEW Metal2 ( 1710800 1648080 ) ( * 1690640 0 )
- NEW Metal2 ( 1722000 48720 ) Via2_VH
- NEW Metal2 ( 1751120 48720 ) Via2_VH
- NEW Metal2 ( 1710800 1648080 ) Via2_VH
- NEW Metal2 ( 1722000 1648080 ) Via2_VH ;
- - wbs_adr_i[26] ( PIN wbs_adr_i[26] ) ( mprj wbs_adr_i[26] ) + USE SIGNAL
- + ROUTED Metal3 ( 1755600 42000 ) ( 1808240 * )
- NEW Metal2 ( 1808240 3920 0 ) ( * 42000 )
- NEW Metal3 ( 1727600 1646960 ) ( 1755600 * )
- NEW Metal2 ( 1755600 42000 ) ( * 1646960 )
- NEW Metal2 ( 1727600 1646960 ) ( * 1690640 0 )
- NEW Metal2 ( 1755600 42000 ) Via2_VH
- NEW Metal2 ( 1808240 42000 ) Via2_VH
- NEW Metal2 ( 1727600 1646960 ) Via2_VH
- NEW Metal2 ( 1755600 1646960 ) Via2_VH ;
- - wbs_adr_i[27] ( PIN wbs_adr_i[27] ) ( mprj wbs_adr_i[27] ) + USE SIGNAL
- + ROUTED Metal2 ( 1865360 3920 0 ) ( * 48720 )
- NEW Metal3 ( 1839600 48720 ) ( 1865360 * )
- NEW Metal3 ( 1734320 1511440 ) ( 1839600 * )
- NEW Metal2 ( 1839600 48720 ) ( * 1511440 )
- NEW Metal2 ( 1734320 1511440 ) ( * 1562400 )
- NEW Metal2 ( 1734320 1562400 ) ( 1737680 * )
- NEW Metal2 ( 1737680 1562400 ) ( * 1680000 )
- NEW Metal2 ( 1737680 1680000 ) ( 1741040 * )
- NEW Metal2 ( 1741040 1680000 ) ( * 1690640 )
- NEW Metal2 ( 1741040 1690640 ) ( 1744400 * 0 )
- NEW Metal2 ( 1865360 48720 ) Via2_VH
- NEW Metal2 ( 1839600 48720 ) Via2_VH
- NEW Metal2 ( 1734320 1511440 ) Via2_VH
- NEW Metal2 ( 1839600 1511440 ) Via2_VH ;
- - wbs_adr_i[28] ( PIN wbs_adr_i[28] ) ( mprj wbs_adr_i[28] ) + USE SIGNAL
- + ROUTED Metal2 ( 1922480 3920 0 ) ( * 49840 )
- NEW Metal3 ( 1747760 49840 ) ( 1922480 * )
- NEW Metal3 ( 1747760 1621200 ) ( 1757840 * )
- NEW Metal2 ( 1747760 49840 ) ( * 1621200 )
- NEW Metal2 ( 1757840 1690640 ) ( 1761200 * 0 )
- NEW Metal2 ( 1757840 1621200 ) ( * 1690640 )
- NEW Metal2 ( 1922480 49840 ) Via2_VH
- NEW Metal2 ( 1747760 49840 ) Via2_VH
- NEW Metal2 ( 1747760 1621200 ) Via2_VH
- NEW Metal2 ( 1757840 1621200 ) Via2_VH ;
- - wbs_adr_i[29] ( PIN wbs_adr_i[29] ) ( mprj wbs_adr_i[29] ) + USE SIGNAL
- + ROUTED Metal3 ( 1765680 40880 ) ( 1809360 * )
- NEW Metal2 ( 1809360 40880 ) ( * 42000 )
- NEW Metal2 ( 1809360 42000 ) ( 1811600 * )
- NEW Metal2 ( 1979600 3920 0 ) ( * 42000 )
- NEW Metal3 ( 1811600 42000 ) ( 1979600 * )
- NEW Metal1 ( 1765680 1620080 ) ( 1774640 * )
- NEW Metal2 ( 1765680 40880 ) ( * 1620080 )
- NEW Metal2 ( 1774640 1690640 ) ( 1778000 * 0 )
- NEW Metal2 ( 1774640 1620080 ) ( * 1690640 )
- NEW Metal2 ( 1765680 40880 ) Via2_VH
- NEW Metal2 ( 1809360 40880 ) Via2_VH
- NEW Metal2 ( 1811600 42000 ) Via2_VH
- NEW Metal2 ( 1979600 42000 ) Via2_VH
- NEW Metal1 ( 1765680 1620080 ) Via1_HV
- NEW Metal1 ( 1774640 1620080 ) Via1_HV ;
- - wbs_adr_i[2] ( PIN wbs_adr_i[2] ) ( mprj wbs_adr_i[2] ) + USE SIGNAL
- + ROUTED Metal2 ( 401520 3920 0 ) ( * 40880 )
- NEW Metal3 ( 401520 40880 ) ( 436800 * )
- NEW Metal3 ( 436800 40880 ) ( * 42000 )
- NEW Metal3 ( 436800 42000 ) ( 1314320 * )
- NEW Metal2 ( 1313200 1612800 ) ( * 1690640 0 )
- NEW Metal2 ( 1313200 1612800 ) ( 1314320 * )
- NEW Metal2 ( 1314320 42000 ) ( * 1612800 )
- NEW Metal2 ( 401520 40880 ) Via2_VH
- NEW Metal2 ( 1314320 42000 ) Via2_VH ;
- - wbs_adr_i[30] ( PIN wbs_adr_i[30] ) ( mprj wbs_adr_i[30] ) + USE SIGNAL
- + ROUTED Metal4 ( 1909040 44240 ) ( * 47600 )
- NEW Metal3 ( 1781360 43120 ) ( 1829520 * )
- NEW Metal3 ( 1829520 43120 ) ( * 44240 )
- NEW Metal3 ( 1829520 44240 ) ( 1909040 * )
- NEW Metal2 ( 2036720 3920 0 ) ( * 47600 )
- NEW Metal3 ( 1909040 47600 ) ( 2036720 * )
- NEW Metal3 ( 1781360 1621200 ) ( 1791440 * )
- NEW Metal2 ( 1781360 43120 ) ( * 1621200 )
- NEW Metal2 ( 1791440 1690640 ) ( 1794800 * 0 )
- NEW Metal2 ( 1791440 1621200 ) ( * 1690640 )
- NEW Metal3 ( 1909040 44240 ) Via3_HV
- NEW Metal3 ( 1909040 47600 ) Via3_HV
- NEW Metal2 ( 1781360 43120 ) Via2_VH
- NEW Metal2 ( 2036720 47600 ) Via2_VH
- NEW Metal2 ( 1781360 1621200 ) Via2_VH
- NEW Metal2 ( 1791440 1621200 ) Via2_VH ;
- - wbs_adr_i[31] ( PIN wbs_adr_i[31] ) ( mprj wbs_adr_i[31] ) + USE SIGNAL
- + ROUTED Metal2 ( 2093840 3920 0 ) ( * 45360 )
- NEW Metal3 ( 1798160 45360 ) ( 2093840 * )
- NEW Metal3 ( 1798160 1651440 ) ( 1808240 * )
- NEW Metal2 ( 1798160 45360 ) ( * 1651440 )
- NEW Metal2 ( 1808240 1690640 ) ( 1811600 * 0 )
- NEW Metal2 ( 1808240 1651440 ) ( * 1690640 )
- NEW Metal2 ( 2093840 45360 ) Via2_VH
- NEW Metal2 ( 1798160 45360 ) Via2_VH
- NEW Metal2 ( 1798160 1651440 ) Via2_VH
- NEW Metal2 ( 1808240 1651440 ) Via2_VH ;
- - wbs_adr_i[3] ( PIN wbs_adr_i[3] ) ( mprj wbs_adr_i[3] ) + USE SIGNAL
- + ROUTED Metal2 ( 477680 3920 0 ) ( * 43120 )
- NEW Metal3 ( 477680 43120 ) ( 1327760 * )
- NEW Metal2 ( 1332240 1690640 ) ( 1335600 * 0 )
- NEW Metal1 ( 1327760 1565200 ) ( 1332240 * )
- NEW Metal2 ( 1327760 43120 ) ( * 1565200 )
- NEW Metal2 ( 1332240 1565200 ) ( * 1690640 )
- NEW Metal2 ( 477680 43120 ) Via2_VH
- NEW Metal2 ( 1327760 43120 ) Via2_VH
- NEW Metal1 ( 1327760 1565200 ) Via1_HV
- NEW Metal1 ( 1332240 1565200 ) Via1_HV ;
- - wbs_adr_i[4] ( PIN wbs_adr_i[4] ) ( mprj wbs_adr_i[4] ) + USE SIGNAL
- + ROUTED Metal2 ( 538160 3920 ) ( 550480 * )
- NEW Metal2 ( 550480 3920 ) ( * 5040 )
- NEW Metal2 ( 550480 5040 ) ( 551600 * )
- NEW Metal2 ( 551600 3920 0 ) ( * 5040 )
- NEW Metal2 ( 538160 3920 ) ( * 1640240 )
- NEW Metal2 ( 1343440 1640240 ) ( * 1661520 )
- NEW Metal3 ( 1343440 1661520 ) ( 1358000 * )
- NEW Metal3 ( 538160 1640240 ) ( 1343440 * )
- NEW Metal2 ( 1358000 1661520 ) ( * 1690640 0 )
- NEW Metal2 ( 538160 1640240 ) Via2_VH
- NEW Metal2 ( 1343440 1640240 ) Via2_VH
- NEW Metal2 ( 1343440 1661520 ) Via2_VH
- NEW Metal2 ( 1358000 1661520 ) Via2_VH ;
- - wbs_adr_i[5] ( PIN wbs_adr_i[5] ) ( mprj wbs_adr_i[5] ) + USE SIGNAL
- + ROUTED Metal2 ( 605360 3920 ) ( 607600 * )
- NEW Metal2 ( 607600 3920 ) ( * 5040 )
- NEW Metal2 ( 607600 5040 ) ( 608720 * )
- NEW Metal2 ( 608720 3920 0 ) ( * 5040 )
- NEW Metal2 ( 1371440 1690640 ) ( 1374800 * 0 )
- NEW Metal2 ( 605360 3920 ) ( * 1604400 )
- NEW Metal3 ( 605360 1604400 ) ( 1371440 * )
- NEW Metal2 ( 1371440 1604400 ) ( * 1690640 )
- NEW Metal2 ( 605360 1604400 ) Via2_VH
- NEW Metal2 ( 1371440 1604400 ) Via2_VH ;
- - wbs_adr_i[6] ( PIN wbs_adr_i[6] ) ( mprj wbs_adr_i[6] ) + USE SIGNAL
- + ROUTED Metal2 ( 1388240 1690640 ) ( 1391600 * 0 )
- NEW Metal2 ( 655760 3920 ) ( 664720 * )
- NEW Metal2 ( 664720 3920 ) ( * 5040 )
- NEW Metal2 ( 664720 5040 ) ( 665840 * )
- NEW Metal2 ( 665840 3920 0 ) ( * 5040 )
- NEW Metal2 ( 655760 3920 ) ( * 1605520 )
- NEW Metal3 ( 655760 1605520 ) ( 1388240 * )
- NEW Metal2 ( 1388240 1605520 ) ( * 1690640 )
- NEW Metal2 ( 655760 1605520 ) Via2_VH
- NEW Metal2 ( 1388240 1605520 ) Via2_VH ;
- - wbs_adr_i[7] ( PIN wbs_adr_i[7] ) ( mprj wbs_adr_i[7] ) + USE SIGNAL
- + ROUTED Metal2 ( 1405040 1690640 ) ( 1408400 * 0 )
- NEW Metal2 ( 722960 3920 0 ) ( * 1606640 )
- NEW Metal3 ( 722960 1606640 ) ( 1405040 * )
- NEW Metal2 ( 1405040 1606640 ) ( * 1690640 )
- NEW Metal2 ( 722960 1606640 ) Via2_VH
- NEW Metal2 ( 1405040 1606640 ) Via2_VH ;
- - wbs_adr_i[8] ( PIN wbs_adr_i[8] ) ( mprj wbs_adr_i[8] ) + USE SIGNAL
- + ROUTED Metal2 ( 782320 3920 0 ) ( * 49840 )
- NEW Metal2 ( 1421840 1690640 ) ( 1425200 * 0 )
- NEW Metal3 ( 782320 49840 ) ( 798000 * )
- NEW Metal2 ( 798000 49840 ) ( * 1607760 )
- NEW Metal3 ( 798000 1607760 ) ( 1421840 * )
- NEW Metal2 ( 1421840 1607760 ) ( * 1690640 )
- NEW Metal2 ( 782320 49840 ) Via2_VH
- NEW Metal2 ( 798000 49840 ) Via2_VH
- NEW Metal2 ( 798000 1607760 ) Via2_VH
- NEW Metal2 ( 1421840 1607760 ) Via2_VH ;
- - wbs_adr_i[9] ( PIN wbs_adr_i[9] ) ( mprj wbs_adr_i[9] ) + USE SIGNAL
- + ROUTED Metal2 ( 823760 3920 ) ( 836080 * )
- NEW Metal2 ( 836080 3920 ) ( * 5040 )
- NEW Metal2 ( 836080 5040 ) ( 837200 * )
- NEW Metal2 ( 837200 3920 0 ) ( * 5040 )
- NEW Metal2 ( 823760 3920 ) ( * 1622320 )
- NEW Metal3 ( 823760 1622320 ) ( 1442000 * )
- NEW Metal2 ( 1442000 1622320 ) ( * 1690640 0 )
- NEW Metal2 ( 823760 1622320 ) Via2_VH
- NEW Metal2 ( 1442000 1622320 ) Via2_VH ;
- - wbs_cyc_i ( PIN wbs_cyc_i ) ( mprj wbs_cyc_i ) + USE SIGNAL
- + ROUTED Metal2 ( 1248240 1690640 ) ( 1251600 * 0 )
- NEW Metal2 ( 1248240 1587600 ) ( * 1690640 )
- NEW Metal2 ( 185360 3920 ) ( 188720 * )
- NEW Metal2 ( 188720 3920 ) ( * 5040 )
- NEW Metal2 ( 188720 5040 ) ( 189840 * )
- NEW Metal2 ( 189840 3920 0 ) ( * 5040 )
- NEW Metal2 ( 185360 3920 ) ( * 1587600 )
- NEW Metal3 ( 185360 1587600 ) ( 1248240 * )
- NEW Metal2 ( 1248240 1587600 ) Via2_VH
- NEW Metal2 ( 185360 1587600 ) Via2_VH ;
- - wbs_dat_i[0] ( PIN wbs_dat_i[0] ) ( mprj wbs_dat_i[0] ) + USE SIGNAL
- + ROUTED Metal2 ( 252560 3920 ) ( 264880 * )
- NEW Metal2 ( 264880 3920 ) ( * 5040 )
- NEW Metal2 ( 264880 5040 ) ( 266000 * )
- NEW Metal2 ( 266000 3920 0 ) ( * 5040 )
- NEW Metal2 ( 252560 3920 ) ( * 1588720 )
- NEW Metal2 ( 1267280 1652560 ) ( 1270640 * )
- NEW Metal2 ( 1270640 1652560 ) ( * 1690640 )
- NEW Metal2 ( 1270640 1690640 ) ( 1274000 * 0 )
- NEW Metal3 ( 252560 1588720 ) ( 1267280 * )
- NEW Metal2 ( 1267280 1588720 ) ( * 1652560 )
- NEW Metal2 ( 252560 1588720 ) Via2_VH
- NEW Metal2 ( 1267280 1588720 ) Via2_VH ;
- - wbs_dat_i[10] ( PIN wbs_dat_i[10] ) ( mprj wbs_dat_i[10] ) + USE SIGNAL
- + ROUTED Metal2 ( 915600 3920 0 ) ( * 40880 )
- NEW Metal3 ( 915600 40880 ) ( 932400 * )
- NEW Metal2 ( 1463280 1651440 ) ( 1464400 * )
- NEW Metal2 ( 1464400 1651440 ) ( * 1690640 0 )
- NEW Metal2 ( 932400 40880 ) ( * 1592080 )
- NEW Metal2 ( 1463280 1592080 ) ( * 1651440 )
- NEW Metal3 ( 932400 1592080 ) ( 1463280 * )
- NEW Metal2 ( 915600 40880 ) Via2_VH
- NEW Metal2 ( 932400 40880 ) Via2_VH
- NEW Metal2 ( 932400 1592080 ) Via2_VH
- NEW Metal2 ( 1463280 1592080 ) Via2_VH ;
- - wbs_dat_i[11] ( PIN wbs_dat_i[11] ) ( mprj wbs_dat_i[11] ) + USE SIGNAL
- + ROUTED Metal2 ( 958160 3920 ) ( 969360 * )
- NEW Metal2 ( 969360 3920 ) ( * 5040 )
- NEW Metal2 ( 969360 5040 ) ( 970480 * )
- NEW Metal2 ( 970480 3920 0 ) ( * 5040 )
- NEW Metal3 ( 1453200 1650320 ) ( 1481200 * )
- NEW Metal2 ( 1481200 1650320 ) ( * 1690640 0 )
- NEW Metal2 ( 958160 3920 ) ( * 1608880 )
- NEW Metal2 ( 1453200 1608880 ) ( * 1650320 )
- NEW Metal3 ( 958160 1608880 ) ( 1453200 * )
- NEW Metal2 ( 1453200 1650320 ) Via2_VH
- NEW Metal2 ( 1481200 1650320 ) Via2_VH
- NEW Metal2 ( 958160 1608880 ) Via2_VH
- NEW Metal2 ( 1453200 1608880 ) Via2_VH ;
- - wbs_dat_i[12] ( PIN wbs_dat_i[12] ) ( mprj wbs_dat_i[12] ) + USE SIGNAL
- + ROUTED Metal3 ( 1025360 932400 ) ( 1496880 * )
- NEW Metal2 ( 1496880 1651440 ) ( 1498000 * )
- NEW Metal2 ( 1498000 1651440 ) ( * 1690640 0 )
- NEW Metal2 ( 1025360 201600 ) ( 1027600 * )
- NEW Metal2 ( 1027600 3920 0 ) ( * 201600 )
- NEW Metal2 ( 1025360 201600 ) ( * 932400 )
- NEW Metal2 ( 1496880 932400 ) ( * 1651440 )
- NEW Metal2 ( 1025360 932400 ) Via2_VH
- NEW Metal2 ( 1496880 932400 ) Via2_VH ;
- - wbs_dat_i[13] ( PIN wbs_dat_i[13] ) ( mprj wbs_dat_i[13] ) + USE SIGNAL
- + ROUTED Metal2 ( 1075760 3920 ) ( 1083600 * )
- NEW Metal2 ( 1083600 3920 ) ( * 5040 )
- NEW Metal2 ( 1083600 5040 ) ( 1084720 * )
- NEW Metal2 ( 1084720 3920 0 ) ( * 5040 )
- NEW Metal3 ( 1075760 1472240 ) ( 1513680 * )
- NEW Metal2 ( 1513680 1651440 ) ( 1514800 * )
- NEW Metal2 ( 1514800 1651440 ) ( * 1690640 0 )
- NEW Metal2 ( 1075760 3920 ) ( * 1472240 )
- NEW Metal2 ( 1513680 1472240 ) ( * 1651440 )
- NEW Metal2 ( 1075760 1472240 ) Via2_VH
- NEW Metal2 ( 1513680 1472240 ) Via2_VH ;
- - wbs_dat_i[14] ( PIN wbs_dat_i[14] ) ( mprj wbs_dat_i[14] ) + USE SIGNAL
- + ROUTED Metal2 ( 1142960 3920 0 ) ( * 1590960 )
- NEW Metal2 ( 1530480 1651440 ) ( 1531600 * )
- NEW Metal2 ( 1531600 1651440 ) ( * 1690640 0 )
- NEW Metal2 ( 1530480 1590960 ) ( * 1651440 )
- NEW Metal3 ( 1142960 1590960 ) ( 1530480 * )
- NEW Metal2 ( 1142960 1590960 ) Via2_VH
- NEW Metal2 ( 1530480 1590960 ) Via2_VH ;
- - wbs_dat_i[15] ( PIN wbs_dat_i[15] ) ( mprj wbs_dat_i[15] ) + USE SIGNAL
- + ROUTED Metal2 ( 1200080 3920 0 ) ( * 48720 )
- NEW Metal3 ( 1200080 48720 ) ( 1548400 * )
- NEW Metal2 ( 1548400 48720 ) ( * 1690640 0 )
- NEW Metal2 ( 1200080 48720 ) Via2_VH
- NEW Metal2 ( 1548400 48720 ) Via2_VH ;
- - wbs_dat_i[16] ( PIN wbs_dat_i[16] ) ( mprj wbs_dat_i[16] ) + USE SIGNAL
- + ROUTED Metal2 ( 1247120 3920 ) ( 1254960 * )
- NEW Metal2 ( 1254960 3920 ) ( * 5040 )
- NEW Metal2 ( 1254960 5040 ) ( 1256080 * )
- NEW Metal2 ( 1256080 3920 0 ) ( * 5040 )
- NEW Metal2 ( 1247120 3920 ) ( * 1593200 )
- NEW Metal2 ( 1564080 1651440 ) ( 1565200 * )
- NEW Metal2 ( 1565200 1593200 ) ( * 1651440 )
- NEW Metal3 ( 1247120 1593200 ) ( 1565200 * )
- NEW Metal2 ( 1564080 1651440 ) ( * 1680000 )
- NEW Metal2 ( 1564080 1680000 ) ( 1565200 * )
- NEW Metal2 ( 1565200 1680000 ) ( * 1690640 0 )
- NEW Metal2 ( 1247120 1593200 ) Via2_VH
- NEW Metal2 ( 1565200 1593200 ) Via2_VH ;
- - wbs_dat_i[17] ( PIN wbs_dat_i[17] ) ( mprj wbs_dat_i[17] ) + USE SIGNAL
- + ROUTED Metal2 ( 1315440 3920 0 ) ( * 40880 )
- NEW Metal3 ( 1315440 40880 ) ( 1503600 * )
- NEW Metal2 ( 1580880 1651440 ) ( 1582000 * )
- NEW Metal3 ( 1503600 386960 ) ( 1580880 * )
- NEW Metal2 ( 1503600 40880 ) ( * 386960 )
- NEW Metal2 ( 1580880 386960 ) ( * 1651440 )
- NEW Metal2 ( 1582000 1651440 ) ( * 1690640 0 )
- NEW Metal2 ( 1315440 40880 ) Via2_VH
- NEW Metal2 ( 1503600 40880 ) Via2_VH
- NEW Metal2 ( 1503600 386960 ) Via2_VH
- NEW Metal2 ( 1580880 386960 ) Via2_VH ;
- - wbs_dat_i[18] ( PIN wbs_dat_i[18] ) ( mprj wbs_dat_i[18] ) + USE SIGNAL
- + ROUTED Metal2 ( 1470000 43120 ) ( * 1605520 )
- NEW Metal2 ( 1372560 3920 0 ) ( * 43120 )
- NEW Metal3 ( 1372560 43120 ) ( 1470000 * )
- NEW Metal3 ( 1470000 1605520 ) ( 1596560 * )
- NEW Metal2 ( 1596560 1690640 ) ( 1598800 * 0 )
- NEW Metal2 ( 1596560 1605520 ) ( * 1690640 )
- NEW Metal2 ( 1470000 43120 ) Via2_VH
- NEW Metal2 ( 1470000 1605520 ) Via2_VH
- NEW Metal2 ( 1372560 43120 ) Via2_VH
- NEW Metal2 ( 1596560 1605520 ) Via2_VH ;
- - wbs_dat_i[19] ( PIN wbs_dat_i[19] ) ( mprj wbs_dat_i[19] ) + USE SIGNAL
- + ROUTED Metal3 ( 1587600 1648080 ) ( 1615600 * )
- NEW Metal2 ( 1587600 1604400 ) ( * 1648080 )
- NEW Metal2 ( 1428560 3920 0 ) ( * 1604400 )
- NEW Metal3 ( 1428560 1604400 ) ( 1587600 * )
- NEW Metal2 ( 1615600 1648080 ) ( * 1690640 0 )
- NEW Metal2 ( 1615600 1648080 ) Via2_VH
- NEW Metal2 ( 1587600 1648080 ) Via2_VH
- NEW Metal2 ( 1587600 1604400 ) Via2_VH
- NEW Metal2 ( 1428560 1604400 ) Via2_VH ;
- - wbs_dat_i[1] ( PIN wbs_dat_i[1] ) ( mprj wbs_dat_i[1] ) + USE SIGNAL
- + ROUTED Metal2 ( 336560 3920 ) ( 341040 * )
- NEW Metal2 ( 341040 3920 ) ( * 5040 )
- NEW Metal2 ( 341040 5040 ) ( 342160 * )
- NEW Metal2 ( 342160 3920 0 ) ( * 5040 )
- NEW Metal2 ( 1295280 1651440 ) ( 1296400 * )
- NEW Metal2 ( 1296400 1651440 ) ( * 1690640 0 )
- NEW Metal2 ( 336560 3920 ) ( * 1570800 )
- NEW Metal3 ( 336560 1570800 ) ( 1295280 * )
- NEW Metal2 ( 1295280 1570800 ) ( * 1651440 )
- NEW Metal2 ( 336560 1570800 ) Via2_VH
- NEW Metal2 ( 1295280 1570800 ) Via2_VH ;
- - wbs_dat_i[20] ( PIN wbs_dat_i[20] ) ( mprj wbs_dat_i[20] ) + USE SIGNAL
- + ROUTED Metal2 ( 1486800 3920 0 ) ( * 43120 )
- NEW Metal3 ( 1486800 43120 ) ( 1570800 * )
- NEW Metal2 ( 1570800 43120 ) ( * 1584240 )
- NEW Metal3 ( 1570800 1584240 ) ( 1632400 * )
- NEW Metal2 ( 1632400 1584240 ) ( * 1690640 0 )
- NEW Metal2 ( 1486800 43120 ) Via2_VH
- NEW Metal2 ( 1632400 1584240 ) Via2_VH
- NEW Metal2 ( 1570800 43120 ) Via2_VH
- NEW Metal2 ( 1570800 1584240 ) Via2_VH ;
- - wbs_dat_i[21] ( PIN wbs_dat_i[21] ) ( mprj wbs_dat_i[21] ) + USE SIGNAL
- + ROUTED Metal2 ( 1648080 1651440 ) ( 1649200 * )
- NEW Metal2 ( 1648080 1503600 ) ( * 1651440 )
- NEW Metal2 ( 1543920 3920 0 ) ( * 42000 )
- NEW Metal3 ( 1543920 42000 ) ( 1573040 * )
- NEW Metal2 ( 1573040 42000 ) ( * 1503600 )
- NEW Metal3 ( 1573040 1503600 ) ( 1648080 * )
- NEW Metal2 ( 1649200 1651440 ) ( * 1690640 0 )
- NEW Metal2 ( 1648080 1503600 ) Via2_VH
- NEW Metal2 ( 1543920 42000 ) Via2_VH
- NEW Metal2 ( 1573040 42000 ) Via2_VH
- NEW Metal2 ( 1573040 1503600 ) Via2_VH ;
- - wbs_dat_i[22] ( PIN wbs_dat_i[22] ) ( mprj wbs_dat_i[22] ) + USE SIGNAL
- + ROUTED Metal3 ( 1602160 1657040 ) ( 1666000 * )
- NEW Metal2 ( 1599920 3920 0 ) ( * 1495200 )
- NEW Metal2 ( 1599920 1495200 ) ( 1602160 * )
- NEW Metal2 ( 1602160 1495200 ) ( * 1657040 )
- NEW Metal2 ( 1666000 1657040 ) ( * 1690640 0 )
- NEW Metal2 ( 1666000 1657040 ) Via2_VH
- NEW Metal2 ( 1602160 1657040 ) Via2_VH ;
- - wbs_dat_i[23] ( PIN wbs_dat_i[23] ) ( mprj wbs_dat_i[23] ) + USE SIGNAL
- + ROUTED Metal2 ( 1646960 3920 ) ( 1654800 * )
- NEW Metal2 ( 1654800 3920 ) ( * 5040 )
- NEW Metal2 ( 1654800 5040 ) ( 1655920 * )
- NEW Metal2 ( 1655920 3920 0 ) ( * 5040 )
- NEW Metal3 ( 1646960 1510320 ) ( 1683920 * )
- NEW Metal2 ( 1646960 3920 ) ( * 1510320 )
- NEW Metal2 ( 1682800 1680000 ) ( 1683920 * )
- NEW Metal2 ( 1682800 1680000 ) ( * 1690640 0 )
- NEW Metal4 ( 1683920 1534960 ) ( * 1623440 )
- NEW Metal2 ( 1683920 1510320 ) ( * 1534960 )
- NEW Metal2 ( 1683920 1623440 ) ( * 1680000 )
- NEW Metal2 ( 1646960 1510320 ) Via2_VH
- NEW Metal2 ( 1683920 1510320 ) Via2_VH
- NEW Metal2 ( 1683920 1534960 ) Via2_VH
- NEW Metal3 ( 1683920 1534960 ) Via3_HV
- NEW Metal2 ( 1683920 1623440 ) Via2_VH
- NEW Metal3 ( 1683920 1623440 ) Via3_HV
- NEW Metal3 ( 1683920 1534960 ) RECT ( -660 -280 0 280 )
- NEW Metal3 ( 1683920 1623440 ) RECT ( -660 -280 0 280 ) ;
- - wbs_dat_i[24] ( PIN wbs_dat_i[24] ) ( mprj wbs_dat_i[24] ) + USE SIGNAL
- + ROUTED Metal3 ( 1699600 1646960 ) ( 1714160 * )
- NEW Metal2 ( 1714160 3920 0 ) ( * 1646960 )
- NEW Metal2 ( 1699600 1646960 ) ( * 1690640 0 )
- NEW Metal2 ( 1699600 1646960 ) Via2_VH
- NEW Metal2 ( 1714160 1646960 ) Via2_VH ;
- - wbs_dat_i[25] ( PIN wbs_dat_i[25] ) ( mprj wbs_dat_i[25] ) + USE SIGNAL
- + ROUTED Metal2 ( 1764560 3920 ) ( 1769040 * )
- NEW Metal2 ( 1769040 3920 ) ( * 5040 )
- NEW Metal2 ( 1769040 5040 ) ( 1770160 * )
- NEW Metal2 ( 1770160 3920 0 ) ( * 5040 )
- NEW Metal3 ( 1716400 1651440 ) ( 1764560 * )
- NEW Metal2 ( 1764560 3920 ) ( * 1651440 )
- NEW Metal2 ( 1716400 1651440 ) ( * 1690640 0 )
- NEW Metal2 ( 1716400 1651440 ) Via2_VH
- NEW Metal2 ( 1764560 1651440 ) Via2_VH ;
- - wbs_dat_i[26] ( PIN wbs_dat_i[26] ) ( mprj wbs_dat_i[26] ) + USE SIGNAL
- + ROUTED Metal3 ( 1806000 44240 ) ( 1827280 * )
- NEW Metal2 ( 1827280 3920 0 ) ( * 44240 )
- NEW Metal2 ( 1806000 44240 ) ( * 1654800 )
- NEW Metal3 ( 1733200 1654800 ) ( 1806000 * )
- NEW Metal2 ( 1733200 1654800 ) ( * 1690640 0 )
- NEW Metal2 ( 1806000 44240 ) Via2_VH
- NEW Metal2 ( 1827280 44240 ) Via2_VH
- NEW Metal2 ( 1806000 1654800 ) Via2_VH
- NEW Metal2 ( 1733200 1654800 ) Via2_VH ;
- - wbs_dat_i[27] ( PIN wbs_dat_i[27] ) ( mprj wbs_dat_i[27] ) + USE SIGNAL
- + ROUTED Metal2 ( 1884400 3920 0 ) ( * 43120 )
- NEW Metal3 ( 1750000 47600 ) ( 1753360 * )
- NEW Metal3 ( 1753360 47600 ) ( * 48720 )
- NEW Metal3 ( 1753360 48720 ) ( 1831760 * )
- NEW Metal2 ( 1831760 43120 ) ( * 48720 )
- NEW Metal3 ( 1831760 43120 ) ( 1884400 * )
- NEW Metal2 ( 1750000 47600 ) ( * 1690640 0 )
- NEW Metal2 ( 1884400 43120 ) Via2_VH
- NEW Metal2 ( 1750000 47600 ) Via2_VH
- NEW Metal2 ( 1831760 48720 ) Via2_VH
- NEW Metal2 ( 1831760 43120 ) Via2_VH ;
- - wbs_dat_i[28] ( PIN wbs_dat_i[28] ) ( mprj wbs_dat_i[28] ) + USE SIGNAL
- + ROUTED Metal2 ( 1941520 3920 0 ) ( * 40880 )
- NEW Metal3 ( 1767920 38640 ) ( 1812720 * )
- NEW Metal3 ( 1812720 38640 ) ( * 40880 )
- NEW Metal3 ( 1812720 40880 ) ( 1941520 * )
- NEW Metal2 ( 1767920 38640 ) ( * 1680000 )
- NEW Metal2 ( 1766800 1680000 ) ( 1767920 * )
- NEW Metal2 ( 1766800 1680000 ) ( * 1690640 0 )
- NEW Metal2 ( 1941520 40880 ) Via2_VH
- NEW Metal2 ( 1767920 38640 ) Via2_VH ;
- - wbs_dat_i[29] ( PIN wbs_dat_i[29] ) ( mprj wbs_dat_i[29] ) + USE SIGNAL
- + ROUTED Metal3 ( 1808240 260400 ) ( 2002000 * )
- NEW Metal2 ( 2000880 3920 0 ) ( * 84000 )
- NEW Metal2 ( 2000880 84000 ) ( 2002000 * )
- NEW Metal2 ( 2002000 84000 ) ( * 260400 )
- NEW Metal2 ( 1808240 260400 ) ( * 1649200 )
- NEW Metal3 ( 1783600 1649200 ) ( 1808240 * )
- NEW Metal2 ( 1783600 1649200 ) ( * 1690640 0 )
- NEW Metal2 ( 1808240 260400 ) Via2_VH
- NEW Metal2 ( 2002000 260400 ) Via2_VH
- NEW Metal2 ( 1808240 1649200 ) Via2_VH
- NEW Metal2 ( 1783600 1649200 ) Via2_VH ;
- - wbs_dat_i[2] ( PIN wbs_dat_i[2] ) ( mprj wbs_dat_i[2] ) + USE SIGNAL
- + ROUTED Metal2 ( 419440 3920 0 ) ( * 42000 )
- NEW Metal3 ( 419440 42000 ) ( 428400 * )
- NEW Metal2 ( 1318800 1671600 ) ( * 1690640 0 )
- NEW Metal3 ( 428400 1671600 ) ( 1318800 * )
- NEW Metal2 ( 428400 42000 ) ( * 1671600 )
- NEW Metal2 ( 419440 42000 ) Via2_VH
- NEW Metal2 ( 428400 42000 ) Via2_VH
- NEW Metal2 ( 428400 1671600 ) Via2_VH
- NEW Metal2 ( 1318800 1671600 ) Via2_VH ;
- - wbs_dat_i[30] ( PIN wbs_dat_i[30] ) ( mprj wbs_dat_i[30] ) + USE SIGNAL
- + ROUTED Metal2 ( 2050160 3920 ) ( 2054640 * )
- NEW Metal2 ( 2054640 3920 ) ( * 5040 )
- NEW Metal2 ( 2054640 5040 ) ( 2055760 * )
- NEW Metal2 ( 2055760 3920 0 ) ( * 5040 )
- NEW Metal2 ( 2050160 3920 ) ( * 1638000 )
- NEW Metal3 ( 1800400 1661520 ) ( 1830640 * )
- NEW Metal2 ( 1830640 1638000 ) ( * 1661520 )
- NEW Metal3 ( 1830640 1638000 ) ( 2050160 * )
- NEW Metal2 ( 1800400 1661520 ) ( * 1690640 0 )
- NEW Metal2 ( 2050160 1638000 ) Via2_VH
- NEW Metal2 ( 1800400 1661520 ) Via2_VH
- NEW Metal2 ( 1830640 1661520 ) Via2_VH
- NEW Metal2 ( 1830640 1638000 ) Via2_VH ;
- - wbs_dat_i[31] ( PIN wbs_dat_i[31] ) ( mprj wbs_dat_i[31] ) + USE SIGNAL
- + ROUTED Metal2 ( 2101680 3920 ) ( 2111760 * )
- NEW Metal2 ( 2111760 3920 ) ( * 5040 )
- NEW Metal2 ( 2111760 5040 ) ( 2112880 * )
- NEW Metal2 ( 2112880 3920 0 ) ( * 5040 )
- NEW Metal2 ( 2101680 3920 ) ( * 1184400 )
- NEW Metal3 ( 1817200 1184400 ) ( 2101680 * )
- NEW Metal2 ( 1817200 1184400 ) ( * 1690640 0 )
- NEW Metal2 ( 2101680 1184400 ) Via2_VH
- NEW Metal2 ( 1817200 1184400 ) Via2_VH ;
- - wbs_dat_i[3] ( PIN wbs_dat_i[3] ) ( mprj wbs_dat_i[3] ) + USE SIGNAL
- + ROUTED Metal2 ( 487760 3920 ) ( 493360 * )
- NEW Metal2 ( 493360 3920 ) ( * 5040 )
- NEW Metal2 ( 493360 5040 ) ( 494480 * )
- NEW Metal2 ( 494480 3920 0 ) ( * 5040 )
- NEW Metal2 ( 487760 3920 ) ( * 1571920 )
- NEW Metal2 ( 1337840 1690640 ) ( 1341200 * 0 )
- NEW Metal3 ( 487760 1571920 ) ( 1337840 * )
- NEW Metal2 ( 1337840 1571920 ) ( * 1690640 )
- NEW Metal2 ( 487760 1571920 ) Via2_VH
- NEW Metal2 ( 1337840 1571920 ) Via2_VH ;
- - wbs_dat_i[4] ( PIN wbs_dat_i[4] ) ( mprj wbs_dat_i[4] ) + USE SIGNAL
- + ROUTED Metal2 ( 571760 3920 0 ) ( * 1573040 )
- NEW Metal3 ( 571760 1573040 ) ( 1363600 * )
- NEW Metal2 ( 1363600 1573040 ) ( * 1690640 0 )
- NEW Metal2 ( 571760 1573040 ) Via2_VH
- NEW Metal2 ( 1363600 1573040 ) Via2_VH ;
- - wbs_dat_i[5] ( PIN wbs_dat_i[5] ) ( mprj wbs_dat_i[5] ) + USE SIGNAL
- + ROUTED Metal2 ( 697200 48720 ) ( * 1555120 )
- NEW Metal2 ( 630000 3920 0 ) ( * 48720 )
- NEW Metal3 ( 630000 48720 ) ( 697200 * )
- NEW Metal3 ( 697200 1555120 ) ( 1380400 * )
- NEW Metal2 ( 1380400 1555120 ) ( * 1690640 0 )
- NEW Metal2 ( 697200 48720 ) Via2_VH
- NEW Metal2 ( 697200 1555120 ) Via2_VH
- NEW Metal2 ( 1380400 1555120 ) Via2_VH
- NEW Metal2 ( 630000 48720 ) Via2_VH ;
- - wbs_dat_i[6] ( PIN wbs_dat_i[6] ) ( mprj wbs_dat_i[6] ) + USE SIGNAL
- + ROUTED Metal2 ( 672560 3920 ) ( 683760 * )
- NEW Metal2 ( 683760 3920 ) ( * 5040 )
- NEW Metal2 ( 683760 5040 ) ( 684880 * )
- NEW Metal2 ( 684880 3920 0 ) ( * 5040 )
- NEW Metal2 ( 672560 3920 ) ( * 1554000 )
- NEW Metal3 ( 672560 1554000 ) ( 1396080 * )
- NEW Metal2 ( 1396080 1554000 ) ( * 1562400 )
- NEW Metal2 ( 1396080 1562400 ) ( 1397200 * )
- NEW Metal2 ( 1397200 1562400 ) ( * 1690640 0 )
- NEW Metal2 ( 672560 1554000 ) Via2_VH
- NEW Metal2 ( 1396080 1554000 ) Via2_VH ;
- - wbs_dat_i[7] ( PIN wbs_dat_i[7] ) ( mprj wbs_dat_i[7] ) + USE SIGNAL
- + ROUTED Metal2 ( 739760 201600 ) ( 742000 * )
- NEW Metal2 ( 742000 3920 0 ) ( * 201600 )
- NEW Metal2 ( 739760 201600 ) ( * 1574160 )
- NEW Metal3 ( 739760 1574160 ) ( 1414000 * )
- NEW Metal2 ( 1414000 1574160 ) ( * 1690640 0 )
- NEW Metal2 ( 739760 1574160 ) Via2_VH
- NEW Metal2 ( 1414000 1574160 ) Via2_VH ;
- - wbs_dat_i[8] ( PIN wbs_dat_i[8] ) ( mprj wbs_dat_i[8] ) + USE SIGNAL
- + ROUTED Metal2 ( 801360 3920 0 ) ( * 39760 )
- NEW Metal3 ( 801360 39760 ) ( 882000 * )
- NEW Metal2 ( 882000 39760 ) ( * 1556240 )
- NEW Metal3 ( 882000 1556240 ) ( 1430800 * )
- NEW Metal2 ( 1430800 1556240 ) ( * 1690640 0 )
- NEW Metal2 ( 1430800 1556240 ) Via2_VH
- NEW Metal2 ( 801360 39760 ) Via2_VH
- NEW Metal2 ( 882000 39760 ) Via2_VH
- NEW Metal2 ( 882000 1556240 ) Via2_VH ;
- - wbs_dat_i[9] ( PIN wbs_dat_i[9] ) ( mprj wbs_dat_i[9] ) + USE SIGNAL
- + ROUTED Metal2 ( 1445360 1658160 ) ( * 1690640 )
- NEW Metal2 ( 1445360 1690640 ) ( 1447600 * 0 )
- NEW Metal2 ( 1446480 1538320 ) ( * 1653680 )
- NEW Metal2 ( 857360 3920 0 ) ( * 1538320 )
- NEW Metal3 ( 857360 1538320 ) ( 1446480 * )
- NEW Metal2 ( 1444240 1653680 ) ( * 1658160 )
- NEW Metal2 ( 1444240 1653680 ) ( 1446480 * )
- NEW Metal2 ( 1444240 1658160 ) ( 1445360 * )
- NEW Metal2 ( 1446480 1538320 ) Via2_VH
- NEW Metal2 ( 857360 1538320 ) Via2_VH ;
- - wbs_dat_o[0] ( PIN wbs_dat_o[0] ) ( mprj wbs_dat_o[0] ) + USE SIGNAL
- + ROUTED Metal2 ( 287280 3920 0 ) ( * 75600 )
- NEW Metal3 ( 287280 75600 ) ( 1279600 * )
- NEW Metal2 ( 1279600 75600 ) ( * 1690640 0 )
- NEW Metal2 ( 287280 75600 ) Via2_VH
- NEW Metal2 ( 1279600 75600 ) Via2_VH ;
- - wbs_dat_o[10] ( PIN wbs_dat_o[10] ) ( mprj wbs_dat_o[10] ) + USE SIGNAL
- + ROUTED Metal2 ( 924560 3920 ) ( 931280 * )
- NEW Metal2 ( 931280 3920 ) ( * 5040 )
- NEW Metal2 ( 931280 5040 ) ( 932400 * )
- NEW Metal2 ( 932400 3920 0 ) ( * 5040 )
- NEW Metal2 ( 1466640 1690640 ) ( 1470000 * 0 )
- NEW Metal2 ( 924560 3920 ) ( * 176400 )
- NEW Metal2 ( 1464400 176400 ) ( * 1495200 )
- NEW Metal2 ( 1464400 1495200 ) ( 1466640 * )
- NEW Metal2 ( 1466640 1495200 ) ( * 1690640 )
- NEW Metal3 ( 924560 176400 ) ( 1464400 * )
- NEW Metal2 ( 924560 176400 ) Via2_VH
- NEW Metal2 ( 1464400 176400 ) Via2_VH ;
- - wbs_dat_o[11] ( PIN wbs_dat_o[11] ) ( mprj wbs_dat_o[11] ) + USE SIGNAL
- + ROUTED Metal2 ( 990640 3920 0 ) ( * 46480 )
- NEW Metal2 ( 1483440 1690640 ) ( 1486800 * 0 )
- NEW Metal2 ( 1481200 46480 ) ( * 1495200 )
- NEW Metal2 ( 1481200 1495200 ) ( 1483440 * )
- NEW Metal2 ( 1483440 1495200 ) ( * 1690640 )
- NEW Metal3 ( 990640 46480 ) ( 1481200 * )
- NEW Metal2 ( 990640 46480 ) Via2_VH
- NEW Metal2 ( 1481200 46480 ) Via2_VH ;
- - wbs_dat_o[12] ( PIN wbs_dat_o[12] ) ( mprj wbs_dat_o[12] ) + USE SIGNAL
- + ROUTED Metal2 ( 1042160 3920 ) ( 1045520 * )
- NEW Metal2 ( 1045520 3920 ) ( * 5040 )
- NEW Metal2 ( 1045520 5040 ) ( 1046640 * )
- NEW Metal2 ( 1046640 3920 0 ) ( * 5040 )
- NEW Metal2 ( 1503600 1653680 ) ( * 1690640 0 )
- NEW Metal2 ( 1042160 3920 ) ( * 1610000 )
- NEW Metal2 ( 1428560 1610000 ) ( * 1653680 )
- NEW Metal3 ( 1042160 1610000 ) ( 1428560 * )
- NEW Metal3 ( 1428560 1653680 ) ( 1503600 * )
- NEW Metal2 ( 1503600 1653680 ) Via2_VH
- NEW Metal2 ( 1042160 1610000 ) Via2_VH
- NEW Metal2 ( 1428560 1610000 ) Via2_VH
- NEW Metal2 ( 1428560 1653680 ) Via2_VH ;
- - wbs_dat_o[13] ( PIN wbs_dat_o[13] ) ( mprj wbs_dat_o[13] ) + USE SIGNAL
- + ROUTED Metal2 ( 1092560 3920 ) ( 1102640 * )
- NEW Metal2 ( 1102640 3920 ) ( * 5040 )
- NEW Metal2 ( 1102640 5040 ) ( 1103760 * )
- NEW Metal2 ( 1103760 3920 0 ) ( * 5040 )
- NEW Metal2 ( 1517040 1690640 ) ( 1520400 * 0 )
- NEW Metal2 ( 1092560 3920 ) ( * 142800 )
- NEW Metal3 ( 1092560 142800 ) ( 1514800 * )
- NEW Metal2 ( 1514800 142800 ) ( * 1495200 )
- NEW Metal2 ( 1514800 1495200 ) ( 1517040 * )
- NEW Metal2 ( 1517040 1495200 ) ( * 1690640 )
- NEW Metal2 ( 1092560 142800 ) Via2_VH
- NEW Metal2 ( 1514800 142800 ) Via2_VH ;
- - wbs_dat_o[14] ( PIN wbs_dat_o[14] ) ( mprj wbs_dat_o[14] ) + USE SIGNAL
- + ROUTED Metal2 ( 1163120 3920 0 ) ( * 47600 )
- NEW Metal3 ( 1163120 47600 ) ( 1531600 * )
- NEW Metal2 ( 1533840 1690640 ) ( 1537200 * 0 )
- NEW Metal2 ( 1531600 47600 ) ( * 1495200 )
- NEW Metal2 ( 1531600 1495200 ) ( 1533840 * )
- NEW Metal2 ( 1533840 1495200 ) ( * 1690640 )
- NEW Metal2 ( 1163120 47600 ) Via2_VH
- NEW Metal2 ( 1531600 47600 ) Via2_VH ;
- - wbs_dat_o[15] ( PIN wbs_dat_o[15] ) ( mprj wbs_dat_o[15] ) + USE SIGNAL
- + ROUTED Metal2 ( 1210160 3920 ) ( 1216880 * )
- NEW Metal2 ( 1216880 3920 ) ( * 5040 )
- NEW Metal2 ( 1216880 5040 ) ( 1218000 * )
- NEW Metal2 ( 1218000 3920 0 ) ( * 5040 )
- NEW Metal2 ( 1210160 3920 ) ( * 1624560 )
- NEW Metal2 ( 1554000 1624560 ) ( * 1690640 0 )
- NEW Metal3 ( 1210160 1624560 ) ( 1554000 * )
- NEW Metal2 ( 1210160 1624560 ) Via2_VH
- NEW Metal2 ( 1554000 1624560 ) Via2_VH ;
- - wbs_dat_o[16] ( PIN wbs_dat_o[16] ) ( mprj wbs_dat_o[16] ) + USE SIGNAL
- + ROUTED Metal2 ( 1276240 3920 0 ) ( * 49840 )
- NEW Metal3 ( 1276240 49840 ) ( 1562960 * )
- NEW Metal1 ( 1562960 1615600 ) ( 1568560 * )
- NEW Metal2 ( 1562960 49840 ) ( * 1615600 )
- NEW Metal2 ( 1568560 1690640 ) ( 1570800 * 0 )
- NEW Metal2 ( 1568560 1615600 ) ( * 1690640 )
- NEW Metal2 ( 1276240 49840 ) Via2_VH
- NEW Metal2 ( 1562960 49840 ) Via2_VH
- NEW Metal1 ( 1562960 1615600 ) Via1_HV
- NEW Metal1 ( 1568560 1615600 ) Via1_HV ;
- - wbs_dat_o[17] ( PIN wbs_dat_o[17] ) ( mprj wbs_dat_o[17] ) + USE SIGNAL
- + ROUTED Metal2 ( 1331120 201600 ) ( 1332240 * )
- NEW Metal2 ( 1332240 3920 0 ) ( * 201600 )
- NEW Metal2 ( 1331120 201600 ) ( * 1638000 )
- NEW Metal3 ( 1331120 1638000 ) ( 1584240 * )
- NEW Metal2 ( 1584240 1690640 ) ( 1587600 * 0 )
- NEW Metal2 ( 1584240 1638000 ) ( * 1690640 )
- NEW Metal2 ( 1584240 1638000 ) Via2_VH
- NEW Metal2 ( 1331120 1638000 ) Via2_VH ;
- - wbs_dat_o[18] ( PIN wbs_dat_o[18] ) ( mprj wbs_dat_o[18] ) + USE SIGNAL
- + ROUTED Metal2 ( 1391600 3920 0 ) ( * 42000 )
- NEW Metal3 ( 1541680 40880 ) ( * 42000 )
- NEW Metal3 ( 1541680 40880 ) ( 1597680 * )
- NEW Metal3 ( 1391600 42000 ) ( 1541680 * )
- NEW Metal2 ( 1597680 1655920 ) ( 1601040 * )
- NEW Metal2 ( 1597680 40880 ) ( * 1655920 )
- NEW Metal2 ( 1601040 1690640 ) ( 1604400 * 0 )
- NEW Metal2 ( 1601040 1655920 ) ( * 1690640 )
- NEW Metal2 ( 1391600 42000 ) Via2_VH
- NEW Metal2 ( 1597680 40880 ) Via2_VH ;
- - wbs_dat_o[19] ( PIN wbs_dat_o[19] ) ( mprj wbs_dat_o[19] ) + USE SIGNAL
- + ROUTED Metal2 ( 1448720 3920 0 ) ( * 1554000 )
- NEW Metal3 ( 1448720 1554000 ) ( 1617840 * )
- NEW Metal2 ( 1617840 1690640 ) ( 1621200 * 0 )
- NEW Metal2 ( 1617840 1554000 ) ( * 1690640 )
- NEW Metal2 ( 1448720 1554000 ) Via2_VH
- NEW Metal2 ( 1617840 1554000 ) Via2_VH ;
- - wbs_dat_o[1] ( PIN wbs_dat_o[1] ) ( mprj wbs_dat_o[1] ) + USE SIGNAL
- + ROUTED Metal2 ( 353360 3920 ) ( 360080 * )
- NEW Metal2 ( 360080 3920 ) ( * 5040 )
- NEW Metal2 ( 360080 5040 ) ( 361200 * )
- NEW Metal2 ( 361200 3920 0 ) ( * 5040 )
- NEW Metal2 ( 1298640 1690640 ) ( 1302000 * 0 )
- NEW Metal2 ( 353360 3920 ) ( * 126000 )
- NEW Metal3 ( 353360 126000 ) ( 1296400 * )
- NEW Metal2 ( 1296400 126000 ) ( * 1495200 )
- NEW Metal2 ( 1296400 1495200 ) ( 1298640 * )
- NEW Metal2 ( 1298640 1495200 ) ( * 1690640 )
- NEW Metal2 ( 353360 126000 ) Via2_VH
- NEW Metal2 ( 1296400 126000 ) Via2_VH ;
- - wbs_dat_o[20] ( PIN wbs_dat_o[20] ) ( mprj wbs_dat_o[20] ) + USE SIGNAL
- + ROUTED Metal2 ( 1495760 3920 ) ( 1502480 * )
- NEW Metal2 ( 1502480 3920 ) ( * 5040 )
- NEW Metal2 ( 1502480 5040 ) ( 1503600 * )
- NEW Metal2 ( 1503600 3920 0 ) ( * 5040 )
- NEW Metal3 ( 1495760 1655920 ) ( 1638000 * )
- NEW Metal2 ( 1495760 3920 ) ( * 1655920 )
- NEW Metal2 ( 1638000 1655920 ) ( * 1690640 0 )
- NEW Metal2 ( 1638000 1655920 ) Via2_VH
- NEW Metal2 ( 1495760 1655920 ) Via2_VH ;
- - wbs_dat_o[21] ( PIN wbs_dat_o[21] ) ( mprj wbs_dat_o[21] ) + USE SIGNAL
- + ROUTED Metal2 ( 1546160 3920 ) ( 1559600 * )
- NEW Metal2 ( 1559600 3920 ) ( * 5040 )
- NEW Metal2 ( 1559600 5040 ) ( 1560720 * )
- NEW Metal2 ( 1560720 3920 0 ) ( * 5040 )
- NEW Metal3 ( 1546160 1639120 ) ( 1654800 * )
- NEW Metal2 ( 1546160 3920 ) ( * 1639120 )
- NEW Metal2 ( 1654800 1639120 ) ( * 1690640 0 )
- NEW Metal2 ( 1654800 1639120 ) Via2_VH
- NEW Metal2 ( 1546160 1639120 ) Via2_VH ;
- - wbs_dat_o[22] ( PIN wbs_dat_o[22] ) ( mprj wbs_dat_o[22] ) + USE SIGNAL
- + ROUTED Metal2 ( 1613360 3920 ) ( 1616720 * )
- NEW Metal2 ( 1616720 3920 ) ( * 5040 )
- NEW Metal2 ( 1616720 5040 ) ( 1617840 * )
- NEW Metal2 ( 1617840 3920 0 ) ( * 5040 )
- NEW Metal3 ( 1613360 1650320 ) ( 1671600 * )
- NEW Metal2 ( 1613360 3920 ) ( * 1650320 )
- NEW Metal2 ( 1671600 1650320 ) ( * 1690640 0 )
- NEW Metal2 ( 1613360 1650320 ) Via2_VH
- NEW Metal2 ( 1671600 1650320 ) Via2_VH ;
- - wbs_dat_o[23] ( PIN wbs_dat_o[23] ) ( mprj wbs_dat_o[23] ) + USE SIGNAL
- + ROUTED Metal2 ( 1677200 3920 0 ) ( * 42000 )
- NEW Metal2 ( 1677200 42000 ) ( 1681680 * )
- NEW Metal2 ( 1686160 1690640 ) ( 1688400 * 0 )
- NEW Metal2 ( 1681680 1587600 ) ( 1686160 * )
- NEW Metal2 ( 1681680 42000 ) ( * 1587600 )
- NEW Metal2 ( 1686160 1587600 ) ( * 1690640 ) ;
- - wbs_dat_o[24] ( PIN wbs_dat_o[24] ) ( mprj wbs_dat_o[24] ) + USE SIGNAL
- + ROUTED Metal3 ( 1726480 1495760 ) ( 1732080 * )
- NEW Metal2 ( 1732080 3920 0 ) ( * 1495760 )
- NEW Metal3 ( 1705200 1649200 ) ( 1726480 * )
- NEW Metal2 ( 1726480 1495760 ) ( * 1649200 )
- NEW Metal2 ( 1705200 1649200 ) ( * 1690640 0 )
- NEW Metal2 ( 1726480 1495760 ) Via2_VH
- NEW Metal2 ( 1732080 1495760 ) Via2_VH
- NEW Metal2 ( 1705200 1649200 ) Via2_VH
- NEW Metal2 ( 1726480 1649200 ) Via2_VH ;
- - wbs_dat_o[25] ( PIN wbs_dat_o[25] ) ( mprj wbs_dat_o[25] ) + USE SIGNAL
- + ROUTED Metal2 ( 1782480 3920 ) ( 1788080 * )
- NEW Metal2 ( 1788080 3920 ) ( * 5040 )
- NEW Metal2 ( 1788080 5040 ) ( 1789200 * )
- NEW Metal2 ( 1789200 3920 0 ) ( * 5040 )
- NEW Metal3 ( 1738800 940240 ) ( 1782480 * )
- NEW Metal2 ( 1782480 3920 ) ( * 940240 )
- NEW Metal3 ( 1722000 1650320 ) ( 1738800 * )
- NEW Metal2 ( 1738800 940240 ) ( * 1650320 )
- NEW Metal2 ( 1722000 1650320 ) ( * 1690640 0 )
- NEW Metal2 ( 1738800 940240 ) Via2_VH
- NEW Metal2 ( 1782480 940240 ) Via2_VH
- NEW Metal2 ( 1722000 1650320 ) Via2_VH
- NEW Metal2 ( 1738800 1650320 ) Via2_VH ;
- - wbs_dat_o[26] ( PIN wbs_dat_o[26] ) ( mprj wbs_dat_o[26] ) + USE SIGNAL
- + ROUTED Metal2 ( 1832880 3920 ) ( 1845200 * )
- NEW Metal2 ( 1845200 3920 ) ( * 5040 )
- NEW Metal2 ( 1845200 5040 ) ( 1846320 * )
- NEW Metal2 ( 1846320 3920 0 ) ( * 5040 )
- NEW Metal3 ( 1730960 133840 ) ( 1832880 * )
- NEW Metal2 ( 1832880 3920 ) ( * 133840 )
- NEW Metal2 ( 1730960 1564080 ) ( 1735440 * )
- NEW Metal2 ( 1730960 133840 ) ( * 1564080 )
- NEW Metal2 ( 1735440 1690640 ) ( 1738800 * 0 )
- NEW Metal2 ( 1735440 1564080 ) ( * 1690640 )
- NEW Metal2 ( 1730960 133840 ) Via2_VH
- NEW Metal2 ( 1832880 133840 ) Via2_VH ;
- - wbs_dat_o[27] ( PIN wbs_dat_o[27] ) ( mprj wbs_dat_o[27] ) + USE SIGNAL
- + ROUTED Metal2 ( 1902320 201600 ) ( 1903440 * )
- NEW Metal2 ( 1903440 3920 0 ) ( * 201600 )
- NEW Metal2 ( 1902320 201600 ) ( * 932400 )
- NEW Metal3 ( 1789200 932400 ) ( 1902320 * )
- NEW Metal3 ( 1755600 1650320 ) ( 1789200 * )
- NEW Metal2 ( 1789200 932400 ) ( * 1650320 )
- NEW Metal2 ( 1755600 1650320 ) ( * 1690640 0 )
- NEW Metal2 ( 1902320 932400 ) Via2_VH
- NEW Metal2 ( 1789200 932400 ) Via2_VH
- NEW Metal2 ( 1755600 1650320 ) Via2_VH
- NEW Metal2 ( 1789200 1650320 ) Via2_VH ;
- - wbs_dat_o[28] ( PIN wbs_dat_o[28] ) ( mprj wbs_dat_o[28] ) + USE SIGNAL
- + ROUTED Metal2 ( 1949360 3920 ) ( 1959440 * )
- NEW Metal2 ( 1959440 3920 ) ( * 5040 )
- NEW Metal2 ( 1959440 5040 ) ( 1960560 * )
- NEW Metal2 ( 1960560 3920 0 ) ( * 5040 )
- NEW Metal2 ( 1949360 3920 ) ( * 1655920 )
- NEW Metal3 ( 1772400 1655920 ) ( 1949360 * )
- NEW Metal2 ( 1772400 1655920 ) ( * 1690640 0 )
- NEW Metal2 ( 1949360 1655920 ) Via2_VH
- NEW Metal2 ( 1772400 1655920 ) Via2_VH ;
- - wbs_dat_o[29] ( PIN wbs_dat_o[29] ) ( mprj wbs_dat_o[29] ) + USE SIGNAL
- + ROUTED Metal3 ( 1906800 47600 ) ( * 48720 )
- NEW Metal3 ( 1783600 47600 ) ( 1906800 * )
- NEW Metal2 ( 2017680 3920 0 ) ( * 48720 )
- NEW Metal3 ( 1906800 48720 ) ( 2017680 * )
- NEW Metal2 ( 1783600 47600 ) ( * 1495200 )
- NEW Metal2 ( 1783600 1495200 ) ( 1785840 * )
- NEW Metal2 ( 1785840 1690640 ) ( 1789200 * 0 )
- NEW Metal2 ( 1785840 1495200 ) ( * 1690640 )
- NEW Metal2 ( 1783600 47600 ) Via2_VH
- NEW Metal2 ( 2017680 48720 ) Via2_VH ;
- - wbs_dat_o[2] ( PIN wbs_dat_o[2] ) ( mprj wbs_dat_o[2] ) + USE SIGNAL
- + ROUTED Metal2 ( 439600 3920 0 ) ( * 43120 )
- NEW Metal3 ( 439600 43120 ) ( 462000 * )
- NEW Metal2 ( 462000 43120 ) ( * 1639120 )
- NEW Metal2 ( 1324400 1639120 ) ( * 1690640 0 )
- NEW Metal3 ( 462000 1639120 ) ( 1324400 * )
- NEW Metal2 ( 439600 43120 ) Via2_VH
- NEW Metal2 ( 462000 43120 ) Via2_VH
- NEW Metal2 ( 462000 1639120 ) Via2_VH
- NEW Metal2 ( 1324400 1639120 ) Via2_VH ;
- - wbs_dat_o[30] ( PIN wbs_dat_o[30] ) ( mprj wbs_dat_o[30] ) + USE SIGNAL
- + ROUTED Metal2 ( 2074800 3920 0 ) ( * 46480 )
- NEW Metal3 ( 1800400 46480 ) ( 2074800 * )
- NEW Metal2 ( 1800400 46480 ) ( * 1495200 )
- NEW Metal2 ( 1800400 1495200 ) ( 1802640 * )
- NEW Metal2 ( 1802640 1690640 ) ( 1806000 * 0 )
- NEW Metal2 ( 1802640 1495200 ) ( * 1690640 )
- NEW Metal2 ( 1800400 46480 ) Via2_VH
- NEW Metal2 ( 2074800 46480 ) Via2_VH ;
- - wbs_dat_o[31] ( PIN wbs_dat_o[31] ) ( mprj wbs_dat_o[31] ) + USE SIGNAL
- + ROUTED Metal2 ( 2131920 3920 0 ) ( * 80080 )
- NEW Metal3 ( 1814960 80080 ) ( 2131920 * )
- NEW Metal3 ( 1814960 1621200 ) ( 1820560 * )
- NEW Metal2 ( 1814960 80080 ) ( * 1621200 )
- NEW Metal2 ( 1820560 1690640 ) ( 1822800 * 0 )
- NEW Metal2 ( 1820560 1621200 ) ( * 1690640 )
- NEW Metal2 ( 2131920 80080 ) Via2_VH
- NEW Metal2 ( 1814960 80080 ) Via2_VH
- NEW Metal2 ( 1814960 1621200 ) Via2_VH
- NEW Metal2 ( 1820560 1621200 ) Via2_VH ;
- - wbs_dat_o[3] ( PIN wbs_dat_o[3] ) ( mprj wbs_dat_o[3] ) + USE SIGNAL
- + ROUTED Metal2 ( 504560 3920 ) ( 512400 * )
- NEW Metal2 ( 512400 3920 ) ( * 5040 )
- NEW Metal2 ( 512400 5040 ) ( 513520 * )
- NEW Metal2 ( 513520 3920 0 ) ( * 5040 )
- NEW Metal2 ( 504560 3920 ) ( * 1589840 )
- NEW Metal3 ( 504560 1589840 ) ( 1302000 * )
- NEW Metal2 ( 1302000 1589840 ) ( * 1648080 )
- NEW Metal3 ( 1302000 1648080 ) ( 1346800 * )
- NEW Metal2 ( 1346800 1648080 ) ( * 1690640 0 )
- NEW Metal2 ( 504560 1589840 ) Via2_VH
- NEW Metal2 ( 1302000 1648080 ) Via2_VH
- NEW Metal2 ( 1302000 1589840 ) Via2_VH
- NEW Metal2 ( 1346800 1648080 ) Via2_VH ;
- - wbs_dat_o[4] ( PIN wbs_dat_o[4] ) ( mprj wbs_dat_o[4] ) + USE SIGNAL
- + ROUTED Metal2 ( 591920 3920 0 ) ( * 40880 )
- NEW Metal3 ( 591920 40880 ) ( 646800 * )
- NEW Metal2 ( 1365840 1690640 ) ( 1369200 * 0 )
- NEW Metal2 ( 646800 40880 ) ( * 1657040 )
- NEW Metal3 ( 646800 1657040 ) ( 1365840 * )
- NEW Metal2 ( 1365840 1657040 ) ( * 1690640 )
- NEW Metal2 ( 591920 40880 ) Via2_VH
- NEW Metal2 ( 646800 40880 ) Via2_VH
- NEW Metal2 ( 646800 1657040 ) Via2_VH
- NEW Metal2 ( 1365840 1657040 ) Via2_VH ;
- - wbs_dat_o[5] ( PIN wbs_dat_o[5] ) ( mprj wbs_dat_o[5] ) + USE SIGNAL
- + ROUTED Metal2 ( 649040 3920 0 ) ( * 92400 )
- NEW Metal3 ( 649040 92400 ) ( 1369200 * )
- NEW Metal3 ( 1369200 1646960 ) ( 1386000 * )
- NEW Metal2 ( 1369200 92400 ) ( * 1646960 )
- NEW Metal2 ( 1386000 1646960 ) ( * 1690640 0 )
- NEW Metal2 ( 649040 92400 ) Via2_VH
- NEW Metal2 ( 1369200 92400 ) Via2_VH
- NEW Metal2 ( 1369200 1646960 ) Via2_VH
- NEW Metal2 ( 1386000 1646960 ) Via2_VH ;
- - wbs_dat_o[6] ( PIN wbs_dat_o[6] ) ( mprj wbs_dat_o[6] ) + USE SIGNAL
- + ROUTED Metal2 ( 705040 3920 0 ) ( * 40880 )
- NEW Metal3 ( 705040 40880 ) ( 714000 * )
- NEW Metal2 ( 714000 40880 ) ( * 1658160 )
- NEW Metal3 ( 714000 1658160 ) ( 1402800 * )
- NEW Metal2 ( 1402800 1658160 ) ( * 1690640 0 )
- NEW Metal2 ( 705040 40880 ) Via2_VH
- NEW Metal2 ( 714000 40880 ) Via2_VH
- NEW Metal2 ( 714000 1658160 ) Via2_VH
- NEW Metal2 ( 1402800 1658160 ) Via2_VH ;
- - wbs_dat_o[7] ( PIN wbs_dat_o[7] ) ( mprj wbs_dat_o[7] ) + USE SIGNAL
- + ROUTED Metal2 ( 763280 3920 0 ) ( * 44240 )
- NEW Metal2 ( 1416240 1690640 ) ( 1419600 * 0 )
- NEW Metal2 ( 1414000 44240 ) ( * 1495200 )
- NEW Metal2 ( 1414000 1495200 ) ( 1416240 * )
- NEW Metal3 ( 763280 44240 ) ( 1414000 * )
- NEW Metal2 ( 1416240 1495200 ) ( * 1690640 )
- NEW Metal2 ( 763280 44240 ) Via2_VH
- NEW Metal2 ( 1414000 44240 ) Via2_VH ;
- - wbs_dat_o[8] ( PIN wbs_dat_o[8] ) ( mprj wbs_dat_o[8] ) + USE SIGNAL
- + ROUTED Metal2 ( 820400 3920 0 ) ( * 40880 )
- NEW Metal3 ( 820400 40880 ) ( 848400 * )
- NEW Metal2 ( 848400 40880 ) ( * 1659280 )
- NEW Metal3 ( 848400 1659280 ) ( 1436400 * )
- NEW Metal2 ( 1436400 1659280 ) ( * 1690640 0 )
- NEW Metal2 ( 820400 40880 ) Via2_VH
- NEW Metal2 ( 848400 40880 ) Via2_VH
- NEW Metal2 ( 848400 1659280 ) Via2_VH
- NEW Metal2 ( 1436400 1659280 ) Via2_VH ;
- - wbs_dat_o[9] ( PIN wbs_dat_o[9] ) ( mprj wbs_dat_o[9] ) + USE SIGNAL
- + ROUTED Metal3 ( 1445360 1650320 ) ( 1449840 * )
- NEW Metal2 ( 1449840 1650320 ) ( * 1690640 )
- NEW Metal2 ( 1449840 1690640 ) ( 1453200 * 0 )
- NEW Metal2 ( 1445360 45360 ) ( * 1650320 )
- NEW Metal2 ( 877520 3920 0 ) ( * 45360 )
- NEW Metal3 ( 877520 45360 ) ( 1445360 * )
- NEW Metal2 ( 1445360 45360 ) Via2_VH
- NEW Metal2 ( 1445360 1650320 ) Via2_VH
- NEW Metal2 ( 1449840 1650320 ) Via2_VH
- NEW Metal2 ( 877520 45360 ) Via2_VH ;
- - wbs_sel_i[0] ( PIN wbs_sel_i[0] ) ( mprj wbs_sel_i[0] ) + USE SIGNAL
- + ROUTED Metal2 ( 306320 3920 0 ) ( * 58800 )
- NEW Metal3 ( 306320 58800 ) ( 1268400 * )
- NEW Metal3 ( 1268400 1650320 ) ( 1285200 * )
- NEW Metal2 ( 1285200 1650320 ) ( * 1690640 0 )
- NEW Metal2 ( 1268400 58800 ) ( * 1650320 )
- NEW Metal2 ( 306320 58800 ) Via2_VH
- NEW Metal2 ( 1268400 58800 ) Via2_VH
- NEW Metal2 ( 1268400 1650320 ) Via2_VH
- NEW Metal2 ( 1285200 1650320 ) Via2_VH ;
- - wbs_sel_i[1] ( PIN wbs_sel_i[1] ) ( mprj wbs_sel_i[1] ) + USE SIGNAL
- + ROUTED Metal2 ( 370160 3920 ) ( 379120 * )
- NEW Metal2 ( 379120 3920 ) ( * 5040 )
- NEW Metal2 ( 379120 5040 ) ( 380240 * )
- NEW Metal2 ( 380240 3920 0 ) ( * 5040 )
- NEW Metal2 ( 1307600 1660400 ) ( * 1690640 0 )
- NEW Metal3 ( 1100400 1660400 ) ( 1307600 * )
- NEW Metal2 ( 370160 3920 ) ( * 1590960 )
- NEW Metal3 ( 370160 1590960 ) ( 1100400 * )
- NEW Metal2 ( 1100400 1590960 ) ( * 1660400 )
- NEW Metal2 ( 1100400 1660400 ) Via2_VH
- NEW Metal2 ( 1307600 1660400 ) Via2_VH
- NEW Metal2 ( 370160 1590960 ) Via2_VH
- NEW Metal2 ( 1100400 1590960 ) Via2_VH ;
- - wbs_sel_i[2] ( PIN wbs_sel_i[2] ) ( mprj wbs_sel_i[2] ) + USE SIGNAL
- + ROUTED Metal2 ( 458640 3920 0 ) ( * 40880 )
- NEW Metal3 ( 458640 40880 ) ( 529200 * )
- NEW Metal2 ( 529200 40880 ) ( * 1537200 )
- NEW Metal3 ( 529200 1537200 ) ( 1330000 * )
- NEW Metal2 ( 1330000 1537200 ) ( * 1562400 )
- NEW Metal2 ( 1328880 1562400 ) ( 1330000 * )
- NEW Metal2 ( 1328880 1562400 ) ( * 1642480 )
- NEW Metal2 ( 1328880 1642480 ) ( 1330000 * )
- NEW Metal2 ( 1330000 1642480 ) ( * 1690640 0 )
- NEW Metal2 ( 458640 40880 ) Via2_VH
- NEW Metal2 ( 529200 40880 ) Via2_VH
- NEW Metal2 ( 529200 1537200 ) Via2_VH
- NEW Metal2 ( 1330000 1537200 ) Via2_VH ;
- - wbs_sel_i[3] ( PIN wbs_sel_i[3] ) ( mprj wbs_sel_i[3] ) + USE SIGNAL
- + ROUTED Metal2 ( 534800 3920 0 ) ( * 49840 )
- NEW Metal3 ( 534800 49840 ) ( 562800 * )
- NEW Metal2 ( 562800 49840 ) ( * 1655920 )
- NEW Metal3 ( 562800 1655920 ) ( 1352400 * )
- NEW Metal2 ( 1352400 1655920 ) ( * 1690640 0 )
- NEW Metal2 ( 534800 49840 ) Via2_VH
- NEW Metal2 ( 562800 49840 ) Via2_VH
- NEW Metal2 ( 562800 1655920 ) Via2_VH
- NEW Metal2 ( 1352400 1655920 ) Via2_VH ;
- - wbs_stb_i ( PIN wbs_stb_i ) ( mprj wbs_stb_i ) + USE SIGNAL
- + ROUTED Metal2 ( 211120 3920 0 ) ( * 45360 )
- NEW Metal3 ( 1243760 1651440 ) ( 1253840 * )
- NEW Metal2 ( 1253840 1651440 ) ( * 1690640 )
- NEW Metal2 ( 1253840 1690640 ) ( 1257200 * 0 )
- NEW Metal2 ( 764400 45360 ) ( * 1575280 )
- NEW Metal2 ( 1243760 1575280 ) ( * 1651440 )
- NEW Metal3 ( 211120 45360 ) ( 764400 * )
- NEW Metal3 ( 764400 1575280 ) ( 1243760 * )
- NEW Metal2 ( 211120 45360 ) Via2_VH
- NEW Metal2 ( 764400 45360 ) Via2_VH
- NEW Metal2 ( 1243760 1651440 ) Via2_VH
- NEW Metal2 ( 1253840 1651440 ) Via2_VH
- NEW Metal2 ( 764400 1575280 ) Via2_VH
- NEW Metal2 ( 1243760 1575280 ) Via2_VH ;
- - wbs_we_i ( PIN wbs_we_i ) ( mprj wbs_we_i ) + USE SIGNAL
- + ROUTED Metal2 ( 230160 3920 0 ) ( * 42000 )
- NEW Metal3 ( 230160 42000 ) ( 310800 * )
- NEW Metal2 ( 310800 42000 ) ( * 1654800 )
- NEW Metal2 ( 1262800 1654800 ) ( * 1690640 0 )
- NEW Metal3 ( 310800 1654800 ) ( 1262800 * )
- NEW Metal2 ( 230160 42000 ) Via2_VH
- NEW Metal2 ( 310800 42000 ) Via2_VH
- NEW Metal2 ( 310800 1654800 ) Via2_VH
- NEW Metal2 ( 1262800 1654800 ) Via2_VH ;
+ NEW Metal2 ( 118160 3920 ) ( * 2208080 )
+ NEW Metal3 ( 118160 2208080 ) ( 1177680 * 0 )
+ NEW Metal2 ( 118160 2208080 ) Via2_VH ;
+ - wb_rst_i ( PIN wb_rst_i ) ( wrapped_vga_clock wb_rst_i ) + USE SIGNAL
+ + ROUTED Metal3 ( 151760 1638000 ) ( 1784720 * )
+ NEW Metal2 ( 151760 3920 0 ) ( * 1638000 )
+ NEW Metal3 ( 1772400 1979600 0 ) ( 1784720 * )
+ NEW Metal2 ( 1784720 1638000 ) ( * 1979600 )
+ NEW Metal2 ( 151760 1638000 ) Via2_VH
+ NEW Metal2 ( 1784720 1638000 ) Via2_VH
+ NEW Metal2 ( 1784720 1979600 ) Via2_VH ;
+ - wbs_ack_o ( PIN wbs_ack_o ) + USE SIGNAL ;
+ - wbs_adr_i[0] ( PIN wbs_adr_i[0] ) + USE SIGNAL ;
+ - wbs_adr_i[10] ( PIN wbs_adr_i[10] ) + USE SIGNAL ;
+ - wbs_adr_i[11] ( PIN wbs_adr_i[11] ) + USE SIGNAL ;
+ - wbs_adr_i[12] ( PIN wbs_adr_i[12] ) + USE SIGNAL ;
+ - wbs_adr_i[13] ( PIN wbs_adr_i[13] ) + USE SIGNAL ;
+ - wbs_adr_i[14] ( PIN wbs_adr_i[14] ) + USE SIGNAL ;
+ - wbs_adr_i[15] ( PIN wbs_adr_i[15] ) + USE SIGNAL ;
+ - wbs_adr_i[16] ( PIN wbs_adr_i[16] ) + USE SIGNAL ;
+ - wbs_adr_i[17] ( PIN wbs_adr_i[17] ) + USE SIGNAL ;
+ - wbs_adr_i[18] ( PIN wbs_adr_i[18] ) + USE SIGNAL ;
+ - wbs_adr_i[19] ( PIN wbs_adr_i[19] ) + USE SIGNAL ;
+ - wbs_adr_i[1] ( PIN wbs_adr_i[1] ) + USE SIGNAL ;
+ - wbs_adr_i[20] ( PIN wbs_adr_i[20] ) + USE SIGNAL ;
+ - wbs_adr_i[21] ( PIN wbs_adr_i[21] ) + USE SIGNAL ;
+ - wbs_adr_i[22] ( PIN wbs_adr_i[22] ) + USE SIGNAL ;
+ - wbs_adr_i[23] ( PIN wbs_adr_i[23] ) + USE SIGNAL ;
+ - wbs_adr_i[24] ( PIN wbs_adr_i[24] ) + USE SIGNAL ;
+ - wbs_adr_i[25] ( PIN wbs_adr_i[25] ) + USE SIGNAL ;
+ - wbs_adr_i[26] ( PIN wbs_adr_i[26] ) + USE SIGNAL ;
+ - wbs_adr_i[27] ( PIN wbs_adr_i[27] ) + USE SIGNAL ;
+ - wbs_adr_i[28] ( PIN wbs_adr_i[28] ) + USE SIGNAL ;
+ - wbs_adr_i[29] ( PIN wbs_adr_i[29] ) + USE SIGNAL ;
+ - wbs_adr_i[2] ( PIN wbs_adr_i[2] ) + USE SIGNAL ;
+ - wbs_adr_i[30] ( PIN wbs_adr_i[30] ) + USE SIGNAL ;
+ - wbs_adr_i[31] ( PIN wbs_adr_i[31] ) + USE SIGNAL ;
+ - wbs_adr_i[3] ( PIN wbs_adr_i[3] ) + USE SIGNAL ;
+ - wbs_adr_i[4] ( PIN wbs_adr_i[4] ) + USE SIGNAL ;
+ - wbs_adr_i[5] ( PIN wbs_adr_i[5] ) + USE SIGNAL ;
+ - wbs_adr_i[6] ( PIN wbs_adr_i[6] ) + USE SIGNAL ;
+ - wbs_adr_i[7] ( PIN wbs_adr_i[7] ) + USE SIGNAL ;
+ - wbs_adr_i[8] ( PIN wbs_adr_i[8] ) + USE SIGNAL ;
+ - wbs_adr_i[9] ( PIN wbs_adr_i[9] ) + USE SIGNAL ;
+ - wbs_cyc_i ( PIN wbs_cyc_i ) + USE SIGNAL ;
+ - wbs_dat_i[0] ( PIN wbs_dat_i[0] ) + USE SIGNAL ;
+ - wbs_dat_i[10] ( PIN wbs_dat_i[10] ) + USE SIGNAL ;
+ - wbs_dat_i[11] ( PIN wbs_dat_i[11] ) + USE SIGNAL ;
+ - wbs_dat_i[12] ( PIN wbs_dat_i[12] ) + USE SIGNAL ;
+ - wbs_dat_i[13] ( PIN wbs_dat_i[13] ) + USE SIGNAL ;
+ - wbs_dat_i[14] ( PIN wbs_dat_i[14] ) + USE SIGNAL ;
+ - wbs_dat_i[15] ( PIN wbs_dat_i[15] ) + USE SIGNAL ;
+ - wbs_dat_i[16] ( PIN wbs_dat_i[16] ) + USE SIGNAL ;
+ - wbs_dat_i[17] ( PIN wbs_dat_i[17] ) + USE SIGNAL ;
+ - wbs_dat_i[18] ( PIN wbs_dat_i[18] ) + USE SIGNAL ;
+ - wbs_dat_i[19] ( PIN wbs_dat_i[19] ) + USE SIGNAL ;
+ - wbs_dat_i[1] ( PIN wbs_dat_i[1] ) + USE SIGNAL ;
+ - wbs_dat_i[20] ( PIN wbs_dat_i[20] ) + USE SIGNAL ;
+ - wbs_dat_i[21] ( PIN wbs_dat_i[21] ) + USE SIGNAL ;
+ - wbs_dat_i[22] ( PIN wbs_dat_i[22] ) + USE SIGNAL ;
+ - wbs_dat_i[23] ( PIN wbs_dat_i[23] ) + USE SIGNAL ;
+ - wbs_dat_i[24] ( PIN wbs_dat_i[24] ) + USE SIGNAL ;
+ - wbs_dat_i[25] ( PIN wbs_dat_i[25] ) + USE SIGNAL ;
+ - wbs_dat_i[26] ( PIN wbs_dat_i[26] ) + USE SIGNAL ;
+ - wbs_dat_i[27] ( PIN wbs_dat_i[27] ) + USE SIGNAL ;
+ - wbs_dat_i[28] ( PIN wbs_dat_i[28] ) + USE SIGNAL ;
+ - wbs_dat_i[29] ( PIN wbs_dat_i[29] ) + USE SIGNAL ;
+ - wbs_dat_i[2] ( PIN wbs_dat_i[2] ) + USE SIGNAL ;
+ - wbs_dat_i[30] ( PIN wbs_dat_i[30] ) + USE SIGNAL ;
+ - wbs_dat_i[31] ( PIN wbs_dat_i[31] ) + USE SIGNAL ;
+ - wbs_dat_i[3] ( PIN wbs_dat_i[3] ) + USE SIGNAL ;
+ - wbs_dat_i[4] ( PIN wbs_dat_i[4] ) + USE SIGNAL ;
+ - wbs_dat_i[5] ( PIN wbs_dat_i[5] ) + USE SIGNAL ;
+ - wbs_dat_i[6] ( PIN wbs_dat_i[6] ) + USE SIGNAL ;
+ - wbs_dat_i[7] ( PIN wbs_dat_i[7] ) + USE SIGNAL ;
+ - wbs_dat_i[8] ( PIN wbs_dat_i[8] ) + USE SIGNAL ;
+ - wbs_dat_i[9] ( PIN wbs_dat_i[9] ) + USE SIGNAL ;
+ - wbs_dat_o[0] ( PIN wbs_dat_o[0] ) + USE SIGNAL ;
+ - wbs_dat_o[10] ( PIN wbs_dat_o[10] ) + USE SIGNAL ;
+ - wbs_dat_o[11] ( PIN wbs_dat_o[11] ) + USE SIGNAL ;
+ - wbs_dat_o[12] ( PIN wbs_dat_o[12] ) + USE SIGNAL ;
+ - wbs_dat_o[13] ( PIN wbs_dat_o[13] ) + USE SIGNAL ;
+ - wbs_dat_o[14] ( PIN wbs_dat_o[14] ) + USE SIGNAL ;
+ - wbs_dat_o[15] ( PIN wbs_dat_o[15] ) + USE SIGNAL ;
+ - wbs_dat_o[16] ( PIN wbs_dat_o[16] ) + USE SIGNAL ;
+ - wbs_dat_o[17] ( PIN wbs_dat_o[17] ) + USE SIGNAL ;
+ - wbs_dat_o[18] ( PIN wbs_dat_o[18] ) + USE SIGNAL ;
+ - wbs_dat_o[19] ( PIN wbs_dat_o[19] ) + USE SIGNAL ;
+ - wbs_dat_o[1] ( PIN wbs_dat_o[1] ) + USE SIGNAL ;
+ - wbs_dat_o[20] ( PIN wbs_dat_o[20] ) + USE SIGNAL ;
+ - wbs_dat_o[21] ( PIN wbs_dat_o[21] ) + USE SIGNAL ;
+ - wbs_dat_o[22] ( PIN wbs_dat_o[22] ) + USE SIGNAL ;
+ - wbs_dat_o[23] ( PIN wbs_dat_o[23] ) + USE SIGNAL ;
+ - wbs_dat_o[24] ( PIN wbs_dat_o[24] ) + USE SIGNAL ;
+ - wbs_dat_o[25] ( PIN wbs_dat_o[25] ) + USE SIGNAL ;
+ - wbs_dat_o[26] ( PIN wbs_dat_o[26] ) + USE SIGNAL ;
+ - wbs_dat_o[27] ( PIN wbs_dat_o[27] ) + USE SIGNAL ;
+ - wbs_dat_o[28] ( PIN wbs_dat_o[28] ) + USE SIGNAL ;
+ - wbs_dat_o[29] ( PIN wbs_dat_o[29] ) + USE SIGNAL ;
+ - wbs_dat_o[2] ( PIN wbs_dat_o[2] ) + USE SIGNAL ;
+ - wbs_dat_o[30] ( PIN wbs_dat_o[30] ) + USE SIGNAL ;
+ - wbs_dat_o[31] ( PIN wbs_dat_o[31] ) + USE SIGNAL ;
+ - wbs_dat_o[3] ( PIN wbs_dat_o[3] ) + USE SIGNAL ;
+ - wbs_dat_o[4] ( PIN wbs_dat_o[4] ) + USE SIGNAL ;
+ - wbs_dat_o[5] ( PIN wbs_dat_o[5] ) + USE SIGNAL ;
+ - wbs_dat_o[6] ( PIN wbs_dat_o[6] ) + USE SIGNAL ;
+ - wbs_dat_o[7] ( PIN wbs_dat_o[7] ) + USE SIGNAL ;
+ - wbs_dat_o[8] ( PIN wbs_dat_o[8] ) + USE SIGNAL ;
+ - wbs_dat_o[9] ( PIN wbs_dat_o[9] ) + USE SIGNAL ;
+ - wbs_sel_i[0] ( PIN wbs_sel_i[0] ) + USE SIGNAL ;
+ - wbs_sel_i[1] ( PIN wbs_sel_i[1] ) + USE SIGNAL ;
+ - wbs_sel_i[2] ( PIN wbs_sel_i[2] ) + USE SIGNAL ;
+ - wbs_sel_i[3] ( PIN wbs_sel_i[3] ) + USE SIGNAL ;
+ - wbs_stb_i ( PIN wbs_stb_i ) + USE SIGNAL ;
+ - wbs_we_i ( PIN wbs_we_i ) + USE SIGNAL ;
END NETS
END DESIGN
diff --git a/def/wrapped_vga_clock.def b/def/wrapped_vga_clock.def
new file mode 100644
index 0000000..345a890
--- /dev/null
+++ b/def/wrapped_vga_clock.def
@@ -0,0 +1,21532 @@
+VERSION 5.8 ;
+DIVIDERCHAR "/" ;
+BUSBITCHARS "[]" ;
+DESIGN wrapped_vga_clock ;
+UNITS DISTANCE MICRONS 2000 ;
+DIEAREA ( 0 0 ) ( 600000 600000 ) ;
+ROW ROW_0 GF018hv5v_mcu_sc7 13440 31360 N DO 511 BY 1 STEP 1120 0 ;
+ROW ROW_1 GF018hv5v_mcu_sc7 13440 39200 FS DO 511 BY 1 STEP 1120 0 ;
+ROW ROW_2 GF018hv5v_mcu_sc7 13440 47040 N DO 511 BY 1 STEP 1120 0 ;
+ROW ROW_3 GF018hv5v_mcu_sc7 13440 54880 FS DO 511 BY 1 STEP 1120 0 ;
+ROW ROW_4 GF018hv5v_mcu_sc7 13440 62720 N DO 511 BY 1 STEP 1120 0 ;
+ROW ROW_5 GF018hv5v_mcu_sc7 13440 70560 FS DO 511 BY 1 STEP 1120 0 ;
+ROW ROW_6 GF018hv5v_mcu_sc7 13440 78400 N DO 511 BY 1 STEP 1120 0 ;
+ROW ROW_7 GF018hv5v_mcu_sc7 13440 86240 FS DO 511 BY 1 STEP 1120 0 ;
+ROW ROW_8 GF018hv5v_mcu_sc7 13440 94080 N DO 511 BY 1 STEP 1120 0 ;
+ROW ROW_9 GF018hv5v_mcu_sc7 13440 101920 FS DO 511 BY 1 STEP 1120 0 ;
+ROW ROW_10 GF018hv5v_mcu_sc7 13440 109760 N DO 511 BY 1 STEP 1120 0 ;
+ROW ROW_11 GF018hv5v_mcu_sc7 13440 117600 FS DO 511 BY 1 STEP 1120 0 ;
+ROW ROW_12 GF018hv5v_mcu_sc7 13440 125440 N DO 511 BY 1 STEP 1120 0 ;
+ROW ROW_13 GF018hv5v_mcu_sc7 13440 133280 FS DO 511 BY 1 STEP 1120 0 ;
+ROW ROW_14 GF018hv5v_mcu_sc7 13440 141120 N DO 511 BY 1 STEP 1120 0 ;
+ROW ROW_15 GF018hv5v_mcu_sc7 13440 148960 FS DO 511 BY 1 STEP 1120 0 ;
+ROW ROW_16 GF018hv5v_mcu_sc7 13440 156800 N DO 511 BY 1 STEP 1120 0 ;
+ROW ROW_17 GF018hv5v_mcu_sc7 13440 164640 FS DO 511 BY 1 STEP 1120 0 ;
+ROW ROW_18 GF018hv5v_mcu_sc7 13440 172480 N DO 511 BY 1 STEP 1120 0 ;
+ROW ROW_19 GF018hv5v_mcu_sc7 13440 180320 FS DO 511 BY 1 STEP 1120 0 ;
+ROW ROW_20 GF018hv5v_mcu_sc7 13440 188160 N DO 511 BY 1 STEP 1120 0 ;
+ROW ROW_21 GF018hv5v_mcu_sc7 13440 196000 FS DO 511 BY 1 STEP 1120 0 ;
+ROW ROW_22 GF018hv5v_mcu_sc7 13440 203840 N DO 511 BY 1 STEP 1120 0 ;
+ROW ROW_23 GF018hv5v_mcu_sc7 13440 211680 FS DO 511 BY 1 STEP 1120 0 ;
+ROW ROW_24 GF018hv5v_mcu_sc7 13440 219520 N DO 511 BY 1 STEP 1120 0 ;
+ROW ROW_25 GF018hv5v_mcu_sc7 13440 227360 FS DO 511 BY 1 STEP 1120 0 ;
+ROW ROW_26 GF018hv5v_mcu_sc7 13440 235200 N DO 511 BY 1 STEP 1120 0 ;
+ROW ROW_27 GF018hv5v_mcu_sc7 13440 243040 FS DO 511 BY 1 STEP 1120 0 ;
+ROW ROW_28 GF018hv5v_mcu_sc7 13440 250880 N DO 511 BY 1 STEP 1120 0 ;
+ROW ROW_29 GF018hv5v_mcu_sc7 13440 258720 FS DO 511 BY 1 STEP 1120 0 ;
+ROW ROW_30 GF018hv5v_mcu_sc7 13440 266560 N DO 511 BY 1 STEP 1120 0 ;
+ROW ROW_31 GF018hv5v_mcu_sc7 13440 274400 FS DO 511 BY 1 STEP 1120 0 ;
+ROW ROW_32 GF018hv5v_mcu_sc7 13440 282240 N DO 511 BY 1 STEP 1120 0 ;
+ROW ROW_33 GF018hv5v_mcu_sc7 13440 290080 FS DO 511 BY 1 STEP 1120 0 ;
+ROW ROW_34 GF018hv5v_mcu_sc7 13440 297920 N DO 511 BY 1 STEP 1120 0 ;
+ROW ROW_35 GF018hv5v_mcu_sc7 13440 305760 FS DO 511 BY 1 STEP 1120 0 ;
+ROW ROW_36 GF018hv5v_mcu_sc7 13440 313600 N DO 511 BY 1 STEP 1120 0 ;
+ROW ROW_37 GF018hv5v_mcu_sc7 13440 321440 FS DO 511 BY 1 STEP 1120 0 ;
+ROW ROW_38 GF018hv5v_mcu_sc7 13440 329280 N DO 511 BY 1 STEP 1120 0 ;
+ROW ROW_39 GF018hv5v_mcu_sc7 13440 337120 FS DO 511 BY 1 STEP 1120 0 ;
+ROW ROW_40 GF018hv5v_mcu_sc7 13440 344960 N DO 511 BY 1 STEP 1120 0 ;
+ROW ROW_41 GF018hv5v_mcu_sc7 13440 352800 FS DO 511 BY 1 STEP 1120 0 ;
+ROW ROW_42 GF018hv5v_mcu_sc7 13440 360640 N DO 511 BY 1 STEP 1120 0 ;
+ROW ROW_43 GF018hv5v_mcu_sc7 13440 368480 FS DO 511 BY 1 STEP 1120 0 ;
+ROW ROW_44 GF018hv5v_mcu_sc7 13440 376320 N DO 511 BY 1 STEP 1120 0 ;
+ROW ROW_45 GF018hv5v_mcu_sc7 13440 384160 FS DO 511 BY 1 STEP 1120 0 ;
+ROW ROW_46 GF018hv5v_mcu_sc7 13440 392000 N DO 511 BY 1 STEP 1120 0 ;
+ROW ROW_47 GF018hv5v_mcu_sc7 13440 399840 FS DO 511 BY 1 STEP 1120 0 ;
+ROW ROW_48 GF018hv5v_mcu_sc7 13440 407680 N DO 511 BY 1 STEP 1120 0 ;
+ROW ROW_49 GF018hv5v_mcu_sc7 13440 415520 FS DO 511 BY 1 STEP 1120 0 ;
+ROW ROW_50 GF018hv5v_mcu_sc7 13440 423360 N DO 511 BY 1 STEP 1120 0 ;
+ROW ROW_51 GF018hv5v_mcu_sc7 13440 431200 FS DO 511 BY 1 STEP 1120 0 ;
+ROW ROW_52 GF018hv5v_mcu_sc7 13440 439040 N DO 511 BY 1 STEP 1120 0 ;
+ROW ROW_53 GF018hv5v_mcu_sc7 13440 446880 FS DO 511 BY 1 STEP 1120 0 ;
+ROW ROW_54 GF018hv5v_mcu_sc7 13440 454720 N DO 511 BY 1 STEP 1120 0 ;
+ROW ROW_55 GF018hv5v_mcu_sc7 13440 462560 FS DO 511 BY 1 STEP 1120 0 ;
+ROW ROW_56 GF018hv5v_mcu_sc7 13440 470400 N DO 511 BY 1 STEP 1120 0 ;
+ROW ROW_57 GF018hv5v_mcu_sc7 13440 478240 FS DO 511 BY 1 STEP 1120 0 ;
+ROW ROW_58 GF018hv5v_mcu_sc7 13440 486080 N DO 511 BY 1 STEP 1120 0 ;
+ROW ROW_59 GF018hv5v_mcu_sc7 13440 493920 FS DO 511 BY 1 STEP 1120 0 ;
+ROW ROW_60 GF018hv5v_mcu_sc7 13440 501760 N DO 511 BY 1 STEP 1120 0 ;
+ROW ROW_61 GF018hv5v_mcu_sc7 13440 509600 FS DO 511 BY 1 STEP 1120 0 ;
+ROW ROW_62 GF018hv5v_mcu_sc7 13440 517440 N DO 511 BY 1 STEP 1120 0 ;
+ROW ROW_63 GF018hv5v_mcu_sc7 13440 525280 FS DO 511 BY 1 STEP 1120 0 ;
+ROW ROW_64 GF018hv5v_mcu_sc7 13440 533120 N DO 511 BY 1 STEP 1120 0 ;
+ROW ROW_65 GF018hv5v_mcu_sc7 13440 540960 FS DO 511 BY 1 STEP 1120 0 ;
+ROW ROW_66 GF018hv5v_mcu_sc7 13440 548800 N DO 511 BY 1 STEP 1120 0 ;
+ROW ROW_67 GF018hv5v_mcu_sc7 13440 556640 FS DO 511 BY 1 STEP 1120 0 ;
+TRACKS X 560 DO 536 STEP 1120 LAYER Metal1 ;
+TRACKS Y 560 DO 536 STEP 1120 LAYER Metal1 ;
+TRACKS X 560 DO 535 STEP 1120 LAYER Metal2 ;
+TRACKS Y 560 DO 535 STEP 1120 LAYER Metal2 ;
+TRACKS X 560 DO 535 STEP 1120 LAYER Metal3 ;
+TRACKS Y 560 DO 535 STEP 1120 LAYER Metal3 ;
+TRACKS X 560 DO 535 STEP 1120 LAYER Metal4 ;
+TRACKS Y 560 DO 535 STEP 1120 LAYER Metal4 ;
+TRACKS X 560 DO 535 STEP 1120 LAYER Metal5 ;
+TRACKS Y 560 DO 535 STEP 1120 LAYER Metal5 ;
+GCELLGRID X 0 DO 35 STEP 16800 ;
+GCELLGRID Y 0 DO 35 STEP 16800 ;
+VIAS 3 ;
+ - via1_2_3200_1200_1_3_1040_1040 + VIARULE Via1_GEN_HH + CUTSIZE 520 520 + LAYERS Metal1 Via1 Metal2 + CUTSPACING 520 520 + ENCLOSURE 120 340 20 120 + ROWCOL 1 3 ;
+ - via2_3_3200_1200_1_3_1040_1040 + VIARULE Via2_GEN_HH + CUTSIZE 520 520 + LAYERS Metal2 Via2 Metal3 + CUTSPACING 520 520 + ENCLOSURE 20 120 120 20 + ROWCOL 1 3 ;
+ - via3_4_3200_1200_1_3_1040_1040 + VIARULE Via3_GEN_HH + CUTSIZE 520 520 + LAYERS Metal3 Via3 Metal4 + CUTSPACING 520 520 + ENCLOSURE 120 20 300 120 + ROWCOL 1 3 ;
+END VIAS
+COMPONENTS 5674 ;
+ - ANTENNA__0675__A2 gf180mcu_fd_sc_mcu7t5v0__antenna + PLACED ( 191520 313600 ) FN ;
+ - ANTENNA__0678__A2 gf180mcu_fd_sc_mcu7t5v0__antenna + PLACED ( 255360 305760 ) FS ;
+ - ANTENNA__0680__A2 gf180mcu_fd_sc_mcu7t5v0__antenna + PLACED ( 225120 313600 ) FN ;
+ - ANTENNA__0682__A2 gf180mcu_fd_sc_mcu7t5v0__antenna + PLACED ( 208320 329280 ) N ;
+ - ANTENNA__0686__A1 gf180mcu_fd_sc_mcu7t5v0__antenna + PLACED ( 267680 329280 ) N ;
+ - ANTENNA__0686__A2 gf180mcu_fd_sc_mcu7t5v0__antenna + PLACED ( 272160 329280 ) FN ;
+ - ANTENNA__0688__A3 gf180mcu_fd_sc_mcu7t5v0__antenna + PLACED ( 227360 321440 ) FS ;
+ - ANTENNA__0690__I gf180mcu_fd_sc_mcu7t5v0__antenna + PLACED ( 507360 290080 ) FS ;
+ - ANTENNA__0692__I gf180mcu_fd_sc_mcu7t5v0__antenna + PLACED ( 215040 94080 ) N ;
+ - ANTENNA__0694__A3 gf180mcu_fd_sc_mcu7t5v0__antenna + PLACED ( 392000 172480 ) N ;
+ - ANTENNA__0698__A2 gf180mcu_fd_sc_mcu7t5v0__antenna + PLACED ( 403200 156800 ) N ;
+ - ANTENNA__0702__A2 gf180mcu_fd_sc_mcu7t5v0__antenna + PLACED ( 432320 133280 ) FS ;
+ - ANTENNA__0705__A1 gf180mcu_fd_sc_mcu7t5v0__antenna + PLACED ( 464800 141120 ) N ;
+ - ANTENNA__0707__I gf180mcu_fd_sc_mcu7t5v0__antenna + PLACED ( 400960 148960 ) FS ;
+ - ANTENNA__0708__A1 gf180mcu_fd_sc_mcu7t5v0__antenna + PLACED ( 412160 156800 ) N ;
+ - ANTENNA__0728__A1 gf180mcu_fd_sc_mcu7t5v0__antenna + PLACED ( 453600 156800 ) N ;
+ - ANTENNA__0732__A1 gf180mcu_fd_sc_mcu7t5v0__antenna + PLACED ( 520800 133280 ) FS ;
+ - ANTENNA__0732__A2 gf180mcu_fd_sc_mcu7t5v0__antenna + PLACED ( 516320 133280 ) S ;
+ - ANTENNA__0733__A1 gf180mcu_fd_sc_mcu7t5v0__antenna + PLACED ( 542080 164640 ) FS ;
+ - ANTENNA__0735__I gf180mcu_fd_sc_mcu7t5v0__antenna + PLACED ( 556640 180320 ) FS ;
+ - ANTENNA__0736__A1 gf180mcu_fd_sc_mcu7t5v0__antenna + PLACED ( 543200 196000 ) FS ;
+ - ANTENNA__0737__A1 gf180mcu_fd_sc_mcu7t5v0__antenna + PLACED ( 547680 196000 ) FS ;
+ - ANTENNA__0737__A2 gf180mcu_fd_sc_mcu7t5v0__antenna + PLACED ( 558880 188160 ) N ;
+ - ANTENNA__0738__A1 gf180mcu_fd_sc_mcu7t5v0__antenna + PLACED ( 516320 172480 ) N ;
+ - ANTENNA__0738__A2 gf180mcu_fd_sc_mcu7t5v0__antenna + PLACED ( 511840 172480 ) N ;
+ - ANTENNA__0738__A3 gf180mcu_fd_sc_mcu7t5v0__antenna + PLACED ( 520800 172480 ) FN ;
+ - ANTENNA__0740__A2 gf180mcu_fd_sc_mcu7t5v0__antenna + PLACED ( 498400 172480 ) N ;
+ - ANTENNA__0741__A1 gf180mcu_fd_sc_mcu7t5v0__antenna + PLACED ( 476000 196000 ) S ;
+ - ANTENNA__0741__A2 gf180mcu_fd_sc_mcu7t5v0__antenna + PLACED ( 483840 180320 ) FS ;
+ - ANTENNA__0742__I gf180mcu_fd_sc_mcu7t5v0__antenna + PLACED ( 500640 133280 ) FS ;
+ - ANTENNA__0744__A2 gf180mcu_fd_sc_mcu7t5v0__antenna + PLACED ( 482720 148960 ) FS ;
+ - ANTENNA__0744__B gf180mcu_fd_sc_mcu7t5v0__antenna + PLACED ( 487200 148960 ) FS ;
+ - ANTENNA__0745__A1 gf180mcu_fd_sc_mcu7t5v0__antenna + PLACED ( 507360 164640 ) FS ;
+ - ANTENNA__0745__C gf180mcu_fd_sc_mcu7t5v0__antenna + PLACED ( 511840 164640 ) FS ;
+ - ANTENNA__0746__B1 gf180mcu_fd_sc_mcu7t5v0__antenna + PLACED ( 511840 188160 ) N ;
+ - ANTENNA__0746__C gf180mcu_fd_sc_mcu7t5v0__antenna + PLACED ( 507360 188160 ) N ;
+ - ANTENNA__0747__A1 gf180mcu_fd_sc_mcu7t5v0__antenna + PLACED ( 517440 203840 ) N ;
+ - ANTENNA__0749__A1 gf180mcu_fd_sc_mcu7t5v0__antenna + PLACED ( 511840 133280 ) S ;
+ - ANTENNA__0750__A1 gf180mcu_fd_sc_mcu7t5v0__antenna + PLACED ( 533120 141120 ) FN ;
+ - ANTENNA__0750__A2 gf180mcu_fd_sc_mcu7t5v0__antenna + PLACED ( 540960 148960 ) FS ;
+ - ANTENNA__0750__A3 gf180mcu_fd_sc_mcu7t5v0__antenna + PLACED ( 536480 148960 ) FS ;
+ - ANTENNA__0751__A1 gf180mcu_fd_sc_mcu7t5v0__antenna + PLACED ( 512960 141120 ) FN ;
+ - ANTENNA__0752__A2 gf180mcu_fd_sc_mcu7t5v0__antenna + PLACED ( 478240 148960 ) FS ;
+ - ANTENNA__0753__A1 gf180mcu_fd_sc_mcu7t5v0__antenna + PLACED ( 505120 141120 ) N ;
+ - ANTENNA__0754__A1 gf180mcu_fd_sc_mcu7t5v0__antenna + PLACED ( 507360 172480 ) FN ;
+ - ANTENNA__0756__A1 gf180mcu_fd_sc_mcu7t5v0__antenna + PLACED ( 548800 156800 ) N ;
+ - ANTENNA__0758__A1 gf180mcu_fd_sc_mcu7t5v0__antenna + PLACED ( 516320 164640 ) FS ;
+ - ANTENNA__0759__A1 gf180mcu_fd_sc_mcu7t5v0__antenna + PLACED ( 537600 164640 ) FS ;
+ - ANTENNA__0760__C gf180mcu_fd_sc_mcu7t5v0__antenna + PLACED ( 526400 172480 ) FN ;
+ - ANTENNA__0761__A1 gf180mcu_fd_sc_mcu7t5v0__antenna + PLACED ( 554400 188160 ) N ;
+ - ANTENNA__0765__A1 gf180mcu_fd_sc_mcu7t5v0__antenna + PLACED ( 502880 172480 ) N ;
+ - ANTENNA__0765__A2 gf180mcu_fd_sc_mcu7t5v0__antenna + PLACED ( 464800 172480 ) FN ;
+ - ANTENNA__0765__B gf180mcu_fd_sc_mcu7t5v0__antenna + PLACED ( 474880 164640 ) S ;
+ - ANTENNA__0766__A1 gf180mcu_fd_sc_mcu7t5v0__antenna + PLACED ( 461440 188160 ) N ;
+ - ANTENNA__0767__B gf180mcu_fd_sc_mcu7t5v0__antenna + PLACED ( 511840 180320 ) FS ;
+ - ANTENNA__0767__C gf180mcu_fd_sc_mcu7t5v0__antenna + PLACED ( 507360 180320 ) FS ;
+ - ANTENNA__0768__A1 gf180mcu_fd_sc_mcu7t5v0__antenna + PLACED ( 511840 196000 ) FS ;
+ - ANTENNA__0768__C gf180mcu_fd_sc_mcu7t5v0__antenna + PLACED ( 507360 196000 ) FS ;
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+ - ANTENNA__1266__A3 gf180mcu_fd_sc_mcu7t5v0__antenna + PLACED ( 417760 454720 ) N ;
+ - ANTENNA__1267__A1 gf180mcu_fd_sc_mcu7t5v0__antenna + PLACED ( 385280 399840 ) FS ;
+ - ANTENNA__1267__C gf180mcu_fd_sc_mcu7t5v0__antenna + PLACED ( 421120 376320 ) N ;
+ - ANTENNA__1268__A1 gf180mcu_fd_sc_mcu7t5v0__antenna + PLACED ( 389760 399840 ) FS ;
+ - ANTENNA__1269__B gf180mcu_fd_sc_mcu7t5v0__antenna + PLACED ( 367360 392000 ) N ;
+ - ANTENNA__1270__A1 gf180mcu_fd_sc_mcu7t5v0__antenna + PLACED ( 398720 399840 ) S ;
+ - ANTENNA__1270__A2 gf180mcu_fd_sc_mcu7t5v0__antenna + PLACED ( 414400 399840 ) FS ;
+ - ANTENNA__1270__B2 gf180mcu_fd_sc_mcu7t5v0__antenna + PLACED ( 414400 384160 ) FS ;
+ - ANTENNA__1270__C gf180mcu_fd_sc_mcu7t5v0__antenna + PLACED ( 407680 399840 ) FS ;
+ - ANTENNA__1271__A1 gf180mcu_fd_sc_mcu7t5v0__antenna + PLACED ( 357280 384160 ) FS ;
+ - ANTENNA__1271__A2 gf180mcu_fd_sc_mcu7t5v0__antenna + PLACED ( 361760 384160 ) FS ;
+ - ANTENNA__1272__A1 gf180mcu_fd_sc_mcu7t5v0__antenna + PLACED ( 408800 360640 ) N ;
+ - ANTENNA__1273__A2 gf180mcu_fd_sc_mcu7t5v0__antenna + PLACED ( 406560 368480 ) FS ;
+ - ANTENNA__1273__A3 gf180mcu_fd_sc_mcu7t5v0__antenna + PLACED ( 414400 368480 ) FS ;
+ - ANTENNA__1274__A1 gf180mcu_fd_sc_mcu7t5v0__antenna + PLACED ( 374080 368480 ) FS ;
+ - ANTENNA__1276__A1 gf180mcu_fd_sc_mcu7t5v0__antenna + PLACED ( 413280 360640 ) FN ;
+ - ANTENNA__1277__A1 gf180mcu_fd_sc_mcu7t5v0__antenna + PLACED ( 405440 337120 ) S ;
+ - ANTENNA__1277__C gf180mcu_fd_sc_mcu7t5v0__antenna + PLACED ( 400960 337120 ) FS ;
+ - ANTENNA__1278__A1 gf180mcu_fd_sc_mcu7t5v0__antenna + PLACED ( 374080 360640 ) FN ;
+ - ANTENNA__1278__A3 gf180mcu_fd_sc_mcu7t5v0__antenna + PLACED ( 374080 344960 ) N ;
+ - ANTENNA__1278__A4 gf180mcu_fd_sc_mcu7t5v0__antenna + PLACED ( 367360 352800 ) FS ;
+ - ANTENNA__1279__A1 gf180mcu_fd_sc_mcu7t5v0__antenna + PLACED ( 387520 337120 ) S ;
+ - ANTENNA__1279__A2 gf180mcu_fd_sc_mcu7t5v0__antenna + PLACED ( 383040 337120 ) S ;
+ - ANTENNA__1281__B2 gf180mcu_fd_sc_mcu7t5v0__antenna + PLACED ( 367360 368480 ) FS ;
+ - ANTENNA__1281__C gf180mcu_fd_sc_mcu7t5v0__antenna + PLACED ( 365120 360640 ) N ;
+ - ANTENNA__1282__A1 gf180mcu_fd_sc_mcu7t5v0__antenna + PLACED ( 352800 392000 ) N ;
+ - ANTENNA__1282__B gf180mcu_fd_sc_mcu7t5v0__antenna + PLACED ( 339360 384160 ) FS ;
+ - ANTENNA__1283__A1 gf180mcu_fd_sc_mcu7t5v0__antenna + PLACED ( 276640 407680 ) N ;
+ - ANTENNA__1283__A2 gf180mcu_fd_sc_mcu7t5v0__antenna + PLACED ( 264320 399840 ) S ;
+ - ANTENNA__1284__A1 gf180mcu_fd_sc_mcu7t5v0__antenna + PLACED ( 305760 407680 ) N ;
+ - ANTENNA__1285__A1 gf180mcu_fd_sc_mcu7t5v0__antenna + PLACED ( 352800 415520 ) FS ;
+ - ANTENNA__1285__A2 gf180mcu_fd_sc_mcu7t5v0__antenna + PLACED ( 336000 399840 ) S ;
+ - ANTENNA__1287__A2 gf180mcu_fd_sc_mcu7t5v0__antenna + PLACED ( 334880 415520 ) FS ;
+ - ANTENNA__1287__A3 gf180mcu_fd_sc_mcu7t5v0__antenna + PLACED ( 314720 415520 ) FS ;
+ - ANTENNA__1288__A1 gf180mcu_fd_sc_mcu7t5v0__antenna + PLACED ( 336000 423360 ) FN ;
+ - ANTENNA__1288__A2 gf180mcu_fd_sc_mcu7t5v0__antenna + PLACED ( 331520 423360 ) N ;
+ - ANTENNA__1294__A2 gf180mcu_fd_sc_mcu7t5v0__antenna + PLACED ( 254240 423360 ) N ;
+ - ANTENNA__1295__A1 gf180mcu_fd_sc_mcu7t5v0__antenna + PLACED ( 422240 454720 ) FN ;
+ - ANTENNA__1295__A2 gf180mcu_fd_sc_mcu7t5v0__antenna + PLACED ( 426720 454720 ) N ;
+ - ANTENNA__1295__A3 gf180mcu_fd_sc_mcu7t5v0__antenna + PLACED ( 434560 454720 ) N ;
+ - ANTENNA__1296__A1 gf180mcu_fd_sc_mcu7t5v0__antenna + PLACED ( 231840 439040 ) N ;
+ - ANTENNA__1296__B gf180mcu_fd_sc_mcu7t5v0__antenna + PLACED ( 255360 431200 ) FS ;
+ - ANTENNA__1297__A2 gf180mcu_fd_sc_mcu7t5v0__antenna + PLACED ( 271040 431200 ) S ;
+ - ANTENNA__1297__A3 gf180mcu_fd_sc_mcu7t5v0__antenna + PLACED ( 262080 431200 ) S ;
+ - ANTENNA__1298__A2 gf180mcu_fd_sc_mcu7t5v0__antenna + PLACED ( 266560 431200 ) S ;
+ - ANTENNA__1299__A1 gf180mcu_fd_sc_mcu7t5v0__antenna + PLACED ( 308000 439040 ) N ;
+ - ANTENNA__1299__A2 gf180mcu_fd_sc_mcu7t5v0__antenna + PLACED ( 275520 446880 ) FS ;
+ - ANTENNA__1300__A1 gf180mcu_fd_sc_mcu7t5v0__antenna + PLACED ( 294560 423360 ) N ;
+ - ANTENNA__1302__A1 gf180mcu_fd_sc_mcu7t5v0__antenna + PLACED ( 287840 439040 ) N ;
+ - ANTENNA__1302__A2 gf180mcu_fd_sc_mcu7t5v0__antenna + PLACED ( 303520 439040 ) N ;
+ - ANTENNA__1303__A1 gf180mcu_fd_sc_mcu7t5v0__antenna + PLACED ( 292320 446880 ) FS ;
+ - ANTENNA__1304__A1 gf180mcu_fd_sc_mcu7t5v0__antenna + PLACED ( 287840 462560 ) FS ;
+ - ANTENNA__1304__C gf180mcu_fd_sc_mcu7t5v0__antenna + PLACED ( 310240 454720 ) N ;
+ - ANTENNA__1305__A1 gf180mcu_fd_sc_mcu7t5v0__antenna + PLACED ( 312480 446880 ) FS ;
+ - ANTENNA__1305__B gf180mcu_fd_sc_mcu7t5v0__antenna + PLACED ( 308000 446880 ) FS ;
+ - ANTENNA__1306__A1 gf180mcu_fd_sc_mcu7t5v0__antenna + PLACED ( 294560 470400 ) N ;
+ - ANTENNA__1306__A2 gf180mcu_fd_sc_mcu7t5v0__antenna + PLACED ( 299040 470400 ) FN ;
+ - ANTENNA__1307__A1 gf180mcu_fd_sc_mcu7t5v0__antenna + PLACED ( 283360 470400 ) FN ;
+ - ANTENNA__1308__A1 gf180mcu_fd_sc_mcu7t5v0__antenna + PLACED ( 269920 462560 ) S ;
+ - ANTENNA__1309__A1 gf180mcu_fd_sc_mcu7t5v0__antenna + PLACED ( 257600 446880 ) FS ;
+ - ANTENNA__1310__A1 gf180mcu_fd_sc_mcu7t5v0__antenna + PLACED ( 232960 407680 ) N ;
+ - ANTENNA__1310__B gf180mcu_fd_sc_mcu7t5v0__antenna + PLACED ( 258720 423360 ) FN ;
+ - ANTENNA__1311__A2 gf180mcu_fd_sc_mcu7t5v0__antenna + PLACED ( 182560 392000 ) N ;
+ - ANTENNA__1312__A2 gf180mcu_fd_sc_mcu7t5v0__antenna + PLACED ( 215040 392000 ) N ;
+ - ANTENNA__1314__A1 gf180mcu_fd_sc_mcu7t5v0__antenna + PLACED ( 200480 423360 ) N ;
+ - ANTENNA__1316__A1 gf180mcu_fd_sc_mcu7t5v0__antenna + PLACED ( 226240 439040 ) N ;
+ - ANTENNA__1316__A2 gf180mcu_fd_sc_mcu7t5v0__antenna + PLACED ( 208320 423360 ) N ;
+ - ANTENNA__1317__A1 gf180mcu_fd_sc_mcu7t5v0__antenna + PLACED ( 201600 439040 ) N ;
+ - ANTENNA__1317__B gf180mcu_fd_sc_mcu7t5v0__antenna + PLACED ( 208320 439040 ) FN ;
+ - ANTENNA__1323__A1 gf180mcu_fd_sc_mcu7t5v0__antenna + PLACED ( 463680 344960 ) N ;
+ - ANTENNA__1323__A2 gf180mcu_fd_sc_mcu7t5v0__antenna + PLACED ( 446880 344960 ) N ;
+ - ANTENNA__1324__A1 gf180mcu_fd_sc_mcu7t5v0__antenna + PLACED ( 169120 352800 ) S ;
+ - ANTENNA__1324__A2 gf180mcu_fd_sc_mcu7t5v0__antenna + PLACED ( 194880 352800 ) S ;
+ - ANTENNA__1325__A1 gf180mcu_fd_sc_mcu7t5v0__antenna + PLACED ( 207200 360640 ) N ;
+ - ANTENNA__1326__A1 gf180mcu_fd_sc_mcu7t5v0__antenna + PLACED ( 224000 360640 ) N ;
+ - ANTENNA__1327__A1 gf180mcu_fd_sc_mcu7t5v0__antenna + PLACED ( 196000 407680 ) FN ;
+ - ANTENNA__1329__A1 gf180mcu_fd_sc_mcu7t5v0__antenna + PLACED ( 187040 415520 ) FS ;
+ - ANTENNA__1329__B gf180mcu_fd_sc_mcu7t5v0__antenna + PLACED ( 178080 392000 ) N ;
+ - ANTENNA__1330__A1 gf180mcu_fd_sc_mcu7t5v0__antenna + PLACED ( 201600 415520 ) FS ;
+ - ANTENNA__1332__A1 gf180mcu_fd_sc_mcu7t5v0__antenna + PLACED ( 208320 407680 ) N ;
+ - ANTENNA__1332__A2 gf180mcu_fd_sc_mcu7t5v0__antenna + PLACED ( 203840 407680 ) FN ;
+ - ANTENNA__1334__A1 gf180mcu_fd_sc_mcu7t5v0__antenna + PLACED ( 231840 399840 ) FS ;
+ - ANTENNA__1335__A2 gf180mcu_fd_sc_mcu7t5v0__antenna + PLACED ( 197120 368480 ) S ;
+ - ANTENNA__1335__A3 gf180mcu_fd_sc_mcu7t5v0__antenna + PLACED ( 207200 376320 ) N ;
+ - ANTENNA__1338__A1 gf180mcu_fd_sc_mcu7t5v0__antenna + PLACED ( 187040 368480 ) FS ;
+ - ANTENNA__1340__A2 gf180mcu_fd_sc_mcu7t5v0__antenna + PLACED ( 267680 352800 ) FS ;
+ - ANTENNA__1340__B gf180mcu_fd_sc_mcu7t5v0__antenna + PLACED ( 287840 352800 ) FS ;
+ - ANTENNA__1341__A2 gf180mcu_fd_sc_mcu7t5v0__antenna + PLACED ( 254240 344960 ) N ;
+ - ANTENNA__1343__A2 gf180mcu_fd_sc_mcu7t5v0__antenna + PLACED ( 255360 352800 ) FS ;
+ - ANTENNA__1344__A3 gf180mcu_fd_sc_mcu7t5v0__antenna + PLACED ( 249760 344960 ) N ;
+ - ANTENNA__1345__A1 gf180mcu_fd_sc_mcu7t5v0__antenna + PLACED ( 255360 321440 ) FS ;
+ - ANTENNA__1347__A1 gf180mcu_fd_sc_mcu7t5v0__antenna + PLACED ( 187040 337120 ) FS ;
+ - ANTENNA__1349__A1 gf180mcu_fd_sc_mcu7t5v0__antenna + PLACED ( 399840 305760 ) FS ;
+ - ANTENNA__1350__A1 gf180mcu_fd_sc_mcu7t5v0__antenna + PLACED ( 411040 329280 ) FN ;
+ - ANTENNA__1352__A1 gf180mcu_fd_sc_mcu7t5v0__antenna + PLACED ( 422240 321440 ) FS ;
+ - ANTENNA__1362__A2 gf180mcu_fd_sc_mcu7t5v0__antenna + PLACED ( 476000 235200 ) FN ;
+ - ANTENNA__1363__I gf180mcu_fd_sc_mcu7t5v0__antenna + PLACED ( 386400 211680 ) S ;
+ - ANTENNA__1364__CLK gf180mcu_fd_sc_mcu7t5v0__antenna + PLACED ( 474880 86240 ) FS ;
+ - ANTENNA__1364__D gf180mcu_fd_sc_mcu7t5v0__antenna + PLACED ( 435680 86240 ) FS ;
+ - ANTENNA__1365__CLK gf180mcu_fd_sc_mcu7t5v0__antenna + PLACED ( 525280 266560 ) N ;
+ - ANTENNA__1366__CLK gf180mcu_fd_sc_mcu7t5v0__antenna + PLACED ( 238560 86240 ) FS ;
+ - ANTENNA__1367__CLK gf180mcu_fd_sc_mcu7t5v0__antenna + PLACED ( 433440 282240 ) N ;
+ - ANTENNA__1368__CLK gf180mcu_fd_sc_mcu7t5v0__antenna + PLACED ( 151200 86240 ) FS ;
+ - ANTENNA__1368__D gf180mcu_fd_sc_mcu7t5v0__antenna + PLACED ( 155680 86240 ) FS ;
+ - ANTENNA__1369__CLK gf180mcu_fd_sc_mcu7t5v0__antenna + PLACED ( 508480 211680 ) FS ;
+ - ANTENNA__1370__CLK gf180mcu_fd_sc_mcu7t5v0__antenna + PLACED ( 526400 203840 ) N ;
+ - ANTENNA__1371__CLK gf180mcu_fd_sc_mcu7t5v0__antenna + PLACED ( 491680 235200 ) FN ;
+ - ANTENNA__1372__CLK gf180mcu_fd_sc_mcu7t5v0__antenna + PLACED ( 189280 297920 ) N ;
+ - ANTENNA__1373__CLK gf180mcu_fd_sc_mcu7t5v0__antenna + PLACED ( 486080 243040 ) FS ;
+ - ANTENNA__1374__CLK gf180mcu_fd_sc_mcu7t5v0__antenna + PLACED ( 493920 258720 ) FS ;
+ - ANTENNA__1375__CLK gf180mcu_fd_sc_mcu7t5v0__antenna + PLACED ( 276640 235200 ) N ;
+ - ANTENNA__1376__CLK gf180mcu_fd_sc_mcu7t5v0__antenna + PLACED ( 253120 219520 ) N ;
+ - ANTENNA__1377__CLK gf180mcu_fd_sc_mcu7t5v0__antenna + PLACED ( 250880 250880 ) N ;
+ - ANTENNA__1378__CLK gf180mcu_fd_sc_mcu7t5v0__antenna + PLACED ( 169120 258720 ) S ;
+ - ANTENNA__1379__CLK gf180mcu_fd_sc_mcu7t5v0__antenna + PLACED ( 143360 250880 ) N ;
+ - ANTENNA__1380__CLK gf180mcu_fd_sc_mcu7t5v0__antenna + PLACED ( 142240 235200 ) N ;
+ - ANTENNA__1381__CLK gf180mcu_fd_sc_mcu7t5v0__antenna + PLACED ( 135520 203840 ) N ;
+ - ANTENNA__1382__CLK gf180mcu_fd_sc_mcu7t5v0__antenna + PLACED ( 154560 188160 ) N ;
+ - ANTENNA__1383__CLK gf180mcu_fd_sc_mcu7t5v0__antenna + PLACED ( 157920 172480 ) N ;
+ - ANTENNA__1384__CLK gf180mcu_fd_sc_mcu7t5v0__antenna + PLACED ( 215040 156800 ) N ;
+ - ANTENNA__1385__CLK gf180mcu_fd_sc_mcu7t5v0__antenna + PLACED ( 124320 141120 ) N ;
+ - ANTENNA__1386__CLK gf180mcu_fd_sc_mcu7t5v0__antenna + PLACED ( 140000 203840 ) N ;
+ - ANTENNA__1387__CLK gf180mcu_fd_sc_mcu7t5v0__antenna + PLACED ( 168000 180320 ) FS ;
+ - ANTENNA__1388__CLK gf180mcu_fd_sc_mcu7t5v0__antenna + PLACED ( 150080 148960 ) FS ;
+ - ANTENNA__1389__CLK gf180mcu_fd_sc_mcu7t5v0__antenna + PLACED ( 110880 156800 ) N ;
+ - ANTENNA__1390__CLK gf180mcu_fd_sc_mcu7t5v0__antenna + PLACED ( 79520 148960 ) FS ;
+ - ANTENNA__1391__CLK gf180mcu_fd_sc_mcu7t5v0__antenna + PLACED ( 49280 172480 ) N ;
+ - ANTENNA__1392__CLK gf180mcu_fd_sc_mcu7t5v0__antenna + PLACED ( 63840 203840 ) N ;
+ - ANTENNA__1393__CLK gf180mcu_fd_sc_mcu7t5v0__antenna + PLACED ( 97440 211680 ) FS ;
+ - ANTENNA__1394__CLK gf180mcu_fd_sc_mcu7t5v0__antenna + PLACED ( 59360 227360 ) FS ;
+ - ANTENNA__1395__CLK gf180mcu_fd_sc_mcu7t5v0__antenna + PLACED ( 49280 250880 ) N ;
+ - ANTENNA__1396__CLK gf180mcu_fd_sc_mcu7t5v0__antenna + PLACED ( 88480 258720 ) S ;
+ - ANTENNA__1397__CLK gf180mcu_fd_sc_mcu7t5v0__antenna + PLACED ( 116480 266560 ) N ;
+ - ANTENNA__1398__CLK gf180mcu_fd_sc_mcu7t5v0__antenna + PLACED ( 151200 258720 ) FS ;
+ - ANTENNA__1399__CLK gf180mcu_fd_sc_mcu7t5v0__antenna + PLACED ( 120960 266560 ) N ;
+ - ANTENNA__1400__CLK gf180mcu_fd_sc_mcu7t5v0__antenna + PLACED ( 123200 305760 ) FS ;
+ - ANTENNA__1401__CLK gf180mcu_fd_sc_mcu7t5v0__antenna + PLACED ( 117600 282240 ) N ;
+ - ANTENNA__1402__CLK gf180mcu_fd_sc_mcu7t5v0__antenna + PLACED ( 170240 329280 ) N ;
+ - ANTENNA__1403__CLK gf180mcu_fd_sc_mcu7t5v0__antenna + PLACED ( 156800 352800 ) FS ;
+ - ANTENNA__1404__CLK gf180mcu_fd_sc_mcu7t5v0__antenna + PLACED ( 124320 360640 ) N ;
+ - ANTENNA__1405__CLK gf180mcu_fd_sc_mcu7t5v0__antenna + PLACED ( 96320 368480 ) FS ;
+ - ANTENNA__1406__CLK gf180mcu_fd_sc_mcu7t5v0__antenna + PLACED ( 57120 376320 ) N ;
+ - ANTENNA__1407__CLK gf180mcu_fd_sc_mcu7t5v0__antenna + PLACED ( 54880 337120 ) FS ;
+ - ANTENNA__1408__CLK gf180mcu_fd_sc_mcu7t5v0__antenna + PLACED ( 51520 321440 ) S ;
+ - ANTENNA__1409__CLK gf180mcu_fd_sc_mcu7t5v0__antenna + PLACED ( 56000 297920 ) N ;
+ - ANTENNA__1410__CLK gf180mcu_fd_sc_mcu7t5v0__antenna + PLACED ( 75040 274400 ) FS ;
+ - ANTENNA__1411__CLK gf180mcu_fd_sc_mcu7t5v0__antenna + PLACED ( 324800 243040 ) FS ;
+ - ANTENNA__1412__CLK gf180mcu_fd_sc_mcu7t5v0__antenna + PLACED ( 325920 211680 ) FS ;
+ - ANTENNA__1413__CLK gf180mcu_fd_sc_mcu7t5v0__antenna + PLACED ( 316960 274400 ) FS ;
+ - ANTENNA__1414__CLK gf180mcu_fd_sc_mcu7t5v0__antenna + PLACED ( 293440 227360 ) FS ;
+ - ANTENNA__1415__CLK gf180mcu_fd_sc_mcu7t5v0__antenna + PLACED ( 284480 258720 ) S ;
+ - ANTENNA__1416__CLK gf180mcu_fd_sc_mcu7t5v0__antenna + PLACED ( 374080 250880 ) N ;
+ - ANTENNA__1417__CLK gf180mcu_fd_sc_mcu7t5v0__antenna + PLACED ( 232960 297920 ) N ;
+ - ANTENNA__1418__CLK gf180mcu_fd_sc_mcu7t5v0__antenna + PLACED ( 255360 274400 ) FS ;
+ - ANTENNA__1419__CLK gf180mcu_fd_sc_mcu7t5v0__antenna + PLACED ( 255360 258720 ) S ;
+ - ANTENNA__1420__CLK gf180mcu_fd_sc_mcu7t5v0__antenna + PLACED ( 255360 290080 ) FS ;
+ - ANTENNA__1421__CLK gf180mcu_fd_sc_mcu7t5v0__antenna + PLACED ( 367360 94080 ) N ;
+ - ANTENNA__1422__CLK gf180mcu_fd_sc_mcu7t5v0__antenna + PLACED ( 374080 78400 ) FN ;
+ - ANTENNA__1423__CLK gf180mcu_fd_sc_mcu7t5v0__antenna + PLACED ( 374080 109760 ) N ;
+ - ANTENNA__1424__CLK gf180mcu_fd_sc_mcu7t5v0__antenna + PLACED ( 406560 101920 ) FS ;
+ - ANTENNA__1425__CLK gf180mcu_fd_sc_mcu7t5v0__antenna + PLACED ( 396480 117600 ) FS ;
+ - ANTENNA__1426__CLK gf180mcu_fd_sc_mcu7t5v0__antenna + PLACED ( 383040 125440 ) N ;
+ - ANTENNA__1427__CLK gf180mcu_fd_sc_mcu7t5v0__antenna + PLACED ( 374080 141120 ) N ;
+ - ANTENNA__1428__CLK gf180mcu_fd_sc_mcu7t5v0__antenna + PLACED ( 374080 172480 ) N ;
+ - ANTENNA__1429__CLK gf180mcu_fd_sc_mcu7t5v0__antenna + PLACED ( 369600 196000 ) FS ;
+ - ANTENNA__1430__CLK gf180mcu_fd_sc_mcu7t5v0__antenna + PLACED ( 376320 180320 ) FS ;
+ - ANTENNA__1431__CLK gf180mcu_fd_sc_mcu7t5v0__antenna + PLACED ( 269920 164640 ) S ;
+ - ANTENNA__1432__CLK gf180mcu_fd_sc_mcu7t5v0__antenna + PLACED ( 253120 78400 ) FN ;
+ - ANTENNA__1433__CLK gf180mcu_fd_sc_mcu7t5v0__antenna + PLACED ( 248640 86240 ) FS ;
+ - ANTENNA__1434__CLK gf180mcu_fd_sc_mcu7t5v0__antenna + PLACED ( 294560 78400 ) FN ;
+ - ANTENNA__1435__CLK gf180mcu_fd_sc_mcu7t5v0__antenna + PLACED ( 255360 117600 ) FS ;
+ - ANTENNA__1436__CLK gf180mcu_fd_sc_mcu7t5v0__antenna + PLACED ( 241920 101920 ) FS ;
+ - ANTENNA__1437__CLK gf180mcu_fd_sc_mcu7t5v0__antenna + PLACED ( 218400 125440 ) N ;
+ - ANTENNA__1438__CLK gf180mcu_fd_sc_mcu7t5v0__antenna + PLACED ( 256480 164640 ) S ;
+ - ANTENNA__1439__CLK gf180mcu_fd_sc_mcu7t5v0__antenna + PLACED ( 259840 196000 ) FS ;
+ - ANTENNA__1440__CLK gf180mcu_fd_sc_mcu7t5v0__antenna + PLACED ( 286720 188160 ) FN ;
+ - ANTENNA__1441__CLK gf180mcu_fd_sc_mcu7t5v0__antenna + PLACED ( 516320 282240 ) N ;
+ - ANTENNA__1441__D gf180mcu_fd_sc_mcu7t5v0__antenna + PLACED ( 518560 297920 ) FN ;
+ - ANTENNA__1442__CLK gf180mcu_fd_sc_mcu7t5v0__antenna + PLACED ( 394240 525280 ) S ;
+ - ANTENNA__1443__CLK gf180mcu_fd_sc_mcu7t5v0__antenna + PLACED ( 449120 493920 ) FS ;
+ - ANTENNA__1444__CLK gf180mcu_fd_sc_mcu7t5v0__antenna + PLACED ( 378560 517440 ) N ;
+ - ANTENNA__1445__CLK gf180mcu_fd_sc_mcu7t5v0__antenna + PLACED ( 374080 501760 ) N ;
+ - ANTENNA__1446__CLK gf180mcu_fd_sc_mcu7t5v0__antenna + PLACED ( 341600 478240 ) FS ;
+ - ANTENNA__1447__CLK gf180mcu_fd_sc_mcu7t5v0__antenna + PLACED ( 418880 399840 ) FS ;
+ - ANTENNA__1448__CLK gf180mcu_fd_sc_mcu7t5v0__antenna + PLACED ( 443520 407680 ) FN ;
+ - ANTENNA__1449__CLK gf180mcu_fd_sc_mcu7t5v0__antenna + PLACED ( 458080 446880 ) FS ;
+ - ANTENNA__1450__CLK gf180mcu_fd_sc_mcu7t5v0__antenna + PLACED ( 380800 431200 ) FS ;
+ - ANTENNA__1451__CLK gf180mcu_fd_sc_mcu7t5v0__antenna + PLACED ( 349440 446880 ) FS ;
+ - ANTENNA__1452__CLK gf180mcu_fd_sc_mcu7t5v0__antenna + PLACED ( 484960 509600 ) FS ;
+ - ANTENNA__1453__CLK gf180mcu_fd_sc_mcu7t5v0__antenna + PLACED ( 467040 478240 ) FS ;
+ - ANTENNA__1454__CLK gf180mcu_fd_sc_mcu7t5v0__antenna + PLACED ( 508480 517440 ) N ;
+ - ANTENNA__1455__CLK gf180mcu_fd_sc_mcu7t5v0__antenna + PLACED ( 505120 509600 ) FS ;
+ - ANTENNA__1456__CLK gf180mcu_fd_sc_mcu7t5v0__antenna + PLACED ( 530880 493920 ) FS ;
+ - ANTENNA__1457__CLK gf180mcu_fd_sc_mcu7t5v0__antenna + PLACED ( 473760 439040 ) N ;
+ - ANTENNA__1458__CLK gf180mcu_fd_sc_mcu7t5v0__antenna + PLACED ( 480480 415520 ) FS ;
+ - ANTENNA__1459__CLK gf180mcu_fd_sc_mcu7t5v0__antenna + PLACED ( 495040 415520 ) FS ;
+ - ANTENNA__1460__CLK gf180mcu_fd_sc_mcu7t5v0__antenna + PLACED ( 519680 431200 ) FS ;
+ - ANTENNA__1461__CLK gf180mcu_fd_sc_mcu7t5v0__antenna + PLACED ( 520800 462560 ) FS ;
+ - ANTENNA__1462__CLK gf180mcu_fd_sc_mcu7t5v0__antenna + PLACED ( 407680 274400 ) FS ;
+ - ANTENNA__1462__D gf180mcu_fd_sc_mcu7t5v0__antenna + PLACED ( 403200 274400 ) FS ;
+ - ANTENNA__1463__CLK gf180mcu_fd_sc_mcu7t5v0__antenna + PLACED ( 404320 258720 ) FS ;
+ - ANTENNA__1464__CLK gf180mcu_fd_sc_mcu7t5v0__antenna + PLACED ( 421120 196000 ) FS ;
+ - ANTENNA__1465__CLK gf180mcu_fd_sc_mcu7t5v0__antenna + PLACED ( 414400 227360 ) FS ;
+ - ANTENNA__1466__CLK gf180mcu_fd_sc_mcu7t5v0__antenna + PLACED ( 423360 250880 ) N ;
+ - ANTENNA__1467__CLK gf180mcu_fd_sc_mcu7t5v0__antenna + PLACED ( 471520 290080 ) S ;
+ - ANTENNA__1468__CLK gf180mcu_fd_sc_mcu7t5v0__antenna + PLACED ( 459200 329280 ) N ;
+ - ANTENNA__1469__CLK gf180mcu_fd_sc_mcu7t5v0__antenna + PLACED ( 510720 282240 ) N ;
+ - ANTENNA__1470__CLK gf180mcu_fd_sc_mcu7t5v0__antenna + PLACED ( 517440 313600 ) FN ;
+ - ANTENNA__1471__CLK gf180mcu_fd_sc_mcu7t5v0__antenna + PLACED ( 524160 344960 ) N ;
+ - ANTENNA__1472__CLK gf180mcu_fd_sc_mcu7t5v0__antenna + PLACED ( 423360 360640 ) N ;
+ - ANTENNA__1473__CLK gf180mcu_fd_sc_mcu7t5v0__antenna + PLACED ( 505120 407680 ) N ;
+ - ANTENNA__1474__CLK gf180mcu_fd_sc_mcu7t5v0__antenna + PLACED ( 474880 392000 ) N ;
+ - ANTENNA__1475__CLK gf180mcu_fd_sc_mcu7t5v0__antenna + PLACED ( 521920 376320 ) N ;
+ - ANTENNA__1476__CLK gf180mcu_fd_sc_mcu7t5v0__antenna + PLACED ( 530880 352800 ) FS ;
+ - ANTENNA__1477__CLK gf180mcu_fd_sc_mcu7t5v0__antenna + PLACED ( 403200 399840 ) FS ;
+ - ANTENNA__1478__CLK gf180mcu_fd_sc_mcu7t5v0__antenna + PLACED ( 374080 376320 ) N ;
+ - ANTENNA__1479__CLK gf180mcu_fd_sc_mcu7t5v0__antenna + PLACED ( 440160 344960 ) N ;
+ - ANTENNA__1480__CLK gf180mcu_fd_sc_mcu7t5v0__antenna + PLACED ( 369600 337120 ) FS ;
+ - ANTENNA__1481__CLK gf180mcu_fd_sc_mcu7t5v0__antenna + PLACED ( 394240 399840 ) FS ;
+ - ANTENNA__1482__CLK gf180mcu_fd_sc_mcu7t5v0__antenna + PLACED ( 330400 439040 ) N ;
+ - ANTENNA__1483__CLK gf180mcu_fd_sc_mcu7t5v0__antenna + PLACED ( 327040 384160 ) FS ;
+ - ANTENNA__1484__CLK gf180mcu_fd_sc_mcu7t5v0__antenna + PLACED ( 255360 407680 ) N ;
+ - ANTENNA__1485__CLK gf180mcu_fd_sc_mcu7t5v0__antenna + PLACED ( 327040 462560 ) FS ;
+ - ANTENNA__1486__CLK gf180mcu_fd_sc_mcu7t5v0__antenna + PLACED ( 259840 478240 ) S ;
+ - ANTENNA__1487__CLK gf180mcu_fd_sc_mcu7t5v0__antenna + PLACED ( 236320 446880 ) FS ;
+ - ANTENNA__1488__CLK gf180mcu_fd_sc_mcu7t5v0__antenna + PLACED ( 199360 446880 ) FS ;
+ - ANTENNA__1489__CLK gf180mcu_fd_sc_mcu7t5v0__antenna + PLACED ( 249760 454720 ) N ;
+ - ANTENNA__1490__CLK gf180mcu_fd_sc_mcu7t5v0__antenna + PLACED ( 250880 407680 ) N ;
+ - ANTENNA__1491__CLK gf180mcu_fd_sc_mcu7t5v0__antenna + PLACED ( 234080 360640 ) N ;
+ - ANTENNA__1492__CLK gf180mcu_fd_sc_mcu7t5v0__antenna + PLACED ( 141120 407680 ) N ;
+ - ANTENNA__1493__CLK gf180mcu_fd_sc_mcu7t5v0__antenna + PLACED ( 255360 399840 ) FS ;
+ - ANTENNA__1494__CLK gf180mcu_fd_sc_mcu7t5v0__antenna + PLACED ( 144480 376320 ) N ;
+ - ANTENNA__1495__CLK gf180mcu_fd_sc_mcu7t5v0__antenna + PLACED ( 248640 337120 ) FS ;
+ - ANTENNA__1496__CLK gf180mcu_fd_sc_mcu7t5v0__antenna + PLACED ( 247520 352800 ) S ;
+ - ANTENNA__1497__CLK gf180mcu_fd_sc_mcu7t5v0__antenna + PLACED ( 190400 352800 ) FS ;
+ - ANTENNA__1498__CLK gf180mcu_fd_sc_mcu7t5v0__antenna + PLACED ( 514080 258720 ) FS ;
+ - ANTENNA__1499__CLK gf180mcu_fd_sc_mcu7t5v0__antenna + PLACED ( 499520 243040 ) FS ;
+ - ANTENNA__1500__CLK gf180mcu_fd_sc_mcu7t5v0__antenna + PLACED ( 488320 109760 ) N ;
+ - ANTENNA__1501__CLK gf180mcu_fd_sc_mcu7t5v0__antenna + PLACED ( 407680 117600 ) FS ;
+ - ANTENNA__1502__CLK gf180mcu_fd_sc_mcu7t5v0__antenna + PLACED ( 476000 133280 ) FS ;
+ - ANTENNA__1503__CLK gf180mcu_fd_sc_mcu7t5v0__antenna + PLACED ( 471520 196000 ) FS ;
+ - ANTENNA__1504__CLK gf180mcu_fd_sc_mcu7t5v0__antenna + PLACED ( 407680 243040 ) FS ;
+ - ANTENNA__1505__CLK gf180mcu_fd_sc_mcu7t5v0__antenna + PLACED ( 480480 219520 ) N ;
+ - ANTENNA__1506__CLK gf180mcu_fd_sc_mcu7t5v0__antenna + PLACED ( 484960 274400 ) FS ;
+ - ANTENNA__1506__D gf180mcu_fd_sc_mcu7t5v0__antenna + PLACED ( 453600 282240 ) FN ;
+ - ANTENNA__1507__CLK gf180mcu_fd_sc_mcu7t5v0__antenna + PLACED ( 455840 258720 ) FS ;
+ - ANTENNA__1507__D gf180mcu_fd_sc_mcu7t5v0__antenna + PLACED ( 418880 250880 ) FN ;
+ - ANTENNA__1508__CLK gf180mcu_fd_sc_mcu7t5v0__antenna + PLACED ( 334880 321440 ) FS ;
+ - ANTENNA__1509__CLK gf180mcu_fd_sc_mcu7t5v0__antenna + PLACED ( 190400 305760 ) FS ;
+ - ANTENNA__1509__D gf180mcu_fd_sc_mcu7t5v0__antenna + PLACED ( 188160 321440 ) FS ;
+ - ANTENNA__1510__CLK gf180mcu_fd_sc_mcu7t5v0__antenna + PLACED ( 245280 305760 ) FS ;
+ - ANTENNA__1510__D gf180mcu_fd_sc_mcu7t5v0__antenna + PLACED ( 273280 313600 ) FN ;
+ - ANTENNA__1511__CLK gf180mcu_fd_sc_mcu7t5v0__antenna + PLACED ( 493920 243040 ) FS ;
+ - ANTENNA__1511__D gf180mcu_fd_sc_mcu7t5v0__antenna + PLACED ( 451360 243040 ) S ;
+ - ANTENNA__1512__CLK gf180mcu_fd_sc_mcu7t5v0__antenna + PLACED ( 416640 297920 ) N ;
+ - ANTENNA__1513__CLK gf180mcu_fd_sc_mcu7t5v0__antenna + PLACED ( 436800 313600 ) FN ;
+ - ANTENNA__1514__CLK gf180mcu_fd_sc_mcu7t5v0__antenna + PLACED ( 390880 211680 ) S ;
+ - ANTENNA_clkbuf_0_wb_clk_i_I gf180mcu_fd_sc_mcu7t5v0__antenna + PLACED ( 287840 297920 ) FN ;
+ - ANTENNA_clkbuf_4_0_0_wb_clk_i_I gf180mcu_fd_sc_mcu7t5v0__antenna + PLACED ( 156800 164640 ) FS ;
+ - ANTENNA_clkbuf_4_10_0_wb_clk_i_I gf180mcu_fd_sc_mcu7t5v0__antenna + PLACED ( 459200 203840 ) N ;
+ - ANTENNA_clkbuf_4_11_0_wb_clk_i_I gf180mcu_fd_sc_mcu7t5v0__antenna + PLACED ( 464800 266560 ) N ;
+ - ANTENNA_clkbuf_4_12_0_wb_clk_i_I gf180mcu_fd_sc_mcu7t5v0__antenna + PLACED ( 362880 392000 ) N ;
+ - ANTENNA_clkbuf_4_13_0_wb_clk_i_I gf180mcu_fd_sc_mcu7t5v0__antenna + PLACED ( 376320 415520 ) FS ;
+ - ANTENNA_clkbuf_4_14_0_wb_clk_i_I gf180mcu_fd_sc_mcu7t5v0__antenna + PLACED ( 470400 392000 ) N ;
+ - ANTENNA_clkbuf_4_15_0_wb_clk_i_I gf180mcu_fd_sc_mcu7t5v0__antenna + PLACED ( 442400 423360 ) N ;
+ - ANTENNA_clkbuf_4_1_0_wb_clk_i_I gf180mcu_fd_sc_mcu7t5v0__antenna + PLACED ( 154560 196000 ) FS ;
+ - ANTENNA_clkbuf_4_2_0_wb_clk_i_I gf180mcu_fd_sc_mcu7t5v0__antenna + PLACED ( 250880 141120 ) FN ;
+ - ANTENNA_clkbuf_4_3_0_wb_clk_i_I gf180mcu_fd_sc_mcu7t5v0__antenna + PLACED ( 265440 203840 ) N ;
+ - ANTENNA_clkbuf_4_4_0_wb_clk_i_I gf180mcu_fd_sc_mcu7t5v0__antenna + PLACED ( 146720 321440 ) FS ;
+ - ANTENNA_clkbuf_4_5_0_wb_clk_i_I gf180mcu_fd_sc_mcu7t5v0__antenna + PLACED ( 150080 337120 ) FS ;
+ - ANTENNA_clkbuf_4_6_0_wb_clk_i_I gf180mcu_fd_sc_mcu7t5v0__antenna + PLACED ( 248640 329280 ) N ;
+ - ANTENNA_clkbuf_4_7_0_wb_clk_i_I gf180mcu_fd_sc_mcu7t5v0__antenna + PLACED ( 239680 368480 ) FS ;
+ - ANTENNA_clkbuf_4_8_0_wb_clk_i_I gf180mcu_fd_sc_mcu7t5v0__antenna + PLACED ( 379680 203840 ) N ;
+ - ANTENNA_clkbuf_4_9_0_wb_clk_i_I gf180mcu_fd_sc_mcu7t5v0__antenna + PLACED ( 388640 266560 ) N ;
+ - ANTENNA_input1_I gf180mcu_fd_sc_mcu7t5v0__antenna + PLACED ( 571200 141120 ) FN ;
+ - ANTENNA_input2_I gf180mcu_fd_sc_mcu7t5v0__antenna + PLACED ( 346080 556640 ) S ;
+ - ANTENNA_input3_I gf180mcu_fd_sc_mcu7t5v0__antenna + PLACED ( 386400 556640 ) S ;
+ - ANTENNA_input4_I gf180mcu_fd_sc_mcu7t5v0__antenna + PLACED ( 580160 297920 ) FN ;
+ - ANTENNA_output11_I gf180mcu_fd_sc_mcu7t5v0__antenna + PLACED ( 580160 462560 ) FS ;
+ - ANTENNA_output5_I gf180mcu_fd_sc_mcu7t5v0__antenna + PLACED ( 34720 439040 ) N ;
+ - ANTENNA_output6_I gf180mcu_fd_sc_mcu7t5v0__antenna + PLACED ( 562240 94080 ) FN ;
+ - FILLER_0_101 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 126560 31360 ) N ;
+ - FILLER_0_107 gf180mcu_fd_sc_mcu7t5v0__fillcap_32 + SOURCE DIST + PLACED ( 133280 31360 ) N ;
+ - FILLER_0_139 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 169120 31360 ) N ;
+ - FILLER_0_142 gf180mcu_fd_sc_mcu7t5v0__fillcap_8 + SOURCE DIST + PLACED ( 172480 31360 ) N ;
+ - FILLER_0_150 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 181440 31360 ) N ;
+ - FILLER_0_155 gf180mcu_fd_sc_mcu7t5v0__fillcap_16 + SOURCE DIST + PLACED ( 187040 31360 ) N ;
+ - FILLER_0_17 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 32480 31360 ) N ;
+ - FILLER_0_171 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 204960 31360 ) N ;
+ - FILLER_0_177 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 211680 31360 ) N ;
+ - FILLER_0_182 gf180mcu_fd_sc_mcu7t5v0__fillcap_16 + SOURCE DIST + PLACED ( 217280 31360 ) N ;
+ - FILLER_0_198 gf180mcu_fd_sc_mcu7t5v0__fillcap_8 + SOURCE DIST + PLACED ( 235200 31360 ) N ;
+ - FILLER_0_2 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 15680 31360 ) N ;
+ - FILLER_0_206 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 244160 31360 ) N ;
+ - FILLER_0_212 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 250880 31360 ) N ;
+ - FILLER_0_217 gf180mcu_fd_sc_mcu7t5v0__fillcap_8 + SOURCE DIST + PLACED ( 256480 31360 ) N ;
+ - FILLER_0_225 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 265440 31360 ) N ;
+ - FILLER_0_23 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 39200 31360 ) N ;
+ - FILLER_0_233 gf180mcu_fd_sc_mcu7t5v0__fillcap_8 + SOURCE DIST + PLACED ( 274400 31360 ) N ;
+ - FILLER_0_241 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 283360 31360 ) N ;
+ - FILLER_0_247 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 290080 31360 ) N ;
+ - FILLER_0_252 gf180mcu_fd_sc_mcu7t5v0__fillcap_8 + SOURCE DIST + PLACED ( 295680 31360 ) N ;
+ - FILLER_0_260 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 304640 31360 ) N ;
+ - FILLER_0_264 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 309120 31360 ) N ;
+ - FILLER_0_279 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 325920 31360 ) N ;
+ - FILLER_0_282 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 329280 31360 ) N ;
+ - FILLER_0_287 gf180mcu_fd_sc_mcu7t5v0__fillcap_8 + SOURCE DIST + PLACED ( 334880 31360 ) N ;
+ - FILLER_0_29 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 45920 31360 ) N ;
+ - FILLER_0_295 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 343840 31360 ) N ;
+ - FILLER_0_299 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 348320 31360 ) N ;
+ - FILLER_0_305 gf180mcu_fd_sc_mcu7t5v0__fillcap_8 + SOURCE DIST + PLACED ( 355040 31360 ) N ;
+ - FILLER_0_313 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 364000 31360 ) N ;
+ - FILLER_0_317 gf180mcu_fd_sc_mcu7t5v0__fillcap_16 + SOURCE DIST + PLACED ( 368480 31360 ) N ;
+ - FILLER_0_33 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 50400 31360 ) N ;
+ - FILLER_0_333 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 386400 31360 ) N ;
+ - FILLER_0_341 gf180mcu_fd_sc_mcu7t5v0__fillcap_8 + SOURCE DIST + PLACED ( 395360 31360 ) N ;
+ - FILLER_0_349 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 404320 31360 ) N ;
+ - FILLER_0_352 gf180mcu_fd_sc_mcu7t5v0__fillcap_8 + SOURCE DIST + PLACED ( 407680 31360 ) N ;
+ - FILLER_0_360 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 416640 31360 ) N ;
+ - FILLER_0_365 gf180mcu_fd_sc_mcu7t5v0__fillcap_8 + SOURCE DIST + PLACED ( 422240 31360 ) N ;
+ - FILLER_0_37 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 54880 31360 ) N ;
+ - FILLER_0_373 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 431200 31360 ) N ;
+ - FILLER_0_377 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 435680 31360 ) N ;
+ - FILLER_0_383 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 442400 31360 ) N ;
+ - FILLER_0_387 gf180mcu_fd_sc_mcu7t5v0__fillcap_8 + SOURCE DIST + PLACED ( 446880 31360 ) N ;
+ - FILLER_0_395 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 455840 31360 ) N ;
+ - FILLER_0_401 gf180mcu_fd_sc_mcu7t5v0__fillcap_8 + SOURCE DIST + PLACED ( 462560 31360 ) N ;
+ - FILLER_0_409 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 471520 31360 ) N ;
+ - FILLER_0_41 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 59360 31360 ) N ;
+ - FILLER_0_413 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 476000 31360 ) N ;
+ - FILLER_0_419 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 482720 31360 ) N ;
+ - FILLER_0_422 gf180mcu_fd_sc_mcu7t5v0__fillcap_8 + SOURCE DIST + PLACED ( 486080 31360 ) N ;
+ - FILLER_0_430 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 495040 31360 ) N ;
+ - FILLER_0_432 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 497280 31360 ) N ;
+ - FILLER_0_437 gf180mcu_fd_sc_mcu7t5v0__fillcap_16 + SOURCE DIST + PLACED ( 502880 31360 ) N ;
+ - FILLER_0_453 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 520800 31360 ) N ;
+ - FILLER_0_457 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 525280 31360 ) N ;
+ - FILLER_0_47 gf180mcu_fd_sc_mcu7t5v0__fillcap_8 + SOURCE DIST + PLACED ( 66080 31360 ) N ;
+ - FILLER_0_472 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 542080 31360 ) N ;
+ - FILLER_0_478 gf180mcu_fd_sc_mcu7t5v0__fillcap_8 + SOURCE DIST + PLACED ( 548800 31360 ) N ;
+ - FILLER_0_486 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 557760 31360 ) N ;
+ - FILLER_0_492 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 564480 31360 ) N ;
+ - FILLER_0_497 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 570080 31360 ) N ;
+ - FILLER_0_501 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 574560 31360 ) N ;
+ - FILLER_0_503 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 576800 31360 ) N ;
+ - FILLER_0_508 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 582400 31360 ) N ;
+ - FILLER_0_55 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 75040 31360 ) N ;
+ - FILLER_0_59 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 79520 31360 ) N ;
+ - FILLER_0_65 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 86240 31360 ) N ;
+ - FILLER_0_69 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 90720 31360 ) N ;
+ - FILLER_0_72 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 94080 31360 ) N ;
+ - FILLER_0_76 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 98560 31360 ) N ;
+ - FILLER_0_78 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 100800 31360 ) N ;
+ - FILLER_0_83 gf180mcu_fd_sc_mcu7t5v0__fillcap_8 + SOURCE DIST + PLACED ( 106400 31360 ) N ;
+ - FILLER_0_91 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 115360 31360 ) N ;
+ - FILLER_0_95 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 119840 31360 ) N ;
+ - FILLER_10_101 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 126560 109760 ) N ;
+ - FILLER_10_105 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 131040 109760 ) N ;
+ - FILLER_10_108 gf180mcu_fd_sc_mcu7t5v0__fillcap_64 + SOURCE DIST + PLACED ( 134400 109760 ) N ;
+ - FILLER_10_172 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 206080 109760 ) N ;
+ - FILLER_10_176 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 210560 109760 ) N ;
+ - FILLER_10_179 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 213920 109760 ) N ;
+ - FILLER_10_182 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 217280 109760 ) N ;
+ - FILLER_10_190 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 226240 109760 ) N ;
+ - FILLER_10_194 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 230720 109760 ) N ;
+ - FILLER_10_197 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 234080 109760 ) N ;
+ - FILLER_10_2 gf180mcu_fd_sc_mcu7t5v0__fillcap_32 + SOURCE DIST + PLACED ( 15680 109760 ) N ;
+ - FILLER_10_201 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 238560 109760 ) N ;
+ - FILLER_10_205 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 243040 109760 ) N ;
+ - FILLER_10_207 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 245280 109760 ) N ;
+ - FILLER_10_217 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 256480 109760 ) N ;
+ - FILLER_10_221 gf180mcu_fd_sc_mcu7t5v0__fillcap_8 + SOURCE DIST + PLACED ( 260960 109760 ) N ;
+ - FILLER_10_229 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 269920 109760 ) N ;
+ - FILLER_10_233 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 274400 109760 ) N ;
+ - FILLER_10_235 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 276640 109760 ) N ;
+ - FILLER_10_238 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 280000 109760 ) N ;
+ - FILLER_10_242 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 284480 109760 ) N ;
+ - FILLER_10_246 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 288960 109760 ) N ;
+ - FILLER_10_250 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 293440 109760 ) N ;
+ - FILLER_10_258 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 302400 109760 ) N ;
+ - FILLER_10_271 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 316960 109760 ) N ;
+ - FILLER_10_278 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 324800 109760 ) N ;
+ - FILLER_10_280 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 327040 109760 ) N ;
+ - FILLER_10_287 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 334880 109760 ) N ;
+ - FILLER_10_318 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 369600 109760 ) N ;
+ - FILLER_10_321 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 372960 109760 ) N ;
+ - FILLER_10_324 gf180mcu_fd_sc_mcu7t5v0__fillcap_16 + SOURCE DIST + PLACED ( 376320 109760 ) N ;
+ - FILLER_10_34 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 51520 109760 ) N ;
+ - FILLER_10_340 gf180mcu_fd_sc_mcu7t5v0__fillcap_8 + SOURCE DIST + PLACED ( 394240 109760 ) N ;
+ - FILLER_10_348 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 403200 109760 ) N ;
+ - FILLER_10_350 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 405440 109760 ) N ;
+ - FILLER_10_364 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 421120 109760 ) N ;
+ - FILLER_10_368 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 425600 109760 ) N ;
+ - FILLER_10_37 gf180mcu_fd_sc_mcu7t5v0__fillcap_64 + SOURCE DIST + PLACED ( 54880 109760 ) N ;
+ - FILLER_10_375 gf180mcu_fd_sc_mcu7t5v0__fillcap_8 + SOURCE DIST + PLACED ( 433440 109760 ) N ;
+ - FILLER_10_383 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 442400 109760 ) N ;
+ - FILLER_10_387 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 446880 109760 ) N ;
+ - FILLER_10_389 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 449120 109760 ) N ;
+ - FILLER_10_392 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 452480 109760 ) N ;
+ - FILLER_10_422 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 486080 109760 ) N ;
+ - FILLER_10_426 gf180mcu_fd_sc_mcu7t5v0__fillcap_32 + SOURCE DIST + PLACED ( 490560 109760 ) N ;
+ - FILLER_10_458 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 526400 109760 ) N ;
+ - FILLER_10_460 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 528640 109760 ) N ;
+ - FILLER_10_463 gf180mcu_fd_sc_mcu7t5v0__fillcap_32 + SOURCE DIST + PLACED ( 532000 109760 ) N ;
+ - FILLER_10_495 gf180mcu_fd_sc_mcu7t5v0__fillcap_8 + SOURCE DIST + PLACED ( 567840 109760 ) N ;
+ - FILLER_10_503 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 576800 109760 ) N ;
+ - FILLER_10_507 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 581280 109760 ) N ;
+ - FILLER_11_137 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 166880 117600 ) FS ;
+ - FILLER_11_141 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 171360 117600 ) FS ;
+ - FILLER_11_144 gf180mcu_fd_sc_mcu7t5v0__fillcap_16 + SOURCE DIST + PLACED ( 174720 117600 ) FS ;
+ - FILLER_11_160 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 192640 117600 ) FS ;
+ - FILLER_11_164 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 197120 117600 ) FS ;
+ - FILLER_11_166 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 199360 117600 ) FS ;
+ - FILLER_11_196 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 232960 117600 ) FS ;
+ - FILLER_11_2 gf180mcu_fd_sc_mcu7t5v0__fillcap_64 + SOURCE DIST + PLACED ( 15680 117600 ) FS ;
+ - FILLER_11_207 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 245280 117600 ) FS ;
+ - FILLER_11_211 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 249760 117600 ) FS ;
+ - FILLER_11_215 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 254240 117600 ) FS ;
+ - FILLER_11_218 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 257600 117600 ) FS ;
+ - FILLER_11_222 gf180mcu_fd_sc_mcu7t5v0__fillcap_8 + SOURCE DIST + PLACED ( 262080 117600 ) FS ;
+ - FILLER_11_230 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 271040 117600 ) FS ;
+ - FILLER_11_234 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 275520 117600 ) FS ;
+ - FILLER_11_237 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 278880 117600 ) FS ;
+ - FILLER_11_251 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 294560 117600 ) FS ;
+ - FILLER_11_257 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 301280 117600 ) FS ;
+ - FILLER_11_261 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 305760 117600 ) FS ;
+ - FILLER_11_267 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 312480 117600 ) FS ;
+ - FILLER_11_274 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 320320 117600 ) FS ;
+ - FILLER_11_278 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 324800 117600 ) FS ;
+ - FILLER_11_282 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 329280 117600 ) FS ;
+ - FILLER_11_286 gf180mcu_fd_sc_mcu7t5v0__fillcap_16 + SOURCE DIST + PLACED ( 333760 117600 ) FS ;
+ - FILLER_11_302 gf180mcu_fd_sc_mcu7t5v0__fillcap_8 + SOURCE DIST + PLACED ( 351680 117600 ) FS ;
+ - FILLER_11_310 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 360640 117600 ) FS ;
+ - FILLER_11_340 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 394240 117600 ) FS ;
+ - FILLER_11_344 gf180mcu_fd_sc_mcu7t5v0__fillcap_8 + SOURCE DIST + PLACED ( 398720 117600 ) FS ;
+ - FILLER_11_354 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 409920 117600 ) FS ;
+ - FILLER_11_357 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 413280 117600 ) FS ;
+ - FILLER_11_390 gf180mcu_fd_sc_mcu7t5v0__fillcap_16 + SOURCE DIST + PLACED ( 450240 117600 ) FS ;
+ - FILLER_11_406 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 468160 117600 ) FS ;
+ - FILLER_11_416 gf180mcu_fd_sc_mcu7t5v0__fillcap_8 + SOURCE DIST + PLACED ( 479360 117600 ) FS ;
+ - FILLER_11_424 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 488320 117600 ) FS ;
+ - FILLER_11_428 gf180mcu_fd_sc_mcu7t5v0__fillcap_64 + SOURCE DIST + PLACED ( 492800 117600 ) FS ;
+ - FILLER_11_492 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 564480 117600 ) FS ;
+ - FILLER_11_496 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 568960 117600 ) FS ;
+ - FILLER_11_499 gf180mcu_fd_sc_mcu7t5v0__fillcap_8 + SOURCE DIST + PLACED ( 572320 117600 ) FS ;
+ - FILLER_11_507 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 581280 117600 ) FS ;
+ - FILLER_11_66 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 87360 117600 ) FS ;
+ - FILLER_11_70 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 91840 117600 ) FS ;
+ - FILLER_11_73 gf180mcu_fd_sc_mcu7t5v0__fillcap_64 + SOURCE DIST + PLACED ( 95200 117600 ) FS ;
+ - FILLER_12_101 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 126560 125440 ) N ;
+ - FILLER_12_105 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 131040 125440 ) N ;
+ - FILLER_12_108 gf180mcu_fd_sc_mcu7t5v0__fillcap_64 + SOURCE DIST + PLACED ( 134400 125440 ) N ;
+ - FILLER_12_172 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 206080 125440 ) N ;
+ - FILLER_12_176 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 210560 125440 ) N ;
+ - FILLER_12_179 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 213920 125440 ) N ;
+ - FILLER_12_185 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 220640 125440 ) N ;
+ - FILLER_12_189 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 225120 125440 ) N ;
+ - FILLER_12_2 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 15680 125440 ) N ;
+ - FILLER_12_203 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 240800 125440 ) N ;
+ - FILLER_12_205 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 243040 125440 ) N ;
+ - FILLER_12_208 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 246400 125440 ) N ;
+ - FILLER_12_212 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 250880 125440 ) N ;
+ - FILLER_12_23 gf180mcu_fd_sc_mcu7t5v0__fillcap_8 + SOURCE DIST + PLACED ( 39200 125440 ) N ;
+ - FILLER_12_243 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 285600 125440 ) N ;
+ - FILLER_12_247 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 290080 125440 ) N ;
+ - FILLER_12_250 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 293440 125440 ) N ;
+ - FILLER_12_257 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 301280 125440 ) N ;
+ - FILLER_12_261 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 305760 125440 ) N ;
+ - FILLER_12_267 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 312480 125440 ) N ;
+ - FILLER_12_279 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 325920 125440 ) N ;
+ - FILLER_12_283 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 330400 125440 ) N ;
+ - FILLER_12_287 gf180mcu_fd_sc_mcu7t5v0__fillcap_32 + SOURCE DIST + PLACED ( 334880 125440 ) N ;
+ - FILLER_12_31 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 48160 125440 ) N ;
+ - FILLER_12_321 gf180mcu_fd_sc_mcu7t5v0__fillcap_8 + SOURCE DIST + PLACED ( 372960 125440 ) N ;
+ - FILLER_12_329 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 381920 125440 ) N ;
+ - FILLER_12_332 gf180mcu_fd_sc_mcu7t5v0__fillcap_8 + SOURCE DIST + PLACED ( 385280 125440 ) N ;
+ - FILLER_12_352 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 407680 125440 ) N ;
+ - FILLER_12_356 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 412160 125440 ) N ;
+ - FILLER_12_363 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 420000 125440 ) N ;
+ - FILLER_12_367 gf180mcu_fd_sc_mcu7t5v0__fillcap_16 + SOURCE DIST + PLACED ( 424480 125440 ) N ;
+ - FILLER_12_37 gf180mcu_fd_sc_mcu7t5v0__fillcap_64 + SOURCE DIST + PLACED ( 54880 125440 ) N ;
+ - FILLER_12_383 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 442400 125440 ) N ;
+ - FILLER_12_387 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 446880 125440 ) N ;
+ - FILLER_12_389 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 449120 125440 ) N ;
+ - FILLER_12_392 gf180mcu_fd_sc_mcu7t5v0__fillcap_64 + SOURCE DIST + PLACED ( 452480 125440 ) N ;
+ - FILLER_12_456 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 524160 125440 ) N ;
+ - FILLER_12_460 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 528640 125440 ) N ;
+ - FILLER_12_463 gf180mcu_fd_sc_mcu7t5v0__fillcap_32 + SOURCE DIST + PLACED ( 532000 125440 ) N ;
+ - FILLER_12_495 gf180mcu_fd_sc_mcu7t5v0__fillcap_8 + SOURCE DIST + PLACED ( 567840 125440 ) N ;
+ - FILLER_12_503 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 576800 125440 ) N ;
+ - FILLER_12_508 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 582400 125440 ) N ;
+ - FILLER_12_7 gf180mcu_fd_sc_mcu7t5v0__fillcap_16 + SOURCE DIST + PLACED ( 21280 125440 ) N ;
+ - FILLER_13_137 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 166880 133280 ) FS ;
+ - FILLER_13_141 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 171360 133280 ) FS ;
+ - FILLER_13_144 gf180mcu_fd_sc_mcu7t5v0__fillcap_8 + SOURCE DIST + PLACED ( 174720 133280 ) FS ;
+ - FILLER_13_152 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 183680 133280 ) FS ;
+ - FILLER_13_156 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 188160 133280 ) FS ;
+ - FILLER_13_187 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 222880 133280 ) FS ;
+ - FILLER_13_2 gf180mcu_fd_sc_mcu7t5v0__fillcap_64 + SOURCE DIST + PLACED ( 15680 133280 ) FS ;
+ - FILLER_13_202 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 239680 133280 ) FS ;
+ - FILLER_13_209 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 247520 133280 ) FS ;
+ - FILLER_13_215 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 254240 133280 ) FS ;
+ - FILLER_13_217 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 256480 133280 ) FS ;
+ - FILLER_13_225 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 265440 133280 ) FS ;
+ - FILLER_13_229 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 269920 133280 ) FS ;
+ - FILLER_13_233 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 274400 133280 ) FS ;
+ - FILLER_13_237 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 278880 133280 ) FS ;
+ - FILLER_13_247 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 290080 133280 ) FS ;
+ - FILLER_13_249 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 292320 133280 ) FS ;
+ - FILLER_13_255 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 299040 133280 ) FS ;
+ - FILLER_13_265 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 310240 133280 ) FS ;
+ - FILLER_13_275 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 321440 133280 ) FS ;
+ - FILLER_13_283 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 330400 133280 ) FS ;
+ - FILLER_13_286 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 333760 133280 ) FS ;
+ - FILLER_13_295 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 343840 133280 ) FS ;
+ - FILLER_13_299 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 348320 133280 ) FS ;
+ - FILLER_13_330 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 383040 133280 ) FS ;
+ - FILLER_13_345 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 399840 133280 ) FS ;
+ - FILLER_13_347 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 402080 133280 ) FS ;
+ - FILLER_13_354 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 409920 133280 ) FS ;
+ - FILLER_13_357 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 413280 133280 ) FS ;
+ - FILLER_13_366 gf180mcu_fd_sc_mcu7t5v0__fillcap_8 + SOURCE DIST + PLACED ( 423360 133280 ) FS ;
+ - FILLER_13_376 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 434560 133280 ) FS ;
+ - FILLER_13_380 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 439040 133280 ) FS ;
+ - FILLER_13_411 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 473760 133280 ) FS ;
+ - FILLER_13_415 gf180mcu_fd_sc_mcu7t5v0__fillcap_8 + SOURCE DIST + PLACED ( 478240 133280 ) FS ;
+ - FILLER_13_423 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 487200 133280 ) FS ;
+ - FILLER_13_425 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 489440 133280 ) FS ;
+ - FILLER_13_428 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 492800 133280 ) FS ;
+ - FILLER_13_433 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 498400 133280 ) FS ;
+ - FILLER_13_437 gf180mcu_fd_sc_mcu7t5v0__fillcap_8 + SOURCE DIST + PLACED ( 502880 133280 ) FS ;
+ - FILLER_13_447 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 514080 133280 ) FS ;
+ - FILLER_13_451 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 518560 133280 ) FS ;
+ - FILLER_13_455 gf180mcu_fd_sc_mcu7t5v0__fillcap_32 + SOURCE DIST + PLACED ( 523040 133280 ) FS ;
+ - FILLER_13_487 gf180mcu_fd_sc_mcu7t5v0__fillcap_8 + SOURCE DIST + PLACED ( 558880 133280 ) FS ;
+ - FILLER_13_495 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 567840 133280 ) FS ;
+ - FILLER_13_499 gf180mcu_fd_sc_mcu7t5v0__fillcap_8 + SOURCE DIST + PLACED ( 572320 133280 ) FS ;
+ - FILLER_13_507 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 581280 133280 ) FS ;
+ - FILLER_13_66 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 87360 133280 ) FS ;
+ - FILLER_13_70 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 91840 133280 ) FS ;
+ - FILLER_13_73 gf180mcu_fd_sc_mcu7t5v0__fillcap_64 + SOURCE DIST + PLACED ( 95200 133280 ) FS ;
+ - FILLER_14_101 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 126560 141120 ) N ;
+ - FILLER_14_105 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 131040 141120 ) N ;
+ - FILLER_14_108 gf180mcu_fd_sc_mcu7t5v0__fillcap_64 + SOURCE DIST + PLACED ( 134400 141120 ) N ;
+ - FILLER_14_172 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 206080 141120 ) N ;
+ - FILLER_14_176 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 210560 141120 ) N ;
+ - FILLER_14_179 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 213920 141120 ) N ;
+ - FILLER_14_181 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 216160 141120 ) N ;
+ - FILLER_14_188 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 224000 141120 ) N ;
+ - FILLER_14_199 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 236320 141120 ) N ;
+ - FILLER_14_2 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 15680 141120 ) N ;
+ - FILLER_14_207 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 245280 141120 ) N ;
+ - FILLER_14_211 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 249760 141120 ) N ;
+ - FILLER_14_214 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 253120 141120 ) N ;
+ - FILLER_14_218 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 257600 141120 ) N ;
+ - FILLER_14_228 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 268800 141120 ) N ;
+ - FILLER_14_23 gf180mcu_fd_sc_mcu7t5v0__fillcap_8 + SOURCE DIST + PLACED ( 39200 141120 ) N ;
+ - FILLER_14_232 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 273280 141120 ) N ;
+ - FILLER_14_236 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 277760 141120 ) N ;
+ - FILLER_14_240 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 282240 141120 ) N ;
+ - FILLER_14_243 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 285600 141120 ) N ;
+ - FILLER_14_247 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 290080 141120 ) N ;
+ - FILLER_14_250 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 293440 141120 ) N ;
+ - FILLER_14_256 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 300160 141120 ) N ;
+ - FILLER_14_262 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 306880 141120 ) N ;
+ - FILLER_14_269 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 314720 141120 ) N ;
+ - FILLER_14_279 gf180mcu_fd_sc_mcu7t5v0__fillcap_8 + SOURCE DIST + PLACED ( 325920 141120 ) N ;
+ - FILLER_14_31 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 48160 141120 ) N ;
+ - FILLER_14_316 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 367360 141120 ) N ;
+ - FILLER_14_318 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 369600 141120 ) N ;
+ - FILLER_14_321 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 372960 141120 ) N ;
+ - FILLER_14_324 gf180mcu_fd_sc_mcu7t5v0__fillcap_16 + SOURCE DIST + PLACED ( 376320 141120 ) N ;
+ - FILLER_14_340 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 394240 141120 ) N ;
+ - FILLER_14_344 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 398720 141120 ) N ;
+ - FILLER_14_37 gf180mcu_fd_sc_mcu7t5v0__fillcap_16 + SOURCE DIST + PLACED ( 54880 141120 ) N ;
+ - FILLER_14_374 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 432320 141120 ) N ;
+ - FILLER_14_378 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 436800 141120 ) N ;
+ - FILLER_14_387 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 446880 141120 ) N ;
+ - FILLER_14_389 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 449120 141120 ) N ;
+ - FILLER_14_392 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 452480 141120 ) N ;
+ - FILLER_14_401 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 462560 141120 ) N ;
+ - FILLER_14_405 gf180mcu_fd_sc_mcu7t5v0__fillcap_8 + SOURCE DIST + PLACED ( 467040 141120 ) N ;
+ - FILLER_14_413 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 476000 141120 ) N ;
+ - FILLER_14_415 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 478240 141120 ) N ;
+ - FILLER_14_429 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 493920 141120 ) N ;
+ - FILLER_14_437 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 502880 141120 ) N ;
+ - FILLER_14_441 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 507360 141120 ) N ;
+ - FILLER_14_445 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 511840 141120 ) N ;
+ - FILLER_14_448 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 515200 141120 ) N ;
+ - FILLER_14_452 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 519680 141120 ) N ;
+ - FILLER_14_458 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 526400 141120 ) N ;
+ - FILLER_14_460 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 528640 141120 ) N ;
+ - FILLER_14_463 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 532000 141120 ) N ;
+ - FILLER_14_466 gf180mcu_fd_sc_mcu7t5v0__fillcap_32 + SOURCE DIST + PLACED ( 535360 141120 ) N ;
+ - FILLER_14_500 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 573440 141120 ) N ;
+ - FILLER_14_508 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 582400 141120 ) N ;
+ - FILLER_14_53 gf180mcu_fd_sc_mcu7t5v0__fillcap_8 + SOURCE DIST + PLACED ( 72800 141120 ) N ;
+ - FILLER_14_61 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 81760 141120 ) N ;
+ - FILLER_14_65 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 86240 141120 ) N ;
+ - FILLER_14_67 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 88480 141120 ) N ;
+ - FILLER_14_7 gf180mcu_fd_sc_mcu7t5v0__fillcap_16 + SOURCE DIST + PLACED ( 21280 141120 ) N ;
+ - FILLER_14_97 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 122080 141120 ) N ;
+ - FILLER_15_120 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 147840 148960 ) FS ;
+ - FILLER_15_124 gf180mcu_fd_sc_mcu7t5v0__fillcap_16 + SOURCE DIST + PLACED ( 152320 148960 ) FS ;
+ - FILLER_15_140 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 170240 148960 ) FS ;
+ - FILLER_15_144 gf180mcu_fd_sc_mcu7t5v0__fillcap_32 + SOURCE DIST + PLACED ( 174720 148960 ) FS ;
+ - FILLER_15_176 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 210560 148960 ) FS ;
+ - FILLER_15_18 gf180mcu_fd_sc_mcu7t5v0__fillcap_8 + SOURCE DIST + PLACED ( 33600 148960 ) FS ;
+ - FILLER_15_180 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 215040 148960 ) FS ;
+ - FILLER_15_184 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 219520 148960 ) FS ;
+ - FILLER_15_2 gf180mcu_fd_sc_mcu7t5v0__fillcap_16 + SOURCE DIST + PLACED ( 15680 148960 ) FS ;
+ - FILLER_15_212 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 250880 148960 ) FS ;
+ - FILLER_15_215 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 254240 148960 ) FS ;
+ - FILLER_15_229 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 269920 148960 ) FS ;
+ - FILLER_15_235 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 276640 148960 ) FS ;
+ - FILLER_15_239 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 281120 148960 ) FS ;
+ - FILLER_15_242 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 284480 148960 ) FS ;
+ - FILLER_15_248 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 291200 148960 ) FS ;
+ - FILLER_15_26 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 42560 148960 ) FS ;
+ - FILLER_15_260 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 304640 148960 ) FS ;
+ - FILLER_15_264 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 309120 148960 ) FS ;
+ - FILLER_15_268 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 313600 148960 ) FS ;
+ - FILLER_15_271 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 316960 148960 ) FS ;
+ - FILLER_15_283 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 330400 148960 ) FS ;
+ - FILLER_15_286 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 333760 148960 ) FS ;
+ - FILLER_15_289 gf180mcu_fd_sc_mcu7t5v0__fillcap_32 + SOURCE DIST + PLACED ( 337120 148960 ) FS ;
+ - FILLER_15_321 gf180mcu_fd_sc_mcu7t5v0__fillcap_16 + SOURCE DIST + PLACED ( 372960 148960 ) FS ;
+ - FILLER_15_337 gf180mcu_fd_sc_mcu7t5v0__fillcap_8 + SOURCE DIST + PLACED ( 390880 148960 ) FS ;
+ - FILLER_15_345 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 399840 148960 ) FS ;
+ - FILLER_15_348 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 403200 148960 ) FS ;
+ - FILLER_15_354 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 409920 148960 ) FS ;
+ - FILLER_15_357 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 413280 148960 ) FS ;
+ - FILLER_15_366 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 423360 148960 ) FS ;
+ - FILLER_15_368 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 425600 148960 ) FS ;
+ - FILLER_15_392 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 452480 148960 ) FS ;
+ - FILLER_15_412 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 474880 148960 ) FS ;
+ - FILLER_15_414 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 477120 148960 ) FS ;
+ - FILLER_15_417 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 480480 148960 ) FS ;
+ - FILLER_15_421 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 484960 148960 ) FS ;
+ - FILLER_15_425 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 489440 148960 ) FS ;
+ - FILLER_15_428 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 492800 148960 ) FS ;
+ - FILLER_15_434 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 499520 148960 ) FS ;
+ - FILLER_15_444 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 510720 148960 ) FS ;
+ - FILLER_15_446 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 512960 148960 ) FS ;
+ - FILLER_15_455 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 523040 148960 ) FS ;
+ - FILLER_15_465 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 534240 148960 ) FS ;
+ - FILLER_15_469 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 538720 148960 ) FS ;
+ - FILLER_15_473 gf180mcu_fd_sc_mcu7t5v0__fillcap_16 + SOURCE DIST + PLACED ( 543200 148960 ) FS ;
+ - FILLER_15_489 gf180mcu_fd_sc_mcu7t5v0__fillcap_8 + SOURCE DIST + PLACED ( 561120 148960 ) FS ;
+ - FILLER_15_499 gf180mcu_fd_sc_mcu7t5v0__fillcap_8 + SOURCE DIST + PLACED ( 572320 148960 ) FS ;
+ - FILLER_15_507 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 581280 148960 ) FS ;
+ - FILLER_15_57 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 77280 148960 ) FS ;
+ - FILLER_15_61 gf180mcu_fd_sc_mcu7t5v0__fillcap_8 + SOURCE DIST + PLACED ( 81760 148960 ) FS ;
+ - FILLER_15_69 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 90720 148960 ) FS ;
+ - FILLER_15_73 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 95200 148960 ) FS ;
+ - FILLER_15_75 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 97440 148960 ) FS ;
+ - FILLER_15_78 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 100800 148960 ) FS ;
+ - FILLER_15_86 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 109760 148960 ) FS ;
+ - FILLER_15_90 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 114240 148960 ) FS ;
+ - FILLER_16_105 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 131040 156800 ) N ;
+ - FILLER_16_108 gf180mcu_fd_sc_mcu7t5v0__fillcap_64 + SOURCE DIST + PLACED ( 134400 156800 ) N ;
+ - FILLER_16_172 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 206080 156800 ) N ;
+ - FILLER_16_176 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 210560 156800 ) N ;
+ - FILLER_16_179 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 213920 156800 ) N ;
+ - FILLER_16_182 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 217280 156800 ) N ;
+ - FILLER_16_186 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 221760 156800 ) N ;
+ - FILLER_16_2 gf180mcu_fd_sc_mcu7t5v0__fillcap_32 + SOURCE DIST + PLACED ( 15680 156800 ) N ;
+ - FILLER_16_217 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 256480 156800 ) N ;
+ - FILLER_16_219 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 258720 156800 ) N ;
+ - FILLER_16_226 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 266560 156800 ) N ;
+ - FILLER_16_240 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 282240 156800 ) N ;
+ - FILLER_16_247 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 290080 156800 ) N ;
+ - FILLER_16_250 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 293440 156800 ) N ;
+ - FILLER_16_255 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 299040 156800 ) N ;
+ - FILLER_16_259 gf180mcu_fd_sc_mcu7t5v0__fillcap_8 + SOURCE DIST + PLACED ( 303520 156800 ) N ;
+ - FILLER_16_269 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 314720 156800 ) N ;
+ - FILLER_16_279 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 325920 156800 ) N ;
+ - FILLER_16_286 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 333760 156800 ) N ;
+ - FILLER_16_290 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 338240 156800 ) N ;
+ - FILLER_16_294 gf180mcu_fd_sc_mcu7t5v0__fillcap_16 + SOURCE DIST + PLACED ( 342720 156800 ) N ;
+ - FILLER_16_310 gf180mcu_fd_sc_mcu7t5v0__fillcap_8 + SOURCE DIST + PLACED ( 360640 156800 ) N ;
+ - FILLER_16_318 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 369600 156800 ) N ;
+ - FILLER_16_321 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 372960 156800 ) N ;
+ - FILLER_16_327 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 379680 156800 ) N ;
+ - FILLER_16_331 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 384160 156800 ) N ;
+ - FILLER_16_333 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 386400 156800 ) N ;
+ - FILLER_16_34 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 51520 156800 ) N ;
+ - FILLER_16_346 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 400960 156800 ) N ;
+ - FILLER_16_350 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 405440 156800 ) N ;
+ - FILLER_16_354 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 409920 156800 ) N ;
+ - FILLER_16_358 gf180mcu_fd_sc_mcu7t5v0__fillcap_32 + SOURCE DIST + PLACED ( 414400 156800 ) N ;
+ - FILLER_16_37 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 54880 156800 ) N ;
+ - FILLER_16_392 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 452480 156800 ) N ;
+ - FILLER_16_395 gf180mcu_fd_sc_mcu7t5v0__fillcap_8 + SOURCE DIST + PLACED ( 455840 156800 ) N ;
+ - FILLER_16_403 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 464800 156800 ) N ;
+ - FILLER_16_412 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 474880 156800 ) N ;
+ - FILLER_16_426 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 490560 156800 ) N ;
+ - FILLER_16_436 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 501760 156800 ) N ;
+ - FILLER_16_446 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 512960 156800 ) N ;
+ - FILLER_16_460 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 528640 156800 ) N ;
+ - FILLER_16_463 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 532000 156800 ) N ;
+ - FILLER_16_469 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 538720 156800 ) N ;
+ - FILLER_16_47 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 66080 156800 ) N ;
+ - FILLER_16_476 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 546560 156800 ) N ;
+ - FILLER_16_480 gf180mcu_fd_sc_mcu7t5v0__fillcap_16 + SOURCE DIST + PLACED ( 551040 156800 ) N ;
+ - FILLER_16_496 gf180mcu_fd_sc_mcu7t5v0__fillcap_8 + SOURCE DIST + PLACED ( 568960 156800 ) N ;
+ - FILLER_16_504 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 577920 156800 ) N ;
+ - FILLER_16_508 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 582400 156800 ) N ;
+ - FILLER_16_51 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 70560 156800 ) N ;
+ - FILLER_16_55 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 75040 156800 ) N ;
+ - FILLER_16_85 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 108640 156800 ) N ;
+ - FILLER_16_89 gf180mcu_fd_sc_mcu7t5v0__fillcap_16 + SOURCE DIST + PLACED ( 113120 156800 ) N ;
+ - FILLER_17_126 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 154560 164640 ) FS ;
+ - FILLER_17_130 gf180mcu_fd_sc_mcu7t5v0__fillcap_8 + SOURCE DIST + PLACED ( 159040 164640 ) FS ;
+ - FILLER_17_138 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 168000 164640 ) FS ;
+ - FILLER_17_144 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 174720 164640 ) FS ;
+ - FILLER_17_179 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 213920 164640 ) FS ;
+ - FILLER_17_191 gf180mcu_fd_sc_mcu7t5v0__fillcap_8 + SOURCE DIST + PLACED ( 227360 164640 ) FS ;
+ - FILLER_17_199 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 236320 164640 ) FS ;
+ - FILLER_17_2 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 15680 164640 ) FS ;
+ - FILLER_17_203 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 240800 164640 ) FS ;
+ - FILLER_17_209 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 247520 164640 ) FS ;
+ - FILLER_17_215 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 254240 164640 ) FS ;
+ - FILLER_17_219 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 258720 164640 ) FS ;
+ - FILLER_17_223 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 263200 164640 ) FS ;
+ - FILLER_17_227 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 267680 164640 ) FS ;
+ - FILLER_17_231 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 272160 164640 ) FS ;
+ - FILLER_17_262 gf180mcu_fd_sc_mcu7t5v0__fillcap_8 + SOURCE DIST + PLACED ( 306880 164640 ) FS ;
+ - FILLER_17_270 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 315840 164640 ) FS ;
+ - FILLER_17_274 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 320320 164640 ) FS ;
+ - FILLER_17_283 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 330400 164640 ) FS ;
+ - FILLER_17_286 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 333760 164640 ) FS ;
+ - FILLER_17_319 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 370720 164640 ) FS ;
+ - FILLER_17_331 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 384160 164640 ) FS ;
+ - FILLER_17_346 gf180mcu_fd_sc_mcu7t5v0__fillcap_8 + SOURCE DIST + PLACED ( 400960 164640 ) FS ;
+ - FILLER_17_354 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 409920 164640 ) FS ;
+ - FILLER_17_357 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 413280 164640 ) FS ;
+ - FILLER_17_364 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 421120 164640 ) FS ;
+ - FILLER_17_374 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 432320 164640 ) FS ;
+ - FILLER_17_39 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 57120 164640 ) FS ;
+ - FILLER_17_399 gf180mcu_fd_sc_mcu7t5v0__fillcap_8 + SOURCE DIST + PLACED ( 460320 164640 ) FS ;
+ - FILLER_17_407 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 469280 164640 ) FS ;
+ - FILLER_17_411 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 473760 164640 ) FS ;
+ - FILLER_17_414 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 477120 164640 ) FS ;
+ - FILLER_17_422 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 486080 164640 ) FS ;
+ - FILLER_17_428 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 492800 164640 ) FS ;
+ - FILLER_17_43 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 61600 164640 ) FS ;
+ - FILLER_17_439 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 505120 164640 ) FS ;
+ - FILLER_17_443 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 509600 164640 ) FS ;
+ - FILLER_17_447 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 514080 164640 ) FS ;
+ - FILLER_17_451 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 518560 164640 ) FS ;
+ - FILLER_17_459 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 527520 164640 ) FS ;
+ - FILLER_17_466 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 535360 164640 ) FS ;
+ - FILLER_17_470 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 539840 164640 ) FS ;
+ - FILLER_17_474 gf180mcu_fd_sc_mcu7t5v0__fillcap_16 + SOURCE DIST + PLACED ( 544320 164640 ) FS ;
+ - FILLER_17_490 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 562240 164640 ) FS ;
+ - FILLER_17_494 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 566720 164640 ) FS ;
+ - FILLER_17_496 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 568960 164640 ) FS ;
+ - FILLER_17_499 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 572320 164640 ) FS ;
+ - FILLER_17_503 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 576800 164640 ) FS ;
+ - FILLER_17_508 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 582400 164640 ) FS ;
+ - FILLER_17_52 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 71680 164640 ) FS ;
+ - FILLER_17_60 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 80640 164640 ) FS ;
+ - FILLER_17_7 gf180mcu_fd_sc_mcu7t5v0__fillcap_32 + SOURCE DIST + PLACED ( 21280 164640 ) FS ;
+ - FILLER_17_70 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 91840 164640 ) FS ;
+ - FILLER_17_73 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 95200 164640 ) FS ;
+ - FILLER_17_76 gf180mcu_fd_sc_mcu7t5v0__fillcap_8 + SOURCE DIST + PLACED ( 98560 164640 ) FS ;
+ - FILLER_17_84 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 107520 164640 ) FS ;
+ - FILLER_17_88 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 112000 164640 ) FS ;
+ - FILLER_17_98 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 123200 164640 ) FS ;
+ - FILLER_18_105 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 131040 172480 ) N ;
+ - FILLER_18_108 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 134400 172480 ) N ;
+ - FILLER_18_115 gf180mcu_fd_sc_mcu7t5v0__fillcap_8 + SOURCE DIST + PLACED ( 142240 172480 ) N ;
+ - FILLER_18_123 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 151200 172480 ) N ;
+ - FILLER_18_127 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 155680 172480 ) N ;
+ - FILLER_18_131 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 160160 172480 ) N ;
+ - FILLER_18_164 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 197120 172480 ) N ;
+ - FILLER_18_172 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 206080 172480 ) N ;
+ - FILLER_18_176 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 210560 172480 ) N ;
+ - FILLER_18_179 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 213920 172480 ) N ;
+ - FILLER_18_188 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 224000 172480 ) N ;
+ - FILLER_18_192 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 228480 172480 ) N ;
+ - FILLER_18_196 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 232960 172480 ) N ;
+ - FILLER_18_2 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 15680 172480 ) N ;
+ - FILLER_18_200 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 237440 172480 ) N ;
+ - FILLER_18_207 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 245280 172480 ) N ;
+ - FILLER_18_211 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 249760 172480 ) N ;
+ - FILLER_18_222 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 262080 172480 ) N ;
+ - FILLER_18_226 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 266560 172480 ) N ;
+ - FILLER_18_23 gf180mcu_fd_sc_mcu7t5v0__fillcap_8 + SOURCE DIST + PLACED ( 39200 172480 ) N ;
+ - FILLER_18_230 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 271040 172480 ) N ;
+ - FILLER_18_232 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 273280 172480 ) N ;
+ - FILLER_18_235 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 276640 172480 ) N ;
+ - FILLER_18_243 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 285600 172480 ) N ;
+ - FILLER_18_247 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 290080 172480 ) N ;
+ - FILLER_18_250 gf180mcu_fd_sc_mcu7t5v0__fillcap_16 + SOURCE DIST + PLACED ( 293440 172480 ) N ;
+ - FILLER_18_266 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 311360 172480 ) N ;
+ - FILLER_18_270 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 315840 172480 ) N ;
+ - FILLER_18_277 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 323680 172480 ) N ;
+ - FILLER_18_281 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 328160 172480 ) N ;
+ - FILLER_18_283 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 330400 172480 ) N ;
+ - FILLER_18_290 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 338240 172480 ) N ;
+ - FILLER_18_294 gf180mcu_fd_sc_mcu7t5v0__fillcap_16 + SOURCE DIST + PLACED ( 342720 172480 ) N ;
+ - FILLER_18_31 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 48160 172480 ) N ;
+ - FILLER_18_310 gf180mcu_fd_sc_mcu7t5v0__fillcap_8 + SOURCE DIST + PLACED ( 360640 172480 ) N ;
+ - FILLER_18_318 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 369600 172480 ) N ;
+ - FILLER_18_321 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 372960 172480 ) N ;
+ - FILLER_18_324 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 376320 172480 ) N ;
+ - FILLER_18_328 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 380800 172480 ) N ;
+ - FILLER_18_336 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 389760 172480 ) N ;
+ - FILLER_18_34 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 51520 172480 ) N ;
+ - FILLER_18_340 gf180mcu_fd_sc_mcu7t5v0__fillcap_8 + SOURCE DIST + PLACED ( 394240 172480 ) N ;
+ - FILLER_18_348 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 403200 172480 ) N ;
+ - FILLER_18_355 gf180mcu_fd_sc_mcu7t5v0__fillcap_8 + SOURCE DIST + PLACED ( 411040 172480 ) N ;
+ - FILLER_18_363 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 420000 172480 ) N ;
+ - FILLER_18_37 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 54880 172480 ) N ;
+ - FILLER_18_376 gf180mcu_fd_sc_mcu7t5v0__fillcap_8 + SOURCE DIST + PLACED ( 434560 172480 ) N ;
+ - FILLER_18_384 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 443520 172480 ) N ;
+ - FILLER_18_388 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 448000 172480 ) N ;
+ - FILLER_18_392 gf180mcu_fd_sc_mcu7t5v0__fillcap_8 + SOURCE DIST + PLACED ( 452480 172480 ) N ;
+ - FILLER_18_400 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 461440 172480 ) N ;
+ - FILLER_18_402 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 463680 172480 ) N ;
+ - FILLER_18_405 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 467040 172480 ) N ;
+ - FILLER_18_417 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 480480 172480 ) N ;
+ - FILLER_18_425 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 489440 172480 ) N ;
+ - FILLER_18_431 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 496160 172480 ) N ;
+ - FILLER_18_435 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 500640 172480 ) N ;
+ - FILLER_18_439 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 505120 172480 ) N ;
+ - FILLER_18_44 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 62720 172480 ) N ;
+ - FILLER_18_443 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 509600 172480 ) N ;
+ - FILLER_18_447 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 514080 172480 ) N ;
+ - FILLER_18_451 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 518560 172480 ) N ;
+ - FILLER_18_455 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 523040 172480 ) N ;
+ - FILLER_18_457 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 525280 172480 ) N ;
+ - FILLER_18_460 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 528640 172480 ) N ;
+ - FILLER_18_463 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 532000 172480 ) N ;
+ - FILLER_18_474 gf180mcu_fd_sc_mcu7t5v0__fillcap_32 + SOURCE DIST + PLACED ( 544320 172480 ) N ;
+ - FILLER_18_48 gf180mcu_fd_sc_mcu7t5v0__fillcap_16 + SOURCE DIST + PLACED ( 67200 172480 ) N ;
+ - FILLER_18_506 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 580160 172480 ) N ;
+ - FILLER_18_508 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 582400 172480 ) N ;
+ - FILLER_18_64 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 85120 172480 ) N ;
+ - FILLER_18_66 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 87360 172480 ) N ;
+ - FILLER_18_7 gf180mcu_fd_sc_mcu7t5v0__fillcap_16 + SOURCE DIST + PLACED ( 21280 172480 ) N ;
+ - FILLER_18_75 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 97440 172480 ) N ;
+ - FILLER_18_83 gf180mcu_fd_sc_mcu7t5v0__fillcap_8 + SOURCE DIST + PLACED ( 106400 172480 ) N ;
+ - FILLER_18_91 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 115360 172480 ) N ;
+ - FILLER_18_95 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 119840 172480 ) N ;
+ - FILLER_19_105 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 131040 180320 ) FS ;
+ - FILLER_19_136 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 165760 180320 ) FS ;
+ - FILLER_19_140 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 170240 180320 ) FS ;
+ - FILLER_19_144 gf180mcu_fd_sc_mcu7t5v0__fillcap_16 + SOURCE DIST + PLACED ( 174720 180320 ) FS ;
+ - FILLER_19_160 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 192640 180320 ) FS ;
+ - FILLER_19_163 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 196000 180320 ) FS ;
+ - FILLER_19_173 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 207200 180320 ) FS ;
+ - FILLER_19_179 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 213920 180320 ) FS ;
+ - FILLER_19_2 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 15680 180320 ) FS ;
+ - FILLER_19_207 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 245280 180320 ) FS ;
+ - FILLER_19_211 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 249760 180320 ) FS ;
+ - FILLER_19_215 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 254240 180320 ) FS ;
+ - FILLER_19_228 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 268800 180320 ) FS ;
+ - FILLER_19_232 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 273280 180320 ) FS ;
+ - FILLER_19_236 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 277760 180320 ) FS ;
+ - FILLER_19_247 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 290080 180320 ) FS ;
+ - FILLER_19_251 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 294560 180320 ) FS ;
+ - FILLER_19_255 gf180mcu_fd_sc_mcu7t5v0__fillcap_8 + SOURCE DIST + PLACED ( 299040 180320 ) FS ;
+ - FILLER_19_263 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 308000 180320 ) FS ;
+ - FILLER_19_265 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 310240 180320 ) FS ;
+ - FILLER_19_268 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 313600 180320 ) FS ;
+ - FILLER_19_278 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 324800 180320 ) FS ;
+ - FILLER_19_282 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 329280 180320 ) FS ;
+ - FILLER_19_286 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 333760 180320 ) FS ;
+ - FILLER_19_290 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 338240 180320 ) FS ;
+ - FILLER_19_292 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 340480 180320 ) FS ;
+ - FILLER_19_32 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 49280 180320 ) FS ;
+ - FILLER_19_322 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 374080 180320 ) FS ;
+ - FILLER_19_326 gf180mcu_fd_sc_mcu7t5v0__fillcap_16 + SOURCE DIST + PLACED ( 378560 180320 ) FS ;
+ - FILLER_19_342 gf180mcu_fd_sc_mcu7t5v0__fillcap_8 + SOURCE DIST + PLACED ( 396480 180320 ) FS ;
+ - FILLER_19_350 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 405440 180320 ) FS ;
+ - FILLER_19_354 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 409920 180320 ) FS ;
+ - FILLER_19_357 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 413280 180320 ) FS ;
+ - FILLER_19_361 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 417760 180320 ) FS ;
+ - FILLER_19_368 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 425600 180320 ) FS ;
+ - FILLER_19_393 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 453600 180320 ) FS ;
+ - FILLER_19_397 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 458080 180320 ) FS ;
+ - FILLER_19_399 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 460320 180320 ) FS ;
+ - FILLER_19_408 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 470400 180320 ) FS ;
+ - FILLER_19_418 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 481600 180320 ) FS ;
+ - FILLER_19_422 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 486080 180320 ) FS ;
+ - FILLER_19_428 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 492800 180320 ) FS ;
+ - FILLER_19_439 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 505120 180320 ) FS ;
+ - FILLER_19_443 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 509600 180320 ) FS ;
+ - FILLER_19_447 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 514080 180320 ) FS ;
+ - FILLER_19_458 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 526400 180320 ) FS ;
+ - FILLER_19_47 gf180mcu_fd_sc_mcu7t5v0__fillcap_16 + SOURCE DIST + PLACED ( 66080 180320 ) FS ;
+ - FILLER_19_470 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 539840 180320 ) FS ;
+ - FILLER_19_477 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 547680 180320 ) FS ;
+ - FILLER_19_483 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 554400 180320 ) FS ;
+ - FILLER_19_487 gf180mcu_fd_sc_mcu7t5v0__fillcap_8 + SOURCE DIST + PLACED ( 558880 180320 ) FS ;
+ - FILLER_19_495 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 567840 180320 ) FS ;
+ - FILLER_19_499 gf180mcu_fd_sc_mcu7t5v0__fillcap_8 + SOURCE DIST + PLACED ( 572320 180320 ) FS ;
+ - FILLER_19_507 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 581280 180320 ) FS ;
+ - FILLER_19_63 gf180mcu_fd_sc_mcu7t5v0__fillcap_8 + SOURCE DIST + PLACED ( 84000 180320 ) FS ;
+ - FILLER_19_73 gf180mcu_fd_sc_mcu7t5v0__fillcap_16 + SOURCE DIST + PLACED ( 95200 180320 ) FS ;
+ - FILLER_19_89 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 113120 180320 ) FS ;
+ - FILLER_19_95 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 119840 180320 ) FS ;
+ - FILLER_1_137 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 166880 39200 ) FS ;
+ - FILLER_1_14 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 29120 39200 ) FS ;
+ - FILLER_1_141 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 171360 39200 ) FS ;
+ - FILLER_1_144 gf180mcu_fd_sc_mcu7t5v0__fillcap_64 + SOURCE DIST + PLACED ( 174720 39200 ) FS ;
+ - FILLER_1_2 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 15680 39200 ) FS ;
+ - FILLER_1_20 gf180mcu_fd_sc_mcu7t5v0__fillcap_32 + SOURCE DIST + PLACED ( 35840 39200 ) FS ;
+ - FILLER_1_208 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 246400 39200 ) FS ;
+ - FILLER_1_212 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 250880 39200 ) FS ;
+ - FILLER_1_215 gf180mcu_fd_sc_mcu7t5v0__fillcap_32 + SOURCE DIST + PLACED ( 254240 39200 ) FS ;
+ - FILLER_1_247 gf180mcu_fd_sc_mcu7t5v0__fillcap_8 + SOURCE DIST + PLACED ( 290080 39200 ) FS ;
+ - FILLER_1_255 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 299040 39200 ) FS ;
+ - FILLER_1_262 gf180mcu_fd_sc_mcu7t5v0__fillcap_16 + SOURCE DIST + PLACED ( 306880 39200 ) FS ;
+ - FILLER_1_278 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 324800 39200 ) FS ;
+ - FILLER_1_282 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 329280 39200 ) FS ;
+ - FILLER_1_286 gf180mcu_fd_sc_mcu7t5v0__fillcap_64 + SOURCE DIST + PLACED ( 333760 39200 ) FS ;
+ - FILLER_1_350 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 405440 39200 ) FS ;
+ - FILLER_1_354 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 409920 39200 ) FS ;
+ - FILLER_1_357 gf180mcu_fd_sc_mcu7t5v0__fillcap_64 + SOURCE DIST + PLACED ( 413280 39200 ) FS ;
+ - FILLER_1_421 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 484960 39200 ) FS ;
+ - FILLER_1_425 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 489440 39200 ) FS ;
+ - FILLER_1_428 gf180mcu_fd_sc_mcu7t5v0__fillcap_8 + SOURCE DIST + PLACED ( 492800 39200 ) FS ;
+ - FILLER_1_436 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 501760 39200 ) FS ;
+ - FILLER_1_440 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 506240 39200 ) FS ;
+ - FILLER_1_448 gf180mcu_fd_sc_mcu7t5v0__fillcap_32 + SOURCE DIST + PLACED ( 515200 39200 ) FS ;
+ - FILLER_1_480 gf180mcu_fd_sc_mcu7t5v0__fillcap_16 + SOURCE DIST + PLACED ( 551040 39200 ) FS ;
+ - FILLER_1_496 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 568960 39200 ) FS ;
+ - FILLER_1_499 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 572320 39200 ) FS ;
+ - FILLER_1_503 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 576800 39200 ) FS ;
+ - FILLER_1_508 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 582400 39200 ) FS ;
+ - FILLER_1_52 gf180mcu_fd_sc_mcu7t5v0__fillcap_16 + SOURCE DIST + PLACED ( 71680 39200 ) FS ;
+ - FILLER_1_6 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 20160 39200 ) FS ;
+ - FILLER_1_68 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 89600 39200 ) FS ;
+ - FILLER_1_70 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 91840 39200 ) FS ;
+ - FILLER_1_73 gf180mcu_fd_sc_mcu7t5v0__fillcap_64 + SOURCE DIST + PLACED ( 95200 39200 ) FS ;
+ - FILLER_20_103 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 128800 188160 ) N ;
+ - FILLER_20_105 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 131040 188160 ) N ;
+ - FILLER_20_108 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 134400 188160 ) N ;
+ - FILLER_20_115 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 142240 188160 ) N ;
+ - FILLER_20_123 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 151200 188160 ) N ;
+ - FILLER_20_125 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 153440 188160 ) N ;
+ - FILLER_20_128 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 156800 188160 ) N ;
+ - FILLER_20_159 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 191520 188160 ) N ;
+ - FILLER_20_169 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 202720 188160 ) N ;
+ - FILLER_20_173 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 207200 188160 ) N ;
+ - FILLER_20_179 gf180mcu_fd_sc_mcu7t5v0__fillcap_8 + SOURCE DIST + PLACED ( 213920 188160 ) N ;
+ - FILLER_20_187 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 222880 188160 ) N ;
+ - FILLER_20_2 gf180mcu_fd_sc_mcu7t5v0__fillcap_32 + SOURCE DIST + PLACED ( 15680 188160 ) N ;
+ - FILLER_20_220 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 259840 188160 ) N ;
+ - FILLER_20_224 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 264320 188160 ) N ;
+ - FILLER_20_233 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 274400 188160 ) N ;
+ - FILLER_20_237 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 278880 188160 ) N ;
+ - FILLER_20_239 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 281120 188160 ) N ;
+ - FILLER_20_242 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 284480 188160 ) N ;
+ - FILLER_20_246 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 288960 188160 ) N ;
+ - FILLER_20_250 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 293440 188160 ) N ;
+ - FILLER_20_255 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 299040 188160 ) N ;
+ - FILLER_20_259 gf180mcu_fd_sc_mcu7t5v0__fillcap_8 + SOURCE DIST + PLACED ( 303520 188160 ) N ;
+ - FILLER_20_269 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 314720 188160 ) N ;
+ - FILLER_20_283 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 330400 188160 ) N ;
+ - FILLER_20_293 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 341600 188160 ) N ;
+ - FILLER_20_297 gf180mcu_fd_sc_mcu7t5v0__fillcap_16 + SOURCE DIST + PLACED ( 346080 188160 ) N ;
+ - FILLER_20_313 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 364000 188160 ) N ;
+ - FILLER_20_317 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 368480 188160 ) N ;
+ - FILLER_20_321 gf180mcu_fd_sc_mcu7t5v0__fillcap_8 + SOURCE DIST + PLACED ( 372960 188160 ) N ;
+ - FILLER_20_329 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 381920 188160 ) N ;
+ - FILLER_20_34 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 51520 188160 ) N ;
+ - FILLER_20_362 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 418880 188160 ) N ;
+ - FILLER_20_369 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 426720 188160 ) N ;
+ - FILLER_20_37 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 54880 188160 ) N ;
+ - FILLER_20_373 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 431200 188160 ) N ;
+ - FILLER_20_380 gf180mcu_fd_sc_mcu7t5v0__fillcap_8 + SOURCE DIST + PLACED ( 439040 188160 ) N ;
+ - FILLER_20_388 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 448000 188160 ) N ;
+ - FILLER_20_39 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 57120 188160 ) N ;
+ - FILLER_20_392 gf180mcu_fd_sc_mcu7t5v0__fillcap_8 + SOURCE DIST + PLACED ( 452480 188160 ) N ;
+ - FILLER_20_402 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 463680 188160 ) N ;
+ - FILLER_20_414 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 477120 188160 ) N ;
+ - FILLER_20_416 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 479360 188160 ) N ;
+ - FILLER_20_425 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 489440 188160 ) N ;
+ - FILLER_20_439 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 505120 188160 ) N ;
+ - FILLER_20_443 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 509600 188160 ) N ;
+ - FILLER_20_447 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 514080 188160 ) N ;
+ - FILLER_20_460 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 528640 188160 ) N ;
+ - FILLER_20_463 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 532000 188160 ) N ;
+ - FILLER_20_473 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 543200 188160 ) N ;
+ - FILLER_20_48 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 67200 188160 ) N ;
+ - FILLER_20_481 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 552160 188160 ) N ;
+ - FILLER_20_485 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 556640 188160 ) N ;
+ - FILLER_20_489 gf180mcu_fd_sc_mcu7t5v0__fillcap_16 + SOURCE DIST + PLACED ( 561120 188160 ) N ;
+ - FILLER_20_505 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 579040 188160 ) N ;
+ - FILLER_20_58 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 78400 188160 ) N ;
+ - FILLER_20_62 gf180mcu_fd_sc_mcu7t5v0__fillcap_16 + SOURCE DIST + PLACED ( 82880 188160 ) N ;
+ - FILLER_20_78 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 100800 188160 ) N ;
+ - FILLER_20_82 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 105280 188160 ) N ;
+ - FILLER_20_90 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 114240 188160 ) N ;
+ - FILLER_21_10 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 24640 196000 ) FS ;
+ - FILLER_21_124 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 152320 196000 ) FS ;
+ - FILLER_21_128 gf180mcu_fd_sc_mcu7t5v0__fillcap_8 + SOURCE DIST + PLACED ( 156800 196000 ) FS ;
+ - FILLER_21_136 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 165760 196000 ) FS ;
+ - FILLER_21_14 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 29120 196000 ) FS ;
+ - FILLER_21_140 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 170240 196000 ) FS ;
+ - FILLER_21_144 gf180mcu_fd_sc_mcu7t5v0__fillcap_16 + SOURCE DIST + PLACED ( 174720 196000 ) FS ;
+ - FILLER_21_160 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 192640 196000 ) FS ;
+ - FILLER_21_169 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 202720 196000 ) FS ;
+ - FILLER_21_175 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 209440 196000 ) FS ;
+ - FILLER_21_179 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 213920 196000 ) FS ;
+ - FILLER_21_191 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 227360 196000 ) FS ;
+ - FILLER_21_193 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 229600 196000 ) FS ;
+ - FILLER_21_2 gf180mcu_fd_sc_mcu7t5v0__fillcap_8 + SOURCE DIST + PLACED ( 15680 196000 ) FS ;
+ - FILLER_21_207 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 245280 196000 ) FS ;
+ - FILLER_21_211 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 249760 196000 ) FS ;
+ - FILLER_21_215 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 254240 196000 ) FS ;
+ - FILLER_21_219 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 258720 196000 ) FS ;
+ - FILLER_21_222 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 262080 196000 ) FS ;
+ - FILLER_21_226 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 266560 196000 ) FS ;
+ - FILLER_21_228 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 268800 196000 ) FS ;
+ - FILLER_21_240 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 282240 196000 ) FS ;
+ - FILLER_21_271 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 316960 196000 ) FS ;
+ - FILLER_21_281 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 328160 196000 ) FS ;
+ - FILLER_21_283 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 330400 196000 ) FS ;
+ - FILLER_21_286 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 333760 196000 ) FS ;
+ - FILLER_21_316 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 367360 196000 ) FS ;
+ - FILLER_21_320 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 371840 196000 ) FS ;
+ - FILLER_21_327 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 379680 196000 ) FS ;
+ - FILLER_21_342 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 396480 196000 ) FS ;
+ - FILLER_21_348 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 403200 196000 ) FS ;
+ - FILLER_21_352 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 407680 196000 ) FS ;
+ - FILLER_21_354 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 409920 196000 ) FS ;
+ - FILLER_21_357 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 413280 196000 ) FS ;
+ - FILLER_21_362 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 418880 196000 ) FS ;
+ - FILLER_21_366 gf180mcu_fd_sc_mcu7t5v0__fillcap_8 + SOURCE DIST + PLACED ( 423360 196000 ) FS ;
+ - FILLER_21_374 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 432320 196000 ) FS ;
+ - FILLER_21_407 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 469280 196000 ) FS ;
+ - FILLER_21_411 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 473760 196000 ) FS ;
+ - FILLER_21_415 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 478240 196000 ) FS ;
+ - FILLER_21_425 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 489440 196000 ) FS ;
+ - FILLER_21_428 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 492800 196000 ) FS ;
+ - FILLER_21_439 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 505120 196000 ) FS ;
+ - FILLER_21_443 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 509600 196000 ) FS ;
+ - FILLER_21_447 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 514080 196000 ) FS ;
+ - FILLER_21_45 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 63840 196000 ) FS ;
+ - FILLER_21_461 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 529760 196000 ) FS ;
+ - FILLER_21_471 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 540960 196000 ) FS ;
+ - FILLER_21_475 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 545440 196000 ) FS ;
+ - FILLER_21_479 gf180mcu_fd_sc_mcu7t5v0__fillcap_16 + SOURCE DIST + PLACED ( 549920 196000 ) FS ;
+ - FILLER_21_495 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 567840 196000 ) FS ;
+ - FILLER_21_499 gf180mcu_fd_sc_mcu7t5v0__fillcap_8 + SOURCE DIST + PLACED ( 572320 196000 ) FS ;
+ - FILLER_21_507 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 581280 196000 ) FS ;
+ - FILLER_21_55 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 75040 196000 ) FS ;
+ - FILLER_21_70 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 91840 196000 ) FS ;
+ - FILLER_21_73 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 95200 196000 ) FS ;
+ - FILLER_21_77 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 99680 196000 ) FS ;
+ - FILLER_21_86 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 109760 196000 ) FS ;
+ - FILLER_21_96 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 120960 196000 ) FS ;
+ - FILLER_22_100 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 125440 203840 ) N ;
+ - FILLER_22_104 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 129920 203840 ) N ;
+ - FILLER_22_108 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 134400 203840 ) N ;
+ - FILLER_22_111 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 137760 203840 ) N ;
+ - FILLER_22_115 gf180mcu_fd_sc_mcu7t5v0__fillcap_32 + SOURCE DIST + PLACED ( 142240 203840 ) N ;
+ - FILLER_22_147 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 178080 203840 ) N ;
+ - FILLER_22_151 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 182560 203840 ) N ;
+ - FILLER_22_160 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 192640 203840 ) N ;
+ - FILLER_22_164 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 197120 203840 ) N ;
+ - FILLER_22_168 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 201600 203840 ) N ;
+ - FILLER_22_170 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 203840 203840 ) N ;
+ - FILLER_22_176 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 210560 203840 ) N ;
+ - FILLER_22_179 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 213920 203840 ) N ;
+ - FILLER_22_181 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 216160 203840 ) N ;
+ - FILLER_22_188 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 224000 203840 ) N ;
+ - FILLER_22_190 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 226240 203840 ) N ;
+ - FILLER_22_195 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 231840 203840 ) N ;
+ - FILLER_22_2 gf180mcu_fd_sc_mcu7t5v0__fillcap_32 + SOURCE DIST + PLACED ( 15680 203840 ) N ;
+ - FILLER_22_223 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 263200 203840 ) N ;
+ - FILLER_22_227 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 267680 203840 ) N ;
+ - FILLER_22_231 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 272160 203840 ) N ;
+ - FILLER_22_239 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 281120 203840 ) N ;
+ - FILLER_22_243 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 285600 203840 ) N ;
+ - FILLER_22_247 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 290080 203840 ) N ;
+ - FILLER_22_250 gf180mcu_fd_sc_mcu7t5v0__fillcap_16 + SOURCE DIST + PLACED ( 293440 203840 ) N ;
+ - FILLER_22_266 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 311360 203840 ) N ;
+ - FILLER_22_270 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 315840 203840 ) N ;
+ - FILLER_22_273 gf180mcu_fd_sc_mcu7t5v0__fillcap_32 + SOURCE DIST + PLACED ( 319200 203840 ) N ;
+ - FILLER_22_305 gf180mcu_fd_sc_mcu7t5v0__fillcap_8 + SOURCE DIST + PLACED ( 355040 203840 ) N ;
+ - FILLER_22_313 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 364000 203840 ) N ;
+ - FILLER_22_317 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 368480 203840 ) N ;
+ - FILLER_22_321 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 372960 203840 ) N ;
+ - FILLER_22_325 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 377440 203840 ) N ;
+ - FILLER_22_329 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 381920 203840 ) N ;
+ - FILLER_22_337 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 390880 203840 ) N ;
+ - FILLER_22_34 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 51520 203840 ) N ;
+ - FILLER_22_365 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 422240 203840 ) N ;
+ - FILLER_22_37 gf180mcu_fd_sc_mcu7t5v0__fillcap_8 + SOURCE DIST + PLACED ( 54880 203840 ) N ;
+ - FILLER_22_385 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 444640 203840 ) N ;
+ - FILLER_22_389 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 449120 203840 ) N ;
+ - FILLER_22_392 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 452480 203840 ) N ;
+ - FILLER_22_396 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 456960 203840 ) N ;
+ - FILLER_22_400 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 461440 203840 ) N ;
+ - FILLER_22_428 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 492800 203840 ) N ;
+ - FILLER_22_440 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 506240 203840 ) N ;
+ - FILLER_22_444 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 510720 203840 ) N ;
+ - FILLER_22_448 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 515200 203840 ) N ;
+ - FILLER_22_452 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 519680 203840 ) N ;
+ - FILLER_22_456 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 524160 203840 ) N ;
+ - FILLER_22_460 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 528640 203840 ) N ;
+ - FILLER_22_463 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 532000 203840 ) N ;
+ - FILLER_22_47 gf180mcu_fd_sc_mcu7t5v0__fillcap_8 + SOURCE DIST + PLACED ( 66080 203840 ) N ;
+ - FILLER_22_493 gf180mcu_fd_sc_mcu7t5v0__fillcap_16 + SOURCE DIST + PLACED ( 565600 203840 ) N ;
+ - FILLER_22_55 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 75040 203840 ) N ;
+ - FILLER_22_58 gf180mcu_fd_sc_mcu7t5v0__fillcap_8 + SOURCE DIST + PLACED ( 78400 203840 ) N ;
+ - FILLER_22_66 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 87360 203840 ) N ;
+ - FILLER_22_72 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 94080 203840 ) N ;
+ - FILLER_22_76 gf180mcu_fd_sc_mcu7t5v0__fillcap_8 + SOURCE DIST + PLACED ( 98560 203840 ) N ;
+ - FILLER_22_84 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 107520 203840 ) N ;
+ - FILLER_22_90 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 114240 203840 ) N ;
+ - FILLER_23_108 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 134400 211680 ) FS ;
+ - FILLER_23_139 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 169120 211680 ) FS ;
+ - FILLER_23_141 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 171360 211680 ) FS ;
+ - FILLER_23_144 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 174720 211680 ) FS ;
+ - FILLER_23_150 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 181440 211680 ) FS ;
+ - FILLER_23_160 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 192640 211680 ) FS ;
+ - FILLER_23_164 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 197120 211680 ) FS ;
+ - FILLER_23_167 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 200480 211680 ) FS ;
+ - FILLER_23_169 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 202720 211680 ) FS ;
+ - FILLER_23_176 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 210560 211680 ) FS ;
+ - FILLER_23_185 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 220640 211680 ) FS ;
+ - FILLER_23_189 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 225120 211680 ) FS ;
+ - FILLER_23_2 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 15680 211680 ) FS ;
+ - FILLER_23_202 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 239680 211680 ) FS ;
+ - FILLER_23_209 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 247520 211680 ) FS ;
+ - FILLER_23_215 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 254240 211680 ) FS ;
+ - FILLER_23_218 gf180mcu_fd_sc_mcu7t5v0__fillcap_8 + SOURCE DIST + PLACED ( 257600 211680 ) FS ;
+ - FILLER_23_226 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 266560 211680 ) FS ;
+ - FILLER_23_23 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 39200 211680 ) FS ;
+ - FILLER_23_235 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 276640 211680 ) FS ;
+ - FILLER_23_239 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 281120 211680 ) FS ;
+ - FILLER_23_251 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 294560 211680 ) FS ;
+ - FILLER_23_255 gf180mcu_fd_sc_mcu7t5v0__fillcap_16 + SOURCE DIST + PLACED ( 299040 211680 ) FS ;
+ - FILLER_23_27 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 43680 211680 ) FS ;
+ - FILLER_23_271 gf180mcu_fd_sc_mcu7t5v0__fillcap_8 + SOURCE DIST + PLACED ( 316960 211680 ) FS ;
+ - FILLER_23_281 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 328160 211680 ) FS ;
+ - FILLER_23_283 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 330400 211680 ) FS ;
+ - FILLER_23_286 gf180mcu_fd_sc_mcu7t5v0__fillcap_16 + SOURCE DIST + PLACED ( 333760 211680 ) FS ;
+ - FILLER_23_331 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 384160 211680 ) FS ;
+ - FILLER_23_335 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 388640 211680 ) FS ;
+ - FILLER_23_339 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 393120 211680 ) FS ;
+ - FILLER_23_349 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 404320 211680 ) FS ;
+ - FILLER_23_353 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 408800 211680 ) FS ;
+ - FILLER_23_357 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 413280 211680 ) FS ;
+ - FILLER_23_366 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 423360 211680 ) FS ;
+ - FILLER_23_368 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 425600 211680 ) FS ;
+ - FILLER_23_37 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 54880 211680 ) FS ;
+ - FILLER_23_398 gf180mcu_fd_sc_mcu7t5v0__fillcap_16 + SOURCE DIST + PLACED ( 459200 211680 ) FS ;
+ - FILLER_23_41 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 59360 211680 ) FS ;
+ - FILLER_23_414 gf180mcu_fd_sc_mcu7t5v0__fillcap_8 + SOURCE DIST + PLACED ( 477120 211680 ) FS ;
+ - FILLER_23_422 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 486080 211680 ) FS ;
+ - FILLER_23_425 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 489440 211680 ) FS ;
+ - FILLER_23_428 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 492800 211680 ) FS ;
+ - FILLER_23_437 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 502880 211680 ) FS ;
+ - FILLER_23_441 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 507360 211680 ) FS ;
+ - FILLER_23_444 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 510720 211680 ) FS ;
+ - FILLER_23_45 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 63840 211680 ) FS ;
+ - FILLER_23_47 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 66080 211680 ) FS ;
+ - FILLER_23_475 gf180mcu_fd_sc_mcu7t5v0__fillcap_16 + SOURCE DIST + PLACED ( 545440 211680 ) FS ;
+ - FILLER_23_491 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 563360 211680 ) FS ;
+ - FILLER_23_495 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 567840 211680 ) FS ;
+ - FILLER_23_499 gf180mcu_fd_sc_mcu7t5v0__fillcap_8 + SOURCE DIST + PLACED ( 572320 211680 ) FS ;
+ - FILLER_23_507 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 581280 211680 ) FS ;
+ - FILLER_23_56 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 76160 211680 ) FS ;
+ - FILLER_23_64 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 85120 211680 ) FS ;
+ - FILLER_23_68 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 89600 211680 ) FS ;
+ - FILLER_23_7 gf180mcu_fd_sc_mcu7t5v0__fillcap_16 + SOURCE DIST + PLACED ( 21280 211680 ) FS ;
+ - FILLER_23_70 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 91840 211680 ) FS ;
+ - FILLER_23_73 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 95200 211680 ) FS ;
+ - FILLER_23_77 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 99680 211680 ) FS ;
+ - FILLER_24_101 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 126560 219520 ) N ;
+ - FILLER_24_105 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 131040 219520 ) N ;
+ - FILLER_24_108 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 134400 219520 ) N ;
+ - FILLER_24_115 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 142240 219520 ) N ;
+ - FILLER_24_119 gf180mcu_fd_sc_mcu7t5v0__fillcap_16 + SOURCE DIST + PLACED ( 146720 219520 ) N ;
+ - FILLER_24_135 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 164640 219520 ) N ;
+ - FILLER_24_145 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 175840 219520 ) N ;
+ - FILLER_24_155 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 187040 219520 ) N ;
+ - FILLER_24_165 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 198240 219520 ) N ;
+ - FILLER_24_169 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 202720 219520 ) N ;
+ - FILLER_24_176 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 210560 219520 ) N ;
+ - FILLER_24_179 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 213920 219520 ) N ;
+ - FILLER_24_181 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 216160 219520 ) N ;
+ - FILLER_24_184 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 219520 219520 ) N ;
+ - FILLER_24_194 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 230720 219520 ) N ;
+ - FILLER_24_2 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 15680 219520 ) N ;
+ - FILLER_24_202 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 239680 219520 ) N ;
+ - FILLER_24_210 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 248640 219520 ) N ;
+ - FILLER_24_216 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 255360 219520 ) N ;
+ - FILLER_24_247 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 290080 219520 ) N ;
+ - FILLER_24_250 gf180mcu_fd_sc_mcu7t5v0__fillcap_8 + SOURCE DIST + PLACED ( 293440 219520 ) N ;
+ - FILLER_24_258 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 302400 219520 ) N ;
+ - FILLER_24_262 gf180mcu_fd_sc_mcu7t5v0__fillcap_8 + SOURCE DIST + PLACED ( 306880 219520 ) N ;
+ - FILLER_24_276 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 322560 219520 ) N ;
+ - FILLER_24_280 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 327040 219520 ) N ;
+ - FILLER_24_310 gf180mcu_fd_sc_mcu7t5v0__fillcap_8 + SOURCE DIST + PLACED ( 360640 219520 ) N ;
+ - FILLER_24_318 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 369600 219520 ) N ;
+ - FILLER_24_32 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 49280 219520 ) N ;
+ - FILLER_24_321 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 372960 219520 ) N ;
+ - FILLER_24_328 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 380800 219520 ) N ;
+ - FILLER_24_34 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 51520 219520 ) N ;
+ - FILLER_24_342 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 396480 219520 ) N ;
+ - FILLER_24_350 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 405440 219520 ) N ;
+ - FILLER_24_354 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 409920 219520 ) N ;
+ - FILLER_24_369 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 426720 219520 ) N ;
+ - FILLER_24_37 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 54880 219520 ) N ;
+ - FILLER_24_379 gf180mcu_fd_sc_mcu7t5v0__fillcap_8 + SOURCE DIST + PLACED ( 437920 219520 ) N ;
+ - FILLER_24_387 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 446880 219520 ) N ;
+ - FILLER_24_389 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 449120 219520 ) N ;
+ - FILLER_24_392 gf180mcu_fd_sc_mcu7t5v0__fillcap_8 + SOURCE DIST + PLACED ( 452480 219520 ) N ;
+ - FILLER_24_400 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 461440 219520 ) N ;
+ - FILLER_24_404 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 465920 219520 ) N ;
+ - FILLER_24_415 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 478240 219520 ) N ;
+ - FILLER_24_419 gf180mcu_fd_sc_mcu7t5v0__fillcap_8 + SOURCE DIST + PLACED ( 482720 219520 ) N ;
+ - FILLER_24_427 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 491680 219520 ) N ;
+ - FILLER_24_437 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 502880 219520 ) N ;
+ - FILLER_24_44 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 62720 219520 ) N ;
+ - FILLER_24_441 gf180mcu_fd_sc_mcu7t5v0__fillcap_16 + SOURCE DIST + PLACED ( 507360 219520 ) N ;
+ - FILLER_24_457 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 525280 219520 ) N ;
+ - FILLER_24_463 gf180mcu_fd_sc_mcu7t5v0__fillcap_32 + SOURCE DIST + PLACED ( 532000 219520 ) N ;
+ - FILLER_24_495 gf180mcu_fd_sc_mcu7t5v0__fillcap_8 + SOURCE DIST + PLACED ( 567840 219520 ) N ;
+ - FILLER_24_503 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 576800 219520 ) N ;
+ - FILLER_24_507 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 581280 219520 ) N ;
+ - FILLER_24_75 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 97440 219520 ) N ;
+ - FILLER_24_85 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 108640 219520 ) N ;
+ - FILLER_24_93 gf180mcu_fd_sc_mcu7t5v0__fillcap_8 + SOURCE DIST + PLACED ( 117600 219520 ) N ;
+ - FILLER_25_106 gf180mcu_fd_sc_mcu7t5v0__fillcap_32 + SOURCE DIST + PLACED ( 132160 227360 ) FS ;
+ - FILLER_25_138 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 168000 227360 ) FS ;
+ - FILLER_25_144 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 174720 227360 ) FS ;
+ - FILLER_25_148 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 179200 227360 ) FS ;
+ - FILLER_25_158 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 190400 227360 ) FS ;
+ - FILLER_25_164 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 197120 227360 ) FS ;
+ - FILLER_25_168 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 201600 227360 ) FS ;
+ - FILLER_25_170 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 203840 227360 ) FS ;
+ - FILLER_25_176 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 210560 227360 ) FS ;
+ - FILLER_25_183 gf180mcu_fd_sc_mcu7t5v0__fillcap_8 + SOURCE DIST + PLACED ( 218400 227360 ) FS ;
+ - FILLER_25_191 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 227360 227360 ) FS ;
+ - FILLER_25_193 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 229600 227360 ) FS ;
+ - FILLER_25_196 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 232960 227360 ) FS ;
+ - FILLER_25_2 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 15680 227360 ) FS ;
+ - FILLER_25_200 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 237440 227360 ) FS ;
+ - FILLER_25_204 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 241920 227360 ) FS ;
+ - FILLER_25_208 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 246400 227360 ) FS ;
+ - FILLER_25_212 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 250880 227360 ) FS ;
+ - FILLER_25_215 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 254240 227360 ) FS ;
+ - FILLER_25_222 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 262080 227360 ) FS ;
+ - FILLER_25_224 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 264320 227360 ) FS ;
+ - FILLER_25_23 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 39200 227360 ) FS ;
+ - FILLER_25_233 gf180mcu_fd_sc_mcu7t5v0__fillcap_16 + SOURCE DIST + PLACED ( 274400 227360 ) FS ;
+ - FILLER_25_249 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 292320 227360 ) FS ;
+ - FILLER_25_252 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 295680 227360 ) FS ;
+ - FILLER_25_283 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 330400 227360 ) FS ;
+ - FILLER_25_286 gf180mcu_fd_sc_mcu7t5v0__fillcap_16 + SOURCE DIST + PLACED ( 333760 227360 ) FS ;
+ - FILLER_25_302 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 351680 227360 ) FS ;
+ - FILLER_25_314 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 365120 227360 ) FS ;
+ - FILLER_25_318 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 369600 227360 ) FS ;
+ - FILLER_25_322 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 374080 227360 ) FS ;
+ - FILLER_25_324 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 376320 227360 ) FS ;
+ - FILLER_25_35 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 52640 227360 ) FS ;
+ - FILLER_25_354 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 409920 227360 ) FS ;
+ - FILLER_25_357 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 413280 227360 ) FS ;
+ - FILLER_25_360 gf180mcu_fd_sc_mcu7t5v0__fillcap_16 + SOURCE DIST + PLACED ( 416640 227360 ) FS ;
+ - FILLER_25_376 gf180mcu_fd_sc_mcu7t5v0__fillcap_8 + SOURCE DIST + PLACED ( 434560 227360 ) FS ;
+ - FILLER_25_39 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 57120 227360 ) FS ;
+ - FILLER_25_413 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 476000 227360 ) FS ;
+ - FILLER_25_425 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 489440 227360 ) FS ;
+ - FILLER_25_428 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 492800 227360 ) FS ;
+ - FILLER_25_43 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 61600 227360 ) FS ;
+ - FILLER_25_458 gf180mcu_fd_sc_mcu7t5v0__fillcap_8 + SOURCE DIST + PLACED ( 526400 227360 ) FS ;
+ - FILLER_25_466 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 535360 227360 ) FS ;
+ - FILLER_25_47 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 66080 227360 ) FS ;
+ - FILLER_25_477 gf180mcu_fd_sc_mcu7t5v0__fillcap_16 + SOURCE DIST + PLACED ( 547680 227360 ) FS ;
+ - FILLER_25_493 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 565600 227360 ) FS ;
+ - FILLER_25_499 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 572320 227360 ) FS ;
+ - FILLER_25_503 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 576800 227360 ) FS ;
+ - FILLER_25_508 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 582400 227360 ) FS ;
+ - FILLER_25_56 gf180mcu_fd_sc_mcu7t5v0__fillcap_8 + SOURCE DIST + PLACED ( 76160 227360 ) FS ;
+ - FILLER_25_64 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 85120 227360 ) FS ;
+ - FILLER_25_7 gf180mcu_fd_sc_mcu7t5v0__fillcap_16 + SOURCE DIST + PLACED ( 21280 227360 ) FS ;
+ - FILLER_25_70 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 91840 227360 ) FS ;
+ - FILLER_25_73 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 95200 227360 ) FS ;
+ - FILLER_26_102 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 127680 235200 ) N ;
+ - FILLER_26_108 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 134400 235200 ) N ;
+ - FILLER_26_112 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 138880 235200 ) N ;
+ - FILLER_26_114 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 141120 235200 ) N ;
+ - FILLER_26_117 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 144480 235200 ) N ;
+ - FILLER_26_148 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 179200 235200 ) N ;
+ - FILLER_26_150 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 181440 235200 ) N ;
+ - FILLER_26_153 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 184800 235200 ) N ;
+ - FILLER_26_161 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 193760 235200 ) N ;
+ - FILLER_26_169 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 202720 235200 ) N ;
+ - FILLER_26_175 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 209440 235200 ) N ;
+ - FILLER_26_179 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 213920 235200 ) N ;
+ - FILLER_26_18 gf180mcu_fd_sc_mcu7t5v0__fillcap_8 + SOURCE DIST + PLACED ( 33600 235200 ) N ;
+ - FILLER_26_182 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 217280 235200 ) N ;
+ - FILLER_26_186 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 221760 235200 ) N ;
+ - FILLER_26_188 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 224000 235200 ) N ;
+ - FILLER_26_194 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 230720 235200 ) N ;
+ - FILLER_26_198 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 235200 235200 ) N ;
+ - FILLER_26_2 gf180mcu_fd_sc_mcu7t5v0__fillcap_16 + SOURCE DIST + PLACED ( 15680 235200 ) N ;
+ - FILLER_26_202 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 239680 235200 ) N ;
+ - FILLER_26_233 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 274400 235200 ) N ;
+ - FILLER_26_237 gf180mcu_fd_sc_mcu7t5v0__fillcap_8 + SOURCE DIST + PLACED ( 278880 235200 ) N ;
+ - FILLER_26_245 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 287840 235200 ) N ;
+ - FILLER_26_247 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 290080 235200 ) N ;
+ - FILLER_26_250 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 293440 235200 ) N ;
+ - FILLER_26_26 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 42560 235200 ) N ;
+ - FILLER_26_260 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 304640 235200 ) N ;
+ - FILLER_26_270 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 315840 235200 ) N ;
+ - FILLER_26_278 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 324800 235200 ) N ;
+ - FILLER_26_309 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 359520 235200 ) N ;
+ - FILLER_26_311 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 361760 235200 ) N ;
+ - FILLER_26_317 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 368480 235200 ) N ;
+ - FILLER_26_321 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 372960 235200 ) N ;
+ - FILLER_26_34 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 51520 235200 ) N ;
+ - FILLER_26_359 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 415520 235200 ) N ;
+ - FILLER_26_363 gf180mcu_fd_sc_mcu7t5v0__fillcap_16 + SOURCE DIST + PLACED ( 420000 235200 ) N ;
+ - FILLER_26_37 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 54880 235200 ) N ;
+ - FILLER_26_379 gf180mcu_fd_sc_mcu7t5v0__fillcap_8 + SOURCE DIST + PLACED ( 437920 235200 ) N ;
+ - FILLER_26_387 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 446880 235200 ) N ;
+ - FILLER_26_389 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 449120 235200 ) N ;
+ - FILLER_26_392 gf180mcu_fd_sc_mcu7t5v0__fillcap_16 + SOURCE DIST + PLACED ( 452480 235200 ) N ;
+ - FILLER_26_408 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 470400 235200 ) N ;
+ - FILLER_26_412 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 474880 235200 ) N ;
+ - FILLER_26_415 gf180mcu_fd_sc_mcu7t5v0__fillcap_8 + SOURCE DIST + PLACED ( 478240 235200 ) N ;
+ - FILLER_26_423 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 487200 235200 ) N ;
+ - FILLER_26_429 gf180mcu_fd_sc_mcu7t5v0__fillcap_32 + SOURCE DIST + PLACED ( 493920 235200 ) N ;
+ - FILLER_26_46 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 64960 235200 ) N ;
+ - FILLER_26_463 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 532000 235200 ) N ;
+ - FILLER_26_467 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 536480 235200 ) N ;
+ - FILLER_26_469 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 538720 235200 ) N ;
+ - FILLER_26_481 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 552160 235200 ) N ;
+ - FILLER_26_489 gf180mcu_fd_sc_mcu7t5v0__fillcap_16 + SOURCE DIST + PLACED ( 561120 235200 ) N ;
+ - FILLER_26_50 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 69440 235200 ) N ;
+ - FILLER_26_505 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 579040 235200 ) N ;
+ - FILLER_26_52 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 71680 235200 ) N ;
+ - FILLER_26_55 gf180mcu_fd_sc_mcu7t5v0__fillcap_16 + SOURCE DIST + PLACED ( 75040 235200 ) N ;
+ - FILLER_26_71 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 92960 235200 ) N ;
+ - FILLER_26_82 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 105280 235200 ) N ;
+ - FILLER_26_88 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 112000 235200 ) N ;
+ - FILLER_26_92 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 116480 235200 ) N ;
+ - FILLER_27_114 gf180mcu_fd_sc_mcu7t5v0__fillcap_16 + SOURCE DIST + PLACED ( 141120 243040 ) FS ;
+ - FILLER_27_130 gf180mcu_fd_sc_mcu7t5v0__fillcap_8 + SOURCE DIST + PLACED ( 159040 243040 ) FS ;
+ - FILLER_27_138 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 168000 243040 ) FS ;
+ - FILLER_27_144 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 174720 243040 ) FS ;
+ - FILLER_27_148 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 179200 243040 ) FS ;
+ - FILLER_27_158 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 190400 243040 ) FS ;
+ - FILLER_27_166 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 199360 243040 ) FS ;
+ - FILLER_27_176 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 210560 243040 ) FS ;
+ - FILLER_27_188 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 224000 243040 ) FS ;
+ - FILLER_27_190 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 226240 243040 ) FS ;
+ - FILLER_27_197 gf180mcu_fd_sc_mcu7t5v0__fillcap_8 + SOURCE DIST + PLACED ( 234080 243040 ) FS ;
+ - FILLER_27_2 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 15680 243040 ) FS ;
+ - FILLER_27_205 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 243040 243040 ) FS ;
+ - FILLER_27_209 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 247520 243040 ) FS ;
+ - FILLER_27_212 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 250880 243040 ) FS ;
+ - FILLER_27_215 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 254240 243040 ) FS ;
+ - FILLER_27_224 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 264320 243040 ) FS ;
+ - FILLER_27_236 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 277760 243040 ) FS ;
+ - FILLER_27_238 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 280000 243040 ) FS ;
+ - FILLER_27_241 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 283360 243040 ) FS ;
+ - FILLER_27_245 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 287840 243040 ) FS ;
+ - FILLER_27_255 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 299040 243040 ) FS ;
+ - FILLER_27_263 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 308000 243040 ) FS ;
+ - FILLER_27_267 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 312480 243040 ) FS ;
+ - FILLER_27_269 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 314720 243040 ) FS ;
+ - FILLER_27_272 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 318080 243040 ) FS ;
+ - FILLER_27_276 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 322560 243040 ) FS ;
+ - FILLER_27_280 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 327040 243040 ) FS ;
+ - FILLER_27_286 gf180mcu_fd_sc_mcu7t5v0__fillcap_32 + SOURCE DIST + PLACED ( 333760 243040 ) FS ;
+ - FILLER_27_318 gf180mcu_fd_sc_mcu7t5v0__fillcap_8 + SOURCE DIST + PLACED ( 369600 243040 ) FS ;
+ - FILLER_27_32 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 49280 243040 ) FS ;
+ - FILLER_27_332 gf180mcu_fd_sc_mcu7t5v0__fillcap_16 + SOURCE DIST + PLACED ( 385280 243040 ) FS ;
+ - FILLER_27_348 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 403200 243040 ) FS ;
+ - FILLER_27_354 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 409920 243040 ) FS ;
+ - FILLER_27_357 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 413280 243040 ) FS ;
+ - FILLER_27_359 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 415520 243040 ) FS ;
+ - FILLER_27_389 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 449120 243040 ) FS ;
+ - FILLER_27_393 gf180mcu_fd_sc_mcu7t5v0__fillcap_16 + SOURCE DIST + PLACED ( 453600 243040 ) FS ;
+ - FILLER_27_409 gf180mcu_fd_sc_mcu7t5v0__fillcap_8 + SOURCE DIST + PLACED ( 471520 243040 ) FS ;
+ - FILLER_27_417 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 480480 243040 ) FS ;
+ - FILLER_27_42 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 60480 243040 ) FS ;
+ - FILLER_27_421 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 484960 243040 ) FS ;
+ - FILLER_27_424 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 488320 243040 ) FS ;
+ - FILLER_27_428 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 492800 243040 ) FS ;
+ - FILLER_27_431 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 496160 243040 ) FS ;
+ - FILLER_27_433 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 498400 243040 ) FS ;
+ - FILLER_27_436 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 501760 243040 ) FS ;
+ - FILLER_27_44 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 62720 243040 ) FS ;
+ - FILLER_27_467 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 536480 243040 ) FS ;
+ - FILLER_27_471 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 540960 243040 ) FS ;
+ - FILLER_27_479 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 549920 243040 ) FS ;
+ - FILLER_27_485 gf180mcu_fd_sc_mcu7t5v0__fillcap_8 + SOURCE DIST + PLACED ( 556640 243040 ) FS ;
+ - FILLER_27_493 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 565600 243040 ) FS ;
+ - FILLER_27_499 gf180mcu_fd_sc_mcu7t5v0__fillcap_8 + SOURCE DIST + PLACED ( 572320 243040 ) FS ;
+ - FILLER_27_507 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 581280 243040 ) FS ;
+ - FILLER_27_53 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 72800 243040 ) FS ;
+ - FILLER_27_57 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 77280 243040 ) FS ;
+ - FILLER_27_62 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 82880 243040 ) FS ;
+ - FILLER_27_70 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 91840 243040 ) FS ;
+ - FILLER_27_73 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 95200 243040 ) FS ;
+ - FILLER_28_103 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 128800 250880 ) N ;
+ - FILLER_28_105 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 131040 250880 ) N ;
+ - FILLER_28_108 gf180mcu_fd_sc_mcu7t5v0__fillcap_8 + SOURCE DIST + PLACED ( 134400 250880 ) N ;
+ - FILLER_28_118 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 145600 250880 ) N ;
+ - FILLER_28_149 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 180320 250880 ) N ;
+ - FILLER_28_153 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 184800 250880 ) N ;
+ - FILLER_28_163 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 196000 250880 ) N ;
+ - FILLER_28_173 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 207200 250880 ) N ;
+ - FILLER_28_179 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 213920 250880 ) N ;
+ - FILLER_28_188 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 224000 250880 ) N ;
+ - FILLER_28_192 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 228480 250880 ) N ;
+ - FILLER_28_2 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 15680 250880 ) N ;
+ - FILLER_28_202 gf180mcu_fd_sc_mcu7t5v0__fillcap_8 + SOURCE DIST + PLACED ( 239680 250880 ) N ;
+ - FILLER_28_210 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 248640 250880 ) N ;
+ - FILLER_28_214 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 253120 250880 ) N ;
+ - FILLER_28_23 gf180mcu_fd_sc_mcu7t5v0__fillcap_8 + SOURCE DIST + PLACED ( 39200 250880 ) N ;
+ - FILLER_28_245 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 287840 250880 ) N ;
+ - FILLER_28_247 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 290080 250880 ) N ;
+ - FILLER_28_250 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 293440 250880 ) N ;
+ - FILLER_28_252 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 295680 250880 ) N ;
+ - FILLER_28_261 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 305760 250880 ) N ;
+ - FILLER_28_265 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 310240 250880 ) N ;
+ - FILLER_28_273 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 319200 250880 ) N ;
+ - FILLER_28_277 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 323680 250880 ) N ;
+ - FILLER_28_281 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 328160 250880 ) N ;
+ - FILLER_28_291 gf180mcu_fd_sc_mcu7t5v0__fillcap_8 + SOURCE DIST + PLACED ( 339360 250880 ) N ;
+ - FILLER_28_299 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 348320 250880 ) N ;
+ - FILLER_28_303 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 352800 250880 ) N ;
+ - FILLER_28_305 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 355040 250880 ) N ;
+ - FILLER_28_31 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 48160 250880 ) N ;
+ - FILLER_28_318 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 369600 250880 ) N ;
+ - FILLER_28_321 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 372960 250880 ) N ;
+ - FILLER_28_324 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 376320 250880 ) N ;
+ - FILLER_28_328 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 380800 250880 ) N ;
+ - FILLER_28_330 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 383040 250880 ) N ;
+ - FILLER_28_34 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 51520 250880 ) N ;
+ - FILLER_28_360 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 416640 250880 ) N ;
+ - FILLER_28_364 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 421120 250880 ) N ;
+ - FILLER_28_368 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 425600 250880 ) N ;
+ - FILLER_28_37 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 54880 250880 ) N ;
+ - FILLER_28_370 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 427840 250880 ) N ;
+ - FILLER_28_373 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 431200 250880 ) N ;
+ - FILLER_28_377 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 435680 250880 ) N ;
+ - FILLER_28_387 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 446880 250880 ) N ;
+ - FILLER_28_389 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 449120 250880 ) N ;
+ - FILLER_28_392 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 452480 250880 ) N ;
+ - FILLER_28_422 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 486080 250880 ) N ;
+ - FILLER_28_453 gf180mcu_fd_sc_mcu7t5v0__fillcap_8 + SOURCE DIST + PLACED ( 520800 250880 ) N ;
+ - FILLER_28_463 gf180mcu_fd_sc_mcu7t5v0__fillcap_32 + SOURCE DIST + PLACED ( 532000 250880 ) N ;
+ - FILLER_28_495 gf180mcu_fd_sc_mcu7t5v0__fillcap_8 + SOURCE DIST + PLACED ( 567840 250880 ) N ;
+ - FILLER_28_503 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 576800 250880 ) N ;
+ - FILLER_28_507 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 581280 250880 ) N ;
+ - FILLER_28_67 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 88480 250880 ) N ;
+ - FILLER_28_7 gf180mcu_fd_sc_mcu7t5v0__fillcap_16 + SOURCE DIST + PLACED ( 21280 250880 ) N ;
+ - FILLER_28_81 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 104160 250880 ) N ;
+ - FILLER_28_85 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 108640 250880 ) N ;
+ - FILLER_28_95 gf180mcu_fd_sc_mcu7t5v0__fillcap_8 + SOURCE DIST + PLACED ( 119840 250880 ) N ;
+ - FILLER_29_121 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 148960 258720 ) FS ;
+ - FILLER_29_125 gf180mcu_fd_sc_mcu7t5v0__fillcap_8 + SOURCE DIST + PLACED ( 153440 258720 ) FS ;
+ - FILLER_29_133 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 162400 258720 ) FS ;
+ - FILLER_29_137 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 166880 258720 ) FS ;
+ - FILLER_29_141 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 171360 258720 ) FS ;
+ - FILLER_29_144 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 174720 258720 ) FS ;
+ - FILLER_29_174 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 208320 258720 ) FS ;
+ - FILLER_29_176 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 210560 258720 ) FS ;
+ - FILLER_29_179 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 213920 258720 ) FS ;
+ - FILLER_29_2 gf180mcu_fd_sc_mcu7t5v0__fillcap_32 + SOURCE DIST + PLACED ( 15680 258720 ) FS ;
+ - FILLER_29_212 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 250880 258720 ) FS ;
+ - FILLER_29_215 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 254240 258720 ) FS ;
+ - FILLER_29_218 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 257600 258720 ) FS ;
+ - FILLER_29_222 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 262080 258720 ) FS ;
+ - FILLER_29_224 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 264320 258720 ) FS ;
+ - FILLER_29_233 gf180mcu_fd_sc_mcu7t5v0__fillcap_8 + SOURCE DIST + PLACED ( 274400 258720 ) FS ;
+ - FILLER_29_241 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 283360 258720 ) FS ;
+ - FILLER_29_244 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 286720 258720 ) FS ;
+ - FILLER_29_275 gf180mcu_fd_sc_mcu7t5v0__fillcap_8 + SOURCE DIST + PLACED ( 321440 258720 ) FS ;
+ - FILLER_29_283 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 330400 258720 ) FS ;
+ - FILLER_29_286 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 333760 258720 ) FS ;
+ - FILLER_29_316 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 367360 258720 ) FS ;
+ - FILLER_29_34 gf180mcu_fd_sc_mcu7t5v0__fillcap_8 + SOURCE DIST + PLACED ( 51520 258720 ) FS ;
+ - FILLER_29_347 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 402080 258720 ) FS ;
+ - FILLER_29_351 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 406560 258720 ) FS ;
+ - FILLER_29_357 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 413280 258720 ) FS ;
+ - FILLER_29_387 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 446880 258720 ) FS ;
+ - FILLER_29_393 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 453600 258720 ) FS ;
+ - FILLER_29_397 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 458080 258720 ) FS ;
+ - FILLER_29_42 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 60480 258720 ) FS ;
+ - FILLER_29_425 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 489440 258720 ) FS ;
+ - FILLER_29_428 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 492800 258720 ) FS ;
+ - FILLER_29_431 gf180mcu_fd_sc_mcu7t5v0__fillcap_16 + SOURCE DIST + PLACED ( 496160 258720 ) FS ;
+ - FILLER_29_44 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 62720 258720 ) FS ;
+ - FILLER_29_449 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 516320 258720 ) FS ;
+ - FILLER_29_480 gf180mcu_fd_sc_mcu7t5v0__fillcap_16 + SOURCE DIST + PLACED ( 551040 258720 ) FS ;
+ - FILLER_29_496 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 568960 258720 ) FS ;
+ - FILLER_29_499 gf180mcu_fd_sc_mcu7t5v0__fillcap_8 + SOURCE DIST + PLACED ( 572320 258720 ) FS ;
+ - FILLER_29_507 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 581280 258720 ) FS ;
+ - FILLER_29_51 gf180mcu_fd_sc_mcu7t5v0__fillcap_16 + SOURCE DIST + PLACED ( 70560 258720 ) FS ;
+ - FILLER_29_69 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 90720 258720 ) FS ;
+ - FILLER_29_73 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 95200 258720 ) FS ;
+ - FILLER_29_80 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 103040 258720 ) FS ;
+ - FILLER_29_88 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 112000 258720 ) FS ;
+ - FILLER_2_101 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 126560 47040 ) N ;
+ - FILLER_2_105 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 131040 47040 ) N ;
+ - FILLER_2_108 gf180mcu_fd_sc_mcu7t5v0__fillcap_64 + SOURCE DIST + PLACED ( 134400 47040 ) N ;
+ - FILLER_2_172 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 206080 47040 ) N ;
+ - FILLER_2_176 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 210560 47040 ) N ;
+ - FILLER_2_179 gf180mcu_fd_sc_mcu7t5v0__fillcap_32 + SOURCE DIST + PLACED ( 213920 47040 ) N ;
+ - FILLER_2_19 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 34720 47040 ) N ;
+ - FILLER_2_2 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 15680 47040 ) N ;
+ - FILLER_2_211 gf180mcu_fd_sc_mcu7t5v0__fillcap_16 + SOURCE DIST + PLACED ( 249760 47040 ) N ;
+ - FILLER_2_227 gf180mcu_fd_sc_mcu7t5v0__fillcap_8 + SOURCE DIST + PLACED ( 267680 47040 ) N ;
+ - FILLER_2_23 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 39200 47040 ) N ;
+ - FILLER_2_235 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 276640 47040 ) N ;
+ - FILLER_2_239 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 281120 47040 ) N ;
+ - FILLER_2_243 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 285600 47040 ) N ;
+ - FILLER_2_247 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 290080 47040 ) N ;
+ - FILLER_2_250 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 293440 47040 ) N ;
+ - FILLER_2_259 gf180mcu_fd_sc_mcu7t5v0__fillcap_32 + SOURCE DIST + PLACED ( 303520 47040 ) N ;
+ - FILLER_2_27 gf180mcu_fd_sc_mcu7t5v0__fillcap_8 + SOURCE DIST + PLACED ( 43680 47040 ) N ;
+ - FILLER_2_291 gf180mcu_fd_sc_mcu7t5v0__fillcap_16 + SOURCE DIST + PLACED ( 339360 47040 ) N ;
+ - FILLER_2_307 gf180mcu_fd_sc_mcu7t5v0__fillcap_8 + SOURCE DIST + PLACED ( 357280 47040 ) N ;
+ - FILLER_2_315 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 366240 47040 ) N ;
+ - FILLER_2_321 gf180mcu_fd_sc_mcu7t5v0__fillcap_64 + SOURCE DIST + PLACED ( 372960 47040 ) N ;
+ - FILLER_2_37 gf180mcu_fd_sc_mcu7t5v0__fillcap_64 + SOURCE DIST + PLACED ( 54880 47040 ) N ;
+ - FILLER_2_385 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 444640 47040 ) N ;
+ - FILLER_2_389 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 449120 47040 ) N ;
+ - FILLER_2_392 gf180mcu_fd_sc_mcu7t5v0__fillcap_32 + SOURCE DIST + PLACED ( 452480 47040 ) N ;
+ - FILLER_2_424 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 488320 47040 ) N ;
+ - FILLER_2_428 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 492800 47040 ) N ;
+ - FILLER_2_432 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 497280 47040 ) N ;
+ - FILLER_2_442 gf180mcu_fd_sc_mcu7t5v0__fillcap_16 + SOURCE DIST + PLACED ( 508480 47040 ) N ;
+ - FILLER_2_458 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 526400 47040 ) N ;
+ - FILLER_2_460 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 528640 47040 ) N ;
+ - FILLER_2_463 gf180mcu_fd_sc_mcu7t5v0__fillcap_32 + SOURCE DIST + PLACED ( 532000 47040 ) N ;
+ - FILLER_2_495 gf180mcu_fd_sc_mcu7t5v0__fillcap_8 + SOURCE DIST + PLACED ( 567840 47040 ) N ;
+ - FILLER_2_503 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 576800 47040 ) N ;
+ - FILLER_2_507 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 581280 47040 ) N ;
+ - FILLER_2_7 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 21280 47040 ) N ;
+ - FILLER_30_102 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 127680 266560 ) N ;
+ - FILLER_30_108 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 134400 266560 ) N ;
+ - FILLER_30_138 gf180mcu_fd_sc_mcu7t5v0__fillcap_32 + SOURCE DIST + PLACED ( 168000 266560 ) N ;
+ - FILLER_30_170 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 203840 266560 ) N ;
+ - FILLER_30_174 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 208320 266560 ) N ;
+ - FILLER_30_176 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 210560 266560 ) N ;
+ - FILLER_30_179 gf180mcu_fd_sc_mcu7t5v0__fillcap_32 + SOURCE DIST + PLACED ( 213920 266560 ) N ;
+ - FILLER_30_2 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 15680 266560 ) N ;
+ - FILLER_30_211 gf180mcu_fd_sc_mcu7t5v0__fillcap_16 + SOURCE DIST + PLACED ( 249760 266560 ) N ;
+ - FILLER_30_227 gf180mcu_fd_sc_mcu7t5v0__fillcap_8 + SOURCE DIST + PLACED ( 267680 266560 ) N ;
+ - FILLER_30_23 gf180mcu_fd_sc_mcu7t5v0__fillcap_8 + SOURCE DIST + PLACED ( 39200 266560 ) N ;
+ - FILLER_30_235 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 276640 266560 ) N ;
+ - FILLER_30_239 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 281120 266560 ) N ;
+ - FILLER_30_247 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 290080 266560 ) N ;
+ - FILLER_30_250 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 293440 266560 ) N ;
+ - FILLER_30_252 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 295680 266560 ) N ;
+ - FILLER_30_261 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 305760 266560 ) N ;
+ - FILLER_30_271 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 316960 266560 ) N ;
+ - FILLER_30_302 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 351680 266560 ) N ;
+ - FILLER_30_31 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 48160 266560 ) N ;
+ - FILLER_30_314 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 365120 266560 ) N ;
+ - FILLER_30_318 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 369600 266560 ) N ;
+ - FILLER_30_321 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 372960 266560 ) N ;
+ - FILLER_30_324 gf180mcu_fd_sc_mcu7t5v0__fillcap_8 + SOURCE DIST + PLACED ( 376320 266560 ) N ;
+ - FILLER_30_332 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 385280 266560 ) N ;
+ - FILLER_30_334 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 387520 266560 ) N ;
+ - FILLER_30_337 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 390880 266560 ) N ;
+ - FILLER_30_365 gf180mcu_fd_sc_mcu7t5v0__fillcap_16 + SOURCE DIST + PLACED ( 422240 266560 ) N ;
+ - FILLER_30_37 gf180mcu_fd_sc_mcu7t5v0__fillcap_16 + SOURCE DIST + PLACED ( 54880 266560 ) N ;
+ - FILLER_30_381 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 440160 266560 ) N ;
+ - FILLER_30_385 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 444640 266560 ) N ;
+ - FILLER_30_389 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 449120 266560 ) N ;
+ - FILLER_30_392 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 452480 266560 ) N ;
+ - FILLER_30_401 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 462560 266560 ) N ;
+ - FILLER_30_405 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 467040 266560 ) N ;
+ - FILLER_30_409 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 471520 266560 ) N ;
+ - FILLER_30_416 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 479360 266560 ) N ;
+ - FILLER_30_424 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 488320 266560 ) N ;
+ - FILLER_30_455 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 523040 266560 ) N ;
+ - FILLER_30_459 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 527520 266560 ) N ;
+ - FILLER_30_463 gf180mcu_fd_sc_mcu7t5v0__fillcap_32 + SOURCE DIST + PLACED ( 532000 266560 ) N ;
+ - FILLER_30_495 gf180mcu_fd_sc_mcu7t5v0__fillcap_8 + SOURCE DIST + PLACED ( 567840 266560 ) N ;
+ - FILLER_30_503 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 576800 266560 ) N ;
+ - FILLER_30_507 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 581280 266560 ) N ;
+ - FILLER_30_53 gf180mcu_fd_sc_mcu7t5v0__fillcap_8 + SOURCE DIST + PLACED ( 72800 266560 ) N ;
+ - FILLER_30_7 gf180mcu_fd_sc_mcu7t5v0__fillcap_16 + SOURCE DIST + PLACED ( 21280 266560 ) N ;
+ - FILLER_30_90 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 114240 266560 ) N ;
+ - FILLER_30_94 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 118720 266560 ) N ;
+ - FILLER_30_98 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 123200 266560 ) N ;
+ - FILLER_31_100 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 125440 274400 ) FS ;
+ - FILLER_31_110 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 136640 274400 ) FS ;
+ - FILLER_31_118 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 145600 274400 ) FS ;
+ - FILLER_31_122 gf180mcu_fd_sc_mcu7t5v0__fillcap_16 + SOURCE DIST + PLACED ( 150080 274400 ) FS ;
+ - FILLER_31_138 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 168000 274400 ) FS ;
+ - FILLER_31_144 gf180mcu_fd_sc_mcu7t5v0__fillcap_16 + SOURCE DIST + PLACED ( 174720 274400 ) FS ;
+ - FILLER_31_160 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 192640 274400 ) FS ;
+ - FILLER_31_162 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 194880 274400 ) FS ;
+ - FILLER_31_171 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 204960 274400 ) FS ;
+ - FILLER_31_175 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 209440 274400 ) FS ;
+ - FILLER_31_177 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 211680 274400 ) FS ;
+ - FILLER_31_18 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 33600 274400 ) FS ;
+ - FILLER_31_184 gf180mcu_fd_sc_mcu7t5v0__fillcap_16 + SOURCE DIST + PLACED ( 219520 274400 ) FS ;
+ - FILLER_31_2 gf180mcu_fd_sc_mcu7t5v0__fillcap_16 + SOURCE DIST + PLACED ( 15680 274400 ) FS ;
+ - FILLER_31_200 gf180mcu_fd_sc_mcu7t5v0__fillcap_8 + SOURCE DIST + PLACED ( 237440 274400 ) FS ;
+ - FILLER_31_208 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 246400 274400 ) FS ;
+ - FILLER_31_212 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 250880 274400 ) FS ;
+ - FILLER_31_215 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 254240 274400 ) FS ;
+ - FILLER_31_218 gf180mcu_fd_sc_mcu7t5v0__fillcap_32 + SOURCE DIST + PLACED ( 257600 274400 ) FS ;
+ - FILLER_31_22 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 38080 274400 ) FS ;
+ - FILLER_31_250 gf180mcu_fd_sc_mcu7t5v0__fillcap_8 + SOURCE DIST + PLACED ( 293440 274400 ) FS ;
+ - FILLER_31_258 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 302400 274400 ) FS ;
+ - FILLER_31_260 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 304640 274400 ) FS ;
+ - FILLER_31_263 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 308000 274400 ) FS ;
+ - FILLER_31_267 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 312480 274400 ) FS ;
+ - FILLER_31_273 gf180mcu_fd_sc_mcu7t5v0__fillcap_8 + SOURCE DIST + PLACED ( 319200 274400 ) FS ;
+ - FILLER_31_281 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 328160 274400 ) FS ;
+ - FILLER_31_283 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 330400 274400 ) FS ;
+ - FILLER_31_286 gf180mcu_fd_sc_mcu7t5v0__fillcap_16 + SOURCE DIST + PLACED ( 333760 274400 ) FS ;
+ - FILLER_31_302 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 351680 274400 ) FS ;
+ - FILLER_31_305 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 355040 274400 ) FS ;
+ - FILLER_31_309 gf180mcu_fd_sc_mcu7t5v0__fillcap_8 + SOURCE DIST + PLACED ( 359520 274400 ) FS ;
+ - FILLER_31_317 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 368480 274400 ) FS ;
+ - FILLER_31_323 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 375200 274400 ) FS ;
+ - FILLER_31_327 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 379680 274400 ) FS ;
+ - FILLER_31_334 gf180mcu_fd_sc_mcu7t5v0__fillcap_8 + SOURCE DIST + PLACED ( 387520 274400 ) FS ;
+ - FILLER_31_342 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 396480 274400 ) FS ;
+ - FILLER_31_346 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 400960 274400 ) FS ;
+ - FILLER_31_350 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 405440 274400 ) FS ;
+ - FILLER_31_354 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 409920 274400 ) FS ;
+ - FILLER_31_357 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 413280 274400 ) FS ;
+ - FILLER_31_388 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 448000 274400 ) FS ;
+ - FILLER_31_419 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 482720 274400 ) FS ;
+ - FILLER_31_423 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 487200 274400 ) FS ;
+ - FILLER_31_425 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 489440 274400 ) FS ;
+ - FILLER_31_428 gf180mcu_fd_sc_mcu7t5v0__fillcap_8 + SOURCE DIST + PLACED ( 492800 274400 ) FS ;
+ - FILLER_31_436 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 501760 274400 ) FS ;
+ - FILLER_31_448 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 515200 274400 ) FS ;
+ - FILLER_31_479 gf180mcu_fd_sc_mcu7t5v0__fillcap_16 + SOURCE DIST + PLACED ( 549920 274400 ) FS ;
+ - FILLER_31_495 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 567840 274400 ) FS ;
+ - FILLER_31_499 gf180mcu_fd_sc_mcu7t5v0__fillcap_8 + SOURCE DIST + PLACED ( 572320 274400 ) FS ;
+ - FILLER_31_507 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 581280 274400 ) FS ;
+ - FILLER_31_53 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 72800 274400 ) FS ;
+ - FILLER_31_57 gf180mcu_fd_sc_mcu7t5v0__fillcap_8 + SOURCE DIST + PLACED ( 77280 274400 ) FS ;
+ - FILLER_31_65 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 86240 274400 ) FS ;
+ - FILLER_31_69 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 90720 274400 ) FS ;
+ - FILLER_31_73 gf180mcu_fd_sc_mcu7t5v0__fillcap_16 + SOURCE DIST + PLACED ( 95200 274400 ) FS ;
+ - FILLER_31_89 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 113120 274400 ) FS ;
+ - FILLER_31_91 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 115360 274400 ) FS ;
+ - FILLER_32_102 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 127680 282240 ) N ;
+ - FILLER_32_108 gf180mcu_fd_sc_mcu7t5v0__fillcap_32 + SOURCE DIST + PLACED ( 134400 282240 ) N ;
+ - FILLER_32_140 gf180mcu_fd_sc_mcu7t5v0__fillcap_8 + SOURCE DIST + PLACED ( 170240 282240 ) N ;
+ - FILLER_32_148 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 179200 282240 ) N ;
+ - FILLER_32_152 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 183680 282240 ) N ;
+ - FILLER_32_155 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 187040 282240 ) N ;
+ - FILLER_32_159 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 191520 282240 ) N ;
+ - FILLER_32_176 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 210560 282240 ) N ;
+ - FILLER_32_179 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 213920 282240 ) N ;
+ - FILLER_32_183 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 218400 282240 ) N ;
+ - FILLER_32_2 gf180mcu_fd_sc_mcu7t5v0__fillcap_32 + SOURCE DIST + PLACED ( 15680 282240 ) N ;
+ - FILLER_32_214 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 253120 282240 ) N ;
+ - FILLER_32_247 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 290080 282240 ) N ;
+ - FILLER_32_250 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 293440 282240 ) N ;
+ - FILLER_32_261 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 305760 282240 ) N ;
+ - FILLER_32_269 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 314720 282240 ) N ;
+ - FILLER_32_276 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 322560 282240 ) N ;
+ - FILLER_32_280 gf180mcu_fd_sc_mcu7t5v0__fillcap_16 + SOURCE DIST + PLACED ( 327040 282240 ) N ;
+ - FILLER_32_296 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 344960 282240 ) N ;
+ - FILLER_32_299 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 348320 282240 ) N ;
+ - FILLER_32_303 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 352800 282240 ) N ;
+ - FILLER_32_305 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 355040 282240 ) N ;
+ - FILLER_32_314 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 365120 282240 ) N ;
+ - FILLER_32_318 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 369600 282240 ) N ;
+ - FILLER_32_321 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 372960 282240 ) N ;
+ - FILLER_32_335 gf180mcu_fd_sc_mcu7t5v0__fillcap_8 + SOURCE DIST + PLACED ( 388640 282240 ) N ;
+ - FILLER_32_34 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 51520 282240 ) N ;
+ - FILLER_32_343 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 397600 282240 ) N ;
+ - FILLER_32_37 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 54880 282240 ) N ;
+ - FILLER_32_373 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 431200 282240 ) N ;
+ - FILLER_32_377 gf180mcu_fd_sc_mcu7t5v0__fillcap_8 + SOURCE DIST + PLACED ( 435680 282240 ) N ;
+ - FILLER_32_385 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 444640 282240 ) N ;
+ - FILLER_32_389 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 449120 282240 ) N ;
+ - FILLER_32_392 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 452480 282240 ) N ;
+ - FILLER_32_395 gf180mcu_fd_sc_mcu7t5v0__fillcap_16 + SOURCE DIST + PLACED ( 455840 282240 ) N ;
+ - FILLER_32_411 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 473760 282240 ) N ;
+ - FILLER_32_442 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 508480 282240 ) N ;
+ - FILLER_32_446 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 512960 282240 ) N ;
+ - FILLER_32_448 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 515200 282240 ) N ;
+ - FILLER_32_451 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 518560 282240 ) N ;
+ - FILLER_32_455 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 523040 282240 ) N ;
+ - FILLER_32_459 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 527520 282240 ) N ;
+ - FILLER_32_463 gf180mcu_fd_sc_mcu7t5v0__fillcap_32 + SOURCE DIST + PLACED ( 532000 282240 ) N ;
+ - FILLER_32_47 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 66080 282240 ) N ;
+ - FILLER_32_495 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 567840 282240 ) N ;
+ - FILLER_32_505 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 579040 282240 ) N ;
+ - FILLER_32_51 gf180mcu_fd_sc_mcu7t5v0__fillcap_8 + SOURCE DIST + PLACED ( 70560 282240 ) N ;
+ - FILLER_32_59 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 79520 282240 ) N ;
+ - FILLER_32_61 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 81760 282240 ) N ;
+ - FILLER_32_91 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 115360 282240 ) N ;
+ - FILLER_32_95 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 119840 282240 ) N ;
+ - FILLER_32_99 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 124320 282240 ) N ;
+ - FILLER_33_101 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 126560 290080 ) FS ;
+ - FILLER_33_105 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 131040 290080 ) FS ;
+ - FILLER_33_113 gf180mcu_fd_sc_mcu7t5v0__fillcap_16 + SOURCE DIST + PLACED ( 140000 290080 ) FS ;
+ - FILLER_33_129 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 157920 290080 ) FS ;
+ - FILLER_33_133 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 162400 290080 ) FS ;
+ - FILLER_33_141 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 171360 290080 ) FS ;
+ - FILLER_33_144 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 174720 290080 ) FS ;
+ - FILLER_33_153 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 184800 290080 ) FS ;
+ - FILLER_33_157 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 189280 290080 ) FS ;
+ - FILLER_33_166 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 199360 290080 ) FS ;
+ - FILLER_33_18 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 33600 290080 ) FS ;
+ - FILLER_33_183 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 218400 290080 ) FS ;
+ - FILLER_33_191 gf180mcu_fd_sc_mcu7t5v0__fillcap_16 + SOURCE DIST + PLACED ( 227360 290080 ) FS ;
+ - FILLER_33_2 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 15680 290080 ) FS ;
+ - FILLER_33_207 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 245280 290080 ) FS ;
+ - FILLER_33_211 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 249760 290080 ) FS ;
+ - FILLER_33_215 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 254240 290080 ) FS ;
+ - FILLER_33_218 gf180mcu_fd_sc_mcu7t5v0__fillcap_16 + SOURCE DIST + PLACED ( 257600 290080 ) FS ;
+ - FILLER_33_22 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 38080 290080 ) FS ;
+ - FILLER_33_234 gf180mcu_fd_sc_mcu7t5v0__fillcap_8 + SOURCE DIST + PLACED ( 275520 290080 ) FS ;
+ - FILLER_33_242 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 284480 290080 ) FS ;
+ - FILLER_33_246 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 288960 290080 ) FS ;
+ - FILLER_33_249 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 292320 290080 ) FS ;
+ - FILLER_33_26 gf180mcu_fd_sc_mcu7t5v0__fillcap_16 + SOURCE DIST + PLACED ( 42560 290080 ) FS ;
+ - FILLER_33_262 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 306880 290080 ) FS ;
+ - FILLER_33_272 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 318080 290080 ) FS ;
+ - FILLER_33_279 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 325920 290080 ) FS ;
+ - FILLER_33_283 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 330400 290080 ) FS ;
+ - FILLER_33_286 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 333760 290080 ) FS ;
+ - FILLER_33_293 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 341600 290080 ) FS ;
+ - FILLER_33_295 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 343840 290080 ) FS ;
+ - FILLER_33_301 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 350560 290080 ) FS ;
+ - FILLER_33_305 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 355040 290080 ) FS ;
+ - FILLER_33_317 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 368480 290080 ) FS ;
+ - FILLER_33_327 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 379680 290080 ) FS ;
+ - FILLER_33_335 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 388640 290080 ) FS ;
+ - FILLER_33_339 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 393120 290080 ) FS ;
+ - FILLER_33_343 gf180mcu_fd_sc_mcu7t5v0__fillcap_8 + SOURCE DIST + PLACED ( 397600 290080 ) FS ;
+ - FILLER_33_351 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 406560 290080 ) FS ;
+ - FILLER_33_357 gf180mcu_fd_sc_mcu7t5v0__fillcap_16 + SOURCE DIST + PLACED ( 413280 290080 ) FS ;
+ - FILLER_33_373 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 431200 290080 ) FS ;
+ - FILLER_33_403 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 464800 290080 ) FS ;
+ - FILLER_33_407 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 469280 290080 ) FS ;
+ - FILLER_33_411 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 473760 290080 ) FS ;
+ - FILLER_33_415 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 478240 290080 ) FS ;
+ - FILLER_33_42 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 60480 290080 ) FS ;
+ - FILLER_33_421 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 484960 290080 ) FS ;
+ - FILLER_33_425 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 489440 290080 ) FS ;
+ - FILLER_33_428 gf180mcu_fd_sc_mcu7t5v0__fillcap_8 + SOURCE DIST + PLACED ( 492800 290080 ) FS ;
+ - FILLER_33_436 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 501760 290080 ) FS ;
+ - FILLER_33_440 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 506240 290080 ) FS ;
+ - FILLER_33_443 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 509600 290080 ) FS ;
+ - FILLER_33_451 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 518560 290080 ) FS ;
+ - FILLER_33_47 gf180mcu_fd_sc_mcu7t5v0__fillcap_16 + SOURCE DIST + PLACED ( 66080 290080 ) FS ;
+ - FILLER_33_482 gf180mcu_fd_sc_mcu7t5v0__fillcap_8 + SOURCE DIST + PLACED ( 553280 290080 ) FS ;
+ - FILLER_33_490 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 562240 290080 ) FS ;
+ - FILLER_33_494 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 566720 290080 ) FS ;
+ - FILLER_33_496 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 568960 290080 ) FS ;
+ - FILLER_33_499 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 572320 290080 ) FS ;
+ - FILLER_33_501 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 574560 290080 ) FS ;
+ - FILLER_33_508 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 582400 290080 ) FS ;
+ - FILLER_33_63 gf180mcu_fd_sc_mcu7t5v0__fillcap_8 + SOURCE DIST + PLACED ( 84000 290080 ) FS ;
+ - FILLER_33_7 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 21280 290080 ) FS ;
+ - FILLER_33_73 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 95200 290080 ) FS ;
+ - FILLER_33_82 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 105280 290080 ) FS ;
+ - FILLER_33_84 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 107520 290080 ) FS ;
+ - FILLER_33_87 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 110880 290080 ) FS ;
+ - FILLER_33_9 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 23520 290080 ) FS ;
+ - FILLER_33_97 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 122080 290080 ) FS ;
+ - FILLER_34_102 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 127680 297920 ) N ;
+ - FILLER_34_108 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 134400 297920 ) N ;
+ - FILLER_34_119 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 146720 297920 ) N ;
+ - FILLER_34_123 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 151200 297920 ) N ;
+ - FILLER_34_125 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 153440 297920 ) N ;
+ - FILLER_34_155 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 187040 297920 ) N ;
+ - FILLER_34_159 gf180mcu_fd_sc_mcu7t5v0__fillcap_8 + SOURCE DIST + PLACED ( 191520 297920 ) N ;
+ - FILLER_34_167 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 200480 297920 ) N ;
+ - FILLER_34_169 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 202720 297920 ) N ;
+ - FILLER_34_175 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 209440 297920 ) N ;
+ - FILLER_34_179 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 213920 297920 ) N ;
+ - FILLER_34_183 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 218400 297920 ) N ;
+ - FILLER_34_193 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 229600 297920 ) N ;
+ - FILLER_34_195 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 231840 297920 ) N ;
+ - FILLER_34_198 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 235200 297920 ) N ;
+ - FILLER_34_2 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 15680 297920 ) N ;
+ - FILLER_34_229 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 269920 297920 ) N ;
+ - FILLER_34_239 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 281120 297920 ) N ;
+ - FILLER_34_243 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 285600 297920 ) N ;
+ - FILLER_34_247 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 290080 297920 ) N ;
+ - FILLER_34_250 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 293440 297920 ) N ;
+ - FILLER_34_301 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 350560 297920 ) N ;
+ - FILLER_34_311 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 361760 297920 ) N ;
+ - FILLER_34_318 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 369600 297920 ) N ;
+ - FILLER_34_32 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 49280 297920 ) N ;
+ - FILLER_34_321 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 372960 297920 ) N ;
+ - FILLER_34_324 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 376320 297920 ) N ;
+ - FILLER_34_328 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 380800 297920 ) N ;
+ - FILLER_34_34 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 51520 297920 ) N ;
+ - FILLER_34_358 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 414400 297920 ) N ;
+ - FILLER_34_362 gf180mcu_fd_sc_mcu7t5v0__fillcap_16 + SOURCE DIST + PLACED ( 418880 297920 ) N ;
+ - FILLER_34_37 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 54880 297920 ) N ;
+ - FILLER_34_378 gf180mcu_fd_sc_mcu7t5v0__fillcap_8 + SOURCE DIST + PLACED ( 436800 297920 ) N ;
+ - FILLER_34_386 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 445760 297920 ) N ;
+ - FILLER_34_392 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 452480 297920 ) N ;
+ - FILLER_34_398 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 459200 297920 ) N ;
+ - FILLER_34_40 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 58240 297920 ) N ;
+ - FILLER_34_405 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 467040 297920 ) N ;
+ - FILLER_34_409 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 471520 297920 ) N ;
+ - FILLER_34_423 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 487200 297920 ) N ;
+ - FILLER_34_427 gf180mcu_fd_sc_mcu7t5v0__fillcap_16 + SOURCE DIST + PLACED ( 491680 297920 ) N ;
+ - FILLER_34_443 gf180mcu_fd_sc_mcu7t5v0__fillcap_8 + SOURCE DIST + PLACED ( 509600 297920 ) N ;
+ - FILLER_34_453 gf180mcu_fd_sc_mcu7t5v0__fillcap_8 + SOURCE DIST + PLACED ( 520800 297920 ) N ;
+ - FILLER_34_463 gf180mcu_fd_sc_mcu7t5v0__fillcap_16 + SOURCE DIST + PLACED ( 532000 297920 ) N ;
+ - FILLER_34_479 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 549920 297920 ) N ;
+ - FILLER_34_483 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 554400 297920 ) N ;
+ - FILLER_34_493 gf180mcu_fd_sc_mcu7t5v0__fillcap_8 + SOURCE DIST + PLACED ( 565600 297920 ) N ;
+ - FILLER_34_501 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 574560 297920 ) N ;
+ - FILLER_34_505 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 579040 297920 ) N ;
+ - FILLER_34_508 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 582400 297920 ) N ;
+ - FILLER_34_53 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 72800 297920 ) N ;
+ - FILLER_34_59 gf180mcu_fd_sc_mcu7t5v0__fillcap_8 + SOURCE DIST + PLACED ( 79520 297920 ) N ;
+ - FILLER_34_67 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 88480 297920 ) N ;
+ - FILLER_34_71 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 92960 297920 ) N ;
+ - FILLER_34_75 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 97440 297920 ) N ;
+ - FILLER_34_85 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 108640 297920 ) N ;
+ - FILLER_34_98 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 123200 297920 ) N ;
+ - FILLER_35_100 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 125440 305760 ) FS ;
+ - FILLER_35_131 gf180mcu_fd_sc_mcu7t5v0__fillcap_8 + SOURCE DIST + PLACED ( 160160 305760 ) FS ;
+ - FILLER_35_139 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 169120 305760 ) FS ;
+ - FILLER_35_14 gf180mcu_fd_sc_mcu7t5v0__fillcap_8 + SOURCE DIST + PLACED ( 29120 305760 ) FS ;
+ - FILLER_35_141 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 171360 305760 ) FS ;
+ - FILLER_35_144 gf180mcu_fd_sc_mcu7t5v0__fillcap_8 + SOURCE DIST + PLACED ( 174720 305760 ) FS ;
+ - FILLER_35_152 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 183680 305760 ) FS ;
+ - FILLER_35_156 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 188160 305760 ) FS ;
+ - FILLER_35_160 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 192640 305760 ) FS ;
+ - FILLER_35_164 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 197120 305760 ) FS ;
+ - FILLER_35_177 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 211680 305760 ) FS ;
+ - FILLER_35_183 gf180mcu_fd_sc_mcu7t5v0__fillcap_8 + SOURCE DIST + PLACED ( 218400 305760 ) FS ;
+ - FILLER_35_191 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 227360 305760 ) FS ;
+ - FILLER_35_2 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 15680 305760 ) FS ;
+ - FILLER_35_205 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 243040 305760 ) FS ;
+ - FILLER_35_209 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 247520 305760 ) FS ;
+ - FILLER_35_215 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 254240 305760 ) FS ;
+ - FILLER_35_218 gf180mcu_fd_sc_mcu7t5v0__fillcap_8 + SOURCE DIST + PLACED ( 257600 305760 ) FS ;
+ - FILLER_35_22 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 38080 305760 ) FS ;
+ - FILLER_35_226 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 266560 305760 ) FS ;
+ - FILLER_35_230 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 271040 305760 ) FS ;
+ - FILLER_35_243 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 285600 305760 ) FS ;
+ - FILLER_35_249 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 292320 305760 ) FS ;
+ - FILLER_35_251 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 294560 305760 ) FS ;
+ - FILLER_35_256 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 300160 305760 ) FS ;
+ - FILLER_35_26 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 42560 305760 ) FS ;
+ - FILLER_35_262 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 306880 305760 ) FS ;
+ - FILLER_35_277 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 323680 305760 ) FS ;
+ - FILLER_35_281 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 328160 305760 ) FS ;
+ - FILLER_35_283 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 330400 305760 ) FS ;
+ - FILLER_35_286 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 333760 305760 ) FS ;
+ - FILLER_35_302 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 351680 305760 ) FS ;
+ - FILLER_35_31 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 48160 305760 ) FS ;
+ - FILLER_35_310 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 360640 305760 ) FS ;
+ - FILLER_35_318 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 369600 305760 ) FS ;
+ - FILLER_35_322 gf180mcu_fd_sc_mcu7t5v0__fillcap_8 + SOURCE DIST + PLACED ( 374080 305760 ) FS ;
+ - FILLER_35_330 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 383040 305760 ) FS ;
+ - FILLER_35_334 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 387520 305760 ) FS ;
+ - FILLER_35_336 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 389760 305760 ) FS ;
+ - FILLER_35_343 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 397600 305760 ) FS ;
+ - FILLER_35_347 gf180mcu_fd_sc_mcu7t5v0__fillcap_8 + SOURCE DIST + PLACED ( 402080 305760 ) FS ;
+ - FILLER_35_357 gf180mcu_fd_sc_mcu7t5v0__fillcap_32 + SOURCE DIST + PLACED ( 413280 305760 ) FS ;
+ - FILLER_35_389 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 449120 305760 ) FS ;
+ - FILLER_35_392 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 452480 305760 ) FS ;
+ - FILLER_35_404 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 465920 305760 ) FS ;
+ - FILLER_35_408 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 470400 305760 ) FS ;
+ - FILLER_35_418 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 481600 305760 ) FS ;
+ - FILLER_35_42 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 60480 305760 ) FS ;
+ - FILLER_35_425 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 489440 305760 ) FS ;
+ - FILLER_35_428 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 492800 305760 ) FS ;
+ - FILLER_35_431 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 496160 305760 ) FS ;
+ - FILLER_35_433 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 498400 305760 ) FS ;
+ - FILLER_35_436 gf180mcu_fd_sc_mcu7t5v0__fillcap_32 + SOURCE DIST + PLACED ( 501760 305760 ) FS ;
+ - FILLER_35_468 gf180mcu_fd_sc_mcu7t5v0__fillcap_8 + SOURCE DIST + PLACED ( 537600 305760 ) FS ;
+ - FILLER_35_476 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 546560 305760 ) FS ;
+ - FILLER_35_480 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 551040 305760 ) FS ;
+ - FILLER_35_483 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 554400 305760 ) FS ;
+ - FILLER_35_493 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 565600 305760 ) FS ;
+ - FILLER_35_499 gf180mcu_fd_sc_mcu7t5v0__fillcap_8 + SOURCE DIST + PLACED ( 572320 305760 ) FS ;
+ - FILLER_35_507 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 581280 305760 ) FS ;
+ - FILLER_35_55 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 75040 305760 ) FS ;
+ - FILLER_35_6 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 20160 305760 ) FS ;
+ - FILLER_35_65 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 86240 305760 ) FS ;
+ - FILLER_35_69 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 90720 305760 ) FS ;
+ - FILLER_35_73 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 95200 305760 ) FS ;
+ - FILLER_35_85 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 108640 305760 ) FS ;
+ - FILLER_35_91 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 115360 305760 ) FS ;
+ - FILLER_35_95 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 119840 305760 ) FS ;
+ - FILLER_35_97 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 122080 305760 ) FS ;
+ - FILLER_36_105 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 131040 313600 ) N ;
+ - FILLER_36_108 gf180mcu_fd_sc_mcu7t5v0__fillcap_16 + SOURCE DIST + PLACED ( 134400 313600 ) N ;
+ - FILLER_36_124 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 152320 313600 ) N ;
+ - FILLER_36_126 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 154560 313600 ) N ;
+ - FILLER_36_156 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 188160 313600 ) N ;
+ - FILLER_36_158 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 190400 313600 ) N ;
+ - FILLER_36_161 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 193760 313600 ) N ;
+ - FILLER_36_17 gf180mcu_fd_sc_mcu7t5v0__fillcap_8 + SOURCE DIST + PLACED ( 32480 313600 ) N ;
+ - FILLER_36_175 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 209440 313600 ) N ;
+ - FILLER_36_179 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 213920 313600 ) N ;
+ - FILLER_36_185 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 220640 313600 ) N ;
+ - FILLER_36_191 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 227360 313600 ) N ;
+ - FILLER_36_199 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 236320 313600 ) N ;
+ - FILLER_36_2 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 15680 313600 ) N ;
+ - FILLER_36_230 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 271040 313600 ) N ;
+ - FILLER_36_234 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 275520 313600 ) N ;
+ - FILLER_36_244 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 286720 313600 ) N ;
+ - FILLER_36_25 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 41440 313600 ) N ;
+ - FILLER_36_250 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 293440 313600 ) N ;
+ - FILLER_36_256 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 300160 313600 ) N ;
+ - FILLER_36_260 gf180mcu_fd_sc_mcu7t5v0__fillcap_32 + SOURCE DIST + PLACED ( 304640 313600 ) N ;
+ - FILLER_36_292 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 340480 313600 ) N ;
+ - FILLER_36_296 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 344960 313600 ) N ;
+ - FILLER_36_306 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 356160 313600 ) N ;
+ - FILLER_36_312 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 362880 313600 ) N ;
+ - FILLER_36_316 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 367360 313600 ) N ;
+ - FILLER_36_318 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 369600 313600 ) N ;
+ - FILLER_36_321 gf180mcu_fd_sc_mcu7t5v0__fillcap_8 + SOURCE DIST + PLACED ( 372960 313600 ) N ;
+ - FILLER_36_329 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 381920 313600 ) N ;
+ - FILLER_36_335 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 388640 313600 ) N ;
+ - FILLER_36_34 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 51520 313600 ) N ;
+ - FILLER_36_345 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 399840 313600 ) N ;
+ - FILLER_36_37 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 54880 313600 ) N ;
+ - FILLER_36_376 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 434560 313600 ) N ;
+ - FILLER_36_380 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 439040 313600 ) N ;
+ - FILLER_36_382 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 441280 313600 ) N ;
+ - FILLER_36_389 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 449120 313600 ) N ;
+ - FILLER_36_392 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 452480 313600 ) N ;
+ - FILLER_36_395 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 455840 313600 ) N ;
+ - FILLER_36_399 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 460320 313600 ) N ;
+ - FILLER_36_407 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 469280 313600 ) N ;
+ - FILLER_36_41 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 59360 313600 ) N ;
+ - FILLER_36_411 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 473760 313600 ) N ;
+ - FILLER_36_415 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 478240 313600 ) N ;
+ - FILLER_36_424 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 488320 313600 ) N ;
+ - FILLER_36_434 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 499520 313600 ) N ;
+ - FILLER_36_444 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 510720 313600 ) N ;
+ - FILLER_36_448 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 515200 313600 ) N ;
+ - FILLER_36_452 gf180mcu_fd_sc_mcu7t5v0__fillcap_8 + SOURCE DIST + PLACED ( 519680 313600 ) N ;
+ - FILLER_36_460 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 528640 313600 ) N ;
+ - FILLER_36_463 gf180mcu_fd_sc_mcu7t5v0__fillcap_32 + SOURCE DIST + PLACED ( 532000 313600 ) N ;
+ - FILLER_36_495 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 567840 313600 ) N ;
+ - FILLER_36_503 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 576800 313600 ) N ;
+ - FILLER_36_507 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 581280 313600 ) N ;
+ - FILLER_36_53 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 72800 313600 ) N ;
+ - FILLER_36_60 gf180mcu_fd_sc_mcu7t5v0__fillcap_8 + SOURCE DIST + PLACED ( 80640 313600 ) N ;
+ - FILLER_36_68 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 89600 313600 ) N ;
+ - FILLER_36_72 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 94080 313600 ) N ;
+ - FILLER_36_76 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 98560 313600 ) N ;
+ - FILLER_36_87 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 110880 313600 ) N ;
+ - FILLER_36_97 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 122080 313600 ) N ;
+ - FILLER_37_117 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 144480 321440 ) FS ;
+ - FILLER_37_121 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 148960 321440 ) FS ;
+ - FILLER_37_125 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 153440 321440 ) FS ;
+ - FILLER_37_128 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 156800 321440 ) FS ;
+ - FILLER_37_135 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 164640 321440 ) FS ;
+ - FILLER_37_139 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 169120 321440 ) FS ;
+ - FILLER_37_141 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 171360 321440 ) FS ;
+ - FILLER_37_144 gf180mcu_fd_sc_mcu7t5v0__fillcap_8 + SOURCE DIST + PLACED ( 174720 321440 ) FS ;
+ - FILLER_37_152 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 183680 321440 ) FS ;
+ - FILLER_37_158 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 190400 321440 ) FS ;
+ - FILLER_37_189 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 225120 321440 ) FS ;
+ - FILLER_37_193 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 229600 321440 ) FS ;
+ - FILLER_37_195 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 231840 321440 ) FS ;
+ - FILLER_37_2 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 15680 321440 ) FS ;
+ - FILLER_37_204 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 241920 321440 ) FS ;
+ - FILLER_37_210 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 248640 321440 ) FS ;
+ - FILLER_37_212 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 250880 321440 ) FS ;
+ - FILLER_37_215 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 254240 321440 ) FS ;
+ - FILLER_37_218 gf180mcu_fd_sc_mcu7t5v0__fillcap_16 + SOURCE DIST + PLACED ( 257600 321440 ) FS ;
+ - FILLER_37_234 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 275520 321440 ) FS ;
+ - FILLER_37_238 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 280000 321440 ) FS ;
+ - FILLER_37_242 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 284480 321440 ) FS ;
+ - FILLER_37_252 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 295680 321440 ) FS ;
+ - FILLER_37_283 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 330400 321440 ) FS ;
+ - FILLER_37_286 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 333760 321440 ) FS ;
+ - FILLER_37_289 gf180mcu_fd_sc_mcu7t5v0__fillcap_16 + SOURCE DIST + PLACED ( 337120 321440 ) FS ;
+ - FILLER_37_305 gf180mcu_fd_sc_mcu7t5v0__fillcap_8 + SOURCE DIST + PLACED ( 355040 321440 ) FS ;
+ - FILLER_37_313 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 364000 321440 ) FS ;
+ - FILLER_37_32 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 49280 321440 ) FS ;
+ - FILLER_37_331 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 384160 321440 ) FS ;
+ - FILLER_37_346 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 400960 321440 ) FS ;
+ - FILLER_37_354 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 409920 321440 ) FS ;
+ - FILLER_37_357 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 413280 321440 ) FS ;
+ - FILLER_37_36 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 53760 321440 ) FS ;
+ - FILLER_37_363 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 420000 321440 ) FS ;
+ - FILLER_37_367 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 424480 321440 ) FS ;
+ - FILLER_37_40 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 58240 321440 ) FS ;
+ - FILLER_37_400 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 461440 321440 ) FS ;
+ - FILLER_37_410 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 472640 321440 ) FS ;
+ - FILLER_37_417 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 480480 321440 ) FS ;
+ - FILLER_37_421 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 484960 321440 ) FS ;
+ - FILLER_37_425 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 489440 321440 ) FS ;
+ - FILLER_37_428 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 492800 321440 ) FS ;
+ - FILLER_37_438 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 504000 321440 ) FS ;
+ - FILLER_37_448 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 515200 321440 ) FS ;
+ - FILLER_37_481 gf180mcu_fd_sc_mcu7t5v0__fillcap_16 + SOURCE DIST + PLACED ( 552160 321440 ) FS ;
+ - FILLER_37_499 gf180mcu_fd_sc_mcu7t5v0__fillcap_8 + SOURCE DIST + PLACED ( 572320 321440 ) FS ;
+ - FILLER_37_50 gf180mcu_fd_sc_mcu7t5v0__fillcap_8 + SOURCE DIST + PLACED ( 69440 321440 ) FS ;
+ - FILLER_37_507 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 581280 321440 ) FS ;
+ - FILLER_37_58 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 78400 321440 ) FS ;
+ - FILLER_37_62 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 82880 321440 ) FS ;
+ - FILLER_37_66 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 87360 321440 ) FS ;
+ - FILLER_37_70 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 91840 321440 ) FS ;
+ - FILLER_37_73 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 95200 321440 ) FS ;
+ - FILLER_37_77 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 99680 321440 ) FS ;
+ - FILLER_37_89 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 113120 321440 ) FS ;
+ - FILLER_38_105 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 131040 329280 ) N ;
+ - FILLER_38_108 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 134400 329280 ) N ;
+ - FILLER_38_138 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 168000 329280 ) N ;
+ - FILLER_38_142 gf180mcu_fd_sc_mcu7t5v0__fillcap_16 + SOURCE DIST + PLACED ( 172480 329280 ) N ;
+ - FILLER_38_15 gf180mcu_fd_sc_mcu7t5v0__fillcap_16 + SOURCE DIST + PLACED ( 30240 329280 ) N ;
+ - FILLER_38_158 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 190400 329280 ) N ;
+ - FILLER_38_165 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 198240 329280 ) N ;
+ - FILLER_38_172 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 206080 329280 ) N ;
+ - FILLER_38_176 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 210560 329280 ) N ;
+ - FILLER_38_179 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 213920 329280 ) N ;
+ - FILLER_38_181 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 216160 329280 ) N ;
+ - FILLER_38_2 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 15680 329280 ) N ;
+ - FILLER_38_208 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 246400 329280 ) N ;
+ - FILLER_38_212 gf180mcu_fd_sc_mcu7t5v0__fillcap_8 + SOURCE DIST + PLACED ( 250880 329280 ) N ;
+ - FILLER_38_224 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 264320 329280 ) N ;
+ - FILLER_38_226 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 266560 329280 ) N ;
+ - FILLER_38_229 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 269920 329280 ) N ;
+ - FILLER_38_233 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 274400 329280 ) N ;
+ - FILLER_38_247 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 290080 329280 ) N ;
+ - FILLER_38_250 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 293440 329280 ) N ;
+ - FILLER_38_269 gf180mcu_fd_sc_mcu7t5v0__fillcap_16 + SOURCE DIST + PLACED ( 314720 329280 ) N ;
+ - FILLER_38_285 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 332640 329280 ) N ;
+ - FILLER_38_31 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 48160 329280 ) N ;
+ - FILLER_38_318 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 369600 329280 ) N ;
+ - FILLER_38_321 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 372960 329280 ) N ;
+ - FILLER_38_326 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 378560 329280 ) N ;
+ - FILLER_38_330 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 383040 329280 ) N ;
+ - FILLER_38_333 gf180mcu_fd_sc_mcu7t5v0__fillcap_8 + SOURCE DIST + PLACED ( 386400 329280 ) N ;
+ - FILLER_38_353 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 408800 329280 ) N ;
+ - FILLER_38_357 gf180mcu_fd_sc_mcu7t5v0__fillcap_16 + SOURCE DIST + PLACED ( 413280 329280 ) N ;
+ - FILLER_38_37 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 54880 329280 ) N ;
+ - FILLER_38_373 gf180mcu_fd_sc_mcu7t5v0__fillcap_8 + SOURCE DIST + PLACED ( 431200 329280 ) N ;
+ - FILLER_38_381 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 440160 329280 ) N ;
+ - FILLER_38_383 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 442400 329280 ) N ;
+ - FILLER_38_389 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 449120 329280 ) N ;
+ - FILLER_38_392 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 452480 329280 ) N ;
+ - FILLER_38_396 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 456960 329280 ) N ;
+ - FILLER_38_400 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 461440 329280 ) N ;
+ - FILLER_38_407 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 469280 329280 ) N ;
+ - FILLER_38_41 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 59360 329280 ) N ;
+ - FILLER_38_411 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 473760 329280 ) N ;
+ - FILLER_38_415 gf180mcu_fd_sc_mcu7t5v0__fillcap_8 + SOURCE DIST + PLACED ( 478240 329280 ) N ;
+ - FILLER_38_423 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 487200 329280 ) N ;
+ - FILLER_38_427 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 491680 329280 ) N ;
+ - FILLER_38_429 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 493920 329280 ) N ;
+ - FILLER_38_441 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 507360 329280 ) N ;
+ - FILLER_38_451 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 518560 329280 ) N ;
+ - FILLER_38_455 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 523040 329280 ) N ;
+ - FILLER_38_459 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 527520 329280 ) N ;
+ - FILLER_38_463 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 532000 329280 ) N ;
+ - FILLER_38_472 gf180mcu_fd_sc_mcu7t5v0__fillcap_32 + SOURCE DIST + PLACED ( 542080 329280 ) N ;
+ - FILLER_38_504 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 577920 329280 ) N ;
+ - FILLER_38_508 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 582400 329280 ) N ;
+ - FILLER_38_53 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 72800 329280 ) N ;
+ - FILLER_38_57 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 77280 329280 ) N ;
+ - FILLER_38_59 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 79520 329280 ) N ;
+ - FILLER_38_6 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 20160 329280 ) N ;
+ - FILLER_38_64 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 85120 329280 ) N ;
+ - FILLER_38_66 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 87360 329280 ) N ;
+ - FILLER_38_75 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 97440 329280 ) N ;
+ - FILLER_38_8 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 22400 329280 ) N ;
+ - FILLER_38_88 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 112000 329280 ) N ;
+ - FILLER_38_92 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 116480 329280 ) N ;
+ - FILLER_38_95 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 119840 329280 ) N ;
+ - FILLER_39_120 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 147840 337120 ) FS ;
+ - FILLER_39_124 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 152320 337120 ) FS ;
+ - FILLER_39_126 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 154560 337120 ) FS ;
+ - FILLER_39_129 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 157920 337120 ) FS ;
+ - FILLER_39_133 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 162400 337120 ) FS ;
+ - FILLER_39_141 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 171360 337120 ) FS ;
+ - FILLER_39_144 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 174720 337120 ) FS ;
+ - FILLER_39_153 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 184800 337120 ) FS ;
+ - FILLER_39_157 gf180mcu_fd_sc_mcu7t5v0__fillcap_32 + SOURCE DIST + PLACED ( 189280 337120 ) FS ;
+ - FILLER_39_189 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 225120 337120 ) FS ;
+ - FILLER_39_193 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 229600 337120 ) FS ;
+ - FILLER_39_2 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 15680 337120 ) FS ;
+ - FILLER_39_205 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 243040 337120 ) FS ;
+ - FILLER_39_209 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 247520 337120 ) FS ;
+ - FILLER_39_212 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 250880 337120 ) FS ;
+ - FILLER_39_215 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 254240 337120 ) FS ;
+ - FILLER_39_245 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 287840 337120 ) FS ;
+ - FILLER_39_273 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 319200 337120 ) FS ;
+ - FILLER_39_283 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 330400 337120 ) FS ;
+ - FILLER_39_286 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 333760 337120 ) FS ;
+ - FILLER_39_297 gf180mcu_fd_sc_mcu7t5v0__fillcap_8 + SOURCE DIST + PLACED ( 346080 337120 ) FS ;
+ - FILLER_39_305 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 355040 337120 ) FS ;
+ - FILLER_39_316 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 367360 337120 ) FS ;
+ - FILLER_39_320 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 371840 337120 ) FS ;
+ - FILLER_39_322 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 374080 337120 ) FS ;
+ - FILLER_39_328 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 380800 337120 ) FS ;
+ - FILLER_39_332 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 385280 337120 ) FS ;
+ - FILLER_39_336 gf180mcu_fd_sc_mcu7t5v0__fillcap_8 + SOURCE DIST + PLACED ( 389760 337120 ) FS ;
+ - FILLER_39_344 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 398720 337120 ) FS ;
+ - FILLER_39_348 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 403200 337120 ) FS ;
+ - FILLER_39_35 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 52640 337120 ) FS ;
+ - FILLER_39_352 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 407680 337120 ) FS ;
+ - FILLER_39_354 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 409920 337120 ) FS ;
+ - FILLER_39_357 gf180mcu_fd_sc_mcu7t5v0__fillcap_32 + SOURCE DIST + PLACED ( 413280 337120 ) FS ;
+ - FILLER_39_389 gf180mcu_fd_sc_mcu7t5v0__fillcap_8 + SOURCE DIST + PLACED ( 449120 337120 ) FS ;
+ - FILLER_39_39 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 57120 337120 ) FS ;
+ - FILLER_39_397 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 458080 337120 ) FS ;
+ - FILLER_39_401 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 462560 337120 ) FS ;
+ - FILLER_39_403 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 464800 337120 ) FS ;
+ - FILLER_39_406 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 468160 337120 ) FS ;
+ - FILLER_39_412 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 474880 337120 ) FS ;
+ - FILLER_39_423 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 487200 337120 ) FS ;
+ - FILLER_39_425 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 489440 337120 ) FS ;
+ - FILLER_39_428 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 492800 337120 ) FS ;
+ - FILLER_39_43 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 61600 337120 ) FS ;
+ - FILLER_39_438 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 504000 337120 ) FS ;
+ - FILLER_39_444 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 510720 337120 ) FS ;
+ - FILLER_39_448 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 515200 337120 ) FS ;
+ - FILLER_39_45 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 63840 337120 ) FS ;
+ - FILLER_39_456 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 524160 337120 ) FS ;
+ - FILLER_39_487 gf180mcu_fd_sc_mcu7t5v0__fillcap_8 + SOURCE DIST + PLACED ( 558880 337120 ) FS ;
+ - FILLER_39_495 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 567840 337120 ) FS ;
+ - FILLER_39_499 gf180mcu_fd_sc_mcu7t5v0__fillcap_8 + SOURCE DIST + PLACED ( 572320 337120 ) FS ;
+ - FILLER_39_507 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 581280 337120 ) FS ;
+ - FILLER_39_62 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 82880 337120 ) FS ;
+ - FILLER_39_68 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 89600 337120 ) FS ;
+ - FILLER_39_70 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 91840 337120 ) FS ;
+ - FILLER_39_73 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 95200 337120 ) FS ;
+ - FILLER_39_86 gf180mcu_fd_sc_mcu7t5v0__fillcap_8 + SOURCE DIST + PLACED ( 109760 337120 ) FS ;
+ - FILLER_3_137 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 166880 54880 ) FS ;
+ - FILLER_3_141 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 171360 54880 ) FS ;
+ - FILLER_3_144 gf180mcu_fd_sc_mcu7t5v0__fillcap_64 + SOURCE DIST + PLACED ( 174720 54880 ) FS ;
+ - FILLER_3_2 gf180mcu_fd_sc_mcu7t5v0__fillcap_64 + SOURCE DIST + PLACED ( 15680 54880 ) FS ;
+ - FILLER_3_208 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 246400 54880 ) FS ;
+ - FILLER_3_212 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 250880 54880 ) FS ;
+ - FILLER_3_215 gf180mcu_fd_sc_mcu7t5v0__fillcap_64 + SOURCE DIST + PLACED ( 254240 54880 ) FS ;
+ - FILLER_3_279 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 325920 54880 ) FS ;
+ - FILLER_3_283 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 330400 54880 ) FS ;
+ - FILLER_3_286 gf180mcu_fd_sc_mcu7t5v0__fillcap_64 + SOURCE DIST + PLACED ( 333760 54880 ) FS ;
+ - FILLER_3_350 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 405440 54880 ) FS ;
+ - FILLER_3_354 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 409920 54880 ) FS ;
+ - FILLER_3_357 gf180mcu_fd_sc_mcu7t5v0__fillcap_64 + SOURCE DIST + PLACED ( 413280 54880 ) FS ;
+ - FILLER_3_421 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 484960 54880 ) FS ;
+ - FILLER_3_425 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 489440 54880 ) FS ;
+ - FILLER_3_428 gf180mcu_fd_sc_mcu7t5v0__fillcap_64 + SOURCE DIST + PLACED ( 492800 54880 ) FS ;
+ - FILLER_3_492 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 564480 54880 ) FS ;
+ - FILLER_3_496 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 568960 54880 ) FS ;
+ - FILLER_3_499 gf180mcu_fd_sc_mcu7t5v0__fillcap_8 + SOURCE DIST + PLACED ( 572320 54880 ) FS ;
+ - FILLER_3_507 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 581280 54880 ) FS ;
+ - FILLER_3_66 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 87360 54880 ) FS ;
+ - FILLER_3_70 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 91840 54880 ) FS ;
+ - FILLER_3_73 gf180mcu_fd_sc_mcu7t5v0__fillcap_64 + SOURCE DIST + PLACED ( 95200 54880 ) FS ;
+ - FILLER_40_108 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 134400 344960 ) N ;
+ - FILLER_40_117 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 144480 344960 ) N ;
+ - FILLER_40_127 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 155680 344960 ) N ;
+ - FILLER_40_158 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 190400 344960 ) N ;
+ - FILLER_40_172 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 206080 344960 ) N ;
+ - FILLER_40_176 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 210560 344960 ) N ;
+ - FILLER_40_179 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 213920 344960 ) N ;
+ - FILLER_40_2 gf180mcu_fd_sc_mcu7t5v0__fillcap_32 + SOURCE DIST + PLACED ( 15680 344960 ) N ;
+ - FILLER_40_209 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 247520 344960 ) N ;
+ - FILLER_40_213 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 252000 344960 ) N ;
+ - FILLER_40_217 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 256480 344960 ) N ;
+ - FILLER_40_227 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 267680 344960 ) N ;
+ - FILLER_40_237 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 278880 344960 ) N ;
+ - FILLER_40_243 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 285600 344960 ) N ;
+ - FILLER_40_247 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 290080 344960 ) N ;
+ - FILLER_40_250 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 293440 344960 ) N ;
+ - FILLER_40_298 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 347200 344960 ) N ;
+ - FILLER_40_302 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 351680 344960 ) N ;
+ - FILLER_40_313 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 364000 344960 ) N ;
+ - FILLER_40_315 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 366240 344960 ) N ;
+ - FILLER_40_318 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 369600 344960 ) N ;
+ - FILLER_40_321 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 372960 344960 ) N ;
+ - FILLER_40_324 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 376320 344960 ) N ;
+ - FILLER_40_334 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 387520 344960 ) N ;
+ - FILLER_40_34 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 51520 344960 ) N ;
+ - FILLER_40_346 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 400960 344960 ) N ;
+ - FILLER_40_37 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 54880 344960 ) N ;
+ - FILLER_40_379 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 437920 344960 ) N ;
+ - FILLER_40_383 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 442400 344960 ) N ;
+ - FILLER_40_389 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 449120 344960 ) N ;
+ - FILLER_40_392 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 452480 344960 ) N ;
+ - FILLER_40_400 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 461440 344960 ) N ;
+ - FILLER_40_404 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 465920 344960 ) N ;
+ - FILLER_40_410 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 472640 344960 ) N ;
+ - FILLER_40_414 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 477120 344960 ) N ;
+ - FILLER_40_416 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 479360 344960 ) N ;
+ - FILLER_40_427 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 491680 344960 ) N ;
+ - FILLER_40_439 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 505120 344960 ) N ;
+ - FILLER_40_449 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 516320 344960 ) N ;
+ - FILLER_40_453 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 520800 344960 ) N ;
+ - FILLER_40_455 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 523040 344960 ) N ;
+ - FILLER_40_458 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 526400 344960 ) N ;
+ - FILLER_40_46 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 64960 344960 ) N ;
+ - FILLER_40_460 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 528640 344960 ) N ;
+ - FILLER_40_463 gf180mcu_fd_sc_mcu7t5v0__fillcap_32 + SOURCE DIST + PLACED ( 532000 344960 ) N ;
+ - FILLER_40_495 gf180mcu_fd_sc_mcu7t5v0__fillcap_8 + SOURCE DIST + PLACED ( 567840 344960 ) N ;
+ - FILLER_40_50 gf180mcu_fd_sc_mcu7t5v0__fillcap_16 + SOURCE DIST + PLACED ( 69440 344960 ) N ;
+ - FILLER_40_503 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 576800 344960 ) N ;
+ - FILLER_40_507 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 581280 344960 ) N ;
+ - FILLER_40_66 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 87360 344960 ) N ;
+ - FILLER_40_70 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 91840 344960 ) N ;
+ - FILLER_40_80 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 103040 344960 ) N ;
+ - FILLER_40_90 gf180mcu_fd_sc_mcu7t5v0__fillcap_16 + SOURCE DIST + PLACED ( 114240 344960 ) N ;
+ - FILLER_41_126 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 154560 352800 ) FS ;
+ - FILLER_41_130 gf180mcu_fd_sc_mcu7t5v0__fillcap_8 + SOURCE DIST + PLACED ( 159040 352800 ) FS ;
+ - FILLER_41_138 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 168000 352800 ) FS ;
+ - FILLER_41_141 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 171360 352800 ) FS ;
+ - FILLER_41_144 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 174720 352800 ) FS ;
+ - FILLER_41_146 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 176960 352800 ) FS ;
+ - FILLER_41_155 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 187040 352800 ) FS ;
+ - FILLER_41_157 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 189280 352800 ) FS ;
+ - FILLER_41_160 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 192640 352800 ) FS ;
+ - FILLER_41_164 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 197120 352800 ) FS ;
+ - FILLER_41_197 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 234080 352800 ) FS ;
+ - FILLER_41_2 gf180mcu_fd_sc_mcu7t5v0__fillcap_32 + SOURCE DIST + PLACED ( 15680 352800 ) FS ;
+ - FILLER_41_207 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 245280 352800 ) FS ;
+ - FILLER_41_211 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 249760 352800 ) FS ;
+ - FILLER_41_215 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 254240 352800 ) FS ;
+ - FILLER_41_218 gf180mcu_fd_sc_mcu7t5v0__fillcap_8 + SOURCE DIST + PLACED ( 257600 352800 ) FS ;
+ - FILLER_41_226 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 266560 352800 ) FS ;
+ - FILLER_41_229 gf180mcu_fd_sc_mcu7t5v0__fillcap_8 + SOURCE DIST + PLACED ( 269920 352800 ) FS ;
+ - FILLER_41_237 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 278880 352800 ) FS ;
+ - FILLER_41_243 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 285600 352800 ) FS ;
+ - FILLER_41_247 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 290080 352800 ) FS ;
+ - FILLER_41_251 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 294560 352800 ) FS ;
+ - FILLER_41_265 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 310240 352800 ) FS ;
+ - FILLER_41_274 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 320320 352800 ) FS ;
+ - FILLER_41_283 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 330400 352800 ) FS ;
+ - FILLER_41_286 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 333760 352800 ) FS ;
+ - FILLER_41_293 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 341600 352800 ) FS ;
+ - FILLER_41_300 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 349440 352800 ) FS ;
+ - FILLER_41_302 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 351680 352800 ) FS ;
+ - FILLER_41_314 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 365120 352800 ) FS ;
+ - FILLER_41_318 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 369600 352800 ) FS ;
+ - FILLER_41_320 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 371840 352800 ) FS ;
+ - FILLER_41_326 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 378560 352800 ) FS ;
+ - FILLER_41_34 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 51520 352800 ) FS ;
+ - FILLER_41_354 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 409920 352800 ) FS ;
+ - FILLER_41_357 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 413280 352800 ) FS ;
+ - FILLER_41_36 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 53760 352800 ) FS ;
+ - FILLER_41_360 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 416640 352800 ) FS ;
+ - FILLER_41_364 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 421120 352800 ) FS ;
+ - FILLER_41_397 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 458080 352800 ) FS ;
+ - FILLER_41_409 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 471520 352800 ) FS ;
+ - FILLER_41_411 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 473760 352800 ) FS ;
+ - FILLER_41_416 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 479360 352800 ) FS ;
+ - FILLER_41_425 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 489440 352800 ) FS ;
+ - FILLER_41_428 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 492800 352800 ) FS ;
+ - FILLER_41_431 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 496160 352800 ) FS ;
+ - FILLER_41_435 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 500640 352800 ) FS ;
+ - FILLER_41_449 gf180mcu_fd_sc_mcu7t5v0__fillcap_8 + SOURCE DIST + PLACED ( 516320 352800 ) FS ;
+ - FILLER_41_45 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 63840 352800 ) FS ;
+ - FILLER_41_457 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 525280 352800 ) FS ;
+ - FILLER_41_461 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 529760 352800 ) FS ;
+ - FILLER_41_464 gf180mcu_fd_sc_mcu7t5v0__fillcap_32 + SOURCE DIST + PLACED ( 533120 352800 ) FS ;
+ - FILLER_41_47 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 66080 352800 ) FS ;
+ - FILLER_41_496 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 568960 352800 ) FS ;
+ - FILLER_41_499 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 572320 352800 ) FS ;
+ - FILLER_41_503 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 576800 352800 ) FS ;
+ - FILLER_41_508 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 582400 352800 ) FS ;
+ - FILLER_41_56 gf180mcu_fd_sc_mcu7t5v0__fillcap_8 + SOURCE DIST + PLACED ( 76160 352800 ) FS ;
+ - FILLER_41_64 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 85120 352800 ) FS ;
+ - FILLER_41_68 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 89600 352800 ) FS ;
+ - FILLER_41_70 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 91840 352800 ) FS ;
+ - FILLER_41_73 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 95200 352800 ) FS ;
+ - FILLER_41_77 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 99680 352800 ) FS ;
+ - FILLER_41_79 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 101920 352800 ) FS ;
+ - FILLER_41_82 gf180mcu_fd_sc_mcu7t5v0__fillcap_8 + SOURCE DIST + PLACED ( 105280 352800 ) FS ;
+ - FILLER_41_90 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 114240 352800 ) FS ;
+ - FILLER_41_94 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 118720 352800 ) FS ;
+ - FILLER_41_96 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 120960 352800 ) FS ;
+ - FILLER_42_101 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 126560 360640 ) N ;
+ - FILLER_42_105 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 131040 360640 ) N ;
+ - FILLER_42_108 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 134400 360640 ) N ;
+ - FILLER_42_113 gf180mcu_fd_sc_mcu7t5v0__fillcap_32 + SOURCE DIST + PLACED ( 140000 360640 ) N ;
+ - FILLER_42_145 gf180mcu_fd_sc_mcu7t5v0__fillcap_8 + SOURCE DIST + PLACED ( 175840 360640 ) N ;
+ - FILLER_42_153 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 184800 360640 ) N ;
+ - FILLER_42_157 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 189280 360640 ) N ;
+ - FILLER_42_171 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 204960 360640 ) N ;
+ - FILLER_42_175 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 209440 360640 ) N ;
+ - FILLER_42_179 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 213920 360640 ) N ;
+ - FILLER_42_18 gf180mcu_fd_sc_mcu7t5v0__fillcap_8 + SOURCE DIST + PLACED ( 33600 360640 ) N ;
+ - FILLER_42_186 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 221760 360640 ) N ;
+ - FILLER_42_190 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 226240 360640 ) N ;
+ - FILLER_42_194 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 230720 360640 ) N ;
+ - FILLER_42_196 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 232960 360640 ) N ;
+ - FILLER_42_199 gf180mcu_fd_sc_mcu7t5v0__fillcap_16 + SOURCE DIST + PLACED ( 236320 360640 ) N ;
+ - FILLER_42_2 gf180mcu_fd_sc_mcu7t5v0__fillcap_16 + SOURCE DIST + PLACED ( 15680 360640 ) N ;
+ - FILLER_42_220 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 259840 360640 ) N ;
+ - FILLER_42_224 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 264320 360640 ) N ;
+ - FILLER_42_228 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 268800 360640 ) N ;
+ - FILLER_42_232 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 273280 360640 ) N ;
+ - FILLER_42_242 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 284480 360640 ) N ;
+ - FILLER_42_246 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 288960 360640 ) N ;
+ - FILLER_42_250 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 293440 360640 ) N ;
+ - FILLER_42_254 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 297920 360640 ) N ;
+ - FILLER_42_269 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 314720 360640 ) N ;
+ - FILLER_42_273 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 319200 360640 ) N ;
+ - FILLER_42_284 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 331520 360640 ) N ;
+ - FILLER_42_288 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 336000 360640 ) N ;
+ - FILLER_42_292 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 340480 360640 ) N ;
+ - FILLER_42_296 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 344960 360640 ) N ;
+ - FILLER_42_300 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 349440 360640 ) N ;
+ - FILLER_42_304 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 353920 360640 ) N ;
+ - FILLER_42_312 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 362880 360640 ) N ;
+ - FILLER_42_316 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 367360 360640 ) N ;
+ - FILLER_42_318 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 369600 360640 ) N ;
+ - FILLER_42_321 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 372960 360640 ) N ;
+ - FILLER_42_324 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 376320 360640 ) N ;
+ - FILLER_42_326 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 378560 360640 ) N ;
+ - FILLER_42_337 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 390880 360640 ) N ;
+ - FILLER_42_34 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 51520 360640 ) N ;
+ - FILLER_42_351 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 406560 360640 ) N ;
+ - FILLER_42_355 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 411040 360640 ) N ;
+ - FILLER_42_359 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 415520 360640 ) N ;
+ - FILLER_42_363 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 420000 360640 ) N ;
+ - FILLER_42_365 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 422240 360640 ) N ;
+ - FILLER_42_368 gf180mcu_fd_sc_mcu7t5v0__fillcap_16 + SOURCE DIST + PLACED ( 425600 360640 ) N ;
+ - FILLER_42_37 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 54880 360640 ) N ;
+ - FILLER_42_384 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 443520 360640 ) N ;
+ - FILLER_42_386 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 445760 360640 ) N ;
+ - FILLER_42_389 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 449120 360640 ) N ;
+ - FILLER_42_39 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 57120 360640 ) N ;
+ - FILLER_42_392 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 452480 360640 ) N ;
+ - FILLER_42_401 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 462560 360640 ) N ;
+ - FILLER_42_405 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 467040 360640 ) N ;
+ - FILLER_42_409 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 471520 360640 ) N ;
+ - FILLER_42_413 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 476000 360640 ) N ;
+ - FILLER_42_419 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 482720 360640 ) N ;
+ - FILLER_42_423 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 487200 360640 ) N ;
+ - FILLER_42_427 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 491680 360640 ) N ;
+ - FILLER_42_437 gf180mcu_fd_sc_mcu7t5v0__fillcap_8 + SOURCE DIST + PLACED ( 502880 360640 ) N ;
+ - FILLER_42_445 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 511840 360640 ) N ;
+ - FILLER_42_447 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 514080 360640 ) N ;
+ - FILLER_42_450 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 517440 360640 ) N ;
+ - FILLER_42_460 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 528640 360640 ) N ;
+ - FILLER_42_463 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 532000 360640 ) N ;
+ - FILLER_42_48 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 67200 360640 ) N ;
+ - FILLER_42_493 gf180mcu_fd_sc_mcu7t5v0__fillcap_16 + SOURCE DIST + PLACED ( 565600 360640 ) N ;
+ - FILLER_42_58 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 78400 360640 ) N ;
+ - FILLER_42_66 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 87360 360640 ) N ;
+ - FILLER_42_97 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 122080 360640 ) N ;
+ - FILLER_43_108 gf180mcu_fd_sc_mcu7t5v0__fillcap_16 + SOURCE DIST + PLACED ( 134400 368480 ) FS ;
+ - FILLER_43_124 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 152320 368480 ) FS ;
+ - FILLER_43_128 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 156800 368480 ) FS ;
+ - FILLER_43_136 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 165760 368480 ) FS ;
+ - FILLER_43_140 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 170240 368480 ) FS ;
+ - FILLER_43_144 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 174720 368480 ) FS ;
+ - FILLER_43_153 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 184800 368480 ) FS ;
+ - FILLER_43_157 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 189280 368480 ) FS ;
+ - FILLER_43_161 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 193760 368480 ) FS ;
+ - FILLER_43_163 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 196000 368480 ) FS ;
+ - FILLER_43_166 gf180mcu_fd_sc_mcu7t5v0__fillcap_32 + SOURCE DIST + PLACED ( 199360 368480 ) FS ;
+ - FILLER_43_2 gf180mcu_fd_sc_mcu7t5v0__fillcap_8 + SOURCE DIST + PLACED ( 15680 368480 ) FS ;
+ - FILLER_43_200 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 237440 368480 ) FS ;
+ - FILLER_43_204 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 241920 368480 ) FS ;
+ - FILLER_43_208 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 246400 368480 ) FS ;
+ - FILLER_43_212 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 250880 368480 ) FS ;
+ - FILLER_43_215 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 254240 368480 ) FS ;
+ - FILLER_43_222 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 262080 368480 ) FS ;
+ - FILLER_43_229 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 269920 368480 ) FS ;
+ - FILLER_43_233 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 274400 368480 ) FS ;
+ - FILLER_43_239 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 281120 368480 ) FS ;
+ - FILLER_43_258 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 302400 368480 ) FS ;
+ - FILLER_43_262 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 306880 368480 ) FS ;
+ - FILLER_43_271 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 316960 368480 ) FS ;
+ - FILLER_43_283 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 330400 368480 ) FS ;
+ - FILLER_43_286 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 333760 368480 ) FS ;
+ - FILLER_43_294 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 342720 368480 ) FS ;
+ - FILLER_43_298 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 347200 368480 ) FS ;
+ - FILLER_43_308 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 358400 368480 ) FS ;
+ - FILLER_43_314 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 365120 368480 ) FS ;
+ - FILLER_43_318 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 369600 368480 ) FS ;
+ - FILLER_43_324 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 376320 368480 ) FS ;
+ - FILLER_43_333 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 386400 368480 ) FS ;
+ - FILLER_43_342 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 396480 368480 ) FS ;
+ - FILLER_43_349 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 404320 368480 ) FS ;
+ - FILLER_43_353 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 408800 368480 ) FS ;
+ - FILLER_43_357 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 413280 368480 ) FS ;
+ - FILLER_43_360 gf180mcu_fd_sc_mcu7t5v0__fillcap_16 + SOURCE DIST + PLACED ( 416640 368480 ) FS ;
+ - FILLER_43_376 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 434560 368480 ) FS ;
+ - FILLER_43_380 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 439040 368480 ) FS ;
+ - FILLER_43_383 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 442400 368480 ) FS ;
+ - FILLER_43_39 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 57120 368480 ) FS ;
+ - FILLER_43_393 gf180mcu_fd_sc_mcu7t5v0__fillcap_8 + SOURCE DIST + PLACED ( 453600 368480 ) FS ;
+ - FILLER_43_401 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 462560 368480 ) FS ;
+ - FILLER_43_404 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 465920 368480 ) FS ;
+ - FILLER_43_408 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 470400 368480 ) FS ;
+ - FILLER_43_419 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 482720 368480 ) FS ;
+ - FILLER_43_425 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 489440 368480 ) FS ;
+ - FILLER_43_428 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 492800 368480 ) FS ;
+ - FILLER_43_447 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 514080 368480 ) FS ;
+ - FILLER_43_449 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 516320 368480 ) FS ;
+ - FILLER_43_452 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 519680 368480 ) FS ;
+ - FILLER_43_464 gf180mcu_fd_sc_mcu7t5v0__fillcap_32 + SOURCE DIST + PLACED ( 533120 368480 ) FS ;
+ - FILLER_43_496 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 568960 368480 ) FS ;
+ - FILLER_43_499 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 572320 368480 ) FS ;
+ - FILLER_43_503 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 576800 368480 ) FS ;
+ - FILLER_43_508 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 582400 368480 ) FS ;
+ - FILLER_43_70 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 91840 368480 ) FS ;
+ - FILLER_43_73 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 95200 368480 ) FS ;
+ - FILLER_43_76 gf180mcu_fd_sc_mcu7t5v0__fillcap_32 + SOURCE DIST + PLACED ( 98560 368480 ) FS ;
+ - FILLER_44_105 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 131040 376320 ) N ;
+ - FILLER_44_108 gf180mcu_fd_sc_mcu7t5v0__fillcap_8 + SOURCE DIST + PLACED ( 134400 376320 ) N ;
+ - FILLER_44_116 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 143360 376320 ) N ;
+ - FILLER_44_119 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 146720 376320 ) N ;
+ - FILLER_44_150 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 181440 376320 ) N ;
+ - FILLER_44_154 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 185920 376320 ) N ;
+ - FILLER_44_165 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 198240 376320 ) N ;
+ - FILLER_44_171 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 204960 376320 ) N ;
+ - FILLER_44_175 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 209440 376320 ) N ;
+ - FILLER_44_179 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 213920 376320 ) N ;
+ - FILLER_44_2 gf180mcu_fd_sc_mcu7t5v0__fillcap_32 + SOURCE DIST + PLACED ( 15680 376320 ) N ;
+ - FILLER_44_206 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 244160 376320 ) N ;
+ - FILLER_44_218 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 257600 376320 ) N ;
+ - FILLER_44_224 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 264320 376320 ) N ;
+ - FILLER_44_226 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 266560 376320 ) N ;
+ - FILLER_44_246 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 288960 376320 ) N ;
+ - FILLER_44_250 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 293440 376320 ) N ;
+ - FILLER_44_259 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 303520 376320 ) N ;
+ - FILLER_44_268 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 313600 376320 ) N ;
+ - FILLER_44_270 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 315840 376320 ) N ;
+ - FILLER_44_273 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 319200 376320 ) N ;
+ - FILLER_44_282 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 329280 376320 ) N ;
+ - FILLER_44_286 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 333760 376320 ) N ;
+ - FILLER_44_288 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 336000 376320 ) N ;
+ - FILLER_44_318 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 369600 376320 ) N ;
+ - FILLER_44_321 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 372960 376320 ) N ;
+ - FILLER_44_324 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 376320 376320 ) N ;
+ - FILLER_44_328 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 380800 376320 ) N ;
+ - FILLER_44_34 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 51520 376320 ) N ;
+ - FILLER_44_362 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 418880 376320 ) N ;
+ - FILLER_44_366 gf180mcu_fd_sc_mcu7t5v0__fillcap_16 + SOURCE DIST + PLACED ( 423360 376320 ) N ;
+ - FILLER_44_37 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 54880 376320 ) N ;
+ - FILLER_44_382 gf180mcu_fd_sc_mcu7t5v0__fillcap_8 + SOURCE DIST + PLACED ( 441280 376320 ) N ;
+ - FILLER_44_392 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 452480 376320 ) N ;
+ - FILLER_44_396 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 456960 376320 ) N ;
+ - FILLER_44_399 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 460320 376320 ) N ;
+ - FILLER_44_408 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 470400 376320 ) N ;
+ - FILLER_44_41 gf180mcu_fd_sc_mcu7t5v0__fillcap_64 + SOURCE DIST + PLACED ( 59360 376320 ) N ;
+ - FILLER_44_436 gf180mcu_fd_sc_mcu7t5v0__fillcap_8 + SOURCE DIST + PLACED ( 501760 376320 ) N ;
+ - FILLER_44_452 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 519680 376320 ) N ;
+ - FILLER_44_456 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 524160 376320 ) N ;
+ - FILLER_44_460 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 528640 376320 ) N ;
+ - FILLER_44_463 gf180mcu_fd_sc_mcu7t5v0__fillcap_32 + SOURCE DIST + PLACED ( 532000 376320 ) N ;
+ - FILLER_44_495 gf180mcu_fd_sc_mcu7t5v0__fillcap_8 + SOURCE DIST + PLACED ( 567840 376320 ) N ;
+ - FILLER_44_503 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 576800 376320 ) N ;
+ - FILLER_44_507 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 581280 376320 ) N ;
+ - FILLER_45_137 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 166880 384160 ) FS ;
+ - FILLER_45_141 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 171360 384160 ) FS ;
+ - FILLER_45_144 gf180mcu_fd_sc_mcu7t5v0__fillcap_8 + SOURCE DIST + PLACED ( 174720 384160 ) FS ;
+ - FILLER_45_164 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 197120 384160 ) FS ;
+ - FILLER_45_173 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 207200 384160 ) FS ;
+ - FILLER_45_189 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 225120 384160 ) FS ;
+ - FILLER_45_195 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 231840 384160 ) FS ;
+ - FILLER_45_199 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 236320 384160 ) FS ;
+ - FILLER_45_2 gf180mcu_fd_sc_mcu7t5v0__fillcap_64 + SOURCE DIST + PLACED ( 15680 384160 ) FS ;
+ - FILLER_45_212 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 250880 384160 ) FS ;
+ - FILLER_45_215 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 254240 384160 ) FS ;
+ - FILLER_45_226 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 266560 384160 ) FS ;
+ - FILLER_45_236 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 277760 384160 ) FS ;
+ - FILLER_45_246 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 288960 384160 ) FS ;
+ - FILLER_45_250 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 293440 384160 ) FS ;
+ - FILLER_45_254 gf180mcu_fd_sc_mcu7t5v0__fillcap_16 + SOURCE DIST + PLACED ( 297920 384160 ) FS ;
+ - FILLER_45_270 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 315840 384160 ) FS ;
+ - FILLER_45_277 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 323680 384160 ) FS ;
+ - FILLER_45_279 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 325920 384160 ) FS ;
+ - FILLER_45_282 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 329280 384160 ) FS ;
+ - FILLER_45_286 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 333760 384160 ) FS ;
+ - FILLER_45_290 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 338240 384160 ) FS ;
+ - FILLER_45_293 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 341600 384160 ) FS ;
+ - FILLER_45_297 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 346080 384160 ) FS ;
+ - FILLER_45_299 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 348320 384160 ) FS ;
+ - FILLER_45_305 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 355040 384160 ) FS ;
+ - FILLER_45_309 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 359520 384160 ) FS ;
+ - FILLER_45_313 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 364000 384160 ) FS ;
+ - FILLER_45_323 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 375200 384160 ) FS ;
+ - FILLER_45_351 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 406560 384160 ) FS ;
+ - FILLER_45_357 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 413280 384160 ) FS ;
+ - FILLER_45_360 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 416640 384160 ) FS ;
+ - FILLER_45_362 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 418880 384160 ) FS ;
+ - FILLER_45_371 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 428960 384160 ) FS ;
+ - FILLER_45_375 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 433440 384160 ) FS ;
+ - FILLER_45_408 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 470400 384160 ) FS ;
+ - FILLER_45_410 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 472640 384160 ) FS ;
+ - FILLER_45_421 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 484960 384160 ) FS ;
+ - FILLER_45_425 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 489440 384160 ) FS ;
+ - FILLER_45_428 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 492800 384160 ) FS ;
+ - FILLER_45_437 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 502880 384160 ) FS ;
+ - FILLER_45_441 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 507360 384160 ) FS ;
+ - FILLER_45_451 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 518560 384160 ) FS ;
+ - FILLER_45_482 gf180mcu_fd_sc_mcu7t5v0__fillcap_8 + SOURCE DIST + PLACED ( 553280 384160 ) FS ;
+ - FILLER_45_490 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 562240 384160 ) FS ;
+ - FILLER_45_494 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 566720 384160 ) FS ;
+ - FILLER_45_496 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 568960 384160 ) FS ;
+ - FILLER_45_499 gf180mcu_fd_sc_mcu7t5v0__fillcap_8 + SOURCE DIST + PLACED ( 572320 384160 ) FS ;
+ - FILLER_45_507 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 581280 384160 ) FS ;
+ - FILLER_45_66 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 87360 384160 ) FS ;
+ - FILLER_45_70 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 91840 384160 ) FS ;
+ - FILLER_45_73 gf180mcu_fd_sc_mcu7t5v0__fillcap_64 + SOURCE DIST + PLACED ( 95200 384160 ) FS ;
+ - FILLER_46_101 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 126560 392000 ) N ;
+ - FILLER_46_105 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 131040 392000 ) N ;
+ - FILLER_46_108 gf180mcu_fd_sc_mcu7t5v0__fillcap_32 + SOURCE DIST + PLACED ( 134400 392000 ) N ;
+ - FILLER_46_140 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 170240 392000 ) N ;
+ - FILLER_46_144 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 174720 392000 ) N ;
+ - FILLER_46_146 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 176960 392000 ) N ;
+ - FILLER_46_149 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 180320 392000 ) N ;
+ - FILLER_46_153 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 184800 392000 ) N ;
+ - FILLER_46_160 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 192640 392000 ) N ;
+ - FILLER_46_176 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 210560 392000 ) N ;
+ - FILLER_46_179 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 213920 392000 ) N ;
+ - FILLER_46_182 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 217280 392000 ) N ;
+ - FILLER_46_2 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 15680 392000 ) N ;
+ - FILLER_46_213 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 252000 392000 ) N ;
+ - FILLER_46_217 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 256480 392000 ) N ;
+ - FILLER_46_219 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 258720 392000 ) N ;
+ - FILLER_46_226 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 266560 392000 ) N ;
+ - FILLER_46_23 gf180mcu_fd_sc_mcu7t5v0__fillcap_8 + SOURCE DIST + PLACED ( 39200 392000 ) N ;
+ - FILLER_46_230 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 271040 392000 ) N ;
+ - FILLER_46_234 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 275520 392000 ) N ;
+ - FILLER_46_241 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 283360 392000 ) N ;
+ - FILLER_46_245 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 287840 392000 ) N ;
+ - FILLER_46_247 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 290080 392000 ) N ;
+ - FILLER_46_250 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 293440 392000 ) N ;
+ - FILLER_46_280 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 327040 392000 ) N ;
+ - FILLER_46_291 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 339360 392000 ) N ;
+ - FILLER_46_301 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 350560 392000 ) N ;
+ - FILLER_46_305 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 355040 392000 ) N ;
+ - FILLER_46_309 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 359520 392000 ) N ;
+ - FILLER_46_31 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 48160 392000 ) N ;
+ - FILLER_46_311 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 361760 392000 ) N ;
+ - FILLER_46_314 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 365120 392000 ) N ;
+ - FILLER_46_318 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 369600 392000 ) N ;
+ - FILLER_46_321 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 372960 392000 ) N ;
+ - FILLER_46_328 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 380800 392000 ) N ;
+ - FILLER_46_341 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 395360 392000 ) N ;
+ - FILLER_46_37 gf180mcu_fd_sc_mcu7t5v0__fillcap_64 + SOURCE DIST + PLACED ( 54880 392000 ) N ;
+ - FILLER_46_372 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 430080 392000 ) N ;
+ - FILLER_46_382 gf180mcu_fd_sc_mcu7t5v0__fillcap_8 + SOURCE DIST + PLACED ( 441280 392000 ) N ;
+ - FILLER_46_392 gf180mcu_fd_sc_mcu7t5v0__fillcap_16 + SOURCE DIST + PLACED ( 452480 392000 ) N ;
+ - FILLER_46_410 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 472640 392000 ) N ;
+ - FILLER_46_414 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 477120 392000 ) N ;
+ - FILLER_46_418 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 481600 392000 ) N ;
+ - FILLER_46_426 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 490560 392000 ) N ;
+ - FILLER_46_430 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 495040 392000 ) N ;
+ - FILLER_46_434 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 499520 392000 ) N ;
+ - FILLER_46_441 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 507360 392000 ) N ;
+ - FILLER_46_443 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 509600 392000 ) N ;
+ - FILLER_46_446 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 512960 392000 ) N ;
+ - FILLER_46_456 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 524160 392000 ) N ;
+ - FILLER_46_460 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 528640 392000 ) N ;
+ - FILLER_46_463 gf180mcu_fd_sc_mcu7t5v0__fillcap_32 + SOURCE DIST + PLACED ( 532000 392000 ) N ;
+ - FILLER_46_495 gf180mcu_fd_sc_mcu7t5v0__fillcap_8 + SOURCE DIST + PLACED ( 567840 392000 ) N ;
+ - FILLER_46_503 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 576800 392000 ) N ;
+ - FILLER_46_508 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 582400 392000 ) N ;
+ - FILLER_46_7 gf180mcu_fd_sc_mcu7t5v0__fillcap_16 + SOURCE DIST + PLACED ( 21280 392000 ) N ;
+ - FILLER_47_137 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 166880 399840 ) FS ;
+ - FILLER_47_141 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 171360 399840 ) FS ;
+ - FILLER_47_144 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 174720 399840 ) FS ;
+ - FILLER_47_153 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 184800 399840 ) FS ;
+ - FILLER_47_163 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 196000 399840 ) FS ;
+ - FILLER_47_170 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 203840 399840 ) FS ;
+ - FILLER_47_179 gf180mcu_fd_sc_mcu7t5v0__fillcap_8 + SOURCE DIST + PLACED ( 213920 399840 ) FS ;
+ - FILLER_47_193 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 229600 399840 ) FS ;
+ - FILLER_47_197 gf180mcu_fd_sc_mcu7t5v0__fillcap_16 + SOURCE DIST + PLACED ( 234080 399840 ) FS ;
+ - FILLER_47_2 gf180mcu_fd_sc_mcu7t5v0__fillcap_64 + SOURCE DIST + PLACED ( 15680 399840 ) FS ;
+ - FILLER_47_215 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 254240 399840 ) FS ;
+ - FILLER_47_218 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 257600 399840 ) FS ;
+ - FILLER_47_222 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 262080 399840 ) FS ;
+ - FILLER_47_226 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 266560 399840 ) FS ;
+ - FILLER_47_233 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 274400 399840 ) FS ;
+ - FILLER_47_261 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 305760 399840 ) FS ;
+ - FILLER_47_277 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 323680 399840 ) FS ;
+ - FILLER_47_283 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 330400 399840 ) FS ;
+ - FILLER_47_286 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 333760 399840 ) FS ;
+ - FILLER_47_290 gf180mcu_fd_sc_mcu7t5v0__fillcap_8 + SOURCE DIST + PLACED ( 338240 399840 ) FS ;
+ - FILLER_47_298 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 347200 399840 ) FS ;
+ - FILLER_47_330 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 383040 399840 ) FS ;
+ - FILLER_47_334 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 387520 399840 ) FS ;
+ - FILLER_47_338 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 392000 399840 ) FS ;
+ - FILLER_47_342 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 396480 399840 ) FS ;
+ - FILLER_47_346 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 400960 399840 ) FS ;
+ - FILLER_47_350 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 405440 399840 ) FS ;
+ - FILLER_47_354 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 409920 399840 ) FS ;
+ - FILLER_47_357 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 413280 399840 ) FS ;
+ - FILLER_47_360 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 416640 399840 ) FS ;
+ - FILLER_47_364 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 421120 399840 ) FS ;
+ - FILLER_47_366 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 423360 399840 ) FS ;
+ - FILLER_47_369 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 426720 399840 ) FS ;
+ - FILLER_47_377 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 435680 399840 ) FS ;
+ - FILLER_47_387 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 446880 399840 ) FS ;
+ - FILLER_47_391 gf180mcu_fd_sc_mcu7t5v0__fillcap_16 + SOURCE DIST + PLACED ( 451360 399840 ) FS ;
+ - FILLER_47_407 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 469280 399840 ) FS ;
+ - FILLER_47_411 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 473760 399840 ) FS ;
+ - FILLER_47_414 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 477120 399840 ) FS ;
+ - FILLER_47_418 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 481600 399840 ) FS ;
+ - FILLER_47_425 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 489440 399840 ) FS ;
+ - FILLER_47_428 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 492800 399840 ) FS ;
+ - FILLER_47_437 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 502880 399840 ) FS ;
+ - FILLER_47_441 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 507360 399840 ) FS ;
+ - FILLER_47_445 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 511840 399840 ) FS ;
+ - FILLER_47_448 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 515200 399840 ) FS ;
+ - FILLER_47_452 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 519680 399840 ) FS ;
+ - FILLER_47_461 gf180mcu_fd_sc_mcu7t5v0__fillcap_32 + SOURCE DIST + PLACED ( 529760 399840 ) FS ;
+ - FILLER_47_493 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 565600 399840 ) FS ;
+ - FILLER_47_499 gf180mcu_fd_sc_mcu7t5v0__fillcap_8 + SOURCE DIST + PLACED ( 572320 399840 ) FS ;
+ - FILLER_47_507 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 581280 399840 ) FS ;
+ - FILLER_47_66 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 87360 399840 ) FS ;
+ - FILLER_47_70 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 91840 399840 ) FS ;
+ - FILLER_47_73 gf180mcu_fd_sc_mcu7t5v0__fillcap_64 + SOURCE DIST + PLACED ( 95200 399840 ) FS ;
+ - FILLER_48_101 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 126560 407680 ) N ;
+ - FILLER_48_105 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 131040 407680 ) N ;
+ - FILLER_48_108 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 134400 407680 ) N ;
+ - FILLER_48_112 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 138880 407680 ) N ;
+ - FILLER_48_116 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 143360 407680 ) N ;
+ - FILLER_48_147 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 178080 407680 ) N ;
+ - FILLER_48_151 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 182560 407680 ) N ;
+ - FILLER_48_160 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 192640 407680 ) N ;
+ - FILLER_48_162 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 194880 407680 ) N ;
+ - FILLER_48_165 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 198240 407680 ) N ;
+ - FILLER_48_169 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 202720 407680 ) N ;
+ - FILLER_48_172 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 206080 407680 ) N ;
+ - FILLER_48_176 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 210560 407680 ) N ;
+ - FILLER_48_179 gf180mcu_fd_sc_mcu7t5v0__fillcap_16 + SOURCE DIST + PLACED ( 213920 407680 ) N ;
+ - FILLER_48_195 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 231840 407680 ) N ;
+ - FILLER_48_198 gf180mcu_fd_sc_mcu7t5v0__fillcap_8 + SOURCE DIST + PLACED ( 235200 407680 ) N ;
+ - FILLER_48_2 gf180mcu_fd_sc_mcu7t5v0__fillcap_32 + SOURCE DIST + PLACED ( 15680 407680 ) N ;
+ - FILLER_48_206 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 244160 407680 ) N ;
+ - FILLER_48_210 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 248640 407680 ) N ;
+ - FILLER_48_214 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 253120 407680 ) N ;
+ - FILLER_48_218 gf180mcu_fd_sc_mcu7t5v0__fillcap_16 + SOURCE DIST + PLACED ( 257600 407680 ) N ;
+ - FILLER_48_234 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 275520 407680 ) N ;
+ - FILLER_48_237 gf180mcu_fd_sc_mcu7t5v0__fillcap_8 + SOURCE DIST + PLACED ( 278880 407680 ) N ;
+ - FILLER_48_245 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 287840 407680 ) N ;
+ - FILLER_48_247 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 290080 407680 ) N ;
+ - FILLER_48_250 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 293440 407680 ) N ;
+ - FILLER_48_257 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 301280 407680 ) N ;
+ - FILLER_48_263 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 308000 407680 ) N ;
+ - FILLER_48_267 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 312480 407680 ) N ;
+ - FILLER_48_277 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 323680 407680 ) N ;
+ - FILLER_48_287 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 334880 407680 ) N ;
+ - FILLER_48_289 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 337120 407680 ) N ;
+ - FILLER_48_303 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 352800 407680 ) N ;
+ - FILLER_48_311 gf180mcu_fd_sc_mcu7t5v0__fillcap_8 + SOURCE DIST + PLACED ( 361760 407680 ) N ;
+ - FILLER_48_321 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 372960 407680 ) N ;
+ - FILLER_48_34 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 51520 407680 ) N ;
+ - FILLER_48_351 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 406560 407680 ) N ;
+ - FILLER_48_37 gf180mcu_fd_sc_mcu7t5v0__fillcap_64 + SOURCE DIST + PLACED ( 54880 407680 ) N ;
+ - FILLER_48_382 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 441280 407680 ) N ;
+ - FILLER_48_386 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 445760 407680 ) N ;
+ - FILLER_48_392 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 452480 407680 ) N ;
+ - FILLER_48_395 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 455840 407680 ) N ;
+ - FILLER_48_403 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 464800 407680 ) N ;
+ - FILLER_48_407 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 469280 407680 ) N ;
+ - FILLER_48_437 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 502880 407680 ) N ;
+ - FILLER_48_441 gf180mcu_fd_sc_mcu7t5v0__fillcap_8 + SOURCE DIST + PLACED ( 507360 407680 ) N ;
+ - FILLER_48_449 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 516320 407680 ) N ;
+ - FILLER_48_453 gf180mcu_fd_sc_mcu7t5v0__fillcap_8 + SOURCE DIST + PLACED ( 520800 407680 ) N ;
+ - FILLER_48_463 gf180mcu_fd_sc_mcu7t5v0__fillcap_32 + SOURCE DIST + PLACED ( 532000 407680 ) N ;
+ - FILLER_48_495 gf180mcu_fd_sc_mcu7t5v0__fillcap_8 + SOURCE DIST + PLACED ( 567840 407680 ) N ;
+ - FILLER_48_503 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 576800 407680 ) N ;
+ - FILLER_48_507 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 581280 407680 ) N ;
+ - FILLER_49_137 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 166880 415520 ) FS ;
+ - FILLER_49_141 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 171360 415520 ) FS ;
+ - FILLER_49_144 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 174720 415520 ) FS ;
+ - FILLER_49_153 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 184800 415520 ) FS ;
+ - FILLER_49_157 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 189280 415520 ) FS ;
+ - FILLER_49_161 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 193760 415520 ) FS ;
+ - FILLER_49_166 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 199360 415520 ) FS ;
+ - FILLER_49_170 gf180mcu_fd_sc_mcu7t5v0__fillcap_8 + SOURCE DIST + PLACED ( 203840 415520 ) FS ;
+ - FILLER_49_178 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 212800 415520 ) FS ;
+ - FILLER_49_182 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 217280 415520 ) FS ;
+ - FILLER_49_2 gf180mcu_fd_sc_mcu7t5v0__fillcap_64 + SOURCE DIST + PLACED ( 15680 415520 ) FS ;
+ - FILLER_49_212 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 250880 415520 ) FS ;
+ - FILLER_49_215 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 254240 415520 ) FS ;
+ - FILLER_49_217 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 256480 415520 ) FS ;
+ - FILLER_49_247 gf180mcu_fd_sc_mcu7t5v0__fillcap_16 + SOURCE DIST + PLACED ( 290080 415520 ) FS ;
+ - FILLER_49_263 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 308000 415520 ) FS ;
+ - FILLER_49_267 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 312480 415520 ) FS ;
+ - FILLER_49_271 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 316960 415520 ) FS ;
+ - FILLER_49_280 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 327040 415520 ) FS ;
+ - FILLER_49_286 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 333760 415520 ) FS ;
+ - FILLER_49_289 gf180mcu_fd_sc_mcu7t5v0__fillcap_8 + SOURCE DIST + PLACED ( 337120 415520 ) FS ;
+ - FILLER_49_297 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 346080 415520 ) FS ;
+ - FILLER_49_301 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 350560 415520 ) FS ;
+ - FILLER_49_305 gf180mcu_fd_sc_mcu7t5v0__fillcap_16 + SOURCE DIST + PLACED ( 355040 415520 ) FS ;
+ - FILLER_49_321 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 372960 415520 ) FS ;
+ - FILLER_49_323 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 375200 415520 ) FS ;
+ - FILLER_49_326 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 378560 415520 ) FS ;
+ - FILLER_49_354 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 409920 415520 ) FS ;
+ - FILLER_49_357 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 413280 415520 ) FS ;
+ - FILLER_49_366 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 423360 415520 ) FS ;
+ - FILLER_49_370 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 427840 415520 ) FS ;
+ - FILLER_49_374 gf180mcu_fd_sc_mcu7t5v0__fillcap_8 + SOURCE DIST + PLACED ( 432320 415520 ) FS ;
+ - FILLER_49_382 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 441280 415520 ) FS ;
+ - FILLER_49_415 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 478240 415520 ) FS ;
+ - FILLER_49_419 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 482720 415520 ) FS ;
+ - FILLER_49_425 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 489440 415520 ) FS ;
+ - FILLER_49_428 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 492800 415520 ) FS ;
+ - FILLER_49_432 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 497280 415520 ) FS ;
+ - FILLER_49_463 gf180mcu_fd_sc_mcu7t5v0__fillcap_32 + SOURCE DIST + PLACED ( 532000 415520 ) FS ;
+ - FILLER_49_495 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 567840 415520 ) FS ;
+ - FILLER_49_499 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 572320 415520 ) FS ;
+ - FILLER_49_503 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 576800 415520 ) FS ;
+ - FILLER_49_508 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 582400 415520 ) FS ;
+ - FILLER_49_66 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 87360 415520 ) FS ;
+ - FILLER_49_70 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 91840 415520 ) FS ;
+ - FILLER_49_73 gf180mcu_fd_sc_mcu7t5v0__fillcap_64 + SOURCE DIST + PLACED ( 95200 415520 ) FS ;
+ - FILLER_4_101 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 126560 62720 ) N ;
+ - FILLER_4_105 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 131040 62720 ) N ;
+ - FILLER_4_108 gf180mcu_fd_sc_mcu7t5v0__fillcap_64 + SOURCE DIST + PLACED ( 134400 62720 ) N ;
+ - FILLER_4_172 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 206080 62720 ) N ;
+ - FILLER_4_176 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 210560 62720 ) N ;
+ - FILLER_4_179 gf180mcu_fd_sc_mcu7t5v0__fillcap_64 + SOURCE DIST + PLACED ( 213920 62720 ) N ;
+ - FILLER_4_2 gf180mcu_fd_sc_mcu7t5v0__fillcap_32 + SOURCE DIST + PLACED ( 15680 62720 ) N ;
+ - FILLER_4_243 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 285600 62720 ) N ;
+ - FILLER_4_247 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 290080 62720 ) N ;
+ - FILLER_4_250 gf180mcu_fd_sc_mcu7t5v0__fillcap_64 + SOURCE DIST + PLACED ( 293440 62720 ) N ;
+ - FILLER_4_314 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 365120 62720 ) N ;
+ - FILLER_4_318 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 369600 62720 ) N ;
+ - FILLER_4_321 gf180mcu_fd_sc_mcu7t5v0__fillcap_64 + SOURCE DIST + PLACED ( 372960 62720 ) N ;
+ - FILLER_4_34 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 51520 62720 ) N ;
+ - FILLER_4_37 gf180mcu_fd_sc_mcu7t5v0__fillcap_64 + SOURCE DIST + PLACED ( 54880 62720 ) N ;
+ - FILLER_4_385 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 444640 62720 ) N ;
+ - FILLER_4_389 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 449120 62720 ) N ;
+ - FILLER_4_392 gf180mcu_fd_sc_mcu7t5v0__fillcap_64 + SOURCE DIST + PLACED ( 452480 62720 ) N ;
+ - FILLER_4_456 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 524160 62720 ) N ;
+ - FILLER_4_460 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 528640 62720 ) N ;
+ - FILLER_4_463 gf180mcu_fd_sc_mcu7t5v0__fillcap_32 + SOURCE DIST + PLACED ( 532000 62720 ) N ;
+ - FILLER_4_495 gf180mcu_fd_sc_mcu7t5v0__fillcap_8 + SOURCE DIST + PLACED ( 567840 62720 ) N ;
+ - FILLER_4_503 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 576800 62720 ) N ;
+ - FILLER_4_507 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 581280 62720 ) N ;
+ - FILLER_50_101 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 126560 423360 ) N ;
+ - FILLER_50_105 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 131040 423360 ) N ;
+ - FILLER_50_108 gf180mcu_fd_sc_mcu7t5v0__fillcap_32 + SOURCE DIST + PLACED ( 134400 423360 ) N ;
+ - FILLER_50_140 gf180mcu_fd_sc_mcu7t5v0__fillcap_8 + SOURCE DIST + PLACED ( 170240 423360 ) N ;
+ - FILLER_50_148 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 179200 423360 ) N ;
+ - FILLER_50_152 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 183680 423360 ) N ;
+ - FILLER_50_165 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 198240 423360 ) N ;
+ - FILLER_50_169 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 202720 423360 ) N ;
+ - FILLER_50_173 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 207200 423360 ) N ;
+ - FILLER_50_176 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 210560 423360 ) N ;
+ - FILLER_50_179 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 213920 423360 ) N ;
+ - FILLER_50_181 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 216160 423360 ) N ;
+ - FILLER_50_194 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 230720 423360 ) N ;
+ - FILLER_50_2 gf180mcu_fd_sc_mcu7t5v0__fillcap_32 + SOURCE DIST + PLACED ( 15680 423360 ) N ;
+ - FILLER_50_206 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 244160 423360 ) N ;
+ - FILLER_50_213 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 252000 423360 ) N ;
+ - FILLER_50_217 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 256480 423360 ) N ;
+ - FILLER_50_221 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 260960 423360 ) N ;
+ - FILLER_50_225 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 265440 423360 ) N ;
+ - FILLER_50_232 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 273280 423360 ) N ;
+ - FILLER_50_244 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 286720 423360 ) N ;
+ - FILLER_50_250 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 293440 423360 ) N ;
+ - FILLER_50_253 gf180mcu_fd_sc_mcu7t5v0__fillcap_8 + SOURCE DIST + PLACED ( 296800 423360 ) N ;
+ - FILLER_50_261 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 305760 423360 ) N ;
+ - FILLER_50_271 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 316960 423360 ) N ;
+ - FILLER_50_275 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 321440 423360 ) N ;
+ - FILLER_50_282 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 329280 423360 ) N ;
+ - FILLER_50_286 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 333760 423360 ) N ;
+ - FILLER_50_290 gf180mcu_fd_sc_mcu7t5v0__fillcap_16 + SOURCE DIST + PLACED ( 338240 423360 ) N ;
+ - FILLER_50_306 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 356160 423360 ) N ;
+ - FILLER_50_310 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 360640 423360 ) N ;
+ - FILLER_50_316 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 367360 423360 ) N ;
+ - FILLER_50_318 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 369600 423360 ) N ;
+ - FILLER_50_321 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 372960 423360 ) N ;
+ - FILLER_50_324 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 376320 423360 ) N ;
+ - FILLER_50_328 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 380800 423360 ) N ;
+ - FILLER_50_330 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 383040 423360 ) N ;
+ - FILLER_50_339 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 393120 423360 ) N ;
+ - FILLER_50_34 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 51520 423360 ) N ;
+ - FILLER_50_349 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 404320 423360 ) N ;
+ - FILLER_50_358 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 414400 423360 ) N ;
+ - FILLER_50_365 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 422240 423360 ) N ;
+ - FILLER_50_369 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 426720 423360 ) N ;
+ - FILLER_50_37 gf180mcu_fd_sc_mcu7t5v0__fillcap_64 + SOURCE DIST + PLACED ( 54880 423360 ) N ;
+ - FILLER_50_373 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 431200 423360 ) N ;
+ - FILLER_50_377 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 435680 423360 ) N ;
+ - FILLER_50_381 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 440160 423360 ) N ;
+ - FILLER_50_385 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 444640 423360 ) N ;
+ - FILLER_50_389 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 449120 423360 ) N ;
+ - FILLER_50_392 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 452480 423360 ) N ;
+ - FILLER_50_402 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 463680 423360 ) N ;
+ - FILLER_50_430 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 495040 423360 ) N ;
+ - FILLER_50_440 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 506240 423360 ) N ;
+ - FILLER_50_448 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 515200 423360 ) N ;
+ - FILLER_50_452 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 519680 423360 ) N ;
+ - FILLER_50_456 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 524160 423360 ) N ;
+ - FILLER_50_460 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 528640 423360 ) N ;
+ - FILLER_50_463 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 532000 423360 ) N ;
+ - FILLER_50_472 gf180mcu_fd_sc_mcu7t5v0__fillcap_16 + SOURCE DIST + PLACED ( 542080 423360 ) N ;
+ - FILLER_50_488 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 560000 423360 ) N ;
+ - FILLER_50_492 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 564480 423360 ) N ;
+ - FILLER_50_495 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 567840 423360 ) N ;
+ - FILLER_50_503 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 576800 423360 ) N ;
+ - FILLER_50_507 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 581280 423360 ) N ;
+ - FILLER_51_137 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 166880 431200 ) FS ;
+ - FILLER_51_141 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 171360 431200 ) FS ;
+ - FILLER_51_144 gf180mcu_fd_sc_mcu7t5v0__fillcap_8 + SOURCE DIST + PLACED ( 174720 431200 ) FS ;
+ - FILLER_51_152 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 183680 431200 ) FS ;
+ - FILLER_51_159 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 191520 431200 ) FS ;
+ - FILLER_51_167 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 200480 431200 ) FS ;
+ - FILLER_51_177 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 211680 431200 ) FS ;
+ - FILLER_51_186 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 221760 431200 ) FS ;
+ - FILLER_51_188 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 224000 431200 ) FS ;
+ - FILLER_51_195 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 231840 431200 ) FS ;
+ - FILLER_51_2 gf180mcu_fd_sc_mcu7t5v0__fillcap_64 + SOURCE DIST + PLACED ( 15680 431200 ) FS ;
+ - FILLER_51_212 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 250880 431200 ) FS ;
+ - FILLER_51_215 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 254240 431200 ) FS ;
+ - FILLER_51_218 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 257600 431200 ) FS ;
+ - FILLER_51_224 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 264320 431200 ) FS ;
+ - FILLER_51_228 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 268800 431200 ) FS ;
+ - FILLER_51_232 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 273280 431200 ) FS ;
+ - FILLER_51_242 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 284480 431200 ) FS ;
+ - FILLER_51_252 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 295680 431200 ) FS ;
+ - FILLER_51_283 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 330400 431200 ) FS ;
+ - FILLER_51_286 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 333760 431200 ) FS ;
+ - FILLER_51_316 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 367360 431200 ) FS ;
+ - FILLER_51_326 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 378560 431200 ) FS ;
+ - FILLER_51_330 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 383040 431200 ) FS ;
+ - FILLER_51_340 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 394240 431200 ) FS ;
+ - FILLER_51_350 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 405440 431200 ) FS ;
+ - FILLER_51_354 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 409920 431200 ) FS ;
+ - FILLER_51_357 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 413280 431200 ) FS ;
+ - FILLER_51_368 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 425600 431200 ) FS ;
+ - FILLER_51_372 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 430080 431200 ) FS ;
+ - FILLER_51_376 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 434560 431200 ) FS ;
+ - FILLER_51_408 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 470400 431200 ) FS ;
+ - FILLER_51_422 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 486080 431200 ) FS ;
+ - FILLER_51_428 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 492800 431200 ) FS ;
+ - FILLER_51_431 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 496160 431200 ) FS ;
+ - FILLER_51_442 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 508480 431200 ) FS ;
+ - FILLER_51_450 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 517440 431200 ) FS ;
+ - FILLER_51_454 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 521920 431200 ) FS ;
+ - FILLER_51_485 gf180mcu_fd_sc_mcu7t5v0__fillcap_8 + SOURCE DIST + PLACED ( 556640 431200 ) FS ;
+ - FILLER_51_493 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 565600 431200 ) FS ;
+ - FILLER_51_499 gf180mcu_fd_sc_mcu7t5v0__fillcap_8 + SOURCE DIST + PLACED ( 572320 431200 ) FS ;
+ - FILLER_51_507 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 581280 431200 ) FS ;
+ - FILLER_51_66 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 87360 431200 ) FS ;
+ - FILLER_51_70 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 91840 431200 ) FS ;
+ - FILLER_51_73 gf180mcu_fd_sc_mcu7t5v0__fillcap_64 + SOURCE DIST + PLACED ( 95200 431200 ) FS ;
+ - FILLER_52_101 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 126560 439040 ) N ;
+ - FILLER_52_105 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 131040 439040 ) N ;
+ - FILLER_52_108 gf180mcu_fd_sc_mcu7t5v0__fillcap_16 + SOURCE DIST + PLACED ( 134400 439040 ) N ;
+ - FILLER_52_124 gf180mcu_fd_sc_mcu7t5v0__fillcap_8 + SOURCE DIST + PLACED ( 152320 439040 ) N ;
+ - FILLER_52_132 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 161280 439040 ) N ;
+ - FILLER_52_136 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 165760 439040 ) N ;
+ - FILLER_52_166 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 199360 439040 ) N ;
+ - FILLER_52_17 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 32480 439040 ) N ;
+ - FILLER_52_170 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 203840 439040 ) N ;
+ - FILLER_52_176 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 210560 439040 ) N ;
+ - FILLER_52_179 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 213920 439040 ) N ;
+ - FILLER_52_188 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 224000 439040 ) N ;
+ - FILLER_52_192 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 228480 439040 ) N ;
+ - FILLER_52_194 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 230720 439040 ) N ;
+ - FILLER_52_197 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 234080 439040 ) N ;
+ - FILLER_52_2 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 15680 439040 ) N ;
+ - FILLER_52_21 gf180mcu_fd_sc_mcu7t5v0__fillcap_8 + SOURCE DIST + PLACED ( 36960 439040 ) N ;
+ - FILLER_52_230 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 271040 439040 ) N ;
+ - FILLER_52_240 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 282240 439040 ) N ;
+ - FILLER_52_244 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 286720 439040 ) N ;
+ - FILLER_52_247 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 290080 439040 ) N ;
+ - FILLER_52_250 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 293440 439040 ) N ;
+ - FILLER_52_257 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 301280 439040 ) N ;
+ - FILLER_52_261 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 305760 439040 ) N ;
+ - FILLER_52_265 gf180mcu_fd_sc_mcu7t5v0__fillcap_16 + SOURCE DIST + PLACED ( 310240 439040 ) N ;
+ - FILLER_52_281 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 328160 439040 ) N ;
+ - FILLER_52_285 gf180mcu_fd_sc_mcu7t5v0__fillcap_8 + SOURCE DIST + PLACED ( 332640 439040 ) N ;
+ - FILLER_52_29 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 45920 439040 ) N ;
+ - FILLER_52_293 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 341600 439040 ) N ;
+ - FILLER_52_305 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 355040 439040 ) N ;
+ - FILLER_52_315 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 366240 439040 ) N ;
+ - FILLER_52_321 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 372960 439040 ) N ;
+ - FILLER_52_324 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 376320 439040 ) N ;
+ - FILLER_52_326 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 378560 439040 ) N ;
+ - FILLER_52_33 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 50400 439040 ) N ;
+ - FILLER_52_353 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 408800 439040 ) N ;
+ - FILLER_52_37 gf180mcu_fd_sc_mcu7t5v0__fillcap_64 + SOURCE DIST + PLACED ( 54880 439040 ) N ;
+ - FILLER_52_388 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 448000 439040 ) N ;
+ - FILLER_52_392 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 452480 439040 ) N ;
+ - FILLER_52_401 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 462560 439040 ) N ;
+ - FILLER_52_405 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 467040 439040 ) N ;
+ - FILLER_52_409 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 471520 439040 ) N ;
+ - FILLER_52_413 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 476000 439040 ) N ;
+ - FILLER_52_417 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 480480 439040 ) N ;
+ - FILLER_52_419 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 482720 439040 ) N ;
+ - FILLER_52_422 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 486080 439040 ) N ;
+ - FILLER_52_426 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 490560 439040 ) N ;
+ - FILLER_52_438 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 504000 439040 ) N ;
+ - FILLER_52_442 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 508480 439040 ) N ;
+ - FILLER_52_444 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 510720 439040 ) N ;
+ - FILLER_52_450 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 517440 439040 ) N ;
+ - FILLER_52_460 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 528640 439040 ) N ;
+ - FILLER_52_463 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 532000 439040 ) N ;
+ - FILLER_52_472 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 542080 439040 ) N ;
+ - FILLER_52_476 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 546560 439040 ) N ;
+ - FILLER_52_480 gf180mcu_fd_sc_mcu7t5v0__fillcap_8 + SOURCE DIST + PLACED ( 551040 439040 ) N ;
+ - FILLER_52_488 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 560000 439040 ) N ;
+ - FILLER_52_492 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 564480 439040 ) N ;
+ - FILLER_52_508 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 582400 439040 ) N ;
+ - FILLER_53_137 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 166880 446880 ) FS ;
+ - FILLER_53_141 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 171360 446880 ) FS ;
+ - FILLER_53_144 gf180mcu_fd_sc_mcu7t5v0__fillcap_16 + SOURCE DIST + PLACED ( 174720 446880 ) FS ;
+ - FILLER_53_160 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 192640 446880 ) FS ;
+ - FILLER_53_164 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 197120 446880 ) FS ;
+ - FILLER_53_168 gf180mcu_fd_sc_mcu7t5v0__fillcap_8 + SOURCE DIST + PLACED ( 201600 446880 ) FS ;
+ - FILLER_53_182 gf180mcu_fd_sc_mcu7t5v0__fillcap_16 + SOURCE DIST + PLACED ( 217280 446880 ) FS ;
+ - FILLER_53_198 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 235200 446880 ) FS ;
+ - FILLER_53_2 gf180mcu_fd_sc_mcu7t5v0__fillcap_64 + SOURCE DIST + PLACED ( 15680 446880 ) FS ;
+ - FILLER_53_201 gf180mcu_fd_sc_mcu7t5v0__fillcap_8 + SOURCE DIST + PLACED ( 238560 446880 ) FS ;
+ - FILLER_53_209 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 247520 446880 ) FS ;
+ - FILLER_53_215 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 254240 446880 ) FS ;
+ - FILLER_53_217 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 256480 446880 ) FS ;
+ - FILLER_53_220 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 259840 446880 ) FS ;
+ - FILLER_53_230 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 271040 446880 ) FS ;
+ - FILLER_53_236 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 277760 446880 ) FS ;
+ - FILLER_53_246 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 288960 446880 ) FS ;
+ - FILLER_53_248 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 291200 446880 ) FS ;
+ - FILLER_53_251 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 294560 446880 ) FS ;
+ - FILLER_53_261 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 305760 446880 ) FS ;
+ - FILLER_53_265 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 310240 446880 ) FS ;
+ - FILLER_53_269 gf180mcu_fd_sc_mcu7t5v0__fillcap_8 + SOURCE DIST + PLACED ( 314720 446880 ) FS ;
+ - FILLER_53_277 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 323680 446880 ) FS ;
+ - FILLER_53_281 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 328160 446880 ) FS ;
+ - FILLER_53_283 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 330400 446880 ) FS ;
+ - FILLER_53_286 gf180mcu_fd_sc_mcu7t5v0__fillcap_8 + SOURCE DIST + PLACED ( 333760 446880 ) FS ;
+ - FILLER_53_294 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 342720 446880 ) FS ;
+ - FILLER_53_298 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 347200 446880 ) FS ;
+ - FILLER_53_302 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 351680 446880 ) FS ;
+ - FILLER_53_304 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 353920 446880 ) FS ;
+ - FILLER_53_313 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 364000 446880 ) FS ;
+ - FILLER_53_354 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 409920 446880 ) FS ;
+ - FILLER_53_357 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 413280 446880 ) FS ;
+ - FILLER_53_367 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 424480 446880 ) FS ;
+ - FILLER_53_371 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 428960 446880 ) FS ;
+ - FILLER_53_375 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 433440 446880 ) FS ;
+ - FILLER_53_381 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 440160 446880 ) FS ;
+ - FILLER_53_385 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 444640 446880 ) FS ;
+ - FILLER_53_395 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 455840 446880 ) FS ;
+ - FILLER_53_399 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 460320 446880 ) FS ;
+ - FILLER_53_403 gf180mcu_fd_sc_mcu7t5v0__fillcap_16 + SOURCE DIST + PLACED ( 464800 446880 ) FS ;
+ - FILLER_53_419 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 482720 446880 ) FS ;
+ - FILLER_53_425 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 489440 446880 ) FS ;
+ - FILLER_53_428 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 492800 446880 ) FS ;
+ - FILLER_53_440 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 506240 446880 ) FS ;
+ - FILLER_53_444 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 510720 446880 ) FS ;
+ - FILLER_53_450 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 517440 446880 ) FS ;
+ - FILLER_53_454 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 521920 446880 ) FS ;
+ - FILLER_53_463 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 532000 446880 ) FS ;
+ - FILLER_53_473 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 543200 446880 ) FS ;
+ - FILLER_53_477 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 547680 446880 ) FS ;
+ - FILLER_53_481 gf180mcu_fd_sc_mcu7t5v0__fillcap_16 + SOURCE DIST + PLACED ( 552160 446880 ) FS ;
+ - FILLER_53_499 gf180mcu_fd_sc_mcu7t5v0__fillcap_8 + SOURCE DIST + PLACED ( 572320 446880 ) FS ;
+ - FILLER_53_507 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 581280 446880 ) FS ;
+ - FILLER_53_66 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 87360 446880 ) FS ;
+ - FILLER_53_70 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 91840 446880 ) FS ;
+ - FILLER_53_73 gf180mcu_fd_sc_mcu7t5v0__fillcap_64 + SOURCE DIST + PLACED ( 95200 446880 ) FS ;
+ - FILLER_54_101 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 126560 454720 ) N ;
+ - FILLER_54_105 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 131040 454720 ) N ;
+ - FILLER_54_108 gf180mcu_fd_sc_mcu7t5v0__fillcap_64 + SOURCE DIST + PLACED ( 134400 454720 ) N ;
+ - FILLER_54_172 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 206080 454720 ) N ;
+ - FILLER_54_176 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 210560 454720 ) N ;
+ - FILLER_54_179 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 213920 454720 ) N ;
+ - FILLER_54_2 gf180mcu_fd_sc_mcu7t5v0__fillcap_32 + SOURCE DIST + PLACED ( 15680 454720 ) N ;
+ - FILLER_54_209 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 247520 454720 ) N ;
+ - FILLER_54_213 gf180mcu_fd_sc_mcu7t5v0__fillcap_8 + SOURCE DIST + PLACED ( 252000 454720 ) N ;
+ - FILLER_54_234 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 275520 454720 ) N ;
+ - FILLER_54_246 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 288960 454720 ) N ;
+ - FILLER_54_250 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 293440 454720 ) N ;
+ - FILLER_54_252 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 295680 454720 ) N ;
+ - FILLER_54_263 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 308000 454720 ) N ;
+ - FILLER_54_267 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 312480 454720 ) N ;
+ - FILLER_54_300 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 349440 454720 ) N ;
+ - FILLER_54_312 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 362880 454720 ) N ;
+ - FILLER_54_314 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 365120 454720 ) N ;
+ - FILLER_54_317 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 368480 454720 ) N ;
+ - FILLER_54_321 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 372960 454720 ) N ;
+ - FILLER_54_330 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 383040 454720 ) N ;
+ - FILLER_54_332 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 385280 454720 ) N ;
+ - FILLER_54_337 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 390880 454720 ) N ;
+ - FILLER_54_34 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 51520 454720 ) N ;
+ - FILLER_54_344 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 398720 454720 ) N ;
+ - FILLER_54_353 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 408800 454720 ) N ;
+ - FILLER_54_359 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 415520 454720 ) N ;
+ - FILLER_54_363 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 420000 454720 ) N ;
+ - FILLER_54_367 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 424480 454720 ) N ;
+ - FILLER_54_37 gf180mcu_fd_sc_mcu7t5v0__fillcap_64 + SOURCE DIST + PLACED ( 54880 454720 ) N ;
+ - FILLER_54_371 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 428960 454720 ) N ;
+ - FILLER_54_375 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 433440 454720 ) N ;
+ - FILLER_54_378 gf180mcu_fd_sc_mcu7t5v0__fillcap_8 + SOURCE DIST + PLACED ( 436800 454720 ) N ;
+ - FILLER_54_386 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 445760 454720 ) N ;
+ - FILLER_54_392 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 452480 454720 ) N ;
+ - FILLER_54_395 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 455840 454720 ) N ;
+ - FILLER_54_399 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 460320 454720 ) N ;
+ - FILLER_54_414 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 477120 454720 ) N ;
+ - FILLER_54_439 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 505120 454720 ) N ;
+ - FILLER_54_455 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 523040 454720 ) N ;
+ - FILLER_54_459 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 527520 454720 ) N ;
+ - FILLER_54_463 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 532000 454720 ) N ;
+ - FILLER_54_474 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 544320 454720 ) N ;
+ - FILLER_54_478 gf180mcu_fd_sc_mcu7t5v0__fillcap_16 + SOURCE DIST + PLACED ( 548800 454720 ) N ;
+ - FILLER_54_494 gf180mcu_fd_sc_mcu7t5v0__fillcap_8 + SOURCE DIST + PLACED ( 566720 454720 ) N ;
+ - FILLER_54_502 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 575680 454720 ) N ;
+ - FILLER_54_508 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 582400 454720 ) N ;
+ - FILLER_55_137 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 166880 462560 ) FS ;
+ - FILLER_55_141 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 171360 462560 ) FS ;
+ - FILLER_55_144 gf180mcu_fd_sc_mcu7t5v0__fillcap_64 + SOURCE DIST + PLACED ( 174720 462560 ) FS ;
+ - FILLER_55_2 gf180mcu_fd_sc_mcu7t5v0__fillcap_64 + SOURCE DIST + PLACED ( 15680 462560 ) FS ;
+ - FILLER_55_208 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 246400 462560 ) FS ;
+ - FILLER_55_212 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 250880 462560 ) FS ;
+ - FILLER_55_215 gf180mcu_fd_sc_mcu7t5v0__fillcap_8 + SOURCE DIST + PLACED ( 254240 462560 ) FS ;
+ - FILLER_55_223 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 263200 462560 ) FS ;
+ - FILLER_55_227 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 267680 462560 ) FS ;
+ - FILLER_55_231 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 272160 462560 ) FS ;
+ - FILLER_55_241 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 283360 462560 ) FS ;
+ - FILLER_55_247 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 290080 462560 ) FS ;
+ - FILLER_55_278 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 324800 462560 ) FS ;
+ - FILLER_55_282 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 329280 462560 ) FS ;
+ - FILLER_55_286 gf180mcu_fd_sc_mcu7t5v0__fillcap_16 + SOURCE DIST + PLACED ( 333760 462560 ) FS ;
+ - FILLER_55_302 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 351680 462560 ) FS ;
+ - FILLER_55_304 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 353920 462560 ) FS ;
+ - FILLER_55_307 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 357280 462560 ) FS ;
+ - FILLER_55_321 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 372960 462560 ) FS ;
+ - FILLER_55_327 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 379680 462560 ) FS ;
+ - FILLER_55_334 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 387520 462560 ) FS ;
+ - FILLER_55_349 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 404320 462560 ) FS ;
+ - FILLER_55_353 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 408800 462560 ) FS ;
+ - FILLER_55_357 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 413280 462560 ) FS ;
+ - FILLER_55_360 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 416640 462560 ) FS ;
+ - FILLER_55_362 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 418880 462560 ) FS ;
+ - FILLER_55_376 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 434560 462560 ) FS ;
+ - FILLER_55_378 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 436800 462560 ) FS ;
+ - FILLER_55_387 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 446880 462560 ) FS ;
+ - FILLER_55_391 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 451360 462560 ) FS ;
+ - FILLER_55_400 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 461440 462560 ) FS ;
+ - FILLER_55_425 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 489440 462560 ) FS ;
+ - FILLER_55_428 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 492800 462560 ) FS ;
+ - FILLER_55_442 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 508480 462560 ) FS ;
+ - FILLER_55_446 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 512960 462560 ) FS ;
+ - FILLER_55_450 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 517440 462560 ) FS ;
+ - FILLER_55_452 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 519680 462560 ) FS ;
+ - FILLER_55_455 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 523040 462560 ) FS ;
+ - FILLER_55_486 gf180mcu_fd_sc_mcu7t5v0__fillcap_8 + SOURCE DIST + PLACED ( 557760 462560 ) FS ;
+ - FILLER_55_494 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 566720 462560 ) FS ;
+ - FILLER_55_496 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 568960 462560 ) FS ;
+ - FILLER_55_499 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 572320 462560 ) FS ;
+ - FILLER_55_503 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 576800 462560 ) FS ;
+ - FILLER_55_505 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 579040 462560 ) FS ;
+ - FILLER_55_508 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 582400 462560 ) FS ;
+ - FILLER_55_66 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 87360 462560 ) FS ;
+ - FILLER_55_70 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 91840 462560 ) FS ;
+ - FILLER_55_73 gf180mcu_fd_sc_mcu7t5v0__fillcap_64 + SOURCE DIST + PLACED ( 95200 462560 ) FS ;
+ - FILLER_56_101 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 126560 470400 ) N ;
+ - FILLER_56_105 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 131040 470400 ) N ;
+ - FILLER_56_108 gf180mcu_fd_sc_mcu7t5v0__fillcap_64 + SOURCE DIST + PLACED ( 134400 470400 ) N ;
+ - FILLER_56_172 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 206080 470400 ) N ;
+ - FILLER_56_176 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 210560 470400 ) N ;
+ - FILLER_56_179 gf180mcu_fd_sc_mcu7t5v0__fillcap_32 + SOURCE DIST + PLACED ( 213920 470400 ) N ;
+ - FILLER_56_2 gf180mcu_fd_sc_mcu7t5v0__fillcap_32 + SOURCE DIST + PLACED ( 15680 470400 ) N ;
+ - FILLER_56_211 gf180mcu_fd_sc_mcu7t5v0__fillcap_16 + SOURCE DIST + PLACED ( 249760 470400 ) N ;
+ - FILLER_56_227 gf180mcu_fd_sc_mcu7t5v0__fillcap_8 + SOURCE DIST + PLACED ( 267680 470400 ) N ;
+ - FILLER_56_235 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 276640 470400 ) N ;
+ - FILLER_56_239 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 281120 470400 ) N ;
+ - FILLER_56_243 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 285600 470400 ) N ;
+ - FILLER_56_247 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 290080 470400 ) N ;
+ - FILLER_56_250 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 293440 470400 ) N ;
+ - FILLER_56_253 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 296800 470400 ) N ;
+ - FILLER_56_257 gf180mcu_fd_sc_mcu7t5v0__fillcap_32 + SOURCE DIST + PLACED ( 301280 470400 ) N ;
+ - FILLER_56_289 gf180mcu_fd_sc_mcu7t5v0__fillcap_8 + SOURCE DIST + PLACED ( 337120 470400 ) N ;
+ - FILLER_56_297 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 346080 470400 ) N ;
+ - FILLER_56_301 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 350560 470400 ) N ;
+ - FILLER_56_315 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 366240 470400 ) N ;
+ - FILLER_56_321 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 372960 470400 ) N ;
+ - FILLER_56_330 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 383040 470400 ) N ;
+ - FILLER_56_34 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 51520 470400 ) N ;
+ - FILLER_56_355 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 411040 470400 ) N ;
+ - FILLER_56_37 gf180mcu_fd_sc_mcu7t5v0__fillcap_64 + SOURCE DIST + PLACED ( 54880 470400 ) N ;
+ - FILLER_56_371 gf180mcu_fd_sc_mcu7t5v0__fillcap_16 + SOURCE DIST + PLACED ( 428960 470400 ) N ;
+ - FILLER_56_387 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 446880 470400 ) N ;
+ - FILLER_56_389 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 449120 470400 ) N ;
+ - FILLER_56_392 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 452480 470400 ) N ;
+ - FILLER_56_395 gf180mcu_fd_sc_mcu7t5v0__fillcap_8 + SOURCE DIST + PLACED ( 455840 470400 ) N ;
+ - FILLER_56_403 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 464800 470400 ) N ;
+ - FILLER_56_406 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 468160 470400 ) N ;
+ - FILLER_56_412 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 474880 470400 ) N ;
+ - FILLER_56_437 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 502880 470400 ) N ;
+ - FILLER_56_451 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 518560 470400 ) N ;
+ - FILLER_56_455 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 523040 470400 ) N ;
+ - FILLER_56_459 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 527520 470400 ) N ;
+ - FILLER_56_463 gf180mcu_fd_sc_mcu7t5v0__fillcap_16 + SOURCE DIST + PLACED ( 532000 470400 ) N ;
+ - FILLER_56_479 gf180mcu_fd_sc_mcu7t5v0__fillcap_8 + SOURCE DIST + PLACED ( 549920 470400 ) N ;
+ - FILLER_56_487 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 558880 470400 ) N ;
+ - FILLER_56_491 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 563360 470400 ) N ;
+ - FILLER_56_493 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 565600 470400 ) N ;
+ - FILLER_56_508 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 582400 470400 ) N ;
+ - FILLER_57_137 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 166880 478240 ) FS ;
+ - FILLER_57_141 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 171360 478240 ) FS ;
+ - FILLER_57_144 gf180mcu_fd_sc_mcu7t5v0__fillcap_64 + SOURCE DIST + PLACED ( 174720 478240 ) FS ;
+ - FILLER_57_2 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 15680 478240 ) FS ;
+ - FILLER_57_208 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 246400 478240 ) FS ;
+ - FILLER_57_212 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 250880 478240 ) FS ;
+ - FILLER_57_215 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 254240 478240 ) FS ;
+ - FILLER_57_219 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 258720 478240 ) FS ;
+ - FILLER_57_222 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 262080 478240 ) FS ;
+ - FILLER_57_253 gf180mcu_fd_sc_mcu7t5v0__fillcap_16 + SOURCE DIST + PLACED ( 296800 478240 ) FS ;
+ - FILLER_57_269 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 314720 478240 ) FS ;
+ - FILLER_57_273 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 319200 478240 ) FS ;
+ - FILLER_57_280 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 327040 478240 ) FS ;
+ - FILLER_57_286 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 333760 478240 ) FS ;
+ - FILLER_57_290 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 338240 478240 ) FS ;
+ - FILLER_57_292 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 340480 478240 ) FS ;
+ - FILLER_57_295 gf180mcu_fd_sc_mcu7t5v0__fillcap_16 + SOURCE DIST + PLACED ( 343840 478240 ) FS ;
+ - FILLER_57_311 gf180mcu_fd_sc_mcu7t5v0__fillcap_8 + SOURCE DIST + PLACED ( 361760 478240 ) FS ;
+ - FILLER_57_319 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 370720 478240 ) FS ;
+ - FILLER_57_322 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 374080 478240 ) FS ;
+ - FILLER_57_326 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 378560 478240 ) FS ;
+ - FILLER_57_329 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 381920 478240 ) FS ;
+ - FILLER_57_343 gf180mcu_fd_sc_mcu7t5v0__fillcap_8 + SOURCE DIST + PLACED ( 397600 478240 ) FS ;
+ - FILLER_57_351 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 406560 478240 ) FS ;
+ - FILLER_57_357 gf180mcu_fd_sc_mcu7t5v0__fillcap_16 + SOURCE DIST + PLACED ( 413280 478240 ) FS ;
+ - FILLER_57_373 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 431200 478240 ) FS ;
+ - FILLER_57_403 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 464800 478240 ) FS ;
+ - FILLER_57_407 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 469280 478240 ) FS ;
+ - FILLER_57_409 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 471520 478240 ) FS ;
+ - FILLER_57_414 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 477120 478240 ) FS ;
+ - FILLER_57_418 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 481600 478240 ) FS ;
+ - FILLER_57_420 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 483840 478240 ) FS ;
+ - FILLER_57_425 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 489440 478240 ) FS ;
+ - FILLER_57_428 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 492800 478240 ) FS ;
+ - FILLER_57_443 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 509600 478240 ) FS ;
+ - FILLER_57_447 gf180mcu_fd_sc_mcu7t5v0__fillcap_8 + SOURCE DIST + PLACED ( 514080 478240 ) FS ;
+ - FILLER_57_455 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 523040 478240 ) FS ;
+ - FILLER_57_459 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 527520 478240 ) FS ;
+ - FILLER_57_461 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 529760 478240 ) FS ;
+ - FILLER_57_468 gf180mcu_fd_sc_mcu7t5v0__fillcap_16 + SOURCE DIST + PLACED ( 537600 478240 ) FS ;
+ - FILLER_57_484 gf180mcu_fd_sc_mcu7t5v0__fillcap_8 + SOURCE DIST + PLACED ( 555520 478240 ) FS ;
+ - FILLER_57_492 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 564480 478240 ) FS ;
+ - FILLER_57_496 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 568960 478240 ) FS ;
+ - FILLER_57_499 gf180mcu_fd_sc_mcu7t5v0__fillcap_8 + SOURCE DIST + PLACED ( 572320 478240 ) FS ;
+ - FILLER_57_507 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 581280 478240 ) FS ;
+ - FILLER_57_7 gf180mcu_fd_sc_mcu7t5v0__fillcap_64 + SOURCE DIST + PLACED ( 21280 478240 ) FS ;
+ - FILLER_57_73 gf180mcu_fd_sc_mcu7t5v0__fillcap_64 + SOURCE DIST + PLACED ( 95200 478240 ) FS ;
+ - FILLER_58_101 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 126560 486080 ) N ;
+ - FILLER_58_105 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 131040 486080 ) N ;
+ - FILLER_58_108 gf180mcu_fd_sc_mcu7t5v0__fillcap_64 + SOURCE DIST + PLACED ( 134400 486080 ) N ;
+ - FILLER_58_172 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 206080 486080 ) N ;
+ - FILLER_58_176 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 210560 486080 ) N ;
+ - FILLER_58_179 gf180mcu_fd_sc_mcu7t5v0__fillcap_64 + SOURCE DIST + PLACED ( 213920 486080 ) N ;
+ - FILLER_58_2 gf180mcu_fd_sc_mcu7t5v0__fillcap_32 + SOURCE DIST + PLACED ( 15680 486080 ) N ;
+ - FILLER_58_243 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 285600 486080 ) N ;
+ - FILLER_58_247 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 290080 486080 ) N ;
+ - FILLER_58_250 gf180mcu_fd_sc_mcu7t5v0__fillcap_8 + SOURCE DIST + PLACED ( 293440 486080 ) N ;
+ - FILLER_58_258 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 302400 486080 ) N ;
+ - FILLER_58_262 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 306880 486080 ) N ;
+ - FILLER_58_293 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 341600 486080 ) N ;
+ - FILLER_58_303 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 352800 486080 ) N ;
+ - FILLER_58_318 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 369600 486080 ) N ;
+ - FILLER_58_321 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 372960 486080 ) N ;
+ - FILLER_58_327 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 379680 486080 ) N ;
+ - FILLER_58_334 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 387520 486080 ) N ;
+ - FILLER_58_338 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 392000 486080 ) N ;
+ - FILLER_58_34 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 51520 486080 ) N ;
+ - FILLER_58_342 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 396480 486080 ) N ;
+ - FILLER_58_350 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 405440 486080 ) N ;
+ - FILLER_58_354 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 409920 486080 ) N ;
+ - FILLER_58_364 gf180mcu_fd_sc_mcu7t5v0__fillcap_16 + SOURCE DIST + PLACED ( 421120 486080 ) N ;
+ - FILLER_58_37 gf180mcu_fd_sc_mcu7t5v0__fillcap_64 + SOURCE DIST + PLACED ( 54880 486080 ) N ;
+ - FILLER_58_380 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 439040 486080 ) N ;
+ - FILLER_58_389 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 449120 486080 ) N ;
+ - FILLER_58_392 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 452480 486080 ) N ;
+ - FILLER_58_399 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 460320 486080 ) N ;
+ - FILLER_58_403 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 464800 486080 ) N ;
+ - FILLER_58_408 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 470400 486080 ) N ;
+ - FILLER_58_412 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 474880 486080 ) N ;
+ - FILLER_58_421 gf180mcu_fd_sc_mcu7t5v0__fillcap_8 + SOURCE DIST + PLACED ( 484960 486080 ) N ;
+ - FILLER_58_429 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 493920 486080 ) N ;
+ - FILLER_58_435 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 500640 486080 ) N ;
+ - FILLER_58_439 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 505120 486080 ) N ;
+ - FILLER_58_443 gf180mcu_fd_sc_mcu7t5v0__fillcap_8 + SOURCE DIST + PLACED ( 509600 486080 ) N ;
+ - FILLER_58_451 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 518560 486080 ) N ;
+ - FILLER_58_460 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 528640 486080 ) N ;
+ - FILLER_58_463 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 532000 486080 ) N ;
+ - FILLER_58_493 gf180mcu_fd_sc_mcu7t5v0__fillcap_16 + SOURCE DIST + PLACED ( 565600 486080 ) N ;
+ - FILLER_59_137 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 166880 493920 ) FS ;
+ - FILLER_59_141 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 171360 493920 ) FS ;
+ - FILLER_59_144 gf180mcu_fd_sc_mcu7t5v0__fillcap_64 + SOURCE DIST + PLACED ( 174720 493920 ) FS ;
+ - FILLER_59_2 gf180mcu_fd_sc_mcu7t5v0__fillcap_64 + SOURCE DIST + PLACED ( 15680 493920 ) FS ;
+ - FILLER_59_208 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 246400 493920 ) FS ;
+ - FILLER_59_212 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 250880 493920 ) FS ;
+ - FILLER_59_215 gf180mcu_fd_sc_mcu7t5v0__fillcap_64 + SOURCE DIST + PLACED ( 254240 493920 ) FS ;
+ - FILLER_59_279 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 325920 493920 ) FS ;
+ - FILLER_59_283 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 330400 493920 ) FS ;
+ - FILLER_59_286 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 333760 493920 ) FS ;
+ - FILLER_59_290 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 338240 493920 ) FS ;
+ - FILLER_59_292 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 340480 493920 ) FS ;
+ - FILLER_59_301 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 350560 493920 ) FS ;
+ - FILLER_59_303 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 352800 493920 ) FS ;
+ - FILLER_59_312 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 362880 493920 ) FS ;
+ - FILLER_59_322 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 374080 493920 ) FS ;
+ - FILLER_59_326 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 378560 493920 ) FS ;
+ - FILLER_59_338 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 392000 493920 ) FS ;
+ - FILLER_59_344 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 398720 493920 ) FS ;
+ - FILLER_59_354 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 409920 493920 ) FS ;
+ - FILLER_59_357 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 413280 493920 ) FS ;
+ - FILLER_59_387 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 446880 493920 ) FS ;
+ - FILLER_59_391 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 451360 493920 ) FS ;
+ - FILLER_59_393 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 453600 493920 ) FS ;
+ - FILLER_59_402 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 463680 493920 ) FS ;
+ - FILLER_59_411 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 473760 493920 ) FS ;
+ - FILLER_59_420 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 483840 493920 ) FS ;
+ - FILLER_59_424 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 488320 493920 ) FS ;
+ - FILLER_59_428 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 492800 493920 ) FS ;
+ - FILLER_59_431 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 496160 493920 ) FS ;
+ - FILLER_59_443 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 509600 493920 ) FS ;
+ - FILLER_59_453 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 520800 493920 ) FS ;
+ - FILLER_59_457 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 525280 493920 ) FS ;
+ - FILLER_59_461 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 529760 493920 ) FS ;
+ - FILLER_59_464 gf180mcu_fd_sc_mcu7t5v0__fillcap_32 + SOURCE DIST + PLACED ( 533120 493920 ) FS ;
+ - FILLER_59_496 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 568960 493920 ) FS ;
+ - FILLER_59_499 gf180mcu_fd_sc_mcu7t5v0__fillcap_8 + SOURCE DIST + PLACED ( 572320 493920 ) FS ;
+ - FILLER_59_507 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 581280 493920 ) FS ;
+ - FILLER_59_66 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 87360 493920 ) FS ;
+ - FILLER_59_70 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 91840 493920 ) FS ;
+ - FILLER_59_73 gf180mcu_fd_sc_mcu7t5v0__fillcap_64 + SOURCE DIST + PLACED ( 95200 493920 ) FS ;
+ - FILLER_5_137 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 166880 70560 ) FS ;
+ - FILLER_5_141 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 171360 70560 ) FS ;
+ - FILLER_5_144 gf180mcu_fd_sc_mcu7t5v0__fillcap_64 + SOURCE DIST + PLACED ( 174720 70560 ) FS ;
+ - FILLER_5_2 gf180mcu_fd_sc_mcu7t5v0__fillcap_64 + SOURCE DIST + PLACED ( 15680 70560 ) FS ;
+ - FILLER_5_208 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 246400 70560 ) FS ;
+ - FILLER_5_212 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 250880 70560 ) FS ;
+ - FILLER_5_215 gf180mcu_fd_sc_mcu7t5v0__fillcap_64 + SOURCE DIST + PLACED ( 254240 70560 ) FS ;
+ - FILLER_5_279 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 325920 70560 ) FS ;
+ - FILLER_5_283 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 330400 70560 ) FS ;
+ - FILLER_5_286 gf180mcu_fd_sc_mcu7t5v0__fillcap_64 + SOURCE DIST + PLACED ( 333760 70560 ) FS ;
+ - FILLER_5_350 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 405440 70560 ) FS ;
+ - FILLER_5_354 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 409920 70560 ) FS ;
+ - FILLER_5_357 gf180mcu_fd_sc_mcu7t5v0__fillcap_64 + SOURCE DIST + PLACED ( 413280 70560 ) FS ;
+ - FILLER_5_421 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 484960 70560 ) FS ;
+ - FILLER_5_425 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 489440 70560 ) FS ;
+ - FILLER_5_428 gf180mcu_fd_sc_mcu7t5v0__fillcap_64 + SOURCE DIST + PLACED ( 492800 70560 ) FS ;
+ - FILLER_5_492 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 564480 70560 ) FS ;
+ - FILLER_5_496 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 568960 70560 ) FS ;
+ - FILLER_5_499 gf180mcu_fd_sc_mcu7t5v0__fillcap_8 + SOURCE DIST + PLACED ( 572320 70560 ) FS ;
+ - FILLER_5_507 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 581280 70560 ) FS ;
+ - FILLER_5_66 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 87360 70560 ) FS ;
+ - FILLER_5_70 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 91840 70560 ) FS ;
+ - FILLER_5_73 gf180mcu_fd_sc_mcu7t5v0__fillcap_64 + SOURCE DIST + PLACED ( 95200 70560 ) FS ;
+ - FILLER_60_101 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 126560 501760 ) N ;
+ - FILLER_60_105 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 131040 501760 ) N ;
+ - FILLER_60_108 gf180mcu_fd_sc_mcu7t5v0__fillcap_64 + SOURCE DIST + PLACED ( 134400 501760 ) N ;
+ - FILLER_60_172 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 206080 501760 ) N ;
+ - FILLER_60_176 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 210560 501760 ) N ;
+ - FILLER_60_179 gf180mcu_fd_sc_mcu7t5v0__fillcap_64 + SOURCE DIST + PLACED ( 213920 501760 ) N ;
+ - FILLER_60_2 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 15680 501760 ) N ;
+ - FILLER_60_23 gf180mcu_fd_sc_mcu7t5v0__fillcap_8 + SOURCE DIST + PLACED ( 39200 501760 ) N ;
+ - FILLER_60_243 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 285600 501760 ) N ;
+ - FILLER_60_247 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 290080 501760 ) N ;
+ - FILLER_60_250 gf180mcu_fd_sc_mcu7t5v0__fillcap_16 + SOURCE DIST + PLACED ( 293440 501760 ) N ;
+ - FILLER_60_266 gf180mcu_fd_sc_mcu7t5v0__fillcap_8 + SOURCE DIST + PLACED ( 311360 501760 ) N ;
+ - FILLER_60_274 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 320320 501760 ) N ;
+ - FILLER_60_305 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 355040 501760 ) N ;
+ - FILLER_60_31 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 48160 501760 ) N ;
+ - FILLER_60_311 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 361760 501760 ) N ;
+ - FILLER_60_315 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 366240 501760 ) N ;
+ - FILLER_60_321 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 372960 501760 ) N ;
+ - FILLER_60_324 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 376320 501760 ) N ;
+ - FILLER_60_326 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 378560 501760 ) N ;
+ - FILLER_60_335 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 388640 501760 ) N ;
+ - FILLER_60_345 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 399840 501760 ) N ;
+ - FILLER_60_354 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 409920 501760 ) N ;
+ - FILLER_60_361 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 417760 501760 ) N ;
+ - FILLER_60_365 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 422240 501760 ) N ;
+ - FILLER_60_369 gf180mcu_fd_sc_mcu7t5v0__fillcap_16 + SOURCE DIST + PLACED ( 426720 501760 ) N ;
+ - FILLER_60_37 gf180mcu_fd_sc_mcu7t5v0__fillcap_64 + SOURCE DIST + PLACED ( 54880 501760 ) N ;
+ - FILLER_60_385 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 444640 501760 ) N ;
+ - FILLER_60_389 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 449120 501760 ) N ;
+ - FILLER_60_392 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 452480 501760 ) N ;
+ - FILLER_60_403 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 464800 501760 ) N ;
+ - FILLER_60_407 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 469280 501760 ) N ;
+ - FILLER_60_409 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 471520 501760 ) N ;
+ - FILLER_60_420 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 483840 501760 ) N ;
+ - FILLER_60_422 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 486080 501760 ) N ;
+ - FILLER_60_431 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 496160 501760 ) N ;
+ - FILLER_60_441 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 507360 501760 ) N ;
+ - FILLER_60_453 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 520800 501760 ) N ;
+ - FILLER_60_459 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 527520 501760 ) N ;
+ - FILLER_60_463 gf180mcu_fd_sc_mcu7t5v0__fillcap_32 + SOURCE DIST + PLACED ( 532000 501760 ) N ;
+ - FILLER_60_495 gf180mcu_fd_sc_mcu7t5v0__fillcap_8 + SOURCE DIST + PLACED ( 567840 501760 ) N ;
+ - FILLER_60_503 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 576800 501760 ) N ;
+ - FILLER_60_508 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 582400 501760 ) N ;
+ - FILLER_60_7 gf180mcu_fd_sc_mcu7t5v0__fillcap_16 + SOURCE DIST + PLACED ( 21280 501760 ) N ;
+ - FILLER_61_137 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 166880 509600 ) FS ;
+ - FILLER_61_141 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 171360 509600 ) FS ;
+ - FILLER_61_144 gf180mcu_fd_sc_mcu7t5v0__fillcap_64 + SOURCE DIST + PLACED ( 174720 509600 ) FS ;
+ - FILLER_61_2 gf180mcu_fd_sc_mcu7t5v0__fillcap_64 + SOURCE DIST + PLACED ( 15680 509600 ) FS ;
+ - FILLER_61_208 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 246400 509600 ) FS ;
+ - FILLER_61_212 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 250880 509600 ) FS ;
+ - FILLER_61_215 gf180mcu_fd_sc_mcu7t5v0__fillcap_64 + SOURCE DIST + PLACED ( 254240 509600 ) FS ;
+ - FILLER_61_279 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 325920 509600 ) FS ;
+ - FILLER_61_283 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 330400 509600 ) FS ;
+ - FILLER_61_286 gf180mcu_fd_sc_mcu7t5v0__fillcap_8 + SOURCE DIST + PLACED ( 333760 509600 ) FS ;
+ - FILLER_61_294 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 342720 509600 ) FS ;
+ - FILLER_61_296 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 344960 509600 ) FS ;
+ - FILLER_61_326 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 378560 509600 ) FS ;
+ - FILLER_61_338 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 392000 509600 ) FS ;
+ - FILLER_61_342 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 396480 509600 ) FS ;
+ - FILLER_61_353 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 408800 509600 ) FS ;
+ - FILLER_61_357 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 413280 509600 ) FS ;
+ - FILLER_61_360 gf180mcu_fd_sc_mcu7t5v0__fillcap_8 + SOURCE DIST + PLACED ( 416640 509600 ) FS ;
+ - FILLER_61_368 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 425600 509600 ) FS ;
+ - FILLER_61_372 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 430080 509600 ) FS ;
+ - FILLER_61_402 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 463680 509600 ) FS ;
+ - FILLER_61_409 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 471520 509600 ) FS ;
+ - FILLER_61_413 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 476000 509600 ) FS ;
+ - FILLER_61_419 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 482720 509600 ) FS ;
+ - FILLER_61_423 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 487200 509600 ) FS ;
+ - FILLER_61_425 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 489440 509600 ) FS ;
+ - FILLER_61_428 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 492800 509600 ) FS ;
+ - FILLER_61_431 gf180mcu_fd_sc_mcu7t5v0__fillcap_8 + SOURCE DIST + PLACED ( 496160 509600 ) FS ;
+ - FILLER_61_441 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 507360 509600 ) FS ;
+ - FILLER_61_472 gf180mcu_fd_sc_mcu7t5v0__fillcap_16 + SOURCE DIST + PLACED ( 542080 509600 ) FS ;
+ - FILLER_61_488 gf180mcu_fd_sc_mcu7t5v0__fillcap_8 + SOURCE DIST + PLACED ( 560000 509600 ) FS ;
+ - FILLER_61_496 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 568960 509600 ) FS ;
+ - FILLER_61_499 gf180mcu_fd_sc_mcu7t5v0__fillcap_8 + SOURCE DIST + PLACED ( 572320 509600 ) FS ;
+ - FILLER_61_507 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 581280 509600 ) FS ;
+ - FILLER_61_66 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 87360 509600 ) FS ;
+ - FILLER_61_70 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 91840 509600 ) FS ;
+ - FILLER_61_73 gf180mcu_fd_sc_mcu7t5v0__fillcap_64 + SOURCE DIST + PLACED ( 95200 509600 ) FS ;
+ - FILLER_62_101 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 126560 517440 ) N ;
+ - FILLER_62_105 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 131040 517440 ) N ;
+ - FILLER_62_108 gf180mcu_fd_sc_mcu7t5v0__fillcap_64 + SOURCE DIST + PLACED ( 134400 517440 ) N ;
+ - FILLER_62_172 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 206080 517440 ) N ;
+ - FILLER_62_176 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 210560 517440 ) N ;
+ - FILLER_62_179 gf180mcu_fd_sc_mcu7t5v0__fillcap_64 + SOURCE DIST + PLACED ( 213920 517440 ) N ;
+ - FILLER_62_2 gf180mcu_fd_sc_mcu7t5v0__fillcap_32 + SOURCE DIST + PLACED ( 15680 517440 ) N ;
+ - FILLER_62_243 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 285600 517440 ) N ;
+ - FILLER_62_247 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 290080 517440 ) N ;
+ - FILLER_62_250 gf180mcu_fd_sc_mcu7t5v0__fillcap_32 + SOURCE DIST + PLACED ( 293440 517440 ) N ;
+ - FILLER_62_282 gf180mcu_fd_sc_mcu7t5v0__fillcap_16 + SOURCE DIST + PLACED ( 329280 517440 ) N ;
+ - FILLER_62_298 gf180mcu_fd_sc_mcu7t5v0__fillcap_8 + SOURCE DIST + PLACED ( 347200 517440 ) N ;
+ - FILLER_62_308 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 358400 517440 ) N ;
+ - FILLER_62_315 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 366240 517440 ) N ;
+ - FILLER_62_321 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 372960 517440 ) N ;
+ - FILLER_62_325 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 377440 517440 ) N ;
+ - FILLER_62_328 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 380800 517440 ) N ;
+ - FILLER_62_332 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 385280 517440 ) N ;
+ - FILLER_62_334 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 387520 517440 ) N ;
+ - FILLER_62_34 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 51520 517440 ) N ;
+ - FILLER_62_340 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 394240 517440 ) N ;
+ - FILLER_62_37 gf180mcu_fd_sc_mcu7t5v0__fillcap_64 + SOURCE DIST + PLACED ( 54880 517440 ) N ;
+ - FILLER_62_371 gf180mcu_fd_sc_mcu7t5v0__fillcap_16 + SOURCE DIST + PLACED ( 428960 517440 ) N ;
+ - FILLER_62_387 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 446880 517440 ) N ;
+ - FILLER_62_389 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 449120 517440 ) N ;
+ - FILLER_62_392 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 452480 517440 ) N ;
+ - FILLER_62_396 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 456960 517440 ) N ;
+ - FILLER_62_403 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 464800 517440 ) N ;
+ - FILLER_62_407 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 469280 517440 ) N ;
+ - FILLER_62_440 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 506240 517440 ) N ;
+ - FILLER_62_444 gf180mcu_fd_sc_mcu7t5v0__fillcap_16 + SOURCE DIST + PLACED ( 510720 517440 ) N ;
+ - FILLER_62_460 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 528640 517440 ) N ;
+ - FILLER_62_463 gf180mcu_fd_sc_mcu7t5v0__fillcap_32 + SOURCE DIST + PLACED ( 532000 517440 ) N ;
+ - FILLER_62_495 gf180mcu_fd_sc_mcu7t5v0__fillcap_8 + SOURCE DIST + PLACED ( 567840 517440 ) N ;
+ - FILLER_62_503 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 576800 517440 ) N ;
+ - FILLER_62_508 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 582400 517440 ) N ;
+ - FILLER_63_137 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 166880 525280 ) FS ;
+ - FILLER_63_141 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 171360 525280 ) FS ;
+ - FILLER_63_144 gf180mcu_fd_sc_mcu7t5v0__fillcap_64 + SOURCE DIST + PLACED ( 174720 525280 ) FS ;
+ - FILLER_63_2 gf180mcu_fd_sc_mcu7t5v0__fillcap_64 + SOURCE DIST + PLACED ( 15680 525280 ) FS ;
+ - FILLER_63_208 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 246400 525280 ) FS ;
+ - FILLER_63_212 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 250880 525280 ) FS ;
+ - FILLER_63_215 gf180mcu_fd_sc_mcu7t5v0__fillcap_64 + SOURCE DIST + PLACED ( 254240 525280 ) FS ;
+ - FILLER_63_279 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 325920 525280 ) FS ;
+ - FILLER_63_283 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 330400 525280 ) FS ;
+ - FILLER_63_286 gf180mcu_fd_sc_mcu7t5v0__fillcap_32 + SOURCE DIST + PLACED ( 333760 525280 ) FS ;
+ - FILLER_63_318 gf180mcu_fd_sc_mcu7t5v0__fillcap_16 + SOURCE DIST + PLACED ( 369600 525280 ) FS ;
+ - FILLER_63_334 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 387520 525280 ) FS ;
+ - FILLER_63_338 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 392000 525280 ) FS ;
+ - FILLER_63_342 gf180mcu_fd_sc_mcu7t5v0__fillcap_8 + SOURCE DIST + PLACED ( 396480 525280 ) FS ;
+ - FILLER_63_350 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 405440 525280 ) FS ;
+ - FILLER_63_354 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 409920 525280 ) FS ;
+ - FILLER_63_357 gf180mcu_fd_sc_mcu7t5v0__fillcap_64 + SOURCE DIST + PLACED ( 413280 525280 ) FS ;
+ - FILLER_63_421 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 484960 525280 ) FS ;
+ - FILLER_63_425 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 489440 525280 ) FS ;
+ - FILLER_63_428 gf180mcu_fd_sc_mcu7t5v0__fillcap_64 + SOURCE DIST + PLACED ( 492800 525280 ) FS ;
+ - FILLER_63_492 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 564480 525280 ) FS ;
+ - FILLER_63_496 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 568960 525280 ) FS ;
+ - FILLER_63_499 gf180mcu_fd_sc_mcu7t5v0__fillcap_8 + SOURCE DIST + PLACED ( 572320 525280 ) FS ;
+ - FILLER_63_507 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 581280 525280 ) FS ;
+ - FILLER_63_66 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 87360 525280 ) FS ;
+ - FILLER_63_70 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 91840 525280 ) FS ;
+ - FILLER_63_73 gf180mcu_fd_sc_mcu7t5v0__fillcap_64 + SOURCE DIST + PLACED ( 95200 525280 ) FS ;
+ - FILLER_64_101 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 126560 533120 ) N ;
+ - FILLER_64_105 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 131040 533120 ) N ;
+ - FILLER_64_108 gf180mcu_fd_sc_mcu7t5v0__fillcap_64 + SOURCE DIST + PLACED ( 134400 533120 ) N ;
+ - FILLER_64_172 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 206080 533120 ) N ;
+ - FILLER_64_176 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 210560 533120 ) N ;
+ - FILLER_64_179 gf180mcu_fd_sc_mcu7t5v0__fillcap_64 + SOURCE DIST + PLACED ( 213920 533120 ) N ;
+ - FILLER_64_2 gf180mcu_fd_sc_mcu7t5v0__fillcap_32 + SOURCE DIST + PLACED ( 15680 533120 ) N ;
+ - FILLER_64_243 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 285600 533120 ) N ;
+ - FILLER_64_247 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 290080 533120 ) N ;
+ - FILLER_64_250 gf180mcu_fd_sc_mcu7t5v0__fillcap_64 + SOURCE DIST + PLACED ( 293440 533120 ) N ;
+ - FILLER_64_314 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 365120 533120 ) N ;
+ - FILLER_64_318 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 369600 533120 ) N ;
+ - FILLER_64_321 gf180mcu_fd_sc_mcu7t5v0__fillcap_64 + SOURCE DIST + PLACED ( 372960 533120 ) N ;
+ - FILLER_64_34 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 51520 533120 ) N ;
+ - FILLER_64_37 gf180mcu_fd_sc_mcu7t5v0__fillcap_64 + SOURCE DIST + PLACED ( 54880 533120 ) N ;
+ - FILLER_64_385 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 444640 533120 ) N ;
+ - FILLER_64_389 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 449120 533120 ) N ;
+ - FILLER_64_392 gf180mcu_fd_sc_mcu7t5v0__fillcap_64 + SOURCE DIST + PLACED ( 452480 533120 ) N ;
+ - FILLER_64_456 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 524160 533120 ) N ;
+ - FILLER_64_460 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 528640 533120 ) N ;
+ - FILLER_64_463 gf180mcu_fd_sc_mcu7t5v0__fillcap_32 + SOURCE DIST + PLACED ( 532000 533120 ) N ;
+ - FILLER_64_495 gf180mcu_fd_sc_mcu7t5v0__fillcap_8 + SOURCE DIST + PLACED ( 567840 533120 ) N ;
+ - FILLER_64_503 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 576800 533120 ) N ;
+ - FILLER_64_507 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 581280 533120 ) N ;
+ - FILLER_65_137 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 166880 540960 ) FS ;
+ - FILLER_65_141 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 171360 540960 ) FS ;
+ - FILLER_65_144 gf180mcu_fd_sc_mcu7t5v0__fillcap_64 + SOURCE DIST + PLACED ( 174720 540960 ) FS ;
+ - FILLER_65_2 gf180mcu_fd_sc_mcu7t5v0__fillcap_64 + SOURCE DIST + PLACED ( 15680 540960 ) FS ;
+ - FILLER_65_208 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 246400 540960 ) FS ;
+ - FILLER_65_212 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 250880 540960 ) FS ;
+ - FILLER_65_215 gf180mcu_fd_sc_mcu7t5v0__fillcap_64 + SOURCE DIST + PLACED ( 254240 540960 ) FS ;
+ - FILLER_65_279 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 325920 540960 ) FS ;
+ - FILLER_65_283 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 330400 540960 ) FS ;
+ - FILLER_65_286 gf180mcu_fd_sc_mcu7t5v0__fillcap_64 + SOURCE DIST + PLACED ( 333760 540960 ) FS ;
+ - FILLER_65_350 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 405440 540960 ) FS ;
+ - FILLER_65_354 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 409920 540960 ) FS ;
+ - FILLER_65_357 gf180mcu_fd_sc_mcu7t5v0__fillcap_64 + SOURCE DIST + PLACED ( 413280 540960 ) FS ;
+ - FILLER_65_421 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 484960 540960 ) FS ;
+ - FILLER_65_425 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 489440 540960 ) FS ;
+ - FILLER_65_428 gf180mcu_fd_sc_mcu7t5v0__fillcap_64 + SOURCE DIST + PLACED ( 492800 540960 ) FS ;
+ - FILLER_65_492 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 564480 540960 ) FS ;
+ - FILLER_65_496 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 568960 540960 ) FS ;
+ - FILLER_65_499 gf180mcu_fd_sc_mcu7t5v0__fillcap_8 + SOURCE DIST + PLACED ( 572320 540960 ) FS ;
+ - FILLER_65_507 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 581280 540960 ) FS ;
+ - FILLER_65_66 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 87360 540960 ) FS ;
+ - FILLER_65_70 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 91840 540960 ) FS ;
+ - FILLER_65_73 gf180mcu_fd_sc_mcu7t5v0__fillcap_64 + SOURCE DIST + PLACED ( 95200 540960 ) FS ;
+ - FILLER_66_101 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 126560 548800 ) N ;
+ - FILLER_66_105 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 131040 548800 ) N ;
+ - FILLER_66_108 gf180mcu_fd_sc_mcu7t5v0__fillcap_64 + SOURCE DIST + PLACED ( 134400 548800 ) N ;
+ - FILLER_66_172 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 206080 548800 ) N ;
+ - FILLER_66_176 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 210560 548800 ) N ;
+ - FILLER_66_179 gf180mcu_fd_sc_mcu7t5v0__fillcap_64 + SOURCE DIST + PLACED ( 213920 548800 ) N ;
+ - FILLER_66_2 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 15680 548800 ) N ;
+ - FILLER_66_23 gf180mcu_fd_sc_mcu7t5v0__fillcap_8 + SOURCE DIST + PLACED ( 39200 548800 ) N ;
+ - FILLER_66_243 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 285600 548800 ) N ;
+ - FILLER_66_247 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 290080 548800 ) N ;
+ - FILLER_66_250 gf180mcu_fd_sc_mcu7t5v0__fillcap_64 + SOURCE DIST + PLACED ( 293440 548800 ) N ;
+ - FILLER_66_31 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 48160 548800 ) N ;
+ - FILLER_66_314 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 365120 548800 ) N ;
+ - FILLER_66_318 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 369600 548800 ) N ;
+ - FILLER_66_321 gf180mcu_fd_sc_mcu7t5v0__fillcap_64 + SOURCE DIST + PLACED ( 372960 548800 ) N ;
+ - FILLER_66_37 gf180mcu_fd_sc_mcu7t5v0__fillcap_64 + SOURCE DIST + PLACED ( 54880 548800 ) N ;
+ - FILLER_66_385 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 444640 548800 ) N ;
+ - FILLER_66_389 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 449120 548800 ) N ;
+ - FILLER_66_392 gf180mcu_fd_sc_mcu7t5v0__fillcap_64 + SOURCE DIST + PLACED ( 452480 548800 ) N ;
+ - FILLER_66_456 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 524160 548800 ) N ;
+ - FILLER_66_460 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 528640 548800 ) N ;
+ - FILLER_66_463 gf180mcu_fd_sc_mcu7t5v0__fillcap_32 + SOURCE DIST + PLACED ( 532000 548800 ) N ;
+ - FILLER_66_495 gf180mcu_fd_sc_mcu7t5v0__fillcap_8 + SOURCE DIST + PLACED ( 567840 548800 ) N ;
+ - FILLER_66_503 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 576800 548800 ) N ;
+ - FILLER_66_508 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 582400 548800 ) N ;
+ - FILLER_66_7 gf180mcu_fd_sc_mcu7t5v0__fillcap_16 + SOURCE DIST + PLACED ( 21280 548800 ) N ;
+ - FILLER_67_101 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 126560 556640 ) FS ;
+ - FILLER_67_107 gf180mcu_fd_sc_mcu7t5v0__fillcap_8 + SOURCE DIST + PLACED ( 133280 556640 ) FS ;
+ - FILLER_67_11 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 25760 556640 ) FS ;
+ - FILLER_67_119 gf180mcu_fd_sc_mcu7t5v0__fillcap_8 + SOURCE DIST + PLACED ( 146720 556640 ) FS ;
+ - FILLER_67_127 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 155680 556640 ) FS ;
+ - FILLER_67_131 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 160160 556640 ) FS ;
+ - FILLER_67_137 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 166880 556640 ) FS ;
+ - FILLER_67_139 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 169120 556640 ) FS ;
+ - FILLER_67_142 gf180mcu_fd_sc_mcu7t5v0__fillcap_32 + SOURCE DIST + PLACED ( 172480 556640 ) FS ;
+ - FILLER_67_17 gf180mcu_fd_sc_mcu7t5v0__fillcap_8 + SOURCE DIST + PLACED ( 32480 556640 ) FS ;
+ - FILLER_67_174 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 208320 556640 ) FS ;
+ - FILLER_67_177 gf180mcu_fd_sc_mcu7t5v0__fillcap_16 + SOURCE DIST + PLACED ( 211680 556640 ) FS ;
+ - FILLER_67_197 gf180mcu_fd_sc_mcu7t5v0__fillcap_8 + SOURCE DIST + PLACED ( 234080 556640 ) FS ;
+ - FILLER_67_2 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 15680 556640 ) FS ;
+ - FILLER_67_205 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 243040 556640 ) FS ;
+ - FILLER_67_209 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 247520 556640 ) FS ;
+ - FILLER_67_212 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 250880 556640 ) FS ;
+ - FILLER_67_217 gf180mcu_fd_sc_mcu7t5v0__fillcap_16 + SOURCE DIST + PLACED ( 256480 556640 ) FS ;
+ - FILLER_67_233 gf180mcu_fd_sc_mcu7t5v0__fillcap_8 + SOURCE DIST + PLACED ( 274400 556640 ) FS ;
+ - FILLER_67_241 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 283360 556640 ) FS ;
+ - FILLER_67_247 gf180mcu_fd_sc_mcu7t5v0__fillcap_16 + SOURCE DIST + PLACED ( 290080 556640 ) FS ;
+ - FILLER_67_263 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 308000 556640 ) FS ;
+ - FILLER_67_269 gf180mcu_fd_sc_mcu7t5v0__fillcap_8 + SOURCE DIST + PLACED ( 314720 556640 ) FS ;
+ - FILLER_67_277 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 323680 556640 ) FS ;
+ - FILLER_67_279 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 325920 556640 ) FS ;
+ - FILLER_67_282 gf180mcu_fd_sc_mcu7t5v0__fillcap_8 + SOURCE DIST + PLACED ( 329280 556640 ) FS ;
+ - FILLER_67_29 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 45920 556640 ) FS ;
+ - FILLER_67_290 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 338240 556640 ) FS ;
+ - FILLER_67_294 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 342720 556640 ) FS ;
+ - FILLER_67_296 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 344960 556640 ) FS ;
+ - FILLER_67_299 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 348320 556640 ) FS ;
+ - FILLER_67_309 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 359520 556640 ) FS ;
+ - FILLER_67_313 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 364000 556640 ) FS ;
+ - FILLER_67_317 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 368480 556640 ) FS ;
+ - FILLER_67_323 gf180mcu_fd_sc_mcu7t5v0__fillcap_8 + SOURCE DIST + PLACED ( 375200 556640 ) FS ;
+ - FILLER_67_33 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 50400 556640 ) FS ;
+ - FILLER_67_331 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 384160 556640 ) FS ;
+ - FILLER_67_335 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 388640 556640 ) FS ;
+ - FILLER_67_345 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 399840 556640 ) FS ;
+ - FILLER_67_349 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 404320 556640 ) FS ;
+ - FILLER_67_352 gf180mcu_fd_sc_mcu7t5v0__fillcap_8 + SOURCE DIST + PLACED ( 407680 556640 ) FS ;
+ - FILLER_67_360 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 416640 556640 ) FS ;
+ - FILLER_67_365 gf180mcu_fd_sc_mcu7t5v0__fillcap_16 + SOURCE DIST + PLACED ( 422240 556640 ) FS ;
+ - FILLER_67_37 gf180mcu_fd_sc_mcu7t5v0__fillcap_16 + SOURCE DIST + PLACED ( 54880 556640 ) FS ;
+ - FILLER_67_381 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 440160 556640 ) FS ;
+ - FILLER_67_387 gf180mcu_fd_sc_mcu7t5v0__fillcap_8 + SOURCE DIST + PLACED ( 446880 556640 ) FS ;
+ - FILLER_67_395 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 455840 556640 ) FS ;
+ - FILLER_67_401 gf180mcu_fd_sc_mcu7t5v0__fillcap_8 + SOURCE DIST + PLACED ( 462560 556640 ) FS ;
+ - FILLER_67_409 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 471520 556640 ) FS ;
+ - FILLER_67_413 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 476000 556640 ) FS ;
+ - FILLER_67_419 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 482720 556640 ) FS ;
+ - FILLER_67_422 gf180mcu_fd_sc_mcu7t5v0__fillcap_8 + SOURCE DIST + PLACED ( 486080 556640 ) FS ;
+ - FILLER_67_430 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 495040 556640 ) FS ;
+ - FILLER_67_432 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 497280 556640 ) FS ;
+ - FILLER_67_437 gf180mcu_fd_sc_mcu7t5v0__fillcap_16 + SOURCE DIST + PLACED ( 502880 556640 ) FS ;
+ - FILLER_67_453 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 520800 556640 ) FS ;
+ - FILLER_67_457 gf180mcu_fd_sc_mcu7t5v0__fillcap_32 + SOURCE DIST + PLACED ( 525280 556640 ) FS ;
+ - FILLER_67_489 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 561120 556640 ) FS ;
+ - FILLER_67_492 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 564480 556640 ) FS ;
+ - FILLER_67_497 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 570080 556640 ) FS ;
+ - FILLER_67_501 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 574560 556640 ) FS ;
+ - FILLER_67_503 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 576800 556640 ) FS ;
+ - FILLER_67_508 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 582400 556640 ) FS ;
+ - FILLER_67_53 gf180mcu_fd_sc_mcu7t5v0__fillcap_8 + SOURCE DIST + PLACED ( 72800 556640 ) FS ;
+ - FILLER_67_6 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 20160 556640 ) FS ;
+ - FILLER_67_65 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 86240 556640 ) FS ;
+ - FILLER_67_69 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 90720 556640 ) FS ;
+ - FILLER_67_72 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 94080 556640 ) FS ;
+ - FILLER_67_76 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 98560 556640 ) FS ;
+ - FILLER_67_78 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 100800 556640 ) FS ;
+ - FILLER_67_83 gf180mcu_fd_sc_mcu7t5v0__fillcap_8 + SOURCE DIST + PLACED ( 106400 556640 ) FS ;
+ - FILLER_67_91 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 115360 556640 ) FS ;
+ - FILLER_67_95 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 119840 556640 ) FS ;
+ - FILLER_6_101 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 126560 78400 ) N ;
+ - FILLER_6_105 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 131040 78400 ) N ;
+ - FILLER_6_108 gf180mcu_fd_sc_mcu7t5v0__fillcap_64 + SOURCE DIST + PLACED ( 134400 78400 ) N ;
+ - FILLER_6_172 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 206080 78400 ) N ;
+ - FILLER_6_176 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 210560 78400 ) N ;
+ - FILLER_6_179 gf180mcu_fd_sc_mcu7t5v0__fillcap_32 + SOURCE DIST + PLACED ( 213920 78400 ) N ;
+ - FILLER_6_2 gf180mcu_fd_sc_mcu7t5v0__fillcap_32 + SOURCE DIST + PLACED ( 15680 78400 ) N ;
+ - FILLER_6_211 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 249760 78400 ) N ;
+ - FILLER_6_213 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 252000 78400 ) N ;
+ - FILLER_6_216 gf180mcu_fd_sc_mcu7t5v0__fillcap_8 + SOURCE DIST + PLACED ( 255360 78400 ) N ;
+ - FILLER_6_224 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 264320 78400 ) N ;
+ - FILLER_6_230 gf180mcu_fd_sc_mcu7t5v0__fillcap_8 + SOURCE DIST + PLACED ( 271040 78400 ) N ;
+ - FILLER_6_238 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 280000 78400 ) N ;
+ - FILLER_6_240 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 282240 78400 ) N ;
+ - FILLER_6_245 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 287840 78400 ) N ;
+ - FILLER_6_247 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 290080 78400 ) N ;
+ - FILLER_6_250 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 293440 78400 ) N ;
+ - FILLER_6_253 gf180mcu_fd_sc_mcu7t5v0__fillcap_32 + SOURCE DIST + PLACED ( 296800 78400 ) N ;
+ - FILLER_6_285 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 332640 78400 ) N ;
+ - FILLER_6_318 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 369600 78400 ) N ;
+ - FILLER_6_321 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 372960 78400 ) N ;
+ - FILLER_6_324 gf180mcu_fd_sc_mcu7t5v0__fillcap_64 + SOURCE DIST + PLACED ( 376320 78400 ) N ;
+ - FILLER_6_34 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 51520 78400 ) N ;
+ - FILLER_6_37 gf180mcu_fd_sc_mcu7t5v0__fillcap_64 + SOURCE DIST + PLACED ( 54880 78400 ) N ;
+ - FILLER_6_388 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 448000 78400 ) N ;
+ - FILLER_6_392 gf180mcu_fd_sc_mcu7t5v0__fillcap_64 + SOURCE DIST + PLACED ( 452480 78400 ) N ;
+ - FILLER_6_456 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 524160 78400 ) N ;
+ - FILLER_6_460 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 528640 78400 ) N ;
+ - FILLER_6_463 gf180mcu_fd_sc_mcu7t5v0__fillcap_32 + SOURCE DIST + PLACED ( 532000 78400 ) N ;
+ - FILLER_6_495 gf180mcu_fd_sc_mcu7t5v0__fillcap_8 + SOURCE DIST + PLACED ( 567840 78400 ) N ;
+ - FILLER_6_503 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 576800 78400 ) N ;
+ - FILLER_6_508 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 582400 78400 ) N ;
+ - FILLER_7_121 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 148960 86240 ) FS ;
+ - FILLER_7_125 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 153440 86240 ) FS ;
+ - FILLER_7_129 gf180mcu_fd_sc_mcu7t5v0__fillcap_8 + SOURCE DIST + PLACED ( 157920 86240 ) FS ;
+ - FILLER_7_137 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 166880 86240 ) FS ;
+ - FILLER_7_141 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 171360 86240 ) FS ;
+ - FILLER_7_144 gf180mcu_fd_sc_mcu7t5v0__fillcap_16 + SOURCE DIST + PLACED ( 174720 86240 ) FS ;
+ - FILLER_7_160 gf180mcu_fd_sc_mcu7t5v0__fillcap_8 + SOURCE DIST + PLACED ( 192640 86240 ) FS ;
+ - FILLER_7_168 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 201600 86240 ) FS ;
+ - FILLER_7_199 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 236320 86240 ) FS ;
+ - FILLER_7_2 gf180mcu_fd_sc_mcu7t5v0__fillcap_64 + SOURCE DIST + PLACED ( 15680 86240 ) FS ;
+ - FILLER_7_203 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 240800 86240 ) FS ;
+ - FILLER_7_207 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 245280 86240 ) FS ;
+ - FILLER_7_209 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 247520 86240 ) FS ;
+ - FILLER_7_212 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 250880 86240 ) FS ;
+ - FILLER_7_215 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 254240 86240 ) FS ;
+ - FILLER_7_245 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 287840 86240 ) FS ;
+ - FILLER_7_247 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 290080 86240 ) FS ;
+ - FILLER_7_250 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 293440 86240 ) FS ;
+ - FILLER_7_281 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 328160 86240 ) FS ;
+ - FILLER_7_283 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 330400 86240 ) FS ;
+ - FILLER_7_286 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 333760 86240 ) FS ;
+ - FILLER_7_316 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 367360 86240 ) FS ;
+ - FILLER_7_324 gf180mcu_fd_sc_mcu7t5v0__fillcap_16 + SOURCE DIST + PLACED ( 376320 86240 ) FS ;
+ - FILLER_7_340 gf180mcu_fd_sc_mcu7t5v0__fillcap_8 + SOURCE DIST + PLACED ( 394240 86240 ) FS ;
+ - FILLER_7_348 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 403200 86240 ) FS ;
+ - FILLER_7_352 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 407680 86240 ) FS ;
+ - FILLER_7_354 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 409920 86240 ) FS ;
+ - FILLER_7_357 gf180mcu_fd_sc_mcu7t5v0__fillcap_16 + SOURCE DIST + PLACED ( 413280 86240 ) FS ;
+ - FILLER_7_373 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 431200 86240 ) FS ;
+ - FILLER_7_379 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 437920 86240 ) FS ;
+ - FILLER_7_410 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 472640 86240 ) FS ;
+ - FILLER_7_414 gf180mcu_fd_sc_mcu7t5v0__fillcap_8 + SOURCE DIST + PLACED ( 477120 86240 ) FS ;
+ - FILLER_7_422 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 486080 86240 ) FS ;
+ - FILLER_7_428 gf180mcu_fd_sc_mcu7t5v0__fillcap_64 + SOURCE DIST + PLACED ( 492800 86240 ) FS ;
+ - FILLER_7_492 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 564480 86240 ) FS ;
+ - FILLER_7_496 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 568960 86240 ) FS ;
+ - FILLER_7_499 gf180mcu_fd_sc_mcu7t5v0__fillcap_8 + SOURCE DIST + PLACED ( 572320 86240 ) FS ;
+ - FILLER_7_507 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 581280 86240 ) FS ;
+ - FILLER_7_66 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 87360 86240 ) FS ;
+ - FILLER_7_70 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 91840 86240 ) FS ;
+ - FILLER_7_73 gf180mcu_fd_sc_mcu7t5v0__fillcap_16 + SOURCE DIST + PLACED ( 95200 86240 ) FS ;
+ - FILLER_7_89 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 113120 86240 ) FS ;
+ - FILLER_7_91 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 115360 86240 ) FS ;
+ - FILLER_8_101 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 126560 94080 ) N ;
+ - FILLER_8_105 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 131040 94080 ) N ;
+ - FILLER_8_108 gf180mcu_fd_sc_mcu7t5v0__fillcap_32 + SOURCE DIST + PLACED ( 134400 94080 ) N ;
+ - FILLER_8_140 gf180mcu_fd_sc_mcu7t5v0__fillcap_16 + SOURCE DIST + PLACED ( 170240 94080 ) N ;
+ - FILLER_8_156 gf180mcu_fd_sc_mcu7t5v0__fillcap_8 + SOURCE DIST + PLACED ( 188160 94080 ) N ;
+ - FILLER_8_164 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 197120 94080 ) N ;
+ - FILLER_8_168 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 201600 94080 ) N ;
+ - FILLER_8_175 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 209440 94080 ) N ;
+ - FILLER_8_179 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 213920 94080 ) N ;
+ - FILLER_8_182 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 217280 94080 ) N ;
+ - FILLER_8_2 gf180mcu_fd_sc_mcu7t5v0__fillcap_32 + SOURCE DIST + PLACED ( 15680 94080 ) N ;
+ - FILLER_8_215 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 254240 94080 ) N ;
+ - FILLER_8_219 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 258720 94080 ) N ;
+ - FILLER_8_222 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 262080 94080 ) N ;
+ - FILLER_8_228 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 268800 94080 ) N ;
+ - FILLER_8_242 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 284480 94080 ) N ;
+ - FILLER_8_246 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 288960 94080 ) N ;
+ - FILLER_8_250 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 293440 94080 ) N ;
+ - FILLER_8_252 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 295680 94080 ) N ;
+ - FILLER_8_271 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 316960 94080 ) N ;
+ - FILLER_8_277 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 323680 94080 ) N ;
+ - FILLER_8_281 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 328160 94080 ) N ;
+ - FILLER_8_289 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 337120 94080 ) N ;
+ - FILLER_8_297 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 346080 94080 ) N ;
+ - FILLER_8_301 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 350560 94080 ) N ;
+ - FILLER_8_305 gf180mcu_fd_sc_mcu7t5v0__fillcap_8 + SOURCE DIST + PLACED ( 355040 94080 ) N ;
+ - FILLER_8_313 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 364000 94080 ) N ;
+ - FILLER_8_315 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 366240 94080 ) N ;
+ - FILLER_8_318 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 369600 94080 ) N ;
+ - FILLER_8_321 gf180mcu_fd_sc_mcu7t5v0__fillcap_64 + SOURCE DIST + PLACED ( 372960 94080 ) N ;
+ - FILLER_8_34 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 51520 94080 ) N ;
+ - FILLER_8_37 gf180mcu_fd_sc_mcu7t5v0__fillcap_64 + SOURCE DIST + PLACED ( 54880 94080 ) N ;
+ - FILLER_8_385 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 444640 94080 ) N ;
+ - FILLER_8_389 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 449120 94080 ) N ;
+ - FILLER_8_392 gf180mcu_fd_sc_mcu7t5v0__fillcap_64 + SOURCE DIST + PLACED ( 452480 94080 ) N ;
+ - FILLER_8_456 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 524160 94080 ) N ;
+ - FILLER_8_460 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 528640 94080 ) N ;
+ - FILLER_8_463 gf180mcu_fd_sc_mcu7t5v0__fillcap_16 + SOURCE DIST + PLACED ( 532000 94080 ) N ;
+ - FILLER_8_479 gf180mcu_fd_sc_mcu7t5v0__fillcap_8 + SOURCE DIST + PLACED ( 549920 94080 ) N ;
+ - FILLER_8_487 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 558880 94080 ) N ;
+ - FILLER_8_489 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 561120 94080 ) N ;
+ - FILLER_8_492 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 564480 94080 ) N ;
+ - FILLER_8_508 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 582400 94080 ) N ;
+ - FILLER_9_137 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 166880 101920 ) FS ;
+ - FILLER_9_141 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 171360 101920 ) FS ;
+ - FILLER_9_144 gf180mcu_fd_sc_mcu7t5v0__fillcap_32 + SOURCE DIST + PLACED ( 174720 101920 ) FS ;
+ - FILLER_9_176 gf180mcu_fd_sc_mcu7t5v0__fillcap_16 + SOURCE DIST + PLACED ( 210560 101920 ) FS ;
+ - FILLER_9_194 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 230720 101920 ) FS ;
+ - FILLER_9_2 gf180mcu_fd_sc_mcu7t5v0__fillcap_64 + SOURCE DIST + PLACED ( 15680 101920 ) FS ;
+ - FILLER_9_202 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 239680 101920 ) FS ;
+ - FILLER_9_206 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 244160 101920 ) FS ;
+ - FILLER_9_210 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 248640 101920 ) FS ;
+ - FILLER_9_212 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 250880 101920 ) FS ;
+ - FILLER_9_215 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 254240 101920 ) FS ;
+ - FILLER_9_228 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 268800 101920 ) FS ;
+ - FILLER_9_236 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 277760 101920 ) FS ;
+ - FILLER_9_244 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 286720 101920 ) FS ;
+ - FILLER_9_258 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 302400 101920 ) FS ;
+ - FILLER_9_268 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 313600 101920 ) FS ;
+ - FILLER_9_278 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 324800 101920 ) FS ;
+ - FILLER_9_282 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 329280 101920 ) FS ;
+ - FILLER_9_286 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 333760 101920 ) FS ;
+ - FILLER_9_293 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 341600 101920 ) FS ;
+ - FILLER_9_297 gf180mcu_fd_sc_mcu7t5v0__fillcap_16 + SOURCE DIST + PLACED ( 346080 101920 ) FS ;
+ - FILLER_9_313 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 364000 101920 ) FS ;
+ - FILLER_9_317 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 368480 101920 ) FS ;
+ - FILLER_9_319 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 370720 101920 ) FS ;
+ - FILLER_9_349 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 404320 101920 ) FS ;
+ - FILLER_9_353 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 408800 101920 ) FS ;
+ - FILLER_9_357 gf180mcu_fd_sc_mcu7t5v0__fillcap_64 + SOURCE DIST + PLACED ( 413280 101920 ) FS ;
+ - FILLER_9_421 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 484960 101920 ) FS ;
+ - FILLER_9_425 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 489440 101920 ) FS ;
+ - FILLER_9_428 gf180mcu_fd_sc_mcu7t5v0__fillcap_64 + SOURCE DIST + PLACED ( 492800 101920 ) FS ;
+ - FILLER_9_492 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 564480 101920 ) FS ;
+ - FILLER_9_496 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 568960 101920 ) FS ;
+ - FILLER_9_499 gf180mcu_fd_sc_mcu7t5v0__fillcap_8 + SOURCE DIST + PLACED ( 572320 101920 ) FS ;
+ - FILLER_9_507 gf180mcu_fd_sc_mcu7t5v0__fill_2 + SOURCE DIST + PLACED ( 581280 101920 ) FS ;
+ - FILLER_9_66 gf180mcu_fd_sc_mcu7t5v0__fillcap_4 + SOURCE DIST + PLACED ( 87360 101920 ) FS ;
+ - FILLER_9_70 gf180mcu_fd_sc_mcu7t5v0__fill_1 + SOURCE DIST + PLACED ( 91840 101920 ) FS ;
+ - FILLER_9_73 gf180mcu_fd_sc_mcu7t5v0__fillcap_64 + SOURCE DIST + PLACED ( 95200 101920 ) FS ;
+ - PHY_0 gf180mcu_fd_sc_mcu7t5v0__endcap + SOURCE DIST + FIXED ( 13440 31360 ) N ;
+ - PHY_1 gf180mcu_fd_sc_mcu7t5v0__endcap + SOURCE DIST + FIXED ( 583520 31360 ) FN ;
+ - PHY_10 gf180mcu_fd_sc_mcu7t5v0__endcap + SOURCE DIST + FIXED ( 13440 70560 ) FS ;
+ - PHY_100 gf180mcu_fd_sc_mcu7t5v0__endcap + SOURCE DIST + FIXED ( 13440 423360 ) N ;
+ - PHY_101 gf180mcu_fd_sc_mcu7t5v0__endcap + SOURCE DIST + FIXED ( 583520 423360 ) FN ;
+ - PHY_102 gf180mcu_fd_sc_mcu7t5v0__endcap + SOURCE DIST + FIXED ( 13440 431200 ) FS ;
+ - PHY_103 gf180mcu_fd_sc_mcu7t5v0__endcap + SOURCE DIST + FIXED ( 583520 431200 ) S ;
+ - PHY_104 gf180mcu_fd_sc_mcu7t5v0__endcap + SOURCE DIST + FIXED ( 13440 439040 ) N ;
+ - PHY_105 gf180mcu_fd_sc_mcu7t5v0__endcap + SOURCE DIST + FIXED ( 583520 439040 ) FN ;
+ - PHY_106 gf180mcu_fd_sc_mcu7t5v0__endcap + SOURCE DIST + FIXED ( 13440 446880 ) FS ;
+ - PHY_107 gf180mcu_fd_sc_mcu7t5v0__endcap + SOURCE DIST + FIXED ( 583520 446880 ) S ;
+ - PHY_108 gf180mcu_fd_sc_mcu7t5v0__endcap + SOURCE DIST + FIXED ( 13440 454720 ) N ;
+ - PHY_109 gf180mcu_fd_sc_mcu7t5v0__endcap + SOURCE DIST + FIXED ( 583520 454720 ) FN ;
+ - PHY_11 gf180mcu_fd_sc_mcu7t5v0__endcap + SOURCE DIST + FIXED ( 583520 70560 ) S ;
+ - PHY_110 gf180mcu_fd_sc_mcu7t5v0__endcap + SOURCE DIST + FIXED ( 13440 462560 ) FS ;
+ - PHY_111 gf180mcu_fd_sc_mcu7t5v0__endcap + SOURCE DIST + FIXED ( 583520 462560 ) S ;
+ - PHY_112 gf180mcu_fd_sc_mcu7t5v0__endcap + SOURCE DIST + FIXED ( 13440 470400 ) N ;
+ - PHY_113 gf180mcu_fd_sc_mcu7t5v0__endcap + SOURCE DIST + FIXED ( 583520 470400 ) FN ;
+ - PHY_114 gf180mcu_fd_sc_mcu7t5v0__endcap + SOURCE DIST + FIXED ( 13440 478240 ) FS ;
+ - PHY_115 gf180mcu_fd_sc_mcu7t5v0__endcap + SOURCE DIST + FIXED ( 583520 478240 ) S ;
+ - PHY_116 gf180mcu_fd_sc_mcu7t5v0__endcap + SOURCE DIST + FIXED ( 13440 486080 ) N ;
+ - PHY_117 gf180mcu_fd_sc_mcu7t5v0__endcap + SOURCE DIST + FIXED ( 583520 486080 ) FN ;
+ - PHY_118 gf180mcu_fd_sc_mcu7t5v0__endcap + SOURCE DIST + FIXED ( 13440 493920 ) FS ;
+ - PHY_119 gf180mcu_fd_sc_mcu7t5v0__endcap + SOURCE DIST + FIXED ( 583520 493920 ) S ;
+ - PHY_12 gf180mcu_fd_sc_mcu7t5v0__endcap + SOURCE DIST + FIXED ( 13440 78400 ) N ;
+ - PHY_120 gf180mcu_fd_sc_mcu7t5v0__endcap + SOURCE DIST + FIXED ( 13440 501760 ) N ;
+ - PHY_121 gf180mcu_fd_sc_mcu7t5v0__endcap + SOURCE DIST + FIXED ( 583520 501760 ) FN ;
+ - PHY_122 gf180mcu_fd_sc_mcu7t5v0__endcap + SOURCE DIST + FIXED ( 13440 509600 ) FS ;
+ - PHY_123 gf180mcu_fd_sc_mcu7t5v0__endcap + SOURCE DIST + FIXED ( 583520 509600 ) S ;
+ - PHY_124 gf180mcu_fd_sc_mcu7t5v0__endcap + SOURCE DIST + FIXED ( 13440 517440 ) N ;
+ - PHY_125 gf180mcu_fd_sc_mcu7t5v0__endcap + SOURCE DIST + FIXED ( 583520 517440 ) FN ;
+ - PHY_126 gf180mcu_fd_sc_mcu7t5v0__endcap + SOURCE DIST + FIXED ( 13440 525280 ) FS ;
+ - PHY_127 gf180mcu_fd_sc_mcu7t5v0__endcap + SOURCE DIST + FIXED ( 583520 525280 ) S ;
+ - PHY_128 gf180mcu_fd_sc_mcu7t5v0__endcap + SOURCE DIST + FIXED ( 13440 533120 ) N ;
+ - PHY_129 gf180mcu_fd_sc_mcu7t5v0__endcap + SOURCE DIST + FIXED ( 583520 533120 ) FN ;
+ - PHY_13 gf180mcu_fd_sc_mcu7t5v0__endcap + SOURCE DIST + FIXED ( 583520 78400 ) FN ;
+ - PHY_130 gf180mcu_fd_sc_mcu7t5v0__endcap + SOURCE DIST + FIXED ( 13440 540960 ) FS ;
+ - PHY_131 gf180mcu_fd_sc_mcu7t5v0__endcap + SOURCE DIST + FIXED ( 583520 540960 ) S ;
+ - PHY_132 gf180mcu_fd_sc_mcu7t5v0__endcap + SOURCE DIST + FIXED ( 13440 548800 ) N ;
+ - PHY_133 gf180mcu_fd_sc_mcu7t5v0__endcap + SOURCE DIST + FIXED ( 583520 548800 ) FN ;
+ - PHY_134 gf180mcu_fd_sc_mcu7t5v0__endcap + SOURCE DIST + FIXED ( 13440 556640 ) FS ;
+ - PHY_135 gf180mcu_fd_sc_mcu7t5v0__endcap + SOURCE DIST + FIXED ( 583520 556640 ) S ;
+ - PHY_14 gf180mcu_fd_sc_mcu7t5v0__endcap + SOURCE DIST + FIXED ( 13440 86240 ) FS ;
+ - PHY_15 gf180mcu_fd_sc_mcu7t5v0__endcap + SOURCE DIST + FIXED ( 583520 86240 ) S ;
+ - PHY_16 gf180mcu_fd_sc_mcu7t5v0__endcap + SOURCE DIST + FIXED ( 13440 94080 ) N ;
+ - PHY_17 gf180mcu_fd_sc_mcu7t5v0__endcap + SOURCE DIST + FIXED ( 583520 94080 ) FN ;
+ - PHY_18 gf180mcu_fd_sc_mcu7t5v0__endcap + SOURCE DIST + FIXED ( 13440 101920 ) FS ;
+ - PHY_19 gf180mcu_fd_sc_mcu7t5v0__endcap + SOURCE DIST + FIXED ( 583520 101920 ) S ;
+ - PHY_2 gf180mcu_fd_sc_mcu7t5v0__endcap + SOURCE DIST + FIXED ( 13440 39200 ) FS ;
+ - PHY_20 gf180mcu_fd_sc_mcu7t5v0__endcap + SOURCE DIST + FIXED ( 13440 109760 ) N ;
+ - PHY_21 gf180mcu_fd_sc_mcu7t5v0__endcap + SOURCE DIST + FIXED ( 583520 109760 ) FN ;
+ - PHY_22 gf180mcu_fd_sc_mcu7t5v0__endcap + SOURCE DIST + FIXED ( 13440 117600 ) FS ;
+ - PHY_23 gf180mcu_fd_sc_mcu7t5v0__endcap + SOURCE DIST + FIXED ( 583520 117600 ) S ;
+ - PHY_24 gf180mcu_fd_sc_mcu7t5v0__endcap + SOURCE DIST + FIXED ( 13440 125440 ) N ;
+ - PHY_25 gf180mcu_fd_sc_mcu7t5v0__endcap + SOURCE DIST + FIXED ( 583520 125440 ) FN ;
+ - PHY_26 gf180mcu_fd_sc_mcu7t5v0__endcap + SOURCE DIST + FIXED ( 13440 133280 ) FS ;
+ - PHY_27 gf180mcu_fd_sc_mcu7t5v0__endcap + SOURCE DIST + FIXED ( 583520 133280 ) S ;
+ - PHY_28 gf180mcu_fd_sc_mcu7t5v0__endcap + SOURCE DIST + FIXED ( 13440 141120 ) N ;
+ - PHY_29 gf180mcu_fd_sc_mcu7t5v0__endcap + SOURCE DIST + FIXED ( 583520 141120 ) FN ;
+ - PHY_3 gf180mcu_fd_sc_mcu7t5v0__endcap + SOURCE DIST + FIXED ( 583520 39200 ) S ;
+ - PHY_30 gf180mcu_fd_sc_mcu7t5v0__endcap + SOURCE DIST + FIXED ( 13440 148960 ) FS ;
+ - PHY_31 gf180mcu_fd_sc_mcu7t5v0__endcap + SOURCE DIST + FIXED ( 583520 148960 ) S ;
+ - PHY_32 gf180mcu_fd_sc_mcu7t5v0__endcap + SOURCE DIST + FIXED ( 13440 156800 ) N ;
+ - PHY_33 gf180mcu_fd_sc_mcu7t5v0__endcap + SOURCE DIST + FIXED ( 583520 156800 ) FN ;
+ - PHY_34 gf180mcu_fd_sc_mcu7t5v0__endcap + SOURCE DIST + FIXED ( 13440 164640 ) FS ;
+ - PHY_35 gf180mcu_fd_sc_mcu7t5v0__endcap + SOURCE DIST + FIXED ( 583520 164640 ) S ;
+ - PHY_36 gf180mcu_fd_sc_mcu7t5v0__endcap + SOURCE DIST + FIXED ( 13440 172480 ) N ;
+ - PHY_37 gf180mcu_fd_sc_mcu7t5v0__endcap + SOURCE DIST + FIXED ( 583520 172480 ) FN ;
+ - PHY_38 gf180mcu_fd_sc_mcu7t5v0__endcap + SOURCE DIST + FIXED ( 13440 180320 ) FS ;
+ - PHY_39 gf180mcu_fd_sc_mcu7t5v0__endcap + SOURCE DIST + FIXED ( 583520 180320 ) S ;
+ - PHY_4 gf180mcu_fd_sc_mcu7t5v0__endcap + SOURCE DIST + FIXED ( 13440 47040 ) N ;
+ - PHY_40 gf180mcu_fd_sc_mcu7t5v0__endcap + SOURCE DIST + FIXED ( 13440 188160 ) N ;
+ - PHY_41 gf180mcu_fd_sc_mcu7t5v0__endcap + SOURCE DIST + FIXED ( 583520 188160 ) FN ;
+ - PHY_42 gf180mcu_fd_sc_mcu7t5v0__endcap + SOURCE DIST + FIXED ( 13440 196000 ) FS ;
+ - PHY_43 gf180mcu_fd_sc_mcu7t5v0__endcap + SOURCE DIST + FIXED ( 583520 196000 ) S ;
+ - PHY_44 gf180mcu_fd_sc_mcu7t5v0__endcap + SOURCE DIST + FIXED ( 13440 203840 ) N ;
+ - PHY_45 gf180mcu_fd_sc_mcu7t5v0__endcap + SOURCE DIST + FIXED ( 583520 203840 ) FN ;
+ - PHY_46 gf180mcu_fd_sc_mcu7t5v0__endcap + SOURCE DIST + FIXED ( 13440 211680 ) FS ;
+ - PHY_47 gf180mcu_fd_sc_mcu7t5v0__endcap + SOURCE DIST + FIXED ( 583520 211680 ) S ;
+ - PHY_48 gf180mcu_fd_sc_mcu7t5v0__endcap + SOURCE DIST + FIXED ( 13440 219520 ) N ;
+ - PHY_49 gf180mcu_fd_sc_mcu7t5v0__endcap + SOURCE DIST + FIXED ( 583520 219520 ) FN ;
+ - PHY_5 gf180mcu_fd_sc_mcu7t5v0__endcap + SOURCE DIST + FIXED ( 583520 47040 ) FN ;
+ - PHY_50 gf180mcu_fd_sc_mcu7t5v0__endcap + SOURCE DIST + FIXED ( 13440 227360 ) FS ;
+ - PHY_51 gf180mcu_fd_sc_mcu7t5v0__endcap + SOURCE DIST + FIXED ( 583520 227360 ) S ;
+ - PHY_52 gf180mcu_fd_sc_mcu7t5v0__endcap + SOURCE DIST + FIXED ( 13440 235200 ) N ;
+ - PHY_53 gf180mcu_fd_sc_mcu7t5v0__endcap + SOURCE DIST + FIXED ( 583520 235200 ) FN ;
+ - PHY_54 gf180mcu_fd_sc_mcu7t5v0__endcap + SOURCE DIST + FIXED ( 13440 243040 ) FS ;
+ - PHY_55 gf180mcu_fd_sc_mcu7t5v0__endcap + SOURCE DIST + FIXED ( 583520 243040 ) S ;
+ - PHY_56 gf180mcu_fd_sc_mcu7t5v0__endcap + SOURCE DIST + FIXED ( 13440 250880 ) N ;
+ - PHY_57 gf180mcu_fd_sc_mcu7t5v0__endcap + SOURCE DIST + FIXED ( 583520 250880 ) FN ;
+ - PHY_58 gf180mcu_fd_sc_mcu7t5v0__endcap + SOURCE DIST + FIXED ( 13440 258720 ) FS ;
+ - PHY_59 gf180mcu_fd_sc_mcu7t5v0__endcap + SOURCE DIST + FIXED ( 583520 258720 ) S ;
+ - PHY_6 gf180mcu_fd_sc_mcu7t5v0__endcap + SOURCE DIST + FIXED ( 13440 54880 ) FS ;
+ - PHY_60 gf180mcu_fd_sc_mcu7t5v0__endcap + SOURCE DIST + FIXED ( 13440 266560 ) N ;
+ - PHY_61 gf180mcu_fd_sc_mcu7t5v0__endcap + SOURCE DIST + FIXED ( 583520 266560 ) FN ;
+ - PHY_62 gf180mcu_fd_sc_mcu7t5v0__endcap + SOURCE DIST + FIXED ( 13440 274400 ) FS ;
+ - PHY_63 gf180mcu_fd_sc_mcu7t5v0__endcap + SOURCE DIST + FIXED ( 583520 274400 ) S ;
+ - PHY_64 gf180mcu_fd_sc_mcu7t5v0__endcap + SOURCE DIST + FIXED ( 13440 282240 ) N ;
+ - PHY_65 gf180mcu_fd_sc_mcu7t5v0__endcap + SOURCE DIST + FIXED ( 583520 282240 ) FN ;
+ - PHY_66 gf180mcu_fd_sc_mcu7t5v0__endcap + SOURCE DIST + FIXED ( 13440 290080 ) FS ;
+ - PHY_67 gf180mcu_fd_sc_mcu7t5v0__endcap + SOURCE DIST + FIXED ( 583520 290080 ) S ;
+ - PHY_68 gf180mcu_fd_sc_mcu7t5v0__endcap + SOURCE DIST + FIXED ( 13440 297920 ) N ;
+ - PHY_69 gf180mcu_fd_sc_mcu7t5v0__endcap + SOURCE DIST + FIXED ( 583520 297920 ) FN ;
+ - PHY_7 gf180mcu_fd_sc_mcu7t5v0__endcap + SOURCE DIST + FIXED ( 583520 54880 ) S ;
+ - PHY_70 gf180mcu_fd_sc_mcu7t5v0__endcap + SOURCE DIST + FIXED ( 13440 305760 ) FS ;
+ - PHY_71 gf180mcu_fd_sc_mcu7t5v0__endcap + SOURCE DIST + FIXED ( 583520 305760 ) S ;
+ - PHY_72 gf180mcu_fd_sc_mcu7t5v0__endcap + SOURCE DIST + FIXED ( 13440 313600 ) N ;
+ - PHY_73 gf180mcu_fd_sc_mcu7t5v0__endcap + SOURCE DIST + FIXED ( 583520 313600 ) FN ;
+ - PHY_74 gf180mcu_fd_sc_mcu7t5v0__endcap + SOURCE DIST + FIXED ( 13440 321440 ) FS ;
+ - PHY_75 gf180mcu_fd_sc_mcu7t5v0__endcap + SOURCE DIST + FIXED ( 583520 321440 ) S ;
+ - PHY_76 gf180mcu_fd_sc_mcu7t5v0__endcap + SOURCE DIST + FIXED ( 13440 329280 ) N ;
+ - PHY_77 gf180mcu_fd_sc_mcu7t5v0__endcap + SOURCE DIST + FIXED ( 583520 329280 ) FN ;
+ - PHY_78 gf180mcu_fd_sc_mcu7t5v0__endcap + SOURCE DIST + FIXED ( 13440 337120 ) FS ;
+ - PHY_79 gf180mcu_fd_sc_mcu7t5v0__endcap + SOURCE DIST + FIXED ( 583520 337120 ) S ;
+ - PHY_8 gf180mcu_fd_sc_mcu7t5v0__endcap + SOURCE DIST + FIXED ( 13440 62720 ) N ;
+ - PHY_80 gf180mcu_fd_sc_mcu7t5v0__endcap + SOURCE DIST + FIXED ( 13440 344960 ) N ;
+ - PHY_81 gf180mcu_fd_sc_mcu7t5v0__endcap + SOURCE DIST + FIXED ( 583520 344960 ) FN ;
+ - PHY_82 gf180mcu_fd_sc_mcu7t5v0__endcap + SOURCE DIST + FIXED ( 13440 352800 ) FS ;
+ - PHY_83 gf180mcu_fd_sc_mcu7t5v0__endcap + SOURCE DIST + FIXED ( 583520 352800 ) S ;
+ - PHY_84 gf180mcu_fd_sc_mcu7t5v0__endcap + SOURCE DIST + FIXED ( 13440 360640 ) N ;
+ - PHY_85 gf180mcu_fd_sc_mcu7t5v0__endcap + SOURCE DIST + FIXED ( 583520 360640 ) FN ;
+ - PHY_86 gf180mcu_fd_sc_mcu7t5v0__endcap + SOURCE DIST + FIXED ( 13440 368480 ) FS ;
+ - PHY_87 gf180mcu_fd_sc_mcu7t5v0__endcap + SOURCE DIST + FIXED ( 583520 368480 ) S ;
+ - PHY_88 gf180mcu_fd_sc_mcu7t5v0__endcap + SOURCE DIST + FIXED ( 13440 376320 ) N ;
+ - PHY_89 gf180mcu_fd_sc_mcu7t5v0__endcap + SOURCE DIST + FIXED ( 583520 376320 ) FN ;
+ - PHY_9 gf180mcu_fd_sc_mcu7t5v0__endcap + SOURCE DIST + FIXED ( 583520 62720 ) FN ;
+ - PHY_90 gf180mcu_fd_sc_mcu7t5v0__endcap + SOURCE DIST + FIXED ( 13440 384160 ) FS ;
+ - PHY_91 gf180mcu_fd_sc_mcu7t5v0__endcap + SOURCE DIST + FIXED ( 583520 384160 ) S ;
+ - PHY_92 gf180mcu_fd_sc_mcu7t5v0__endcap + SOURCE DIST + FIXED ( 13440 392000 ) N ;
+ - PHY_93 gf180mcu_fd_sc_mcu7t5v0__endcap + SOURCE DIST + FIXED ( 583520 392000 ) FN ;
+ - PHY_94 gf180mcu_fd_sc_mcu7t5v0__endcap + SOURCE DIST + FIXED ( 13440 399840 ) FS ;
+ - PHY_95 gf180mcu_fd_sc_mcu7t5v0__endcap + SOURCE DIST + FIXED ( 583520 399840 ) S ;
+ - PHY_96 gf180mcu_fd_sc_mcu7t5v0__endcap + SOURCE DIST + FIXED ( 13440 407680 ) N ;
+ - PHY_97 gf180mcu_fd_sc_mcu7t5v0__endcap + SOURCE DIST + FIXED ( 583520 407680 ) FN ;
+ - PHY_98 gf180mcu_fd_sc_mcu7t5v0__endcap + SOURCE DIST + FIXED ( 13440 415520 ) FS ;
+ - PHY_99 gf180mcu_fd_sc_mcu7t5v0__endcap + SOURCE DIST + FIXED ( 583520 415520 ) S ;
+ - TAP_136 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 52640 31360 ) N ;
+ - TAP_137 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 91840 31360 ) N ;
+ - TAP_138 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 131040 31360 ) N ;
+ - TAP_139 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 170240 31360 ) N ;
+ - TAP_140 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 209440 31360 ) N ;
+ - TAP_141 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 248640 31360 ) N ;
+ - TAP_142 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 287840 31360 ) N ;
+ - TAP_143 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 327040 31360 ) N ;
+ - TAP_144 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 366240 31360 ) N ;
+ - TAP_145 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 405440 31360 ) N ;
+ - TAP_146 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 444640 31360 ) N ;
+ - TAP_147 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 483840 31360 ) N ;
+ - TAP_148 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 523040 31360 ) N ;
+ - TAP_149 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 562240 31360 ) N ;
+ - TAP_150 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 92960 39200 ) FS ;
+ - TAP_151 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 172480 39200 ) FS ;
+ - TAP_152 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 252000 39200 ) FS ;
+ - TAP_153 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 331520 39200 ) FS ;
+ - TAP_154 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 411040 39200 ) FS ;
+ - TAP_155 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 490560 39200 ) FS ;
+ - TAP_156 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 570080 39200 ) FS ;
+ - TAP_157 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 52640 47040 ) N ;
+ - TAP_158 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 132160 47040 ) N ;
+ - TAP_159 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 211680 47040 ) N ;
+ - TAP_160 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 291200 47040 ) N ;
+ - TAP_161 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 370720 47040 ) N ;
+ - TAP_162 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 450240 47040 ) N ;
+ - TAP_163 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 529760 47040 ) N ;
+ - TAP_164 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 92960 54880 ) FS ;
+ - TAP_165 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 172480 54880 ) FS ;
+ - TAP_166 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 252000 54880 ) FS ;
+ - TAP_167 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 331520 54880 ) FS ;
+ - TAP_168 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 411040 54880 ) FS ;
+ - TAP_169 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 490560 54880 ) FS ;
+ - TAP_170 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 570080 54880 ) FS ;
+ - TAP_171 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 52640 62720 ) N ;
+ - TAP_172 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 132160 62720 ) N ;
+ - TAP_173 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 211680 62720 ) N ;
+ - TAP_174 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 291200 62720 ) N ;
+ - TAP_175 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 370720 62720 ) N ;
+ - TAP_176 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 450240 62720 ) N ;
+ - TAP_177 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 529760 62720 ) N ;
+ - TAP_178 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 92960 70560 ) FS ;
+ - TAP_179 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 172480 70560 ) FS ;
+ - TAP_180 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 252000 70560 ) FS ;
+ - TAP_181 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 331520 70560 ) FS ;
+ - TAP_182 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 411040 70560 ) FS ;
+ - TAP_183 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 490560 70560 ) FS ;
+ - TAP_184 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 570080 70560 ) FS ;
+ - TAP_185 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 52640 78400 ) N ;
+ - TAP_186 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 132160 78400 ) N ;
+ - TAP_187 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 211680 78400 ) N ;
+ - TAP_188 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 291200 78400 ) N ;
+ - TAP_189 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 370720 78400 ) N ;
+ - TAP_190 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 450240 78400 ) N ;
+ - TAP_191 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 529760 78400 ) N ;
+ - TAP_192 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 92960 86240 ) FS ;
+ - TAP_193 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 172480 86240 ) FS ;
+ - TAP_194 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 252000 86240 ) FS ;
+ - TAP_195 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 331520 86240 ) FS ;
+ - TAP_196 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 411040 86240 ) FS ;
+ - TAP_197 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 490560 86240 ) FS ;
+ - TAP_198 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 570080 86240 ) FS ;
+ - TAP_199 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 52640 94080 ) N ;
+ - TAP_200 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 132160 94080 ) N ;
+ - TAP_201 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 211680 94080 ) N ;
+ - TAP_202 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 291200 94080 ) N ;
+ - TAP_203 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 370720 94080 ) N ;
+ - TAP_204 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 450240 94080 ) N ;
+ - TAP_205 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 529760 94080 ) N ;
+ - TAP_206 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 92960 101920 ) FS ;
+ - TAP_207 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 172480 101920 ) FS ;
+ - TAP_208 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 252000 101920 ) FS ;
+ - TAP_209 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 331520 101920 ) FS ;
+ - TAP_210 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 411040 101920 ) FS ;
+ - TAP_211 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 490560 101920 ) FS ;
+ - TAP_212 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 570080 101920 ) FS ;
+ - TAP_213 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 52640 109760 ) N ;
+ - TAP_214 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 132160 109760 ) N ;
+ - TAP_215 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 211680 109760 ) N ;
+ - TAP_216 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 291200 109760 ) N ;
+ - TAP_217 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 370720 109760 ) N ;
+ - TAP_218 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 450240 109760 ) N ;
+ - TAP_219 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 529760 109760 ) N ;
+ - TAP_220 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 92960 117600 ) FS ;
+ - TAP_221 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 172480 117600 ) FS ;
+ - TAP_222 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 252000 117600 ) FS ;
+ - TAP_223 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 331520 117600 ) FS ;
+ - TAP_224 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 411040 117600 ) FS ;
+ - TAP_225 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 490560 117600 ) FS ;
+ - TAP_226 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 570080 117600 ) FS ;
+ - TAP_227 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 52640 125440 ) N ;
+ - TAP_228 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 132160 125440 ) N ;
+ - TAP_229 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 211680 125440 ) N ;
+ - TAP_230 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 291200 125440 ) N ;
+ - TAP_231 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 370720 125440 ) N ;
+ - TAP_232 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 450240 125440 ) N ;
+ - TAP_233 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 529760 125440 ) N ;
+ - TAP_234 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 92960 133280 ) FS ;
+ - TAP_235 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 172480 133280 ) FS ;
+ - TAP_236 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 252000 133280 ) FS ;
+ - TAP_237 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 331520 133280 ) FS ;
+ - TAP_238 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 411040 133280 ) FS ;
+ - TAP_239 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 490560 133280 ) FS ;
+ - TAP_240 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 570080 133280 ) FS ;
+ - TAP_241 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 52640 141120 ) N ;
+ - TAP_242 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 132160 141120 ) N ;
+ - TAP_243 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 211680 141120 ) N ;
+ - TAP_244 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 291200 141120 ) N ;
+ - TAP_245 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 370720 141120 ) N ;
+ - TAP_246 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 450240 141120 ) N ;
+ - TAP_247 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 529760 141120 ) N ;
+ - TAP_248 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 92960 148960 ) FS ;
+ - TAP_249 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 172480 148960 ) FS ;
+ - TAP_250 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 252000 148960 ) FS ;
+ - TAP_251 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 331520 148960 ) FS ;
+ - TAP_252 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 411040 148960 ) FS ;
+ - TAP_253 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 490560 148960 ) FS ;
+ - TAP_254 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 570080 148960 ) FS ;
+ - TAP_255 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 52640 156800 ) N ;
+ - TAP_256 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 132160 156800 ) N ;
+ - TAP_257 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 211680 156800 ) N ;
+ - TAP_258 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 291200 156800 ) N ;
+ - TAP_259 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 370720 156800 ) N ;
+ - TAP_260 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 450240 156800 ) N ;
+ - TAP_261 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 529760 156800 ) N ;
+ - TAP_262 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 92960 164640 ) FS ;
+ - TAP_263 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 172480 164640 ) FS ;
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+ - TAP_269 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 52640 172480 ) N ;
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+ - TAP_272 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 291200 172480 ) N ;
+ - TAP_273 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 370720 172480 ) N ;
+ - TAP_274 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 450240 172480 ) N ;
+ - TAP_275 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 529760 172480 ) N ;
+ - TAP_276 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 92960 180320 ) FS ;
+ - TAP_277 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 172480 180320 ) FS ;
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+ - TAP_283 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 52640 188160 ) N ;
+ - TAP_284 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 132160 188160 ) N ;
+ - TAP_285 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 211680 188160 ) N ;
+ - TAP_286 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 291200 188160 ) N ;
+ - TAP_287 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 370720 188160 ) N ;
+ - TAP_288 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 450240 188160 ) N ;
+ - TAP_289 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 529760 188160 ) N ;
+ - TAP_290 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 92960 196000 ) FS ;
+ - TAP_291 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 172480 196000 ) FS ;
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+ - TAP_295 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 490560 196000 ) FS ;
+ - TAP_296 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 570080 196000 ) FS ;
+ - TAP_297 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 52640 203840 ) N ;
+ - TAP_298 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 132160 203840 ) N ;
+ - TAP_299 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 211680 203840 ) N ;
+ - TAP_300 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 291200 203840 ) N ;
+ - TAP_301 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 370720 203840 ) N ;
+ - TAP_302 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 450240 203840 ) N ;
+ - TAP_303 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 529760 203840 ) N ;
+ - TAP_304 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 92960 211680 ) FS ;
+ - TAP_305 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 172480 211680 ) FS ;
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+ - TAP_308 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 411040 211680 ) FS ;
+ - TAP_309 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 490560 211680 ) FS ;
+ - TAP_310 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 570080 211680 ) FS ;
+ - TAP_311 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 52640 219520 ) N ;
+ - TAP_312 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 132160 219520 ) N ;
+ - TAP_313 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 211680 219520 ) N ;
+ - TAP_314 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 291200 219520 ) N ;
+ - TAP_315 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 370720 219520 ) N ;
+ - TAP_316 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 450240 219520 ) N ;
+ - TAP_317 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 529760 219520 ) N ;
+ - TAP_318 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 92960 227360 ) FS ;
+ - TAP_319 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 172480 227360 ) FS ;
+ - TAP_320 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 252000 227360 ) FS ;
+ - TAP_321 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 331520 227360 ) FS ;
+ - TAP_322 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 411040 227360 ) FS ;
+ - TAP_323 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 490560 227360 ) FS ;
+ - TAP_324 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 570080 227360 ) FS ;
+ - TAP_325 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 52640 235200 ) N ;
+ - TAP_326 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 132160 235200 ) N ;
+ - TAP_327 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 211680 235200 ) N ;
+ - TAP_328 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 291200 235200 ) N ;
+ - TAP_329 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 370720 235200 ) N ;
+ - TAP_330 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 450240 235200 ) N ;
+ - TAP_331 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 529760 235200 ) N ;
+ - TAP_332 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 92960 243040 ) FS ;
+ - TAP_333 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 172480 243040 ) FS ;
+ - TAP_334 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 252000 243040 ) FS ;
+ - TAP_335 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 331520 243040 ) FS ;
+ - TAP_336 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 411040 243040 ) FS ;
+ - TAP_337 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 490560 243040 ) FS ;
+ - TAP_338 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 570080 243040 ) FS ;
+ - TAP_339 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 52640 250880 ) N ;
+ - TAP_340 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 132160 250880 ) N ;
+ - TAP_341 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 211680 250880 ) N ;
+ - TAP_342 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 291200 250880 ) N ;
+ - TAP_343 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 370720 250880 ) N ;
+ - TAP_344 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 450240 250880 ) N ;
+ - TAP_345 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 529760 250880 ) N ;
+ - TAP_346 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 92960 258720 ) FS ;
+ - TAP_347 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 172480 258720 ) FS ;
+ - TAP_348 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 252000 258720 ) FS ;
+ - TAP_349 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 331520 258720 ) FS ;
+ - TAP_350 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 411040 258720 ) FS ;
+ - TAP_351 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 490560 258720 ) FS ;
+ - TAP_352 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 570080 258720 ) FS ;
+ - TAP_353 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 52640 266560 ) N ;
+ - TAP_354 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 132160 266560 ) N ;
+ - TAP_355 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 211680 266560 ) N ;
+ - TAP_356 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 291200 266560 ) N ;
+ - TAP_357 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 370720 266560 ) N ;
+ - TAP_358 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 450240 266560 ) N ;
+ - TAP_359 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 529760 266560 ) N ;
+ - TAP_360 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 92960 274400 ) FS ;
+ - TAP_361 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 172480 274400 ) FS ;
+ - TAP_362 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 252000 274400 ) FS ;
+ - TAP_363 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 331520 274400 ) FS ;
+ - TAP_364 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 411040 274400 ) FS ;
+ - TAP_365 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 490560 274400 ) FS ;
+ - TAP_366 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 570080 274400 ) FS ;
+ - TAP_367 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 52640 282240 ) N ;
+ - TAP_368 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 132160 282240 ) N ;
+ - TAP_369 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 211680 282240 ) N ;
+ - TAP_370 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 291200 282240 ) N ;
+ - TAP_371 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 370720 282240 ) N ;
+ - TAP_372 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 450240 282240 ) N ;
+ - TAP_373 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 529760 282240 ) N ;
+ - TAP_374 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 92960 290080 ) FS ;
+ - TAP_375 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 172480 290080 ) FS ;
+ - TAP_376 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 252000 290080 ) FS ;
+ - TAP_377 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 331520 290080 ) FS ;
+ - TAP_378 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 411040 290080 ) FS ;
+ - TAP_379 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 490560 290080 ) FS ;
+ - TAP_380 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 570080 290080 ) FS ;
+ - TAP_381 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 52640 297920 ) N ;
+ - TAP_382 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 132160 297920 ) N ;
+ - TAP_383 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 211680 297920 ) N ;
+ - TAP_384 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 291200 297920 ) N ;
+ - TAP_385 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 370720 297920 ) N ;
+ - TAP_386 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 450240 297920 ) N ;
+ - TAP_387 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 529760 297920 ) N ;
+ - TAP_388 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 92960 305760 ) FS ;
+ - TAP_389 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 172480 305760 ) FS ;
+ - TAP_390 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 252000 305760 ) FS ;
+ - TAP_391 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 331520 305760 ) FS ;
+ - TAP_392 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 411040 305760 ) FS ;
+ - TAP_393 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 490560 305760 ) FS ;
+ - TAP_394 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 570080 305760 ) FS ;
+ - TAP_395 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 52640 313600 ) N ;
+ - TAP_396 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 132160 313600 ) N ;
+ - TAP_397 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 211680 313600 ) N ;
+ - TAP_398 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 291200 313600 ) N ;
+ - TAP_399 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 370720 313600 ) N ;
+ - TAP_400 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 450240 313600 ) N ;
+ - TAP_401 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 529760 313600 ) N ;
+ - TAP_402 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 92960 321440 ) FS ;
+ - TAP_403 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 172480 321440 ) FS ;
+ - TAP_404 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 252000 321440 ) FS ;
+ - TAP_405 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 331520 321440 ) FS ;
+ - TAP_406 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 411040 321440 ) FS ;
+ - TAP_407 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 490560 321440 ) FS ;
+ - TAP_408 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 570080 321440 ) FS ;
+ - TAP_409 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 52640 329280 ) N ;
+ - TAP_410 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 132160 329280 ) N ;
+ - TAP_411 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 211680 329280 ) N ;
+ - TAP_412 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 291200 329280 ) N ;
+ - TAP_413 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 370720 329280 ) N ;
+ - TAP_414 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 450240 329280 ) N ;
+ - TAP_415 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 529760 329280 ) N ;
+ - TAP_416 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 92960 337120 ) FS ;
+ - TAP_417 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 172480 337120 ) FS ;
+ - TAP_418 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 252000 337120 ) FS ;
+ - TAP_419 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 331520 337120 ) FS ;
+ - TAP_420 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 411040 337120 ) FS ;
+ - TAP_421 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 490560 337120 ) FS ;
+ - TAP_422 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 570080 337120 ) FS ;
+ - TAP_423 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 52640 344960 ) N ;
+ - TAP_424 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 132160 344960 ) N ;
+ - TAP_425 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 211680 344960 ) N ;
+ - TAP_426 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 291200 344960 ) N ;
+ - TAP_427 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 370720 344960 ) N ;
+ - TAP_428 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 450240 344960 ) N ;
+ - TAP_429 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 529760 344960 ) N ;
+ - TAP_430 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 92960 352800 ) FS ;
+ - TAP_431 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 172480 352800 ) FS ;
+ - TAP_432 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 252000 352800 ) FS ;
+ - TAP_433 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 331520 352800 ) FS ;
+ - TAP_434 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 411040 352800 ) FS ;
+ - TAP_435 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 490560 352800 ) FS ;
+ - TAP_436 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 570080 352800 ) FS ;
+ - TAP_437 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 52640 360640 ) N ;
+ - TAP_438 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 132160 360640 ) N ;
+ - TAP_439 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 211680 360640 ) N ;
+ - TAP_440 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 291200 360640 ) N ;
+ - TAP_441 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 370720 360640 ) N ;
+ - TAP_442 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 450240 360640 ) N ;
+ - TAP_443 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 529760 360640 ) N ;
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+ - TAP_456 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 450240 376320 ) N ;
+ - TAP_457 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 529760 376320 ) N ;
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+ - TAP_471 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 529760 392000 ) N ;
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+ - TAP_479 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 52640 407680 ) N ;
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+ - TAP_481 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 211680 407680 ) N ;
+ - TAP_482 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 291200 407680 ) N ;
+ - TAP_483 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 370720 407680 ) N ;
+ - TAP_484 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 450240 407680 ) N ;
+ - TAP_485 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 529760 407680 ) N ;
+ - TAP_486 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 92960 415520 ) FS ;
+ - TAP_487 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 172480 415520 ) FS ;
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+ - TAP_493 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 52640 423360 ) N ;
+ - TAP_494 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 132160 423360 ) N ;
+ - TAP_495 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 211680 423360 ) N ;
+ - TAP_496 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 291200 423360 ) N ;
+ - TAP_497 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 370720 423360 ) N ;
+ - TAP_498 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 450240 423360 ) N ;
+ - TAP_499 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 529760 423360 ) N ;
+ - TAP_500 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 92960 431200 ) FS ;
+ - TAP_501 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 172480 431200 ) FS ;
+ - TAP_502 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 252000 431200 ) FS ;
+ - TAP_503 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 331520 431200 ) FS ;
+ - TAP_504 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 411040 431200 ) FS ;
+ - TAP_505 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 490560 431200 ) FS ;
+ - TAP_506 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 570080 431200 ) FS ;
+ - TAP_507 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 52640 439040 ) N ;
+ - TAP_508 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 132160 439040 ) N ;
+ - TAP_509 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 211680 439040 ) N ;
+ - TAP_510 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 291200 439040 ) N ;
+ - TAP_511 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 370720 439040 ) N ;
+ - TAP_512 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 450240 439040 ) N ;
+ - TAP_513 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 529760 439040 ) N ;
+ - TAP_514 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 92960 446880 ) FS ;
+ - TAP_515 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 172480 446880 ) FS ;
+ - TAP_516 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 252000 446880 ) FS ;
+ - TAP_517 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 331520 446880 ) FS ;
+ - TAP_518 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 411040 446880 ) FS ;
+ - TAP_519 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 490560 446880 ) FS ;
+ - TAP_520 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 570080 446880 ) FS ;
+ - TAP_521 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 52640 454720 ) N ;
+ - TAP_522 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 132160 454720 ) N ;
+ - TAP_523 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 211680 454720 ) N ;
+ - TAP_524 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 291200 454720 ) N ;
+ - TAP_525 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 370720 454720 ) N ;
+ - TAP_526 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 450240 454720 ) N ;
+ - TAP_527 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 529760 454720 ) N ;
+ - TAP_528 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 92960 462560 ) FS ;
+ - TAP_529 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 172480 462560 ) FS ;
+ - TAP_530 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 252000 462560 ) FS ;
+ - TAP_531 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 331520 462560 ) FS ;
+ - TAP_532 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 411040 462560 ) FS ;
+ - TAP_533 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 490560 462560 ) FS ;
+ - TAP_534 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 570080 462560 ) FS ;
+ - TAP_535 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 52640 470400 ) N ;
+ - TAP_536 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 132160 470400 ) N ;
+ - TAP_537 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 211680 470400 ) N ;
+ - TAP_538 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 291200 470400 ) N ;
+ - TAP_539 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 370720 470400 ) N ;
+ - TAP_540 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 450240 470400 ) N ;
+ - TAP_541 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 529760 470400 ) N ;
+ - TAP_542 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 92960 478240 ) FS ;
+ - TAP_543 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 172480 478240 ) FS ;
+ - TAP_544 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 252000 478240 ) FS ;
+ - TAP_545 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 331520 478240 ) FS ;
+ - TAP_546 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 411040 478240 ) FS ;
+ - TAP_547 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 490560 478240 ) FS ;
+ - TAP_548 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 570080 478240 ) FS ;
+ - TAP_549 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 52640 486080 ) N ;
+ - TAP_550 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 132160 486080 ) N ;
+ - TAP_551 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 211680 486080 ) N ;
+ - TAP_552 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 291200 486080 ) N ;
+ - TAP_553 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 370720 486080 ) N ;
+ - TAP_554 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 450240 486080 ) N ;
+ - TAP_555 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 529760 486080 ) N ;
+ - TAP_556 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 92960 493920 ) FS ;
+ - TAP_557 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 172480 493920 ) FS ;
+ - TAP_558 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 252000 493920 ) FS ;
+ - TAP_559 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 331520 493920 ) FS ;
+ - TAP_560 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 411040 493920 ) FS ;
+ - TAP_561 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 490560 493920 ) FS ;
+ - TAP_562 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 570080 493920 ) FS ;
+ - TAP_563 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 52640 501760 ) N ;
+ - TAP_564 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 132160 501760 ) N ;
+ - TAP_565 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 211680 501760 ) N ;
+ - TAP_566 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 291200 501760 ) N ;
+ - TAP_567 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 370720 501760 ) N ;
+ - TAP_568 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 450240 501760 ) N ;
+ - TAP_569 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 529760 501760 ) N ;
+ - TAP_570 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 92960 509600 ) FS ;
+ - TAP_571 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 172480 509600 ) FS ;
+ - TAP_572 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 252000 509600 ) FS ;
+ - TAP_573 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 331520 509600 ) FS ;
+ - TAP_574 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 411040 509600 ) FS ;
+ - TAP_575 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 490560 509600 ) FS ;
+ - TAP_576 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 570080 509600 ) FS ;
+ - TAP_577 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 52640 517440 ) N ;
+ - TAP_578 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 132160 517440 ) N ;
+ - TAP_579 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 211680 517440 ) N ;
+ - TAP_580 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 291200 517440 ) N ;
+ - TAP_581 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 370720 517440 ) N ;
+ - TAP_582 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 450240 517440 ) N ;
+ - TAP_583 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 529760 517440 ) N ;
+ - TAP_584 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 92960 525280 ) FS ;
+ - TAP_585 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 172480 525280 ) FS ;
+ - TAP_586 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 252000 525280 ) FS ;
+ - TAP_587 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 331520 525280 ) FS ;
+ - TAP_588 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 411040 525280 ) FS ;
+ - TAP_589 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 490560 525280 ) FS ;
+ - TAP_590 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 570080 525280 ) FS ;
+ - TAP_591 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 52640 533120 ) N ;
+ - TAP_592 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 132160 533120 ) N ;
+ - TAP_593 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 211680 533120 ) N ;
+ - TAP_594 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 291200 533120 ) N ;
+ - TAP_595 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 370720 533120 ) N ;
+ - TAP_596 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 450240 533120 ) N ;
+ - TAP_597 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 529760 533120 ) N ;
+ - TAP_598 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 92960 540960 ) FS ;
+ - TAP_599 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 172480 540960 ) FS ;
+ - TAP_600 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 252000 540960 ) FS ;
+ - TAP_601 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 331520 540960 ) FS ;
+ - TAP_602 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 411040 540960 ) FS ;
+ - TAP_603 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 490560 540960 ) FS ;
+ - TAP_604 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 570080 540960 ) FS ;
+ - TAP_605 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 52640 548800 ) N ;
+ - TAP_606 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 132160 548800 ) N ;
+ - TAP_607 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 211680 548800 ) N ;
+ - TAP_608 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 291200 548800 ) N ;
+ - TAP_609 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 370720 548800 ) N ;
+ - TAP_610 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 450240 548800 ) N ;
+ - TAP_611 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 529760 548800 ) N ;
+ - TAP_612 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 52640 556640 ) FS ;
+ - TAP_613 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 91840 556640 ) FS ;
+ - TAP_614 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 131040 556640 ) FS ;
+ - TAP_615 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 170240 556640 ) FS ;
+ - TAP_616 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 209440 556640 ) FS ;
+ - TAP_617 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 248640 556640 ) FS ;
+ - TAP_618 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 287840 556640 ) FS ;
+ - TAP_619 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 327040 556640 ) FS ;
+ - TAP_620 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 366240 556640 ) FS ;
+ - TAP_621 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 405440 556640 ) FS ;
+ - TAP_622 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 444640 556640 ) FS ;
+ - TAP_623 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 483840 556640 ) FS ;
+ - TAP_624 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 523040 556640 ) FS ;
+ - TAP_625 gf180mcu_fd_sc_mcu7t5v0__filltie + SOURCE DIST + FIXED ( 562240 556640 ) FS ;
+ - _0672_ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 + PLACED ( 287840 305760 ) S ;
+ - _0673_ gf180mcu_fd_sc_mcu7t5v0__xor2_1 + PLACED ( 272160 305760 ) FS ;
+ - _0674_ gf180mcu_fd_sc_mcu7t5v0__clkbuf_2 + PLACED ( 277760 313600 ) N ;
+ - _0675_ gf180mcu_fd_sc_mcu7t5v0__xor2_1 + PLACED ( 196000 313600 ) N ;
+ - _0676_ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 + PLACED ( 244160 321440 ) S ;
+ - _0677_ gf180mcu_fd_sc_mcu7t5v0__buf_2 + PLACED ( 272160 297920 ) FN ;
+ - _0678_ gf180mcu_fd_sc_mcu7t5v0__xor2_1 + PLACED ( 229600 305760 ) S ;
+ - _0679_ gf180mcu_fd_sc_mcu7t5v0__nand2_1 + PLACED ( 203840 297920 ) FN ;
+ - _0680_ gf180mcu_fd_sc_mcu7t5v0__nor2_1 + PLACED ( 229600 313600 ) N ;
+ - _0681_ gf180mcu_fd_sc_mcu7t5v0__xor2_1 + PLACED ( 198240 305760 ) FS ;
+ - _0682_ gf180mcu_fd_sc_mcu7t5v0__nand2_1 + PLACED ( 200480 329280 ) FN ;
+ - _0683_ gf180mcu_fd_sc_mcu7t5v0__nand2_1 + PLACED ( 215040 313600 ) FN ;
+ - _0684_ gf180mcu_fd_sc_mcu7t5v0__nand2_1 + PLACED ( 192640 329280 ) N ;
+ - _0685_ gf180mcu_fd_sc_mcu7t5v0__nor2_2 + PLACED ( 294560 282240 ) N ;
+ - _0686_ gf180mcu_fd_sc_mcu7t5v0__xor2_1 + PLACED ( 276640 329280 ) N ;
+ - _0687_ gf180mcu_fd_sc_mcu7t5v0__buf_2 + PLACED ( 286720 321440 ) FS ;
+ - _0688_ gf180mcu_fd_sc_mcu7t5v0__xor3_2 + PLACED ( 192640 321440 ) FS ;
+ - _0689_ gf180mcu_fd_sc_mcu7t5v0__mux2_2 + PLACED ( 201600 290080 ) S ;
+ - _0690_ gf180mcu_fd_sc_mcu7t5v0__clkbuf_1 + PLACED ( 511840 290080 ) FS ;
+ - _0691_ gf180mcu_fd_sc_mcu7t5v0__mux2_2 + PLACED ( 193760 282240 ) FN ;
+ - _0692_ gf180mcu_fd_sc_mcu7t5v0__clkbuf_1 + PLACED ( 202720 94080 ) N ;
+ - _0693_ gf180mcu_fd_sc_mcu7t5v0__or3_2 + PLACED ( 394240 125440 ) FN ;
+ - _0694_ gf180mcu_fd_sc_mcu7t5v0__nand3_1 + PLACED ( 381920 172480 ) FN ;
+ - _0695_ gf180mcu_fd_sc_mcu7t5v0__xor2_1 + PLACED ( 383040 219520 ) N ;
+ - _0696_ gf180mcu_fd_sc_mcu7t5v0__clkbuf_1 + PLACED ( 398720 219520 ) N ;
+ - _0697_ gf180mcu_fd_sc_mcu7t5v0__xnor2_1 + PLACED ( 412160 219520 ) N ;
+ - _0698_ gf180mcu_fd_sc_mcu7t5v0__xor2_1 + PLACED ( 387520 156800 ) N ;
+ - _0699_ gf180mcu_fd_sc_mcu7t5v0__clkbuf_1 + PLACED ( 414400 164640 ) FS ;
+ - _0700_ gf180mcu_fd_sc_mcu7t5v0__nor2_1 + PLACED ( 425600 164640 ) FS ;
+ - _0701_ gf180mcu_fd_sc_mcu7t5v0__nor2_1 + PLACED ( 403200 133280 ) FS ;
+ - _0702_ gf180mcu_fd_sc_mcu7t5v0__xor3_2 + PLACED ( 399840 141120 ) N ;
+ - _0703_ gf180mcu_fd_sc_mcu7t5v0__xnor2_1 + PLACED ( 406560 109760 ) N ;
+ - _0704_ gf180mcu_fd_sc_mcu7t5v0__clkbuf_1 + PLACED ( 426720 109760 ) N ;
+ - _0705_ gf180mcu_fd_sc_mcu7t5v0__and2_1 + PLACED ( 453600 141120 ) N ;
+ - _0706_ gf180mcu_fd_sc_mcu7t5v0__oai21_1 + PLACED ( 414400 133280 ) FS ;
+ - _0707_ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 + PLACED ( 405440 148960 ) FS ;
+ - _0708_ gf180mcu_fd_sc_mcu7t5v0__aoi21_1 + PLACED ( 414400 148960 ) S ;
+ - _0709_ gf180mcu_fd_sc_mcu7t5v0__aoi221_2 + PLACED ( 426720 148960 ) S ;
+ - _0710_ gf180mcu_fd_sc_mcu7t5v0__oai31_1 + PLACED ( 387520 133280 ) S ;
+ - _0711_ gf180mcu_fd_sc_mcu7t5v0__xnor2_1 + PLACED ( 386400 164640 ) FS ;
+ - _0712_ gf180mcu_fd_sc_mcu7t5v0__clkbuf_1 + PLACED ( 404320 172480 ) N ;
+ - _0713_ gf180mcu_fd_sc_mcu7t5v0__nor2_1 + PLACED ( 418880 180320 ) FS ;
+ - _0714_ gf180mcu_fd_sc_mcu7t5v0__nand2_1 + PLACED ( 421120 188160 ) N ;
+ - _0715_ gf180mcu_fd_sc_mcu7t5v0__oai31_1 + PLACED ( 422240 172480 ) FN ;
+ - _0716_ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 + PLACED ( 414400 196000 ) FS ;
+ - _0717_ gf180mcu_fd_sc_mcu7t5v0__nand2_1 + PLACED ( 417760 211680 ) FS ;
+ - _0718_ gf180mcu_fd_sc_mcu7t5v0__oai21_1 + PLACED ( 428960 219520 ) N ;
+ - _0719_ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 + PLACED ( 398720 196000 ) S ;
+ - _0720_ gf180mcu_fd_sc_mcu7t5v0__nand2_1 + PLACED ( 374080 196000 ) FS ;
+ - _0721_ gf180mcu_fd_sc_mcu7t5v0__xnor2_1 + PLACED ( 381920 196000 ) FS ;
+ - _0722_ gf180mcu_fd_sc_mcu7t5v0__clkbuf_1 + PLACED ( 397600 211680 ) FS ;
+ - _0723_ gf180mcu_fd_sc_mcu7t5v0__xor3_2 + PLACED ( 426720 211680 ) FS ;
+ - _0724_ gf180mcu_fd_sc_mcu7t5v0__xnor2_1 + PLACED ( 479360 141120 ) N ;
+ - _0725_ gf180mcu_fd_sc_mcu7t5v0__nor2_1 + PLACED ( 432320 188160 ) FN ;
+ - _0726_ gf180mcu_fd_sc_mcu7t5v0__xor3_1 + PLACED ( 427840 180320 ) FS ;
+ - _0727_ gf180mcu_fd_sc_mcu7t5v0__buf_2 + PLACED ( 472640 180320 ) FS ;
+ - _0728_ gf180mcu_fd_sc_mcu7t5v0__xor2_2 + PLACED ( 454720 148960 ) FS ;
+ - _0729_ gf180mcu_fd_sc_mcu7t5v0__aoi21_1 + PLACED ( 437920 141120 ) FN ;
+ - _0730_ gf180mcu_fd_sc_mcu7t5v0__xor3_1 + PLACED ( 434560 164640 ) FS ;
+ - _0731_ gf180mcu_fd_sc_mcu7t5v0__buf_2 + PLACED ( 465920 156800 ) N ;
+ - _0732_ gf180mcu_fd_sc_mcu7t5v0__nand2_1 + PLACED ( 520800 141120 ) N ;
+ - _0733_ gf180mcu_fd_sc_mcu7t5v0__nand2_1 + PLACED ( 540960 156800 ) N ;
+ - _0734_ gf180mcu_fd_sc_mcu7t5v0__xor2_2 + PLACED ( 424480 203840 ) N ;
+ - _0735_ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 + PLACED ( 549920 180320 ) S ;
+ - _0736_ gf180mcu_fd_sc_mcu7t5v0__oai21_1 + PLACED ( 532000 196000 ) FS ;
+ - _0737_ gf180mcu_fd_sc_mcu7t5v0__nor2_1 + PLACED ( 545440 188160 ) FN ;
+ - _0738_ gf180mcu_fd_sc_mcu7t5v0__nand4_1 + PLACED ( 518560 188160 ) N ;
+ - _0739_ gf180mcu_fd_sc_mcu7t5v0__xor2_1 + PLACED ( 477120 156800 ) N ;
+ - _0740_ gf180mcu_fd_sc_mcu7t5v0__nor2_1 + PLACED ( 482720 172480 ) N ;
+ - _0741_ gf180mcu_fd_sc_mcu7t5v0__or2_1 + PLACED ( 480480 188160 ) N ;
+ - _0742_ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 + PLACED ( 493920 133280 ) FS ;
+ - _0743_ gf180mcu_fd_sc_mcu7t5v0__nor2_1 + PLACED ( 496160 141120 ) N ;
+ - _0744_ gf180mcu_fd_sc_mcu7t5v0__oai21_1 + PLACED ( 492800 156800 ) FN ;
+ - _0745_ gf180mcu_fd_sc_mcu7t5v0__oai211_1 + PLACED ( 493920 164640 ) S ;
+ - _0746_ gf180mcu_fd_sc_mcu7t5v0__oai221_1 + PLACED ( 491680 188160 ) FN ;
+ - _0747_ gf180mcu_fd_sc_mcu7t5v0__oai211_1 + PLACED ( 518560 196000 ) S ;
+ - _0748_ gf180mcu_fd_sc_mcu7t5v0__nor2_1 + PLACED ( 504000 148960 ) S ;
+ - _0749_ gf180mcu_fd_sc_mcu7t5v0__and2_1 + PLACED ( 514080 148960 ) S ;
+ - _0750_ gf180mcu_fd_sc_mcu7t5v0__nor3_1 + PLACED ( 525280 148960 ) S ;
+ - _0751_ gf180mcu_fd_sc_mcu7t5v0__oai32_1 + PLACED ( 515200 156800 ) N ;
+ - _0752_ gf180mcu_fd_sc_mcu7t5v0__nand2_1 + PLACED ( 493920 148960 ) S ;
+ - _0753_ gf180mcu_fd_sc_mcu7t5v0__aoi21_1 + PLACED ( 504000 156800 ) N ;
+ - _0754_ gf180mcu_fd_sc_mcu7t5v0__aoi22_1 + PLACED ( 516320 180320 ) FS ;
+ - _0755_ gf180mcu_fd_sc_mcu7t5v0__nand2_1 + PLACED ( 542080 180320 ) FS ;
+ - _0756_ gf180mcu_fd_sc_mcu7t5v0__nand2_1 + PLACED ( 533120 156800 ) N ;
+ - _0757_ gf180mcu_fd_sc_mcu7t5v0__nand2_1 + PLACED ( 529760 164640 ) S ;
+ - _0758_ gf180mcu_fd_sc_mcu7t5v0__nor2_1 + PLACED ( 520800 164640 ) FS ;
+ - _0759_ gf180mcu_fd_sc_mcu7t5v0__aoi211_1 + PLACED ( 533120 172480 ) N ;
+ - _0760_ gf180mcu_fd_sc_mcu7t5v0__aoi211_1 + PLACED ( 528640 180320 ) FS ;
+ - _0761_ gf180mcu_fd_sc_mcu7t5v0__aoi22_1 + PLACED ( 533120 188160 ) N ;
+ - _0762_ gf180mcu_fd_sc_mcu7t5v0__and2_1 + PLACED ( 461440 180320 ) FS ;
+ - _0763_ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 + PLACED ( 491680 172480 ) FN ;
+ - _0764_ gf180mcu_fd_sc_mcu7t5v0__nor2_1 + PLACED ( 479360 164640 ) S ;
+ - _0765_ gf180mcu_fd_sc_mcu7t5v0__aoi211_1 + PLACED ( 469280 172480 ) N ;
+ - _0766_ gf180mcu_fd_sc_mcu7t5v0__or3_1 + PLACED ( 465920 188160 ) N ;
+ - _0767_ gf180mcu_fd_sc_mcu7t5v0__oai211_1 + PLACED ( 493920 180320 ) FS ;
+ - _0768_ gf180mcu_fd_sc_mcu7t5v0__oai211_1 + PLACED ( 493920 196000 ) FS ;
+ - _0769_ gf180mcu_fd_sc_mcu7t5v0__and2_1 + PLACED ( 480480 196000 ) FS ;
+ - _0770_ gf180mcu_fd_sc_mcu7t5v0__oai211_1 + PLACED ( 495040 203840 ) N ;
+ - _0771_ gf180mcu_fd_sc_mcu7t5v0__oai21_1 + PLACED ( 493920 211680 ) FS ;
+ - _0772_ gf180mcu_fd_sc_mcu7t5v0__oai31_1 + PLACED ( 294560 290080 ) FS ;
+ - _0773_ gf180mcu_fd_sc_mcu7t5v0__nor2_1 + PLACED ( 308000 282240 ) N ;
+ - _0774_ gf180mcu_fd_sc_mcu7t5v0__nand2_1 + PLACED ( 320320 290080 ) FS ;
+ - _0775_ gf180mcu_fd_sc_mcu7t5v0__nand2_1 + PLACED ( 316960 282240 ) FN ;
+ - _0776_ gf180mcu_fd_sc_mcu7t5v0__buf_1 + PLACED ( 311360 290080 ) S ;
+ - _0777_ gf180mcu_fd_sc_mcu7t5v0__nor2_4 + PLACED ( 294560 329280 ) FN ;
+ - _0778_ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 + PLACED ( 295680 305760 ) S ;
+ - _0779_ gf180mcu_fd_sc_mcu7t5v0__nand2_1 + PLACED ( 294560 313600 ) FN ;
+ - _0780_ gf180mcu_fd_sc_mcu7t5v0__nand2_1 + PLACED ( 280000 352800 ) FS ;
+ - _0781_ gf180mcu_fd_sc_mcu7t5v0__nand2_1 + PLACED ( 254240 360640 ) FN ;
+ - _0782_ gf180mcu_fd_sc_mcu7t5v0__nand2_1 + PLACED ( 264320 368480 ) S ;
+ - _0783_ gf180mcu_fd_sc_mcu7t5v0__oai22_1 + PLACED ( 246400 376320 ) N ;
+ - _0784_ gf180mcu_fd_sc_mcu7t5v0__nor2_1 + PLACED ( 255360 368480 ) FS ;
+ - _0785_ gf180mcu_fd_sc_mcu7t5v0__aoi211_2 + PLACED ( 283360 368480 ) FS ;
+ - _0786_ gf180mcu_fd_sc_mcu7t5v0__nand3_1 + PLACED ( 323680 360640 ) N ;
+ - _0787_ gf180mcu_fd_sc_mcu7t5v0__buf_2 + PLACED ( 420000 384160 ) S ;
+ - _0788_ gf180mcu_fd_sc_mcu7t5v0__nor3_4 + PLACED ( 290080 337120 ) FS ;
+ - _0789_ gf180mcu_fd_sc_mcu7t5v0__nand2_1 + PLACED ( 343840 352800 ) FS ;
+ - _0790_ gf180mcu_fd_sc_mcu7t5v0__oai211_1 + PLACED ( 334880 337120 ) FS ;
+ - _0791_ gf180mcu_fd_sc_mcu7t5v0__nand3_2 + PLACED ( 309120 305760 ) S ;
+ - _0792_ gf180mcu_fd_sc_mcu7t5v0__mux2_2 + PLACED ( 334880 305760 ) FS ;
+ - _0793_ gf180mcu_fd_sc_mcu7t5v0__clkbuf_1 + PLACED ( 334880 290080 ) FS ;
+ - _0794_ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 + PLACED ( 384160 313600 ) FN ;
+ - _0795_ gf180mcu_fd_sc_mcu7t5v0__and2_1 + PLACED ( 275520 360640 ) N ;
+ - _0796_ gf180mcu_fd_sc_mcu7t5v0__nor2_1 + PLACED ( 282240 384160 ) FS ;
+ - _0797_ gf180mcu_fd_sc_mcu7t5v0__aoi221_1 + PLACED ( 238560 384160 ) FS ;
+ - _0798_ gf180mcu_fd_sc_mcu7t5v0__nor2_2 + PLACED ( 299040 352800 ) FS ;
+ - _0799_ gf180mcu_fd_sc_mcu7t5v0__oai21_1 + PLACED ( 294560 376320 ) N ;
+ - _0800_ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 + PLACED ( 325920 399840 ) FS ;
+ - _0801_ gf180mcu_fd_sc_mcu7t5v0__nand3_1 + PLACED ( 321440 376320 ) N ;
+ - _0802_ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 + PLACED ( 360640 368480 ) S ;
+ - _0803_ gf180mcu_fd_sc_mcu7t5v0__oai21_1 + PLACED ( 321440 368480 ) FS ;
+ - _0804_ gf180mcu_fd_sc_mcu7t5v0__nand3_1 + PLACED ( 334880 368480 ) FS ;
+ - _0805_ gf180mcu_fd_sc_mcu7t5v0__oai21_1 + PLACED ( 347200 313600 ) N ;
+ - _0806_ gf180mcu_fd_sc_mcu7t5v0__clkbuf_1 + PLACED ( 362880 305760 ) FS ;
+ - _0807_ gf180mcu_fd_sc_mcu7t5v0__oai22_1 + PLACED ( 255360 384160 ) FS ;
+ - _0808_ gf180mcu_fd_sc_mcu7t5v0__nand2_1 + PLACED ( 277760 392000 ) FN ;
+ - _0809_ gf180mcu_fd_sc_mcu7t5v0__oai21_1 + PLACED ( 268800 384160 ) FS ;
+ - _0810_ gf180mcu_fd_sc_mcu7t5v0__nand3_1 + PLACED ( 312480 352800 ) FS ;
+ - _0811_ gf180mcu_fd_sc_mcu7t5v0__nand3_1 + PLACED ( 309120 368480 ) FS ;
+ - _0812_ gf180mcu_fd_sc_mcu7t5v0__nand2_1 + PLACED ( 308000 376320 ) N ;
+ - _0813_ gf180mcu_fd_sc_mcu7t5v0__aoi21_2 + PLACED ( 300160 360640 ) FN ;
+ - _0814_ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 + PLACED ( 200480 376320 ) N ;
+ - _0815_ gf180mcu_fd_sc_mcu7t5v0__nor2_1 + PLACED ( 259840 392000 ) FN ;
+ - _0816_ gf180mcu_fd_sc_mcu7t5v0__oai22_2 + PLACED ( 267680 376320 ) N ;
+ - _0817_ gf180mcu_fd_sc_mcu7t5v0__inv_1 + PLACED ( 374080 329280 ) FN ;
+ - _0818_ gf180mcu_fd_sc_mcu7t5v0__aoi222_4 + PLACED ( 294560 344960 ) FN ;
+ - _0819_ gf180mcu_fd_sc_mcu7t5v0__nor2_1 + PLACED ( 381920 290080 ) S ;
+ - _0820_ gf180mcu_fd_sc_mcu7t5v0__xor2_1 + PLACED ( 375200 282240 ) N ;
+ - _0821_ gf180mcu_fd_sc_mcu7t5v0__clkbuf_1 + PLACED ( 384160 203840 ) N ;
+ - _0822_ gf180mcu_fd_sc_mcu7t5v0__nor2_1 + PLACED ( 334880 352800 ) FS ;
+ - _0823_ gf180mcu_fd_sc_mcu7t5v0__nand2_1 + PLACED ( 324800 352800 ) FS ;
+ - _0824_ gf180mcu_fd_sc_mcu7t5v0__nor2_1 + PLACED ( 323680 337120 ) S ;
+ - _0825_ gf180mcu_fd_sc_mcu7t5v0__nand2_1 + PLACED ( 344960 290080 ) FS ;
+ - _0826_ gf180mcu_fd_sc_mcu7t5v0__oai21_1 + PLACED ( 352800 297920 ) FN ;
+ - _0827_ gf180mcu_fd_sc_mcu7t5v0__xor2_1 + PLACED ( 356160 250880 ) N ;
+ - _0828_ gf180mcu_fd_sc_mcu7t5v0__clkbuf_1 + PLACED ( 378560 243040 ) FS ;
+ - _0829_ gf180mcu_fd_sc_mcu7t5v0__aoi211_1 + PLACED ( 357280 290080 ) S ;
+ - _0830_ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 + PLACED ( 358400 313600 ) FN ;
+ - _0831_ gf180mcu_fd_sc_mcu7t5v0__nor2_1 + PLACED ( 353920 305760 ) S ;
+ - _0832_ gf180mcu_fd_sc_mcu7t5v0__or2_1 + PLACED ( 370720 290080 ) FS ;
+ - _0833_ gf180mcu_fd_sc_mcu7t5v0__clkbuf_1 + PLACED ( 380800 274400 ) FS ;
+ - _0834_ gf180mcu_fd_sc_mcu7t5v0__nand2_1 + PLACED ( 204960 203840 ) N ;
+ - _0835_ gf180mcu_fd_sc_mcu7t5v0__nor2_1 + PLACED ( 217280 203840 ) N ;
+ - _0836_ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 + PLACED ( 296800 117600 ) S ;
+ - _0837_ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 + PLACED ( 297920 109760 ) FN ;
+ - _0838_ gf180mcu_fd_sc_mcu7t5v0__nand2_1 + PLACED ( 314720 117600 ) FS ;
+ - _0839_ gf180mcu_fd_sc_mcu7t5v0__and2_1 + PLACED ( 312480 133280 ) S ;
+ - _0840_ gf180mcu_fd_sc_mcu7t5v0__or2_1 + PLACED ( 316960 141120 ) N ;
+ - _0841_ gf180mcu_fd_sc_mcu7t5v0__or2_1 + PLACED ( 316960 156800 ) N ;
+ - _0842_ gf180mcu_fd_sc_mcu7t5v0__or2_1 + PLACED ( 315840 180320 ) FS ;
+ - _0843_ gf180mcu_fd_sc_mcu7t5v0__oai21_1 + PLACED ( 319200 196000 ) FS ;
+ - _0844_ gf180mcu_fd_sc_mcu7t5v0__aoi21_2 + PLACED ( 230720 196000 ) S ;
+ - _0845_ gf180mcu_fd_sc_mcu7t5v0__and2_1 + PLACED ( 24640 290080 ) S ;
+ - _0846_ gf180mcu_fd_sc_mcu7t5v0__clkbuf_1 + PLACED ( 22400 305760 ) FS ;
+ - _0847_ gf180mcu_fd_sc_mcu7t5v0__and2_1 + PLACED ( 25760 47040 ) FN ;
+ - _0848_ gf180mcu_fd_sc_mcu7t5v0__clkbuf_1 + PLACED ( 22400 39200 ) FS ;
+ - _0849_ gf180mcu_fd_sc_mcu7t5v0__and2_1 + PLACED ( 556640 305760 ) FS ;
+ - _0850_ gf180mcu_fd_sc_mcu7t5v0__clkbuf_1 + PLACED ( 570080 423360 ) FN ;
+ - _0851_ gf180mcu_fd_sc_mcu7t5v0__and2_1 + PLACED ( 499520 47040 ) N ;
+ - _0852_ gf180mcu_fd_sc_mcu7t5v0__clkbuf_1 + PLACED ( 508480 39200 ) FS ;
+ - _0853_ gf180mcu_fd_sc_mcu7t5v0__and2_1 + PLACED ( 556640 297920 ) N ;
+ - _0854_ gf180mcu_fd_sc_mcu7t5v0__clkbuf_1 + PLACED ( 570080 313600 ) N ;
+ - _0855_ gf180mcu_fd_sc_mcu7t5v0__and2_1 + PLACED ( 294560 47040 ) N ;
+ - _0856_ gf180mcu_fd_sc_mcu7t5v0__clkbuf_1 + PLACED ( 300160 39200 ) FS ;
+ - _0857_ gf180mcu_fd_sc_mcu7t5v0__and2_1 + PLACED ( 215040 250880 ) FN ;
+ - _0858_ gf180mcu_fd_sc_mcu7t5v0__nor2_1 + PLACED ( 203840 219520 ) N ;
+ - _0859_ gf180mcu_fd_sc_mcu7t5v0__oai211_1 + PLACED ( 212800 243040 ) FS ;
+ - _0860_ gf180mcu_fd_sc_mcu7t5v0__or3_1 + PLACED ( 293440 148960 ) FS ;
+ - _0861_ gf180mcu_fd_sc_mcu7t5v0__nor3_1 + PLACED ( 301280 133280 ) FS ;
+ - _0862_ gf180mcu_fd_sc_mcu7t5v0__oai21_1 + PLACED ( 304640 101920 ) FS ;
+ - _0863_ gf180mcu_fd_sc_mcu7t5v0__aoi221_1 + PLACED ( 304640 109760 ) N ;
+ - _0864_ gf180mcu_fd_sc_mcu7t5v0__nand2_1 + PLACED ( 319200 109760 ) N ;
+ - _0865_ gf180mcu_fd_sc_mcu7t5v0__nand2_1 + PLACED ( 414400 125440 ) N ;
+ - _0866_ gf180mcu_fd_sc_mcu7t5v0__nor2_1 + PLACED ( 220640 290080 ) FS ;
+ - _0867_ gf180mcu_fd_sc_mcu7t5v0__nor2_1 + PLACED ( 212800 274400 ) FS ;
+ - _0868_ gf180mcu_fd_sc_mcu7t5v0__nand2_1 + PLACED ( 364000 297920 ) FN ;
+ - _0869_ gf180mcu_fd_sc_mcu7t5v0__oai21_1 + PLACED ( 356160 282240 ) FN ;
+ - _0870_ gf180mcu_fd_sc_mcu7t5v0__and2_1 + PLACED ( 196000 274400 ) S ;
+ - _0871_ gf180mcu_fd_sc_mcu7t5v0__clkbuf_1 + PLACED ( 135520 219520 ) FN ;
+ - _0872_ gf180mcu_fd_sc_mcu7t5v0__and2_1 + PLACED ( 190400 290080 ) S ;
+ - _0873_ gf180mcu_fd_sc_mcu7t5v0__clkbuf_1 + PLACED ( 164640 290080 ) FS ;
+ - _0874_ gf180mcu_fd_sc_mcu7t5v0__or2_1 + PLACED ( 437920 250880 ) N ;
+ - _0875_ gf180mcu_fd_sc_mcu7t5v0__clkbuf_1 + PLACED ( 472640 266560 ) N ;
+ - _0876_ gf180mcu_fd_sc_mcu7t5v0__or2_1 + PLACED ( 453600 266560 ) N ;
+ - _0877_ gf180mcu_fd_sc_mcu7t5v0__clkbuf_1 + PLACED ( 481600 266560 ) N ;
+ - _0878_ gf180mcu_fd_sc_mcu7t5v0__buf_2 + PLACED ( 570080 282240 ) FN ;
+ - _0879_ gf180mcu_fd_sc_mcu7t5v0__clkinv_2 + PLACED ( 294560 407680 ) N ;
+ - _0880_ gf180mcu_fd_sc_mcu7t5v0__and3_1 + PLACED ( 266560 243040 ) S ;
+ - _0881_ gf180mcu_fd_sc_mcu7t5v0__and2_1 + PLACED ( 201600 243040 ) S ;
+ - _0882_ gf180mcu_fd_sc_mcu7t5v0__nand2_1 + PLACED ( 204960 227360 ) FS ;
+ - _0883_ gf180mcu_fd_sc_mcu7t5v0__nand2_1 + PLACED ( 212800 227360 ) FS ;
+ - _0884_ gf180mcu_fd_sc_mcu7t5v0__nand3_4 + PLACED ( 216160 180320 ) FS ;
+ - _0885_ gf180mcu_fd_sc_mcu7t5v0__nand2_1 + PLACED ( 218400 172480 ) FN ;
+ - _0886_ gf180mcu_fd_sc_mcu7t5v0__buf_2 + PLACED ( 218400 164640 ) FS ;
+ - _0887_ gf180mcu_fd_sc_mcu7t5v0__nor2_1 + PLACED ( 255360 227360 ) FS ;
+ - _0888_ gf180mcu_fd_sc_mcu7t5v0__and3_1 + PLACED ( 216160 196000 ) FS ;
+ - _0889_ gf180mcu_fd_sc_mcu7t5v0__nor2_1 + PLACED ( 274400 203840 ) N ;
+ - _0890_ gf180mcu_fd_sc_mcu7t5v0__oai21_1 + PLACED ( 267680 211680 ) S ;
+ - _0891_ gf180mcu_fd_sc_mcu7t5v0__aoi21_1 + PLACED ( 265440 227360 ) FS ;
+ - _0892_ gf180mcu_fd_sc_mcu7t5v0__aoi21_1 + PLACED ( 265440 258720 ) FS ;
+ - _0893_ gf180mcu_fd_sc_mcu7t5v0__nor3_1 + PLACED ( 255360 243040 ) S ;
+ - _0894_ gf180mcu_fd_sc_mcu7t5v0__and2_1 + PLACED ( 198240 250880 ) FN ;
+ - _0895_ gf180mcu_fd_sc_mcu7t5v0__nor2_1 + PLACED ( 192640 243040 ) S ;
+ - _0896_ gf180mcu_fd_sc_mcu7t5v0__nor3_1 + PLACED ( 187040 250880 ) FN ;
+ - _0897_ gf180mcu_fd_sc_mcu7t5v0__nor2_1 + PLACED ( 187040 235200 ) FN ;
+ - _0898_ gf180mcu_fd_sc_mcu7t5v0__nor3_1 + PLACED ( 181440 243040 ) S ;
+ - _0899_ gf180mcu_fd_sc_mcu7t5v0__and2_1 + PLACED ( 181440 227360 ) S ;
+ - _0900_ gf180mcu_fd_sc_mcu7t5v0__nor2_1 + PLACED ( 196000 235200 ) FN ;
+ - _0901_ gf180mcu_fd_sc_mcu7t5v0__nor3_1 + PLACED ( 178080 219520 ) FN ;
+ - _0902_ gf180mcu_fd_sc_mcu7t5v0__oai21_1 + PLACED ( 189280 219520 ) N ;
+ - _0903_ gf180mcu_fd_sc_mcu7t5v0__aoi21_1 + PLACED ( 166880 219520 ) N ;
+ - _0904_ gf180mcu_fd_sc_mcu7t5v0__nor2_1 + PLACED ( 203840 211680 ) S ;
+ - _0905_ gf180mcu_fd_sc_mcu7t5v0__aoi21_1 + PLACED ( 183680 211680 ) FS ;
+ - _0906_ gf180mcu_fd_sc_mcu7t5v0__nor3_1 + PLACED ( 183680 203840 ) FN ;
+ - _0907_ gf180mcu_fd_sc_mcu7t5v0__oai21_1 + PLACED ( 193760 196000 ) S ;
+ - _0908_ gf180mcu_fd_sc_mcu7t5v0__aoi21_1 + PLACED ( 193760 188160 ) N ;
+ - _0909_ gf180mcu_fd_sc_mcu7t5v0__aoi21_1 + PLACED ( 198240 180320 ) FS ;
+ - _0910_ gf180mcu_fd_sc_mcu7t5v0__nor2_1 + PLACED ( 199360 172480 ) N ;
+ - _0911_ gf180mcu_fd_sc_mcu7t5v0__nor2_1 + PLACED ( 110880 219520 ) FN ;
+ - _0912_ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 + PLACED ( 110880 305760 ) FS ;
+ - _0913_ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 + PLACED ( 85120 337120 ) FS ;
+ - _0914_ gf180mcu_fd_sc_mcu7t5v0__or4_1 + PLACED ( 96320 337120 ) S ;
+ - _0915_ gf180mcu_fd_sc_mcu7t5v0__nor3_1 + PLACED ( 113120 313600 ) FN ;
+ - _0916_ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 + PLACED ( 75040 297920 ) FN ;
+ - _0917_ gf180mcu_fd_sc_mcu7t5v0__nand4_1 + PLACED ( 59360 321440 ) FS ;
+ - _0918_ gf180mcu_fd_sc_mcu7t5v0__nor3_1 + PLACED ( 99680 305760 ) FS ;
+ - _0919_ gf180mcu_fd_sc_mcu7t5v0__nor2_1 + PLACED ( 135520 188160 ) N ;
+ - _0920_ gf180mcu_fd_sc_mcu7t5v0__nor2_1 + PLACED ( 107520 188160 ) FN ;
+ - _0921_ gf180mcu_fd_sc_mcu7t5v0__and2_1 + PLACED ( 69440 188160 ) N ;
+ - _0922_ gf180mcu_fd_sc_mcu7t5v0__nand3_1 + PLACED ( 101920 196000 ) FS ;
+ - _0923_ gf180mcu_fd_sc_mcu7t5v0__inv_1 + PLACED ( 78400 243040 ) FS ;
+ - _0924_ gf180mcu_fd_sc_mcu7t5v0__inv_1 + PLACED ( 107520 258720 ) S ;
+ - _0925_ gf180mcu_fd_sc_mcu7t5v0__nand4_1 + PLACED ( 95200 235200 ) FN ;
+ - _0926_ gf180mcu_fd_sc_mcu7t5v0__nand2_1 + PLACED ( 88480 203840 ) N ;
+ - _0927_ gf180mcu_fd_sc_mcu7t5v0__nor3_1 + PLACED ( 99680 219520 ) N ;
+ - _0928_ gf180mcu_fd_sc_mcu7t5v0__nand4_1 + PLACED ( 100800 313600 ) N ;
+ - _0929_ gf180mcu_fd_sc_mcu7t5v0__nand2_1 + PLACED ( 159040 321440 ) S ;
+ - _0930_ gf180mcu_fd_sc_mcu7t5v0__buf_2 + PLACED ( 96320 290080 ) S ;
+ - _0931_ gf180mcu_fd_sc_mcu7t5v0__nor2_1 + PLACED ( 103040 148960 ) FS ;
+ - _0932_ gf180mcu_fd_sc_mcu7t5v0__and2_1 + PLACED ( 112000 196000 ) FS ;
+ - _0933_ gf180mcu_fd_sc_mcu7t5v0__nor3_1 + PLACED ( 116480 203840 ) FN ;
+ - _0934_ gf180mcu_fd_sc_mcu7t5v0__and2_1 + PLACED ( 122080 172480 ) N ;
+ - _0935_ gf180mcu_fd_sc_mcu7t5v0__nor2_1 + PLACED ( 144480 188160 ) N ;
+ - _0936_ gf180mcu_fd_sc_mcu7t5v0__nor3_1 + PLACED ( 122080 180320 ) S ;
+ - _0937_ gf180mcu_fd_sc_mcu7t5v0__and4_1 + PLACED ( 116480 188160 ) FN ;
+ - _0938_ gf180mcu_fd_sc_mcu7t5v0__nor2_1 + PLACED ( 135520 172480 ) N ;
+ - _0939_ gf180mcu_fd_sc_mcu7t5v0__nor3_1 + PLACED ( 114240 164640 ) S ;
+ - _0940_ gf180mcu_fd_sc_mcu7t5v0__and2_1 + PLACED ( 88480 172480 ) FN ;
+ - _0941_ gf180mcu_fd_sc_mcu7t5v0__nor2_1 + PLACED ( 99680 172480 ) FN ;
+ - _0942_ gf180mcu_fd_sc_mcu7t5v0__nor3_1 + PLACED ( 82880 164640 ) S ;
+ - _0943_ gf180mcu_fd_sc_mcu7t5v0__and2_1 + PLACED ( 62720 164640 ) S ;
+ - _0944_ gf180mcu_fd_sc_mcu7t5v0__nor2_1 + PLACED ( 73920 164640 ) S ;
+ - _0945_ gf180mcu_fd_sc_mcu7t5v0__nor3_1 + PLACED ( 57120 156800 ) FN ;
+ - _0946_ gf180mcu_fd_sc_mcu7t5v0__xnor2_1 + PLACED ( 51520 180320 ) FS ;
+ - _0947_ gf180mcu_fd_sc_mcu7t5v0__nor2_1 + PLACED ( 56000 172480 ) FN ;
+ - _0948_ gf180mcu_fd_sc_mcu7t5v0__aoi21_1 + PLACED ( 58240 188160 ) N ;
+ - _0949_ gf180mcu_fd_sc_mcu7t5v0__and4_1 + PLACED ( 79520 196000 ) S ;
+ - _0950_ gf180mcu_fd_sc_mcu7t5v0__nor3_1 + PLACED ( 66080 196000 ) S ;
+ - _0951_ gf180mcu_fd_sc_mcu7t5v0__buf_2 + PLACED ( 88480 329280 ) N ;
+ - _0952_ gf180mcu_fd_sc_mcu7t5v0__nor2_1 + PLACED ( 78400 211680 ) S ;
+ - _0953_ gf180mcu_fd_sc_mcu7t5v0__and2_1 + PLACED ( 67200 227360 ) S ;
+ - _0954_ gf180mcu_fd_sc_mcu7t5v0__nor3_1 + PLACED ( 67200 211680 ) FS ;
+ - _0955_ gf180mcu_fd_sc_mcu7t5v0__nor2_1 + PLACED ( 56000 219520 ) FN ;
+ - _0956_ gf180mcu_fd_sc_mcu7t5v0__and2_1 + PLACED ( 45920 211680 ) S ;
+ - _0957_ gf180mcu_fd_sc_mcu7t5v0__nor3_1 + PLACED ( 43680 227360 ) S ;
+ - _0958_ gf180mcu_fd_sc_mcu7t5v0__nor2_1 + PLACED ( 44800 235200 ) N ;
+ - _0959_ gf180mcu_fd_sc_mcu7t5v0__and2_1 + PLACED ( 56000 235200 ) N ;
+ - _0960_ gf180mcu_fd_sc_mcu7t5v0__nor3_1 + PLACED ( 51520 243040 ) S ;
+ - _0961_ gf180mcu_fd_sc_mcu7t5v0__nor2_1 + PLACED ( 63840 258720 ) FS ;
+ - _0962_ gf180mcu_fd_sc_mcu7t5v0__nand4_4 + PLACED ( 96320 227360 ) FS ;
+ - _0963_ gf180mcu_fd_sc_mcu7t5v0__nor2_1 + PLACED ( 85120 243040 ) S ;
+ - _0964_ gf180mcu_fd_sc_mcu7t5v0__nor3_1 + PLACED ( 63840 243040 ) S ;
+ - _0965_ gf180mcu_fd_sc_mcu7t5v0__xor2_1 + PLACED ( 90720 250880 ) N ;
+ - _0966_ gf180mcu_fd_sc_mcu7t5v0__nor2_1 + PLACED ( 96320 258720 ) S ;
+ - _0967_ gf180mcu_fd_sc_mcu7t5v0__aoi21_1 + PLACED ( 110880 250880 ) N ;
+ - _0968_ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 + PLACED ( 107520 235200 ) N ;
+ - _0969_ gf180mcu_fd_sc_mcu7t5v0__nor4_4 + PLACED ( 99680 243040 ) S ;
+ - _0970_ gf180mcu_fd_sc_mcu7t5v0__nor3_1 + PLACED ( 118720 235200 ) N ;
+ - _0971_ gf180mcu_fd_sc_mcu7t5v0__nor2_1 + PLACED ( 138880 274400 ) FS ;
+ - _0972_ gf180mcu_fd_sc_mcu7t5v0__and2_1 + PLACED ( 116480 274400 ) FS ;
+ - _0973_ gf180mcu_fd_sc_mcu7t5v0__nor3_1 + PLACED ( 127680 274400 ) S ;
+ - _0974_ gf180mcu_fd_sc_mcu7t5v0__nor2_1 + PLACED ( 133280 290080 ) FS ;
+ - _0975_ gf180mcu_fd_sc_mcu7t5v0__aoi211_1 + PLACED ( 135520 297920 ) N ;
+ - _0976_ gf180mcu_fd_sc_mcu7t5v0__aoi21_1 + PLACED ( 113120 290080 ) S ;
+ - _0977_ gf180mcu_fd_sc_mcu7t5v0__and4_1 + PLACED ( 110880 297920 ) N ;
+ - _0978_ gf180mcu_fd_sc_mcu7t5v0__nor3_1 + PLACED ( 99680 297920 ) FN ;
+ - _0979_ gf180mcu_fd_sc_mcu7t5v0__nor2_1 + PLACED ( 124320 313600 ) N ;
+ - _0980_ gf180mcu_fd_sc_mcu7t5v0__and2_1 + PLACED ( 104160 321440 ) FS ;
+ - _0981_ gf180mcu_fd_sc_mcu7t5v0__nor3_1 + PLACED ( 122080 329280 ) N ;
+ - _0982_ gf180mcu_fd_sc_mcu7t5v0__aoi21_1 + PLACED ( 146720 344960 ) N ;
+ - _0983_ gf180mcu_fd_sc_mcu7t5v0__oai21_1 + PLACED ( 135520 344960 ) N ;
+ - _0984_ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 + PLACED ( 135520 360640 ) N ;
+ - _0985_ gf180mcu_fd_sc_mcu7t5v0__aoi21_1 + PLACED ( 105280 344960 ) FN ;
+ - _0986_ gf180mcu_fd_sc_mcu7t5v0__and4_1 + PLACED ( 99680 329280 ) FN ;
+ - _0987_ gf180mcu_fd_sc_mcu7t5v0__nor3_1 + PLACED ( 94080 344960 ) N ;
+ - _0988_ gf180mcu_fd_sc_mcu7t5v0__and2_1 + PLACED ( 67200 352800 ) S ;
+ - _0989_ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 + PLACED ( 80640 329280 ) FN ;
+ - _0990_ gf180mcu_fd_sc_mcu7t5v0__oai21_1 + PLACED ( 69440 360640 ) FN ;
+ - _0991_ gf180mcu_fd_sc_mcu7t5v0__nor2_1 + PLACED ( 80640 360640 ) N ;
+ - _0992_ gf180mcu_fd_sc_mcu7t5v0__oai21_1 + PLACED ( 58240 360640 ) N ;
+ - _0993_ gf180mcu_fd_sc_mcu7t5v0__aoi21_1 + PLACED ( 42560 360640 ) N ;
+ - _0994_ gf180mcu_fd_sc_mcu7t5v0__aoi21_1 + PLACED ( 54880 352800 ) S ;
+ - _0995_ gf180mcu_fd_sc_mcu7t5v0__and4_1 + PLACED ( 60480 329280 ) FN ;
+ - _0996_ gf180mcu_fd_sc_mcu7t5v0__nor3_1 + PLACED ( 56000 344960 ) N ;
+ - _0997_ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 + PLACED ( 61600 290080 ) FS ;
+ - _0998_ gf180mcu_fd_sc_mcu7t5v0__nand4_2 + PLACED ( 64960 337120 ) FS ;
+ - _0999_ gf180mcu_fd_sc_mcu7t5v0__nand2_1 + PLACED ( 75040 313600 ) FN ;
+ - _1000_ gf180mcu_fd_sc_mcu7t5v0__nand2_1 + PLACED ( 45920 313600 ) FN ;
+ - _1001_ gf180mcu_fd_sc_mcu7t5v0__and3_1 + PLACED ( 61600 313600 ) FN ;
+ - _1002_ gf180mcu_fd_sc_mcu7t5v0__clkbuf_1 + PLACED ( 23520 329280 ) FN ;
+ - _1003_ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 + PLACED ( 43680 305760 ) FS ;
+ - _1004_ gf180mcu_fd_sc_mcu7t5v0__oai31_1 + PLACED ( 62720 305760 ) FS ;
+ - _1005_ gf180mcu_fd_sc_mcu7t5v0__aoi21_1 + PLACED ( 77280 305760 ) FS ;
+ - _1006_ gf180mcu_fd_sc_mcu7t5v0__nand4_1 + PLACED ( 50400 305760 ) FS ;
+ - _1007_ gf180mcu_fd_sc_mcu7t5v0__oai31_1 + PLACED ( 60480 297920 ) FN ;
+ - _1008_ gf180mcu_fd_sc_mcu7t5v0__aoi21_1 + PLACED ( 57120 282240 ) FN ;
+ - _1009_ gf180mcu_fd_sc_mcu7t5v0__buf_2 + PLACED ( 330400 250880 ) N ;
+ - _1010_ gf180mcu_fd_sc_mcu7t5v0__and2_1 + PLACED ( 295680 235200 ) N ;
+ - _1011_ gf180mcu_fd_sc_mcu7t5v0__clkbuf_1 + PLACED ( 318080 235200 ) N ;
+ - _1012_ gf180mcu_fd_sc_mcu7t5v0__and2_1 + PLACED ( 306880 235200 ) N ;
+ - _1013_ gf180mcu_fd_sc_mcu7t5v0__clkbuf_1 + PLACED ( 315840 219520 ) N ;
+ - _1014_ gf180mcu_fd_sc_mcu7t5v0__and2_1 + PLACED ( 296800 266560 ) N ;
+ - _1015_ gf180mcu_fd_sc_mcu7t5v0__clkbuf_1 + PLACED ( 310240 266560 ) N ;
+ - _1016_ gf180mcu_fd_sc_mcu7t5v0__and2_1 + PLACED ( 290080 243040 ) FS ;
+ - _1017_ gf180mcu_fd_sc_mcu7t5v0__clkbuf_1 + PLACED ( 301280 243040 ) FS ;
+ - _1018_ gf180mcu_fd_sc_mcu7t5v0__buf_2 + PLACED ( 175840 290080 ) FS ;
+ - _1019_ gf180mcu_fd_sc_mcu7t5v0__and2_1 + PLACED ( 230720 250880 ) N ;
+ - _1020_ gf180mcu_fd_sc_mcu7t5v0__clkbuf_1 + PLACED ( 283360 266560 ) N ;
+ - _1021_ gf180mcu_fd_sc_mcu7t5v0__and2_1 + PLACED ( 296800 250880 ) N ;
+ - _1022_ gf180mcu_fd_sc_mcu7t5v0__clkbuf_1 + PLACED ( 312480 250880 ) N ;
+ - _1023_ gf180mcu_fd_sc_mcu7t5v0__buf_2 + PLACED ( 437920 462560 ) FS ;
+ - _1024_ gf180mcu_fd_sc_mcu7t5v0__buf_2 + PLACED ( 285600 211680 ) FS ;
+ - _1025_ gf180mcu_fd_sc_mcu7t5v0__nor2_1 + PLACED ( 232960 219520 ) FN ;
+ - _1026_ gf180mcu_fd_sc_mcu7t5v0__nand2_1 + PLACED ( 225120 235200 ) N ;
+ - _1027_ gf180mcu_fd_sc_mcu7t5v0__nor2_1 + PLACED ( 227360 243040 ) FS ;
+ - _1028_ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 + PLACED ( 227360 203840 ) N ;
+ - _1029_ gf180mcu_fd_sc_mcu7t5v0__nand2_1 + PLACED ( 241920 211680 ) S ;
+ - _1030_ gf180mcu_fd_sc_mcu7t5v0__nand3_1 + PLACED ( 212800 211680 ) FS ;
+ - _1031_ gf180mcu_fd_sc_mcu7t5v0__buf_2 + PLACED ( 437920 399840 ) FS ;
+ - _1032_ gf180mcu_fd_sc_mcu7t5v0__aoi21_1 + PLACED ( 221760 219520 ) N ;
+ - _1033_ gf180mcu_fd_sc_mcu7t5v0__xor2_1 + PLACED ( 226240 211680 ) FS ;
+ - _1034_ gf180mcu_fd_sc_mcu7t5v0__nor2_1 + PLACED ( 241920 219520 ) N ;
+ - _1035_ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 + PLACED ( 264320 94080 ) N ;
+ - _1036_ gf180mcu_fd_sc_mcu7t5v0__nor2_1 + PLACED ( 330400 94080 ) FN ;
+ - _1037_ gf180mcu_fd_sc_mcu7t5v0__inv_1 + PLACED ( 283360 78400 ) FN ;
+ - _1038_ gf180mcu_fd_sc_mcu7t5v0__nor2_1 + PLACED ( 339360 94080 ) N ;
+ - _1039_ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 + PLACED ( 319200 94080 ) N ;
+ - _1040_ gf180mcu_fd_sc_mcu7t5v0__nor2_1 + PLACED ( 328160 109760 ) FN ;
+ - _1041_ gf180mcu_fd_sc_mcu7t5v0__nor2_1 + PLACED ( 334880 101920 ) S ;
+ - _1042_ gf180mcu_fd_sc_mcu7t5v0__nand2_1 + PLACED ( 306880 117600 ) FS ;
+ - _1043_ gf180mcu_fd_sc_mcu7t5v0__aoi21_1 + PLACED ( 316960 125440 ) N ;
+ - _1044_ gf180mcu_fd_sc_mcu7t5v0__buf_2 + PLACED ( 493920 219520 ) N ;
+ - _1045_ gf180mcu_fd_sc_mcu7t5v0__nor2_1 + PLACED ( 323680 133280 ) FS ;
+ - _1046_ gf180mcu_fd_sc_mcu7t5v0__nor3_1 + PLACED ( 321440 148960 ) FS ;
+ - _1047_ gf180mcu_fd_sc_mcu7t5v0__nand2_1 + PLACED ( 309120 141120 ) FN ;
+ - _1048_ gf180mcu_fd_sc_mcu7t5v0__aoi21_1 + PLACED ( 334880 133280 ) FS ;
+ - _1049_ gf180mcu_fd_sc_mcu7t5v0__nand2_1 + PLACED ( 328160 156800 ) FN ;
+ - _1050_ gf180mcu_fd_sc_mcu7t5v0__aoi21_1 + PLACED ( 321440 164640 ) S ;
+ - _1051_ gf180mcu_fd_sc_mcu7t5v0__nand2_1 + PLACED ( 318080 172480 ) N ;
+ - _1052_ gf180mcu_fd_sc_mcu7t5v0__aoi21_1 + PLACED ( 332640 188160 ) N ;
+ - _1053_ gf180mcu_fd_sc_mcu7t5v0__xor2_1 + PLACED ( 316960 188160 ) N ;
+ - _1054_ gf180mcu_fd_sc_mcu7t5v0__nor2_1 + PLACED ( 331520 172480 ) N ;
+ - _1055_ gf180mcu_fd_sc_mcu7t5v0__nor2_1 + PLACED ( 280000 101920 ) S ;
+ - _1056_ gf180mcu_fd_sc_mcu7t5v0__aoi21_1 + PLACED ( 315840 101920 ) FS ;
+ - _1057_ gf180mcu_fd_sc_mcu7t5v0__nand2_1 + PLACED ( 293440 133280 ) FS ;
+ - _1058_ gf180mcu_fd_sc_mcu7t5v0__nand2_1 + PLACED ( 294560 141120 ) N ;
+ - _1059_ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 + PLACED ( 294560 156800 ) FN ;
+ - _1060_ gf180mcu_fd_sc_mcu7t5v0__nor2_2 + PLACED ( 271040 156800 ) N ;
+ - _1061_ gf180mcu_fd_sc_mcu7t5v0__nor2_1 + PLACED ( 278880 172480 ) N ;
+ - _1062_ gf180mcu_fd_sc_mcu7t5v0__buf_2 + PLACED ( 506240 274400 ) FS ;
+ - _1063_ gf180mcu_fd_sc_mcu7t5v0__aoi211_1 + PLACED ( 278880 180320 ) FS ;
+ - _1064_ gf180mcu_fd_sc_mcu7t5v0__nor2_1 + PLACED ( 271040 101920 ) FS ;
+ - _1065_ gf180mcu_fd_sc_mcu7t5v0__nand2_1 + PLACED ( 284480 156800 ) N ;
+ - _1066_ gf180mcu_fd_sc_mcu7t5v0__oai32_1 + PLACED ( 271040 94080 ) FN ;
+ - _1067_ gf180mcu_fd_sc_mcu7t5v0__xor2_1 + PLACED ( 255360 101920 ) S ;
+ - _1068_ gf180mcu_fd_sc_mcu7t5v0__aoi22_1 + PLACED ( 246400 109760 ) FN ;
+ - _1069_ gf180mcu_fd_sc_mcu7t5v0__nor2_1 + PLACED ( 232960 101920 ) S ;
+ - _1070_ gf180mcu_fd_sc_mcu7t5v0__nor4_2 + PLACED ( 296800 94080 ) N ;
+ - _1071_ gf180mcu_fd_sc_mcu7t5v0__oai32_1 + PLACED ( 288960 101920 ) FS ;
+ - _1072_ gf180mcu_fd_sc_mcu7t5v0__nor2_1 + PLACED ( 294560 125440 ) FN ;
+ - _1073_ gf180mcu_fd_sc_mcu7t5v0__and2_1 + PLACED ( 281120 133280 ) S ;
+ - _1074_ gf180mcu_fd_sc_mcu7t5v0__oai32_1 + PLACED ( 281120 117600 ) FS ;
+ - _1075_ gf180mcu_fd_sc_mcu7t5v0__xor2_1 + PLACED ( 227360 125440 ) N ;
+ - _1076_ gf180mcu_fd_sc_mcu7t5v0__aoi22_1 + PLACED ( 235200 117600 ) FS ;
+ - _1077_ gf180mcu_fd_sc_mcu7t5v0__nor2_1 + PLACED ( 219520 109760 ) FN ;
+ - _1078_ gf180mcu_fd_sc_mcu7t5v0__nand2_1 + PLACED ( 241920 133280 ) S ;
+ - _1079_ gf180mcu_fd_sc_mcu7t5v0__xnor2_1 + PLACED ( 225120 133280 ) FS ;
+ - _1080_ gf180mcu_fd_sc_mcu7t5v0__aoi22_1 + PLACED ( 226240 141120 ) FN ;
+ - _1081_ gf180mcu_fd_sc_mcu7t5v0__nor2_1 + PLACED ( 217280 141120 ) FN ;
+ - _1082_ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 + PLACED ( 272160 148960 ) S ;
+ - _1083_ gf180mcu_fd_sc_mcu7t5v0__nand3_1 + PLACED ( 257600 133280 ) FS ;
+ - _1084_ gf180mcu_fd_sc_mcu7t5v0__xor2_1 + PLACED ( 256480 148960 ) FS ;
+ - _1085_ gf180mcu_fd_sc_mcu7t5v0__aoi22_1 + PLACED ( 258720 141120 ) FN ;
+ - _1086_ gf180mcu_fd_sc_mcu7t5v0__nor2_1 + PLACED ( 238560 141120 ) FN ;
+ - _1087_ gf180mcu_fd_sc_mcu7t5v0__nor2_1 + PLACED ( 259840 156800 ) N ;
+ - _1088_ gf180mcu_fd_sc_mcu7t5v0__xor2_1 + PLACED ( 255360 180320 ) S ;
+ - _1089_ gf180mcu_fd_sc_mcu7t5v0__aoi22_1 + PLACED ( 252000 172480 ) FN ;
+ - _1090_ gf180mcu_fd_sc_mcu7t5v0__nor2_1 + PLACED ( 238560 172480 ) FN ;
+ - _1091_ gf180mcu_fd_sc_mcu7t5v0__nand3_1 + PLACED ( 266560 188160 ) N ;
+ - _1092_ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 + PLACED ( 294560 188160 ) FN ;
+ - _1093_ gf180mcu_fd_sc_mcu7t5v0__aoi221_1 + PLACED ( 269920 196000 ) FS ;
+ - _1094_ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 + PLACED ( 213920 305760 ) FS ;
+ - _1095_ gf180mcu_fd_sc_mcu7t5v0__nor3_1 + PLACED ( 220640 297920 ) N ;
+ - _1096_ gf180mcu_fd_sc_mcu7t5v0__or2_1 + PLACED ( 396480 431200 ) FS ;
+ - _1097_ gf180mcu_fd_sc_mcu7t5v0__nor4_4 + PLACED ( 368480 446880 ) S ;
+ - _1098_ gf180mcu_fd_sc_mcu7t5v0__oai31_1 + PLACED ( 357280 486080 ) N ;
+ - _1099_ gf180mcu_fd_sc_mcu7t5v0__nand2_1 + PLACED ( 374080 486080 ) N ;
+ - _1100_ gf180mcu_fd_sc_mcu7t5v0__nor3_1 + PLACED ( 356160 266560 ) FN ;
+ - _1101_ gf180mcu_fd_sc_mcu7t5v0__nor4_1 + PLACED ( 353920 227360 ) FS ;
+ - _1102_ gf180mcu_fd_sc_mcu7t5v0__nand2_1 + PLACED ( 362880 235200 ) N ;
+ - _1103_ gf180mcu_fd_sc_mcu7t5v0__nor2_1 + PLACED ( 369600 86240 ) FS ;
+ - _1104_ gf180mcu_fd_sc_mcu7t5v0__nor4_1 + PLACED ( 372960 164640 ) S ;
+ - _1105_ gf180mcu_fd_sc_mcu7t5v0__nand2_1 + PLACED ( 374080 156800 ) FN ;
+ - _1106_ gf180mcu_fd_sc_mcu7t5v0__nor4_4 + PLACED ( 374080 235200 ) N ;
+ - _1107_ gf180mcu_fd_sc_mcu7t5v0__buf_2 + PLACED ( 432320 392000 ) N ;
+ - _1108_ gf180mcu_fd_sc_mcu7t5v0__nand2_1 + PLACED ( 381920 486080 ) FN ;
+ - _1109_ gf180mcu_fd_sc_mcu7t5v0__nand3_1 + PLACED ( 402080 501760 ) FN ;
+ - _1110_ gf180mcu_fd_sc_mcu7t5v0__nand2_1 + PLACED ( 388640 517440 ) N ;
+ - _1111_ gf180mcu_fd_sc_mcu7t5v0__oai211_1 + PLACED ( 397600 509600 ) FS ;
+ - _1112_ gf180mcu_fd_sc_mcu7t5v0__oai21_1 + PLACED ( 400960 493920 ) FS ;
+ - _1113_ gf180mcu_fd_sc_mcu7t5v0__or2_1 + PLACED ( 412160 486080 ) FN ;
+ - _1114_ gf180mcu_fd_sc_mcu7t5v0__aoi21_1 + PLACED ( 390880 501760 ) N ;
+ - _1115_ gf180mcu_fd_sc_mcu7t5v0__nor2_1 + PLACED ( 398720 486080 ) N ;
+ - _1116_ gf180mcu_fd_sc_mcu7t5v0__nand2_1 + PLACED ( 412160 501760 ) N ;
+ - _1117_ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 + PLACED ( 394240 493920 ) FS ;
+ - _1118_ gf180mcu_fd_sc_mcu7t5v0__or2_1 + PLACED ( 383040 493920 ) S ;
+ - _1119_ gf180mcu_fd_sc_mcu7t5v0__oai22_1 + PLACED ( 380800 509600 ) S ;
+ - _1120_ gf180mcu_fd_sc_mcu7t5v0__nand2_1 + PLACED ( 360640 517440 ) FN ;
+ - _1121_ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 + PLACED ( 357280 501760 ) FN ;
+ - _1122_ gf180mcu_fd_sc_mcu7t5v0__nor3_1 + PLACED ( 379680 501760 ) FN ;
+ - _1123_ gf180mcu_fd_sc_mcu7t5v0__oai21_1 + PLACED ( 365120 493920 ) FS ;
+ - _1124_ gf180mcu_fd_sc_mcu7t5v0__aoi21_1 + PLACED ( 353920 493920 ) S ;
+ - _1125_ gf180mcu_fd_sc_mcu7t5v0__oai21_1 + PLACED ( 341600 493920 ) FS ;
+ - _1126_ gf180mcu_fd_sc_mcu7t5v0__and2_1 + PLACED ( 343840 486080 ) FN ;
+ - _1127_ gf180mcu_fd_sc_mcu7t5v0__clkbuf_1 + PLACED ( 320320 478240 ) S ;
+ - _1128_ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 + PLACED ( 386400 454720 ) N ;
+ - _1129_ gf180mcu_fd_sc_mcu7t5v0__xor2_1 + PLACED ( 359520 462560 ) FS ;
+ - _1130_ gf180mcu_fd_sc_mcu7t5v0__aoi221_2 + PLACED ( 385280 470400 ) N ;
+ - _1131_ gf180mcu_fd_sc_mcu7t5v0__xor2_1 + PLACED ( 415520 470400 ) FN ;
+ - _1132_ gf180mcu_fd_sc_mcu7t5v0__oai22_1 + PLACED ( 386400 478240 ) S ;
+ - _1133_ gf180mcu_fd_sc_mcu7t5v0__xor2_1 + PLACED ( 352800 470400 ) N ;
+ - _1134_ gf180mcu_fd_sc_mcu7t5v0__nor3_1 + PLACED ( 374080 470400 ) N ;
+ - _1135_ gf180mcu_fd_sc_mcu7t5v0__nand2_1 + PLACED ( 381920 462560 ) S ;
+ - _1136_ gf180mcu_fd_sc_mcu7t5v0__aoi21_2 + PLACED ( 389760 462560 ) FS ;
+ - _1137_ gf180mcu_fd_sc_mcu7t5v0__oai21_1 + PLACED ( 395360 423360 ) N ;
+ - _1138_ gf180mcu_fd_sc_mcu7t5v0__aoi21_1 + PLACED ( 384160 423360 ) N ;
+ - _1139_ gf180mcu_fd_sc_mcu7t5v0__inv_2 + PLACED ( 428960 399840 ) FS ;
+ - _1140_ gf180mcu_fd_sc_mcu7t5v0__nand2_1 + PLACED ( 416640 423360 ) FN ;
+ - _1141_ gf180mcu_fd_sc_mcu7t5v0__nand2_1 + PLACED ( 393120 454720 ) N ;
+ - _1142_ gf180mcu_fd_sc_mcu7t5v0__nand3_1 + PLACED ( 406560 423360 ) FN ;
+ - _1143_ gf180mcu_fd_sc_mcu7t5v0__aoi21_1 + PLACED ( 414400 415520 ) FS ;
+ - _1144_ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 + PLACED ( 411040 454720 ) FN ;
+ - _1145_ gf180mcu_fd_sc_mcu7t5v0__nand3_1 + PLACED ( 400960 454720 ) N ;
+ - _1146_ gf180mcu_fd_sc_mcu7t5v0__aoi22_1 + PLACED ( 414400 446880 ) FS ;
+ - _1147_ gf180mcu_fd_sc_mcu7t5v0__aoi211_1 + PLACED ( 414400 431200 ) FS ;
+ - _1148_ gf180mcu_fd_sc_mcu7t5v0__nor2_1 + PLACED ( 387520 431200 ) S ;
+ - _1149_ gf180mcu_fd_sc_mcu7t5v0__aoi21_1 + PLACED ( 357280 439040 ) N ;
+ - _1150_ gf180mcu_fd_sc_mcu7t5v0__nand2_1 + PLACED ( 361760 423360 ) N ;
+ - _1151_ gf180mcu_fd_sc_mcu7t5v0__aoi21_1 + PLACED ( 369600 431200 ) FS ;
+ - _1152_ gf180mcu_fd_sc_mcu7t5v0__nor3_1 + PLACED ( 346080 439040 ) FN ;
+ - _1153_ gf180mcu_fd_sc_mcu7t5v0__and2_1 + PLACED ( 355040 446880 ) FS ;
+ - _1154_ gf180mcu_fd_sc_mcu7t5v0__aoi21_1 + PLACED ( 374080 454720 ) N ;
+ - _1155_ gf180mcu_fd_sc_mcu7t5v0__aoi211_1 + PLACED ( 351680 454720 ) N ;
+ - _1156_ gf180mcu_fd_sc_mcu7t5v0__or3_1 + PLACED ( 495040 446880 ) FS ;
+ - _1157_ gf180mcu_fd_sc_mcu7t5v0__nor3_2 + PLACED ( 507360 454720 ) N ;
+ - _1158_ gf180mcu_fd_sc_mcu7t5v0__oai31_1 + PLACED ( 497280 478240 ) FS ;
+ - _1159_ gf180mcu_fd_sc_mcu7t5v0__nand2_1 + PLACED ( 495040 486080 ) FN ;
+ - _1160_ gf180mcu_fd_sc_mcu7t5v0__nand2_1 + PLACED ( 465920 509600 ) S ;
+ - _1161_ gf180mcu_fd_sc_mcu7t5v0__nand3_1 + PLACED ( 465920 493920 ) S ;
+ - _1162_ gf180mcu_fd_sc_mcu7t5v0__nand2_1 + PLACED ( 459200 517440 ) FN ;
+ - _1163_ gf180mcu_fd_sc_mcu7t5v0__oai211_1 + PLACED ( 453600 501760 ) FN ;
+ - _1164_ gf180mcu_fd_sc_mcu7t5v0__oai21_1 + PLACED ( 454720 493920 ) FS ;
+ - _1165_ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 + PLACED ( 472640 478240 ) S ;
+ - _1166_ gf180mcu_fd_sc_mcu7t5v0__inv_1 + PLACED ( 465920 486080 ) N ;
+ - _1167_ gf180mcu_fd_sc_mcu7t5v0__nand2_1 + PLACED ( 479360 486080 ) N ;
+ - _1168_ gf180mcu_fd_sc_mcu7t5v0__aoi21_1 + PLACED ( 487200 501760 ) N ;
+ - _1169_ gf180mcu_fd_sc_mcu7t5v0__nor2_1 + PLACED ( 453600 486080 ) FN ;
+ - _1170_ gf180mcu_fd_sc_mcu7t5v0__nand2_1 + PLACED ( 443520 486080 ) FN ;
+ - _1171_ gf180mcu_fd_sc_mcu7t5v0__nand3_1 + PLACED ( 476000 493920 ) S ;
+ - _1172_ gf180mcu_fd_sc_mcu7t5v0__oai22_1 + PLACED ( 472640 501760 ) N ;
+ - _1173_ gf180mcu_fd_sc_mcu7t5v0__nand2_1 + PLACED ( 477120 509600 ) FS ;
+ - _1174_ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 + PLACED ( 523040 501760 ) FN ;
+ - _1175_ gf180mcu_fd_sc_mcu7t5v0__nor3_1 + PLACED ( 498400 501760 ) N ;
+ - _1176_ gf180mcu_fd_sc_mcu7t5v0__oai21_1 + PLACED ( 500640 493920 ) S ;
+ - _1177_ gf180mcu_fd_sc_mcu7t5v0__aoi21_1 + PLACED ( 511840 493920 ) FS ;
+ - _1178_ gf180mcu_fd_sc_mcu7t5v0__oai21_1 + PLACED ( 511840 501760 ) N ;
+ - _1179_ gf180mcu_fd_sc_mcu7t5v0__and2_1 + PLACED ( 519680 486080 ) N ;
+ - _1180_ gf180mcu_fd_sc_mcu7t5v0__clkbuf_1 + PLACED ( 530880 478240 ) FS ;
+ - _1181_ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 + PLACED ( 484960 478240 ) FS ;
+ - _1182_ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 + PLACED ( 470400 470400 ) N ;
+ - _1183_ gf180mcu_fd_sc_mcu7t5v0__xor2_1 + PLACED ( 505120 470400 ) FN ;
+ - _1184_ gf180mcu_fd_sc_mcu7t5v0__aoi221_2 + PLACED ( 477120 470400 ) N ;
+ - _1185_ gf180mcu_fd_sc_mcu7t5v0__xnor2_1 + PLACED ( 493920 462560 ) S ;
+ - _1186_ gf180mcu_fd_sc_mcu7t5v0__oai221_2 + PLACED ( 479360 454720 ) N ;
+ - _1187_ gf180mcu_fd_sc_mcu7t5v0__aoi221_2 + PLACED ( 463680 462560 ) S ;
+ - _1188_ gf180mcu_fd_sc_mcu7t5v0__nand2_1 + PLACED ( 455840 462560 ) FS ;
+ - _1189_ gf180mcu_fd_sc_mcu7t5v0__aoi21_2 + PLACED ( 462560 454720 ) N ;
+ - _1190_ gf180mcu_fd_sc_mcu7t5v0__oai21_1 + PLACED ( 453600 439040 ) FN ;
+ - _1191_ gf180mcu_fd_sc_mcu7t5v0__aoi21_1 + PLACED ( 446880 446880 ) FS ;
+ - _1192_ gf180mcu_fd_sc_mcu7t5v0__xor2_1 + PLACED ( 472640 431200 ) S ;
+ - _1193_ gf180mcu_fd_sc_mcu7t5v0__aoi22_1 + PLACED ( 453600 423360 ) FN ;
+ - _1194_ gf180mcu_fd_sc_mcu7t5v0__nor2_1 + PLACED ( 458080 407680 ) N ;
+ - _1195_ gf180mcu_fd_sc_mcu7t5v0__and3_1 + PLACED ( 492800 439040 ) N ;
+ - _1196_ gf180mcu_fd_sc_mcu7t5v0__aoi21_1 + PLACED ( 497280 423360 ) N ;
+ - _1197_ gf180mcu_fd_sc_mcu7t5v0__nor2_1 + PLACED ( 510720 431200 ) FS ;
+ - _1198_ gf180mcu_fd_sc_mcu7t5v0__aoi22_1 + PLACED ( 498400 431200 ) S ;
+ - _1199_ gf180mcu_fd_sc_mcu7t5v0__nor2_1 + PLACED ( 508480 423360 ) N ;
+ - _1200_ gf180mcu_fd_sc_mcu7t5v0__aoi21_1 + PLACED ( 533120 439040 ) N ;
+ - _1201_ gf180mcu_fd_sc_mcu7t5v0__nand2_1 + PLACED ( 511840 439040 ) N ;
+ - _1202_ gf180mcu_fd_sc_mcu7t5v0__aoi21_1 + PLACED ( 519680 439040 ) N ;
+ - _1203_ gf180mcu_fd_sc_mcu7t5v0__nor3_1 + PLACED ( 533120 423360 ) FN ;
+ - _1204_ gf180mcu_fd_sc_mcu7t5v0__and2_1 + PLACED ( 523040 446880 ) FS ;
+ - _1205_ gf180mcu_fd_sc_mcu7t5v0__aoi21_1 + PLACED ( 534240 446880 ) FS ;
+ - _1206_ gf180mcu_fd_sc_mcu7t5v0__aoi211_1 + PLACED ( 533120 454720 ) FN ;
+ - _1207_ gf180mcu_fd_sc_mcu7t5v0__or2_1 + PLACED ( 493920 384160 ) FS ;
+ - _1208_ gf180mcu_fd_sc_mcu7t5v0__nor4_2 + PLACED ( 493920 368480 ) FS ;
+ - _1209_ gf180mcu_fd_sc_mcu7t5v0__oai31_1 + PLACED ( 495040 329280 ) FN ;
+ - _1210_ gf180mcu_fd_sc_mcu7t5v0__nand2_1 + PLACED ( 463680 329280 ) FN ;
+ - _1211_ gf180mcu_fd_sc_mcu7t5v0__nand2_1 + PLACED ( 474880 321440 ) FS ;
+ - _1212_ gf180mcu_fd_sc_mcu7t5v0__nand3_1 + PLACED ( 461440 313600 ) FN ;
+ - _1213_ gf180mcu_fd_sc_mcu7t5v0__nand2_1 + PLACED ( 461440 297920 ) FN ;
+ - _1214_ gf180mcu_fd_sc_mcu7t5v0__oai211_1 + PLACED ( 454720 305760 ) S ;
+ - _1215_ gf180mcu_fd_sc_mcu7t5v0__oai21_1 + PLACED ( 463680 321440 ) FS ;
+ - _1216_ gf180mcu_fd_sc_mcu7t5v0__or2_1 + PLACED ( 479360 313600 ) N ;
+ - _1217_ gf180mcu_fd_sc_mcu7t5v0__aoi21_1 + PLACED ( 490560 313600 ) FN ;
+ - _1218_ gf180mcu_fd_sc_mcu7t5v0__nor2_1 + PLACED ( 442400 313600 ) FN ;
+ - _1219_ gf180mcu_fd_sc_mcu7t5v0__nand2_1 + PLACED ( 443520 329280 ) N ;
+ - _1220_ gf180mcu_fd_sc_mcu7t5v0__nor2_1 + PLACED ( 474880 305760 ) FS ;
+ - _1221_ gf180mcu_fd_sc_mcu7t5v0__nand2_1 + PLACED ( 483840 305760 ) FS ;
+ - _1222_ gf180mcu_fd_sc_mcu7t5v0__oai22_1 + PLACED ( 476000 297920 ) N ;
+ - _1223_ gf180mcu_fd_sc_mcu7t5v0__nand2_1 + PLACED ( 479360 290080 ) FS ;
+ - _1224_ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 + PLACED ( 506240 337120 ) S ;
+ - _1225_ gf180mcu_fd_sc_mcu7t5v0__nor3_1 + PLACED ( 501760 313600 ) N ;
+ - _1226_ gf180mcu_fd_sc_mcu7t5v0__oai21_1 + PLACED ( 495040 321440 ) S ;
+ - _1227_ gf180mcu_fd_sc_mcu7t5v0__aoi21_1 + PLACED ( 509600 329280 ) N ;
+ - _1228_ gf180mcu_fd_sc_mcu7t5v0__oai21_1 + PLACED ( 506240 321440 ) FS ;
+ - _1229_ gf180mcu_fd_sc_mcu7t5v0__and2_1 + PLACED ( 533120 329280 ) N ;
+ - _1230_ gf180mcu_fd_sc_mcu7t5v0__clkbuf_1 + PLACED ( 517440 337120 ) FS ;
+ - _1231_ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 + PLACED ( 484960 368480 ) S ;
+ - _1232_ gf180mcu_fd_sc_mcu7t5v0__aoi22_1 + PLACED ( 493920 337120 ) FS ;
+ - _1233_ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 + PLACED ( 470400 337120 ) FS ;
+ - _1234_ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 + PLACED ( 474880 352800 ) FS ;
+ - _1235_ gf180mcu_fd_sc_mcu7t5v0__aoi22_1 + PLACED ( 477120 337120 ) FS ;
+ - _1236_ gf180mcu_fd_sc_mcu7t5v0__xor2_1 + PLACED ( 502880 352800 ) FS ;
+ - _1237_ gf180mcu_fd_sc_mcu7t5v0__oai22_1 + PLACED ( 493920 344960 ) N ;
+ - _1238_ gf180mcu_fd_sc_mcu7t5v0__oai22_1 + PLACED ( 480480 344960 ) N ;
+ - _1239_ gf180mcu_fd_sc_mcu7t5v0__nor3_1 + PLACED ( 507360 344960 ) N ;
+ - _1240_ gf180mcu_fd_sc_mcu7t5v0__nand3_1 + PLACED ( 481600 352800 ) S ;
+ - _1241_ gf180mcu_fd_sc_mcu7t5v0__and3_1 + PLACED ( 460320 352800 ) S ;
+ - _1242_ gf180mcu_fd_sc_mcu7t5v0__oai21_1 + PLACED ( 453600 360640 ) FN ;
+ - _1243_ gf180mcu_fd_sc_mcu7t5v0__aoi21_1 + PLACED ( 444640 368480 ) FS ;
+ - _1244_ gf180mcu_fd_sc_mcu7t5v0__nand2_1 + PLACED ( 483840 399840 ) FS ;
+ - _1245_ gf180mcu_fd_sc_mcu7t5v0__nand2_1 + PLACED ( 477120 360640 ) N ;
+ - _1246_ gf180mcu_fd_sc_mcu7t5v0__nand3_1 + PLACED ( 482720 392000 ) N ;
+ - _1247_ gf180mcu_fd_sc_mcu7t5v0__aoi21_1 + PLACED ( 493920 399840 ) FS ;
+ - _1248_ gf180mcu_fd_sc_mcu7t5v0__nand3_1 + PLACED ( 462560 376320 ) N ;
+ - _1249_ gf180mcu_fd_sc_mcu7t5v0__aoi22_1 + PLACED ( 472640 368480 ) FS ;
+ - _1250_ gf180mcu_fd_sc_mcu7t5v0__aoi211_1 + PLACED ( 473760 384160 ) S ;
+ - _1251_ gf180mcu_fd_sc_mcu7t5v0__nor2_1 + PLACED ( 496160 360640 ) N ;
+ - _1252_ gf180mcu_fd_sc_mcu7t5v0__aoi21_1 + PLACED ( 509600 384160 ) FS ;
+ - _1253_ gf180mcu_fd_sc_mcu7t5v0__nand2_1 + PLACED ( 501760 392000 ) N ;
+ - _1254_ gf180mcu_fd_sc_mcu7t5v0__aoi21_1 + PLACED ( 515200 392000 ) N ;
+ - _1255_ gf180mcu_fd_sc_mcu7t5v0__nor3_1 + PLACED ( 520800 399840 ) FS ;
+ - _1256_ gf180mcu_fd_sc_mcu7t5v0__and2_1 + PLACED ( 510720 376320 ) N ;
+ - _1257_ gf180mcu_fd_sc_mcu7t5v0__aoi21_1 + PLACED ( 519680 360640 ) N ;
+ - _1258_ gf180mcu_fd_sc_mcu7t5v0__aoi211_1 + PLACED ( 521920 368480 ) FS ;
+ - _1259_ gf180mcu_fd_sc_mcu7t5v0__nand2_2 + PLACED ( 329280 392000 ) N ;
+ - _1260_ gf180mcu_fd_sc_mcu7t5v0__nor2_1 + PLACED ( 356160 360640 ) N ;
+ - _1261_ gf180mcu_fd_sc_mcu7t5v0__nand3_1 + PLACED ( 359520 337120 ) FS ;
+ - _1262_ gf180mcu_fd_sc_mcu7t5v0__nor3_2 + PLACED ( 368480 321440 ) S ;
+ - _1263_ gf180mcu_fd_sc_mcu7t5v0__nand2_1 + PLACED ( 375200 337120 ) FS ;
+ - _1264_ gf180mcu_fd_sc_mcu7t5v0__nor3_4 + PLACED ( 380800 352800 ) FS ;
+ - _1265_ gf180mcu_fd_sc_mcu7t5v0__nor2_2 + PLACED ( 379680 360640 ) FN ;
+ - _1266_ gf180mcu_fd_sc_mcu7t5v0__nand3_4 + PLACED ( 379680 439040 ) N ;
+ - _1267_ gf180mcu_fd_sc_mcu7t5v0__oai211_4 + PLACED ( 381920 376320 ) N ;
+ - _1268_ gf180mcu_fd_sc_mcu7t5v0__nor2_1 + PLACED ( 374080 392000 ) FN ;
+ - _1269_ gf180mcu_fd_sc_mcu7t5v0__aoi21_1 + PLACED ( 366240 384160 ) S ;
+ - _1270_ gf180mcu_fd_sc_mcu7t5v0__aoi221_1 + PLACED ( 383040 392000 ) FN ;
+ - _1271_ gf180mcu_fd_sc_mcu7t5v0__nand2_1 + PLACED ( 349440 384160 ) S ;
+ - _1272_ gf180mcu_fd_sc_mcu7t5v0__nand2_1 + PLACED ( 398720 368480 ) S ;
+ - _1273_ gf180mcu_fd_sc_mcu7t5v0__nand3_1 + PLACED ( 378560 368480 ) S ;
+ - _1274_ gf180mcu_fd_sc_mcu7t5v0__nand3_1 + PLACED ( 388640 368480 ) S ;
+ - _1275_ gf180mcu_fd_sc_mcu7t5v0__aoi21_1 + PLACED ( 349440 368480 ) FS ;
+ - _1276_ gf180mcu_fd_sc_mcu7t5v0__xor2_1 + PLACED ( 393120 360640 ) FN ;
+ - _1277_ gf180mcu_fd_sc_mcu7t5v0__aoi211_1 + PLACED ( 389760 344960 ) N ;
+ - _1278_ gf180mcu_fd_sc_mcu7t5v0__nand4_1 + PLACED ( 353920 344960 ) N ;
+ - _1279_ gf180mcu_fd_sc_mcu7t5v0__nand2_1 + PLACED ( 372960 352800 ) FS ;
+ - _1280_ gf180mcu_fd_sc_mcu7t5v0__oai21_1 + PLACED ( 378560 344960 ) N ;
+ - _1281_ gf180mcu_fd_sc_mcu7t5v0__aoi221_1 + PLACED ( 352800 352800 ) S ;
+ - _1282_ gf180mcu_fd_sc_mcu7t5v0__oai21_1 + PLACED ( 341600 392000 ) FN ;
+ - _1283_ gf180mcu_fd_sc_mcu7t5v0__nand2_1 + PLACED ( 268800 399840 ) FS ;
+ - _1284_ gf180mcu_fd_sc_mcu7t5v0__nor3_4 + PLACED ( 276640 399840 ) FS ;
+ - _1285_ gf180mcu_fd_sc_mcu7t5v0__xnor2_1 + PLACED ( 338240 407680 ) N ;
+ - _1286_ gf180mcu_fd_sc_mcu7t5v0__nor2_1 + PLACED ( 355040 407680 ) N ;
+ - _1287_ gf180mcu_fd_sc_mcu7t5v0__nand3_1 + PLACED ( 319200 415520 ) FS ;
+ - _1288_ gf180mcu_fd_sc_mcu7t5v0__nand2_1 + PLACED ( 323680 423360 ) N ;
+ - _1289_ gf180mcu_fd_sc_mcu7t5v0__aoi21_1 + PLACED ( 325920 407680 ) N ;
+ - _1290_ gf180mcu_fd_sc_mcu7t5v0__and2_1 + PLACED ( 314720 407680 ) FN ;
+ - _1291_ gf180mcu_fd_sc_mcu7t5v0__clkbuf_1 + PLACED ( 310240 423360 ) FN ;
+ - _1292_ gf180mcu_fd_sc_mcu7t5v0__xor2_1 + PLACED ( 310240 399840 ) FS ;
+ - _1293_ gf180mcu_fd_sc_mcu7t5v0__nor2_1 + PLACED ( 316960 384160 ) FS ;
+ - _1294_ gf180mcu_fd_sc_mcu7t5v0__nand2_1 + PLACED ( 246400 423360 ) FN ;
+ - _1295_ gf180mcu_fd_sc_mcu7t5v0__nand3_2 + PLACED ( 420000 462560 ) FS ;
+ - _1296_ gf180mcu_fd_sc_mcu7t5v0__oai21_2 + PLACED ( 234080 431200 ) S ;
+ - _1297_ gf180mcu_fd_sc_mcu7t5v0__nor3_1 + PLACED ( 275520 431200 ) FS ;
+ - _1298_ gf180mcu_fd_sc_mcu7t5v0__and2_1 + PLACED ( 286720 431200 ) FS ;
+ - _1299_ gf180mcu_fd_sc_mcu7t5v0__and2_1 + PLACED ( 273280 439040 ) FN ;
+ - _1300_ gf180mcu_fd_sc_mcu7t5v0__nor4_1 + PLACED ( 275520 423360 ) N ;
+ - _1301_ gf180mcu_fd_sc_mcu7t5v0__clkbuf_1 + PLACED ( 266560 423360 ) FN ;
+ - _1302_ gf180mcu_fd_sc_mcu7t5v0__nand2_1 + PLACED ( 295680 439040 ) N ;
+ - _1303_ gf180mcu_fd_sc_mcu7t5v0__aoi21_1 + PLACED ( 296800 446880 ) S ;
+ - _1304_ gf180mcu_fd_sc_mcu7t5v0__aoi211_1 + PLACED ( 296800 454720 ) N ;
+ - _1305_ gf180mcu_fd_sc_mcu7t5v0__aoi21_1 + PLACED ( 280000 446880 ) FS ;
+ - _1306_ gf180mcu_fd_sc_mcu7t5v0__and3_1 + PLACED ( 277760 454720 ) FN ;
+ - _1307_ gf180mcu_fd_sc_mcu7t5v0__nor3_1 + PLACED ( 274400 462560 ) S ;
+ - _1308_ gf180mcu_fd_sc_mcu7t5v0__xnor2_1 + PLACED ( 260960 454720 ) FN ;
+ - _1309_ gf180mcu_fd_sc_mcu7t5v0__nor3_1 + PLACED ( 262080 446880 ) FS ;
+ - _1310_ gf180mcu_fd_sc_mcu7t5v0__oai21_1 + PLACED ( 235200 423360 ) FN ;
+ - _1311_ gf180mcu_fd_sc_mcu7t5v0__nand2_1 + PLACED ( 187040 392000 ) N ;
+ - _1312_ gf180mcu_fd_sc_mcu7t5v0__nor3_2 + PLACED ( 194880 392000 ) N ;
+ - _1313_ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 + PLACED ( 194880 415520 ) S ;
+ - _1314_ gf180mcu_fd_sc_mcu7t5v0__xor2_1 + PLACED ( 184800 423360 ) FN ;
+ - _1315_ gf180mcu_fd_sc_mcu7t5v0__nor2_1 + PLACED ( 184800 431200 ) FS ;
+ - _1316_ gf180mcu_fd_sc_mcu7t5v0__nand3_1 + PLACED ( 213920 431200 ) FS ;
+ - _1317_ gf180mcu_fd_sc_mcu7t5v0__aoi21_1 + PLACED ( 202720 431200 ) FS ;
+ - _1318_ gf180mcu_fd_sc_mcu7t5v0__nor2_1 + PLACED ( 193760 431200 ) S ;
+ - _1319_ gf180mcu_fd_sc_mcu7t5v0__and2_1 + PLACED ( 215040 439040 ) FN ;
+ - _1320_ gf180mcu_fd_sc_mcu7t5v0__clkbuf_1 + PLACED ( 210560 446880 ) FS ;
+ - _1321_ gf180mcu_fd_sc_mcu7t5v0__xor2_1 + PLACED ( 217280 423360 ) N ;
+ - _1322_ gf180mcu_fd_sc_mcu7t5v0__nor2_1 + PLACED ( 225120 431200 ) FS ;
+ - _1323_ gf180mcu_fd_sc_mcu7t5v0__nand3_1 + PLACED ( 453600 344960 ) FN ;
+ - _1324_ gf180mcu_fd_sc_mcu7t5v0__and2_1 + PLACED ( 178080 352800 ) FS ;
+ - _1325_ gf180mcu_fd_sc_mcu7t5v0__xor2_1 + PLACED ( 191520 360640 ) N ;
+ - _1326_ gf180mcu_fd_sc_mcu7t5v0__nor2_1 + PLACED ( 215040 360640 ) N ;
+ - _1327_ gf180mcu_fd_sc_mcu7t5v0__nor2_1 + PLACED ( 189280 399840 ) FS ;
+ - _1328_ gf180mcu_fd_sc_mcu7t5v0__aoi21_1 + PLACED ( 183680 407680 ) N ;
+ - _1329_ gf180mcu_fd_sc_mcu7t5v0__oai21_1 + PLACED ( 175840 399840 ) S ;
+ - _1330_ gf180mcu_fd_sc_mcu7t5v0__aoi21_1 + PLACED ( 175840 415520 ) S ;
+ - _1331_ gf180mcu_fd_sc_mcu7t5v0__nand2_1 + PLACED ( 198240 399840 ) FS ;
+ - _1332_ gf180mcu_fd_sc_mcu7t5v0__nand3_1 + PLACED ( 206080 399840 ) FS ;
+ - _1333_ gf180mcu_fd_sc_mcu7t5v0__xor2_1 + PLACED ( 211680 384160 ) FS ;
+ - _1334_ gf180mcu_fd_sc_mcu7t5v0__nor2_1 + PLACED ( 222880 399840 ) FS ;
+ - _1335_ gf180mcu_fd_sc_mcu7t5v0__nand3_1 + PLACED ( 199360 384160 ) S ;
+ - _1336_ gf180mcu_fd_sc_mcu7t5v0__xor2_1 + PLACED ( 183680 384160 ) FS ;
+ - _1337_ gf180mcu_fd_sc_mcu7t5v0__oai22_1 + PLACED ( 187040 376320 ) N ;
+ - _1338_ gf180mcu_fd_sc_mcu7t5v0__and2_1 + PLACED ( 175840 368480 ) S ;
+ - _1339_ gf180mcu_fd_sc_mcu7t5v0__clkbuf_1 + PLACED ( 159040 368480 ) S ;
+ - _1340_ gf180mcu_fd_sc_mcu7t5v0__aoi21_1 + PLACED ( 269920 344960 ) N ;
+ - _1341_ gf180mcu_fd_sc_mcu7t5v0__oai21_1 + PLACED ( 258720 344960 ) N ;
+ - _1342_ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 + PLACED ( 259840 329280 ) N ;
+ - _1343_ gf180mcu_fd_sc_mcu7t5v0__aoi21_1 + PLACED ( 236320 352800 ) S ;
+ - _1344_ gf180mcu_fd_sc_mcu7t5v0__and3_1 + PLACED ( 231840 337120 ) S ;
+ - _1345_ gf180mcu_fd_sc_mcu7t5v0__nor3_1 + PLACED ( 232960 321440 ) S ;
+ - _1346_ gf180mcu_fd_sc_mcu7t5v0__xor2_1 + PLACED ( 192640 344960 ) FN ;
+ - _1347_ gf180mcu_fd_sc_mcu7t5v0__and2_1 + PLACED ( 175840 337120 ) S ;
+ - _1348_ gf180mcu_fd_sc_mcu7t5v0__clkbuf_1 + PLACED ( 164640 337120 ) S ;
+ - _1349_ gf180mcu_fd_sc_mcu7t5v0__or2_1 + PLACED ( 390880 313600 ) N ;
+ - _1350_ gf180mcu_fd_sc_mcu7t5v0__xnor2_1 + PLACED ( 386400 321440 ) S ;
+ - _1351_ gf180mcu_fd_sc_mcu7t5v0__nor2_1 + PLACED ( 390880 305760 ) FS ;
+ - _1352_ gf180mcu_fd_sc_mcu7t5v0__nand2_1 + PLACED ( 414400 321440 ) FS ;
+ - _1353_ gf180mcu_fd_sc_mcu7t5v0__xor2_1 + PLACED ( 395360 329280 ) N ;
+ - _1354_ gf180mcu_fd_sc_mcu7t5v0__nor2_1 + PLACED ( 403200 321440 ) FS ;
+ - _1355_ gf180mcu_fd_sc_mcu7t5v0__nor4_1 + PLACED ( 467040 219520 ) N ;
+ - _1356_ gf180mcu_fd_sc_mcu7t5v0__oai21_1 + PLACED ( 470400 117600 ) S ;
+ - _1357_ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 + PLACED ( 552160 243040 ) FS ;
+ - _1358_ gf180mcu_fd_sc_mcu7t5v0__nor2_1 + PLACED ( 554400 235200 ) N ;
+ - _1359_ gf180mcu_fd_sc_mcu7t5v0__nor2_1 + PLACED ( 543200 243040 ) S ;
+ - _1360_ gf180mcu_fd_sc_mcu7t5v0__nand3_1 + PLACED ( 539840 227360 ) FS ;
+ - _1361_ gf180mcu_fd_sc_mcu7t5v0__oai31_1 + PLACED ( 539840 235200 ) N ;
+ - _1362_ gf180mcu_fd_sc_mcu7t5v0__and3_1 + PLACED ( 478240 227360 ) FS ;
+ - _1363_ gf180mcu_fd_sc_mcu7t5v0__clkbuf_1 + PLACED ( 374080 219520 ) FN ;
+ - _1364_ gf180mcu_fd_sc_mcu7t5v0__dffq_1 + PLACED ( 440160 86240 ) FS ;
+ - _1365_ gf180mcu_fd_sc_mcu7t5v0__dffq_1 + PLACED ( 517440 274400 ) FS ;
+ - _1366_ gf180mcu_fd_sc_mcu7t5v0__dffq_1 + PLACED ( 203840 86240 ) FS ;
+ - _1367_ gf180mcu_fd_sc_mcu7t5v0__dffq_1 + PLACED ( 398720 282240 ) N ;
+ - _1368_ gf180mcu_fd_sc_mcu7t5v0__dffq_1 + PLACED ( 116480 86240 ) S ;
+ - _1369_ gf180mcu_fd_sc_mcu7t5v0__dffq_1 + PLACED ( 512960 211680 ) FS ;
+ - _1370_ gf180mcu_fd_sc_mcu7t5v0__dffq_1 + PLACED ( 533120 203840 ) N ;
+ - _1371_ gf180mcu_fd_sc_mcu7t5v0__dffq_1 + PLACED ( 493920 227360 ) FS ;
+ - _1372_ gf180mcu_fd_sc_mcu7t5v0__dffq_1 + PLACED ( 154560 297920 ) FN ;
+ - _1373_ gf180mcu_fd_sc_mcu7t5v0__dffq_1 + PLACED ( 488320 250880 ) N ;
+ - _1374_ gf180mcu_fd_sc_mcu7t5v0__dffq_1 + PLACED ( 490560 266560 ) N ;
+ - _1375_ gf180mcu_fd_sc_mcu7t5v0__dffq_1 + PLACED ( 241920 235200 ) N ;
+ - _1376_ gf180mcu_fd_sc_mcu7t5v0__dffq_1 + PLACED ( 257600 219520 ) N ;
+ - _1377_ gf180mcu_fd_sc_mcu7t5v0__dffq_1 + PLACED ( 255360 250880 ) N ;
+ - _1378_ gf180mcu_fd_sc_mcu7t5v0__dffq_1 + PLACED ( 175840 258720 ) FS ;
+ - _1379_ gf180mcu_fd_sc_mcu7t5v0__dffq_1 + PLACED ( 147840 250880 ) N ;
+ - _1380_ gf180mcu_fd_sc_mcu7t5v0__dffq_1 + PLACED ( 146720 235200 ) N ;
+ - _1381_ gf180mcu_fd_sc_mcu7t5v0__dffq_1 + PLACED ( 136640 211680 ) FS ;
+ - _1382_ gf180mcu_fd_sc_mcu7t5v0__dffq_1 + PLACED ( 159040 188160 ) N ;
+ - _1383_ gf180mcu_fd_sc_mcu7t5v0__dffq_2 + PLACED ( 162400 172480 ) N ;
+ - _1384_ gf180mcu_fd_sc_mcu7t5v0__dffq_2 + PLACED ( 179200 164640 ) S ;
+ - _1385_ gf180mcu_fd_sc_mcu7t5v0__dffq_1 + PLACED ( 89600 141120 ) N ;
+ - _1386_ gf180mcu_fd_sc_mcu7t5v0__dffq_1 + PLACED ( 101920 211680 ) FS ;
+ - _1387_ gf180mcu_fd_sc_mcu7t5v0__dffq_1 + PLACED ( 133280 180320 ) S ;
+ - _1388_ gf180mcu_fd_sc_mcu7t5v0__dffq_1 + PLACED ( 115360 148960 ) FS ;
+ - _1389_ gf180mcu_fd_sc_mcu7t5v0__dffq_1 + PLACED ( 76160 156800 ) N ;
+ - _1390_ gf180mcu_fd_sc_mcu7t5v0__dffq_1 + PLACED ( 44800 148960 ) FS ;
+ - _1391_ gf180mcu_fd_sc_mcu7t5v0__dffq_1 + PLACED ( 16800 180320 ) S ;
+ - _1392_ gf180mcu_fd_sc_mcu7t5v0__dffq_1 + PLACED ( 31360 196000 ) FS ;
+ - _1393_ gf180mcu_fd_sc_mcu7t5v0__dffq_1 + PLACED ( 64960 219520 ) N ;
+ - _1394_ gf180mcu_fd_sc_mcu7t5v0__dffq_1 + PLACED ( 16800 219520 ) N ;
+ - _1395_ gf180mcu_fd_sc_mcu7t5v0__dffq_1 + PLACED ( 16800 243040 ) FS ;
+ - _1396_ gf180mcu_fd_sc_mcu7t5v0__dffq_1 + PLACED ( 56000 250880 ) N ;
+ - _1397_ gf180mcu_fd_sc_mcu7t5v0__dffq_1 + PLACED ( 81760 266560 ) N ;
+ - _1398_ gf180mcu_fd_sc_mcu7t5v0__dffq_1 + PLACED ( 116480 258720 ) S ;
+ - _1399_ gf180mcu_fd_sc_mcu7t5v0__dffq_1 + PLACED ( 135520 266560 ) N ;
+ - _1400_ gf180mcu_fd_sc_mcu7t5v0__dffq_1 + PLACED ( 127680 305760 ) S ;
+ - _1401_ gf180mcu_fd_sc_mcu7t5v0__dffq_1 + PLACED ( 82880 282240 ) N ;
+ - _1402_ gf180mcu_fd_sc_mcu7t5v0__dffq_1 + PLACED ( 135520 329280 ) FN ;
+ - _1403_ gf180mcu_fd_sc_mcu7t5v0__dffq_1 + PLACED ( 122080 352800 ) S ;
+ - _1404_ gf180mcu_fd_sc_mcu7t5v0__dffq_1 + PLACED ( 89600 360640 ) N ;
+ - _1405_ gf180mcu_fd_sc_mcu7t5v0__dffq_1 + PLACED ( 59360 368480 ) S ;
+ - _1406_ gf180mcu_fd_sc_mcu7t5v0__dffq_1 + PLACED ( 24640 368480 ) FS ;
+ - _1407_ gf180mcu_fd_sc_mcu7t5v0__dffq_1 + PLACED ( 20160 337120 ) FS ;
+ - _1408_ gf180mcu_fd_sc_mcu7t5v0__dffq_1 + PLACED ( 16800 321440 ) FS ;
+ - _1409_ gf180mcu_fd_sc_mcu7t5v0__dffq_1 + PLACED ( 16800 297920 ) N ;
+ - _1410_ gf180mcu_fd_sc_mcu7t5v0__dffq_1 + PLACED ( 40320 274400 ) FS ;
+ - _1411_ gf180mcu_fd_sc_mcu7t5v0__dffq_1 + PLACED ( 327040 235200 ) N ;
+ - _1412_ gf180mcu_fd_sc_mcu7t5v0__dffq_1 + PLACED ( 328160 219520 ) N ;
+ - _1413_ gf180mcu_fd_sc_mcu7t5v0__dffq_1 + PLACED ( 319200 266560 ) N ;
+ - _1414_ gf180mcu_fd_sc_mcu7t5v0__dffq_1 + PLACED ( 297920 227360 ) FS ;
+ - _1415_ gf180mcu_fd_sc_mcu7t5v0__dffq_1 + PLACED ( 288960 258720 ) FS ;
+ - _1416_ gf180mcu_fd_sc_mcu7t5v0__dffq_1 + PLACED ( 334880 258720 ) FS ;
+ - _1417_ gf180mcu_fd_sc_mcu7t5v0__dffq_1 + PLACED ( 237440 297920 ) N ;
+ - _1418_ gf180mcu_fd_sc_mcu7t5v0__dffq_1 + PLACED ( 220640 282240 ) N ;
+ - _1419_ gf180mcu_fd_sc_mcu7t5v0__dffq_2 + PLACED ( 216160 258720 ) FS ;
+ - _1420_ gf180mcu_fd_sc_mcu7t5v0__dffq_2 + PLACED ( 255360 282240 ) N ;
+ - _1421_ gf180mcu_fd_sc_mcu7t5v0__dffq_1 + PLACED ( 334880 86240 ) FS ;
+ - _1422_ gf180mcu_fd_sc_mcu7t5v0__dffq_1 + PLACED ( 337120 78400 ) N ;
+ - _1423_ gf180mcu_fd_sc_mcu7t5v0__dffq_1 + PLACED ( 337120 109760 ) N ;
+ - _1424_ gf180mcu_fd_sc_mcu7t5v0__dffq_1 + PLACED ( 371840 101920 ) FS ;
+ - _1425_ gf180mcu_fd_sc_mcu7t5v0__dffq_1 + PLACED ( 361760 117600 ) FS ;
+ - _1426_ gf180mcu_fd_sc_mcu7t5v0__dffq_1 + PLACED ( 350560 133280 ) FS ;
+ - _1427_ gf180mcu_fd_sc_mcu7t5v0__dffq_1 + PLACED ( 334880 141120 ) N ;
+ - _1428_ gf180mcu_fd_sc_mcu7t5v0__dffq_1 + PLACED ( 338240 164640 ) FS ;
+ - _1429_ gf180mcu_fd_sc_mcu7t5v0__dffq_1 + PLACED ( 334880 196000 ) FS ;
+ - _1430_ gf180mcu_fd_sc_mcu7t5v0__dffq_1 + PLACED ( 341600 180320 ) FS ;
+ - _1431_ gf180mcu_fd_sc_mcu7t5v0__dffq_1 + PLACED ( 274400 164640 ) FS ;
+ - _1432_ gf180mcu_fd_sc_mcu7t5v0__dffq_1 + PLACED ( 255360 86240 ) FS ;
+ - _1433_ gf180mcu_fd_sc_mcu7t5v0__dffq_1 + PLACED ( 221760 94080 ) N ;
+ - _1434_ gf180mcu_fd_sc_mcu7t5v0__dffq_1 + PLACED ( 295680 86240 ) FS ;
+ - _1435_ gf180mcu_fd_sc_mcu7t5v0__dffq_1 + PLACED ( 253120 125440 ) N ;
+ - _1436_ gf180mcu_fd_sc_mcu7t5v0__dffq_1 + PLACED ( 200480 117600 ) FS ;
+ - _1437_ gf180mcu_fd_sc_mcu7t5v0__dffq_1 + PLACED ( 190400 133280 ) S ;
+ - _1438_ gf180mcu_fd_sc_mcu7t5v0__dffq_1 + PLACED ( 224000 156800 ) N ;
+ - _1439_ gf180mcu_fd_sc_mcu7t5v0__dffq_1 + PLACED ( 227360 188160 ) N ;
+ - _1440_ gf180mcu_fd_sc_mcu7t5v0__dffq_1 + PLACED ( 284480 196000 ) FS ;
+ - _1441_ gf180mcu_fd_sc_mcu7t5v0__dffq_1 + PLACED ( 520800 290080 ) FS ;
+ - _1442_ gf180mcu_fd_sc_mcu7t5v0__dffq_1 + PLACED ( 396480 517440 ) N ;
+ - _1443_ gf180mcu_fd_sc_mcu7t5v0__dffq_1 + PLACED ( 414400 493920 ) S ;
+ - _1444_ gf180mcu_fd_sc_mcu7t5v0__dffq_1 + PLACED ( 346080 509600 ) FS ;
+ - _1445_ gf180mcu_fd_sc_mcu7t5v0__dffq_1 + PLACED ( 322560 501760 ) N ;
+ - _1446_ gf180mcu_fd_sc_mcu7t5v0__dffq_1 + PLACED ( 309120 486080 ) N ;
+ - _1447_ gf180mcu_fd_sc_mcu7t5v0__dffq_1 + PLACED ( 374080 407680 ) N ;
+ - _1448_ gf180mcu_fd_sc_mcu7t5v0__dffq_1 + PLACED ( 408800 407680 ) FN ;
+ - _1449_ gf180mcu_fd_sc_mcu7t5v0__dffq_2 + PLACED ( 413280 439040 ) FN ;
+ - _1450_ gf180mcu_fd_sc_mcu7t5v0__dffq_1 + PLACED ( 334880 431200 ) FS ;
+ - _1451_ gf180mcu_fd_sc_mcu7t5v0__dffq_1 + PLACED ( 316960 454720 ) N ;
+ - _1452_ gf180mcu_fd_sc_mcu7t5v0__dffq_1 + PLACED ( 431200 509600 ) FS ;
+ - _1453_ gf180mcu_fd_sc_mcu7t5v0__dffq_1 + PLACED ( 432320 478240 ) FS ;
+ - _1454_ gf180mcu_fd_sc_mcu7t5v0__dffq_1 + PLACED ( 473760 517440 ) N ;
+ - _1455_ gf180mcu_fd_sc_mcu7t5v0__dffq_1 + PLACED ( 509600 509600 ) FS ;
+ - _1456_ gf180mcu_fd_sc_mcu7t5v0__dffq_1 + PLACED ( 533120 486080 ) N ;
+ - _1457_ gf180mcu_fd_sc_mcu7t5v0__dffq_2 + PLACED ( 435680 431200 ) FS ;
+ - _1458_ gf180mcu_fd_sc_mcu7t5v0__dffq_2 + PLACED ( 443520 415520 ) FS ;
+ - _1459_ gf180mcu_fd_sc_mcu7t5v0__dffq_1 + PLACED ( 499520 415520 ) S ;
+ - _1460_ gf180mcu_fd_sc_mcu7t5v0__dffq_1 + PLACED ( 524160 431200 ) FS ;
+ - _1461_ gf180mcu_fd_sc_mcu7t5v0__dffq_1 + PLACED ( 525280 462560 ) FS ;
+ - _1462_ gf180mcu_fd_sc_mcu7t5v0__dffq_1 + PLACED ( 415520 274400 ) FS ;
+ - _1463_ gf180mcu_fd_sc_mcu7t5v0__dffq_1 + PLACED ( 369600 258720 ) FS ;
+ - _1464_ gf180mcu_fd_sc_mcu7t5v0__dffq_1 + PLACED ( 386400 188160 ) N ;
+ - _1465_ gf180mcu_fd_sc_mcu7t5v0__dffq_1 + PLACED ( 377440 227360 ) FS ;
+ - _1466_ gf180mcu_fd_sc_mcu7t5v0__dffq_1 + PLACED ( 384160 250880 ) N ;
+ - _1467_ gf180mcu_fd_sc_mcu7t5v0__dffq_1 + PLACED ( 432320 290080 ) FS ;
+ - _1468_ gf180mcu_fd_sc_mcu7t5v0__dffq_1 + PLACED ( 428960 321440 ) FS ;
+ - _1469_ gf180mcu_fd_sc_mcu7t5v0__dffq_1 + PLACED ( 476000 282240 ) N ;
+ - _1470_ gf180mcu_fd_sc_mcu7t5v0__dffq_1 + PLACED ( 519680 321440 ) S ;
+ - _1471_ gf180mcu_fd_sc_mcu7t5v0__dffq_1 + PLACED ( 526400 337120 ) S ;
+ - _1472_ gf180mcu_fd_sc_mcu7t5v0__dffq_1 + PLACED ( 425600 352800 ) FS ;
+ - _1473_ gf180mcu_fd_sc_mcu7t5v0__dffq_1 + PLACED ( 470400 407680 ) FN ;
+ - _1474_ gf180mcu_fd_sc_mcu7t5v0__dffq_1 + PLACED ( 437920 384160 ) FS ;
+ - _1475_ gf180mcu_fd_sc_mcu7t5v0__dffq_1 + PLACED ( 520800 384160 ) S ;
+ - _1476_ gf180mcu_fd_sc_mcu7t5v0__dffq_1 + PLACED ( 533120 360640 ) N ;
+ - _1477_ gf180mcu_fd_sc_mcu7t5v0__dffq_1 + PLACED ( 397600 392000 ) N ;
+ - _1478_ gf180mcu_fd_sc_mcu7t5v0__dffq_1 + PLACED ( 337120 376320 ) N ;
+ - _1479_ gf180mcu_fd_sc_mcu7t5v0__dffq_2 + PLACED ( 403200 344960 ) FN ;
+ - _1480_ gf180mcu_fd_sc_mcu7t5v0__dffq_1 + PLACED ( 337120 329280 ) N ;
+ - _1481_ gf180mcu_fd_sc_mcu7t5v0__dffq_2 + PLACED ( 348320 399840 ) FS ;
+ - _1482_ gf180mcu_fd_sc_mcu7t5v0__dffq_1 + PLACED ( 297920 431200 ) FS ;
+ - _1483_ gf180mcu_fd_sc_mcu7t5v0__dffq_1 + PLACED ( 294560 392000 ) N ;
+ - _1484_ gf180mcu_fd_sc_mcu7t5v0__dffq_1 + PLACED ( 257600 415520 ) FS ;
+ - _1485_ gf180mcu_fd_sc_mcu7t5v0__dffq_1 + PLACED ( 292320 462560 ) S ;
+ - _1486_ gf180mcu_fd_sc_mcu7t5v0__dffq_1 + PLACED ( 264320 478240 ) FS ;
+ - _1487_ gf180mcu_fd_sc_mcu7t5v0__dffq_1 + PLACED ( 238560 439040 ) N ;
+ - _1488_ gf180mcu_fd_sc_mcu7t5v0__dffq_1 + PLACED ( 166880 439040 ) N ;
+ - _1489_ gf180mcu_fd_sc_mcu7t5v0__dffq_1 + PLACED ( 215040 454720 ) N ;
+ - _1490_ gf180mcu_fd_sc_mcu7t5v0__dffq_1 + PLACED ( 218400 415520 ) FS ;
+ - _1491_ gf180mcu_fd_sc_mcu7t5v0__dffq_1 + PLACED ( 201600 352800 ) S ;
+ - _1492_ gf180mcu_fd_sc_mcu7t5v0__dffq_1 + PLACED ( 145600 407680 ) N ;
+ - _1493_ gf180mcu_fd_sc_mcu7t5v0__dffq_1 + PLACED ( 219520 392000 ) N ;
+ - _1494_ gf180mcu_fd_sc_mcu7t5v0__dffq_1 + PLACED ( 148960 376320 ) N ;
+ - _1495_ gf180mcu_fd_sc_mcu7t5v0__dffq_1 + PLACED ( 255360 337120 ) FS ;
+ - _1496_ gf180mcu_fd_sc_mcu7t5v0__dffq_1 + PLACED ( 215040 344960 ) FN ;
+ - _1497_ gf180mcu_fd_sc_mcu7t5v0__dffq_1 + PLACED ( 157920 344960 ) N ;
+ - _1498_ gf180mcu_fd_sc_mcu7t5v0__dffq_1 + PLACED ( 518560 258720 ) FS ;
+ - _1499_ gf180mcu_fd_sc_mcu7t5v0__dffq_1 + PLACED ( 504000 243040 ) FS ;
+ - _1500_ gf180mcu_fd_sc_mcu7t5v0__dffq_1 + PLACED ( 453600 109760 ) N ;
+ - _1501_ gf180mcu_fd_sc_mcu7t5v0__dffq_1 + PLACED ( 417760 117600 ) FS ;
+ - _1502_ gf180mcu_fd_sc_mcu7t5v0__dffq_1 + PLACED ( 441280 133280 ) FS ;
+ - _1503_ gf180mcu_fd_sc_mcu7t5v0__dffq_1 + PLACED ( 436800 196000 ) FS ;
+ - _1504_ gf180mcu_fd_sc_mcu7t5v0__dffq_1 + PLACED ( 416640 243040 ) FS ;
+ - _1505_ gf180mcu_fd_sc_mcu7t5v0__dffq_1 + PLACED ( 443520 227360 ) FS ;
+ - _1506_ gf180mcu_fd_sc_mcu7t5v0__dffq_1 + PLACED ( 450240 274400 ) FS ;
+ - _1507_ gf180mcu_fd_sc_mcu7t5v0__dffq_1 + PLACED ( 414400 258720 ) S ;
+ - _1508_ gf180mcu_fd_sc_mcu7t5v0__dffq_1 + PLACED ( 297920 321440 ) FS ;
+ - _1509_ gf180mcu_fd_sc_mcu7t5v0__dffq_1 + PLACED ( 155680 313600 ) FN ;
+ - _1510_ gf180mcu_fd_sc_mcu7t5v0__dffq_1 + PLACED ( 238560 313600 ) FN ;
+ - _1511_ gf180mcu_fd_sc_mcu7t5v0__dffq_1 + PLACED ( 453600 250880 ) N ;
+ - _1512_ gf180mcu_fd_sc_mcu7t5v0__dffq_1 + PLACED ( 381920 297920 ) N ;
+ - _1513_ gf180mcu_fd_sc_mcu7t5v0__dffq_1 + PLACED ( 402080 313600 ) FN ;
+ - _1514_ gf180mcu_fd_sc_mcu7t5v0__dffq_1 + PLACED ( 351680 211680 ) S ;
+ - clkbuf_0_wb_clk_i gf180mcu_fd_sc_mcu7t5v0__clkbuf_16 + SOURCE TIMING + PLACED ( 294560 297920 ) N ;
+ - clkbuf_4_0_0_wb_clk_i gf180mcu_fd_sc_mcu7t5v0__clkbuf_8 + SOURCE TIMING + PLACED ( 125440 164640 ) FS ;
+ - clkbuf_4_10_0_wb_clk_i gf180mcu_fd_sc_mcu7t5v0__clkbuf_8 + SOURCE TIMING + PLACED ( 463680 203840 ) N ;
+ - clkbuf_4_11_0_wb_clk_i gf180mcu_fd_sc_mcu7t5v0__clkbuf_8 + SOURCE TIMING + PLACED ( 460320 258720 ) FS ;
+ - clkbuf_4_12_0_wb_clk_i gf180mcu_fd_sc_mcu7t5v0__clkbuf_8 + SOURCE TIMING + PLACED ( 377440 384160 ) FS ;
+ - clkbuf_4_13_0_wb_clk_i gf180mcu_fd_sc_mcu7t5v0__clkbuf_8 + SOURCE TIMING + PLACED ( 380800 415520 ) FS ;
+ - clkbuf_4_14_0_wb_clk_i gf180mcu_fd_sc_mcu7t5v0__clkbuf_8 + SOURCE TIMING + PLACED ( 472640 376320 ) N ;
+ - clkbuf_4_15_0_wb_clk_i gf180mcu_fd_sc_mcu7t5v0__clkbuf_8 + SOURCE TIMING + PLACED ( 465920 423360 ) N ;
+ - clkbuf_4_1_0_wb_clk_i gf180mcu_fd_sc_mcu7t5v0__clkbuf_8 + SOURCE TIMING + PLACED ( 123200 196000 ) S ;
+ - clkbuf_4_2_0_wb_clk_i gf180mcu_fd_sc_mcu7t5v0__clkbuf_8 + SOURCE TIMING + PLACED ( 221760 148960 ) FS ;
+ - clkbuf_4_3_0_wb_clk_i gf180mcu_fd_sc_mcu7t5v0__clkbuf_8 + SOURCE TIMING + PLACED ( 234080 203840 ) N ;
+ - clkbuf_4_4_0_wb_clk_i gf180mcu_fd_sc_mcu7t5v0__clkbuf_8 + SOURCE TIMING + PLACED ( 115360 321440 ) S ;
+ - clkbuf_4_5_0_wb_clk_i gf180mcu_fd_sc_mcu7t5v0__clkbuf_8 + SOURCE TIMING + PLACED ( 118720 337120 ) FS ;
+ - clkbuf_4_6_0_wb_clk_i gf180mcu_fd_sc_mcu7t5v0__clkbuf_8 + SOURCE TIMING + PLACED ( 217280 329280 ) N ;
+ - clkbuf_4_7_0_wb_clk_i gf180mcu_fd_sc_mcu7t5v0__clkbuf_8 + SOURCE TIMING + PLACED ( 215040 376320 ) N ;
+ - clkbuf_4_8_0_wb_clk_i gf180mcu_fd_sc_mcu7t5v0__clkbuf_8 + SOURCE TIMING + PLACED ( 393120 203840 ) N ;
+ - clkbuf_4_9_0_wb_clk_i gf180mcu_fd_sc_mcu7t5v0__clkbuf_8 + SOURCE TIMING + PLACED ( 393120 266560 ) N ;
+ - input1 gf180mcu_fd_sc_mcu7t5v0__buf_1 + SOURCE TIMING + PLACED ( 575680 141120 ) FN ;
+ - input2 gf180mcu_fd_sc_mcu7t5v0__buf_2 + SOURCE TIMING + PLACED ( 350560 556640 ) FS ;
+ - input3 gf180mcu_fd_sc_mcu7t5v0__clkbuf_2 + SOURCE TIMING + PLACED ( 390880 556640 ) FS ;
+ - input4 gf180mcu_fd_sc_mcu7t5v0__clkbuf_1 + SOURCE TIMING + PLACED ( 575680 290080 ) S ;
+ - output10 gf180mcu_fd_sc_mcu7t5v0__clkbuf_4 + SOURCE TIMING + PLACED ( 526400 31360 ) N ;
+ - output11 gf180mcu_fd_sc_mcu7t5v0__clkbuf_4 + SOURCE TIMING + PLACED ( 566720 470400 ) FN ;
+ - output12 gf180mcu_fd_sc_mcu7t5v0__clkbuf_4 + SOURCE TIMING + PLACED ( 310240 31360 ) N ;
+ - output5 gf180mcu_fd_sc_mcu7t5v0__clkbuf_4 + SOURCE TIMING + PLACED ( 16800 439040 ) FN ;
+ - output6 gf180mcu_fd_sc_mcu7t5v0__clkbuf_4 + SOURCE TIMING + PLACED ( 566720 94080 ) N ;
+ - output7 gf180mcu_fd_sc_mcu7t5v0__clkbuf_4 + SOURCE TIMING + PLACED ( 16800 313600 ) FN ;
+ - output8 gf180mcu_fd_sc_mcu7t5v0__clkbuf_4 + SOURCE TIMING + PLACED ( 16800 31360 ) FN ;
+ - output9 gf180mcu_fd_sc_mcu7t5v0__clkbuf_4 + SOURCE TIMING + PLACED ( 566720 439040 ) N ;
+ - wrapped_vga_clock_13 gf180mcu_fd_sc_mcu7t5v0__tiel + SOURCE TIMING + PLACED ( 478240 556640 ) S ;
+ - wrapped_vga_clock_14 gf180mcu_fd_sc_mcu7t5v0__tiel + SOURCE TIMING + PLACED ( 16800 290080 ) S ;
+ - wrapped_vga_clock_15 gf180mcu_fd_sc_mcu7t5v0__tiel + SOURCE TIMING + PLACED ( 577920 556640 ) S ;
+ - wrapped_vga_clock_16 gf180mcu_fd_sc_mcu7t5v0__tiel + SOURCE TIMING + PLACED ( 81760 556640 ) S ;
+ - wrapped_vga_clock_17 gf180mcu_fd_sc_mcu7t5v0__tiel + SOURCE TIMING + PLACED ( 16800 392000 ) FN ;
+ - wrapped_vga_clock_18 gf180mcu_fd_sc_mcu7t5v0__tiel + SOURCE TIMING + PLACED ( 437920 31360 ) FN ;
+ - wrapped_vga_clock_19 gf180mcu_fd_sc_mcu7t5v0__tiel + SOURCE TIMING + PLACED ( 61600 31360 ) FN ;
+ - wrapped_vga_clock_20 gf180mcu_fd_sc_mcu7t5v0__tiel + SOURCE TIMING + PLACED ( 16800 250880 ) FN ;
+ - wrapped_vga_clock_21 gf180mcu_fd_sc_mcu7t5v0__tiel + SOURCE TIMING + PLACED ( 577920 31360 ) N ;
+ - wrapped_vga_clock_22 gf180mcu_fd_sc_mcu7t5v0__tiel + SOURCE TIMING + PLACED ( 577920 352800 ) FS ;
+ - wrapped_vga_clock_23 gf180mcu_fd_sc_mcu7t5v0__tiel + SOURCE TIMING + PLACED ( 577920 548800 ) N ;
+ - wrapped_vga_clock_24 gf180mcu_fd_sc_mcu7t5v0__tiel + SOURCE TIMING + PLACED ( 577920 501760 ) N ;
+ - wrapped_vga_clock_25 gf180mcu_fd_sc_mcu7t5v0__tiel + SOURCE TIMING + PLACED ( 81760 31360 ) FN ;
+ - wrapped_vga_clock_26 gf180mcu_fd_sc_mcu7t5v0__tiel + SOURCE TIMING + PLACED ( 101920 556640 ) S ;
+ - wrapped_vga_clock_27 gf180mcu_fd_sc_mcu7t5v0__tiel + SOURCE TIMING + PLACED ( 269920 31360 ) FN ;
+ - wrapped_vga_clock_28 gf180mcu_fd_sc_mcu7t5v0__tiel + SOURCE TIMING + PLACED ( 350560 31360 ) FN ;
+ - wrapped_vga_clock_29 gf180mcu_fd_sc_mcu7t5v0__tiel + SOURCE TIMING + PLACED ( 577920 517440 ) N ;
+ - wrapped_vga_clock_30 gf180mcu_fd_sc_mcu7t5v0__tiel + SOURCE TIMING + PLACED ( 544320 31360 ) FN ;
+ - wrapped_vga_clock_31 gf180mcu_fd_sc_mcu7t5v0__tiel + SOURCE TIMING + PLACED ( 577920 392000 ) N ;
+ - wrapped_vga_clock_32 gf180mcu_fd_sc_mcu7t5v0__tiel + SOURCE TIMING + PLACED ( 252000 556640 ) S ;
+ - wrapped_vga_clock_33 gf180mcu_fd_sc_mcu7t5v0__tiel + SOURCE TIMING + PLACED ( 142240 556640 ) S ;
+ - wrapped_vga_clock_34 gf180mcu_fd_sc_mcu7t5v0__tiel + SOURCE TIMING + PLACED ( 310240 556640 ) S ;
+ - wrapped_vga_clock_35 gf180mcu_fd_sc_mcu7t5v0__tiel + SOURCE TIMING + PLACED ( 478240 31360 ) FN ;
+ - wrapped_vga_clock_36 gf180mcu_fd_sc_mcu7t5v0__tiel + SOURCE TIMING + PLACED ( 182560 31360 ) FN ;
+ - wrapped_vga_clock_37 gf180mcu_fd_sc_mcu7t5v0__tiel + SOURCE TIMING + PLACED ( 577920 164640 ) FS ;
+ - wrapped_vga_clock_38 gf180mcu_fd_sc_mcu7t5v0__tiel + SOURCE TIMING + PLACED ( 162400 556640 ) S ;
+ - wrapped_vga_clock_39 gf180mcu_fd_sc_mcu7t5v0__tiel + SOURCE TIMING + PLACED ( 577920 415520 ) FS ;
+ - wrapped_vga_clock_40 gf180mcu_fd_sc_mcu7t5v0__tiel + SOURCE TIMING + PLACED ( 41440 31360 ) FN ;
+ - wrapped_vga_clock_41 gf180mcu_fd_sc_mcu7t5v0__tiel + SOURCE TIMING + PLACED ( 565600 31360 ) FN ;
+ - wrapped_vga_clock_42 gf180mcu_fd_sc_mcu7t5v0__tiel + SOURCE TIMING + PLACED ( 577920 125440 ) N ;
+ - wrapped_vga_clock_43 gf180mcu_fd_sc_mcu7t5v0__tiel + SOURCE TIMING + PLACED ( 16800 501760 ) FN ;
+ - wrapped_vga_clock_44 gf180mcu_fd_sc_mcu7t5v0__tiel + SOURCE TIMING + PLACED ( 498400 31360 ) FN ;
+ - wrapped_vga_clock_45 gf180mcu_fd_sc_mcu7t5v0__tiel + SOURCE TIMING + PLACED ( 252000 31360 ) FN ;
+ - wrapped_vga_clock_46 gf180mcu_fd_sc_mcu7t5v0__tiel + SOURCE TIMING + PLACED ( 16800 478240 ) S ;
+ - wrapped_vga_clock_47 gf180mcu_fd_sc_mcu7t5v0__tiel + SOURCE TIMING + PLACED ( 577920 454720 ) N ;
+ - wrapped_vga_clock_48 gf180mcu_fd_sc_mcu7t5v0__tiel + SOURCE TIMING + PLACED ( 16800 266560 ) FN ;
+ - wrapped_vga_clock_49 gf180mcu_fd_sc_mcu7t5v0__tiel + SOURCE TIMING + PLACED ( 577920 39200 ) FS ;
+ - wrapped_vga_clock_50 gf180mcu_fd_sc_mcu7t5v0__tiel + SOURCE TIMING + PLACED ( 16800 548800 ) FN ;
+ - wrapped_vga_clock_51 gf180mcu_fd_sc_mcu7t5v0__tiel + SOURCE TIMING + PLACED ( 577920 227360 ) FS ;
+ - wrapped_vga_clock_52 gf180mcu_fd_sc_mcu7t5v0__tiel + SOURCE TIMING + PLACED ( 16800 227360 ) S ;
+ - wrapped_vga_clock_53 gf180mcu_fd_sc_mcu7t5v0__tiel + SOURCE TIMING + PLACED ( 291200 31360 ) FN ;
+ - wrapped_vga_clock_54 gf180mcu_fd_sc_mcu7t5v0__tiel + SOURCE TIMING + PLACED ( 330400 31360 ) FN ;
+ - wrapped_vga_clock_55 gf180mcu_fd_sc_mcu7t5v0__tiel + SOURCE TIMING + PLACED ( 16800 141120 ) FN ;
+ - wrapped_vga_clock_56 gf180mcu_fd_sc_mcu7t5v0__tiel + SOURCE TIMING + PLACED ( 458080 556640 ) S ;
+ - wrapped_vga_clock_57 gf180mcu_fd_sc_mcu7t5v0__tiel + SOURCE TIMING + PLACED ( 21280 556640 ) S ;
+ - wrapped_vga_clock_58 gf180mcu_fd_sc_mcu7t5v0__tiel + SOURCE TIMING + PLACED ( 122080 556640 ) S ;
+ - wrapped_vga_clock_59 gf180mcu_fd_sc_mcu7t5v0__tiel + SOURCE TIMING + PLACED ( 417760 31360 ) FN ;
+ - wrapped_vga_clock_60 gf180mcu_fd_sc_mcu7t5v0__tiel + SOURCE TIMING + PLACED ( 16800 164640 ) S ;
+ - wrapped_vga_clock_61 gf180mcu_fd_sc_mcu7t5v0__tiel + SOURCE TIMING + PLACED ( 458080 31360 ) FN ;
+ - wrapped_vga_clock_62 gf180mcu_fd_sc_mcu7t5v0__tiel + SOURCE TIMING + PLACED ( 16800 125440 ) FN ;
+ - wrapped_vga_clock_63 gf180mcu_fd_sc_mcu7t5v0__tiel + SOURCE TIMING + PLACED ( 31360 39200 ) S ;
+ - wrapped_vga_clock_64 gf180mcu_fd_sc_mcu7t5v0__tiel + SOURCE TIMING + PLACED ( 390880 31360 ) FN ;
+ - wrapped_vga_clock_65 gf180mcu_fd_sc_mcu7t5v0__tiel + SOURCE TIMING + PLACED ( 41440 556640 ) S ;
+ - wrapped_vga_clock_66 gf180mcu_fd_sc_mcu7t5v0__tiel + SOURCE TIMING + PLACED ( 229600 556640 ) S ;
+ - wrapped_vga_clock_67 gf180mcu_fd_sc_mcu7t5v0__tiel + SOURCE TIMING + PLACED ( 417760 556640 ) S ;
+ - wrapped_vga_clock_68 gf180mcu_fd_sc_mcu7t5v0__tiel + SOURCE TIMING + PLACED ( 16800 47040 ) FN ;
+ - wrapped_vga_clock_69 gf180mcu_fd_sc_mcu7t5v0__tiel + SOURCE TIMING + PLACED ( 101920 31360 ) FN ;
+ - wrapped_vga_clock_70 gf180mcu_fd_sc_mcu7t5v0__tiel + SOURCE TIMING + PLACED ( 34720 31360 ) FN ;
+ - wrapped_vga_clock_71 gf180mcu_fd_sc_mcu7t5v0__tiel + SOURCE TIMING + PLACED ( 498400 556640 ) S ;
+ - wrapped_vga_clock_72 gf180mcu_fd_sc_mcu7t5v0__tiel + SOURCE TIMING + PLACED ( 370720 556640 ) S ;
+ - wrapped_vga_clock_73 gf180mcu_fd_sc_mcu7t5v0__tiel + SOURCE TIMING + PLACED ( 565600 556640 ) S ;
+ - wrapped_vga_clock_74 gf180mcu_fd_sc_mcu7t5v0__tiel + SOURCE TIMING + PLACED ( 577920 78400 ) N ;
+ - wrapped_vga_clock_75 gf180mcu_fd_sc_mcu7t5v0__tiel + SOURCE TIMING + PLACED ( 28000 556640 ) S ;
+ - wrapped_vga_clock_76 gf180mcu_fd_sc_mcu7t5v0__tiel + SOURCE TIMING + PLACED ( 16800 211680 ) S ;
+ - wrapped_vga_clock_77 gf180mcu_fd_sc_mcu7t5v0__tiel + SOURCE TIMING + PLACED ( 122080 31360 ) FN ;
+ - wrapped_vga_clock_78 gf180mcu_fd_sc_mcu7t5v0__tiel + SOURCE TIMING + PLACED ( 212800 31360 ) FN ;
+ - wrapped_vga_clock_79 gf180mcu_fd_sc_mcu7t5v0__tiel + SOURCE TIMING + PLACED ( 16800 172480 ) FN ;
+ - wrapped_vga_clock_80 gf180mcu_fd_sc_mcu7t5v0__tiel + SOURCE TIMING + PLACED ( 577920 368480 ) FS ;
+END COMPONENTS
+PINS 118 ;
+ - io_in[0] + NET io_in[0] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal3 ( -3000 -1120 ) ( 3000 1120 )
+ + PLACED ( 595000 578480 ) N ;
+ - io_in[10] + NET io_in[10] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal3 ( -3000 -1120 ) ( 3000 1120 )
+ + PLACED ( 595000 141680 ) N ;
+ - io_in[11] + NET io_in[11] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -3000 ) ( 1120 3000 )
+ + PLACED ( 61040 595000 ) N ;
+ - io_in[12] + NET io_in[12] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal3 ( -3000 -1120 ) ( 3000 1120 )
+ + PLACED ( 5000 329840 ) N ;
+ - io_in[13] + NET io_in[13] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -3000 ) ( 1120 3000 )
+ + PLACED ( 538160 595000 ) N ;
+ - io_in[14] + NET io_in[14] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -3000 ) ( 1120 3000 )
+ + PLACED ( 437360 595000 ) N ;
+ - io_in[15] + NET io_in[15] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal3 ( -3000 -1120 ) ( 3000 1120 )
+ + PLACED ( 5000 370160 ) N ;
+ - io_in[16] + NET io_in[16] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal3 ( -3000 -1120 ) ( 3000 1120 )
+ + PLACED ( 5000 101360 ) N ;
+ - io_in[17] + NET io_in[17] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -3000 ) ( 1120 3000 )
+ + PLACED ( 208880 595000 ) N ;
+ - io_in[18] + NET io_in[18] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -3000 ) ( 1120 3000 )
+ + PLACED ( 161840 5000 ) N ;
+ - io_in[19] + NET io_in[19] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal3 ( -3000 -1120 ) ( 3000 1120 )
+ + PLACED ( 5000 81200 ) N ;
+ - io_in[1] + NET io_in[1] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal3 ( -3000 -1120 ) ( 3000 1120 )
+ + PLACED ( 595000 538160 ) N ;
+ - io_in[20] + NET io_in[20] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal3 ( -3000 -1120 ) ( 3000 1120 )
+ + PLACED ( 595000 20720 ) N ;
+ - io_in[21] + NET io_in[21] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -3000 ) ( 1120 3000 )
+ + PLACED ( 518000 595000 ) N ;
+ - io_in[22] + NET io_in[22] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal3 ( -3000 -1120 ) ( 3000 1120 )
+ + PLACED ( 5000 417200 ) N ;
+ - io_in[23] + NET io_in[23] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal3 ( -3000 -1120 ) ( 3000 1120 )
+ + PLACED ( 5000 538160 ) N ;
+ - io_in[24] + NET io_in[24] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal3 ( -3000 -1120 ) ( 3000 1120 )
+ + PLACED ( 595000 269360 ) N ;
+ - io_in[25] + NET io_in[25] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal3 ( -3000 -1120 ) ( 3000 1120 )
+ + PLACED ( 5000 61040 ) N ;
+ - io_in[26] + NET io_in[26] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal3 ( -3000 -1120 ) ( 3000 1120 )
+ + PLACED ( 5000 558320 ) N ;
+ - io_in[27] + NET io_in[27] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -3000 ) ( 1120 3000 )
+ + PLACED ( 289520 595000 ) N ;
+ - io_in[28] + NET io_in[28] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal3 ( -3000 -1120 ) ( 3000 1120 )
+ + PLACED ( 595000 558320 ) N ;
+ - io_in[29] + NET io_in[29] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -3000 ) ( 1120 3000 )
+ + PLACED ( 578480 5000 ) N ;
+ - io_in[2] + NET io_in[2] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal3 ( -3000 -1120 ) ( 3000 1120 )
+ + PLACED ( 595000 182000 ) N ;
+ - io_in[30] + NET io_in[30] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -3000 ) ( 1120 3000 )
+ + PLACED ( 269360 595000 ) N ;
+ - io_in[31] + NET io_in[31] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -3000 ) ( 1120 3000 )
+ + PLACED ( 370160 5000 ) N ;
+ - io_in[32] + NET io_in[32] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal3 ( -3000 -1120 ) ( 3000 1120 )
+ + PLACED ( 595000 309680 ) N ;
+ - io_in[33] + NET io_in[33] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal3 ( -3000 -1120 ) ( 3000 1120 )
+ + PLACED ( 5000 350000 ) N ;
+ - io_in[34] + NET io_in[34] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -3000 ) ( 1120 3000 )
+ + PLACED ( 141680 5000 ) N ;
+ - io_in[35] + NET io_in[35] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -3000 ) ( 1120 3000 )
+ + PLACED ( 229040 5000 ) N ;
+ - io_in[36] + NET io_in[36] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal3 ( -3000 -1120 ) ( 3000 1120 )
+ + PLACED ( 595000 61040 ) N ;
+ - io_in[37] + NET io_in[37] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal3 ( -3000 -1120 ) ( 3000 1120 )
+ + PLACED ( 5000 457520 ) N ;
+ - io_in[3] + NET io_in[3] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -3000 ) ( 1120 3000 )
+ + PLACED ( 182000 595000 ) N ;
+ - io_in[4] + NET io_in[4] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal3 ( -3000 -1120 ) ( 3000 1120 )
+ + PLACED ( 595000 208880 ) N ;
+ - io_in[5] + NET io_in[5] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal3 ( -3000 -1120 ) ( 3000 1120 )
+ + PLACED ( 595000 329840 ) N ;
+ - io_in[6] + NET io_in[6] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -3000 ) ( 1120 3000 )
+ + PLACED ( 329840 595000 ) N ;
+ - io_in[7] + NET io_in[7] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal3 ( -3000 -1120 ) ( 3000 1120 )
+ + PLACED ( 595000 249200 ) N ;
+ - io_in[8] + NET io_in[8] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -3000 ) ( 1120 3000 )
+ + PLACED ( 350000 595000 ) N ;
+ - io_in[9] + NET io_in[9] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -3000 ) ( 1120 3000 )
+ + PLACED ( 390320 595000 ) N ;
+ - io_oeb[0] + NET net13 + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -3000 ) ( 1120 3000 )
+ + PLACED ( 477680 595000 ) N ;
+ - io_oeb[10] + NET net23 + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -3000 ) ( 1120 3000 )
+ + PLACED ( 598640 595000 ) N ;
+ - io_oeb[11] + NET net24 + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal3 ( -3000 -1120 ) ( 3000 1120 )
+ + PLACED ( 595000 497840 ) N ;
+ - io_oeb[12] + NET net25 + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -3000 ) ( 1120 3000 )
+ + PLACED ( 81200 5000 ) N ;
+ - io_oeb[13] + NET net26 + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -3000 ) ( 1120 3000 )
+ + PLACED ( 101360 595000 ) N ;
+ - io_oeb[14] + NET net27 + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -3000 ) ( 1120 3000 )
+ + PLACED ( 269360 5000 ) N ;
+ - io_oeb[15] + NET net28 + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -3000 ) ( 1120 3000 )
+ + PLACED ( 350000 5000 ) N ;
+ - io_oeb[16] + NET net29 + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal3 ( -3000 -1120 ) ( 3000 1120 )
+ + PLACED ( 595000 518000 ) N ;
+ - io_oeb[17] + NET net30 + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -3000 ) ( 1120 3000 )
+ + PLACED ( 538160 5000 ) N ;
+ - io_oeb[18] + NET net31 + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal3 ( -3000 -1120 ) ( 3000 1120 )
+ + PLACED ( 595000 390320 ) N ;
+ - io_oeb[19] + NET net32 + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -3000 ) ( 1120 3000 )
+ + PLACED ( 249200 595000 ) N ;
+ - io_oeb[1] + NET net14 + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal3 ( -3000 -1120 ) ( 3000 1120 )
+ + PLACED ( 5000 289520 ) N ;
+ - io_oeb[20] + NET net33 + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -3000 ) ( 1120 3000 )
+ + PLACED ( 141680 595000 ) N ;
+ - io_oeb[21] + NET net34 + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -3000 ) ( 1120 3000 )
+ + PLACED ( 309680 595000 ) N ;
+ - io_oeb[22] + NET net35 + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -3000 ) ( 1120 3000 )
+ + PLACED ( 477680 5000 ) N ;
+ - io_oeb[23] + NET net36 + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -3000 ) ( 1120 3000 )
+ + PLACED ( 182000 5000 ) N ;
+ - io_oeb[24] + NET net37 + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal3 ( -3000 -1120 ) ( 3000 1120 )
+ + PLACED ( 595000 161840 ) N ;
+ - io_oeb[25] + NET net38 + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -3000 ) ( 1120 3000 )
+ + PLACED ( 161840 595000 ) N ;
+ - io_oeb[26] + NET net39 + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal3 ( -3000 -1120 ) ( 3000 1120 )
+ + PLACED ( 595000 417200 ) N ;
+ - io_oeb[27] + NET net40 + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -3000 ) ( 1120 3000 )
+ + PLACED ( 40880 5000 ) N ;
+ - io_oeb[28] + NET net41 + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -3000 ) ( 1120 3000 )
+ + PLACED ( 558320 5000 ) N ;
+ - io_oeb[29] + NET net42 + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal3 ( -3000 -1120 ) ( 3000 1120 )
+ + PLACED ( 595000 121520 ) N ;
+ - io_oeb[2] + NET net15 + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -3000 ) ( 1120 3000 )
+ + PLACED ( 578480 595000 ) N ;
+ - io_oeb[30] + NET net43 + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal3 ( -3000 -1120 ) ( 3000 1120 )
+ + PLACED ( 5000 497840 ) N ;
+ - io_oeb[31] + NET net44 + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -3000 ) ( 1120 3000 )
+ + PLACED ( 497840 5000 ) N ;
+ - io_oeb[32] + NET net45 + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -3000 ) ( 1120 3000 )
+ + PLACED ( 249200 5000 ) N ;
+ - io_oeb[33] + NET net46 + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal3 ( -3000 -1120 ) ( 3000 1120 )
+ + PLACED ( 5000 477680 ) N ;
+ - io_oeb[34] + NET net47 + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal3 ( -3000 -1120 ) ( 3000 1120 )
+ + PLACED ( 595000 457520 ) N ;
+ - io_oeb[35] + NET net48 + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal3 ( -3000 -1120 ) ( 3000 1120 )
+ + PLACED ( 5000 269360 ) N ;
+ - io_oeb[36] + NET net49 + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal3 ( -3000 -1120 ) ( 3000 1120 )
+ + PLACED ( 595000 40880 ) N ;
+ - io_oeb[37] + NET net50 + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal3 ( -3000 -1120 ) ( 3000 1120 )
+ + PLACED ( 5000 598640 ) N ;
+ - io_oeb[3] + NET net16 + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -3000 ) ( 1120 3000 )
+ + PLACED ( 81200 595000 ) N ;
+ - io_oeb[4] + NET net17 + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal3 ( -3000 -1120 ) ( 3000 1120 )
+ + PLACED ( 5000 390320 ) N ;
+ - io_oeb[5] + NET net18 + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -3000 ) ( 1120 3000 )
+ + PLACED ( 437360 5000 ) N ;
+ - io_oeb[6] + NET net19 + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -3000 ) ( 1120 3000 )
+ + PLACED ( 61040 5000 ) N ;
+ - io_oeb[7] + NET net20 + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal3 ( -3000 -1120 ) ( 3000 1120 )
+ + PLACED ( 5000 249200 ) N ;
+ - io_oeb[8] + NET net21 + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal3 ( -3000 -1120 ) ( 3000 1120 )
+ + PLACED ( 595000 560 ) N ;
+ - io_oeb[9] + NET net22 + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal3 ( -3000 -1120 ) ( 3000 1120 )
+ + PLACED ( 595000 350000 ) N ;
+ - io_out[0] + NET net51 + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal3 ( -3000 -1120 ) ( 3000 1120 )
+ + PLACED ( 595000 229040 ) N ;
+ - io_out[10] + NET net61 + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -3000 ) ( 1120 3000 )
+ + PLACED ( 457520 5000 ) N ;
+ - io_out[11] + NET io_out[11] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal3 ( -3000 -1120 ) ( 3000 1120 )
+ + PLACED ( 5000 437360 ) N ;
+ - io_out[12] + NET io_out[12] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal3 ( -3000 -1120 ) ( 3000 1120 )
+ + PLACED ( 595000 101360 ) N ;
+ - io_out[13] + NET io_out[13] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal3 ( -3000 -1120 ) ( 3000 1120 )
+ + PLACED ( 5000 309680 ) N ;
+ - io_out[14] + NET io_out[14] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal3 ( -3000 -1120 ) ( 3000 1120 )
+ + PLACED ( 5000 20720 ) N ;
+ - io_out[15] + NET io_out[15] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal3 ( -3000 -1120 ) ( 3000 1120 )
+ + PLACED ( 595000 437360 ) N ;
+ - io_out[16] + NET io_out[16] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -3000 ) ( 1120 3000 )
+ + PLACED ( 518000 5000 ) N ;
+ - io_out[17] + NET io_out[17] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal3 ( -3000 -1120 ) ( 3000 1120 )
+ + PLACED ( 595000 477680 ) N ;
+ - io_out[18] + NET io_out[18] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -3000 ) ( 1120 3000 )
+ + PLACED ( 309680 5000 ) N ;
+ - io_out[19] + NET net62 + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal3 ( -3000 -1120 ) ( 3000 1120 )
+ + PLACED ( 5000 121520 ) N ;
+ - io_out[1] + NET net52 + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal3 ( -3000 -1120 ) ( 3000 1120 )
+ + PLACED ( 5000 229040 ) N ;
+ - io_out[20] + NET net63 + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -3000 ) ( 1120 3000 )
+ + PLACED ( 560 5000 ) N ;
+ - io_out[21] + NET net64 + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -3000 ) ( 1120 3000 )
+ + PLACED ( 390320 5000 ) N ;
+ - io_out[22] + NET net65 + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -3000 ) ( 1120 3000 )
+ + PLACED ( 40880 595000 ) N ;
+ - io_out[23] + NET net66 + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -3000 ) ( 1120 3000 )
+ + PLACED ( 229040 595000 ) N ;
+ - io_out[24] + NET net67 + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -3000 ) ( 1120 3000 )
+ + PLACED ( 417200 595000 ) N ;
+ - io_out[25] + NET net68 + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal3 ( -3000 -1120 ) ( 3000 1120 )
+ + PLACED ( 5000 40880 ) N ;
+ - io_out[26] + NET net69 + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -3000 ) ( 1120 3000 )
+ + PLACED ( 101360 5000 ) N ;
+ - io_out[27] + NET net70 + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -3000 ) ( 1120 3000 )
+ + PLACED ( 20720 5000 ) N ;
+ - io_out[28] + NET net71 + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -3000 ) ( 1120 3000 )
+ + PLACED ( 497840 595000 ) N ;
+ - io_out[29] + NET net72 + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -3000 ) ( 1120 3000 )
+ + PLACED ( 370160 595000 ) N ;
+ - io_out[2] + NET net53 + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -3000 ) ( 1120 3000 )
+ + PLACED ( 289520 5000 ) N ;
+ - io_out[30] + NET net73 + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -3000 ) ( 1120 3000 )
+ + PLACED ( 558320 595000 ) N ;
+ - io_out[31] + NET net74 + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal3 ( -3000 -1120 ) ( 3000 1120 )
+ + PLACED ( 595000 81200 ) N ;
+ - io_out[32] + NET net75 + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal3 ( -3000 -1120 ) ( 3000 1120 )
+ + PLACED ( 5000 578480 ) N ;
+ - io_out[33] + NET net76 + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal3 ( -3000 -1120 ) ( 3000 1120 )
+ + PLACED ( 5000 208880 ) N ;
+ - io_out[34] + NET net77 + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -3000 ) ( 1120 3000 )
+ + PLACED ( 121520 5000 ) N ;
+ - io_out[35] + NET net78 + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -3000 ) ( 1120 3000 )
+ + PLACED ( 208880 5000 ) N ;
+ - io_out[36] + NET net79 + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal3 ( -3000 -1120 ) ( 3000 1120 )
+ + PLACED ( 5000 182000 ) N ;
+ - io_out[37] + NET net80 + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal3 ( -3000 -1120 ) ( 3000 1120 )
+ + PLACED ( 595000 370160 ) N ;
+ - io_out[3] + NET net54 + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -3000 ) ( 1120 3000 )
+ + PLACED ( 329840 5000 ) N ;
+ - io_out[4] + NET net55 + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal3 ( -3000 -1120 ) ( 3000 1120 )
+ + PLACED ( 5000 141680 ) N ;
+ - io_out[5] + NET net56 + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -3000 ) ( 1120 3000 )
+ + PLACED ( 457520 595000 ) N ;
+ - io_out[6] + NET net57 + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -3000 ) ( 1120 3000 )
+ + PLACED ( 20720 595000 ) N ;
+ - io_out[7] + NET net58 + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -3000 ) ( 1120 3000 )
+ + PLACED ( 121520 595000 ) N ;
+ - io_out[8] + NET net59 + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal2 ( -1120 -3000 ) ( 1120 3000 )
+ + PLACED ( 417200 5000 ) N ;
+ - io_out[9] + NET net60 + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal3 ( -3000 -1120 ) ( 3000 1120 )
+ + PLACED ( 5000 161840 ) N ;
+ - vdd + NET vdd + SPECIAL + DIRECTION INOUT + USE POWER
+ + PORT
+ + LAYER Metal4 ( -1600 -267160 ) ( 1600 267160 )
+ + LAYER Metal4 ( -308800 -267160 ) ( -305600 267160 )
+ + FIXED ( 353280 297920 ) N ;
+ - vss + NET vss + SPECIAL + DIRECTION INOUT + USE GROUND
+ + PORT
+ + LAYER Metal4 ( -1600 -267160 ) ( 1600 267160 )
+ + LAYER Metal4 ( -308800 -267160 ) ( -305600 267160 )
+ + FIXED ( 506880 297920 ) N ;
+ - wb_clk_i + NET wb_clk_i + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal3 ( -3000 -1120 ) ( 3000 1120 )
+ + PLACED ( 5000 518000 ) N ;
+ - wb_rst_i + NET wb_rst_i + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER Metal3 ( -3000 -1120 ) ( 3000 1120 )
+ + PLACED ( 595000 289520 ) N ;
+END PINS
+SPECIALNETS 2 ;
+ - vdd ( PIN vdd ) ( * VDD ) + USE POWER
+ + ROUTED Metal1 1200 + SHAPE FOLLOWPIN ( 13440 556640 ) ( 585760 556640 )
+ NEW Metal1 1200 + SHAPE FOLLOWPIN ( 13440 540960 ) ( 585760 540960 )
+ NEW Metal1 1200 + SHAPE FOLLOWPIN ( 13440 525280 ) ( 585760 525280 )
+ NEW Metal1 1200 + SHAPE FOLLOWPIN ( 13440 509600 ) ( 585760 509600 )
+ NEW Metal1 1200 + SHAPE FOLLOWPIN ( 13440 493920 ) ( 585760 493920 )
+ NEW Metal1 1200 + SHAPE FOLLOWPIN ( 13440 478240 ) ( 585760 478240 )
+ NEW Metal1 1200 + SHAPE FOLLOWPIN ( 13440 462560 ) ( 585760 462560 )
+ NEW Metal1 1200 + SHAPE FOLLOWPIN ( 13440 446880 ) ( 585760 446880 )
+ NEW Metal1 1200 + SHAPE FOLLOWPIN ( 13440 431200 ) ( 585760 431200 )
+ NEW Metal1 1200 + SHAPE FOLLOWPIN ( 13440 415520 ) ( 585760 415520 )
+ NEW Metal1 1200 + SHAPE FOLLOWPIN ( 13440 399840 ) ( 585760 399840 )
+ NEW Metal1 1200 + SHAPE FOLLOWPIN ( 13440 384160 ) ( 585760 384160 )
+ NEW Metal1 1200 + SHAPE FOLLOWPIN ( 13440 368480 ) ( 585760 368480 )
+ NEW Metal1 1200 + SHAPE FOLLOWPIN ( 13440 352800 ) ( 585760 352800 )
+ NEW Metal1 1200 + SHAPE FOLLOWPIN ( 13440 337120 ) ( 585760 337120 )
+ NEW Metal1 1200 + SHAPE FOLLOWPIN ( 13440 321440 ) ( 585760 321440 )
+ NEW Metal1 1200 + SHAPE FOLLOWPIN ( 13440 305760 ) ( 585760 305760 )
+ NEW Metal1 1200 + SHAPE FOLLOWPIN ( 13440 290080 ) ( 585760 290080 )
+ NEW Metal1 1200 + SHAPE FOLLOWPIN ( 13440 274400 ) ( 585760 274400 )
+ NEW Metal1 1200 + SHAPE FOLLOWPIN ( 13440 258720 ) ( 585760 258720 )
+ NEW Metal1 1200 + SHAPE FOLLOWPIN ( 13440 243040 ) ( 585760 243040 )
+ NEW Metal1 1200 + SHAPE FOLLOWPIN ( 13440 227360 ) ( 585760 227360 )
+ NEW Metal1 1200 + SHAPE FOLLOWPIN ( 13440 211680 ) ( 585760 211680 )
+ NEW Metal1 1200 + SHAPE FOLLOWPIN ( 13440 196000 ) ( 585760 196000 )
+ NEW Metal1 1200 + SHAPE FOLLOWPIN ( 13440 180320 ) ( 585760 180320 )
+ NEW Metal1 1200 + SHAPE FOLLOWPIN ( 13440 164640 ) ( 585760 164640 )
+ NEW Metal1 1200 + SHAPE FOLLOWPIN ( 13440 148960 ) ( 585760 148960 )
+ NEW Metal1 1200 + SHAPE FOLLOWPIN ( 13440 133280 ) ( 585760 133280 )
+ NEW Metal1 1200 + SHAPE FOLLOWPIN ( 13440 117600 ) ( 585760 117600 )
+ NEW Metal1 1200 + SHAPE FOLLOWPIN ( 13440 101920 ) ( 585760 101920 )
+ NEW Metal1 1200 + SHAPE FOLLOWPIN ( 13440 86240 ) ( 585760 86240 )
+ NEW Metal1 1200 + SHAPE FOLLOWPIN ( 13440 70560 ) ( 585760 70560 )
+ NEW Metal1 1200 + SHAPE FOLLOWPIN ( 13440 54880 ) ( 585760 54880 )
+ NEW Metal1 1200 + SHAPE FOLLOWPIN ( 13440 39200 ) ( 585760 39200 )
+ NEW Metal4 3200 + SHAPE STRIPE ( 353280 30760 ) ( 353280 565080 )
+ NEW Metal4 3200 + SHAPE STRIPE ( 46080 30760 ) ( 46080 565080 )
+ NEW Metal3 0 + SHAPE STRIPE ( 353280 556640 ) via3_4_3200_1200_1_3_1040_1040
+ NEW Metal2 0 + SHAPE STRIPE ( 353280 556640 ) via2_3_3200_1200_1_3_1040_1040
+ NEW Metal1 0 + SHAPE STRIPE ( 353280 556640 ) via1_2_3200_1200_1_3_1040_1040
+ NEW Metal3 0 + SHAPE STRIPE ( 353280 540960 ) via3_4_3200_1200_1_3_1040_1040
+ NEW Metal2 0 + SHAPE STRIPE ( 353280 540960 ) via2_3_3200_1200_1_3_1040_1040
+ NEW Metal1 0 + SHAPE STRIPE ( 353280 540960 ) via1_2_3200_1200_1_3_1040_1040
+ NEW Metal3 0 + SHAPE STRIPE ( 353280 525280 ) via3_4_3200_1200_1_3_1040_1040
+ NEW Metal2 0 + SHAPE STRIPE ( 353280 525280 ) via2_3_3200_1200_1_3_1040_1040
+ NEW Metal1 0 + SHAPE STRIPE ( 353280 525280 ) via1_2_3200_1200_1_3_1040_1040
+ NEW Metal3 0 + SHAPE STRIPE ( 353280 509600 ) via3_4_3200_1200_1_3_1040_1040
+ NEW Metal2 0 + SHAPE STRIPE ( 353280 509600 ) via2_3_3200_1200_1_3_1040_1040
+ NEW Metal1 0 + SHAPE STRIPE ( 353280 509600 ) via1_2_3200_1200_1_3_1040_1040
+ NEW Metal3 0 + SHAPE STRIPE ( 353280 493920 ) via3_4_3200_1200_1_3_1040_1040
+ NEW Metal2 0 + SHAPE STRIPE ( 353280 493920 ) via2_3_3200_1200_1_3_1040_1040
+ NEW Metal1 0 + SHAPE STRIPE ( 353280 493920 ) via1_2_3200_1200_1_3_1040_1040
+ NEW Metal3 0 + SHAPE STRIPE ( 353280 478240 ) via3_4_3200_1200_1_3_1040_1040
+ NEW Metal2 0 + SHAPE STRIPE ( 353280 478240 ) via2_3_3200_1200_1_3_1040_1040
+ NEW Metal1 0 + SHAPE STRIPE ( 353280 478240 ) via1_2_3200_1200_1_3_1040_1040
+ NEW Metal3 0 + SHAPE STRIPE ( 353280 462560 ) via3_4_3200_1200_1_3_1040_1040
+ NEW Metal2 0 + SHAPE STRIPE ( 353280 462560 ) via2_3_3200_1200_1_3_1040_1040
+ NEW Metal1 0 + SHAPE STRIPE ( 353280 462560 ) via1_2_3200_1200_1_3_1040_1040
+ NEW Metal3 0 + SHAPE STRIPE ( 353280 446880 ) via3_4_3200_1200_1_3_1040_1040
+ NEW Metal2 0 + SHAPE STRIPE ( 353280 446880 ) via2_3_3200_1200_1_3_1040_1040
+ NEW Metal1 0 + SHAPE STRIPE ( 353280 446880 ) via1_2_3200_1200_1_3_1040_1040
+ NEW Metal3 0 + SHAPE STRIPE ( 353280 431200 ) via3_4_3200_1200_1_3_1040_1040
+ NEW Metal2 0 + SHAPE STRIPE ( 353280 431200 ) via2_3_3200_1200_1_3_1040_1040
+ NEW Metal1 0 + SHAPE STRIPE ( 353280 431200 ) via1_2_3200_1200_1_3_1040_1040
+ NEW Metal3 0 + SHAPE STRIPE ( 353280 415520 ) via3_4_3200_1200_1_3_1040_1040
+ NEW Metal2 0 + SHAPE STRIPE ( 353280 415520 ) via2_3_3200_1200_1_3_1040_1040
+ NEW Metal1 0 + SHAPE STRIPE ( 353280 415520 ) via1_2_3200_1200_1_3_1040_1040
+ NEW Metal3 0 + SHAPE STRIPE ( 353280 399840 ) via3_4_3200_1200_1_3_1040_1040
+ NEW Metal2 0 + SHAPE STRIPE ( 353280 399840 ) via2_3_3200_1200_1_3_1040_1040
+ NEW Metal1 0 + SHAPE STRIPE ( 353280 399840 ) via1_2_3200_1200_1_3_1040_1040
+ NEW Metal3 0 + SHAPE STRIPE ( 353280 384160 ) via3_4_3200_1200_1_3_1040_1040
+ NEW Metal2 0 + SHAPE STRIPE ( 353280 384160 ) via2_3_3200_1200_1_3_1040_1040
+ NEW Metal1 0 + SHAPE STRIPE ( 353280 384160 ) via1_2_3200_1200_1_3_1040_1040
+ NEW Metal3 0 + SHAPE STRIPE ( 353280 368480 ) via3_4_3200_1200_1_3_1040_1040
+ NEW Metal2 0 + SHAPE STRIPE ( 353280 368480 ) via2_3_3200_1200_1_3_1040_1040
+ NEW Metal1 0 + SHAPE STRIPE ( 353280 368480 ) via1_2_3200_1200_1_3_1040_1040
+ NEW Metal3 0 + SHAPE STRIPE ( 353280 352800 ) via3_4_3200_1200_1_3_1040_1040
+ NEW Metal2 0 + SHAPE STRIPE ( 353280 352800 ) via2_3_3200_1200_1_3_1040_1040
+ NEW Metal1 0 + SHAPE STRIPE ( 353280 352800 ) via1_2_3200_1200_1_3_1040_1040
+ NEW Metal3 0 + SHAPE STRIPE ( 353280 337120 ) via3_4_3200_1200_1_3_1040_1040
+ NEW Metal2 0 + SHAPE STRIPE ( 353280 337120 ) via2_3_3200_1200_1_3_1040_1040
+ NEW Metal1 0 + SHAPE STRIPE ( 353280 337120 ) via1_2_3200_1200_1_3_1040_1040
+ NEW Metal3 0 + SHAPE STRIPE ( 353280 321440 ) via3_4_3200_1200_1_3_1040_1040
+ NEW Metal2 0 + SHAPE STRIPE ( 353280 321440 ) via2_3_3200_1200_1_3_1040_1040
+ NEW Metal1 0 + SHAPE STRIPE ( 353280 321440 ) via1_2_3200_1200_1_3_1040_1040
+ NEW Metal3 0 + SHAPE STRIPE ( 353280 305760 ) via3_4_3200_1200_1_3_1040_1040
+ NEW Metal2 0 + SHAPE STRIPE ( 353280 305760 ) via2_3_3200_1200_1_3_1040_1040
+ NEW Metal1 0 + SHAPE STRIPE ( 353280 305760 ) via1_2_3200_1200_1_3_1040_1040
+ NEW Metal3 0 + SHAPE STRIPE ( 353280 290080 ) via3_4_3200_1200_1_3_1040_1040
+ NEW Metal2 0 + SHAPE STRIPE ( 353280 290080 ) via2_3_3200_1200_1_3_1040_1040
+ NEW Metal1 0 + SHAPE STRIPE ( 353280 290080 ) via1_2_3200_1200_1_3_1040_1040
+ NEW Metal3 0 + SHAPE STRIPE ( 353280 274400 ) via3_4_3200_1200_1_3_1040_1040
+ NEW Metal2 0 + SHAPE STRIPE ( 353280 274400 ) via2_3_3200_1200_1_3_1040_1040
+ NEW Metal1 0 + SHAPE STRIPE ( 353280 274400 ) via1_2_3200_1200_1_3_1040_1040
+ NEW Metal3 0 + SHAPE STRIPE ( 353280 258720 ) via3_4_3200_1200_1_3_1040_1040
+ NEW Metal2 0 + SHAPE STRIPE ( 353280 258720 ) via2_3_3200_1200_1_3_1040_1040
+ NEW Metal1 0 + SHAPE STRIPE ( 353280 258720 ) via1_2_3200_1200_1_3_1040_1040
+ NEW Metal3 0 + SHAPE STRIPE ( 353280 243040 ) via3_4_3200_1200_1_3_1040_1040
+ NEW Metal2 0 + SHAPE STRIPE ( 353280 243040 ) via2_3_3200_1200_1_3_1040_1040
+ NEW Metal1 0 + SHAPE STRIPE ( 353280 243040 ) via1_2_3200_1200_1_3_1040_1040
+ NEW Metal3 0 + SHAPE STRIPE ( 353280 227360 ) via3_4_3200_1200_1_3_1040_1040
+ NEW Metal2 0 + SHAPE STRIPE ( 353280 227360 ) via2_3_3200_1200_1_3_1040_1040
+ NEW Metal1 0 + SHAPE STRIPE ( 353280 227360 ) via1_2_3200_1200_1_3_1040_1040
+ NEW Metal3 0 + SHAPE STRIPE ( 353280 211680 ) via3_4_3200_1200_1_3_1040_1040
+ NEW Metal2 0 + SHAPE STRIPE ( 353280 211680 ) via2_3_3200_1200_1_3_1040_1040
+ NEW Metal1 0 + SHAPE STRIPE ( 353280 211680 ) via1_2_3200_1200_1_3_1040_1040
+ NEW Metal3 0 + SHAPE STRIPE ( 353280 196000 ) via3_4_3200_1200_1_3_1040_1040
+ NEW Metal2 0 + SHAPE STRIPE ( 353280 196000 ) via2_3_3200_1200_1_3_1040_1040
+ NEW Metal1 0 + SHAPE STRIPE ( 353280 196000 ) via1_2_3200_1200_1_3_1040_1040
+ NEW Metal3 0 + SHAPE STRIPE ( 353280 180320 ) via3_4_3200_1200_1_3_1040_1040
+ NEW Metal2 0 + SHAPE STRIPE ( 353280 180320 ) via2_3_3200_1200_1_3_1040_1040
+ NEW Metal1 0 + SHAPE STRIPE ( 353280 180320 ) via1_2_3200_1200_1_3_1040_1040
+ NEW Metal3 0 + SHAPE STRIPE ( 353280 164640 ) via3_4_3200_1200_1_3_1040_1040
+ NEW Metal2 0 + SHAPE STRIPE ( 353280 164640 ) via2_3_3200_1200_1_3_1040_1040
+ NEW Metal1 0 + SHAPE STRIPE ( 353280 164640 ) via1_2_3200_1200_1_3_1040_1040
+ NEW Metal3 0 + SHAPE STRIPE ( 353280 148960 ) via3_4_3200_1200_1_3_1040_1040
+ NEW Metal2 0 + SHAPE STRIPE ( 353280 148960 ) via2_3_3200_1200_1_3_1040_1040
+ NEW Metal1 0 + SHAPE STRIPE ( 353280 148960 ) via1_2_3200_1200_1_3_1040_1040
+ NEW Metal3 0 + SHAPE STRIPE ( 353280 133280 ) via3_4_3200_1200_1_3_1040_1040
+ NEW Metal2 0 + SHAPE STRIPE ( 353280 133280 ) via2_3_3200_1200_1_3_1040_1040
+ NEW Metal1 0 + SHAPE STRIPE ( 353280 133280 ) via1_2_3200_1200_1_3_1040_1040
+ NEW Metal3 0 + SHAPE STRIPE ( 353280 117600 ) via3_4_3200_1200_1_3_1040_1040
+ NEW Metal2 0 + SHAPE STRIPE ( 353280 117600 ) via2_3_3200_1200_1_3_1040_1040
+ NEW Metal1 0 + SHAPE STRIPE ( 353280 117600 ) via1_2_3200_1200_1_3_1040_1040
+ NEW Metal3 0 + SHAPE STRIPE ( 353280 101920 ) via3_4_3200_1200_1_3_1040_1040
+ NEW Metal2 0 + SHAPE STRIPE ( 353280 101920 ) via2_3_3200_1200_1_3_1040_1040
+ NEW Metal1 0 + SHAPE STRIPE ( 353280 101920 ) via1_2_3200_1200_1_3_1040_1040
+ NEW Metal3 0 + SHAPE STRIPE ( 353280 86240 ) via3_4_3200_1200_1_3_1040_1040
+ NEW Metal2 0 + SHAPE STRIPE ( 353280 86240 ) via2_3_3200_1200_1_3_1040_1040
+ NEW Metal1 0 + SHAPE STRIPE ( 353280 86240 ) via1_2_3200_1200_1_3_1040_1040
+ NEW Metal3 0 + SHAPE STRIPE ( 353280 70560 ) via3_4_3200_1200_1_3_1040_1040
+ NEW Metal2 0 + SHAPE STRIPE ( 353280 70560 ) via2_3_3200_1200_1_3_1040_1040
+ NEW Metal1 0 + SHAPE STRIPE ( 353280 70560 ) via1_2_3200_1200_1_3_1040_1040
+ NEW Metal3 0 + SHAPE STRIPE ( 353280 54880 ) via3_4_3200_1200_1_3_1040_1040
+ NEW Metal2 0 + SHAPE STRIPE ( 353280 54880 ) via2_3_3200_1200_1_3_1040_1040
+ NEW Metal1 0 + SHAPE STRIPE ( 353280 54880 ) via1_2_3200_1200_1_3_1040_1040
+ NEW Metal3 0 + SHAPE STRIPE ( 353280 39200 ) via3_4_3200_1200_1_3_1040_1040
+ NEW Metal2 0 + SHAPE STRIPE ( 353280 39200 ) via2_3_3200_1200_1_3_1040_1040
+ NEW Metal1 0 + SHAPE STRIPE ( 353280 39200 ) via1_2_3200_1200_1_3_1040_1040
+ NEW Metal3 0 + SHAPE STRIPE ( 46080 556640 ) via3_4_3200_1200_1_3_1040_1040
+ NEW Metal2 0 + SHAPE STRIPE ( 46080 556640 ) via2_3_3200_1200_1_3_1040_1040
+ NEW Metal1 0 + SHAPE STRIPE ( 46080 556640 ) via1_2_3200_1200_1_3_1040_1040
+ NEW Metal3 0 + SHAPE STRIPE ( 46080 540960 ) via3_4_3200_1200_1_3_1040_1040
+ NEW Metal2 0 + SHAPE STRIPE ( 46080 540960 ) via2_3_3200_1200_1_3_1040_1040
+ NEW Metal1 0 + SHAPE STRIPE ( 46080 540960 ) via1_2_3200_1200_1_3_1040_1040
+ NEW Metal3 0 + SHAPE STRIPE ( 46080 525280 ) via3_4_3200_1200_1_3_1040_1040
+ NEW Metal2 0 + SHAPE STRIPE ( 46080 525280 ) via2_3_3200_1200_1_3_1040_1040
+ NEW Metal1 0 + SHAPE STRIPE ( 46080 525280 ) via1_2_3200_1200_1_3_1040_1040
+ NEW Metal3 0 + SHAPE STRIPE ( 46080 509600 ) via3_4_3200_1200_1_3_1040_1040
+ NEW Metal2 0 + SHAPE STRIPE ( 46080 509600 ) via2_3_3200_1200_1_3_1040_1040
+ NEW Metal1 0 + SHAPE STRIPE ( 46080 509600 ) via1_2_3200_1200_1_3_1040_1040
+ NEW Metal3 0 + SHAPE STRIPE ( 46080 493920 ) via3_4_3200_1200_1_3_1040_1040
+ NEW Metal2 0 + SHAPE STRIPE ( 46080 493920 ) via2_3_3200_1200_1_3_1040_1040
+ NEW Metal1 0 + SHAPE STRIPE ( 46080 493920 ) via1_2_3200_1200_1_3_1040_1040
+ NEW Metal3 0 + SHAPE STRIPE ( 46080 478240 ) via3_4_3200_1200_1_3_1040_1040
+ NEW Metal2 0 + SHAPE STRIPE ( 46080 478240 ) via2_3_3200_1200_1_3_1040_1040
+ NEW Metal1 0 + SHAPE STRIPE ( 46080 478240 ) via1_2_3200_1200_1_3_1040_1040
+ NEW Metal3 0 + SHAPE STRIPE ( 46080 462560 ) via3_4_3200_1200_1_3_1040_1040
+ NEW Metal2 0 + SHAPE STRIPE ( 46080 462560 ) via2_3_3200_1200_1_3_1040_1040
+ NEW Metal1 0 + SHAPE STRIPE ( 46080 462560 ) via1_2_3200_1200_1_3_1040_1040
+ NEW Metal3 0 + SHAPE STRIPE ( 46080 446880 ) via3_4_3200_1200_1_3_1040_1040
+ NEW Metal2 0 + SHAPE STRIPE ( 46080 446880 ) via2_3_3200_1200_1_3_1040_1040
+ NEW Metal1 0 + SHAPE STRIPE ( 46080 446880 ) via1_2_3200_1200_1_3_1040_1040
+ NEW Metal3 0 + SHAPE STRIPE ( 46080 431200 ) via3_4_3200_1200_1_3_1040_1040
+ NEW Metal2 0 + SHAPE STRIPE ( 46080 431200 ) via2_3_3200_1200_1_3_1040_1040
+ NEW Metal1 0 + SHAPE STRIPE ( 46080 431200 ) via1_2_3200_1200_1_3_1040_1040
+ NEW Metal3 0 + SHAPE STRIPE ( 46080 415520 ) via3_4_3200_1200_1_3_1040_1040
+ NEW Metal2 0 + SHAPE STRIPE ( 46080 415520 ) via2_3_3200_1200_1_3_1040_1040
+ NEW Metal1 0 + SHAPE STRIPE ( 46080 415520 ) via1_2_3200_1200_1_3_1040_1040
+ NEW Metal3 0 + SHAPE STRIPE ( 46080 399840 ) via3_4_3200_1200_1_3_1040_1040
+ NEW Metal2 0 + SHAPE STRIPE ( 46080 399840 ) via2_3_3200_1200_1_3_1040_1040
+ NEW Metal1 0 + SHAPE STRIPE ( 46080 399840 ) via1_2_3200_1200_1_3_1040_1040
+ NEW Metal3 0 + SHAPE STRIPE ( 46080 384160 ) via3_4_3200_1200_1_3_1040_1040
+ NEW Metal2 0 + SHAPE STRIPE ( 46080 384160 ) via2_3_3200_1200_1_3_1040_1040
+ NEW Metal1 0 + SHAPE STRIPE ( 46080 384160 ) via1_2_3200_1200_1_3_1040_1040
+ NEW Metal3 0 + SHAPE STRIPE ( 46080 368480 ) via3_4_3200_1200_1_3_1040_1040
+ NEW Metal2 0 + SHAPE STRIPE ( 46080 368480 ) via2_3_3200_1200_1_3_1040_1040
+ NEW Metal1 0 + SHAPE STRIPE ( 46080 368480 ) via1_2_3200_1200_1_3_1040_1040
+ NEW Metal3 0 + SHAPE STRIPE ( 46080 352800 ) via3_4_3200_1200_1_3_1040_1040
+ NEW Metal2 0 + SHAPE STRIPE ( 46080 352800 ) via2_3_3200_1200_1_3_1040_1040
+ NEW Metal1 0 + SHAPE STRIPE ( 46080 352800 ) via1_2_3200_1200_1_3_1040_1040
+ NEW Metal3 0 + SHAPE STRIPE ( 46080 337120 ) via3_4_3200_1200_1_3_1040_1040
+ NEW Metal2 0 + SHAPE STRIPE ( 46080 337120 ) via2_3_3200_1200_1_3_1040_1040
+ NEW Metal1 0 + SHAPE STRIPE ( 46080 337120 ) via1_2_3200_1200_1_3_1040_1040
+ NEW Metal3 0 + SHAPE STRIPE ( 46080 321440 ) via3_4_3200_1200_1_3_1040_1040
+ NEW Metal2 0 + SHAPE STRIPE ( 46080 321440 ) via2_3_3200_1200_1_3_1040_1040
+ NEW Metal1 0 + SHAPE STRIPE ( 46080 321440 ) via1_2_3200_1200_1_3_1040_1040
+ NEW Metal3 0 + SHAPE STRIPE ( 46080 305760 ) via3_4_3200_1200_1_3_1040_1040
+ NEW Metal2 0 + SHAPE STRIPE ( 46080 305760 ) via2_3_3200_1200_1_3_1040_1040
+ NEW Metal1 0 + SHAPE STRIPE ( 46080 305760 ) via1_2_3200_1200_1_3_1040_1040
+ NEW Metal3 0 + SHAPE STRIPE ( 46080 290080 ) via3_4_3200_1200_1_3_1040_1040
+ NEW Metal2 0 + SHAPE STRIPE ( 46080 290080 ) via2_3_3200_1200_1_3_1040_1040
+ NEW Metal1 0 + SHAPE STRIPE ( 46080 290080 ) via1_2_3200_1200_1_3_1040_1040
+ NEW Metal3 0 + SHAPE STRIPE ( 46080 274400 ) via3_4_3200_1200_1_3_1040_1040
+ NEW Metal2 0 + SHAPE STRIPE ( 46080 274400 ) via2_3_3200_1200_1_3_1040_1040
+ NEW Metal1 0 + SHAPE STRIPE ( 46080 274400 ) via1_2_3200_1200_1_3_1040_1040
+ NEW Metal3 0 + SHAPE STRIPE ( 46080 258720 ) via3_4_3200_1200_1_3_1040_1040
+ NEW Metal2 0 + SHAPE STRIPE ( 46080 258720 ) via2_3_3200_1200_1_3_1040_1040
+ NEW Metal1 0 + SHAPE STRIPE ( 46080 258720 ) via1_2_3200_1200_1_3_1040_1040
+ NEW Metal3 0 + SHAPE STRIPE ( 46080 243040 ) via3_4_3200_1200_1_3_1040_1040
+ NEW Metal2 0 + SHAPE STRIPE ( 46080 243040 ) via2_3_3200_1200_1_3_1040_1040
+ NEW Metal1 0 + SHAPE STRIPE ( 46080 243040 ) via1_2_3200_1200_1_3_1040_1040
+ NEW Metal3 0 + SHAPE STRIPE ( 46080 227360 ) via3_4_3200_1200_1_3_1040_1040
+ NEW Metal2 0 + SHAPE STRIPE ( 46080 227360 ) via2_3_3200_1200_1_3_1040_1040
+ NEW Metal1 0 + SHAPE STRIPE ( 46080 227360 ) via1_2_3200_1200_1_3_1040_1040
+ NEW Metal3 0 + SHAPE STRIPE ( 46080 211680 ) via3_4_3200_1200_1_3_1040_1040
+ NEW Metal2 0 + SHAPE STRIPE ( 46080 211680 ) via2_3_3200_1200_1_3_1040_1040
+ NEW Metal1 0 + SHAPE STRIPE ( 46080 211680 ) via1_2_3200_1200_1_3_1040_1040
+ NEW Metal3 0 + SHAPE STRIPE ( 46080 196000 ) via3_4_3200_1200_1_3_1040_1040
+ NEW Metal2 0 + SHAPE STRIPE ( 46080 196000 ) via2_3_3200_1200_1_3_1040_1040
+ NEW Metal1 0 + SHAPE STRIPE ( 46080 196000 ) via1_2_3200_1200_1_3_1040_1040
+ NEW Metal3 0 + SHAPE STRIPE ( 46080 180320 ) via3_4_3200_1200_1_3_1040_1040
+ NEW Metal2 0 + SHAPE STRIPE ( 46080 180320 ) via2_3_3200_1200_1_3_1040_1040
+ NEW Metal1 0 + SHAPE STRIPE ( 46080 180320 ) via1_2_3200_1200_1_3_1040_1040
+ NEW Metal3 0 + SHAPE STRIPE ( 46080 164640 ) via3_4_3200_1200_1_3_1040_1040
+ NEW Metal2 0 + SHAPE STRIPE ( 46080 164640 ) via2_3_3200_1200_1_3_1040_1040
+ NEW Metal1 0 + SHAPE STRIPE ( 46080 164640 ) via1_2_3200_1200_1_3_1040_1040
+ NEW Metal3 0 + SHAPE STRIPE ( 46080 148960 ) via3_4_3200_1200_1_3_1040_1040
+ NEW Metal2 0 + SHAPE STRIPE ( 46080 148960 ) via2_3_3200_1200_1_3_1040_1040
+ NEW Metal1 0 + SHAPE STRIPE ( 46080 148960 ) via1_2_3200_1200_1_3_1040_1040
+ NEW Metal3 0 + SHAPE STRIPE ( 46080 133280 ) via3_4_3200_1200_1_3_1040_1040
+ NEW Metal2 0 + SHAPE STRIPE ( 46080 133280 ) via2_3_3200_1200_1_3_1040_1040
+ NEW Metal1 0 + SHAPE STRIPE ( 46080 133280 ) via1_2_3200_1200_1_3_1040_1040
+ NEW Metal3 0 + SHAPE STRIPE ( 46080 117600 ) via3_4_3200_1200_1_3_1040_1040
+ NEW Metal2 0 + SHAPE STRIPE ( 46080 117600 ) via2_3_3200_1200_1_3_1040_1040
+ NEW Metal1 0 + SHAPE STRIPE ( 46080 117600 ) via1_2_3200_1200_1_3_1040_1040
+ NEW Metal3 0 + SHAPE STRIPE ( 46080 101920 ) via3_4_3200_1200_1_3_1040_1040
+ NEW Metal2 0 + SHAPE STRIPE ( 46080 101920 ) via2_3_3200_1200_1_3_1040_1040
+ NEW Metal1 0 + SHAPE STRIPE ( 46080 101920 ) via1_2_3200_1200_1_3_1040_1040
+ NEW Metal3 0 + SHAPE STRIPE ( 46080 86240 ) via3_4_3200_1200_1_3_1040_1040
+ NEW Metal2 0 + SHAPE STRIPE ( 46080 86240 ) via2_3_3200_1200_1_3_1040_1040
+ NEW Metal1 0 + SHAPE STRIPE ( 46080 86240 ) via1_2_3200_1200_1_3_1040_1040
+ NEW Metal3 0 + SHAPE STRIPE ( 46080 70560 ) via3_4_3200_1200_1_3_1040_1040
+ NEW Metal2 0 + SHAPE STRIPE ( 46080 70560 ) via2_3_3200_1200_1_3_1040_1040
+ NEW Metal1 0 + SHAPE STRIPE ( 46080 70560 ) via1_2_3200_1200_1_3_1040_1040
+ NEW Metal3 0 + SHAPE STRIPE ( 46080 54880 ) via3_4_3200_1200_1_3_1040_1040
+ NEW Metal2 0 + SHAPE STRIPE ( 46080 54880 ) via2_3_3200_1200_1_3_1040_1040
+ NEW Metal1 0 + SHAPE STRIPE ( 46080 54880 ) via1_2_3200_1200_1_3_1040_1040
+ NEW Metal3 0 + SHAPE STRIPE ( 46080 39200 ) via3_4_3200_1200_1_3_1040_1040
+ NEW Metal2 0 + SHAPE STRIPE ( 46080 39200 ) via2_3_3200_1200_1_3_1040_1040
+ NEW Metal1 0 + SHAPE STRIPE ( 46080 39200 ) via1_2_3200_1200_1_3_1040_1040 ;
+ - vss ( PIN vss ) ( * VSS ) + USE GROUND
+ + ROUTED Metal1 1200 + SHAPE FOLLOWPIN ( 13440 564480 ) ( 585760 564480 )
+ NEW Metal1 1200 + SHAPE FOLLOWPIN ( 13440 548800 ) ( 585760 548800 )
+ NEW Metal1 1200 + SHAPE FOLLOWPIN ( 13440 533120 ) ( 585760 533120 )
+ NEW Metal1 1200 + SHAPE FOLLOWPIN ( 13440 517440 ) ( 585760 517440 )
+ NEW Metal1 1200 + SHAPE FOLLOWPIN ( 13440 501760 ) ( 585760 501760 )
+ NEW Metal1 1200 + SHAPE FOLLOWPIN ( 13440 486080 ) ( 585760 486080 )
+ NEW Metal1 1200 + SHAPE FOLLOWPIN ( 13440 470400 ) ( 585760 470400 )
+ NEW Metal1 1200 + SHAPE FOLLOWPIN ( 13440 454720 ) ( 585760 454720 )
+ NEW Metal1 1200 + SHAPE FOLLOWPIN ( 13440 439040 ) ( 585760 439040 )
+ NEW Metal1 1200 + SHAPE FOLLOWPIN ( 13440 423360 ) ( 585760 423360 )
+ NEW Metal1 1200 + SHAPE FOLLOWPIN ( 13440 407680 ) ( 585760 407680 )
+ NEW Metal1 1200 + SHAPE FOLLOWPIN ( 13440 392000 ) ( 585760 392000 )
+ NEW Metal1 1200 + SHAPE FOLLOWPIN ( 13440 376320 ) ( 585760 376320 )
+ NEW Metal1 1200 + SHAPE FOLLOWPIN ( 13440 360640 ) ( 585760 360640 )
+ NEW Metal1 1200 + SHAPE FOLLOWPIN ( 13440 344960 ) ( 585760 344960 )
+ NEW Metal1 1200 + SHAPE FOLLOWPIN ( 13440 329280 ) ( 585760 329280 )
+ NEW Metal1 1200 + SHAPE FOLLOWPIN ( 13440 313600 ) ( 585760 313600 )
+ NEW Metal1 1200 + SHAPE FOLLOWPIN ( 13440 297920 ) ( 585760 297920 )
+ NEW Metal1 1200 + SHAPE FOLLOWPIN ( 13440 282240 ) ( 585760 282240 )
+ NEW Metal1 1200 + SHAPE FOLLOWPIN ( 13440 266560 ) ( 585760 266560 )
+ NEW Metal1 1200 + SHAPE FOLLOWPIN ( 13440 250880 ) ( 585760 250880 )
+ NEW Metal1 1200 + SHAPE FOLLOWPIN ( 13440 235200 ) ( 585760 235200 )
+ NEW Metal1 1200 + SHAPE FOLLOWPIN ( 13440 219520 ) ( 585760 219520 )
+ NEW Metal1 1200 + SHAPE FOLLOWPIN ( 13440 203840 ) ( 585760 203840 )
+ NEW Metal1 1200 + SHAPE FOLLOWPIN ( 13440 188160 ) ( 585760 188160 )
+ NEW Metal1 1200 + SHAPE FOLLOWPIN ( 13440 172480 ) ( 585760 172480 )
+ NEW Metal1 1200 + SHAPE FOLLOWPIN ( 13440 156800 ) ( 585760 156800 )
+ NEW Metal1 1200 + SHAPE FOLLOWPIN ( 13440 141120 ) ( 585760 141120 )
+ NEW Metal1 1200 + SHAPE FOLLOWPIN ( 13440 125440 ) ( 585760 125440 )
+ NEW Metal1 1200 + SHAPE FOLLOWPIN ( 13440 109760 ) ( 585760 109760 )
+ NEW Metal1 1200 + SHAPE FOLLOWPIN ( 13440 94080 ) ( 585760 94080 )
+ NEW Metal1 1200 + SHAPE FOLLOWPIN ( 13440 78400 ) ( 585760 78400 )
+ NEW Metal1 1200 + SHAPE FOLLOWPIN ( 13440 62720 ) ( 585760 62720 )
+ NEW Metal1 1200 + SHAPE FOLLOWPIN ( 13440 47040 ) ( 585760 47040 )
+ NEW Metal1 1200 + SHAPE FOLLOWPIN ( 13440 31360 ) ( 585760 31360 )
+ NEW Metal4 3200 + SHAPE STRIPE ( 506880 30760 ) ( 506880 565080 )
+ NEW Metal4 3200 + SHAPE STRIPE ( 199680 30760 ) ( 199680 565080 )
+ NEW Metal3 0 + SHAPE STRIPE ( 506880 564480 ) via3_4_3200_1200_1_3_1040_1040
+ NEW Metal2 0 + SHAPE STRIPE ( 506880 564480 ) via2_3_3200_1200_1_3_1040_1040
+ NEW Metal1 0 + SHAPE STRIPE ( 506880 564480 ) via1_2_3200_1200_1_3_1040_1040
+ NEW Metal3 0 + SHAPE STRIPE ( 506880 548800 ) via3_4_3200_1200_1_3_1040_1040
+ NEW Metal2 0 + SHAPE STRIPE ( 506880 548800 ) via2_3_3200_1200_1_3_1040_1040
+ NEW Metal1 0 + SHAPE STRIPE ( 506880 548800 ) via1_2_3200_1200_1_3_1040_1040
+ NEW Metal3 0 + SHAPE STRIPE ( 506880 533120 ) via3_4_3200_1200_1_3_1040_1040
+ NEW Metal2 0 + SHAPE STRIPE ( 506880 533120 ) via2_3_3200_1200_1_3_1040_1040
+ NEW Metal1 0 + SHAPE STRIPE ( 506880 533120 ) via1_2_3200_1200_1_3_1040_1040
+ NEW Metal3 0 + SHAPE STRIPE ( 506880 517440 ) via3_4_3200_1200_1_3_1040_1040
+ NEW Metal2 0 + SHAPE STRIPE ( 506880 517440 ) via2_3_3200_1200_1_3_1040_1040
+ NEW Metal1 0 + SHAPE STRIPE ( 506880 517440 ) via1_2_3200_1200_1_3_1040_1040
+ NEW Metal3 0 + SHAPE STRIPE ( 506880 501760 ) via3_4_3200_1200_1_3_1040_1040
+ NEW Metal2 0 + SHAPE STRIPE ( 506880 501760 ) via2_3_3200_1200_1_3_1040_1040
+ NEW Metal1 0 + SHAPE STRIPE ( 506880 501760 ) via1_2_3200_1200_1_3_1040_1040
+ NEW Metal3 0 + SHAPE STRIPE ( 506880 486080 ) via3_4_3200_1200_1_3_1040_1040
+ NEW Metal2 0 + SHAPE STRIPE ( 506880 486080 ) via2_3_3200_1200_1_3_1040_1040
+ NEW Metal1 0 + SHAPE STRIPE ( 506880 486080 ) via1_2_3200_1200_1_3_1040_1040
+ NEW Metal3 0 + SHAPE STRIPE ( 506880 470400 ) via3_4_3200_1200_1_3_1040_1040
+ NEW Metal2 0 + SHAPE STRIPE ( 506880 470400 ) via2_3_3200_1200_1_3_1040_1040
+ NEW Metal1 0 + SHAPE STRIPE ( 506880 470400 ) via1_2_3200_1200_1_3_1040_1040
+ NEW Metal3 0 + SHAPE STRIPE ( 506880 454720 ) via3_4_3200_1200_1_3_1040_1040
+ NEW Metal2 0 + SHAPE STRIPE ( 506880 454720 ) via2_3_3200_1200_1_3_1040_1040
+ NEW Metal1 0 + SHAPE STRIPE ( 506880 454720 ) via1_2_3200_1200_1_3_1040_1040
+ NEW Metal3 0 + SHAPE STRIPE ( 506880 439040 ) via3_4_3200_1200_1_3_1040_1040
+ NEW Metal2 0 + SHAPE STRIPE ( 506880 439040 ) via2_3_3200_1200_1_3_1040_1040
+ NEW Metal1 0 + SHAPE STRIPE ( 506880 439040 ) via1_2_3200_1200_1_3_1040_1040
+ NEW Metal3 0 + SHAPE STRIPE ( 506880 423360 ) via3_4_3200_1200_1_3_1040_1040
+ NEW Metal2 0 + SHAPE STRIPE ( 506880 423360 ) via2_3_3200_1200_1_3_1040_1040
+ NEW Metal1 0 + SHAPE STRIPE ( 506880 423360 ) via1_2_3200_1200_1_3_1040_1040
+ NEW Metal3 0 + SHAPE STRIPE ( 506880 407680 ) via3_4_3200_1200_1_3_1040_1040
+ NEW Metal2 0 + SHAPE STRIPE ( 506880 407680 ) via2_3_3200_1200_1_3_1040_1040
+ NEW Metal1 0 + SHAPE STRIPE ( 506880 407680 ) via1_2_3200_1200_1_3_1040_1040
+ NEW Metal3 0 + SHAPE STRIPE ( 506880 392000 ) via3_4_3200_1200_1_3_1040_1040
+ NEW Metal2 0 + SHAPE STRIPE ( 506880 392000 ) via2_3_3200_1200_1_3_1040_1040
+ NEW Metal1 0 + SHAPE STRIPE ( 506880 392000 ) via1_2_3200_1200_1_3_1040_1040
+ NEW Metal3 0 + SHAPE STRIPE ( 506880 376320 ) via3_4_3200_1200_1_3_1040_1040
+ NEW Metal2 0 + SHAPE STRIPE ( 506880 376320 ) via2_3_3200_1200_1_3_1040_1040
+ NEW Metal1 0 + SHAPE STRIPE ( 506880 376320 ) via1_2_3200_1200_1_3_1040_1040
+ NEW Metal3 0 + SHAPE STRIPE ( 506880 360640 ) via3_4_3200_1200_1_3_1040_1040
+ NEW Metal2 0 + SHAPE STRIPE ( 506880 360640 ) via2_3_3200_1200_1_3_1040_1040
+ NEW Metal1 0 + SHAPE STRIPE ( 506880 360640 ) via1_2_3200_1200_1_3_1040_1040
+ NEW Metal3 0 + SHAPE STRIPE ( 506880 344960 ) via3_4_3200_1200_1_3_1040_1040
+ NEW Metal2 0 + SHAPE STRIPE ( 506880 344960 ) via2_3_3200_1200_1_3_1040_1040
+ NEW Metal1 0 + SHAPE STRIPE ( 506880 344960 ) via1_2_3200_1200_1_3_1040_1040
+ NEW Metal3 0 + SHAPE STRIPE ( 506880 329280 ) via3_4_3200_1200_1_3_1040_1040
+ NEW Metal2 0 + SHAPE STRIPE ( 506880 329280 ) via2_3_3200_1200_1_3_1040_1040
+ NEW Metal1 0 + SHAPE STRIPE ( 506880 329280 ) via1_2_3200_1200_1_3_1040_1040
+ NEW Metal3 0 + SHAPE STRIPE ( 506880 313600 ) via3_4_3200_1200_1_3_1040_1040
+ NEW Metal2 0 + SHAPE STRIPE ( 506880 313600 ) via2_3_3200_1200_1_3_1040_1040
+ NEW Metal1 0 + SHAPE STRIPE ( 506880 313600 ) via1_2_3200_1200_1_3_1040_1040
+ NEW Metal3 0 + SHAPE STRIPE ( 506880 297920 ) via3_4_3200_1200_1_3_1040_1040
+ NEW Metal2 0 + SHAPE STRIPE ( 506880 297920 ) via2_3_3200_1200_1_3_1040_1040
+ NEW Metal1 0 + SHAPE STRIPE ( 506880 297920 ) via1_2_3200_1200_1_3_1040_1040
+ NEW Metal3 0 + SHAPE STRIPE ( 506880 282240 ) via3_4_3200_1200_1_3_1040_1040
+ NEW Metal2 0 + SHAPE STRIPE ( 506880 282240 ) via2_3_3200_1200_1_3_1040_1040
+ NEW Metal1 0 + SHAPE STRIPE ( 506880 282240 ) via1_2_3200_1200_1_3_1040_1040
+ NEW Metal3 0 + SHAPE STRIPE ( 506880 266560 ) via3_4_3200_1200_1_3_1040_1040
+ NEW Metal2 0 + SHAPE STRIPE ( 506880 266560 ) via2_3_3200_1200_1_3_1040_1040
+ NEW Metal1 0 + SHAPE STRIPE ( 506880 266560 ) via1_2_3200_1200_1_3_1040_1040
+ NEW Metal3 0 + SHAPE STRIPE ( 506880 250880 ) via3_4_3200_1200_1_3_1040_1040
+ NEW Metal2 0 + SHAPE STRIPE ( 506880 250880 ) via2_3_3200_1200_1_3_1040_1040
+ NEW Metal1 0 + SHAPE STRIPE ( 506880 250880 ) via1_2_3200_1200_1_3_1040_1040
+ NEW Metal3 0 + SHAPE STRIPE ( 506880 235200 ) via3_4_3200_1200_1_3_1040_1040
+ NEW Metal2 0 + SHAPE STRIPE ( 506880 235200 ) via2_3_3200_1200_1_3_1040_1040
+ NEW Metal1 0 + SHAPE STRIPE ( 506880 235200 ) via1_2_3200_1200_1_3_1040_1040
+ NEW Metal3 0 + SHAPE STRIPE ( 506880 219520 ) via3_4_3200_1200_1_3_1040_1040
+ NEW Metal2 0 + SHAPE STRIPE ( 506880 219520 ) via2_3_3200_1200_1_3_1040_1040
+ NEW Metal1 0 + SHAPE STRIPE ( 506880 219520 ) via1_2_3200_1200_1_3_1040_1040
+ NEW Metal3 0 + SHAPE STRIPE ( 506880 203840 ) via3_4_3200_1200_1_3_1040_1040
+ NEW Metal2 0 + SHAPE STRIPE ( 506880 203840 ) via2_3_3200_1200_1_3_1040_1040
+ NEW Metal1 0 + SHAPE STRIPE ( 506880 203840 ) via1_2_3200_1200_1_3_1040_1040
+ NEW Metal3 0 + SHAPE STRIPE ( 506880 188160 ) via3_4_3200_1200_1_3_1040_1040
+ NEW Metal2 0 + SHAPE STRIPE ( 506880 188160 ) via2_3_3200_1200_1_3_1040_1040
+ NEW Metal1 0 + SHAPE STRIPE ( 506880 188160 ) via1_2_3200_1200_1_3_1040_1040
+ NEW Metal3 0 + SHAPE STRIPE ( 506880 172480 ) via3_4_3200_1200_1_3_1040_1040
+ NEW Metal2 0 + SHAPE STRIPE ( 506880 172480 ) via2_3_3200_1200_1_3_1040_1040
+ NEW Metal1 0 + SHAPE STRIPE ( 506880 172480 ) via1_2_3200_1200_1_3_1040_1040
+ NEW Metal3 0 + SHAPE STRIPE ( 506880 156800 ) via3_4_3200_1200_1_3_1040_1040
+ NEW Metal2 0 + SHAPE STRIPE ( 506880 156800 ) via2_3_3200_1200_1_3_1040_1040
+ NEW Metal1 0 + SHAPE STRIPE ( 506880 156800 ) via1_2_3200_1200_1_3_1040_1040
+ NEW Metal3 0 + SHAPE STRIPE ( 506880 141120 ) via3_4_3200_1200_1_3_1040_1040
+ NEW Metal2 0 + SHAPE STRIPE ( 506880 141120 ) via2_3_3200_1200_1_3_1040_1040
+ NEW Metal1 0 + SHAPE STRIPE ( 506880 141120 ) via1_2_3200_1200_1_3_1040_1040
+ NEW Metal3 0 + SHAPE STRIPE ( 506880 125440 ) via3_4_3200_1200_1_3_1040_1040
+ NEW Metal2 0 + SHAPE STRIPE ( 506880 125440 ) via2_3_3200_1200_1_3_1040_1040
+ NEW Metal1 0 + SHAPE STRIPE ( 506880 125440 ) via1_2_3200_1200_1_3_1040_1040
+ NEW Metal3 0 + SHAPE STRIPE ( 506880 109760 ) via3_4_3200_1200_1_3_1040_1040
+ NEW Metal2 0 + SHAPE STRIPE ( 506880 109760 ) via2_3_3200_1200_1_3_1040_1040
+ NEW Metal1 0 + SHAPE STRIPE ( 506880 109760 ) via1_2_3200_1200_1_3_1040_1040
+ NEW Metal3 0 + SHAPE STRIPE ( 506880 94080 ) via3_4_3200_1200_1_3_1040_1040
+ NEW Metal2 0 + SHAPE STRIPE ( 506880 94080 ) via2_3_3200_1200_1_3_1040_1040
+ NEW Metal1 0 + SHAPE STRIPE ( 506880 94080 ) via1_2_3200_1200_1_3_1040_1040
+ NEW Metal3 0 + SHAPE STRIPE ( 506880 78400 ) via3_4_3200_1200_1_3_1040_1040
+ NEW Metal2 0 + SHAPE STRIPE ( 506880 78400 ) via2_3_3200_1200_1_3_1040_1040
+ NEW Metal1 0 + SHAPE STRIPE ( 506880 78400 ) via1_2_3200_1200_1_3_1040_1040
+ NEW Metal3 0 + SHAPE STRIPE ( 506880 62720 ) via3_4_3200_1200_1_3_1040_1040
+ NEW Metal2 0 + SHAPE STRIPE ( 506880 62720 ) via2_3_3200_1200_1_3_1040_1040
+ NEW Metal1 0 + SHAPE STRIPE ( 506880 62720 ) via1_2_3200_1200_1_3_1040_1040
+ NEW Metal3 0 + SHAPE STRIPE ( 506880 47040 ) via3_4_3200_1200_1_3_1040_1040
+ NEW Metal2 0 + SHAPE STRIPE ( 506880 47040 ) via2_3_3200_1200_1_3_1040_1040
+ NEW Metal1 0 + SHAPE STRIPE ( 506880 47040 ) via1_2_3200_1200_1_3_1040_1040
+ NEW Metal3 0 + SHAPE STRIPE ( 506880 31360 ) via3_4_3200_1200_1_3_1040_1040
+ NEW Metal2 0 + SHAPE STRIPE ( 506880 31360 ) via2_3_3200_1200_1_3_1040_1040
+ NEW Metal1 0 + SHAPE STRIPE ( 506880 31360 ) via1_2_3200_1200_1_3_1040_1040
+ NEW Metal3 0 + SHAPE STRIPE ( 199680 564480 ) via3_4_3200_1200_1_3_1040_1040
+ NEW Metal2 0 + SHAPE STRIPE ( 199680 564480 ) via2_3_3200_1200_1_3_1040_1040
+ NEW Metal1 0 + SHAPE STRIPE ( 199680 564480 ) via1_2_3200_1200_1_3_1040_1040
+ NEW Metal3 0 + SHAPE STRIPE ( 199680 548800 ) via3_4_3200_1200_1_3_1040_1040
+ NEW Metal2 0 + SHAPE STRIPE ( 199680 548800 ) via2_3_3200_1200_1_3_1040_1040
+ NEW Metal1 0 + SHAPE STRIPE ( 199680 548800 ) via1_2_3200_1200_1_3_1040_1040
+ NEW Metal3 0 + SHAPE STRIPE ( 199680 533120 ) via3_4_3200_1200_1_3_1040_1040
+ NEW Metal2 0 + SHAPE STRIPE ( 199680 533120 ) via2_3_3200_1200_1_3_1040_1040
+ NEW Metal1 0 + SHAPE STRIPE ( 199680 533120 ) via1_2_3200_1200_1_3_1040_1040
+ NEW Metal3 0 + SHAPE STRIPE ( 199680 517440 ) via3_4_3200_1200_1_3_1040_1040
+ NEW Metal2 0 + SHAPE STRIPE ( 199680 517440 ) via2_3_3200_1200_1_3_1040_1040
+ NEW Metal1 0 + SHAPE STRIPE ( 199680 517440 ) via1_2_3200_1200_1_3_1040_1040
+ NEW Metal3 0 + SHAPE STRIPE ( 199680 501760 ) via3_4_3200_1200_1_3_1040_1040
+ NEW Metal2 0 + SHAPE STRIPE ( 199680 501760 ) via2_3_3200_1200_1_3_1040_1040
+ NEW Metal1 0 + SHAPE STRIPE ( 199680 501760 ) via1_2_3200_1200_1_3_1040_1040
+ NEW Metal3 0 + SHAPE STRIPE ( 199680 486080 ) via3_4_3200_1200_1_3_1040_1040
+ NEW Metal2 0 + SHAPE STRIPE ( 199680 486080 ) via2_3_3200_1200_1_3_1040_1040
+ NEW Metal1 0 + SHAPE STRIPE ( 199680 486080 ) via1_2_3200_1200_1_3_1040_1040
+ NEW Metal3 0 + SHAPE STRIPE ( 199680 470400 ) via3_4_3200_1200_1_3_1040_1040
+ NEW Metal2 0 + SHAPE STRIPE ( 199680 470400 ) via2_3_3200_1200_1_3_1040_1040
+ NEW Metal1 0 + SHAPE STRIPE ( 199680 470400 ) via1_2_3200_1200_1_3_1040_1040
+ NEW Metal3 0 + SHAPE STRIPE ( 199680 454720 ) via3_4_3200_1200_1_3_1040_1040
+ NEW Metal2 0 + SHAPE STRIPE ( 199680 454720 ) via2_3_3200_1200_1_3_1040_1040
+ NEW Metal1 0 + SHAPE STRIPE ( 199680 454720 ) via1_2_3200_1200_1_3_1040_1040
+ NEW Metal3 0 + SHAPE STRIPE ( 199680 439040 ) via3_4_3200_1200_1_3_1040_1040
+ NEW Metal2 0 + SHAPE STRIPE ( 199680 439040 ) via2_3_3200_1200_1_3_1040_1040
+ NEW Metal1 0 + SHAPE STRIPE ( 199680 439040 ) via1_2_3200_1200_1_3_1040_1040
+ NEW Metal3 0 + SHAPE STRIPE ( 199680 423360 ) via3_4_3200_1200_1_3_1040_1040
+ NEW Metal2 0 + SHAPE STRIPE ( 199680 423360 ) via2_3_3200_1200_1_3_1040_1040
+ NEW Metal1 0 + SHAPE STRIPE ( 199680 423360 ) via1_2_3200_1200_1_3_1040_1040
+ NEW Metal3 0 + SHAPE STRIPE ( 199680 407680 ) via3_4_3200_1200_1_3_1040_1040
+ NEW Metal2 0 + SHAPE STRIPE ( 199680 407680 ) via2_3_3200_1200_1_3_1040_1040
+ NEW Metal1 0 + SHAPE STRIPE ( 199680 407680 ) via1_2_3200_1200_1_3_1040_1040
+ NEW Metal3 0 + SHAPE STRIPE ( 199680 392000 ) via3_4_3200_1200_1_3_1040_1040
+ NEW Metal2 0 + SHAPE STRIPE ( 199680 392000 ) via2_3_3200_1200_1_3_1040_1040
+ NEW Metal1 0 + SHAPE STRIPE ( 199680 392000 ) via1_2_3200_1200_1_3_1040_1040
+ NEW Metal3 0 + SHAPE STRIPE ( 199680 376320 ) via3_4_3200_1200_1_3_1040_1040
+ NEW Metal2 0 + SHAPE STRIPE ( 199680 376320 ) via2_3_3200_1200_1_3_1040_1040
+ NEW Metal1 0 + SHAPE STRIPE ( 199680 376320 ) via1_2_3200_1200_1_3_1040_1040
+ NEW Metal3 0 + SHAPE STRIPE ( 199680 360640 ) via3_4_3200_1200_1_3_1040_1040
+ NEW Metal2 0 + SHAPE STRIPE ( 199680 360640 ) via2_3_3200_1200_1_3_1040_1040
+ NEW Metal1 0 + SHAPE STRIPE ( 199680 360640 ) via1_2_3200_1200_1_3_1040_1040
+ NEW Metal3 0 + SHAPE STRIPE ( 199680 344960 ) via3_4_3200_1200_1_3_1040_1040
+ NEW Metal2 0 + SHAPE STRIPE ( 199680 344960 ) via2_3_3200_1200_1_3_1040_1040
+ NEW Metal1 0 + SHAPE STRIPE ( 199680 344960 ) via1_2_3200_1200_1_3_1040_1040
+ NEW Metal3 0 + SHAPE STRIPE ( 199680 329280 ) via3_4_3200_1200_1_3_1040_1040
+ NEW Metal2 0 + SHAPE STRIPE ( 199680 329280 ) via2_3_3200_1200_1_3_1040_1040
+ NEW Metal1 0 + SHAPE STRIPE ( 199680 329280 ) via1_2_3200_1200_1_3_1040_1040
+ NEW Metal3 0 + SHAPE STRIPE ( 199680 313600 ) via3_4_3200_1200_1_3_1040_1040
+ NEW Metal2 0 + SHAPE STRIPE ( 199680 313600 ) via2_3_3200_1200_1_3_1040_1040
+ NEW Metal1 0 + SHAPE STRIPE ( 199680 313600 ) via1_2_3200_1200_1_3_1040_1040
+ NEW Metal3 0 + SHAPE STRIPE ( 199680 297920 ) via3_4_3200_1200_1_3_1040_1040
+ NEW Metal2 0 + SHAPE STRIPE ( 199680 297920 ) via2_3_3200_1200_1_3_1040_1040
+ NEW Metal1 0 + SHAPE STRIPE ( 199680 297920 ) via1_2_3200_1200_1_3_1040_1040
+ NEW Metal3 0 + SHAPE STRIPE ( 199680 282240 ) via3_4_3200_1200_1_3_1040_1040
+ NEW Metal2 0 + SHAPE STRIPE ( 199680 282240 ) via2_3_3200_1200_1_3_1040_1040
+ NEW Metal1 0 + SHAPE STRIPE ( 199680 282240 ) via1_2_3200_1200_1_3_1040_1040
+ NEW Metal3 0 + SHAPE STRIPE ( 199680 266560 ) via3_4_3200_1200_1_3_1040_1040
+ NEW Metal2 0 + SHAPE STRIPE ( 199680 266560 ) via2_3_3200_1200_1_3_1040_1040
+ NEW Metal1 0 + SHAPE STRIPE ( 199680 266560 ) via1_2_3200_1200_1_3_1040_1040
+ NEW Metal3 0 + SHAPE STRIPE ( 199680 250880 ) via3_4_3200_1200_1_3_1040_1040
+ NEW Metal2 0 + SHAPE STRIPE ( 199680 250880 ) via2_3_3200_1200_1_3_1040_1040
+ NEW Metal1 0 + SHAPE STRIPE ( 199680 250880 ) via1_2_3200_1200_1_3_1040_1040
+ NEW Metal3 0 + SHAPE STRIPE ( 199680 235200 ) via3_4_3200_1200_1_3_1040_1040
+ NEW Metal2 0 + SHAPE STRIPE ( 199680 235200 ) via2_3_3200_1200_1_3_1040_1040
+ NEW Metal1 0 + SHAPE STRIPE ( 199680 235200 ) via1_2_3200_1200_1_3_1040_1040
+ NEW Metal3 0 + SHAPE STRIPE ( 199680 219520 ) via3_4_3200_1200_1_3_1040_1040
+ NEW Metal2 0 + SHAPE STRIPE ( 199680 219520 ) via2_3_3200_1200_1_3_1040_1040
+ NEW Metal1 0 + SHAPE STRIPE ( 199680 219520 ) via1_2_3200_1200_1_3_1040_1040
+ NEW Metal3 0 + SHAPE STRIPE ( 199680 203840 ) via3_4_3200_1200_1_3_1040_1040
+ NEW Metal2 0 + SHAPE STRIPE ( 199680 203840 ) via2_3_3200_1200_1_3_1040_1040
+ NEW Metal1 0 + SHAPE STRIPE ( 199680 203840 ) via1_2_3200_1200_1_3_1040_1040
+ NEW Metal3 0 + SHAPE STRIPE ( 199680 188160 ) via3_4_3200_1200_1_3_1040_1040
+ NEW Metal2 0 + SHAPE STRIPE ( 199680 188160 ) via2_3_3200_1200_1_3_1040_1040
+ NEW Metal1 0 + SHAPE STRIPE ( 199680 188160 ) via1_2_3200_1200_1_3_1040_1040
+ NEW Metal3 0 + SHAPE STRIPE ( 199680 172480 ) via3_4_3200_1200_1_3_1040_1040
+ NEW Metal2 0 + SHAPE STRIPE ( 199680 172480 ) via2_3_3200_1200_1_3_1040_1040
+ NEW Metal1 0 + SHAPE STRIPE ( 199680 172480 ) via1_2_3200_1200_1_3_1040_1040
+ NEW Metal3 0 + SHAPE STRIPE ( 199680 156800 ) via3_4_3200_1200_1_3_1040_1040
+ NEW Metal2 0 + SHAPE STRIPE ( 199680 156800 ) via2_3_3200_1200_1_3_1040_1040
+ NEW Metal1 0 + SHAPE STRIPE ( 199680 156800 ) via1_2_3200_1200_1_3_1040_1040
+ NEW Metal3 0 + SHAPE STRIPE ( 199680 141120 ) via3_4_3200_1200_1_3_1040_1040
+ NEW Metal2 0 + SHAPE STRIPE ( 199680 141120 ) via2_3_3200_1200_1_3_1040_1040
+ NEW Metal1 0 + SHAPE STRIPE ( 199680 141120 ) via1_2_3200_1200_1_3_1040_1040
+ NEW Metal3 0 + SHAPE STRIPE ( 199680 125440 ) via3_4_3200_1200_1_3_1040_1040
+ NEW Metal2 0 + SHAPE STRIPE ( 199680 125440 ) via2_3_3200_1200_1_3_1040_1040
+ NEW Metal1 0 + SHAPE STRIPE ( 199680 125440 ) via1_2_3200_1200_1_3_1040_1040
+ NEW Metal3 0 + SHAPE STRIPE ( 199680 109760 ) via3_4_3200_1200_1_3_1040_1040
+ NEW Metal2 0 + SHAPE STRIPE ( 199680 109760 ) via2_3_3200_1200_1_3_1040_1040
+ NEW Metal1 0 + SHAPE STRIPE ( 199680 109760 ) via1_2_3200_1200_1_3_1040_1040
+ NEW Metal3 0 + SHAPE STRIPE ( 199680 94080 ) via3_4_3200_1200_1_3_1040_1040
+ NEW Metal2 0 + SHAPE STRIPE ( 199680 94080 ) via2_3_3200_1200_1_3_1040_1040
+ NEW Metal1 0 + SHAPE STRIPE ( 199680 94080 ) via1_2_3200_1200_1_3_1040_1040
+ NEW Metal3 0 + SHAPE STRIPE ( 199680 78400 ) via3_4_3200_1200_1_3_1040_1040
+ NEW Metal2 0 + SHAPE STRIPE ( 199680 78400 ) via2_3_3200_1200_1_3_1040_1040
+ NEW Metal1 0 + SHAPE STRIPE ( 199680 78400 ) via1_2_3200_1200_1_3_1040_1040
+ NEW Metal3 0 + SHAPE STRIPE ( 199680 62720 ) via3_4_3200_1200_1_3_1040_1040
+ NEW Metal2 0 + SHAPE STRIPE ( 199680 62720 ) via2_3_3200_1200_1_3_1040_1040
+ NEW Metal1 0 + SHAPE STRIPE ( 199680 62720 ) via1_2_3200_1200_1_3_1040_1040
+ NEW Metal3 0 + SHAPE STRIPE ( 199680 47040 ) via3_4_3200_1200_1_3_1040_1040
+ NEW Metal2 0 + SHAPE STRIPE ( 199680 47040 ) via2_3_3200_1200_1_3_1040_1040
+ NEW Metal1 0 + SHAPE STRIPE ( 199680 47040 ) via1_2_3200_1200_1_3_1040_1040
+ NEW Metal3 0 + SHAPE STRIPE ( 199680 31360 ) via3_4_3200_1200_1_3_1040_1040
+ NEW Metal2 0 + SHAPE STRIPE ( 199680 31360 ) via2_3_3200_1200_1_3_1040_1040
+ NEW Metal1 0 + SHAPE STRIPE ( 199680 31360 ) via1_2_3200_1200_1_3_1040_1040 ;
+END SPECIALNETS
+NETS 980 ;
+ - _0000_ ( _1365_ D ) ( _0690_ Z ) + USE SIGNAL
+ + ROUTED Metal2 ( 526960 279440 ) ( * 285040 )
+ NEW Metal3 ( 516880 285040 ) ( 526960 * )
+ NEW Metal3 ( 516880 285040 ) ( * 286160 )
+ NEW Metal2 ( 516880 286160 ) ( * 295120 )
+ NEW Metal1 ( 526960 279440 ) Via1_HV
+ NEW Metal2 ( 526960 285040 ) Via2_VH
+ NEW Metal2 ( 516880 286160 ) Via2_VH
+ NEW Metal1 ( 516880 295120 ) Via1_VV ;
+ - _0001_ ( _1366_ D ) ( _0692_ Z ) + USE SIGNAL
+ + ROUTED Metal2 ( 213360 91280 ) ( * 95760 )
+ NEW Metal2 ( 207760 95760 ) ( 213360 * )
+ NEW Metal1 ( 213360 91280 ) Via1_HV
+ NEW Metal1 ( 207760 95760 ) Via1_VV ;
+ - _0002_ ( _1464_ D ) ( _0821_ Z ) + USE SIGNAL
+ + ROUTED Metal2 ( 395920 193200 ) ( * 196560 )
+ NEW Metal2 ( 389200 196560 ) ( 395920 * )
+ NEW Metal2 ( 389200 196560 ) ( * 205520 )
+ NEW Metal1 ( 395920 193200 ) Via1_HV
+ NEW Metal1 ( 389200 205520 ) Via1_VV ;
+ - _0003_ ( _1465_ D ) ( _0828_ Z ) + USE SIGNAL
+ + ROUTED Metal2 ( 384720 232400 ) ( * 248080 )
+ NEW Metal2 ( 383600 248080 ) ( 384720 * )
+ NEW Metal2 ( 384720 232400 ) ( 386960 * )
+ NEW Metal1 ( 383600 248080 ) Via1_VV
+ NEW Metal1 ( 386960 232400 ) Via1_HV ;
+ - _0004_ ( _1466_ D ) ( _0833_ Z ) + USE SIGNAL
+ + ROUTED Metal2 ( 385840 257040 ) ( * 279440 )
+ NEW Metal2 ( 393680 255920 ) ( * 257040 )
+ NEW Metal3 ( 385840 257040 ) ( 393680 * )
+ NEW Metal2 ( 385840 257040 ) Via2_VH
+ NEW Metal1 ( 385840 279440 ) Via1_VV
+ NEW Metal1 ( 393680 255920 ) Via1_HV
+ NEW Metal2 ( 393680 257040 ) Via2_VH ;
+ - _0005_ ( _1369_ D ) ( _0747_ ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 522480 214480 ) ( 524720 * )
+ NEW Metal2 ( 524720 198800 ) ( * 214480 )
+ NEW Metal1 ( 522480 214480 ) Via1_HV
+ NEW Metal1 ( 524720 198800 ) Via1_HV ;
+ - _0006_ ( _1370_ D ) ( _0761_ ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 542640 201600 ) ( * 206640 )
+ NEW Metal2 ( 540400 193200 ) ( * 201600 )
+ NEW Metal2 ( 540400 201600 ) ( 542640 * )
+ NEW Metal1 ( 542640 206640 ) Via1_HV
+ NEW Metal1 ( 540400 193200 ) Via1_HV ;
+ - _0007_ ( _1371_ D ) ( _0771_ ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 496720 217840 ) ( * 230160 )
+ NEW Metal2 ( 496720 230160 ) ( 503440 * )
+ NEW Metal1 ( 496720 217840 ) Via1_VV
+ NEW Metal1 ( 503440 230160 ) Via1_HV ;
+ - _0008_ ( ANTENNA__1364__D I ) ( _1364_ D ) ( _0867_ ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 449680 91280 ) ( * 92400 )
+ NEW Metal3 ( 216720 92400 ) ( 449680 * )
+ NEW Metal2 ( 216720 210000 ) ( 217840 * )
+ NEW Metal2 ( 217840 210000 ) ( * 245840 )
+ NEW Metal2 ( 217840 245840 ) ( 218960 * )
+ NEW Metal2 ( 218960 245840 ) ( * 250320 )
+ NEW Metal2 ( 217840 250320 ) ( 218960 * )
+ NEW Metal2 ( 216720 92400 ) ( * 210000 )
+ NEW Metal2 ( 217840 250320 ) ( * 276080 )
+ NEW Metal1 ( 217840 276080 ) Via1_VV
+ NEW Metal2 ( 216720 92400 ) Via2_VH
+ NEW Metal1 ( 449680 91280 ) Via1_HV
+ NEW Metal2 ( 449680 92400 ) Via2_VH
+ NEW Metal1 ( 436240 92400 ) Via1_VV
+ NEW Metal2 ( 436240 92400 ) Via2_VH
+ NEW Metal2 ( 436240 92400 ) RECT ( -280 -660 280 0 )
+ NEW Metal3 ( 436240 92400 ) RECT ( -1040 -280 0 280 ) ;
+ - _0009_ ( _1367_ D ) ( _0869_ ZN ) + USE SIGNAL
+ + ROUTED Metal3 ( 362320 283920 ) ( 408240 * )
+ NEW Metal2 ( 408240 283920 ) ( * 285040 )
+ NEW Metal1 ( 362320 283920 ) Via1_VV
+ NEW Metal2 ( 362320 283920 ) Via2_VH
+ NEW Metal2 ( 408240 283920 ) Via2_VH
+ NEW Metal1 ( 408240 285040 ) Via1_HV
+ NEW Metal2 ( 362320 283920 ) RECT ( -280 -660 280 0 ) ;
+ - _0010_ ( ANTENNA__1368__D I ) ( _1368_ D ) ( _0871_ Z ) + USE SIGNAL
+ + ROUTED Metal2 ( 137200 201600 ) ( * 221200 )
+ NEW Metal2 ( 139440 91280 ) ( 140560 * )
+ NEW Metal2 ( 140560 91280 ) ( * 201600 )
+ NEW Metal2 ( 137200 201600 ) ( 140560 * )
+ NEW Metal3 ( 140560 92400 ) ( 156240 * )
+ NEW Metal1 ( 137200 221200 ) Via1_VV
+ NEW Metal1 ( 139440 91280 ) Via1_HV
+ NEW Metal1 ( 156240 92400 ) Via1_VV
+ NEW Metal2 ( 156240 92400 ) Via2_VH
+ NEW Metal2 ( 140560 92400 ) Via2_VH
+ NEW Metal2 ( 156240 92400 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 140560 92400 ) RECT ( -280 -1040 280 0 ) ;
+ - _0011_ ( _1372_ D ) ( _0873_ Z ) + USE SIGNAL
+ + ROUTED Metal2 ( 169680 296240 ) ( * 300720 )
+ NEW Metal2 ( 169680 300720 ) ( 177520 * )
+ NEW Metal1 ( 169680 296240 ) Via1_VV
+ NEW Metal1 ( 177520 300720 ) Via1_HV ;
+ - _0012_ ( _1373_ D ) ( _0875_ Z ) + USE SIGNAL
+ + ROUTED Metal2 ( 497840 255920 ) ( * 258160 )
+ NEW Metal3 ( 477680 258160 ) ( 497840 * )
+ NEW Metal2 ( 477680 258160 ) ( * 268240 )
+ NEW Metal1 ( 497840 255920 ) Via1_HV
+ NEW Metal2 ( 497840 258160 ) Via2_VH
+ NEW Metal2 ( 477680 258160 ) Via2_VH
+ NEW Metal1 ( 477680 268240 ) Via1_VV ;
+ - _0013_ ( _1374_ D ) ( _0877_ Z ) + USE SIGNAL
+ + ROUTED Metal3 ( 486640 269360 ) ( 500080 * )
+ NEW Metal2 ( 486640 268240 ) ( * 269360 )
+ NEW Metal2 ( 486640 269360 ) Via2_VH
+ NEW Metal1 ( 500080 269360 ) Via1_HV
+ NEW Metal2 ( 500080 269360 ) Via2_VH
+ NEW Metal1 ( 486640 268240 ) Via1_VV
+ NEW Metal2 ( 500080 269360 ) RECT ( -280 -660 280 0 ) ;
+ - _0014_ ( _1375_ D ) ( _0887_ ZN ) + USE SIGNAL
+ + ROUTED Metal3 ( 251440 233520 ) ( 258160 * )
+ NEW Metal2 ( 251440 233520 ) ( * 238000 )
+ NEW Metal1 ( 258160 233520 ) Via1_VV
+ NEW Metal2 ( 258160 233520 ) Via2_VH
+ NEW Metal2 ( 251440 233520 ) Via2_VH
+ NEW Metal1 ( 251440 238000 ) Via1_HV
+ NEW Metal2 ( 258160 233520 ) RECT ( -280 -660 280 0 ) ;
+ - _0015_ ( _1376_ D ) ( _0891_ ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 267120 224560 ) ( 268240 * )
+ NEW Metal2 ( 268240 224560 ) ( * 230160 )
+ NEW Metal1 ( 267120 224560 ) Via1_HV
+ NEW Metal1 ( 268240 230160 ) Via1_VV ;
+ - _0016_ ( _1377_ D ) ( _0893_ ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 261520 249200 ) ( * 253680 )
+ NEW Metal2 ( 261520 253680 ) ( 264880 * )
+ NEW Metal1 ( 261520 249200 ) Via1_VV
+ NEW Metal1 ( 264880 253680 ) Via1_HV ;
+ - _0017_ ( _1378_ D ) ( _0896_ ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 185360 257040 ) ( * 261520 )
+ NEW Metal2 ( 185360 257040 ) ( 188720 * )
+ NEW Metal1 ( 185360 261520 ) Via1_HV
+ NEW Metal1 ( 188720 257040 ) Via1_VV ;
+ - _0018_ ( _1379_ D ) ( _0898_ ZN ) + USE SIGNAL
+ + ROUTED Metal3 ( 157360 249200 ) ( 187600 * )
+ NEW Metal2 ( 157360 249200 ) ( * 253680 )
+ NEW Metal1 ( 187600 249200 ) Via1_VV
+ NEW Metal2 ( 187600 249200 ) Via2_VH
+ NEW Metal2 ( 157360 249200 ) Via2_VH
+ NEW Metal1 ( 157360 253680 ) Via1_HV
+ NEW Metal2 ( 187600 249200 ) RECT ( -280 -660 280 0 ) ;
+ - _0019_ ( _1380_ D ) ( _0901_ ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 156240 225680 ) ( * 238000 )
+ NEW Metal3 ( 156240 225680 ) ( 179760 * )
+ NEW Metal1 ( 156240 238000 ) Via1_HV
+ NEW Metal2 ( 156240 225680 ) Via2_VH
+ NEW Metal1 ( 179760 225680 ) Via1_VV
+ NEW Metal2 ( 179760 225680 ) Via2_VH
+ NEW Metal2 ( 179760 225680 ) RECT ( -280 -660 280 0 ) ;
+ - _0020_ ( _1381_ D ) ( _0903_ ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 146160 216720 ) ( * 221200 )
+ NEW Metal3 ( 146160 221200 ) ( 169680 * )
+ NEW Metal1 ( 146160 216720 ) Via1_HV
+ NEW Metal2 ( 146160 221200 ) Via2_VH
+ NEW Metal1 ( 169680 221200 ) Via1_VV
+ NEW Metal2 ( 169680 221200 ) Via2_VH
+ NEW Metal2 ( 169680 221200 ) RECT ( -280 -660 280 0 ) ;
+ - _0021_ ( _1382_ D ) ( _0906_ ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 168560 193200 ) ( * 206640 )
+ NEW Metal3 ( 168560 206640 ) ( 185360 * )
+ NEW Metal1 ( 168560 193200 ) Via1_HV
+ NEW Metal2 ( 168560 206640 ) Via2_VH
+ NEW Metal1 ( 185360 206640 ) Via1_VV
+ NEW Metal2 ( 185360 206640 ) Via2_VH
+ NEW Metal2 ( 185360 206640 ) RECT ( -280 -660 280 0 ) ;
+ - _0022_ ( _1383_ D ) ( _0908_ ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 171920 177520 ) ( * 189840 )
+ NEW Metal3 ( 171920 189840 ) ( 196560 * )
+ NEW Metal1 ( 171920 177520 ) Via1_HV
+ NEW Metal2 ( 171920 189840 ) Via2_VH
+ NEW Metal1 ( 196560 189840 ) Via1_VV
+ NEW Metal2 ( 196560 189840 ) Via2_VH
+ NEW Metal2 ( 196560 189840 ) RECT ( -280 -660 280 0 ) ;
+ - _0023_ ( _1384_ D ) ( _0910_ ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 204400 169680 ) ( * 177520 )
+ NEW Metal1 ( 204400 169680 ) Via1_HV
+ NEW Metal1 ( 204400 177520 ) Via1_HV ;
+ - _0024_ ( _1385_ D ) ( _0931_ ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 99120 146160 ) ( 100240 * )
+ NEW Metal2 ( 100240 146160 ) ( * 152880 )
+ NEW Metal3 ( 100240 152880 ) ( 105840 * )
+ NEW Metal1 ( 99120 146160 ) Via1_HV
+ NEW Metal2 ( 100240 152880 ) Via2_VH
+ NEW Metal1 ( 105840 152880 ) Via1_VV
+ NEW Metal2 ( 105840 152880 ) Via2_VH
+ NEW Metal2 ( 105840 152880 ) RECT ( -280 -660 280 0 ) ;
+ - _0025_ ( _1386_ D ) ( _0933_ ZN ) + USE SIGNAL
+ + ROUTED Metal3 ( 111440 214480 ) ( 118160 * )
+ NEW Metal2 ( 118160 210000 ) ( * 214480 )
+ NEW Metal1 ( 111440 214480 ) Via1_HV
+ NEW Metal2 ( 111440 214480 ) Via2_VH
+ NEW Metal2 ( 118160 214480 ) Via2_VH
+ NEW Metal1 ( 118160 210000 ) Via1_VV
+ NEW Metal2 ( 111440 214480 ) RECT ( -280 -660 280 0 ) ;
+ - _0026_ ( _1387_ D ) ( _0936_ ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 128240 183120 ) ( * 186480 )
+ NEW Metal3 ( 128240 183120 ) ( 156240 * )
+ NEW Metal1 ( 128240 186480 ) Via1_VV
+ NEW Metal2 ( 128240 183120 ) Via2_VH
+ NEW Metal1 ( 156240 183120 ) Via1_HV
+ NEW Metal2 ( 156240 183120 ) Via2_VH
+ NEW Metal2 ( 156240 183120 ) RECT ( -280 -660 280 0 ) ;
+ - _0027_ ( _1388_ D ) ( _0939_ ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 124880 154000 ) ( * 159600 )
+ NEW Metal2 ( 120400 159600 ) ( 124880 * )
+ NEW Metal2 ( 120400 159600 ) ( * 170800 )
+ NEW Metal1 ( 124880 154000 ) Via1_HV
+ NEW Metal1 ( 120400 170800 ) Via1_VV ;
+ - _0028_ ( _1389_ D ) ( _0942_ ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 84560 161840 ) ( 85680 * )
+ NEW Metal2 ( 84560 161840 ) ( * 166320 )
+ NEW Metal1 ( 85680 161840 ) Via1_HV
+ NEW Metal1 ( 84560 166320 ) Via1_VV ;
+ - _0029_ ( _1390_ D ) ( _0945_ ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 54320 154000 ) ( * 159600 )
+ NEW Metal2 ( 54320 159600 ) ( 58800 * )
+ NEW Metal1 ( 54320 154000 ) Via1_HV
+ NEW Metal1 ( 58800 159600 ) Via1_VV ;
+ - _0030_ ( _1391_ D ) ( _0947_ ZN ) + USE SIGNAL
+ + ROUTED Metal3 ( 39760 178640 ) ( 57680 * )
+ NEW Metal2 ( 39760 178640 ) ( * 183120 )
+ NEW Metal1 ( 57680 178640 ) Via1_VV
+ NEW Metal2 ( 57680 178640 ) Via2_VH
+ NEW Metal2 ( 39760 178640 ) Via2_VH
+ NEW Metal1 ( 39760 183120 ) Via1_HV
+ NEW Metal2 ( 57680 178640 ) RECT ( -280 -660 280 0 ) ;
+ - _0031_ ( _1392_ D ) ( _0950_ ZN ) + USE SIGNAL
+ + ROUTED Metal3 ( 40880 202160 ) ( 72240 * )
+ NEW Metal2 ( 40880 201040 ) ( * 202160 )
+ NEW Metal1 ( 72240 202160 ) Via1_VV
+ NEW Metal2 ( 72240 202160 ) Via2_VH
+ NEW Metal2 ( 40880 202160 ) Via2_VH
+ NEW Metal1 ( 40880 201040 ) Via1_HV
+ NEW Metal2 ( 72240 202160 ) RECT ( -280 0 280 660 ) ;
+ - _0032_ ( _1393_ D ) ( _0954_ ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 74480 216720 ) ( * 222320 )
+ NEW Metal1 ( 74480 216720 ) Via1_VV
+ NEW Metal1 ( 74480 222320 ) Via1_HV ;
+ - _0033_ ( _1394_ D ) ( _0957_ ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 26320 224560 ) ( * 229040 )
+ NEW Metal3 ( 26320 229040 ) ( 45360 * )
+ NEW Metal1 ( 26320 224560 ) Via1_HV
+ NEW Metal2 ( 26320 229040 ) Via2_VH
+ NEW Metal1 ( 45360 229040 ) Via1_VV
+ NEW Metal2 ( 45360 229040 ) Via2_VH
+ NEW Metal2 ( 45360 229040 ) RECT ( -280 0 280 660 ) ;
+ - _0034_ ( _1395_ D ) ( _0960_ ZN ) + USE SIGNAL
+ + ROUTED Metal3 ( 26320 245840 ) ( 53200 * )
+ NEW Metal1 ( 26320 245840 ) Via1_HV
+ NEW Metal2 ( 26320 245840 ) Via2_VH
+ NEW Metal1 ( 53200 245840 ) Via1_VV
+ NEW Metal2 ( 53200 245840 ) Via2_VH
+ NEW Metal2 ( 26320 245840 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 53200 245840 ) RECT ( -280 -660 280 0 ) ;
+ - _0035_ ( _1396_ D ) ( _0964_ ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 65520 248080 ) ( * 253680 )
+ NEW Metal1 ( 65520 248080 ) Via1_VV
+ NEW Metal1 ( 65520 253680 ) Via1_HV ;
+ - _0036_ ( _1397_ D ) ( _0966_ ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 98000 261520 ) ( * 269360 )
+ NEW Metal2 ( 91280 269360 ) ( 98000 * )
+ NEW Metal1 ( 98000 261520 ) Via1_HV
+ NEW Metal1 ( 91280 269360 ) Via1_HV ;
+ - _0037_ ( _1398_ D ) ( _0970_ ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 126000 241360 ) ( * 261520 )
+ NEW Metal3 ( 126000 261520 ) ( 139440 * )
+ NEW Metal1 ( 126000 241360 ) Via1_VV
+ NEW Metal2 ( 126000 261520 ) Via2_VH
+ NEW Metal1 ( 139440 261520 ) Via1_HV
+ NEW Metal2 ( 139440 261520 ) Via2_VH
+ NEW Metal2 ( 139440 261520 ) RECT ( -280 -660 280 0 ) ;
+ - _0038_ ( _1399_ D ) ( _0973_ ZN ) + USE SIGNAL
+ + ROUTED Metal3 ( 129360 271600 ) ( 145040 * )
+ NEW Metal2 ( 129360 271600 ) ( * 276080 )
+ NEW Metal1 ( 145040 271600 ) Via1_HV
+ NEW Metal2 ( 145040 271600 ) Via2_VH
+ NEW Metal2 ( 129360 271600 ) Via2_VH
+ NEW Metal1 ( 129360 276080 ) Via1_VV
+ NEW Metal2 ( 145040 271600 ) RECT ( -280 -660 280 0 ) ;
+ - _0039_ ( _1400_ D ) ( _0975_ ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 145040 299600 ) ( * 308560 )
+ NEW Metal2 ( 145040 308560 ) ( 150640 * )
+ NEW Metal1 ( 145040 299600 ) Via1_VV
+ NEW Metal1 ( 150640 308560 ) Via1_HV ;
+ - _0040_ ( _1401_ D ) ( _0978_ ZN ) + USE SIGNAL
+ + ROUTED Metal3 ( 92400 287280 ) ( 101360 * )
+ NEW Metal2 ( 101360 287280 ) ( * 300720 )
+ NEW Metal1 ( 92400 287280 ) Via1_HV
+ NEW Metal2 ( 92400 287280 ) Via2_VH
+ NEW Metal2 ( 101360 287280 ) Via2_VH
+ NEW Metal1 ( 101360 300720 ) Via1_VV
+ NEW Metal2 ( 92400 287280 ) RECT ( -280 -660 280 0 ) ;
+ - _0041_ ( _1402_ D ) ( _0981_ ZN ) + USE SIGNAL
+ + ROUTED Metal3 ( 129360 332080 ) ( 158480 * )
+ NEW Metal1 ( 129360 332080 ) Via1_VV
+ NEW Metal2 ( 129360 332080 ) Via2_VH
+ NEW Metal1 ( 158480 332080 ) Via1_HV
+ NEW Metal2 ( 158480 332080 ) Via2_VH
+ NEW Metal2 ( 129360 332080 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 158480 332080 ) RECT ( -280 -660 280 0 ) ;
+ - _0042_ ( _1403_ D ) ( _0984_ ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 145040 357840 ) ( * 362320 )
+ NEW Metal2 ( 138320 362320 ) ( 145040 * )
+ NEW Metal1 ( 145040 357840 ) Via1_HV
+ NEW Metal1 ( 138320 362320 ) Via1_VV ;
+ - _0043_ ( _1404_ D ) ( _0987_ ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 96880 346640 ) ( 99120 * )
+ NEW Metal2 ( 99120 346640 ) ( * 363440 )
+ NEW Metal1 ( 96880 346640 ) Via1_VV
+ NEW Metal1 ( 99120 363440 ) Via1_HV ;
+ - _0044_ ( _1405_ D ) ( _0991_ ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 82320 365680 ) ( * 371280 )
+ NEW Metal2 ( 82320 365680 ) ( 84560 * )
+ NEW Metal1 ( 82320 371280 ) Via1_HV
+ NEW Metal1 ( 84560 365680 ) Via1_HV ;
+ - _0045_ ( _1406_ D ) ( _0993_ ZN ) + USE SIGNAL
+ + ROUTED Metal3 ( 34160 365680 ) ( 45360 * )
+ NEW Metal2 ( 34160 365680 ) ( * 371280 )
+ NEW Metal1 ( 45360 365680 ) Via1_VV
+ NEW Metal2 ( 45360 365680 ) Via2_VH
+ NEW Metal2 ( 34160 365680 ) Via2_VH
+ NEW Metal1 ( 34160 371280 ) Via1_HV
+ NEW Metal2 ( 45360 365680 ) RECT ( -280 -660 280 0 ) ;
+ - _0046_ ( _1407_ D ) ( _0996_ ZN ) + USE SIGNAL
+ + ROUTED Metal3 ( 29680 342160 ) ( 58800 * )
+ NEW Metal2 ( 58800 342160 ) ( * 346640 )
+ NEW Metal1 ( 29680 342160 ) Via1_HV
+ NEW Metal2 ( 29680 342160 ) Via2_VH
+ NEW Metal2 ( 58800 342160 ) Via2_VH
+ NEW Metal1 ( 58800 346640 ) Via1_VV
+ NEW Metal2 ( 29680 342160 ) RECT ( -280 -660 280 0 ) ;
+ - _0047_ ( _1408_ D ) ( _1002_ Z ) + USE SIGNAL
+ + ROUTED Metal2 ( 25200 326480 ) ( 26320 * )
+ NEW Metal2 ( 25200 326480 ) ( * 330960 )
+ NEW Metal1 ( 26320 326480 ) Via1_HV
+ NEW Metal1 ( 25200 330960 ) Via1_VV ;
+ - _0048_ ( _1409_ D ) ( _1005_ ZN ) + USE SIGNAL
+ + ROUTED Metal3 ( 26320 300720 ) ( 80080 * )
+ NEW Metal2 ( 80080 300720 ) ( * 308560 )
+ NEW Metal1 ( 26320 300720 ) Via1_HV
+ NEW Metal2 ( 26320 300720 ) Via2_VH
+ NEW Metal2 ( 80080 300720 ) Via2_VH
+ NEW Metal1 ( 80080 308560 ) Via1_VV
+ NEW Metal2 ( 26320 300720 ) RECT ( -280 -660 280 0 ) ;
+ - _0049_ ( _1410_ D ) ( _1008_ ZN ) + USE SIGNAL
+ + ROUTED Metal3 ( 49840 279440 ) ( 62160 * )
+ NEW Metal2 ( 62160 279440 ) ( * 283920 )
+ NEW Metal1 ( 49840 279440 ) Via1_HV
+ NEW Metal2 ( 49840 279440 ) Via2_VH
+ NEW Metal2 ( 62160 279440 ) Via2_VH
+ NEW Metal1 ( 62160 283920 ) Via1_VV
+ NEW Metal2 ( 49840 279440 ) RECT ( -280 -660 280 0 ) ;
+ - _0050_ ( _1411_ D ) ( _1011_ Z ) + USE SIGNAL
+ + ROUTED Metal3 ( 323120 238000 ) ( 336560 * )
+ NEW Metal1 ( 323120 238000 ) Via1_VV
+ NEW Metal2 ( 323120 238000 ) Via2_VH
+ NEW Metal1 ( 336560 238000 ) Via1_HV
+ NEW Metal2 ( 336560 238000 ) Via2_VH
+ NEW Metal2 ( 323120 238000 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 336560 238000 ) RECT ( -280 -660 280 0 ) ;
+ - _0051_ ( _1412_ D ) ( _1013_ Z ) + USE SIGNAL
+ + ROUTED Metal3 ( 320880 222320 ) ( 337680 * )
+ NEW Metal1 ( 320880 222320 ) Via1_VV
+ NEW Metal2 ( 320880 222320 ) Via2_VH
+ NEW Metal1 ( 337680 222320 ) Via1_HV
+ NEW Metal2 ( 337680 222320 ) Via2_VH
+ NEW Metal2 ( 320880 222320 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 337680 222320 ) RECT ( -280 -660 280 0 ) ;
+ - _0052_ ( _1413_ D ) ( _1015_ Z ) + USE SIGNAL
+ + ROUTED Metal2 ( 315280 268240 ) ( * 269360 )
+ NEW Metal3 ( 315280 269360 ) ( 328720 * )
+ NEW Metal1 ( 315280 268240 ) Via1_VV
+ NEW Metal2 ( 315280 269360 ) Via2_VH
+ NEW Metal1 ( 328720 269360 ) Via1_HV
+ NEW Metal2 ( 328720 269360 ) Via2_VH
+ NEW Metal2 ( 328720 269360 ) RECT ( -280 -660 280 0 ) ;
+ - _0053_ ( _1414_ D ) ( _1017_ Z ) + USE SIGNAL
+ + ROUTED Metal2 ( 306320 232400 ) ( 307440 * )
+ NEW Metal2 ( 306320 232400 ) ( * 248080 )
+ NEW Metal1 ( 307440 232400 ) Via1_HV
+ NEW Metal1 ( 306320 248080 ) Via1_VV ;
+ - _0054_ ( _1415_ D ) ( _1020_ Z ) + USE SIGNAL
+ + ROUTED Metal3 ( 288400 263760 ) ( 298480 * )
+ NEW Metal2 ( 288400 263760 ) ( * 268240 )
+ NEW Metal1 ( 298480 263760 ) Via1_HV
+ NEW Metal2 ( 298480 263760 ) Via2_VH
+ NEW Metal2 ( 288400 263760 ) Via2_VH
+ NEW Metal1 ( 288400 268240 ) Via1_VV
+ NEW Metal2 ( 298480 263760 ) RECT ( -280 -660 280 0 ) ;
+ - _0055_ ( _1416_ D ) ( _1022_ Z ) + USE SIGNAL
+ + ROUTED Metal2 ( 344400 253680 ) ( * 261520 )
+ NEW Metal3 ( 317520 253680 ) ( 344400 * )
+ NEW Metal1 ( 317520 253680 ) Via1_VV
+ NEW Metal2 ( 317520 253680 ) Via2_VH
+ NEW Metal2 ( 344400 253680 ) Via2_VH
+ NEW Metal1 ( 344400 261520 ) Via1_HV
+ NEW Metal2 ( 317520 253680 ) RECT ( -280 -660 280 0 ) ;
+ - _0056_ ( _1417_ D ) ( _1025_ ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 236880 271600 ) ( 246960 * )
+ NEW Metal2 ( 246960 271600 ) ( * 300720 )
+ NEW Metal2 ( 234640 225680 ) ( * 227920 )
+ NEW Metal2 ( 234640 227920 ) ( 236880 * )
+ NEW Metal2 ( 236880 227920 ) ( * 271600 )
+ NEW Metal1 ( 246960 300720 ) Via1_HV
+ NEW Metal1 ( 234640 225680 ) Via1_VV ;
+ - _0057_ ( _1418_ D ) ( _1027_ ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 230160 249200 ) ( * 285040 )
+ NEW Metal1 ( 230160 285040 ) Via1_HV
+ NEW Metal1 ( 230160 249200 ) Via1_VV ;
+ - _0058_ ( _1419_ D ) ( _1032_ ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 225680 221200 ) ( * 261520 )
+ NEW Metal1 ( 225680 221200 ) Via1_VV
+ NEW Metal1 ( 225680 261520 ) Via1_HV ;
+ - _0059_ ( _1420_ D ) ( _1034_ ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 264880 285040 ) ( 266000 * )
+ NEW Metal3 ( 246960 225680 ) ( 266000 * )
+ NEW Metal2 ( 266000 225680 ) ( * 285040 )
+ NEW Metal1 ( 264880 285040 ) Via1_HV
+ NEW Metal1 ( 246960 225680 ) Via1_VV
+ NEW Metal2 ( 246960 225680 ) Via2_VH
+ NEW Metal2 ( 266000 225680 ) Via2_VH
+ NEW Metal2 ( 246960 225680 ) RECT ( -280 -660 280 0 ) ;
+ - _0060_ ( _1421_ D ) ( _1036_ ZN ) + USE SIGNAL
+ + ROUTED Metal3 ( 334320 91280 ) ( 344400 * )
+ NEW Metal2 ( 334320 91280 ) ( * 95760 )
+ NEW Metal1 ( 344400 91280 ) Via1_HV
+ NEW Metal2 ( 344400 91280 ) Via2_VH
+ NEW Metal2 ( 334320 91280 ) Via2_VH
+ NEW Metal1 ( 334320 95760 ) Via1_VV
+ NEW Metal2 ( 344400 91280 ) RECT ( -280 -660 280 0 ) ;
+ - _0061_ ( _1422_ D ) ( _1038_ ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 344400 99120 ) ( 346640 * )
+ NEW Metal2 ( 346640 83440 ) ( * 99120 )
+ NEW Metal1 ( 346640 83440 ) Via1_HV
+ NEW Metal1 ( 344400 99120 ) Via1_HV ;
+ - _0062_ ( _1423_ D ) ( _1040_ ZN ) + USE SIGNAL
+ + ROUTED Metal3 ( 332080 112560 ) ( 346640 * )
+ NEW Metal1 ( 346640 112560 ) Via1_HV
+ NEW Metal2 ( 346640 112560 ) Via2_VH
+ NEW Metal1 ( 332080 112560 ) Via1_VV
+ NEW Metal2 ( 332080 112560 ) Via2_VH
+ NEW Metal2 ( 346640 112560 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 332080 112560 ) RECT ( -280 -660 280 0 ) ;
+ - _0063_ ( _1424_ D ) ( _1041_ ZN ) + USE SIGNAL
+ + ROUTED Metal3 ( 337680 104720 ) ( 381360 * )
+ NEW Metal1 ( 337680 104720 ) Via1_HV
+ NEW Metal2 ( 337680 104720 ) Via2_VH
+ NEW Metal1 ( 381360 104720 ) Via1_HV
+ NEW Metal2 ( 381360 104720 ) Via2_VH
+ NEW Metal2 ( 337680 104720 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 381360 104720 ) RECT ( -280 -660 280 0 ) ;
+ - _0064_ ( _1425_ D ) ( _1043_ ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 371280 122640 ) ( * 127120 )
+ NEW Metal3 ( 319760 127120 ) ( 371280 * )
+ NEW Metal1 ( 371280 122640 ) Via1_HV
+ NEW Metal2 ( 371280 127120 ) Via2_VH
+ NEW Metal1 ( 319760 127120 ) Via1_VV
+ NEW Metal2 ( 319760 127120 ) Via2_VH
+ NEW Metal2 ( 319760 127120 ) RECT ( -280 -660 280 0 ) ;
+ - _0065_ ( _1426_ D ) ( _1046_ ZN ) + USE SIGNAL
+ + ROUTED Metal3 ( 328720 138320 ) ( 360080 * )
+ NEW Metal2 ( 328720 138320 ) ( * 150640 )
+ NEW Metal1 ( 360080 138320 ) Via1_HV
+ NEW Metal2 ( 360080 138320 ) Via2_VH
+ NEW Metal2 ( 328720 138320 ) Via2_VH
+ NEW Metal1 ( 328720 150640 ) Via1_VV
+ NEW Metal2 ( 360080 138320 ) RECT ( -280 -660 280 0 ) ;
+ - _0066_ ( _1427_ D ) ( _1048_ ZN ) + USE SIGNAL
+ + ROUTED Metal3 ( 337680 139440 ) ( 344400 * )
+ NEW Metal2 ( 344400 139440 ) ( * 143920 )
+ NEW Metal1 ( 337680 139440 ) Via1_VV
+ NEW Metal2 ( 337680 139440 ) Via2_VH
+ NEW Metal2 ( 344400 139440 ) Via2_VH
+ NEW Metal1 ( 344400 143920 ) Via1_HV
+ NEW Metal2 ( 337680 139440 ) RECT ( -280 -660 280 0 ) ;
+ - _0067_ ( _1428_ D ) ( _1050_ ZN ) + USE SIGNAL
+ + ROUTED Metal3 ( 327600 168560 ) ( 347760 * )
+ NEW Metal1 ( 347760 168560 ) Via1_HV
+ NEW Metal2 ( 347760 168560 ) Via2_VH
+ NEW Metal1 ( 327600 168560 ) Via1_VV
+ NEW Metal2 ( 327600 168560 ) Via2_VH
+ NEW Metal2 ( 347760 168560 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 327600 168560 ) RECT ( -280 -660 280 0 ) ;
+ - _0068_ ( _1429_ D ) ( _1052_ ZN ) + USE SIGNAL
+ + ROUTED Metal3 ( 335440 193200 ) ( 344400 * )
+ NEW Metal2 ( 344400 193200 ) ( * 198800 )
+ NEW Metal1 ( 335440 193200 ) Via1_VV
+ NEW Metal2 ( 335440 193200 ) Via2_VH
+ NEW Metal2 ( 344400 193200 ) Via2_VH
+ NEW Metal1 ( 344400 198800 ) Via1_HV
+ NEW Metal2 ( 335440 193200 ) RECT ( -280 -660 280 0 ) ;
+ - _0069_ ( _1430_ D ) ( _1054_ ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 336560 178640 ) ( * 182000 )
+ NEW Metal3 ( 336560 182000 ) ( 351120 * )
+ NEW Metal2 ( 351120 182000 ) ( * 183120 )
+ NEW Metal1 ( 336560 178640 ) Via1_VV
+ NEW Metal2 ( 336560 182000 ) Via2_VH
+ NEW Metal2 ( 351120 182000 ) Via2_VH
+ NEW Metal1 ( 351120 183120 ) Via1_HV ;
+ - _0070_ ( _1431_ D ) ( _1063_ ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 283920 169680 ) ( 285040 * )
+ NEW Metal2 ( 285040 169680 ) ( * 176400 )
+ NEW Metal2 ( 285040 176400 ) ( 286160 * )
+ NEW Metal2 ( 286160 176400 ) ( * 184240 )
+ NEW Metal2 ( 285040 184240 ) ( 286160 * )
+ NEW Metal2 ( 285040 184240 ) ( * 186480 )
+ NEW Metal1 ( 283920 169680 ) Via1_HV
+ NEW Metal1 ( 285040 186480 ) Via1_HV ;
+ - _0071_ ( _1432_ D ) ( _1066_ ZN ) + USE SIGNAL
+ + ROUTED Metal3 ( 264880 91280 ) ( 274960 * )
+ NEW Metal2 ( 274960 91280 ) ( * 95760 )
+ NEW Metal1 ( 264880 91280 ) Via1_HV
+ NEW Metal2 ( 264880 91280 ) Via2_VH
+ NEW Metal2 ( 274960 91280 ) Via2_VH
+ NEW Metal1 ( 274960 95760 ) Via1_VV
+ NEW Metal2 ( 264880 91280 ) RECT ( -280 -660 280 0 ) ;
+ - _0072_ ( _1433_ D ) ( _1069_ ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 231280 99120 ) ( * 103600 )
+ NEW Metal2 ( 231280 103600 ) ( 234640 * )
+ NEW Metal1 ( 231280 99120 ) Via1_HV
+ NEW Metal1 ( 234640 103600 ) Via1_VV ;
+ - _0073_ ( _1434_ D ) ( _1071_ ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 305200 91280 ) ( * 99120 )
+ NEW Metal3 ( 298480 99120 ) ( 305200 * )
+ NEW Metal2 ( 298480 99120 ) ( * 104720 )
+ NEW Metal1 ( 305200 91280 ) Via1_HV
+ NEW Metal2 ( 305200 99120 ) Via2_VH
+ NEW Metal2 ( 298480 99120 ) Via2_VH
+ NEW Metal1 ( 298480 104720 ) Via1_HV ;
+ - _0074_ ( _1435_ D ) ( _1074_ ZN ) + USE SIGNAL
+ + ROUTED Metal3 ( 262640 123760 ) ( 290640 * )
+ NEW Metal2 ( 262640 123760 ) ( * 128240 )
+ NEW Metal1 ( 290640 123760 ) Via1_VV
+ NEW Metal2 ( 290640 123760 ) Via2_VH
+ NEW Metal2 ( 262640 123760 ) Via2_VH
+ NEW Metal1 ( 262640 128240 ) Via1_HV
+ NEW Metal2 ( 290640 123760 ) RECT ( -280 -660 280 0 ) ;
+ - _0075_ ( _1436_ D ) ( _1077_ ZN ) + USE SIGNAL
+ + ROUTED Metal3 ( 210000 115920 ) ( 221200 * )
+ NEW Metal2 ( 210000 115920 ) ( * 120400 )
+ NEW Metal1 ( 221200 115920 ) Via1_VV
+ NEW Metal2 ( 221200 115920 ) Via2_VH
+ NEW Metal2 ( 210000 115920 ) Via2_VH
+ NEW Metal1 ( 210000 120400 ) Via1_HV
+ NEW Metal2 ( 221200 115920 ) RECT ( -280 -660 280 0 ) ;
+ - _0076_ ( _1437_ D ) ( _1081_ ZN ) + USE SIGNAL
+ + ROUTED Metal3 ( 213360 138320 ) ( 218960 * )
+ NEW Metal2 ( 218960 138320 ) ( * 146160 )
+ NEW Metal1 ( 213360 138320 ) Via1_HV
+ NEW Metal2 ( 213360 138320 ) Via2_VH
+ NEW Metal2 ( 218960 138320 ) Via2_VH
+ NEW Metal1 ( 218960 146160 ) Via1_HV
+ NEW Metal2 ( 213360 138320 ) RECT ( -280 -660 280 0 ) ;
+ - _0077_ ( _1438_ D ) ( _1086_ ZN ) + USE SIGNAL
+ + ROUTED Metal3 ( 232400 147280 ) ( 240240 * )
+ NEW Metal2 ( 232400 159600 ) ( 233520 * )
+ NEW Metal2 ( 232400 147280 ) ( * 159600 )
+ NEW Metal1 ( 240240 147280 ) Via1_VV
+ NEW Metal2 ( 240240 147280 ) Via2_VH
+ NEW Metal2 ( 232400 147280 ) Via2_VH
+ NEW Metal1 ( 233520 159600 ) Via1_HV
+ NEW Metal2 ( 240240 147280 ) RECT ( -280 -660 280 0 ) ;
+ - _0078_ ( _1439_ D ) ( _1090_ ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 240240 178640 ) ( * 190960 )
+ NEW Metal2 ( 236880 190960 ) ( 240240 * )
+ NEW Metal1 ( 240240 178640 ) Via1_VV
+ NEW Metal1 ( 236880 190960 ) Via1_HV ;
+ - _0079_ ( _1440_ D ) ( _1093_ ZN ) + USE SIGNAL
+ + ROUTED Metal3 ( 281680 201040 ) ( 294000 * )
+ NEW Metal2 ( 281680 201040 ) ( * 202160 )
+ NEW Metal1 ( 281680 202160 ) Via1_VV
+ NEW Metal1 ( 294000 201040 ) Via1_HV
+ NEW Metal2 ( 294000 201040 ) Via2_VH
+ NEW Metal2 ( 281680 201040 ) Via2_VH
+ NEW Metal2 ( 294000 201040 ) RECT ( -280 -660 280 0 ) ;
+ - _0080_ ( ANTENNA__1441__D I ) ( _1441_ D ) ( _1095_ ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 223440 288400 ) ( * 299600 )
+ NEW Metal3 ( 223440 287280 ) ( * 288400 )
+ NEW Metal2 ( 519120 299600 ) ( 520240 * )
+ NEW Metal2 ( 519120 287280 ) ( * 299600 )
+ NEW Metal3 ( 519120 292880 ) ( 530320 * )
+ NEW Metal3 ( 223440 287280 ) ( 519120 * )
+ NEW Metal1 ( 223440 299600 ) Via1_VV
+ NEW Metal2 ( 223440 288400 ) Via2_VH
+ NEW Metal1 ( 520240 299600 ) Via1_VV
+ NEW Metal2 ( 519120 287280 ) Via2_VH
+ NEW Metal1 ( 530320 292880 ) Via1_HV
+ NEW Metal2 ( 530320 292880 ) Via2_VH
+ NEW Metal2 ( 519120 292880 ) Via2_VH
+ NEW Metal2 ( 530320 292880 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 519120 292880 ) RECT ( -280 -1040 280 0 ) ;
+ - _0081_ ( _1442_ D ) ( _1111_ ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 407120 512400 ) ( * 521360 )
+ NEW Metal2 ( 406000 521360 ) ( 407120 * )
+ NEW Metal1 ( 407120 512400 ) Via1_HV
+ NEW Metal1 ( 406000 521360 ) Via1_HV ;
+ - _0082_ ( _1443_ D ) ( _1116_ ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 417200 496720 ) ( * 503440 )
+ NEW Metal3 ( 417200 496720 ) ( 437360 * )
+ NEW Metal1 ( 437360 496720 ) Via1_HV
+ NEW Metal2 ( 437360 496720 ) Via2_VH
+ NEW Metal2 ( 417200 496720 ) Via2_VH
+ NEW Metal1 ( 417200 503440 ) Via1_VV
+ NEW Metal2 ( 437360 496720 ) RECT ( -280 -660 280 0 ) ;
+ - _0083_ ( _1444_ D ) ( _1120_ ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 355600 514640 ) ( * 516880 )
+ NEW Metal2 ( 355600 516880 ) ( 358960 * )
+ NEW Metal2 ( 358960 516880 ) ( * 519120 )
+ NEW Metal2 ( 358960 519120 ) ( 361200 * )
+ NEW Metal1 ( 355600 514640 ) Via1_HV
+ NEW Metal1 ( 361200 519120 ) Via1_VV ;
+ - _0084_ ( _1445_ D ) ( _1125_ ZN ) + USE SIGNAL
+ + ROUTED Metal3 ( 332080 500080 ) ( 344400 * )
+ NEW Metal2 ( 332080 500080 ) ( * 504560 )
+ NEW Metal1 ( 344400 500080 ) Via1_VV
+ NEW Metal2 ( 344400 500080 ) Via2_VH
+ NEW Metal2 ( 332080 500080 ) Via2_VH
+ NEW Metal1 ( 332080 504560 ) Via1_HV
+ NEW Metal2 ( 344400 500080 ) RECT ( -280 -660 280 0 ) ;
+ - _0085_ ( _1446_ D ) ( _1127_ Z ) + USE SIGNAL
+ + ROUTED Metal2 ( 318640 484400 ) ( * 488880 )
+ NEW Metal2 ( 318640 484400 ) ( 322000 * )
+ NEW Metal1 ( 318640 488880 ) Via1_HV
+ NEW Metal1 ( 322000 484400 ) Via1_VV ;
+ - _0086_ ( _1447_ D ) ( _1138_ ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 383600 412720 ) ( * 420560 )
+ NEW Metal2 ( 383600 420560 ) ( 386960 * )
+ NEW Metal2 ( 386960 420560 ) ( * 425040 )
+ NEW Metal1 ( 383600 412720 ) Via1_HV
+ NEW Metal1 ( 386960 425040 ) Via1_VV ;
+ - _0087_ ( _1448_ D ) ( _1143_ ZN ) + USE SIGNAL
+ + ROUTED Metal3 ( 417200 412720 ) ( 431760 * )
+ NEW Metal2 ( 417200 412720 ) ( * 418320 )
+ NEW Metal1 ( 431760 412720 ) Via1_HV
+ NEW Metal2 ( 431760 412720 ) Via2_VH
+ NEW Metal2 ( 417200 412720 ) Via2_VH
+ NEW Metal1 ( 417200 418320 ) Via1_VV
+ NEW Metal2 ( 431760 412720 ) RECT ( -280 -660 280 0 ) ;
+ - _0088_ ( _1449_ D ) ( _1147_ ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 423920 437360 ) ( * 441840 )
+ NEW Metal3 ( 423920 441840 ) ( 438480 * )
+ NEW Metal1 ( 438480 441840 ) Via1_HV
+ NEW Metal2 ( 438480 441840 ) Via2_VH
+ NEW Metal2 ( 423920 441840 ) Via2_VH
+ NEW Metal1 ( 423920 437360 ) Via1_VV
+ NEW Metal2 ( 438480 441840 ) RECT ( -280 -660 280 0 ) ;
+ - _0089_ ( _1450_ D ) ( _1152_ ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 347760 436800 ) ( * 441840 )
+ NEW Metal2 ( 344400 436240 ) ( * 436800 )
+ NEW Metal2 ( 344400 436800 ) ( 347760 * )
+ NEW Metal1 ( 347760 441840 ) Via1_VV
+ NEW Metal1 ( 344400 436240 ) Via1_HV ;
+ - _0090_ ( _1451_ D ) ( _1155_ ZN ) + USE SIGNAL
+ + ROUTED Metal3 ( 326480 457520 ) ( 354480 * )
+ NEW Metal1 ( 326480 457520 ) Via1_HV
+ NEW Metal2 ( 326480 457520 ) Via2_VH
+ NEW Metal1 ( 354480 457520 ) Via1_VV
+ NEW Metal2 ( 354480 457520 ) Via2_VH
+ NEW Metal2 ( 326480 457520 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 354480 457520 ) RECT ( -280 -660 280 0 ) ;
+ - _0091_ ( _1452_ D ) ( _1163_ ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 455280 506800 ) ( * 512400 )
+ NEW Metal3 ( 440720 512400 ) ( 455280 * )
+ NEW Metal1 ( 455280 506800 ) Via1_HV
+ NEW Metal2 ( 455280 512400 ) Via2_VH
+ NEW Metal1 ( 440720 512400 ) Via1_HV
+ NEW Metal2 ( 440720 512400 ) Via2_VH
+ NEW Metal2 ( 440720 512400 ) RECT ( -280 -660 280 0 ) ;
+ - _0092_ ( _1453_ D ) ( _1170_ ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 441840 483280 ) ( * 487760 )
+ NEW Metal2 ( 441840 487760 ) ( 444080 * )
+ NEW Metal1 ( 441840 483280 ) Via1_HV
+ NEW Metal1 ( 444080 487760 ) Via1_VV ;
+ - _0093_ ( _1454_ D ) ( _1173_ ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 482160 515760 ) ( 483280 * )
+ NEW Metal2 ( 483280 515760 ) ( * 520240 )
+ NEW Metal1 ( 482160 515760 ) Via1_VV
+ NEW Metal1 ( 483280 520240 ) Via1_HV ;
+ - _0094_ ( _1455_ D ) ( _1178_ ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 514640 506800 ) ( * 512400 )
+ NEW Metal2 ( 514640 512400 ) ( 519120 * )
+ NEW Metal1 ( 514640 506800 ) Via1_VV
+ NEW Metal1 ( 519120 512400 ) Via1_HV ;
+ - _0095_ ( _1456_ D ) ( _1180_ Z ) + USE SIGNAL
+ + ROUTED Metal2 ( 535920 484400 ) ( * 488880 )
+ NEW Metal3 ( 535920 488880 ) ( 542640 * )
+ NEW Metal1 ( 535920 484400 ) Via1_VV
+ NEW Metal2 ( 535920 488880 ) Via2_VH
+ NEW Metal1 ( 542640 488880 ) Via1_HV
+ NEW Metal2 ( 542640 488880 ) Via2_VH
+ NEW Metal2 ( 542640 488880 ) RECT ( -280 -660 280 0 ) ;
+ - _0096_ ( _1457_ D ) ( _1191_ ZN ) + USE SIGNAL
+ + ROUTED Metal3 ( 445200 436240 ) ( 449680 * )
+ NEW Metal2 ( 449680 436240 ) ( * 449680 )
+ NEW Metal1 ( 449680 449680 ) Via1_VV
+ NEW Metal1 ( 445200 436240 ) Via1_HV
+ NEW Metal2 ( 445200 436240 ) Via2_VH
+ NEW Metal2 ( 449680 436240 ) Via2_VH
+ NEW Metal2 ( 445200 436240 ) RECT ( -280 -660 280 0 ) ;
+ - _0097_ ( _1458_ D ) ( _1194_ ZN ) + USE SIGNAL
+ + ROUTED Metal3 ( 453040 412720 ) ( 460880 * )
+ NEW Metal2 ( 453040 412720 ) ( * 418320 )
+ NEW Metal1 ( 460880 412720 ) Via1_VV
+ NEW Metal2 ( 460880 412720 ) Via2_VH
+ NEW Metal2 ( 453040 412720 ) Via2_VH
+ NEW Metal1 ( 453040 418320 ) Via1_HV
+ NEW Metal2 ( 460880 412720 ) RECT ( -280 -660 280 0 ) ;
+ - _0098_ ( _1459_ D ) ( _1199_ ZN ) + USE SIGNAL
+ + ROUTED Metal3 ( 511280 419440 ) ( 522480 * )
+ NEW Metal2 ( 511280 419440 ) ( * 425040 )
+ NEW Metal1 ( 522480 419440 ) Via1_HV
+ NEW Metal2 ( 522480 419440 ) Via2_VH
+ NEW Metal2 ( 511280 419440 ) Via2_VH
+ NEW Metal1 ( 511280 425040 ) Via1_VV
+ NEW Metal2 ( 522480 419440 ) RECT ( -280 -660 280 0 ) ;
+ - _0099_ ( _1460_ D ) ( _1203_ ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 533680 434000 ) ( 534800 * )
+ NEW Metal2 ( 534800 429520 ) ( * 434000 )
+ NEW Metal1 ( 533680 434000 ) Via1_HV
+ NEW Metal1 ( 534800 429520 ) Via1_VV ;
+ - _0100_ ( _1461_ D ) ( _1206_ ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 534800 465360 ) ( 535920 * )
+ NEW Metal2 ( 535920 456400 ) ( * 465360 )
+ NEW Metal2 ( 534800 456400 ) ( 535920 * )
+ NEW Metal1 ( 534800 465360 ) Via1_HV
+ NEW Metal1 ( 534800 456400 ) Via1_VV ;
+ - _0101_ ( _1467_ D ) ( _1214_ ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 441840 295120 ) ( * 308560 )
+ NEW Metal3 ( 441840 308560 ) ( 460880 * )
+ NEW Metal1 ( 441840 295120 ) Via1_HV
+ NEW Metal2 ( 441840 308560 ) Via2_VH
+ NEW Metal1 ( 460880 308560 ) Via1_HV
+ NEW Metal2 ( 460880 308560 ) Via2_VH
+ NEW Metal2 ( 460880 308560 ) RECT ( -280 -660 280 0 ) ;
+ - _0102_ ( _1468_ D ) ( _1219_ ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 438480 326480 ) ( * 335440 )
+ NEW Metal2 ( 438480 335440 ) ( 446320 * )
+ NEW Metal1 ( 438480 326480 ) Via1_HV
+ NEW Metal1 ( 446320 335440 ) Via1_VV ;
+ - _0103_ ( _1469_ D ) ( _1223_ ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 484400 287280 ) ( 485520 * )
+ NEW Metal2 ( 484400 287280 ) ( * 294000 )
+ NEW Metal1 ( 485520 287280 ) Via1_HV
+ NEW Metal1 ( 484400 294000 ) Via1_VV ;
+ - _0104_ ( _1470_ D ) ( _1228_ ZN ) + USE SIGNAL
+ + ROUTED Metal3 ( 509040 324240 ) ( 542640 * )
+ NEW Metal1 ( 542640 324240 ) Via1_HV
+ NEW Metal2 ( 542640 324240 ) Via2_VH
+ NEW Metal1 ( 509040 324240 ) Via1_VV
+ NEW Metal2 ( 509040 324240 ) Via2_VH
+ NEW Metal2 ( 542640 324240 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 509040 324240 ) RECT ( -280 -660 280 0 ) ;
+ - _0105_ ( _1471_ D ) ( _1230_ Z ) + USE SIGNAL
+ + ROUTED Metal3 ( 522480 342160 ) ( 549360 * )
+ NEW Metal1 ( 549360 342160 ) Via1_HV
+ NEW Metal2 ( 549360 342160 ) Via2_VH
+ NEW Metal1 ( 522480 342160 ) Via1_VV
+ NEW Metal2 ( 522480 342160 ) Via2_VH
+ NEW Metal2 ( 549360 342160 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 522480 342160 ) RECT ( -280 -660 280 0 ) ;
+ - _0106_ ( _1472_ D ) ( _1243_ ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 435120 357840 ) ( * 371280 )
+ NEW Metal3 ( 435120 371280 ) ( 447440 * )
+ NEW Metal1 ( 447440 371280 ) Via1_VV
+ NEW Metal2 ( 447440 371280 ) Via2_VH
+ NEW Metal1 ( 435120 357840 ) Via1_HV
+ NEW Metal2 ( 435120 371280 ) Via2_VH
+ NEW Metal2 ( 447440 371280 ) RECT ( -280 -660 280 0 ) ;
+ - _0107_ ( _1473_ D ) ( _1247_ ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 496720 406000 ) ( * 410480 )
+ NEW Metal2 ( 493360 410480 ) ( 496720 * )
+ NEW Metal1 ( 496720 406000 ) Via1_VV
+ NEW Metal1 ( 493360 410480 ) Via1_HV ;
+ - _0108_ ( _1474_ D ) ( _1250_ ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 447440 389200 ) ( * 390320 )
+ NEW Metal3 ( 447440 390320 ) ( 475440 * )
+ NEW Metal1 ( 447440 389200 ) Via1_HV
+ NEW Metal2 ( 447440 390320 ) Via2_VH
+ NEW Metal1 ( 475440 390320 ) Via1_VV
+ NEW Metal2 ( 475440 390320 ) Via2_VH
+ NEW Metal2 ( 475440 390320 ) RECT ( -280 0 280 660 ) ;
+ - _0109_ ( _1475_ D ) ( _1255_ ZN ) + USE SIGNAL
+ + ROUTED Metal3 ( 528080 389200 ) ( 543760 * )
+ NEW Metal2 ( 528080 389200 ) ( * 401520 )
+ NEW Metal1 ( 543760 389200 ) Via1_HV
+ NEW Metal2 ( 543760 389200 ) Via2_VH
+ NEW Metal2 ( 528080 389200 ) Via2_VH
+ NEW Metal1 ( 528080 401520 ) Via1_VV
+ NEW Metal2 ( 543760 389200 ) RECT ( -280 -660 280 0 ) ;
+ - _0110_ ( _1476_ D ) ( _1258_ ZN ) + USE SIGNAL
+ + ROUTED Metal3 ( 531440 365680 ) ( 542640 * )
+ NEW Metal2 ( 531440 365680 ) ( * 374640 )
+ NEW Metal1 ( 542640 365680 ) Via1_HV
+ NEW Metal2 ( 542640 365680 ) Via2_VH
+ NEW Metal2 ( 531440 365680 ) Via2_VH
+ NEW Metal1 ( 531440 374640 ) Via1_VV
+ NEW Metal2 ( 542640 365680 ) RECT ( -280 -660 280 0 ) ;
+ - _0111_ ( _1477_ D ) ( _1270_ ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 390320 393680 ) ( * 394800 )
+ NEW Metal3 ( 390320 394800 ) ( 407120 * )
+ NEW Metal1 ( 390320 393680 ) Via1_HV
+ NEW Metal2 ( 390320 394800 ) Via2_VH
+ NEW Metal1 ( 407120 394800 ) Via1_HV
+ NEW Metal2 ( 407120 394800 ) Via2_VH
+ NEW Metal2 ( 407120 394800 ) RECT ( -280 -660 280 0 ) ;
+ - _0112_ ( _1478_ D ) ( _1275_ ZN ) + USE SIGNAL
+ + ROUTED Metal3 ( 346640 374640 ) ( 352240 * )
+ NEW Metal2 ( 346640 374640 ) ( * 379120 )
+ NEW Metal1 ( 352240 374640 ) Via1_VV
+ NEW Metal2 ( 352240 374640 ) Via2_VH
+ NEW Metal2 ( 346640 374640 ) Via2_VH
+ NEW Metal1 ( 346640 379120 ) Via1_HV
+ NEW Metal2 ( 352240 374640 ) RECT ( -280 -660 280 0 ) ;
+ - _0113_ ( _1479_ D ) ( _1277_ ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 399280 346640 ) ( * 347760 )
+ NEW Metal3 ( 399280 347760 ) ( 428400 * )
+ NEW Metal1 ( 399280 346640 ) Via1_VV
+ NEW Metal2 ( 399280 347760 ) Via2_VH
+ NEW Metal1 ( 428400 347760 ) Via1_HV
+ NEW Metal2 ( 428400 347760 ) Via2_VH
+ NEW Metal2 ( 428400 347760 ) RECT ( -280 -660 280 0 ) ;
+ - _0114_ ( _1480_ D ) ( _1281_ ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 346640 334320 ) ( * 350000 )
+ NEW Metal3 ( 346640 350000 ) ( 355600 * )
+ NEW Metal2 ( 355600 350000 ) ( * 355600 )
+ NEW Metal1 ( 346640 334320 ) Via1_HV
+ NEW Metal2 ( 346640 350000 ) Via2_VH
+ NEW Metal2 ( 355600 350000 ) Via2_VH
+ NEW Metal1 ( 355600 355600 ) Via1_VV ;
+ - _0115_ ( _1481_ D ) ( _1286_ ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 357840 404880 ) ( * 409360 )
+ NEW Metal1 ( 357840 404880 ) Via1_HV
+ NEW Metal1 ( 357840 409360 ) Via1_VV ;
+ - _0116_ ( _1482_ D ) ( _1291_ Z ) + USE SIGNAL
+ + ROUTED Metal2 ( 311920 426160 ) ( * 434000 )
+ NEW Metal2 ( 307440 434000 ) ( 311920 * )
+ NEW Metal1 ( 311920 426160 ) Via1_VV
+ NEW Metal1 ( 307440 434000 ) Via1_HV ;
+ - _0117_ ( _1483_ D ) ( _1293_ ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 304080 390320 ) ( * 394800 )
+ NEW Metal3 ( 304080 390320 ) ( 319760 * )
+ NEW Metal2 ( 304080 390320 ) Via2_VH
+ NEW Metal1 ( 304080 394800 ) Via1_HV
+ NEW Metal1 ( 319760 390320 ) Via1_VV
+ NEW Metal2 ( 319760 390320 ) Via2_VH
+ NEW Metal2 ( 319760 390320 ) RECT ( -280 -660 280 0 ) ;
+ - _0118_ ( _1484_ D ) ( _1301_ Z ) + USE SIGNAL
+ + ROUTED Metal2 ( 267120 420560 ) ( 268240 * )
+ NEW Metal2 ( 268240 420560 ) ( * 425040 )
+ NEW Metal1 ( 267120 420560 ) Via1_HV
+ NEW Metal1 ( 268240 425040 ) Via1_VV ;
+ - _0119_ ( _1485_ D ) ( _1304_ ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 306320 456400 ) ( * 465360 )
+ NEW Metal2 ( 306320 465360 ) ( 315280 * )
+ NEW Metal1 ( 306320 456400 ) Via1_VV
+ NEW Metal1 ( 315280 465360 ) Via1_HV ;
+ - _0120_ ( _1486_ D ) ( _1307_ ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 276080 467600 ) ( * 481040 )
+ NEW Metal2 ( 273840 481040 ) ( 276080 * )
+ NEW Metal1 ( 276080 467600 ) Via1_VV
+ NEW Metal1 ( 273840 481040 ) Via1_HV ;
+ - _0121_ ( _1487_ D ) ( _1309_ ZN ) + USE SIGNAL
+ + ROUTED Metal3 ( 248080 444080 ) ( 264880 * )
+ NEW Metal2 ( 264880 444080 ) ( * 453040 )
+ NEW Metal1 ( 248080 444080 ) Via1_HV
+ NEW Metal2 ( 248080 444080 ) Via2_VH
+ NEW Metal2 ( 264880 444080 ) Via2_VH
+ NEW Metal1 ( 264880 453040 ) Via1_VV
+ NEW Metal2 ( 248080 444080 ) RECT ( -280 -660 280 0 ) ;
+ - _0122_ ( _1488_ D ) ( _1315_ ZN ) + USE SIGNAL
+ + ROUTED Metal3 ( 176400 435120 ) ( 187600 * )
+ NEW Metal2 ( 176400 435120 ) ( * 441840 )
+ NEW Metal1 ( 176400 441840 ) Via1_HV
+ NEW Metal1 ( 187600 435120 ) Via1_VV
+ NEW Metal2 ( 187600 435120 ) Via2_VH
+ NEW Metal2 ( 176400 435120 ) Via2_VH
+ NEW Metal2 ( 187600 435120 ) RECT ( -280 -660 280 0 ) ;
+ - _0123_ ( _1489_ D ) ( _1320_ Z ) + USE SIGNAL
+ + ROUTED Metal2 ( 215600 453040 ) ( * 457520 )
+ NEW Metal3 ( 215600 457520 ) ( 224560 * )
+ NEW Metal1 ( 215600 453040 ) Via1_VV
+ NEW Metal2 ( 215600 457520 ) Via2_VH
+ NEW Metal1 ( 224560 457520 ) Via1_HV
+ NEW Metal2 ( 224560 457520 ) Via2_VH
+ NEW Metal2 ( 224560 457520 ) RECT ( -280 -660 280 0 ) ;
+ - _0124_ ( _1490_ D ) ( _1322_ ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 227920 420560 ) ( 230160 * )
+ NEW Metal2 ( 230160 420560 ) ( * 432880 )
+ NEW Metal1 ( 227920 420560 ) Via1_HV
+ NEW Metal1 ( 230160 432880 ) Via1_VV ;
+ - _0125_ ( _1491_ D ) ( _1326_ ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 223440 357840 ) ( 224560 * )
+ NEW Metal2 ( 223440 357840 ) ( * 363440 )
+ NEW Metal1 ( 221200 363440 ) ( 223440 * )
+ NEW Metal2 ( 221200 363440 ) ( * 365680 )
+ NEW Metal2 ( 220080 365680 ) ( 221200 * )
+ NEW Metal1 ( 224560 357840 ) Via1_HV
+ NEW Metal1 ( 223440 363440 ) Via1_HV
+ NEW Metal1 ( 221200 363440 ) Via1_HV
+ NEW Metal1 ( 220080 365680 ) Via1_HV ;
+ - _0126_ ( _1492_ D ) ( _1330_ ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 155120 412720 ) ( * 420560 )
+ NEW Metal3 ( 155120 420560 ) ( 182000 * )
+ NEW Metal1 ( 155120 412720 ) Via1_HV
+ NEW Metal2 ( 155120 420560 ) Via2_VH
+ NEW Metal1 ( 182000 420560 ) Via1_VV
+ NEW Metal2 ( 182000 420560 ) Via2_VH
+ NEW Metal2 ( 182000 420560 ) RECT ( -280 -660 280 0 ) ;
+ - _0127_ ( _1493_ D ) ( _1334_ ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 227920 397040 ) ( 229040 * )
+ NEW Metal2 ( 227920 397040 ) ( * 401520 )
+ NEW Metal1 ( 229040 397040 ) Via1_HV
+ NEW Metal1 ( 227920 401520 ) Via1_VV ;
+ - _0128_ ( _1494_ D ) ( _1339_ Z ) + USE SIGNAL
+ + ROUTED Metal2 ( 160720 374640 ) ( * 379120 )
+ NEW Metal2 ( 158480 379120 ) ( 160720 * )
+ NEW Metal1 ( 160720 374640 ) Via1_VV
+ NEW Metal1 ( 158480 379120 ) Via1_HV ;
+ - _0129_ ( _1495_ D ) ( _1342_ ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 262640 335440 ) ( * 339920 )
+ NEW Metal2 ( 262640 339920 ) ( 264880 * )
+ NEW Metal1 ( 262640 335440 ) Via1_VV
+ NEW Metal1 ( 264880 339920 ) Via1_HV ;
+ - _0130_ ( _1496_ D ) ( _1345_ ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 239120 327600 ) ( * 335440 )
+ NEW Metal2 ( 236880 335440 ) ( 239120 * )
+ NEW Metal2 ( 236880 335440 ) ( * 347760 )
+ NEW Metal2 ( 236880 347760 ) ( 238000 * )
+ NEW Metal1 ( 239120 327600 ) Via1_VV
+ NEW Metal1 ( 238000 347760 ) Via1_HV ;
+ - _0131_ ( _1497_ D ) ( _1348_ Z ) + USE SIGNAL
+ + ROUTED Metal2 ( 166320 343280 ) ( 167440 * )
+ NEW Metal2 ( 167440 343280 ) ( * 347760 )
+ NEW Metal1 ( 166320 343280 ) Via1_VV
+ NEW Metal1 ( 167440 347760 ) Via1_HV ;
+ - _0132_ ( _1512_ D ) ( _1351_ ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 391440 302960 ) ( * 308560 )
+ NEW Metal2 ( 391440 308560 ) ( 393680 * )
+ NEW Metal1 ( 391440 302960 ) Via1_HV
+ NEW Metal1 ( 393680 308560 ) Via1_VV ;
+ - _0133_ ( _1513_ D ) ( _1354_ ZN ) + USE SIGNAL
+ + ROUTED Metal3 ( 408240 318640 ) ( 425040 * )
+ NEW Metal2 ( 408240 318640 ) ( * 323120 )
+ NEW Metal1 ( 425040 318640 ) Via1_HV
+ NEW Metal2 ( 425040 318640 ) Via2_VH
+ NEW Metal2 ( 408240 318640 ) Via2_VH
+ NEW Metal1 ( 408240 323120 ) Via1_VV
+ NEW Metal2 ( 425040 318640 ) RECT ( -280 -660 280 0 ) ;
+ - _0134_ ( _1514_ D ) ( _1363_ Z ) + USE SIGNAL
+ + ROUTED Metal2 ( 374640 216720 ) ( 375760 * )
+ NEW Metal2 ( 375760 216720 ) ( * 221200 )
+ NEW Metal1 ( 374640 216720 ) Via1_HV
+ NEW Metal1 ( 375760 221200 ) Via1_VV ;
+ - _0135_ ( _0674_ I ) ( _0673_ Z ) + USE SIGNAL
+ + ROUTED Metal2 ( 283920 310800 ) ( * 317520 )
+ NEW Metal2 ( 280560 317520 ) ( 283920 * )
+ NEW Metal1 ( 283920 310800 ) Via1_VV
+ NEW Metal1 ( 280560 317520 ) Via1_HV ;
+ - _0136_ ( _0683_ A1 ) ( _0681_ A1 ) ( _0679_ A1 ) ( _0675_ Z ) + USE SIGNAL
+ + ROUTED Metal2 ( 207760 317520 ) ( 216720 * )
+ NEW Metal2 ( 216720 316400 ) ( * 317520 )
+ NEW Metal2 ( 216720 316400 ) ( 217840 * )
+ NEW Metal2 ( 205520 309680 ) ( 207760 * )
+ NEW Metal2 ( 207760 309680 ) ( * 317520 )
+ NEW Metal2 ( 206640 300720 ) ( * 309680 )
+ NEW Metal1 ( 207760 317520 ) Via1_VV
+ NEW Metal1 ( 217840 316400 ) Via1_VV
+ NEW Metal1 ( 205520 309680 ) Via1_HV
+ NEW Metal1 ( 206640 300720 ) Via1_VV ;
+ - _0137_ ( _0680_ A1 ) ( _0678_ A1 ) ( _0676_ ZN ) + USE SIGNAL
+ + ROUTED Metal3 ( 234640 317520 ) ( 245840 * )
+ NEW Metal2 ( 234640 309680 ) ( 235760 * )
+ NEW Metal2 ( 234640 309680 ) ( * 317520 )
+ NEW Metal2 ( 245840 317520 ) ( * 323120 )
+ NEW Metal1 ( 234640 317520 ) Via1_HV
+ NEW Metal2 ( 234640 317520 ) Via2_VH
+ NEW Metal2 ( 245840 317520 ) Via2_VH
+ NEW Metal1 ( 235760 309680 ) Via1_HV
+ NEW Metal1 ( 245840 323120 ) Via1_VV
+ NEW Metal2 ( 234640 317520 ) RECT ( -280 -660 280 0 ) ;
+ - _0138_ ( ANTENNA__0678__A2 I ) ( ANTENNA__0680__A2 I ) ( ANTENNA__0779__A1 I ) ( ANTENNA__0782__A1 I ) ( ANTENNA__0783__A2 I ) ( ANTENNA__0791__A1 I ) ( ANTENNA__0797__A2 I )
+ ( ANTENNA__0803__A2 I ) ( ANTENNA__0807__A2 I ) ( ANTENNA__0815__A2 I ) ( _0815_ A2 ) ( _0807_ A2 ) ( _0803_ A2 ) ( _0797_ A2 ) ( _0791_ A1 )
+ ( _0783_ A2 ) ( _0782_ A1 ) ( _0779_ A1 ) ( _0680_ A2 ) ( _0678_ A2 ) ( _0677_ Z ) + USE SIGNAL
+ + ROUTED Metal3 ( 226800 317520 ) ( 231280 * )
+ NEW Metal2 ( 232400 309680 ) ( * 311920 )
+ NEW Metal2 ( 231280 311920 ) ( 232400 * )
+ NEW Metal2 ( 231280 311920 ) ( * 317520 )
+ NEW Metal3 ( 232400 311920 ) ( 255920 * )
+ NEW Metal2 ( 255920 311920 ) ( 257040 * )
+ NEW Metal2 ( 273840 301840 ) ( * 311920 )
+ NEW Metal3 ( 255920 311920 ) ( 273840 * )
+ NEW Metal2 ( 297360 313040 ) ( * 315280 )
+ NEW Metal3 ( 273840 313040 ) ( 297360 * )
+ NEW Metal3 ( 273840 311920 ) ( * 313040 )
+ NEW Metal2 ( 302960 313040 ) ( * 315280 )
+ NEW Metal3 ( 297360 313040 ) ( 302960 * )
+ NEW Metal2 ( 305200 311920 ) ( * 313040 )
+ NEW Metal2 ( 302960 313040 ) ( 305200 * )
+ NEW Metal2 ( 316400 310800 ) ( * 313040 )
+ NEW Metal3 ( 302960 313040 ) ( 316400 * )
+ NEW Metal2 ( 257040 311920 ) ( * 319200 )
+ NEW Metal2 ( 249200 370160 ) ( * 371280 )
+ NEW Metal2 ( 249200 370160 ) ( 252560 * )
+ NEW Metal2 ( 252560 319200 ) ( * 370160 )
+ NEW Metal2 ( 252560 319200 ) ( 257040 * )
+ NEW Metal2 ( 254800 375760 ) ( * 378000 )
+ NEW Metal2 ( 252560 375760 ) ( 254800 * )
+ NEW Metal2 ( 252560 370160 ) ( * 375760 )
+ NEW Metal2 ( 267120 374640 ) ( * 375760 )
+ NEW Metal3 ( 254800 375760 ) ( 267120 * )
+ NEW Metal2 ( 272720 374640 ) ( * 375760 )
+ NEW Metal3 ( 267120 375760 ) ( 272720 * )
+ NEW Metal2 ( 263760 380240 ) ( * 388080 )
+ NEW Metal2 ( 262640 380240 ) ( 263760 * )
+ NEW Metal2 ( 262640 376880 ) ( * 380240 )
+ NEW Metal3 ( 262640 375760 ) ( * 376880 )
+ NEW Metal2 ( 246960 382480 ) ( * 386960 )
+ NEW Metal2 ( 246960 382480 ) ( 249200 * )
+ NEW Metal2 ( 249200 371280 ) ( * 382480 )
+ NEW Metal2 ( 269360 375760 ) ( * 393680 )
+ NEW Metal2 ( 264880 393680 ) ( * 394800 )
+ NEW Metal2 ( 264880 393680 ) ( 269360 * )
+ NEW Metal2 ( 269360 393680 ) ( 273840 * )
+ NEW Metal3 ( 234640 389200 ) ( 246960 * )
+ NEW Metal2 ( 246960 386960 ) ( * 389200 )
+ NEW Metal2 ( 317520 376880 ) ( * 378000 )
+ NEW Metal3 ( 272720 376880 ) ( 317520 * )
+ NEW Metal3 ( 272720 375760 ) ( * 376880 )
+ NEW Metal2 ( 317520 373520 ) ( * 376880 )
+ NEW Metal3 ( 317520 373520 ) ( 323120 * )
+ NEW Metal1 ( 231280 317520 ) Via1_VV
+ NEW Metal2 ( 231280 317520 ) Via2_VH
+ NEW Metal1 ( 226800 317520 ) Via1_VV
+ NEW Metal2 ( 226800 317520 ) Via2_VH
+ NEW Metal1 ( 232400 309680 ) Via1_VV
+ NEW Metal1 ( 255920 311920 ) Via1_VV
+ NEW Metal2 ( 255920 311920 ) Via2_VH
+ NEW Metal2 ( 232400 311920 ) Via2_VH
+ NEW Metal1 ( 273840 301840 ) Via1_VV
+ NEW Metal2 ( 273840 311920 ) Via2_VH
+ NEW Metal1 ( 297360 315280 ) Via1_VV
+ NEW Metal2 ( 297360 313040 ) Via2_VH
+ NEW Metal1 ( 302960 315280 ) Via1_VV
+ NEW Metal2 ( 302960 313040 ) Via2_VH
+ NEW Metal1 ( 305200 311920 ) Via1_VV
+ NEW Metal1 ( 316400 310800 ) Via1_HV
+ NEW Metal2 ( 316400 313040 ) Via2_VH
+ NEW Metal1 ( 249200 371280 ) Via1_VV
+ NEW Metal1 ( 254800 378000 ) Via1_VV
+ NEW Metal1 ( 267120 374640 ) Via1_VV
+ NEW Metal2 ( 267120 375760 ) Via2_VH
+ NEW Metal2 ( 254800 375760 ) Via2_VH
+ NEW Metal1 ( 272720 374640 ) Via1_VV
+ NEW Metal2 ( 272720 375760 ) Via2_VH
+ NEW Metal1 ( 263760 388080 ) Via1_VV
+ NEW Metal2 ( 262640 376880 ) Via2_VH
+ NEW Metal1 ( 246960 386960 ) Via1_VV
+ NEW Metal1 ( 269360 393680 ) Via1_VV
+ NEW Metal2 ( 269360 375760 ) Via2_VH
+ NEW Metal1 ( 264880 394800 ) Via1_VV
+ NEW Metal1 ( 273840 393680 ) Via1_VV
+ NEW Metal1 ( 234640 389200 ) Via1_VV
+ NEW Metal2 ( 234640 389200 ) Via2_VH
+ NEW Metal2 ( 246960 389200 ) Via2_VH
+ NEW Metal1 ( 317520 378000 ) Via1_VV
+ NEW Metal2 ( 317520 376880 ) Via2_VH
+ NEW Metal2 ( 317520 373520 ) Via2_VH
+ NEW Metal1 ( 323120 373520 ) Via1_VV
+ NEW Metal2 ( 323120 373520 ) Via2_VH
+ NEW Metal2 ( 231280 317520 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 226800 317520 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 255920 311920 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 232400 311920 ) RECT ( -280 -1040 280 0 )
+ NEW Metal2 ( 254800 375760 ) RECT ( -280 -1040 280 0 )
+ NEW Metal3 ( 269360 375760 ) RECT ( -1040 -280 0 280 )
+ NEW Metal2 ( 234640 389200 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 323120 373520 ) RECT ( -280 -660 280 0 ) ;
+ - _0139_ ( _1095_ A1 ) ( _0866_ A1 ) ( _0691_ I1 ) ( _0679_ A2 ) ( _0678_ Z ) + USE SIGNAL
+ + ROUTED Metal2 ( 207760 288400 ) ( * 300720 )
+ NEW Metal3 ( 204400 288400 ) ( 207760 * )
+ NEW Metal3 ( 207760 296240 ) ( 224560 * )
+ NEW Metal2 ( 226800 296240 ) ( * 301840 )
+ NEW Metal2 ( 224560 296240 ) ( 226800 * )
+ NEW Metal2 ( 231280 301840 ) ( * 308560 )
+ NEW Metal3 ( 226800 301840 ) ( 231280 * )
+ NEW Metal1 ( 207760 300720 ) Via1_VV
+ NEW Metal2 ( 207760 288400 ) Via2_VH
+ NEW Metal1 ( 204400 288400 ) Via1_VV
+ NEW Metal2 ( 204400 288400 ) Via2_VH
+ NEW Metal1 ( 224560 296240 ) Via1_VV
+ NEW Metal2 ( 224560 296240 ) Via2_VH
+ NEW Metal2 ( 207760 296240 ) Via2_VH
+ NEW Metal1 ( 226800 301840 ) Via1_VV
+ NEW Metal1 ( 231280 308560 ) Via1_VV
+ NEW Metal2 ( 231280 301840 ) Via2_VH
+ NEW Metal2 ( 226800 301840 ) Via2_VH
+ NEW Metal2 ( 204400 288400 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 224560 296240 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 207760 296240 ) RECT ( -280 -1040 280 0 )
+ NEW Metal2 ( 226800 301840 ) RECT ( -280 -1040 280 0 ) ;
+ - _0140_ ( _0870_ A1 ) ( _0691_ I0 ) ( _0689_ I0 ) ( _0679_ ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 205520 295120 ) ( * 299600 )
+ NEW Metal2 ( 204400 299600 ) ( 205520 * )
+ NEW Metal2 ( 205520 285040 ) ( * 295120 )
+ NEW Metal2 ( 203280 278320 ) ( * 285040 )
+ NEW Metal3 ( 198800 285040 ) ( 205520 * )
+ NEW Metal1 ( 205520 295120 ) Via1_HV
+ NEW Metal1 ( 204400 299600 ) Via1_VV
+ NEW Metal2 ( 205520 285040 ) Via2_VH
+ NEW Metal1 ( 203280 278320 ) Via1_VV
+ NEW Metal2 ( 203280 285040 ) Via2_VH
+ NEW Metal1 ( 198800 285040 ) Via1_HV
+ NEW Metal2 ( 198800 285040 ) Via2_VH
+ NEW Metal3 ( 203280 285040 ) RECT ( -1040 -280 0 280 )
+ NEW Metal2 ( 198800 285040 ) RECT ( -280 -660 280 0 ) ;
+ - _0141_ ( _0683_ A2 ) ( _0681_ A2 ) ( _0680_ ZN ) + USE SIGNAL
+ + ROUTED Metal3 ( 218960 316400 ) ( 232400 * )
+ NEW Metal3 ( 208880 309680 ) ( 218960 * )
+ NEW Metal2 ( 218960 309680 ) ( * 316400 )
+ NEW Metal1 ( 218960 316400 ) Via1_VV
+ NEW Metal2 ( 218960 316400 ) Via2_VH
+ NEW Metal1 ( 232400 316400 ) Via1_VV
+ NEW Metal2 ( 232400 316400 ) Via2_VH
+ NEW Metal1 ( 208880 309680 ) Via1_VV
+ NEW Metal2 ( 208880 309680 ) Via2_VH
+ NEW Metal2 ( 218960 309680 ) Via2_VH
+ NEW Metal2 ( 218960 316400 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 232400 316400 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 208880 309680 ) RECT ( -280 -660 280 0 ) ;
+ - _0142_ ( _1094_ I ) ( _0866_ A2 ) ( _0689_ I1 ) ( _0681_ Z ) + USE SIGNAL
+ + ROUTED Metal3 ( 212240 294000 ) ( 222320 * )
+ NEW Metal2 ( 215600 294000 ) ( * 308560 )
+ NEW Metal2 ( 210000 308560 ) ( 215600 * )
+ NEW Metal1 ( 212240 294000 ) Via1_VV
+ NEW Metal2 ( 212240 294000 ) Via2_VH
+ NEW Metal1 ( 222320 294000 ) Via1_VV
+ NEW Metal2 ( 222320 294000 ) Via2_VH
+ NEW Metal1 ( 215600 308560 ) Via1_VV
+ NEW Metal2 ( 215600 294000 ) Via2_VH
+ NEW Metal1 ( 210000 308560 ) Via1_VV
+ NEW Metal2 ( 212240 294000 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 222320 294000 ) RECT ( -280 -660 280 0 )
+ NEW Metal3 ( 215600 294000 ) RECT ( -1040 -280 0 280 ) ;
+ - _0143_ ( _0684_ A1 ) ( _0682_ ZN ) + USE SIGNAL
+ + ROUTED Metal3 ( 195440 330960 ) ( 201040 * )
+ NEW Metal1 ( 195440 330960 ) Via1_VV
+ NEW Metal2 ( 195440 330960 ) Via2_VH
+ NEW Metal1 ( 201040 330960 ) Via1_VV
+ NEW Metal2 ( 201040 330960 ) Via2_VH
+ NEW Metal2 ( 195440 330960 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 201040 330960 ) RECT ( -280 0 280 660 ) ;
+ - _0144_ ( _0684_ A2 ) ( _0683_ ZN ) + USE SIGNAL
+ + ROUTED Metal3 ( 194320 315280 ) ( 215600 * )
+ NEW Metal2 ( 194320 315280 ) ( * 332080 )
+ NEW Metal1 ( 215600 315280 ) Via1_VV
+ NEW Metal2 ( 215600 315280 ) Via2_VH
+ NEW Metal2 ( 194320 315280 ) Via2_VH
+ NEW Metal1 ( 194320 332080 ) Via1_VV
+ NEW Metal2 ( 215600 315280 ) RECT ( -280 -660 280 0 ) ;
+ - _0145_ ( _0688_ A2 ) ( _0684_ ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 196560 324240 ) ( * 330960 )
+ NEW Metal2 ( 196560 330960 ) ( 197680 * )
+ NEW Metal1 ( 196560 324240 ) Via1_HV
+ NEW Metal1 ( 197680 330960 ) Via1_VV ;
+ - _0146_ ( ANTENNA__0686__A2 I ) ( ANTENNA__0774__A1 I ) ( ANTENNA__0786__A2 I ) ( ANTENNA__0801__A2 I ) ( ANTENNA__0811__A2 I ) ( _0811_ A2 ) ( _0801_ A2 )
+ ( _0786_ A2 ) ( _0774_ A1 ) ( _0686_ A2 ) ( _0685_ ZN ) + USE SIGNAL
+ + ROUTED Metal3 ( 291760 283920 ) ( 297360 * )
+ NEW Metal3 ( 305200 372400 ) ( 313040 * )
+ NEW Metal3 ( 285040 334320 ) ( 291760 * )
+ NEW Metal3 ( 273840 334320 ) ( 285040 * )
+ NEW Metal2 ( 291760 283920 ) ( * 334320 )
+ NEW Metal2 ( 328720 296240 ) ( 329840 * )
+ NEW Metal3 ( 323120 295120 ) ( 328720 * )
+ NEW Metal2 ( 328720 295120 ) ( * 296240 )
+ NEW Metal2 ( 328720 283920 ) ( * 295120 )
+ NEW Metal3 ( 297360 283920 ) ( 328720 * )
+ NEW Metal2 ( 329840 296240 ) ( * 319200 )
+ NEW Metal3 ( 313040 372400 ) ( 319200 * )
+ NEW Metal3 ( 327600 362320 ) ( 332080 * )
+ NEW Metal2 ( 332080 319200 ) ( * 362320 )
+ NEW Metal2 ( 329840 319200 ) ( 332080 * )
+ NEW Metal3 ( 332080 362320 ) ( 338800 * )
+ NEW Metal2 ( 332080 378000 ) ( 333200 * )
+ NEW Metal2 ( 332080 362320 ) ( * 378000 )
+ NEW Metal3 ( 325360 378000 ) ( 332080 * )
+ NEW Metal3 ( 319200 371280 ) ( * 372400 )
+ NEW Metal3 ( 319200 371280 ) ( 332080 * )
+ NEW Metal1 ( 297360 283920 ) Via1_VV
+ NEW Metal2 ( 297360 283920 ) Via2_VH
+ NEW Metal2 ( 291760 283920 ) Via2_VH
+ NEW Metal1 ( 313040 372400 ) Via1_HV
+ NEW Metal2 ( 313040 372400 ) Via2_VH
+ NEW Metal1 ( 305200 372400 ) Via1_VV
+ NEW Metal2 ( 305200 372400 ) Via2_VH
+ NEW Metal1 ( 285040 334320 ) Via1_HV
+ NEW Metal2 ( 285040 334320 ) Via2_VH
+ NEW Metal2 ( 291760 334320 ) Via2_VH
+ NEW Metal1 ( 273840 334320 ) Via1_VV
+ NEW Metal2 ( 273840 334320 ) Via2_VH
+ NEW Metal1 ( 328720 296240 ) Via1_VV
+ NEW Metal1 ( 323120 295120 ) Via1_VV
+ NEW Metal2 ( 323120 295120 ) Via2_VH
+ NEW Metal2 ( 328720 295120 ) Via2_VH
+ NEW Metal2 ( 328720 283920 ) Via2_VH
+ NEW Metal1 ( 327600 362320 ) Via1_VV
+ NEW Metal2 ( 327600 362320 ) Via2_VH
+ NEW Metal2 ( 332080 362320 ) Via2_VH
+ NEW Metal1 ( 338800 362320 ) Via1_VV
+ NEW Metal2 ( 338800 362320 ) Via2_VH
+ NEW Metal1 ( 333200 378000 ) Via1_VV
+ NEW Metal1 ( 325360 378000 ) Via1_VV
+ NEW Metal2 ( 325360 378000 ) Via2_VH
+ NEW Metal2 ( 332080 378000 ) Via2_VH
+ NEW Metal2 ( 332080 371280 ) Via2_VH
+ NEW Metal2 ( 297360 283920 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 313040 372400 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 305200 372400 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 285040 334320 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 273840 334320 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 323120 295120 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 327600 362320 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 338800 362320 ) RECT ( -280 0 280 660 )
+ NEW Metal2 ( 325360 378000 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 332080 378000 ) RECT ( -280 -1040 280 0 )
+ NEW Metal2 ( 332080 371280 ) RECT ( -280 -1040 280 0 ) ;
+ - _0147_ ( _0687_ I ) ( _0686_ Z ) + USE SIGNAL
+ + ROUTED Metal2 ( 288400 327600 ) ( * 332080 )
+ NEW Metal1 ( 288400 327600 ) Via1_VV
+ NEW Metal1 ( 288400 332080 ) Via1_VV ;
+ - _0148_ ( _1095_ A2 ) ( _0872_ A1 ) ( _0870_ A2 ) ( _0867_ A1 ) ( _0691_ S ) ( _0689_ S ) ( _0688_ Z ) + USE SIGNAL
+ + ROUTED Metal2 ( 223440 304080 ) ( 224560 * )
+ NEW Metal2 ( 210000 295120 ) ( * 304080 )
+ NEW Metal3 ( 210000 304080 ) ( 223440 * )
+ NEW Metal2 ( 202160 294000 ) ( * 304080 )
+ NEW Metal3 ( 202160 304080 ) ( 210000 * )
+ NEW Metal2 ( 217840 278320 ) ( * 304080 )
+ NEW Metal2 ( 202160 278320 ) ( * 286160 )
+ NEW Metal2 ( 223440 304080 ) ( * 323120 )
+ NEW Metal2 ( 197680 286160 ) ( * 292880 )
+ NEW Metal2 ( 201040 286160 ) ( * 287280 )
+ NEW Metal2 ( 197680 287280 ) ( 201040 * )
+ NEW Metal2 ( 201040 287280 ) ( * 294000 )
+ NEW Metal2 ( 201040 278320 ) ( 202160 * )
+ NEW Metal2 ( 201040 286160 ) ( 202160 * )
+ NEW Metal2 ( 201040 294000 ) ( 202160 * )
+ NEW Metal1 ( 224560 304080 ) Via1_VV
+ NEW Metal1 ( 210000 295120 ) Via1_HV
+ NEW Metal2 ( 210000 304080 ) Via2_VH
+ NEW Metal2 ( 223440 304080 ) Via2_VH
+ NEW Metal2 ( 202160 304080 ) Via2_VH
+ NEW Metal1 ( 217840 278320 ) Via1_HV
+ NEW Metal2 ( 217840 304080 ) Via2_VH
+ NEW Metal1 ( 223440 323120 ) Via1_VV
+ NEW Metal1 ( 197680 286160 ) Via1_HV
+ NEW Metal1 ( 197680 292880 ) Via1_VV
+ NEW Metal1 ( 201040 278320 ) Via1_VV
+ NEW Metal2 ( 223440 304080 ) RECT ( -280 -1040 280 0 )
+ NEW Metal3 ( 217840 304080 ) RECT ( -1040 -280 0 280 ) ;
+ - _0149_ ( ANTENNA__0690__I I ) ( _0690_ I ) ( _0689_ Z ) + USE SIGNAL
+ + ROUTED Metal2 ( 215600 291760 ) ( 216720 * )
+ NEW Metal2 ( 216720 291760 ) ( * 297360 )
+ NEW Metal2 ( 513520 295120 ) ( * 296240 )
+ NEW Metal3 ( 507920 296240 ) ( 513520 * )
+ NEW Metal3 ( 216720 297360 ) ( 319200 * )
+ NEW Metal3 ( 319200 296240 ) ( * 297360 )
+ NEW Metal3 ( 319200 296240 ) ( 507920 * )
+ NEW Metal1 ( 215600 291760 ) Via1_VV
+ NEW Metal2 ( 216720 297360 ) Via2_VH
+ NEW Metal1 ( 507920 296240 ) Via1_VV
+ NEW Metal2 ( 507920 296240 ) Via2_VH
+ NEW Metal1 ( 513520 295120 ) Via1_VV
+ NEW Metal2 ( 513520 296240 ) Via2_VH
+ NEW Metal2 ( 507920 296240 ) RECT ( -280 -660 280 0 ) ;
+ - _0150_ ( ANTENNA__0692__I I ) ( _0692_ I ) ( _0691_ Z ) + USE SIGNAL
+ + ROUTED Metal2 ( 206640 283920 ) ( 207760 * )
+ NEW Metal2 ( 215600 99120 ) ( * 100240 )
+ NEW Metal2 ( 205520 100240 ) ( 215600 * )
+ NEW Metal2 ( 206640 268800 ) ( * 283920 )
+ NEW Metal2 ( 204400 182000 ) ( 205520 * )
+ NEW Metal2 ( 204400 182000 ) ( * 207760 )
+ NEW Metal1 ( 204400 207760 ) ( * 208880 )
+ NEW Metal1 ( 202160 208880 ) ( 204400 * )
+ NEW Metal2 ( 202160 208880 ) ( * 218960 )
+ NEW Metal2 ( 202160 218960 ) ( 204400 * )
+ NEW Metal2 ( 204400 218960 ) ( * 268800 )
+ NEW Metal2 ( 204400 268800 ) ( 206640 * )
+ NEW Metal2 ( 205520 98000 ) ( * 182000 )
+ NEW Metal1 ( 207760 283920 ) Via1_VV
+ NEW Metal1 ( 205520 98000 ) Via1_HV
+ NEW Metal1 ( 215600 99120 ) Via1_VV
+ NEW Metal1 ( 204400 207760 ) Via1_HV
+ NEW Metal1 ( 202160 208880 ) Via1_HV ;
+ - _0151_ ( ANTENNA__0694__A3 I ) ( ANTENNA__0698__A2 I ) ( ANTENNA__0708__A1 I ) ( ANTENNA__0865__A1 I ) ( ANTENNA__1106__A1 I ) ( _1106_ A1 ) ( _0865_ A1 )
+ ( _0708_ A1 ) ( _0698_ A2 ) ( _0694_ A3 ) ( _0693_ Z ) + USE SIGNAL
+ + ROUTED Metal2 ( 397040 131600 ) ( * 134960 )
+ NEW Metal2 ( 395920 134960 ) ( 397040 * )
+ NEW Metal3 ( 397040 127120 ) ( 417200 * )
+ NEW Metal2 ( 397040 127120 ) ( * 131600 )
+ NEW Metal3 ( 417200 128240 ) ( 422800 * )
+ NEW Metal3 ( 417200 127120 ) ( * 128240 )
+ NEW Metal2 ( 395920 134960 ) ( * 151200 )
+ NEW Metal3 ( 412720 238000 ) ( 419440 * )
+ NEW Metal2 ( 412720 161840 ) ( * 238000 )
+ NEW Metal2 ( 418320 154000 ) ( * 161840 )
+ NEW Metal3 ( 412720 161840 ) ( 418320 * )
+ NEW Metal3 ( 403760 161840 ) ( 412720 * )
+ NEW Metal2 ( 398160 160720 ) ( * 161840 )
+ NEW Metal3 ( 398160 161840 ) ( 403760 * )
+ NEW Metal2 ( 395920 151200 ) ( 398160 * )
+ NEW Metal2 ( 398160 151200 ) ( * 160720 )
+ NEW Metal2 ( 392560 161840 ) ( * 174160 )
+ NEW Metal3 ( 392560 161840 ) ( 398160 * )
+ NEW Metal2 ( 389200 174160 ) ( * 176400 )
+ NEW Metal2 ( 389200 174160 ) ( 392560 * )
+ NEW Metal1 ( 397040 131600 ) Via1_VV
+ NEW Metal1 ( 417200 127120 ) Via1_VV
+ NEW Metal2 ( 417200 127120 ) Via2_VH
+ NEW Metal2 ( 397040 127120 ) Via2_VH
+ NEW Metal1 ( 422800 128240 ) Via1_VV
+ NEW Metal2 ( 422800 128240 ) Via2_VH
+ NEW Metal1 ( 412720 238000 ) Via1_HV
+ NEW Metal2 ( 412720 238000 ) Via2_VH
+ NEW Metal1 ( 419440 238000 ) Via1_VV
+ NEW Metal2 ( 419440 238000 ) Via2_VH
+ NEW Metal1 ( 412720 161840 ) Via1_VV
+ NEW Metal1 ( 418320 154000 ) Via1_VV
+ NEW Metal2 ( 418320 161840 ) Via2_VH
+ NEW Metal2 ( 412720 161840 ) Via2_VH
+ NEW Metal1 ( 403760 161840 ) Via1_VV
+ NEW Metal2 ( 403760 161840 ) Via2_VH
+ NEW Metal1 ( 398160 160720 ) Via1_VV
+ NEW Metal2 ( 398160 161840 ) Via2_VH
+ NEW Metal1 ( 392560 174160 ) Via1_VV
+ NEW Metal2 ( 392560 161840 ) Via2_VH
+ NEW Metal1 ( 389200 176400 ) Via1_VV
+ NEW Metal2 ( 417200 127120 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 422800 128240 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 412720 238000 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 419440 238000 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 412720 161840 ) RECT ( -280 -1040 280 0 )
+ NEW Metal2 ( 403760 161840 ) RECT ( -280 -660 280 0 ) ;
+ - _0152_ ( _0720_ A2 ) ( _0695_ A2 ) ( _0694_ ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 375760 198800 ) ( * 199920 )
+ NEW Metal2 ( 382480 178640 ) ( * 198800 )
+ NEW Metal2 ( 390320 198800 ) ( * 224560 )
+ NEW Metal3 ( 375760 198800 ) ( 390320 * )
+ NEW Metal1 ( 375760 199920 ) Via1_VV
+ NEW Metal2 ( 375760 198800 ) Via2_VH
+ NEW Metal1 ( 382480 178640 ) Via1_VV
+ NEW Metal2 ( 382480 198800 ) Via2_VH
+ NEW Metal2 ( 390320 198800 ) Via2_VH
+ NEW Metal1 ( 390320 224560 ) Via1_HV
+ NEW Metal3 ( 382480 198800 ) RECT ( -1040 -280 0 280 ) ;
+ - _0153_ ( _0696_ I ) ( _0695_ Z ) + USE SIGNAL
+ + ROUTED Metal2 ( 394800 222320 ) ( 400400 * )
+ NEW Metal1 ( 394800 222320 ) Via1_VV
+ NEW Metal1 ( 400400 222320 ) Via1_VV ;
+ - _0154_ ( _0734_ A1 ) ( _0718_ A1 ) ( _0697_ ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 428400 223440 ) ( 432880 * )
+ NEW Metal2 ( 428400 222320 ) ( * 223440 )
+ NEW Metal2 ( 425040 222320 ) ( 428400 * )
+ NEW Metal2 ( 432880 207760 ) ( * 223440 )
+ NEW Metal1 ( 432880 223440 ) Via1_VV
+ NEW Metal1 ( 425040 222320 ) Via1_VV
+ NEW Metal1 ( 432880 207760 ) Via1_HV ;
+ - _0155_ ( _0699_ I ) ( _0698_ Z ) + USE SIGNAL
+ + ROUTED Metal2 ( 399280 161840 ) ( 400400 * )
+ NEW Metal2 ( 400400 161840 ) ( * 168560 )
+ NEW Metal3 ( 400400 168560 ) ( 416080 * )
+ NEW Metal1 ( 399280 161840 ) Via1_VV
+ NEW Metal2 ( 400400 168560 ) Via2_VH
+ NEW Metal1 ( 416080 168560 ) Via1_VV
+ NEW Metal2 ( 416080 168560 ) Via2_VH
+ NEW Metal2 ( 416080 168560 ) RECT ( -280 -660 280 0 ) ;
+ - _0156_ ( _0725_ A1 ) ( _0715_ A1 ) ( _0700_ ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 431760 176400 ) ( 434000 * )
+ NEW Metal2 ( 434000 176400 ) ( * 192080 )
+ NEW Metal2 ( 430640 167440 ) ( * 176400 )
+ NEW Metal2 ( 430640 176400 ) ( 431760 * )
+ NEW Metal1 ( 431760 176400 ) Via1_VV
+ NEW Metal1 ( 434000 192080 ) Via1_HV
+ NEW Metal1 ( 430640 167440 ) Via1_HV ;
+ - _0157_ ( _0702_ A3 ) ( _0701_ ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 408240 136080 ) ( 409360 * )
+ NEW Metal2 ( 409360 136080 ) ( * 145040 )
+ NEW Metal2 ( 409360 145040 ) ( 417200 * )
+ NEW Metal1 ( 408240 136080 ) Via1_HV
+ NEW Metal1 ( 417200 145040 ) Via1_HV ;
+ - _0158_ ( _0752_ A1 ) ( _0743_ A1 ) ( _0739_ A1 ) ( _0729_ A1 ) ( _0724_ A1 ) ( _0709_ B1 ) ( _0702_ Z ) + USE SIGNAL
+ + ROUTED Metal3 ( 441840 145040 ) ( 483280 * )
+ NEW Metal2 ( 483280 145040 ) ( 484400 * )
+ NEW Metal3 ( 484400 150640 ) ( 496720 * )
+ NEW Metal2 ( 500080 143920 ) ( * 150640 )
+ NEW Metal3 ( 496720 150640 ) ( 500080 * )
+ NEW Metal2 ( 430640 143920 ) ( * 145040 )
+ NEW Metal3 ( 430640 145040 ) ( 441840 * )
+ NEW Metal2 ( 440720 152880 ) ( 441840 * )
+ NEW Metal2 ( 441840 145040 ) ( * 152880 )
+ NEW Metal2 ( 484400 145040 ) ( * 160720 )
+ NEW Metal2 ( 496720 150640 ) ( * 154000 )
+ NEW Metal1 ( 441840 145040 ) Via1_VV
+ NEW Metal2 ( 441840 145040 ) Via2_VH
+ NEW Metal1 ( 483280 145040 ) Via1_HV
+ NEW Metal2 ( 483280 145040 ) Via2_VH
+ NEW Metal2 ( 496720 150640 ) Via2_VH
+ NEW Metal2 ( 484400 150640 ) Via2_VH
+ NEW Metal1 ( 500080 143920 ) Via1_VV
+ NEW Metal2 ( 500080 150640 ) Via2_VH
+ NEW Metal2 ( 430640 145040 ) Via2_VH
+ NEW Metal1 ( 430640 143920 ) Via1_HV
+ NEW Metal1 ( 484400 160720 ) Via1_HV
+ NEW Metal1 ( 496720 154000 ) Via1_VV
+ NEW Metal1 ( 440720 152880 ) Via1_HV
+ NEW Metal2 ( 441840 145040 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 483280 145040 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 484400 150640 ) RECT ( -280 -1040 280 0 ) ;
+ - _0159_ ( _0704_ I ) ( _0703_ ZN ) + USE SIGNAL
+ + ROUTED Metal3 ( 419440 112560 ) ( 428400 * )
+ NEW Metal1 ( 428400 112560 ) Via1_VV
+ NEW Metal2 ( 428400 112560 ) Via2_VH
+ NEW Metal1 ( 419440 112560 ) Via1_VV
+ NEW Metal2 ( 419440 112560 ) Via2_VH
+ NEW Metal2 ( 428400 112560 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 419440 112560 ) RECT ( -280 -660 280 0 ) ;
+ - _0160_ ( _0739_ A2 ) ( _0729_ A2 ) ( _0724_ A2 ) ( _0709_ B2 ) ( _0705_ Z ) + USE SIGNAL
+ + ROUTED Metal3 ( 460880 147280 ) ( 486640 * )
+ NEW Metal3 ( 449680 147280 ) ( 460880 * )
+ NEW Metal2 ( 446320 145040 ) ( * 147280 )
+ NEW Metal3 ( 446320 147280 ) ( 449680 * )
+ NEW Metal2 ( 449680 147280 ) ( * 152880 )
+ NEW Metal2 ( 486640 146160 ) ( * 160720 )
+ NEW Metal1 ( 486640 146160 ) Via1_HV
+ NEW Metal1 ( 460880 147280 ) Via1_HV
+ NEW Metal2 ( 460880 147280 ) Via2_VH
+ NEW Metal2 ( 486640 147280 ) Via2_VH
+ NEW Metal2 ( 449680 147280 ) Via2_VH
+ NEW Metal1 ( 446320 145040 ) Via1_VV
+ NEW Metal2 ( 446320 147280 ) Via2_VH
+ NEW Metal1 ( 486640 160720 ) Via1_HV
+ NEW Metal1 ( 449680 152880 ) Via1_HV
+ NEW Metal2 ( 460880 147280 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 486640 147280 ) RECT ( -280 -1040 280 0 ) ;
+ - _0161_ ( _0865_ A2 ) ( _0708_ A2 ) ( _0706_ ZN ) + USE SIGNAL
+ + ROUTED Metal3 ( 417200 139440 ) ( 421680 * )
+ NEW Metal2 ( 416080 129360 ) ( 417200 * )
+ NEW Metal2 ( 417200 129360 ) ( * 139440 )
+ NEW Metal2 ( 421680 139440 ) ( * 152880 )
+ NEW Metal1 ( 417200 139440 ) Via1_VV
+ NEW Metal2 ( 417200 139440 ) Via2_VH
+ NEW Metal2 ( 421680 139440 ) Via2_VH
+ NEW Metal1 ( 416080 129360 ) Via1_VV
+ NEW Metal1 ( 421680 152880 ) Via1_VV
+ NEW Metal2 ( 417200 139440 ) RECT ( -280 -660 280 0 ) ;
+ - _0162_ ( _0708_ B ) ( _0707_ ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 408240 152880 ) ( 416080 * )
+ NEW Metal1 ( 416080 152880 ) Via1_VV
+ NEW Metal1 ( 408240 152880 ) Via1_VV ;
+ - _0163_ ( _0729_ B ) ( _0709_ C ) ( _0708_ ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 439600 145040 ) ( * 151200 )
+ NEW Metal3 ( 419440 154000 ) ( 437360 * )
+ NEW Metal2 ( 419440 154000 ) ( * 155120 )
+ NEW Metal2 ( 437360 151200 ) ( 439600 * )
+ NEW Metal2 ( 437360 151200 ) ( * 154000 )
+ NEW Metal1 ( 439600 145040 ) Via1_VV
+ NEW Metal1 ( 437360 154000 ) Via1_HV
+ NEW Metal2 ( 437360 154000 ) Via2_VH
+ NEW Metal2 ( 419440 154000 ) Via2_VH
+ NEW Metal1 ( 419440 155120 ) Via1_VV
+ NEW Metal2 ( 437360 154000 ) RECT ( -280 -660 280 0 ) ;
+ - _0164_ ( _0725_ A2 ) ( _0715_ A2 ) ( _0709_ ZN ) + USE SIGNAL
+ + ROUTED Metal3 ( 427280 176400 ) ( 438480 * )
+ NEW Metal2 ( 438480 155120 ) ( * 176400 )
+ NEW Metal2 ( 437360 190960 ) ( 438480 * )
+ NEW Metal2 ( 438480 176400 ) ( * 190960 )
+ NEW Metal1 ( 427280 176400 ) Via1_VV
+ NEW Metal2 ( 427280 176400 ) Via2_VH
+ NEW Metal2 ( 438480 176400 ) Via2_VH
+ NEW Metal1 ( 438480 155120 ) Via1_HV
+ NEW Metal1 ( 437360 190960 ) Via1_VV
+ NEW Metal2 ( 427280 176400 ) RECT ( -280 -660 280 0 ) ;
+ - _0165_ ( _0711_ A2 ) ( _0710_ ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 394800 138320 ) ( * 167440 )
+ NEW Metal1 ( 394800 138320 ) Via1_VV
+ NEW Metal1 ( 394800 167440 ) Via1_HV ;
+ - _0166_ ( _0712_ I ) ( _0711_ ZN ) + USE SIGNAL
+ + ROUTED Metal3 ( 399280 175280 ) ( 406000 * )
+ NEW Metal2 ( 399280 169680 ) ( * 175280 )
+ NEW Metal1 ( 406000 175280 ) Via1_VV
+ NEW Metal2 ( 406000 175280 ) Via2_VH
+ NEW Metal2 ( 399280 175280 ) Via2_VH
+ NEW Metal1 ( 399280 169680 ) Via1_VV
+ NEW Metal2 ( 406000 175280 ) RECT ( -280 -660 280 0 ) ;
+ - _0167_ ( _0715_ A3 ) ( _0713_ ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 423920 178640 ) ( 425040 * )
+ NEW Metal2 ( 423920 178640 ) ( * 182000 )
+ NEW Metal1 ( 425040 178640 ) Via1_VV
+ NEW Metal1 ( 423920 182000 ) Via1_VV ;
+ - _0168_ ( _0715_ B ) ( _0714_ ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 431760 178640 ) ( 432880 * )
+ NEW Metal2 ( 431760 178640 ) ( * 189840 )
+ NEW Metal3 ( 426160 189840 ) ( 431760 * )
+ NEW Metal1 ( 432880 178640 ) Via1_VV
+ NEW Metal2 ( 431760 189840 ) Via2_VH
+ NEW Metal1 ( 426160 189840 ) Via1_VV
+ NEW Metal2 ( 426160 189840 ) Via2_VH
+ NEW Metal2 ( 426160 189840 ) RECT ( -280 -660 280 0 ) ;
+ - _0169_ ( _0734_ A2 ) ( _0716_ I ) ( _0715_ ZN ) + USE SIGNAL
+ + ROUTED Metal3 ( 416080 201040 ) ( 427280 * )
+ NEW Metal2 ( 427280 201040 ) ( * 207760 )
+ NEW Metal2 ( 429520 177520 ) ( * 178640 )
+ NEW Metal2 ( 427280 178640 ) ( 429520 * )
+ NEW Metal2 ( 427280 178640 ) ( * 201040 )
+ NEW Metal1 ( 416080 201040 ) Via1_VV
+ NEW Metal2 ( 416080 201040 ) Via2_VH
+ NEW Metal2 ( 427280 201040 ) Via2_VH
+ NEW Metal1 ( 427280 207760 ) Via1_HV
+ NEW Metal1 ( 429520 177520 ) Via1_HV
+ NEW Metal2 ( 416080 201040 ) RECT ( -280 -660 280 0 ) ;
+ - _0170_ ( _0718_ A2 ) ( _0716_ ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 417200 201040 ) ( * 203280 )
+ NEW Metal3 ( 417200 203280 ) ( 429520 * )
+ NEW Metal2 ( 429520 203280 ) ( * 221200 )
+ NEW Metal2 ( 429520 221200 ) ( 430640 * )
+ NEW Metal1 ( 417200 201040 ) Via1_VV
+ NEW Metal2 ( 417200 203280 ) Via2_VH
+ NEW Metal2 ( 429520 203280 ) Via2_VH
+ NEW Metal1 ( 430640 221200 ) Via1_VV ;
+ - _0171_ ( _0718_ B ) ( _0717_ ZN ) + USE SIGNAL
+ + ROUTED Metal3 ( 422800 217840 ) ( 435120 * )
+ NEW Metal2 ( 435120 217840 ) ( * 221200 )
+ NEW Metal1 ( 422800 217840 ) Via1_VV
+ NEW Metal2 ( 422800 217840 ) Via2_VH
+ NEW Metal2 ( 435120 217840 ) Via2_VH
+ NEW Metal1 ( 435120 221200 ) Via1_VV
+ NEW Metal2 ( 422800 217840 ) RECT ( -280 -660 280 0 ) ;
+ - _0172_ ( _0723_ A2 ) ( _0718_ ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 431760 218960 ) ( * 221200 )
+ NEW Metal2 ( 430640 218960 ) ( 431760 * )
+ NEW Metal2 ( 430640 214480 ) ( * 218960 )
+ NEW Metal1 ( 431760 221200 ) Via1_VV
+ NEW Metal1 ( 430640 214480 ) Via1_HV ;
+ - _0173_ ( _0720_ A1 ) ( _0719_ ZN ) + USE SIGNAL
+ + ROUTED Metal3 ( 376880 201040 ) ( 400400 * )
+ NEW Metal1 ( 376880 201040 ) Via1_VV
+ NEW Metal2 ( 376880 201040 ) Via2_VH
+ NEW Metal1 ( 400400 201040 ) Via1_VV
+ NEW Metal2 ( 400400 201040 ) Via2_VH
+ NEW Metal2 ( 376880 201040 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 400400 201040 ) RECT ( -280 -660 280 0 ) ;
+ - _0174_ ( _0721_ A2 ) ( _0720_ ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 388080 198800 ) ( * 199920 )
+ NEW Metal3 ( 379120 199920 ) ( 388080 * )
+ NEW Metal1 ( 379120 199920 ) Via1_VV
+ NEW Metal2 ( 379120 199920 ) Via2_VH
+ NEW Metal1 ( 388080 198800 ) Via1_HV
+ NEW Metal2 ( 388080 199920 ) Via2_VH
+ NEW Metal2 ( 379120 199920 ) RECT ( -280 -660 280 0 ) ;
+ - _0175_ ( _0722_ I ) ( _0721_ ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 399280 201040 ) ( * 215600 )
+ NEW Metal2 ( 394800 201040 ) ( 399280 * )
+ NEW Metal1 ( 399280 215600 ) Via1_VV
+ NEW Metal1 ( 394800 201040 ) Via1_VV ;
+ - _0176_ ( ANTENNA__0738__A3 I ) ( ANTENNA__0746__B1 I ) ( ANTENNA__0747__A1 I ) ( ANTENNA__0760__C I ) ( ANTENNA__0761__A1 I ) ( ANTENNA__0770__B I ) ( ANTENNA__0771__A1 I )
+ ( _0771_ A1 ) ( _0770_ B ) ( _0761_ A1 ) ( _0760_ C ) ( _0747_ A1 ) ( _0746_ B1 ) ( _0738_ A3 ) ( _0723_ Z ) + USE SIGNAL
+ + ROUTED Metal2 ( 513520 205520 ) ( 518000 * )
+ NEW Metal2 ( 504560 195440 ) ( * 201040 )
+ NEW Metal3 ( 504560 193200 ) ( 512400 * )
+ NEW Metal2 ( 504560 193200 ) ( * 195440 )
+ NEW Metal3 ( 512400 193200 ) ( 518000 * )
+ NEW Metal2 ( 522480 192080 ) ( * 193200 )
+ NEW Metal3 ( 518000 193200 ) ( 522480 * )
+ NEW Metal2 ( 525840 193200 ) ( * 201040 )
+ NEW Metal3 ( 522480 193200 ) ( 525840 * )
+ NEW Metal2 ( 539280 192080 ) ( * 193200 )
+ NEW Metal3 ( 525840 193200 ) ( 539280 * )
+ NEW Metal2 ( 535920 184240 ) ( * 193200 )
+ NEW Metal2 ( 528080 177520 ) ( * 193200 )
+ NEW Metal2 ( 522480 177520 ) ( * 178640 )
+ NEW Metal1 ( 522480 178640 ) ( 528080 * )
+ NEW Metal2 ( 518000 193200 ) ( * 205520 )
+ NEW Metal3 ( 539280 193200 ) ( 554960 * )
+ NEW Metal3 ( 457520 216720 ) ( 487760 * )
+ NEW Metal3 ( 487760 216720 ) ( 497840 * )
+ NEW Metal2 ( 500080 206640 ) ( * 216720 )
+ NEW Metal3 ( 497840 216720 ) ( 500080 * )
+ NEW Metal2 ( 501200 201040 ) ( * 206640 )
+ NEW Metal2 ( 500080 206640 ) ( 501200 * )
+ NEW Metal2 ( 502320 194320 ) ( * 195440 )
+ NEW Metal2 ( 502320 195440 ) ( 504560 * )
+ NEW Metal3 ( 501200 201040 ) ( 504560 * )
+ NEW Metal1 ( 518000 205520 ) Via1_VV
+ NEW Metal1 ( 513520 205520 ) Via1_VV
+ NEW Metal2 ( 504560 201040 ) Via2_VH
+ NEW Metal1 ( 512400 193200 ) Via1_VV
+ NEW Metal2 ( 512400 193200 ) Via2_VH
+ NEW Metal2 ( 504560 193200 ) Via2_VH
+ NEW Metal2 ( 518000 193200 ) Via2_VH
+ NEW Metal1 ( 522480 192080 ) Via1_VV
+ NEW Metal2 ( 522480 193200 ) Via2_VH
+ NEW Metal1 ( 525840 201040 ) Via1_VV
+ NEW Metal2 ( 525840 193200 ) Via2_VH
+ NEW Metal1 ( 539280 192080 ) Via1_VV
+ NEW Metal2 ( 539280 193200 ) Via2_VH
+ NEW Metal1 ( 535920 184240 ) Via1_HV
+ NEW Metal2 ( 535920 193200 ) Via2_VH
+ NEW Metal1 ( 528080 177520 ) Via1_VV
+ NEW Metal2 ( 528080 193200 ) Via2_VH
+ NEW Metal1 ( 522480 177520 ) Via1_VV
+ NEW Metal1 ( 522480 178640 ) Via1_HV
+ NEW Metal1 ( 528080 178640 ) Via1_HV
+ NEW Metal1 ( 554960 193200 ) Via1_VV
+ NEW Metal2 ( 554960 193200 ) Via2_VH
+ NEW Metal1 ( 487760 216720 ) Via1_VV
+ NEW Metal2 ( 487760 216720 ) Via2_VH
+ NEW Metal1 ( 457520 216720 ) Via1_HV
+ NEW Metal2 ( 457520 216720 ) Via2_VH
+ NEW Metal1 ( 497840 216720 ) Via1_VV
+ NEW Metal2 ( 497840 216720 ) Via2_VH
+ NEW Metal1 ( 500080 206640 ) Via1_VV
+ NEW Metal2 ( 500080 216720 ) Via2_VH
+ NEW Metal2 ( 501200 201040 ) Via2_VH
+ NEW Metal1 ( 502320 194320 ) Via1_VV
+ NEW Metal2 ( 512400 193200 ) RECT ( -280 -660 280 0 )
+ NEW Metal3 ( 535920 193200 ) RECT ( -1040 -280 0 280 )
+ NEW Metal3 ( 528080 193200 ) RECT ( -1040 -280 0 280 )
+ NEW Metal2 ( 528080 178640 ) RECT ( -280 -1040 280 0 )
+ NEW Metal2 ( 554960 193200 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 487760 216720 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 457520 216720 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 497840 216720 ) RECT ( -280 -660 280 0 ) ;
+ - _0177_ ( ANTENNA__0736__A1 I ) ( ANTENNA__0738__A1 I ) ( ANTENNA__0750__A1 I ) ( ANTENNA__0768__A1 I ) ( _0768_ A1 ) ( _0750_ A1 ) ( _0738_ A1 )
+ ( _0736_ A1 ) ( _0724_ ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 528080 147280 ) ( * 150640 )
+ NEW Metal3 ( 491120 147280 ) ( 528080 * )
+ NEW Metal2 ( 534800 146160 ) ( * 147280 )
+ NEW Metal3 ( 528080 147280 ) ( 534800 * )
+ NEW Metal2 ( 516880 174160 ) ( 518000 * )
+ NEW Metal2 ( 518000 168560 ) ( * 174160 )
+ NEW Metal2 ( 518000 168560 ) ( 521360 * )
+ NEW Metal2 ( 521360 165200 ) ( * 168560 )
+ NEW Metal2 ( 521360 165200 ) ( 522480 * )
+ NEW Metal2 ( 522480 147280 ) ( * 165200 )
+ NEW Metal2 ( 526960 189840 ) ( * 190960 )
+ NEW Metal3 ( 516880 189840 ) ( 526960 * )
+ NEW Metal2 ( 516880 174160 ) ( * 189840 )
+ NEW Metal2 ( 512400 198800 ) ( 513520 * )
+ NEW Metal2 ( 513520 189840 ) ( * 198800 )
+ NEW Metal3 ( 513520 189840 ) ( 516880 * )
+ NEW Metal3 ( 526960 199920 ) ( 535920 * )
+ NEW Metal2 ( 526960 190960 ) ( * 199920 )
+ NEW Metal3 ( 535920 199920 ) ( 543760 * )
+ NEW Metal2 ( 497840 197680 ) ( * 201040 )
+ NEW Metal3 ( 497840 197680 ) ( 513520 * )
+ NEW Metal1 ( 528080 150640 ) Via1_VV
+ NEW Metal2 ( 528080 147280 ) Via2_VH
+ NEW Metal1 ( 491120 147280 ) Via1_HV
+ NEW Metal2 ( 491120 147280 ) Via2_VH
+ NEW Metal1 ( 534800 146160 ) Via1_VV
+ NEW Metal2 ( 534800 147280 ) Via2_VH
+ NEW Metal1 ( 516880 174160 ) Via1_VV
+ NEW Metal2 ( 522480 147280 ) Via2_VH
+ NEW Metal1 ( 526960 190960 ) Via1_VV
+ NEW Metal2 ( 526960 189840 ) Via2_VH
+ NEW Metal2 ( 516880 189840 ) Via2_VH
+ NEW Metal1 ( 512400 198800 ) Via1_VV
+ NEW Metal2 ( 513520 189840 ) Via2_VH
+ NEW Metal1 ( 535920 199920 ) Via1_VV
+ NEW Metal2 ( 535920 199920 ) Via2_VH
+ NEW Metal2 ( 526960 199920 ) Via2_VH
+ NEW Metal1 ( 543760 199920 ) Via1_VV
+ NEW Metal2 ( 543760 199920 ) Via2_VH
+ NEW Metal2 ( 513520 197680 ) Via2_VH
+ NEW Metal2 ( 497840 197680 ) Via2_VH
+ NEW Metal1 ( 497840 201040 ) Via1_VV
+ NEW Metal2 ( 491120 147280 ) RECT ( -280 -660 280 0 )
+ NEW Metal3 ( 522480 147280 ) RECT ( -1040 -280 0 280 )
+ NEW Metal2 ( 535920 199920 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 543760 199920 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 513520 197680 ) RECT ( -280 -1040 280 0 ) ;
+ - _0178_ ( _0726_ A3 ) ( _0725_ ZN ) + USE SIGNAL
+ + ROUTED Metal3 ( 436240 185360 ) ( 448560 * )
+ NEW Metal2 ( 436240 185360 ) ( * 189840 )
+ NEW Metal1 ( 448560 185360 ) Via1_HV
+ NEW Metal2 ( 448560 185360 ) Via2_VH
+ NEW Metal2 ( 436240 185360 ) Via2_VH
+ NEW Metal1 ( 436240 189840 ) Via1_VV
+ NEW Metal2 ( 448560 185360 ) RECT ( -280 -660 280 0 ) ;
+ - _0179_ ( _0762_ A2 ) ( _0727_ I ) ( _0726_ Z ) + USE SIGNAL
+ + ROUTED Metal2 ( 465360 184240 ) ( * 185360 )
+ NEW Metal3 ( 451920 185360 ) ( 465360 * )
+ NEW Metal3 ( 465360 185360 ) ( 474320 * )
+ NEW Metal1 ( 465360 184240 ) Via1_VV
+ NEW Metal2 ( 465360 185360 ) Via2_VH
+ NEW Metal1 ( 451920 185360 ) Via1_VV
+ NEW Metal2 ( 451920 185360 ) Via2_VH
+ NEW Metal1 ( 474320 185360 ) Via1_VV
+ NEW Metal2 ( 474320 185360 ) Via2_VH
+ NEW Metal2 ( 451920 185360 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 474320 185360 ) RECT ( -280 -660 280 0 ) ;
+ - _0180_ ( ANTENNA__0733__A1 I ) ( ANTENNA__0737__A2 I ) ( ANTENNA__0741__A2 I ) ( ANTENNA__0745__C I ) ( ANTENNA__0751__A1 I ) ( ANTENNA__0756__A1 I ) ( ANTENNA__0758__A1 I )
+ ( ANTENNA__0759__A1 I ) ( ANTENNA__0765__B I ) ( ANTENNA__0767__B I ) ( _0767_ B ) ( _0765_ B ) ( _0759_ A1 ) ( _0758_ A1 ) ( _0756_ A1 )
+ ( _0751_ A1 ) ( _0745_ C ) ( _0741_ A2 ) ( _0737_ A2 ) ( _0733_ A1 ) ( _0727_ Z ) + USE SIGNAL
+ + ROUTED Metal2 ( 537040 176400 ) ( * 177520 )
+ NEW Metal3 ( 537040 177520 ) ( 550480 * )
+ NEW Metal2 ( 550480 177520 ) ( * 190960 )
+ NEW Metal2 ( 538160 170800 ) ( * 176400 )
+ NEW Metal2 ( 537040 176400 ) ( 538160 * )
+ NEW Metal2 ( 542640 170800 ) ( * 177520 )
+ NEW Metal2 ( 549360 161840 ) ( 550480 * )
+ NEW Metal2 ( 550480 161840 ) ( * 177520 )
+ NEW Metal2 ( 543760 159600 ) ( * 166320 )
+ NEW Metal2 ( 542640 166320 ) ( 543760 * )
+ NEW Metal2 ( 542640 166320 ) ( * 170800 )
+ NEW Metal2 ( 535920 156240 ) ( * 158480 )
+ NEW Metal2 ( 535920 156240 ) ( 538160 * )
+ NEW Metal2 ( 538160 156240 ) ( * 170800 )
+ NEW Metal3 ( 524720 170800 ) ( 538160 * )
+ NEW Metal3 ( 516880 169680 ) ( 522480 * )
+ NEW Metal3 ( 522480 169680 ) ( * 170800 )
+ NEW Metal3 ( 522480 170800 ) ( 524720 * )
+ NEW Metal2 ( 520240 161840 ) ( 521360 * )
+ NEW Metal2 ( 520240 161840 ) ( * 165200 )
+ NEW Metal2 ( 516880 165200 ) ( 520240 * )
+ NEW Metal2 ( 516880 165200 ) ( * 169680 )
+ NEW Metal3 ( 512400 169680 ) ( 516880 * )
+ NEW Metal2 ( 512400 183120 ) ( 513520 * )
+ NEW Metal2 ( 513520 169680 ) ( * 183120 )
+ NEW Metal2 ( 512400 169680 ) ( 513520 * )
+ NEW Metal2 ( 514640 142800 ) ( 518000 * )
+ NEW Metal2 ( 518000 142800 ) ( * 165200 )
+ NEW Metal2 ( 512400 183120 ) ( * 184240 )
+ NEW Metal3 ( 512400 168560 ) ( * 169680 )
+ NEW Metal3 ( 550480 190960 ) ( 559440 * )
+ NEW Metal3 ( 498960 184240 ) ( * 185360 )
+ NEW Metal3 ( 484400 184240 ) ( 498960 * )
+ NEW Metal3 ( 479920 184240 ) ( 484400 * )
+ NEW Metal2 ( 484400 184240 ) ( * 192080 )
+ NEW Metal2 ( 476560 178640 ) ( * 184240 )
+ NEW Metal3 ( 476560 184240 ) ( 479920 * )
+ NEW Metal2 ( 476560 170800 ) ( * 178640 )
+ NEW Metal3 ( 496720 168560 ) ( 512400 * )
+ NEW Metal3 ( 498960 184240 ) ( 512400 * )
+ NEW Metal1 ( 550480 190960 ) Via1_VV
+ NEW Metal2 ( 550480 190960 ) Via2_VH
+ NEW Metal1 ( 537040 176400 ) Via1_HV
+ NEW Metal2 ( 537040 177520 ) Via2_VH
+ NEW Metal2 ( 550480 177520 ) Via2_VH
+ NEW Metal1 ( 538160 170800 ) Via1_VV
+ NEW Metal1 ( 542640 170800 ) Via1_VV
+ NEW Metal2 ( 542640 177520 ) Via2_VH
+ NEW Metal1 ( 549360 161840 ) Via1_VV
+ NEW Metal1 ( 543760 159600 ) Via1_VV
+ NEW Metal1 ( 535920 158480 ) Via1_VV
+ NEW Metal1 ( 524720 170800 ) Via1_VV
+ NEW Metal2 ( 524720 170800 ) Via2_VH
+ NEW Metal2 ( 538160 170800 ) Via2_VH
+ NEW Metal1 ( 516880 169680 ) Via1_VV
+ NEW Metal2 ( 516880 169680 ) Via2_VH
+ NEW Metal1 ( 521360 161840 ) Via1_VV
+ NEW Metal1 ( 512400 169680 ) Via1_VV
+ NEW Metal2 ( 512400 169680 ) Via2_VH
+ NEW Metal1 ( 512400 183120 ) Via1_VV
+ NEW Metal1 ( 514640 142800 ) Via1_VV
+ NEW Metal2 ( 512400 184240 ) Via2_VH
+ NEW Metal1 ( 559440 190960 ) Via1_VV
+ NEW Metal2 ( 559440 190960 ) Via2_VH
+ NEW Metal1 ( 498960 185360 ) Via1_VV
+ NEW Metal2 ( 498960 185360 ) Via2_VH
+ NEW Metal1 ( 484400 184240 ) Via1_VV
+ NEW Metal2 ( 484400 184240 ) Via2_VH
+ NEW Metal1 ( 479920 184240 ) Via1_VV
+ NEW Metal2 ( 479920 184240 ) Via2_VH
+ NEW Metal1 ( 484400 192080 ) Via1_VV
+ NEW Metal1 ( 476560 178640 ) Via1_HV
+ NEW Metal2 ( 476560 184240 ) Via2_VH
+ NEW Metal1 ( 476560 170800 ) Via1_VV
+ NEW Metal1 ( 496720 168560 ) Via1_HV
+ NEW Metal2 ( 496720 168560 ) Via2_VH
+ NEW Metal2 ( 550480 190960 ) RECT ( -280 -660 280 0 )
+ NEW Metal3 ( 542640 177520 ) RECT ( -1040 -280 0 280 )
+ NEW Metal2 ( 524720 170800 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 538160 170800 ) RECT ( -280 -1040 280 0 )
+ NEW Metal2 ( 516880 169680 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 512400 169680 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 559440 190960 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 498960 185360 ) RECT ( -280 0 280 660 )
+ NEW Metal2 ( 484400 184240 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 479920 184240 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 496720 168560 ) RECT ( -280 -660 280 0 ) ;
+ - _0181_ ( ANTENNA__0732__A1 I ) ( ANTENNA__0740__A2 I ) ( ANTENNA__0742__I I ) ( ANTENNA__0744__A2 I ) ( ANTENNA__0750__A2 I ) ( ANTENNA__0752__A2 I ) ( ANTENNA__0765__A1 I )
+ ( _0765_ A1 ) ( _0752_ A2 ) ( _0750_ A2 ) ( _0744_ A2 ) ( _0742_ I ) ( _0740_ A2 ) ( _0732_ A1 ) ( _0728_ Z ) + USE SIGNAL
+ + ROUTED Metal2 ( 498960 139440 ) ( 501200 * )
+ NEW Metal2 ( 495600 137200 ) ( 497840 * )
+ NEW Metal2 ( 497840 137200 ) ( * 138320 )
+ NEW Metal2 ( 497840 138320 ) ( 498960 * )
+ NEW Metal2 ( 498960 138320 ) ( * 139440 )
+ NEW Metal2 ( 523600 143920 ) ( * 151760 )
+ NEW Metal2 ( 521360 139440 ) ( * 141680 )
+ NEW Metal2 ( 521360 141680 ) ( 523600 * )
+ NEW Metal2 ( 523600 141680 ) ( * 143920 )
+ NEW Metal3 ( 523600 151760 ) ( 530320 * )
+ NEW Metal3 ( 530320 151760 ) ( 541520 * )
+ NEW Metal3 ( 473200 175280 ) ( 484400 * )
+ NEW Metal3 ( 484400 175280 ) ( 498960 * )
+ NEW Metal3 ( 498960 175280 ) ( 503440 * )
+ NEW Metal2 ( 500080 160720 ) ( * 175280 )
+ NEW Metal2 ( 498960 175280 ) ( 500080 * )
+ NEW Metal2 ( 483280 155120 ) ( * 175280 )
+ NEW Metal2 ( 483280 175280 ) ( 484400 * )
+ NEW Metal2 ( 478800 155120 ) ( 483280 * )
+ NEW Metal2 ( 497840 154000 ) ( 500080 * )
+ NEW Metal2 ( 500080 154000 ) ( * 160720 )
+ NEW Metal3 ( 473200 154000 ) ( 478800 * )
+ NEW Metal2 ( 478800 154000 ) ( * 155120 )
+ NEW Metal2 ( 498960 139440 ) ( * 154000 )
+ NEW Metal3 ( 498960 151760 ) ( 523600 * )
+ NEW Metal1 ( 501200 139440 ) Via1_VV
+ NEW Metal1 ( 495600 137200 ) Via1_VV
+ NEW Metal1 ( 523600 143920 ) Via1_VV
+ NEW Metal2 ( 523600 151760 ) Via2_VH
+ NEW Metal1 ( 521360 139440 ) Via1_VV
+ NEW Metal1 ( 530320 151760 ) Via1_VV
+ NEW Metal2 ( 530320 151760 ) Via2_VH
+ NEW Metal1 ( 541520 151760 ) Via1_VV
+ NEW Metal2 ( 541520 151760 ) Via2_VH
+ NEW Metal1 ( 484400 175280 ) Via1_VV
+ NEW Metal2 ( 484400 175280 ) Via2_VH
+ NEW Metal1 ( 473200 175280 ) Via1_HV
+ NEW Metal2 ( 473200 175280 ) Via2_VH
+ NEW Metal1 ( 498960 175280 ) Via1_VV
+ NEW Metal2 ( 498960 175280 ) Via2_VH
+ NEW Metal1 ( 503440 175280 ) Via1_VV
+ NEW Metal2 ( 503440 175280 ) Via2_VH
+ NEW Metal1 ( 500080 160720 ) Via1_VV
+ NEW Metal1 ( 483280 155120 ) Via1_VV
+ NEW Metal1 ( 478800 155120 ) Via1_VV
+ NEW Metal1 ( 497840 154000 ) Via1_VV
+ NEW Metal1 ( 473200 154000 ) Via1_HV
+ NEW Metal2 ( 473200 154000 ) Via2_VH
+ NEW Metal2 ( 478800 154000 ) Via2_VH
+ NEW Metal2 ( 498960 151760 ) Via2_VH
+ NEW Metal2 ( 530320 151760 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 541520 151760 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 484400 175280 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 473200 175280 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 498960 175280 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 503440 175280 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 473200 154000 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 498960 151760 ) RECT ( -280 0 280 1040 ) ;
+ - _0182_ ( _0730_ A3 ) ( _0729_ ZN ) + USE SIGNAL
+ + ROUTED Metal3 ( 444080 160720 ) ( 454160 * )
+ NEW Metal2 ( 454160 160720 ) ( * 168560 )
+ NEW Metal2 ( 444080 146160 ) ( * 160720 )
+ NEW Metal1 ( 444080 146160 ) Via1_VV
+ NEW Metal2 ( 444080 160720 ) Via2_VH
+ NEW Metal2 ( 454160 160720 ) Via2_VH
+ NEW Metal1 ( 454160 168560 ) Via1_HV ;
+ - _0183_ ( _0764_ A1 ) ( _0748_ A1 ) ( _0731_ I ) ( _0730_ Z ) + USE SIGNAL
+ + ROUTED Metal2 ( 505680 158480 ) ( * 169680 )
+ NEW Metal2 ( 504560 158480 ) ( 505680 * )
+ NEW Metal2 ( 504560 152880 ) ( * 158480 )
+ NEW Metal2 ( 504560 152880 ) ( 505680 * )
+ NEW Metal2 ( 468720 160720 ) ( * 169680 )
+ NEW Metal3 ( 468720 169680 ) ( 482160 * )
+ NEW Metal3 ( 458640 169680 ) ( 468720 * )
+ NEW Metal3 ( 482160 169680 ) ( 505680 * )
+ NEW Metal2 ( 505680 169680 ) Via2_VH
+ NEW Metal1 ( 505680 152880 ) Via1_HV
+ NEW Metal1 ( 482160 169680 ) Via1_VV
+ NEW Metal2 ( 482160 169680 ) Via2_VH
+ NEW Metal1 ( 468720 160720 ) Via1_HV
+ NEW Metal2 ( 468720 169680 ) Via2_VH
+ NEW Metal1 ( 458640 169680 ) Via1_VV
+ NEW Metal2 ( 458640 169680 ) Via2_VH
+ NEW Metal2 ( 482160 169680 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 458640 169680 ) RECT ( -280 -660 280 0 ) ;
+ - _0184_ ( ANTENNA__0732__A2 I ) ( ANTENNA__0738__A2 I ) ( ANTENNA__0741__A1 I ) ( ANTENNA__0744__B I ) ( ANTENNA__0745__A1 I ) ( ANTENNA__0749__A1 I ) ( ANTENNA__0750__A3 I )
+ ( ANTENNA__0753__A1 I ) ( ANTENNA__0765__A2 I ) ( ANTENNA__0767__C I ) ( _0767_ C ) ( _0765_ A2 ) ( _0753_ A1 ) ( _0750_ A3 ) ( _0749_ A1 )
+ ( _0745_ A1 ) ( _0744_ B ) ( _0741_ A1 ) ( _0738_ A2 ) ( _0732_ A2 ) ( _0731_ Z ) + USE SIGNAL
+ + ROUTED Metal2 ( 509040 160720 ) ( * 174160 )
+ NEW Metal2 ( 507920 174160 ) ( 509040 * )
+ NEW Metal2 ( 507920 174160 ) ( * 183120 )
+ NEW Metal2 ( 507920 167440 ) ( 509040 * )
+ NEW Metal2 ( 509040 174160 ) ( 512400 * )
+ NEW Metal2 ( 505680 146160 ) ( * 150640 )
+ NEW Metal2 ( 502320 150640 ) ( 505680 * )
+ NEW Metal2 ( 513520 139440 ) ( * 146160 )
+ NEW Metal2 ( 505680 146160 ) ( 513520 * )
+ NEW Metal2 ( 513520 139440 ) ( 518000 * )
+ NEW Metal2 ( 521360 142800 ) ( * 151760 )
+ NEW Metal2 ( 520240 142800 ) ( 521360 * )
+ NEW Metal2 ( 520240 139440 ) ( * 142800 )
+ NEW Metal2 ( 518000 139440 ) ( 520240 * )
+ NEW Metal2 ( 521360 145040 ) ( 522480 * )
+ NEW Metal2 ( 524720 183120 ) ( * 189840 )
+ NEW Metal3 ( 507920 183120 ) ( 524720 * )
+ NEW Metal3 ( 521360 150640 ) ( 531440 * )
+ NEW Metal2 ( 537040 150640 ) ( * 151760 )
+ NEW Metal3 ( 531440 150640 ) ( 537040 * )
+ NEW Metal3 ( 475440 192080 ) ( 482160 * )
+ NEW Metal2 ( 475440 192080 ) ( * 198800 )
+ NEW Metal2 ( 475440 198800 ) ( 477680 * )
+ NEW Metal3 ( 470960 176400 ) ( 475440 * )
+ NEW Metal2 ( 475440 176400 ) ( * 192080 )
+ NEW Metal3 ( 466480 176400 ) ( 470960 * )
+ NEW Metal2 ( 470960 161840 ) ( 472080 * )
+ NEW Metal2 ( 470960 161840 ) ( * 176400 )
+ NEW Metal2 ( 487760 155120 ) ( 490000 * )
+ NEW Metal2 ( 490000 155120 ) ( * 176400 )
+ NEW Metal3 ( 475440 176400 ) ( 490000 * )
+ NEW Metal2 ( 490000 160720 ) ( 493360 * )
+ NEW Metal2 ( 501200 176400 ) ( * 185360 )
+ NEW Metal3 ( 490000 176400 ) ( 501200 * )
+ NEW Metal2 ( 501200 170800 ) ( * 176400 )
+ NEW Metal2 ( 501200 168560 ) ( 502320 * )
+ NEW Metal2 ( 501200 168560 ) ( * 170800 )
+ NEW Metal2 ( 502320 150640 ) ( * 168560 )
+ NEW Metal3 ( 501200 183120 ) ( 507920 * )
+ NEW Metal1 ( 507920 183120 ) Via1_VV
+ NEW Metal2 ( 507920 183120 ) Via2_VH
+ NEW Metal1 ( 509040 160720 ) Via1_VV
+ NEW Metal1 ( 507920 167440 ) Via1_VV
+ NEW Metal1 ( 512400 174160 ) Via1_VV
+ NEW Metal1 ( 505680 146160 ) Via1_VV
+ NEW Metal1 ( 513520 139440 ) Via1_VV
+ NEW Metal1 ( 518000 139440 ) Via1_VV
+ NEW Metal1 ( 521360 151760 ) Via1_VV
+ NEW Metal1 ( 522480 145040 ) Via1_VV
+ NEW Metal1 ( 524720 189840 ) Via1_VV
+ NEW Metal2 ( 524720 183120 ) Via2_VH
+ NEW Metal1 ( 531440 150640 ) Via1_VV
+ NEW Metal2 ( 531440 150640 ) Via2_VH
+ NEW Metal2 ( 521360 150640 ) Via2_VH
+ NEW Metal1 ( 537040 151760 ) Via1_VV
+ NEW Metal2 ( 537040 150640 ) Via2_VH
+ NEW Metal1 ( 482160 192080 ) Via1_VV
+ NEW Metal2 ( 482160 192080 ) Via2_VH
+ NEW Metal2 ( 475440 192080 ) Via2_VH
+ NEW Metal1 ( 477680 198800 ) Via1_VV
+ NEW Metal1 ( 470960 176400 ) Via1_VV
+ NEW Metal2 ( 470960 176400 ) Via2_VH
+ NEW Metal2 ( 475440 176400 ) Via2_VH
+ NEW Metal1 ( 466480 176400 ) Via1_VV
+ NEW Metal2 ( 466480 176400 ) Via2_VH
+ NEW Metal1 ( 472080 161840 ) Via1_HV
+ NEW Metal1 ( 487760 155120 ) Via1_VV
+ NEW Metal2 ( 490000 176400 ) Via2_VH
+ NEW Metal1 ( 493360 160720 ) Via1_VV
+ NEW Metal1 ( 501200 185360 ) Via1_HV
+ NEW Metal2 ( 501200 176400 ) Via2_VH
+ NEW Metal1 ( 501200 170800 ) Via1_VV
+ NEW Metal2 ( 501200 183120 ) Via2_VH
+ NEW Metal2 ( 507920 183120 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 531440 150640 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 521360 150640 ) RECT ( -280 -1040 280 0 )
+ NEW Metal2 ( 482160 192080 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 470960 176400 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 466480 176400 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 501200 183120 ) RECT ( -280 -1040 280 0 ) ;
+ - _0185_ ( _0757_ A1 ) ( _0733_ A2 ) ( _0732_ ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 542640 156240 ) ( * 159600 )
+ NEW Metal3 ( 525840 156240 ) ( 542640 * )
+ NEW Metal2 ( 525840 145040 ) ( * 156240 )
+ NEW Metal2 ( 532560 156240 ) ( * 169680 )
+ NEW Metal1 ( 542640 159600 ) Via1_VV
+ NEW Metal2 ( 542640 156240 ) Via2_VH
+ NEW Metal2 ( 525840 156240 ) Via2_VH
+ NEW Metal1 ( 525840 145040 ) Via1_VV
+ NEW Metal1 ( 532560 169680 ) Via1_VV
+ NEW Metal2 ( 532560 156240 ) Via2_VH
+ NEW Metal3 ( 532560 156240 ) RECT ( -1040 -280 0 280 ) ;
+ - _0186_ ( _0751_ B2 ) ( _0736_ A2 ) ( _0733_ ZN ) + USE SIGNAL
+ + ROUTED Metal3 ( 525840 158480 ) ( 537040 * )
+ NEW Metal2 ( 537040 158480 ) ( * 171920 )
+ NEW Metal2 ( 533680 171920 ) ( 537040 * )
+ NEW Metal2 ( 533680 171920 ) ( * 199920 )
+ NEW Metal3 ( 537040 158480 ) ( 546000 * )
+ NEW Metal1 ( 525840 158480 ) Via1_VV
+ NEW Metal2 ( 525840 158480 ) Via2_VH
+ NEW Metal2 ( 537040 158480 ) Via2_VH
+ NEW Metal1 ( 533680 199920 ) Via1_VV
+ NEW Metal1 ( 546000 158480 ) Via1_VV
+ NEW Metal2 ( 546000 158480 ) Via2_VH
+ NEW Metal2 ( 525840 158480 ) RECT ( -280 0 280 660 )
+ NEW Metal2 ( 546000 158480 ) RECT ( -280 -660 280 0 ) ;
+ - _0187_ ( ANTENNA__0735__I I ) ( ANTENNA__0737__A1 I ) ( ANTENNA__0746__C I ) ( ANTENNA__0754__A1 I ) ( ANTENNA__0766__A1 I ) ( ANTENNA__0768__C I ) ( ANTENNA__0770__C I )
+ ( _0770_ C ) ( _0768_ C ) ( _0766_ A1 ) ( _0754_ A1 ) ( _0746_ C ) ( _0737_ A1 ) ( _0735_ I ) ( _0734_ Z ) + USE SIGNAL
+ + ROUTED Metal2 ( 509040 201600 ) ( * 205520 )
+ NEW Metal2 ( 507920 190960 ) ( * 199920 )
+ NEW Metal2 ( 507920 201600 ) ( 509040 * )
+ NEW Metal2 ( 507920 199920 ) ( * 201600 )
+ NEW Metal2 ( 509040 177520 ) ( * 190960 )
+ NEW Metal2 ( 507920 190960 ) ( 509040 * )
+ NEW Metal3 ( 509040 185360 ) ( 522480 * )
+ NEW Metal2 ( 548240 188720 ) ( * 189840 )
+ NEW Metal3 ( 522480 188720 ) ( 548240 * )
+ NEW Metal2 ( 522480 185360 ) ( * 188720 )
+ NEW Metal2 ( 548240 189840 ) ( * 198800 )
+ NEW Metal2 ( 552720 185360 ) ( * 188720 )
+ NEW Metal3 ( 548240 188720 ) ( 552720 * )
+ NEW Metal2 ( 552720 184240 ) ( * 185360 )
+ NEW Metal2 ( 552720 184240 ) ( 557200 * )
+ NEW Metal2 ( 503440 198800 ) ( * 199920 )
+ NEW Metal2 ( 503440 199920 ) ( * 207760 )
+ NEW Metal3 ( 442960 193200 ) ( 462000 * )
+ NEW Metal2 ( 442960 193200 ) ( * 206640 )
+ NEW Metal3 ( 462000 193200 ) ( 467600 * )
+ NEW Metal2 ( 497840 189840 ) ( 498960 * )
+ NEW Metal2 ( 497840 189840 ) ( * 193200 )
+ NEW Metal3 ( 467600 193200 ) ( 497840 * )
+ NEW Metal3 ( 497840 190960 ) ( 507920 * )
+ NEW Metal3 ( 503440 198800 ) ( 507920 * )
+ NEW Metal1 ( 509040 205520 ) Via1_VV
+ NEW Metal1 ( 507920 190960 ) Via1_VV
+ NEW Metal2 ( 507920 190960 ) Via2_VH
+ NEW Metal1 ( 507920 199920 ) Via1_VV
+ NEW Metal2 ( 507920 198800 ) Via2_VH
+ NEW Metal1 ( 509040 177520 ) Via1_VV
+ NEW Metal1 ( 522480 185360 ) Via1_VV
+ NEW Metal2 ( 522480 185360 ) Via2_VH
+ NEW Metal2 ( 509040 185360 ) Via2_VH
+ NEW Metal1 ( 548240 189840 ) Via1_VV
+ NEW Metal2 ( 548240 188720 ) Via2_VH
+ NEW Metal2 ( 522480 188720 ) Via2_VH
+ NEW Metal1 ( 548240 198800 ) Via1_VV
+ NEW Metal1 ( 552720 185360 ) Via1_VV
+ NEW Metal2 ( 552720 188720 ) Via2_VH
+ NEW Metal1 ( 557200 184240 ) Via1_VV
+ NEW Metal1 ( 503440 199920 ) Via1_HV
+ NEW Metal2 ( 503440 198800 ) Via2_VH
+ NEW Metal1 ( 503440 207760 ) Via1_HV
+ NEW Metal1 ( 462000 193200 ) Via1_VV
+ NEW Metal2 ( 462000 193200 ) Via2_VH
+ NEW Metal2 ( 442960 193200 ) Via2_VH
+ NEW Metal1 ( 442960 206640 ) Via1_HV
+ NEW Metal1 ( 467600 193200 ) Via1_VV
+ NEW Metal2 ( 467600 193200 ) Via2_VH
+ NEW Metal1 ( 498960 189840 ) Via1_VV
+ NEW Metal2 ( 497840 193200 ) Via2_VH
+ NEW Metal2 ( 497840 190960 ) Via2_VH
+ NEW Metal2 ( 507920 190960 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 507920 198800 ) RECT ( -280 -1040 280 0 )
+ NEW Metal2 ( 522480 185360 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 509040 185360 ) RECT ( -280 -1040 280 0 )
+ NEW Metal2 ( 462000 193200 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 467600 193200 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 497840 190960 ) RECT ( -280 -1040 280 0 ) ;
+ - _0188_ ( _0760_ A1 ) ( _0759_ C ) ( _0736_ B ) ( _0735_ ZN ) + USE SIGNAL
+ + ROUTED Metal3 ( 532560 185360 ) ( 538160 * )
+ NEW Metal2 ( 538160 185360 ) ( * 201040 )
+ NEW Metal2 ( 540400 176400 ) ( * 178640 )
+ NEW Metal2 ( 538160 178640 ) ( 540400 * )
+ NEW Metal2 ( 538160 178640 ) ( * 185360 )
+ NEW Metal3 ( 538160 185360 ) ( 551600 * )
+ NEW Metal1 ( 532560 185360 ) Via1_HV
+ NEW Metal2 ( 532560 185360 ) Via2_VH
+ NEW Metal2 ( 538160 185360 ) Via2_VH
+ NEW Metal1 ( 538160 201040 ) Via1_VV
+ NEW Metal1 ( 540400 176400 ) Via1_HV
+ NEW Metal1 ( 551600 185360 ) Via1_VV
+ NEW Metal2 ( 551600 185360 ) Via2_VH
+ NEW Metal2 ( 532560 185360 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 551600 185360 ) RECT ( -280 -660 280 0 ) ;
+ - _0189_ ( _0747_ A2 ) ( _0736_ ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 534800 201040 ) ( * 201600 )
+ NEW Metal2 ( 528080 201600 ) ( 534800 * )
+ NEW Metal2 ( 528080 201040 ) ( * 201600 )
+ NEW Metal1 ( 534800 201040 ) Via1_VV
+ NEW Metal1 ( 528080 201040 ) Via1_VV ;
+ - _0190_ ( _0755_ A1 ) ( _0754_ B2 ) ( _0738_ A4 ) ( _0737_ ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 544880 186480 ) ( * 193200 )
+ NEW Metal2 ( 544880 193200 ) ( 547120 * )
+ NEW Metal3 ( 520240 190960 ) ( 544880 * )
+ NEW Metal2 ( 518000 185360 ) ( * 190960 )
+ NEW Metal2 ( 518000 190960 ) ( 520240 * )
+ NEW Metal1 ( 544880 186480 ) Via1_VV
+ NEW Metal1 ( 547120 193200 ) Via1_HV
+ NEW Metal1 ( 520240 190960 ) Via1_VV
+ NEW Metal2 ( 520240 190960 ) Via2_VH
+ NEW Metal2 ( 544880 190960 ) Via2_VH
+ NEW Metal1 ( 518000 185360 ) Via1_VV
+ NEW Metal2 ( 520240 190960 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 544880 190960 ) RECT ( -280 -1040 280 0 ) ;
+ - _0191_ ( _0747_ B ) ( _0738_ ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 521360 194320 ) ( * 199920 )
+ NEW Metal2 ( 521360 199920 ) ( 523600 * )
+ NEW Metal1 ( 521360 194320 ) Via1_VV
+ NEW Metal1 ( 523600 199920 ) Via1_HV ;
+ - _0192_ ( _0770_ A1 ) ( _0744_ A1 ) ( _0740_ A1 ) ( _0739_ Z ) + USE SIGNAL
+ + ROUTED Metal2 ( 487760 176400 ) ( * 192080 )
+ NEW Metal3 ( 487760 192080 ) ( 498960 * )
+ NEW Metal2 ( 498960 192080 ) ( * 205520 )
+ NEW Metal2 ( 487760 161840 ) ( 488880 * )
+ NEW Metal2 ( 487760 161840 ) ( * 176400 )
+ NEW Metal2 ( 497840 160720 ) ( * 161840 )
+ NEW Metal3 ( 488880 161840 ) ( 497840 * )
+ NEW Metal1 ( 487760 176400 ) Via1_HV
+ NEW Metal2 ( 487760 192080 ) Via2_VH
+ NEW Metal2 ( 498960 192080 ) Via2_VH
+ NEW Metal1 ( 498960 205520 ) Via1_VV
+ NEW Metal1 ( 488880 161840 ) Via1_VV
+ NEW Metal1 ( 497840 160720 ) Via1_VV
+ NEW Metal2 ( 497840 161840 ) Via2_VH
+ NEW Metal2 ( 488880 161840 ) Via2_VH
+ NEW Metal2 ( 488880 161840 ) RECT ( -280 -1040 280 0 ) ;
+ - _0193_ ( _0767_ A1 ) ( _0762_ A1 ) ( _0746_ A1 ) ( _0740_ ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 485520 177520 ) ( * 183120 )
+ NEW Metal3 ( 463120 183120 ) ( 485520 * )
+ NEW Metal2 ( 497840 183120 ) ( * 185360 )
+ NEW Metal3 ( 485520 183120 ) ( 497840 * )
+ NEW Metal2 ( 494480 186480 ) ( * 190960 )
+ NEW Metal2 ( 494480 186480 ) ( 496720 * )
+ NEW Metal2 ( 496720 185360 ) ( * 186480 )
+ NEW Metal2 ( 496720 185360 ) ( 497840 * )
+ NEW Metal1 ( 485520 177520 ) Via1_VV
+ NEW Metal2 ( 485520 183120 ) Via2_VH
+ NEW Metal1 ( 463120 183120 ) Via1_VV
+ NEW Metal2 ( 463120 183120 ) Via2_VH
+ NEW Metal1 ( 497840 185360 ) Via1_VV
+ NEW Metal2 ( 497840 183120 ) Via2_VH
+ NEW Metal1 ( 494480 190960 ) Via1_VV
+ NEW Metal2 ( 463120 183120 ) RECT ( -280 -660 280 0 ) ;
+ - _0194_ ( _0770_ A2 ) ( _0768_ A2 ) ( _0746_ A2 ) ( _0741_ Z ) + USE SIGNAL
+ + ROUTED Metal2 ( 495600 202160 ) ( 496720 * )
+ NEW Metal2 ( 496720 202160 ) ( * 205520 )
+ NEW Metal2 ( 496720 192080 ) ( * 196560 )
+ NEW Metal2 ( 495600 196560 ) ( 496720 * )
+ NEW Metal2 ( 495600 196560 ) ( * 202160 )
+ NEW Metal2 ( 487760 194320 ) ( * 196560 )
+ NEW Metal3 ( 487760 196560 ) ( 495600 * )
+ NEW Metal1 ( 495600 202160 ) Via1_VV
+ NEW Metal1 ( 496720 205520 ) Via1_VV
+ NEW Metal1 ( 496720 192080 ) Via1_HV
+ NEW Metal1 ( 487760 194320 ) Via1_VV
+ NEW Metal2 ( 487760 196560 ) Via2_VH
+ NEW Metal2 ( 495600 196560 ) Via2_VH
+ NEW Metal2 ( 495600 196560 ) RECT ( -280 0 280 1040 ) ;
+ - _0195_ ( _0743_ A2 ) ( _0742_ ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 496720 139440 ) ( 497840 * )
+ NEW Metal2 ( 497840 139440 ) ( * 143920 )
+ NEW Metal1 ( 496720 139440 ) Via1_VV
+ NEW Metal1 ( 497840 143920 ) Via1_VV ;
+ - _0196_ ( _0756_ A2 ) ( _0749_ A2 ) ( _0748_ A2 ) ( _0745_ A2 ) ( _0743_ ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 519120 152880 ) ( * 159600 )
+ NEW Metal3 ( 519120 159600 ) ( 534800 * )
+ NEW Metal3 ( 509040 152880 ) ( 519120 * )
+ NEW Metal3 ( 501200 152880 ) ( * 154000 )
+ NEW Metal3 ( 501200 154000 ) ( 503440 * )
+ NEW Metal2 ( 503440 154000 ) ( * 168560 )
+ NEW Metal2 ( 501200 147280 ) ( * 152880 )
+ NEW Metal3 ( 501200 152880 ) ( 509040 * )
+ NEW Metal1 ( 519120 152880 ) Via1_VV
+ NEW Metal2 ( 519120 159600 ) Via2_VH
+ NEW Metal1 ( 534800 159600 ) Via1_VV
+ NEW Metal2 ( 534800 159600 ) Via2_VH
+ NEW Metal1 ( 509040 152880 ) Via1_VV
+ NEW Metal2 ( 509040 152880 ) Via2_VH
+ NEW Metal2 ( 519120 152880 ) Via2_VH
+ NEW Metal1 ( 501200 147280 ) Via1_VV
+ NEW Metal2 ( 501200 152880 ) Via2_VH
+ NEW Metal2 ( 503440 154000 ) Via2_VH
+ NEW Metal1 ( 503440 168560 ) Via1_VV
+ NEW Metal2 ( 534800 159600 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 509040 152880 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 519120 152880 ) RECT ( -280 -1040 280 0 ) ;
+ - _0197_ ( _0758_ A2 ) ( _0745_ B ) ( _0744_ ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 498960 161840 ) ( * 168560 )
+ NEW Metal3 ( 498960 167440 ) ( 522480 * )
+ NEW Metal1 ( 522480 167440 ) Via1_VV
+ NEW Metal2 ( 522480 167440 ) Via2_VH
+ NEW Metal1 ( 498960 168560 ) Via1_HV
+ NEW Metal1 ( 498960 161840 ) Via1_VV
+ NEW Metal2 ( 498960 167440 ) Via2_VH
+ NEW Metal2 ( 522480 167440 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 498960 167440 ) RECT ( -280 -1040 280 0 ) ;
+ - _0198_ ( _0746_ B2 ) ( _0745_ ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 503440 180880 ) ( * 192080 )
+ NEW Metal2 ( 502320 180880 ) ( 503440 * )
+ NEW Metal2 ( 502320 170800 ) ( * 180880 )
+ NEW Metal1 ( 503440 192080 ) Via1_VV
+ NEW Metal1 ( 502320 170800 ) Via1_VV ;
+ - _0199_ ( _0747_ C ) ( _0746_ ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 520240 194320 ) ( * 199920 )
+ NEW Metal2 ( 495600 192080 ) ( * 194320 )
+ NEW Metal3 ( 495600 194320 ) ( 520240 * )
+ NEW Metal2 ( 520240 194320 ) Via2_VH
+ NEW Metal1 ( 520240 199920 ) Via1_HV
+ NEW Metal2 ( 495600 194320 ) Via2_VH
+ NEW Metal1 ( 495600 192080 ) Via1_VV ;
+ - _0200_ ( _0753_ B ) ( _0751_ A2 ) ( _0748_ ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 511280 160720 ) ( * 161840 )
+ NEW Metal3 ( 511280 161840 ) ( 519120 * )
+ NEW Metal2 ( 507920 155120 ) ( 509040 * )
+ NEW Metal2 ( 509040 155120 ) ( * 156240 )
+ NEW Metal2 ( 509040 156240 ) ( 510160 * )
+ NEW Metal2 ( 510160 156240 ) ( * 160720 )
+ NEW Metal2 ( 510160 160720 ) ( 511280 * )
+ NEW Metal1 ( 511280 160720 ) Via1_VV
+ NEW Metal2 ( 511280 161840 ) Via2_VH
+ NEW Metal1 ( 519120 161840 ) Via1_VV
+ NEW Metal2 ( 519120 161840 ) Via2_VH
+ NEW Metal1 ( 507920 155120 ) Via1_VV
+ NEW Metal2 ( 519120 161840 ) RECT ( -280 0 280 660 ) ;
+ - _0201_ ( _0751_ A3 ) ( _0749_ Z ) + USE SIGNAL
+ + ROUTED Metal2 ( 515760 155120 ) ( 516880 * )
+ NEW Metal2 ( 516880 155120 ) ( * 160720 )
+ NEW Metal1 ( 515760 155120 ) Via1_HV
+ NEW Metal1 ( 516880 160720 ) Via1_VV ;
+ - _0202_ ( _0755_ A2 ) ( _0751_ B1 ) ( _0750_ ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 531440 155120 ) ( * 168560 )
+ NEW Metal3 ( 531440 168560 ) ( 543760 * )
+ NEW Metal2 ( 543760 168560 ) ( * 184240 )
+ NEW Metal2 ( 523600 159600 ) ( 524720 * )
+ NEW Metal2 ( 524720 159600 ) ( * 160720 )
+ NEW Metal2 ( 524720 160720 ) ( 531440 * )
+ NEW Metal1 ( 531440 155120 ) Via1_VV
+ NEW Metal2 ( 531440 168560 ) Via2_VH
+ NEW Metal2 ( 543760 168560 ) Via2_VH
+ NEW Metal1 ( 543760 184240 ) Via1_VV
+ NEW Metal1 ( 523600 159600 ) Via1_VV ;
+ - _0203_ ( _0754_ A2 ) ( _0751_ ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 523600 161840 ) ( * 184240 )
+ NEW Metal1 ( 523600 161840 ) Via1_HV
+ NEW Metal1 ( 523600 184240 ) Via1_VV ;
+ - _0204_ ( _0763_ I ) ( _0753_ A2 ) ( _0752_ ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 494480 155120 ) ( * 175280 )
+ NEW Metal3 ( 494480 160720 ) ( 504560 * )
+ NEW Metal1 ( 504560 160720 ) Via1_VV
+ NEW Metal2 ( 504560 160720 ) Via2_VH
+ NEW Metal1 ( 494480 155120 ) Via1_VV
+ NEW Metal1 ( 494480 175280 ) Via1_VV
+ NEW Metal2 ( 494480 160720 ) Via2_VH
+ NEW Metal2 ( 504560 160720 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 494480 160720 ) RECT ( -280 -1040 280 0 ) ;
+ - _0205_ ( _0759_ A2 ) ( _0754_ B1 ) ( _0753_ ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 520240 170800 ) ( * 185360 )
+ NEW Metal3 ( 506800 170800 ) ( 520240 * )
+ NEW Metal2 ( 506800 161840 ) ( * 170800 )
+ NEW Metal3 ( 520240 175280 ) ( 534800 * )
+ NEW Metal1 ( 520240 185360 ) Via1_VV
+ NEW Metal2 ( 520240 170800 ) Via2_VH
+ NEW Metal2 ( 506800 170800 ) Via2_VH
+ NEW Metal1 ( 506800 161840 ) Via1_VV
+ NEW Metal1 ( 534800 175280 ) Via1_VV
+ NEW Metal2 ( 534800 175280 ) Via2_VH
+ NEW Metal2 ( 520240 175280 ) Via2_VH
+ NEW Metal2 ( 534800 175280 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 520240 175280 ) RECT ( -280 -1040 280 0 ) ;
+ - _0206_ ( _0761_ A2 ) ( _0754_ ZN ) + USE SIGNAL
+ + ROUTED Metal3 ( 521360 186480 ) ( 540400 * )
+ NEW Metal2 ( 540400 186480 ) ( * 189840 )
+ NEW Metal1 ( 521360 186480 ) Via1_VV
+ NEW Metal2 ( 521360 186480 ) Via2_VH
+ NEW Metal2 ( 540400 186480 ) Via2_VH
+ NEW Metal1 ( 540400 189840 ) Via1_VV
+ NEW Metal2 ( 521360 186480 ) RECT ( -280 -660 280 0 ) ;
+ - _0207_ ( _0761_ B1 ) ( _0755_ ZN ) + USE SIGNAL
+ + ROUTED Metal3 ( 537040 184240 ) ( 547120 * )
+ NEW Metal2 ( 537040 184240 ) ( * 189840 )
+ NEW Metal1 ( 547120 184240 ) Via1_VV
+ NEW Metal2 ( 547120 184240 ) Via2_VH
+ NEW Metal2 ( 537040 184240 ) Via2_VH
+ NEW Metal1 ( 537040 189840 ) Via1_VV
+ NEW Metal2 ( 547120 184240 ) RECT ( -280 -660 280 0 ) ;
+ - _0208_ ( _0757_ A2 ) ( _0756_ ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 535920 162960 ) ( * 168560 )
+ NEW Metal2 ( 533680 168560 ) ( 535920 * )
+ NEW Metal1 ( 535920 162960 ) Via1_VV
+ NEW Metal1 ( 533680 168560 ) Via1_VV ;
+ - _0209_ ( _0760_ A2 ) ( _0757_ ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 530320 170800 ) ( * 184240 )
+ NEW Metal1 ( 530320 170800 ) Via1_VV
+ NEW Metal1 ( 530320 184240 ) Via1_VV ;
+ - _0210_ ( _0759_ B ) ( _0758_ ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 525840 167440 ) ( * 176400 )
+ NEW Metal3 ( 525840 176400 ) ( 539280 * )
+ NEW Metal1 ( 525840 167440 ) Via1_HV
+ NEW Metal2 ( 525840 176400 ) Via2_VH
+ NEW Metal1 ( 539280 176400 ) Via1_VV
+ NEW Metal2 ( 539280 176400 ) Via2_VH
+ NEW Metal2 ( 539280 176400 ) RECT ( -280 -660 280 0 ) ;
+ - _0211_ ( _0760_ B ) ( _0759_ ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 535920 177520 ) ( * 182000 )
+ NEW Metal1 ( 535920 182000 ) Via1_HV
+ NEW Metal1 ( 535920 177520 ) Via1_VV ;
+ - _0212_ ( _0761_ B2 ) ( _0760_ ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 534800 186480 ) ( * 190960 )
+ NEW Metal1 ( 534800 190960 ) Via1_VV
+ NEW Metal1 ( 534800 186480 ) Via1_HV ;
+ - _0213_ ( _0766_ A2 ) ( _0762_ Z ) + USE SIGNAL
+ + ROUTED Metal2 ( 468720 186480 ) ( 469840 * )
+ NEW Metal2 ( 469840 186480 ) ( * 192080 )
+ NEW Metal1 ( 468720 186480 ) Via1_HV
+ NEW Metal1 ( 469840 192080 ) Via1_VV ;
+ - _0214_ ( _0767_ A2 ) ( _0764_ A2 ) ( _0763_ ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 493360 178640 ) ( * 184240 )
+ NEW Metal2 ( 493360 184240 ) ( 495600 * )
+ NEW Metal2 ( 484400 167440 ) ( * 168560 )
+ NEW Metal3 ( 484400 168560 ) ( 493360 * )
+ NEW Metal2 ( 493360 168560 ) ( * 178640 )
+ NEW Metal1 ( 493360 178640 ) Via1_VV
+ NEW Metal1 ( 495600 184240 ) Via1_VV
+ NEW Metal1 ( 484400 167440 ) Via1_VV
+ NEW Metal2 ( 484400 168560 ) Via2_VH
+ NEW Metal2 ( 493360 168560 ) Via2_VH ;
+ - _0215_ ( _0765_ C ) ( _0764_ ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 478800 176400 ) ( 481040 * )
+ NEW Metal2 ( 481040 167440 ) ( * 176400 )
+ NEW Metal1 ( 478800 176400 ) Via1_HV
+ NEW Metal1 ( 481040 167440 ) Via1_HV ;
+ - _0216_ ( _0766_ A3 ) ( _0765_ ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 472080 177520 ) ( * 192080 )
+ NEW Metal1 ( 472080 192080 ) Via1_VV
+ NEW Metal1 ( 472080 177520 ) Via1_VV ;
+ - _0217_ ( _0769_ A1 ) ( _0766_ Z ) + USE SIGNAL
+ + ROUTED Metal2 ( 476560 194320 ) ( * 195440 )
+ NEW Metal2 ( 476560 195440 ) ( 478800 * )
+ NEW Metal2 ( 478800 195440 ) ( * 198800 )
+ NEW Metal2 ( 478800 198800 ) ( 482160 * )
+ NEW Metal1 ( 476560 194320 ) Via1_VV
+ NEW Metal1 ( 482160 198800 ) Via1_VV ;
+ - _0218_ ( _0768_ B ) ( _0767_ ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 500080 183120 ) ( * 199920 )
+ NEW Metal2 ( 498960 183120 ) ( 500080 * )
+ NEW Metal1 ( 500080 199920 ) Via1_HV
+ NEW Metal1 ( 498960 183120 ) Via1_HV ;
+ - _0219_ ( _0769_ A2 ) ( _0768_ ZN ) + USE SIGNAL
+ + ROUTED Metal3 ( 484400 198800 ) ( 496720 * )
+ NEW Metal1 ( 484400 198800 ) Via1_VV
+ NEW Metal2 ( 484400 198800 ) Via2_VH
+ NEW Metal1 ( 496720 198800 ) Via1_VV
+ NEW Metal2 ( 496720 198800 ) Via2_VH
+ NEW Metal2 ( 484400 198800 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 496720 198800 ) RECT ( -280 -660 280 0 ) ;
+ - _0220_ ( _0771_ A2 ) ( _0769_ Z ) + USE SIGNAL
+ + ROUTED Metal2 ( 487760 202160 ) ( 488880 * )
+ NEW Metal2 ( 488880 202160 ) ( * 215600 )
+ NEW Metal2 ( 488880 215600 ) ( 495600 * )
+ NEW Metal1 ( 487760 202160 ) Via1_HV
+ NEW Metal1 ( 495600 215600 ) Via1_VV ;
+ - _0221_ ( _0771_ B ) ( _0770_ ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 504560 208880 ) ( * 210000 )
+ NEW Metal3 ( 502320 210000 ) ( 503440 * )
+ NEW Metal3 ( 502320 210000 ) ( * 213360 )
+ NEW Metal2 ( 502320 213360 ) ( * 215600 )
+ NEW Metal2 ( 503440 210000 ) ( 504560 * )
+ NEW Metal1 ( 504560 208880 ) Via1_HV
+ NEW Metal2 ( 503440 210000 ) Via2_VH
+ NEW Metal2 ( 502320 213360 ) Via2_VH
+ NEW Metal1 ( 502320 215600 ) Via1_VV ;
+ - _0222_ ( _0775_ A1 ) ( _0772_ ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 299600 285040 ) ( * 292880 )
+ NEW Metal3 ( 299600 285040 ) ( 319760 * )
+ NEW Metal2 ( 299600 285040 ) Via2_VH
+ NEW Metal1 ( 299600 292880 ) Via1_HV
+ NEW Metal1 ( 319760 285040 ) Via1_VV
+ NEW Metal2 ( 319760 285040 ) Via2_VH
+ NEW Metal2 ( 319760 285040 ) RECT ( -280 -660 280 0 ) ;
+ - _0223_ ( _0791_ A3 ) ( _0774_ A2 ) ( _0773_ ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 322000 295120 ) ( * 309680 )
+ NEW Metal2 ( 322000 288400 ) ( * 295120 )
+ NEW Metal3 ( 313040 288400 ) ( 322000 * )
+ NEW Metal1 ( 313040 288400 ) Via1_VV
+ NEW Metal2 ( 313040 288400 ) Via2_VH
+ NEW Metal1 ( 322000 295120 ) Via1_VV
+ NEW Metal1 ( 322000 309680 ) Via1_VV
+ NEW Metal2 ( 322000 288400 ) Via2_VH
+ NEW Metal2 ( 313040 288400 ) RECT ( -280 -660 280 0 ) ;
+ - _0224_ ( ANTENNA__0775__A2 I ) ( ANTENNA__1106__A2 I ) ( _1106_ A2 ) ( _0775_ A2 ) ( _0774_ ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 373520 233520 ) ( * 234640 )
+ NEW Metal2 ( 325360 266000 ) ( * 283920 )
+ NEW Metal2 ( 325360 266000 ) ( 332080 * )
+ NEW Metal2 ( 332080 234640 ) ( * 266000 )
+ NEW Metal3 ( 332080 234640 ) ( 373520 * )
+ NEW Metal2 ( 325360 283920 ) ( * 294000 )
+ NEW Metal2 ( 320880 286160 ) ( 323120 * )
+ NEW Metal2 ( 323120 286160 ) ( * 288400 )
+ NEW Metal1 ( 323120 288400 ) ( 325360 * )
+ NEW Metal2 ( 395920 234640 ) ( * 239120 )
+ NEW Metal3 ( 373520 234640 ) ( 395920 * )
+ NEW Metal1 ( 373520 233520 ) Via1_VV
+ NEW Metal2 ( 373520 234640 ) Via2_VH
+ NEW Metal1 ( 325360 283920 ) Via1_VV
+ NEW Metal2 ( 332080 234640 ) Via2_VH
+ NEW Metal1 ( 325360 294000 ) Via1_VV
+ NEW Metal1 ( 320880 286160 ) Via1_VV
+ NEW Metal1 ( 323120 288400 ) Via1_HV
+ NEW Metal1 ( 325360 288400 ) Via1_HV
+ NEW Metal2 ( 395920 234640 ) Via2_VH
+ NEW Metal1 ( 395920 239120 ) Via1_HV
+ NEW Metal2 ( 325360 288400 ) RECT ( -280 -1040 280 0 ) ;
+ - _0225_ ( _0776_ I ) ( _0775_ ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 316400 286160 ) ( 317520 * )
+ NEW Metal2 ( 316400 286160 ) ( * 294000 )
+ NEW Metal1 ( 317520 286160 ) Via1_VV
+ NEW Metal1 ( 316400 294000 ) Via1_VV ;
+ - _0226_ ( _0822_ A1 ) ( _0818_ A2 ) ( _0811_ A3 ) ( _0801_ A3 ) ( _0798_ A2 ) ( _0790_ A1 ) ( _0786_ A3 )
+ ( _0777_ ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 302960 334320 ) ( * 347760 )
+ NEW Metal2 ( 304080 347760 ) ( * 355600 )
+ NEW Metal2 ( 302960 347760 ) ( 304080 * )
+ NEW Metal2 ( 309680 357840 ) ( * 372400 )
+ NEW Metal3 ( 304080 357840 ) ( 309680 * )
+ NEW Metal2 ( 304080 355600 ) ( * 357840 )
+ NEW Metal2 ( 338800 343280 ) ( * 357840 )
+ NEW Metal2 ( 325360 360080 ) ( * 363440 )
+ NEW Metal3 ( 325360 360080 ) ( 338800 * )
+ NEW Metal2 ( 338800 357840 ) ( * 360080 )
+ NEW Metal2 ( 322000 363440 ) ( * 380240 )
+ NEW Metal3 ( 309680 363440 ) ( 325360 * )
+ NEW Metal1 ( 302960 347760 ) Via1_HV
+ NEW Metal1 ( 302960 334320 ) Via1_HV
+ NEW Metal1 ( 304080 355600 ) Via1_HV
+ NEW Metal1 ( 309680 372400 ) Via1_VV
+ NEW Metal2 ( 309680 357840 ) Via2_VH
+ NEW Metal2 ( 304080 357840 ) Via2_VH
+ NEW Metal2 ( 309680 363440 ) Via2_VH
+ NEW Metal1 ( 338800 357840 ) Via1_VV
+ NEW Metal1 ( 338800 343280 ) Via1_VV
+ NEW Metal1 ( 325360 363440 ) Via1_VV
+ NEW Metal2 ( 325360 360080 ) Via2_VH
+ NEW Metal2 ( 338800 360080 ) Via2_VH
+ NEW Metal2 ( 325360 363440 ) Via2_VH
+ NEW Metal1 ( 322000 380240 ) Via1_VV
+ NEW Metal2 ( 322000 363440 ) Via2_VH
+ NEW Metal2 ( 309680 363440 ) RECT ( -280 -1040 280 0 )
+ NEW Metal2 ( 325360 363440 ) RECT ( -280 -1040 280 0 )
+ NEW Metal3 ( 322000 363440 ) RECT ( -1040 -280 0 280 ) ;
+ - _0227_ ( _0791_ A2 ) ( _0779_ A2 ) ( _0778_ ZN ) + USE SIGNAL
+ + ROUTED Metal3 ( 297360 310800 ) ( 311920 * )
+ NEW Metal2 ( 298480 310800 ) ( * 316400 )
+ NEW Metal2 ( 297360 310800 ) ( 298480 * )
+ NEW Metal1 ( 297360 310800 ) Via1_VV
+ NEW Metal2 ( 297360 310800 ) Via2_VH
+ NEW Metal1 ( 311920 310800 ) Via1_HV
+ NEW Metal2 ( 311920 310800 ) Via2_VH
+ NEW Metal1 ( 298480 316400 ) Via1_VV
+ NEW Metal2 ( 297360 310800 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 311920 310800 ) RECT ( -280 -660 280 0 ) ;
+ - _0228_ ( _0795_ A2 ) ( _0780_ A2 ) ( _0779_ ZN ) + USE SIGNAL
+ + ROUTED Metal3 ( 281680 356720 ) ( 295120 * )
+ NEW Metal2 ( 279440 364560 ) ( 280560 * )
+ NEW Metal2 ( 280560 356720 ) ( * 364560 )
+ NEW Metal2 ( 280560 356720 ) ( 281680 * )
+ NEW Metal2 ( 295120 317520 ) ( * 356720 )
+ NEW Metal1 ( 295120 317520 ) Via1_VV
+ NEW Metal1 ( 281680 356720 ) Via1_VV
+ NEW Metal2 ( 281680 356720 ) Via2_VH
+ NEW Metal2 ( 295120 356720 ) Via2_VH
+ NEW Metal1 ( 279440 364560 ) Via1_VV
+ NEW Metal2 ( 281680 356720 ) RECT ( -280 -660 280 0 ) ;
+ - _0229_ ( _0808_ A2 ) ( _0785_ A2 ) ( _0780_ ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 285040 372400 ) ( * 394800 )
+ NEW Metal2 ( 281680 394800 ) ( 285040 * )
+ NEW Metal2 ( 285040 358960 ) ( * 372400 )
+ NEW Metal1 ( 285040 372400 ) Via1_HV
+ NEW Metal1 ( 281680 394800 ) Via1_VV
+ NEW Metal1 ( 285040 358960 ) Via1_VV ;
+ - _0230_ ( _0816_ B2 ) ( _0809_ A1 ) ( _0797_ C ) ( _0784_ A1 ) ( _0781_ ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 259280 374640 ) ( * 385840 )
+ NEW Metal3 ( 244720 385840 ) ( 259280 * )
+ NEW Metal2 ( 257040 366800 ) ( 258160 * )
+ NEW Metal2 ( 258160 366800 ) ( * 374640 )
+ NEW Metal2 ( 258160 374640 ) ( 259280 * )
+ NEW Metal3 ( 259280 381360 ) ( 270480 * )
+ NEW Metal2 ( 272720 382480 ) ( * 388080 )
+ NEW Metal2 ( 270480 382480 ) ( 272720 * )
+ NEW Metal2 ( 270480 381360 ) ( * 382480 )
+ NEW Metal1 ( 259280 374640 ) Via1_VV
+ NEW Metal2 ( 259280 385840 ) Via2_VH
+ NEW Metal1 ( 244720 385840 ) Via1_VV
+ NEW Metal2 ( 244720 385840 ) Via2_VH
+ NEW Metal1 ( 257040 366800 ) Via1_VV
+ NEW Metal1 ( 270480 381360 ) Via1_HV
+ NEW Metal2 ( 270480 381360 ) Via2_VH
+ NEW Metal2 ( 259280 381360 ) Via2_VH
+ NEW Metal1 ( 272720 388080 ) Via1_VV
+ NEW Metal2 ( 244720 385840 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 270480 381360 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 259280 381360 ) RECT ( -280 -1040 280 0 ) ;
+ - _0231_ ( _0807_ B1 ) ( _0797_ B1 ) ( _0783_ B1 ) ( _0782_ ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 260400 374640 ) ( * 388080 )
+ NEW Metal2 ( 260400 374640 ) ( 264880 * )
+ NEW Metal3 ( 251440 380240 ) ( 260400 * )
+ NEW Metal2 ( 243600 380240 ) ( * 388080 )
+ NEW Metal3 ( 243600 380240 ) ( 251440 * )
+ NEW Metal1 ( 260400 388080 ) Via1_HV
+ NEW Metal1 ( 264880 374640 ) Via1_VV
+ NEW Metal1 ( 251440 380240 ) Via1_HV
+ NEW Metal2 ( 251440 380240 ) Via2_VH
+ NEW Metal2 ( 260400 380240 ) Via2_VH
+ NEW Metal1 ( 243600 388080 ) Via1_VV
+ NEW Metal2 ( 243600 380240 ) Via2_VH
+ NEW Metal2 ( 251440 380240 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 260400 380240 ) RECT ( -280 -1040 280 0 ) ;
+ - _0232_ ( _0784_ A2 ) ( _0783_ ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 257040 373520 ) ( * 379120 )
+ NEW Metal3 ( 253680 379120 ) ( 257040 * )
+ NEW Metal1 ( 257040 373520 ) Via1_VV
+ NEW Metal2 ( 257040 379120 ) Via2_VH
+ NEW Metal1 ( 253680 379120 ) Via1_VV
+ NEW Metal2 ( 253680 379120 ) Via2_VH
+ NEW Metal2 ( 253680 379120 ) RECT ( -280 -660 280 0 ) ;
+ - _0233_ ( _0785_ B ) ( _0784_ ZN ) + USE SIGNAL
+ + ROUTED Metal3 ( 260400 371280 ) ( 292880 * )
+ NEW Metal1 ( 260400 371280 ) Via1_HV
+ NEW Metal2 ( 260400 371280 ) Via2_VH
+ NEW Metal1 ( 292880 371280 ) Via1_VV
+ NEW Metal2 ( 292880 371280 ) Via2_VH
+ NEW Metal2 ( 260400 371280 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 292880 371280 ) RECT ( -280 -660 280 0 ) ;
+ - _0234_ ( _0822_ A2 ) ( _0790_ A2 ) ( _0785_ ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 291760 361200 ) ( * 371280 )
+ NEW Metal2 ( 336560 357840 ) ( * 361200 )
+ NEW Metal2 ( 336560 343280 ) ( * 357840 )
+ NEW Metal3 ( 291760 361200 ) ( 336560 * )
+ NEW Metal2 ( 291760 361200 ) Via2_VH
+ NEW Metal1 ( 291760 371280 ) Via1_VV
+ NEW Metal1 ( 336560 357840 ) Via1_VV
+ NEW Metal2 ( 336560 361200 ) Via2_VH
+ NEW Metal1 ( 336560 343280 ) Via1_VV ;
+ - _0235_ ( _0823_ A1 ) ( _0790_ B ) ( _0786_ ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 327600 357840 ) ( 329840 * )
+ NEW Metal2 ( 329840 342160 ) ( * 357840 )
+ NEW Metal3 ( 329840 342160 ) ( 339920 * )
+ NEW Metal2 ( 328720 357840 ) ( * 365680 )
+ NEW Metal1 ( 327600 357840 ) Via1_VV
+ NEW Metal2 ( 329840 342160 ) Via2_VH
+ NEW Metal1 ( 339920 342160 ) Via1_VV
+ NEW Metal2 ( 339920 342160 ) Via2_VH
+ NEW Metal1 ( 328720 365680 ) Via1_HV
+ NEW Metal2 ( 339920 342160 ) RECT ( -280 0 280 660 ) ;
+ - _0236_ ( ANTENNA__0789__A1 I ) ( ANTENNA__1260__A2 I ) ( ANTENNA__1264__A2 I ) ( ANTENNA__1269__B I ) ( ANTENNA__1270__A1 I ) ( ANTENNA__1271__A1 I ) ( ANTENNA__1273__A2 I )
+ ( ANTENNA__1278__A3 I ) ( ANTENNA__1279__A2 I ) ( _1279_ A2 ) ( _1278_ A3 ) ( _1273_ A2 ) ( _1271_ A1 ) ( _1270_ A1 ) ( _1269_ B )
+ ( _1264_ A2 ) ( _1260_ A2 ) ( _0789_ A1 ) ( _0787_ Z ) + USE SIGNAL
+ + ROUTED Metal2 ( 407120 374640 ) ( * 386960 )
+ NEW Metal3 ( 407120 386960 ) ( 421680 * )
+ NEW Metal3 ( 407120 358960 ) ( 414960 * )
+ NEW Metal2 ( 407120 358960 ) ( * 374640 )
+ NEW Metal2 ( 398160 356720 ) ( * 358960 )
+ NEW Metal3 ( 398160 358960 ) ( 407120 * )
+ NEW Metal2 ( 399280 403760 ) ( 400400 * )
+ NEW Metal2 ( 399280 386960 ) ( * 403760 )
+ NEW Metal3 ( 399280 386960 ) ( 407120 * )
+ NEW Metal3 ( 384720 395920 ) ( 399280 * )
+ NEW Metal2 ( 382480 374640 ) ( * 375760 )
+ NEW Metal2 ( 382480 375760 ) ( 384720 * )
+ NEW Metal2 ( 384720 375760 ) ( * 395920 )
+ NEW Metal2 ( 374640 357840 ) ( * 358960 )
+ NEW Metal3 ( 374640 358960 ) ( 398160 * )
+ NEW Metal3 ( 367920 389200 ) ( 384720 * )
+ NEW Metal2 ( 367920 389200 ) ( * 393680 )
+ NEW Metal2 ( 374640 350000 ) ( * 357840 )
+ NEW Metal3 ( 374640 343280 ) ( 384720 * )
+ NEW Metal2 ( 374640 343280 ) ( * 350000 )
+ NEW Metal2 ( 357840 343280 ) ( * 346640 )
+ NEW Metal3 ( 357840 343280 ) ( 374640 * )
+ NEW Metal2 ( 357840 360080 ) ( * 363440 )
+ NEW Metal3 ( 357840 360080 ) ( 374640 * )
+ NEW Metal3 ( 374640 358960 ) ( * 360080 )
+ NEW Metal3 ( 357840 389200 ) ( 367920 * )
+ NEW Metal2 ( 352240 360080 ) ( * 362320 )
+ NEW Metal3 ( 352240 360080 ) ( 357840 * )
+ NEW Metal3 ( 352240 389200 ) ( 357840 * )
+ NEW Metal2 ( 350000 350000 ) ( * 360080 )
+ NEW Metal2 ( 350000 360080 ) ( 352240 * )
+ NEW Metal2 ( 346640 358960 ) ( 350000 * )
+ NEW Metal1 ( 407120 374640 ) Via1_VV
+ NEW Metal2 ( 407120 386960 ) Via2_VH
+ NEW Metal1 ( 421680 386960 ) Via1_VV
+ NEW Metal2 ( 421680 386960 ) Via2_VH
+ NEW Metal1 ( 414960 358960 ) Via1_VV
+ NEW Metal2 ( 414960 358960 ) Via2_VH
+ NEW Metal2 ( 407120 358960 ) Via2_VH
+ NEW Metal1 ( 398160 356720 ) Via1_HV
+ NEW Metal2 ( 398160 358960 ) Via2_VH
+ NEW Metal1 ( 400400 403760 ) Via1_VV
+ NEW Metal2 ( 399280 386960 ) Via2_VH
+ NEW Metal1 ( 384720 395920 ) Via1_VV
+ NEW Metal2 ( 384720 395920 ) Via2_VH
+ NEW Metal2 ( 399280 395920 ) Via2_VH
+ NEW Metal1 ( 382480 374640 ) Via1_VV
+ NEW Metal1 ( 374640 357840 ) Via1_VV
+ NEW Metal2 ( 374640 358960 ) Via2_VH
+ NEW Metal1 ( 367920 389200 ) Via1_VV
+ NEW Metal2 ( 367920 389200 ) Via2_VH
+ NEW Metal2 ( 384720 389200 ) Via2_VH
+ NEW Metal1 ( 367920 393680 ) Via1_VV
+ NEW Metal1 ( 374640 350000 ) Via1_VV
+ NEW Metal1 ( 384720 343280 ) Via1_VV
+ NEW Metal2 ( 384720 343280 ) Via2_VH
+ NEW Metal2 ( 374640 343280 ) Via2_VH
+ NEW Metal1 ( 357840 346640 ) Via1_VV
+ NEW Metal2 ( 357840 343280 ) Via2_VH
+ NEW Metal1 ( 357840 363440 ) Via1_VV
+ NEW Metal2 ( 357840 360080 ) Via2_VH
+ NEW Metal1 ( 357840 389200 ) Via1_VV
+ NEW Metal2 ( 357840 389200 ) Via2_VH
+ NEW Metal1 ( 352240 362320 ) Via1_VV
+ NEW Metal2 ( 352240 360080 ) Via2_VH
+ NEW Metal1 ( 352240 389200 ) Via1_VV
+ NEW Metal2 ( 352240 389200 ) Via2_VH
+ NEW Metal1 ( 350000 350000 ) Via1_VV
+ NEW Metal1 ( 346640 358960 ) Via1_VV
+ NEW Metal2 ( 421680 386960 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 414960 358960 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 384720 395920 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 399280 395920 ) RECT ( -280 -1040 280 0 )
+ NEW Metal2 ( 367920 389200 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 384720 389200 ) RECT ( -280 -1040 280 0 )
+ NEW Metal2 ( 384720 343280 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 357840 389200 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 352240 389200 ) RECT ( -280 -660 280 0 ) ;
+ - _0237_ ( _0818_ C1 ) ( _0810_ A3 ) ( _0803_ B ) ( _0789_ A2 ) ( _0788_ ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 316400 343280 ) ( * 348880 )
+ NEW Metal2 ( 315280 343280 ) ( 316400 * )
+ NEW Metal2 ( 314160 357840 ) ( * 358960 )
+ NEW Metal2 ( 320880 348880 ) ( * 358960 )
+ NEW Metal3 ( 320880 348880 ) ( 330960 * )
+ NEW Metal2 ( 329840 372400 ) ( 330960 * )
+ NEW Metal2 ( 330960 348880 ) ( * 372400 )
+ NEW Metal3 ( 330960 357840 ) ( 345520 * )
+ NEW Metal3 ( 316400 348880 ) ( 320880 * )
+ NEW Metal3 ( 314160 358960 ) ( 320880 * )
+ NEW Metal2 ( 316400 348880 ) Via2_VH
+ NEW Metal1 ( 315280 343280 ) Via1_VV
+ NEW Metal2 ( 314160 358960 ) Via2_VH
+ NEW Metal1 ( 314160 357840 ) Via1_VV
+ NEW Metal2 ( 320880 358960 ) Via2_VH
+ NEW Metal2 ( 320880 348880 ) Via2_VH
+ NEW Metal1 ( 330960 348880 ) Via1_HV
+ NEW Metal2 ( 330960 348880 ) Via2_VH
+ NEW Metal1 ( 329840 372400 ) Via1_VV
+ NEW Metal1 ( 345520 357840 ) Via1_VV
+ NEW Metal2 ( 345520 357840 ) Via2_VH
+ NEW Metal2 ( 330960 357840 ) Via2_VH
+ NEW Metal2 ( 330960 348880 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 345520 357840 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 330960 357840 ) RECT ( -280 -1040 280 0 ) ;
+ - _0238_ ( _0823_ A2 ) ( _0790_ C ) ( _0789_ ZN ) + USE SIGNAL
+ + ROUTED Metal3 ( 326480 356720 ) ( 348880 * )
+ NEW Metal2 ( 341040 342160 ) ( * 356720 )
+ NEW Metal1 ( 348880 356720 ) Via1_VV
+ NEW Metal2 ( 348880 356720 ) Via2_VH
+ NEW Metal1 ( 326480 356720 ) Via1_VV
+ NEW Metal2 ( 326480 356720 ) Via2_VH
+ NEW Metal1 ( 341040 342160 ) Via1_HV
+ NEW Metal2 ( 341040 356720 ) Via2_VH
+ NEW Metal2 ( 348880 356720 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 326480 356720 ) RECT ( -280 -660 280 0 )
+ NEW Metal3 ( 341040 356720 ) RECT ( -1040 -280 0 280 ) ;
+ - _0239_ ( _0792_ I1 ) ( _0790_ ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 339920 309680 ) ( 341040 * )
+ NEW Metal2 ( 339920 309680 ) ( * 339920 )
+ NEW Metal1 ( 341040 309680 ) Via1_VV
+ NEW Metal1 ( 339920 339920 ) Via1_HV ;
+ - _0240_ ( _0825_ A1 ) ( _0805_ A2 ) ( _0792_ S ) ( _0791_ ZN ) + USE SIGNAL
+ + ROUTED Metal3 ( 323120 310800 ) ( 343280 * )
+ NEW Metal2 ( 347760 315280 ) ( 348880 * )
+ NEW Metal2 ( 347760 310800 ) ( * 315280 )
+ NEW Metal3 ( 343280 310800 ) ( 347760 * )
+ NEW Metal2 ( 347760 296240 ) ( * 310800 )
+ NEW Metal1 ( 343280 310800 ) Via1_HV
+ NEW Metal2 ( 343280 310800 ) Via2_VH
+ NEW Metal1 ( 323120 310800 ) Via1_VV
+ NEW Metal2 ( 323120 310800 ) Via2_VH
+ NEW Metal1 ( 348880 315280 ) Via1_VV
+ NEW Metal2 ( 347760 310800 ) Via2_VH
+ NEW Metal1 ( 347760 296240 ) Via1_VV
+ NEW Metal2 ( 343280 310800 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 323120 310800 ) RECT ( -280 -660 280 0 ) ;
+ - _0241_ ( _0793_ I ) ( _0792_ Z ) + USE SIGNAL
+ + ROUTED Metal2 ( 337680 294000 ) ( * 307440 )
+ NEW Metal1 ( 337680 294000 ) Via1_HV
+ NEW Metal1 ( 337680 307440 ) Via1_VV ;
+ - _0242_ ( _1262_ A1 ) ( _0805_ A1 ) ( _0794_ ZN ) + USE SIGNAL
+ + ROUTED Metal3 ( 351120 317520 ) ( 375760 * )
+ NEW Metal3 ( 375760 317520 ) ( 385840 * )
+ NEW Metal2 ( 375760 317520 ) ( * 325360 )
+ NEW Metal2 ( 375760 317520 ) Via2_VH
+ NEW Metal1 ( 351120 317520 ) Via1_VV
+ NEW Metal2 ( 351120 317520 ) Via2_VH
+ NEW Metal1 ( 385840 317520 ) Via1_VV
+ NEW Metal2 ( 385840 317520 ) Via2_VH
+ NEW Metal1 ( 375760 325360 ) Via1_HV
+ NEW Metal2 ( 351120 317520 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 385840 317520 ) RECT ( -280 -660 280 0 ) ;
+ - _0243_ ( _0816_ A2 ) ( _0796_ A2 ) ( _0795_ Z ) + USE SIGNAL
+ + ROUTED Metal2 ( 282800 366800 ) ( * 381360 )
+ NEW Metal2 ( 282800 385840 ) ( 283920 * )
+ NEW Metal2 ( 282800 381360 ) ( * 385840 )
+ NEW Metal1 ( 282800 381360 ) Via1_HV
+ NEW Metal1 ( 282800 366800 ) Via1_HV
+ NEW Metal1 ( 283920 385840 ) Via1_VV ;
+ - _0244_ ( _0799_ A1 ) ( _0796_ ZN ) + USE SIGNAL
+ + ROUTED Metal3 ( 287280 380240 ) ( 298480 * )
+ NEW Metal2 ( 287280 380240 ) ( * 385840 )
+ NEW Metal1 ( 298480 380240 ) Via1_VV
+ NEW Metal2 ( 298480 380240 ) Via2_VH
+ NEW Metal2 ( 287280 380240 ) Via2_VH
+ NEW Metal1 ( 287280 385840 ) Via1_VV
+ NEW Metal2 ( 298480 380240 ) RECT ( -280 -660 280 0 ) ;
+ - _0245_ ( _0799_ A2 ) ( _0797_ ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 296240 380240 ) ( * 386960 )
+ NEW Metal3 ( 248080 386960 ) ( 296240 * )
+ NEW Metal1 ( 296240 380240 ) Via1_VV
+ NEW Metal2 ( 296240 386960 ) Via2_VH
+ NEW Metal1 ( 248080 386960 ) Via1_VV
+ NEW Metal2 ( 248080 386960 ) Via2_VH
+ NEW Metal2 ( 248080 386960 ) RECT ( -280 -660 280 0 ) ;
+ - _0246_ ( _0818_ B1 ) ( _0813_ A1 ) ( _0799_ B ) ( _0798_ ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 305200 355600 ) ( * 363440 )
+ NEW Metal3 ( 305200 355600 ) ( 308560 * )
+ NEW Metal2 ( 301840 363440 ) ( * 380240 )
+ NEW Metal2 ( 301840 363440 ) ( 305200 * )
+ NEW Metal2 ( 325360 348880 ) ( * 355600 )
+ NEW Metal2 ( 325360 348880 ) ( 327600 * )
+ NEW Metal3 ( 308560 355600 ) ( 325360 * )
+ NEW Metal1 ( 308560 355600 ) Via1_VV
+ NEW Metal2 ( 308560 355600 ) Via2_VH
+ NEW Metal1 ( 305200 363440 ) Via1_HV
+ NEW Metal2 ( 305200 355600 ) Via2_VH
+ NEW Metal1 ( 301840 380240 ) Via1_HV
+ NEW Metal2 ( 325360 355600 ) Via2_VH
+ NEW Metal1 ( 327600 348880 ) Via1_HV
+ NEW Metal2 ( 308560 355600 ) RECT ( -280 -660 280 0 ) ;
+ - _0247_ ( _0804_ A1 ) ( _0799_ ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 297360 375760 ) ( * 378000 )
+ NEW Metal3 ( 323120 375760 ) ( * 379120 )
+ NEW Metal3 ( 323120 379120 ) ( 341040 * )
+ NEW Metal2 ( 341040 374640 ) ( * 379120 )
+ NEW Metal3 ( 297360 375760 ) ( 323120 * )
+ NEW Metal2 ( 297360 375760 ) Via2_VH
+ NEW Metal1 ( 297360 378000 ) Via1_VV
+ NEW Metal2 ( 341040 379120 ) Via2_VH
+ NEW Metal1 ( 341040 374640 ) Via1_VV ;
+ - _0248_ ( _1289_ A1 ) ( _0801_ A1 ) ( _0800_ ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 328720 406000 ) ( 329840 * )
+ NEW Metal2 ( 329840 384720 ) ( * 406000 )
+ NEW Metal2 ( 327600 384720 ) ( 329840 * )
+ NEW Metal2 ( 327600 379120 ) ( * 384720 )
+ NEW Metal2 ( 329840 406000 ) ( * 411600 )
+ NEW Metal1 ( 328720 406000 ) Via1_VV
+ NEW Metal1 ( 327600 379120 ) Via1_VV
+ NEW Metal1 ( 329840 411600 ) Via1_VV ;
+ - _0249_ ( _0804_ A2 ) ( _0801_ ZN ) + USE SIGNAL
+ + ROUTED Metal3 ( 328720 374640 ) ( 338800 * )
+ NEW Metal2 ( 328720 374640 ) ( * 378000 )
+ NEW Metal1 ( 338800 374640 ) Via1_VV
+ NEW Metal2 ( 338800 374640 ) Via2_VH
+ NEW Metal2 ( 328720 374640 ) Via2_VH
+ NEW Metal1 ( 328720 378000 ) Via1_VV
+ NEW Metal2 ( 338800 374640 ) RECT ( -280 -660 280 0 ) ;
+ - _0250_ ( _1275_ A1 ) ( _0803_ A1 ) ( _0802_ ZN ) + USE SIGNAL
+ + ROUTED Metal3 ( 325360 373520 ) ( 354480 * )
+ NEW Metal3 ( 354480 373520 ) ( 362320 * )
+ NEW Metal1 ( 354480 373520 ) Via1_VV
+ NEW Metal2 ( 354480 373520 ) Via2_VH
+ NEW Metal1 ( 325360 373520 ) Via1_VV
+ NEW Metal2 ( 325360 373520 ) Via2_VH
+ NEW Metal1 ( 362320 373520 ) Via1_VV
+ NEW Metal2 ( 362320 373520 ) Via2_VH
+ NEW Metal2 ( 354480 373520 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 325360 373520 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 362320 373520 ) RECT ( -280 -660 280 0 ) ;
+ - _0251_ ( _0804_ A3 ) ( _0803_ ZN ) + USE SIGNAL
+ + ROUTED Metal3 ( 324240 372400 ) ( 335440 * )
+ NEW Metal1 ( 335440 372400 ) Via1_VV
+ NEW Metal2 ( 335440 372400 ) Via2_VH
+ NEW Metal1 ( 324240 372400 ) Via1_VV
+ NEW Metal2 ( 324240 372400 ) Via2_VH
+ NEW Metal2 ( 335440 372400 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 324240 372400 ) RECT ( -280 -660 280 0 ) ;
+ - _0252_ ( _0831_ A1 ) ( _0805_ B ) ( _0804_ ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 355600 317520 ) ( 356720 * )
+ NEW Metal2 ( 356720 311920 ) ( * 317520 )
+ NEW Metal2 ( 356720 348880 ) ( 357840 * )
+ NEW Metal2 ( 357840 348880 ) ( * 357840 )
+ NEW Metal2 ( 356720 357840 ) ( 357840 * )
+ NEW Metal2 ( 356720 357840 ) ( * 370160 )
+ NEW Metal3 ( 342160 370160 ) ( 356720 * )
+ NEW Metal2 ( 356720 317520 ) ( * 348880 )
+ NEW Metal1 ( 355600 317520 ) Via1_VV
+ NEW Metal1 ( 356720 311920 ) Via1_VV
+ NEW Metal2 ( 356720 370160 ) Via2_VH
+ NEW Metal1 ( 342160 370160 ) Via1_VV
+ NEW Metal2 ( 342160 370160 ) Via2_VH
+ NEW Metal2 ( 342160 370160 ) RECT ( -280 -660 280 0 ) ;
+ - _0253_ ( _0806_ I ) ( _0805_ ZN ) + USE SIGNAL
+ + ROUTED Metal3 ( 350000 310800 ) ( 364560 * )
+ NEW Metal2 ( 350000 310800 ) ( * 315280 )
+ NEW Metal1 ( 364560 310800 ) Via1_VV
+ NEW Metal2 ( 364560 310800 ) Via2_VH
+ NEW Metal2 ( 350000 310800 ) Via2_VH
+ NEW Metal1 ( 350000 315280 ) Via1_VV
+ NEW Metal2 ( 364560 310800 ) RECT ( -280 -660 280 0 ) ;
+ - _0254_ ( _0809_ A2 ) ( _0807_ ZN ) + USE SIGNAL
+ + ROUTED Metal3 ( 262640 388080 ) ( 270480 * )
+ NEW Metal1 ( 262640 388080 ) Via1_VV
+ NEW Metal2 ( 262640 388080 ) Via2_VH
+ NEW Metal1 ( 270480 388080 ) Via1_VV
+ NEW Metal2 ( 270480 388080 ) Via2_VH
+ NEW Metal2 ( 262640 388080 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 270480 388080 ) RECT ( -280 -660 280 0 ) ;
+ - _0255_ ( _0809_ B ) ( _0808_ ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 277200 388080 ) ( 278320 * )
+ NEW Metal2 ( 278320 388080 ) ( * 393680 )
+ NEW Metal1 ( 277200 388080 ) Via1_VV
+ NEW Metal1 ( 278320 393680 ) Via1_VV ;
+ - _0256_ ( _0813_ A2 ) ( _0809_ ZN ) + USE SIGNAL
+ + ROUTED Metal3 ( 271600 389200 ) ( 306320 * )
+ NEW Metal2 ( 306320 364560 ) ( * 389200 )
+ NEW Metal1 ( 271600 389200 ) Via1_VV
+ NEW Metal2 ( 271600 389200 ) Via2_VH
+ NEW Metal2 ( 306320 389200 ) Via2_VH
+ NEW Metal1 ( 306320 364560 ) Via1_HV
+ NEW Metal2 ( 271600 389200 ) RECT ( -280 -660 280 0 ) ;
+ - _0257_ ( _0812_ A1 ) ( _0810_ ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 310800 369040 ) ( * 378000 )
+ NEW Metal3 ( 310800 369040 ) ( 315280 * )
+ NEW Metal2 ( 315280 355600 ) ( * 369040 )
+ NEW Metal1 ( 310800 378000 ) Via1_VV
+ NEW Metal2 ( 310800 369040 ) Via2_VH
+ NEW Metal2 ( 315280 369040 ) Via2_VH
+ NEW Metal1 ( 315280 355600 ) Via1_VV ;
+ - _0258_ ( _0812_ A2 ) ( _0811_ ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 309680 380240 ) ( 311920 * )
+ NEW Metal2 ( 311920 371280 ) ( * 380240 )
+ NEW Metal1 ( 309680 380240 ) Via1_VV
+ NEW Metal1 ( 311920 371280 ) Via1_VV ;
+ - _0259_ ( _0813_ B ) ( _0812_ ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 313040 364560 ) ( 314160 * )
+ NEW Metal2 ( 314160 364560 ) ( * 378000 )
+ NEW Metal2 ( 313040 378000 ) ( 314160 * )
+ NEW Metal1 ( 313040 364560 ) Via1_HV
+ NEW Metal1 ( 313040 378000 ) Via1_VV ;
+ - _0260_ ( ANTENNA__0819__A1 I ) ( ANTENNA__0826__A2 I ) ( ANTENNA__0829__B I ) ( ANTENNA__0869__A1 I ) ( _0869_ A1 ) ( _0829_ B ) ( _0826_ A2 )
+ ( _0819_ A1 ) ( _0813_ ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 313040 341040 ) ( 317520 * )
+ NEW Metal2 ( 313040 341040 ) ( * 362320 )
+ NEW Metal2 ( 311920 362320 ) ( 313040 * )
+ NEW Metal2 ( 317520 291760 ) ( * 341040 )
+ NEW Metal2 ( 351120 287280 ) ( * 291760 )
+ NEW Metal3 ( 351120 291760 ) ( 361200 * )
+ NEW Metal2 ( 361200 286160 ) ( * 291760 )
+ NEW Metal2 ( 358960 280560 ) ( * 291760 )
+ NEW Metal3 ( 361200 286160 ) ( 367920 * )
+ NEW Metal2 ( 360080 299600 ) ( 361200 * )
+ NEW Metal2 ( 361200 291760 ) ( * 299600 )
+ NEW Metal2 ( 384720 291760 ) ( * 295120 )
+ NEW Metal3 ( 361200 291760 ) ( 384720 * )
+ NEW Metal2 ( 395920 291760 ) ( * 292880 )
+ NEW Metal3 ( 384720 291760 ) ( 395920 * )
+ NEW Metal3 ( 317520 291760 ) ( 351120 * )
+ NEW Metal2 ( 317520 291760 ) Via2_VH
+ NEW Metal1 ( 311920 362320 ) Via1_HV
+ NEW Metal1 ( 351120 287280 ) Via1_VV
+ NEW Metal2 ( 351120 291760 ) Via2_VH
+ NEW Metal1 ( 361200 291760 ) Via1_HV
+ NEW Metal2 ( 361200 291760 ) Via2_VH
+ NEW Metal1 ( 361200 286160 ) Via1_VV
+ NEW Metal1 ( 358960 280560 ) Via1_VV
+ NEW Metal2 ( 358960 291760 ) Via2_VH
+ NEW Metal1 ( 367920 286160 ) Via1_VV
+ NEW Metal2 ( 367920 286160 ) Via2_VH
+ NEW Metal2 ( 361200 286160 ) Via2_VH
+ NEW Metal1 ( 360080 299600 ) Via1_VV
+ NEW Metal1 ( 384720 295120 ) Via1_VV
+ NEW Metal2 ( 384720 291760 ) Via2_VH
+ NEW Metal1 ( 395920 292880 ) Via1_VV
+ NEW Metal2 ( 395920 291760 ) Via2_VH
+ NEW Metal2 ( 361200 291760 ) RECT ( -280 -660 280 0 )
+ NEW Metal3 ( 358960 291760 ) RECT ( -1040 -280 0 280 )
+ NEW Metal2 ( 367920 286160 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 361200 286160 ) RECT ( -280 -1040 280 0 ) ;
+ - _0261_ ( _1337_ A1 ) ( _0815_ A1 ) ( _0814_ ZN ) + USE SIGNAL
+ + ROUTED Metal3 ( 203280 382480 ) ( 258160 * )
+ NEW Metal2 ( 258160 382480 ) ( * 395920 )
+ NEW Metal2 ( 258160 395920 ) ( 261520 * )
+ NEW Metal2 ( 193200 380240 ) ( * 382480 )
+ NEW Metal3 ( 193200 382480 ) ( 203280 * )
+ NEW Metal1 ( 203280 382480 ) Via1_VV
+ NEW Metal2 ( 203280 382480 ) Via2_VH
+ NEW Metal2 ( 258160 382480 ) Via2_VH
+ NEW Metal1 ( 261520 395920 ) Via1_HV
+ NEW Metal1 ( 193200 380240 ) Via1_VV
+ NEW Metal2 ( 193200 382480 ) Via2_VH
+ NEW Metal2 ( 203280 382480 ) RECT ( -280 -660 280 0 ) ;
+ - _0262_ ( _0816_ B1 ) ( _0815_ ZN ) + USE SIGNAL
+ + ROUTED Metal3 ( 264880 380240 ) ( 271600 * )
+ NEW Metal2 ( 264880 380240 ) ( * 390320 )
+ NEW Metal2 ( 263760 390320 ) ( 264880 * )
+ NEW Metal2 ( 263760 390320 ) ( * 393680 )
+ NEW Metal1 ( 271600 380240 ) Via1_HV
+ NEW Metal2 ( 271600 380240 ) Via2_VH
+ NEW Metal2 ( 264880 380240 ) Via2_VH
+ NEW Metal1 ( 263760 393680 ) Via1_VV
+ NEW Metal2 ( 271600 380240 ) RECT ( -280 -660 280 0 ) ;
+ - _0263_ ( _0818_ B2 ) ( _0816_ ZN ) + USE SIGNAL
+ + ROUTED Metal4 ( 318640 350000 ) ( * 352240 )
+ NEW Metal3 ( 283920 350000 ) ( 318640 * )
+ NEW Metal2 ( 283920 350000 ) ( * 379120 )
+ NEW Metal2 ( 319760 348880 ) ( * 352240 )
+ NEW Metal3 ( 318640 352240 ) ( 319760 * )
+ NEW Metal3 ( 318640 352240 ) Via3_HV
+ NEW Metal3 ( 318640 350000 ) Via3_HV
+ NEW Metal2 ( 283920 350000 ) Via2_VH
+ NEW Metal1 ( 283920 379120 ) Via1_HV
+ NEW Metal2 ( 319760 352240 ) Via2_VH
+ NEW Metal1 ( 319760 348880 ) Via1_HV ;
+ - _0264_ ( _1281_ A1 ) ( _1261_ A1 ) ( _0818_ C2 ) ( _0817_ ZN ) + USE SIGNAL
+ + ROUTED Metal3 ( 365680 342160 ) ( 375760 * )
+ NEW Metal2 ( 375760 335440 ) ( * 342160 )
+ NEW Metal2 ( 354480 354480 ) ( * 356720 )
+ NEW Metal2 ( 351120 354480 ) ( 354480 * )
+ NEW Metal2 ( 351120 342160 ) ( * 354480 )
+ NEW Metal3 ( 351120 342160 ) ( 365680 * )
+ NEW Metal3 ( 345520 348880 ) ( 351120 * )
+ NEW Metal1 ( 365680 342160 ) Via1_VV
+ NEW Metal2 ( 365680 342160 ) Via2_VH
+ NEW Metal2 ( 375760 342160 ) Via2_VH
+ NEW Metal1 ( 375760 335440 ) Via1_VV
+ NEW Metal1 ( 354480 356720 ) Via1_VV
+ NEW Metal2 ( 351120 342160 ) Via2_VH
+ NEW Metal1 ( 345520 348880 ) Via1_HV
+ NEW Metal2 ( 345520 348880 ) Via2_VH
+ NEW Metal2 ( 351120 348880 ) Via2_VH
+ NEW Metal2 ( 365680 342160 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 345520 348880 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 351120 348880 ) RECT ( -280 -1040 280 0 ) ;
+ - _0265_ ( ANTENNA__0819__A2 I ) ( ANTENNA__0825__A2 I ) ( ANTENNA__0829__C I ) ( ANTENNA__0830__I I ) ( _0830_ I ) ( _0829_ C ) ( _0825_ A2 )
+ ( _0819_ A2 ) ( _0818_ ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 315280 345520 ) ( * 346640 )
+ NEW Metal2 ( 345520 295120 ) ( 346640 * )
+ NEW Metal2 ( 353360 291760 ) ( * 292880 )
+ NEW Metal2 ( 353360 291760 ) ( 355600 * )
+ NEW Metal2 ( 355600 280560 ) ( * 291760 )
+ NEW Metal2 ( 354480 280560 ) ( 355600 * )
+ NEW Metal2 ( 357840 294000 ) ( 358960 * )
+ NEW Metal2 ( 357840 291760 ) ( * 294000 )
+ NEW Metal1 ( 355600 291760 ) ( 357840 * )
+ NEW Metal2 ( 361200 316400 ) ( 362320 * )
+ NEW Metal2 ( 362320 299600 ) ( * 316400 )
+ NEW Metal3 ( 357840 299600 ) ( 362320 * )
+ NEW Metal2 ( 357840 294000 ) ( * 299600 )
+ NEW Metal2 ( 362320 315280 ) ( 365680 * )
+ NEW Metal2 ( 386960 295120 ) ( * 298480 )
+ NEW Metal3 ( 362320 298480 ) ( 386960 * )
+ NEW Metal3 ( 362320 298480 ) ( * 299600 )
+ NEW Metal2 ( 391440 296240 ) ( * 298480 )
+ NEW Metal3 ( 386960 298480 ) ( 391440 * )
+ NEW Metal3 ( 345520 338800 ) ( 362320 * )
+ NEW Metal3 ( 315280 345520 ) ( 345520 * )
+ NEW Metal2 ( 345520 295120 ) ( * 345520 )
+ NEW Metal2 ( 362320 316400 ) ( * 338800 )
+ NEW Metal2 ( 315280 345520 ) Via2_VH
+ NEW Metal1 ( 315280 346640 ) Via1_HV
+ NEW Metal1 ( 346640 295120 ) Via1_VV
+ NEW Metal1 ( 353360 292880 ) Via1_VV
+ NEW Metal1 ( 354480 280560 ) Via1_VV
+ NEW Metal1 ( 358960 294000 ) Via1_HV
+ NEW Metal1 ( 357840 291760 ) Via1_HV
+ NEW Metal1 ( 355600 291760 ) Via1_HV
+ NEW Metal1 ( 361200 316400 ) Via1_VV
+ NEW Metal2 ( 362320 299600 ) Via2_VH
+ NEW Metal2 ( 357840 299600 ) Via2_VH
+ NEW Metal1 ( 365680 315280 ) Via1_VV
+ NEW Metal1 ( 386960 295120 ) Via1_VV
+ NEW Metal2 ( 386960 298480 ) Via2_VH
+ NEW Metal1 ( 391440 296240 ) Via1_VV
+ NEW Metal2 ( 391440 298480 ) Via2_VH
+ NEW Metal2 ( 345520 345520 ) Via2_VH
+ NEW Metal2 ( 362320 338800 ) Via2_VH
+ NEW Metal2 ( 345520 338800 ) Via2_VH
+ NEW Metal2 ( 355600 291760 ) RECT ( -280 -1040 280 0 )
+ NEW Metal2 ( 345520 338800 ) RECT ( -280 -1040 280 0 ) ;
+ - _0266_ ( _0820_ A2 ) ( _0819_ ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 383600 287280 ) ( * 291760 )
+ NEW Metal1 ( 383600 291760 ) Via1_VV
+ NEW Metal1 ( 383600 287280 ) Via1_HV ;
+ - _0267_ ( _0821_ I ) ( _0820_ Z ) + USE SIGNAL
+ + ROUTED Metal2 ( 385840 207760 ) ( * 231280 )
+ NEW Metal2 ( 382480 231280 ) ( 385840 * )
+ NEW Metal2 ( 382480 231280 ) ( * 250320 )
+ NEW Metal2 ( 382480 250320 ) ( 384720 * )
+ NEW Metal2 ( 384720 250320 ) ( * 283920 )
+ NEW Metal2 ( 384720 283920 ) ( 386960 * )
+ NEW Metal2 ( 386960 283920 ) ( * 285040 )
+ NEW Metal1 ( 385840 207760 ) Via1_VV
+ NEW Metal1 ( 386960 285040 ) Via1_VV ;
+ - _0268_ ( _0824_ A1 ) ( _0822_ ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 337680 353360 ) ( * 355600 )
+ NEW Metal3 ( 324240 353360 ) ( 337680 * )
+ NEW Metal2 ( 324240 341040 ) ( * 353360 )
+ NEW Metal2 ( 324240 341040 ) ( 325360 * )
+ NEW Metal1 ( 337680 355600 ) Via1_VV
+ NEW Metal2 ( 337680 353360 ) Via2_VH
+ NEW Metal2 ( 324240 353360 ) Via2_VH
+ NEW Metal1 ( 325360 341040 ) Via1_HV ;
+ - _0269_ ( _0824_ A2 ) ( _0823_ ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 328720 342160 ) ( * 354480 )
+ NEW Metal2 ( 327600 354480 ) ( 328720 * )
+ NEW Metal1 ( 328720 342160 ) Via1_VV
+ NEW Metal1 ( 327600 354480 ) Via1_VV ;
+ - _0270_ ( _0826_ A1 ) ( _0824_ ZN ) + USE SIGNAL
+ + ROUTED Metal3 ( 327600 339920 ) ( 357840 * )
+ NEW Metal2 ( 357840 301840 ) ( * 339920 )
+ NEW Metal1 ( 357840 301840 ) Via1_VV
+ NEW Metal2 ( 357840 339920 ) Via2_VH
+ NEW Metal1 ( 327600 339920 ) Via1_VV
+ NEW Metal2 ( 327600 339920 ) Via2_VH
+ NEW Metal2 ( 327600 339920 ) RECT ( -280 -660 280 0 ) ;
+ - _0271_ ( _0869_ B ) ( _0826_ B ) ( _0825_ ZN ) + USE SIGNAL
+ + ROUTED Metal3 ( 350000 294000 ) ( 356720 * )
+ NEW Metal2 ( 356720 286160 ) ( * 294000 )
+ NEW Metal2 ( 355600 299600 ) ( 356720 * )
+ NEW Metal2 ( 356720 294000 ) ( * 299600 )
+ NEW Metal1 ( 350000 294000 ) Via1_VV
+ NEW Metal2 ( 350000 294000 ) Via2_VH
+ NEW Metal2 ( 356720 294000 ) Via2_VH
+ NEW Metal1 ( 356720 286160 ) Via1_VV
+ NEW Metal1 ( 355600 299600 ) Via1_VV
+ NEW Metal2 ( 350000 294000 ) RECT ( -280 -660 280 0 ) ;
+ - _0272_ ( _0827_ A2 ) ( _0826_ ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 360080 255920 ) ( * 296240 )
+ NEW Metal2 ( 358960 296240 ) ( 360080 * )
+ NEW Metal2 ( 358960 296240 ) ( * 299600 )
+ NEW Metal1 ( 360080 255920 ) Via1_HV
+ NEW Metal1 ( 358960 299600 ) Via1_VV ;
+ - _0273_ ( _0828_ I ) ( _0827_ Z ) + USE SIGNAL
+ + ROUTED Metal3 ( 367920 248080 ) ( 380240 * )
+ NEW Metal2 ( 367920 248080 ) ( * 253680 )
+ NEW Metal1 ( 380240 248080 ) Via1_VV
+ NEW Metal2 ( 380240 248080 ) Via2_VH
+ NEW Metal2 ( 367920 248080 ) Via2_VH
+ NEW Metal1 ( 367920 253680 ) Via1_VV
+ NEW Metal2 ( 380240 248080 ) RECT ( -280 -660 280 0 ) ;
+ - _0274_ ( _0832_ A1 ) ( _0829_ ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 362320 295120 ) ( * 296240 )
+ NEW Metal3 ( 362320 295120 ) ( 372400 * )
+ NEW Metal1 ( 362320 296240 ) Via1_HV
+ NEW Metal2 ( 362320 295120 ) Via2_VH
+ NEW Metal1 ( 372400 295120 ) Via1_VV
+ NEW Metal2 ( 372400 295120 ) Via2_VH
+ NEW Metal2 ( 372400 295120 ) RECT ( -280 -660 280 0 ) ;
+ - _0275_ ( _0831_ A2 ) ( _0830_ ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 358960 310800 ) ( 360080 * )
+ NEW Metal2 ( 360080 310800 ) ( * 315280 )
+ NEW Metal1 ( 358960 310800 ) Via1_VV
+ NEW Metal1 ( 360080 315280 ) Via1_VV ;
+ - _0276_ ( _0832_ A2 ) ( _0831_ ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 374640 294000 ) ( * 297360 )
+ NEW Metal3 ( 354480 297360 ) ( 374640 * )
+ NEW Metal2 ( 354480 297360 ) ( * 301840 )
+ NEW Metal2 ( 354480 301840 ) ( 355600 * )
+ NEW Metal2 ( 355600 301840 ) ( * 307440 )
+ NEW Metal1 ( 374640 294000 ) Via1_VV
+ NEW Metal2 ( 374640 297360 ) Via2_VH
+ NEW Metal2 ( 354480 297360 ) Via2_VH
+ NEW Metal1 ( 355600 307440 ) Via1_VV ;
+ - _0277_ ( _0833_ I ) ( _0832_ Z ) + USE SIGNAL
+ + ROUTED Metal2 ( 382480 279440 ) ( * 291760 )
+ NEW Metal2 ( 378000 291760 ) ( 382480 * )
+ NEW Metal1 ( 382480 279440 ) Via1_VV
+ NEW Metal1 ( 378000 291760 ) Via1_VV ;
+ - _0278_ ( _1029_ A2 ) ( _1026_ A2 ) ( _0904_ A1 ) ( _0844_ A1 ) ( _0834_ ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 245840 214480 ) ( * 215600 )
+ NEW Metal3 ( 236880 214480 ) ( 245840 * )
+ NEW Metal2 ( 236880 201040 ) ( * 214480 )
+ NEW Metal3 ( 210000 207760 ) ( 236880 * )
+ NEW Metal2 ( 203280 217840 ) ( 206640 * )
+ NEW Metal2 ( 203280 207760 ) ( * 217840 )
+ NEW Metal3 ( 203280 207760 ) ( 210000 * )
+ NEW Metal2 ( 226800 236880 ) ( * 237440 )
+ NEW Metal3 ( 226800 236880 ) ( 238000 * )
+ NEW Metal2 ( 238000 224560 ) ( * 236880 )
+ NEW Metal2 ( 236880 224560 ) ( 238000 * )
+ NEW Metal2 ( 236880 214480 ) ( * 224560 )
+ NEW Metal1 ( 245840 215600 ) Via1_VV
+ NEW Metal2 ( 245840 214480 ) Via2_VH
+ NEW Metal2 ( 236880 214480 ) Via2_VH
+ NEW Metal1 ( 236880 201040 ) Via1_HV
+ NEW Metal1 ( 210000 207760 ) Via1_VV
+ NEW Metal2 ( 210000 207760 ) Via2_VH
+ NEW Metal2 ( 236880 207760 ) Via2_VH
+ NEW Metal1 ( 206640 217840 ) Via1_VV
+ NEW Metal2 ( 203280 207760 ) Via2_VH
+ NEW Metal1 ( 226800 237440 ) Via1_VV
+ NEW Metal2 ( 226800 236880 ) Via2_VH
+ NEW Metal2 ( 238000 236880 ) Via2_VH
+ NEW Metal2 ( 210000 207760 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 236880 207760 ) RECT ( -280 -1040 280 0 ) ;
+ - _0279_ ( _0859_ C ) ( _0844_ A2 ) ( _0835_ ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 222320 210000 ) ( 223440 * )
+ NEW Metal2 ( 223440 210000 ) ( * 246960 )
+ NEW Metal2 ( 222320 246960 ) ( 223440 * )
+ NEW Metal3 ( 223440 199920 ) ( 235760 * )
+ NEW Metal2 ( 223440 199920 ) ( * 210000 )
+ NEW Metal1 ( 222320 210000 ) Via1_VV
+ NEW Metal1 ( 222320 246960 ) Via1_HV
+ NEW Metal1 ( 235760 199920 ) Via1_HV
+ NEW Metal2 ( 235760 199920 ) Via2_VH
+ NEW Metal2 ( 223440 199920 ) Via2_VH
+ NEW Metal2 ( 235760 199920 ) RECT ( -280 -660 280 0 ) ;
+ - _0280_ ( _1074_ B2 ) ( _0863_ B2 ) ( _0838_ A1 ) ( _0836_ ZN ) + USE SIGNAL
+ + ROUTED Metal3 ( 298480 119280 ) ( 317520 * )
+ NEW Metal2 ( 317520 119280 ) ( * 122640 )
+ NEW Metal2 ( 305200 113680 ) ( * 119280 )
+ NEW Metal2 ( 291760 119280 ) ( * 121520 )
+ NEW Metal3 ( 291760 119280 ) ( 298480 * )
+ NEW Metal1 ( 298480 119280 ) Via1_VV
+ NEW Metal2 ( 298480 119280 ) Via2_VH
+ NEW Metal2 ( 317520 119280 ) Via2_VH
+ NEW Metal1 ( 317520 122640 ) Via1_VV
+ NEW Metal1 ( 305200 113680 ) Via1_VV
+ NEW Metal2 ( 305200 119280 ) Via2_VH
+ NEW Metal1 ( 291760 121520 ) Via1_VV
+ NEW Metal2 ( 291760 119280 ) Via2_VH
+ NEW Metal2 ( 298480 119280 ) RECT ( -280 -660 280 0 )
+ NEW Metal3 ( 305200 119280 ) RECT ( -1040 -280 0 280 ) ;
+ - _0281_ ( _1071_ B2 ) ( _1070_ A1 ) ( _0838_ A2 ) ( _0837_ ZN ) + USE SIGNAL
+ + ROUTED Metal3 ( 299600 115920 ) ( 316400 * )
+ NEW Metal2 ( 316400 115920 ) ( * 121520 )
+ NEW Metal2 ( 299600 108080 ) ( * 115920 )
+ NEW Metal2 ( 314160 96880 ) ( * 115920 )
+ NEW Metal1 ( 299600 115920 ) Via1_VV
+ NEW Metal2 ( 299600 115920 ) Via2_VH
+ NEW Metal2 ( 316400 115920 ) Via2_VH
+ NEW Metal1 ( 316400 121520 ) Via1_VV
+ NEW Metal1 ( 299600 108080 ) Via1_VV
+ NEW Metal1 ( 314160 96880 ) Via1_HV
+ NEW Metal2 ( 314160 115920 ) Via2_VH
+ NEW Metal2 ( 299600 115920 ) RECT ( -280 -660 280 0 )
+ NEW Metal3 ( 314160 115920 ) RECT ( -1040 -280 0 280 ) ;
+ - _0282_ ( _1045_ A2 ) ( _1043_ A1 ) ( _0839_ A2 ) ( _0838_ ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 317520 133840 ) ( * 134960 )
+ NEW Metal2 ( 322000 129360 ) ( * 134960 )
+ NEW Metal2 ( 322000 134960 ) ( 325360 * )
+ NEW Metal2 ( 319760 123760 ) ( 320880 * )
+ NEW Metal2 ( 320880 123760 ) ( * 129360 )
+ NEW Metal2 ( 320880 129360 ) ( 322000 * )
+ NEW Metal3 ( 317520 133840 ) ( 322000 * )
+ NEW Metal2 ( 317520 133840 ) Via2_VH
+ NEW Metal1 ( 317520 134960 ) Via1_VV
+ NEW Metal1 ( 322000 129360 ) Via1_VV
+ NEW Metal1 ( 325360 134960 ) Via1_VV
+ NEW Metal2 ( 322000 133840 ) Via2_VH
+ NEW Metal1 ( 319760 123760 ) Via1_VV
+ NEW Metal2 ( 322000 133840 ) RECT ( -280 -1040 280 0 ) ;
+ - _0283_ ( _1047_ A2 ) ( _1046_ A2 ) ( _0840_ A2 ) ( _0839_ Z ) + USE SIGNAL
+ + ROUTED Metal2 ( 313040 145040 ) ( * 150640 )
+ NEW Metal2 ( 313040 139440 ) ( 314160 * )
+ NEW Metal2 ( 313040 139440 ) ( * 145040 )
+ NEW Metal2 ( 320880 147280 ) ( * 148400 )
+ NEW Metal2 ( 320880 148400 ) ( 325360 * )
+ NEW Metal2 ( 325360 148400 ) ( * 150640 )
+ NEW Metal2 ( 320880 148400 ) ( * 150640 )
+ NEW Metal3 ( 313040 150640 ) ( 320880 * )
+ NEW Metal1 ( 313040 145040 ) Via1_VV
+ NEW Metal2 ( 313040 150640 ) Via2_VH
+ NEW Metal1 ( 314160 139440 ) Via1_HV
+ NEW Metal1 ( 320880 147280 ) Via1_VV
+ NEW Metal1 ( 325360 150640 ) Via1_VV
+ NEW Metal2 ( 320880 150640 ) Via2_VH ;
+ - _0284_ ( _1049_ A2 ) ( _1048_ A1 ) ( _0841_ A2 ) ( _0840_ Z ) + USE SIGNAL
+ + ROUTED Metal2 ( 324240 141680 ) ( * 142800 )
+ NEW Metal3 ( 324240 141680 ) ( 339920 * )
+ NEW Metal2 ( 339920 138320 ) ( * 141680 )
+ NEW Metal2 ( 332080 141680 ) ( * 159600 )
+ NEW Metal2 ( 319760 160720 ) ( 320880 * )
+ NEW Metal2 ( 319760 141680 ) ( * 160720 )
+ NEW Metal3 ( 319760 141680 ) ( 324240 * )
+ NEW Metal1 ( 324240 142800 ) Via1_HV
+ NEW Metal2 ( 324240 141680 ) Via2_VH
+ NEW Metal2 ( 339920 141680 ) Via2_VH
+ NEW Metal1 ( 339920 138320 ) Via1_VV
+ NEW Metal1 ( 332080 159600 ) Via1_VV
+ NEW Metal2 ( 332080 141680 ) Via2_VH
+ NEW Metal1 ( 320880 160720 ) Via1_VV
+ NEW Metal2 ( 319760 141680 ) Via2_VH
+ NEW Metal3 ( 332080 141680 ) RECT ( -1040 -280 0 280 ) ;
+ - _0285_ ( _1051_ A2 ) ( _1050_ A1 ) ( _0842_ A2 ) ( _0841_ Z ) + USE SIGNAL
+ + ROUTED Metal2 ( 319760 176400 ) ( * 182000 )
+ NEW Metal2 ( 325360 169680 ) ( * 170800 )
+ NEW Metal2 ( 322000 170800 ) ( 325360 * )
+ NEW Metal2 ( 322000 170800 ) ( * 176400 )
+ NEW Metal2 ( 319760 176400 ) ( 322000 * )
+ NEW Metal2 ( 324240 162960 ) ( * 170800 )
+ NEW Metal1 ( 319760 176400 ) Via1_VV
+ NEW Metal1 ( 319760 182000 ) Via1_VV
+ NEW Metal1 ( 325360 169680 ) Via1_VV
+ NEW Metal1 ( 324240 162960 ) Via1_VV ;
+ - _0286_ ( _1053_ A2 ) ( _1052_ A1 ) ( _0843_ A2 ) ( _0842_ Z ) + USE SIGNAL
+ + ROUTED Metal2 ( 320880 193200 ) ( * 199920 )
+ NEW Metal2 ( 320880 186480 ) ( 323120 * )
+ NEW Metal2 ( 320880 186480 ) ( * 193200 )
+ NEW Metal3 ( 320880 190960 ) ( 337680 * )
+ NEW Metal1 ( 320880 193200 ) Via1_HV
+ NEW Metal1 ( 320880 199920 ) Via1_VV
+ NEW Metal1 ( 323120 186480 ) Via1_HV
+ NEW Metal1 ( 337680 190960 ) Via1_VV
+ NEW Metal2 ( 337680 190960 ) Via2_VH
+ NEW Metal2 ( 320880 190960 ) Via2_VH
+ NEW Metal2 ( 337680 190960 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 320880 190960 ) RECT ( -280 -1040 280 0 ) ;
+ - _0287_ ( _0844_ B ) ( _0843_ ZN ) + USE SIGNAL
+ + ROUTED Metal3 ( 243600 199920 ) ( 322000 * )
+ NEW Metal1 ( 322000 199920 ) Via1_VV
+ NEW Metal2 ( 322000 199920 ) Via2_VH
+ NEW Metal1 ( 243600 199920 ) Via1_HV
+ NEW Metal2 ( 243600 199920 ) Via2_VH
+ NEW Metal2 ( 322000 199920 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 243600 199920 ) RECT ( -280 -660 280 0 ) ;
+ - _0288_ ( ANTENNA__0845__A2 I ) ( ANTENNA__0847__A2 I ) ( ANTENNA__0849__A2 I ) ( ANTENNA__0851__A2 I ) ( ANTENNA__0853__A2 I ) ( ANTENNA__0855__A2 I ) ( _0855_ A2 )
+ ( _0853_ A2 ) ( _0851_ A2 ) ( _0849_ A2 ) ( _0847_ A2 ) ( _0845_ A2 ) ( _0844_ ZN ) + USE SIGNAL
+ + ROUTED Metal3 ( 30800 50960 ) ( 43120 * )
+ NEW Metal2 ( 40880 208880 ) ( * 292880 )
+ NEW Metal3 ( 29680 291760 ) ( 40880 * )
+ NEW Metal3 ( 241360 50960 ) ( 289520 * )
+ NEW Metal3 ( 289520 50960 ) ( 298480 * )
+ NEW Metal3 ( 496720 50960 ) ( 503440 * )
+ NEW Metal2 ( 538160 205520 ) ( * 302960 )
+ NEW Metal2 ( 552720 308560 ) ( 553840 * )
+ NEW Metal2 ( 552720 302960 ) ( * 308560 )
+ NEW Metal2 ( 241360 50960 ) ( * 84000 )
+ NEW Metal2 ( 241360 84000 ) ( 243600 * )
+ NEW Metal2 ( 243600 84000 ) ( * 139440 )
+ NEW Metal2 ( 242480 139440 ) ( 243600 * )
+ NEW Metal3 ( 43120 50960 ) ( 241360 * )
+ NEW Metal3 ( 298480 50960 ) ( 496720 * )
+ NEW Metal3 ( 319200 202160 ) ( * 205520 )
+ NEW Metal2 ( 560560 302960 ) ( * 307440 )
+ NEW Metal3 ( 538160 302960 ) ( 560560 * )
+ NEW Metal2 ( 242480 139440 ) ( * 151200 )
+ NEW Metal2 ( 242480 202160 ) ( * 207760 )
+ NEW Metal3 ( 239120 207760 ) ( 242480 * )
+ NEW Metal3 ( 239120 207760 ) ( * 208880 )
+ NEW Metal2 ( 242480 151200 ) ( 244720 * )
+ NEW Metal2 ( 244720 151200 ) ( * 202160 )
+ NEW Metal3 ( 40880 208880 ) ( 239120 * )
+ NEW Metal3 ( 242480 202160 ) ( 319200 * )
+ NEW Metal3 ( 319200 205520 ) ( 538160 * )
+ NEW Metal1 ( 43120 50960 ) Via1_VV
+ NEW Metal2 ( 43120 50960 ) Via2_VH
+ NEW Metal1 ( 30800 50960 ) Via1_VV
+ NEW Metal2 ( 30800 50960 ) Via2_VH
+ NEW Metal1 ( 40880 292880 ) Via1_VV
+ NEW Metal2 ( 40880 208880 ) Via2_VH
+ NEW Metal1 ( 29680 291760 ) Via1_VV
+ NEW Metal2 ( 29680 291760 ) Via2_VH
+ NEW Metal2 ( 40880 291760 ) Via2_VH
+ NEW Metal2 ( 241360 50960 ) Via2_VH
+ NEW Metal1 ( 289520 50960 ) Via1_VV
+ NEW Metal2 ( 289520 50960 ) Via2_VH
+ NEW Metal1 ( 298480 50960 ) Via1_VV
+ NEW Metal2 ( 298480 50960 ) Via2_VH
+ NEW Metal1 ( 496720 50960 ) Via1_VV
+ NEW Metal2 ( 496720 50960 ) Via2_VH
+ NEW Metal1 ( 503440 50960 ) Via1_VV
+ NEW Metal2 ( 503440 50960 ) Via2_VH
+ NEW Metal2 ( 538160 302960 ) Via2_VH
+ NEW Metal2 ( 538160 205520 ) Via2_VH
+ NEW Metal1 ( 552720 302960 ) Via1_VV
+ NEW Metal2 ( 552720 302960 ) Via2_VH
+ NEW Metal1 ( 553840 308560 ) Via1_VV
+ NEW Metal1 ( 560560 302960 ) Via1_VV
+ NEW Metal2 ( 560560 302960 ) Via2_VH
+ NEW Metal1 ( 560560 307440 ) Via1_VV
+ NEW Metal1 ( 242480 202160 ) Via1_HV
+ NEW Metal2 ( 242480 207760 ) Via2_VH
+ NEW Metal2 ( 242480 202160 ) Via2_VH
+ NEW Metal2 ( 244720 202160 ) Via2_VH
+ NEW Metal2 ( 43120 50960 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 30800 50960 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 29680 291760 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 40880 291760 ) RECT ( -280 -1040 280 0 )
+ NEW Metal2 ( 289520 50960 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 298480 50960 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 496720 50960 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 503440 50960 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 552720 302960 ) RECT ( -280 -660 280 0 )
+ NEW Metal3 ( 552720 302960 ) RECT ( -1040 -280 0 280 )
+ NEW Metal2 ( 560560 302960 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 242480 202160 ) RECT ( -280 -1040 280 0 )
+ NEW Metal3 ( 244720 202160 ) RECT ( -1040 -280 0 280 ) ;
+ - _0289_ ( _0846_ I ) ( _0845_ Z ) + USE SIGNAL
+ + ROUTED Metal2 ( 25200 296240 ) ( 26320 * )
+ NEW Metal2 ( 25200 296240 ) ( * 309680 )
+ NEW Metal1 ( 26320 296240 ) Via1_HV
+ NEW Metal1 ( 25200 309680 ) Via1_HV ;
+ - _0290_ ( _0848_ I ) ( _0847_ Z ) + USE SIGNAL
+ + ROUTED Metal2 ( 25200 43120 ) ( * 48720 )
+ NEW Metal2 ( 25200 48720 ) ( 27440 * )
+ NEW Metal1 ( 25200 43120 ) Via1_HV
+ NEW Metal1 ( 27440 48720 ) Via1_HV ;
+ - _0291_ ( ANTENNA__0850__I I ) ( _0850_ I ) ( _0849_ Z ) + USE SIGNAL
+ + ROUTED Metal2 ( 563920 311920 ) ( 565040 * )
+ NEW Metal2 ( 565040 311920 ) ( * 319200 )
+ NEW Metal2 ( 567280 319200 ) ( * 425040 )
+ NEW Metal2 ( 565040 319200 ) ( 567280 * )
+ NEW Metal3 ( 567280 426160 ) ( 575120 * )
+ NEW Metal2 ( 567280 425040 ) ( * 426160 )
+ NEW Metal1 ( 563920 311920 ) Via1_HV
+ NEW Metal1 ( 567280 425040 ) Via1_VV
+ NEW Metal1 ( 575120 426160 ) Via1_VV
+ NEW Metal2 ( 575120 426160 ) Via2_VH
+ NEW Metal2 ( 567280 426160 ) Via2_VH
+ NEW Metal2 ( 575120 426160 ) RECT ( -280 -660 280 0 ) ;
+ - _0292_ ( _0852_ I ) ( _0851_ Z ) + USE SIGNAL
+ + ROUTED Metal2 ( 510160 44240 ) ( * 48720 )
+ NEW Metal2 ( 506800 48720 ) ( 510160 * )
+ NEW Metal1 ( 510160 44240 ) Via1_VV
+ NEW Metal1 ( 506800 48720 ) Via1_HV ;
+ - _0293_ ( _0854_ I ) ( _0853_ Z ) + USE SIGNAL
+ + ROUTED Metal2 ( 563920 301840 ) ( * 304080 )
+ NEW Metal3 ( 563920 304080 ) ( 571760 * )
+ NEW Metal2 ( 571760 304080 ) ( * 316400 )
+ NEW Metal1 ( 563920 301840 ) Via1_HV
+ NEW Metal2 ( 563920 304080 ) Via2_VH
+ NEW Metal2 ( 571760 304080 ) Via2_VH
+ NEW Metal1 ( 571760 316400 ) Via1_VV ;
+ - _0294_ ( _0856_ I ) ( _0855_ Z ) + USE SIGNAL
+ + ROUTED Metal2 ( 301840 44240 ) ( * 48720 )
+ NEW Metal1 ( 301840 44240 ) Via1_VV
+ NEW Metal1 ( 301840 48720 ) Via1_HV ;
+ - _0295_ ( _0881_ A1 ) ( _0859_ A2 ) ( _0857_ Z ) + USE SIGNAL
+ + ROUTED Metal2 ( 214480 249200 ) ( * 252560 )
+ NEW Metal2 ( 214480 252560 ) ( 216720 * )
+ NEW Metal2 ( 208880 246960 ) ( * 250320 )
+ NEW Metal2 ( 208880 250320 ) ( 214480 * )
+ NEW Metal1 ( 214480 249200 ) Via1_VV
+ NEW Metal1 ( 216720 252560 ) Via1_HV
+ NEW Metal1 ( 208880 246960 ) Via1_VV ;
+ - _0296_ ( _1027_ A1 ) ( _0883_ A1 ) ( _0859_ B ) ( _0858_ ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 214480 233520 ) ( 215600 * )
+ NEW Metal2 ( 214480 233520 ) ( * 235760 )
+ NEW Metal3 ( 205520 235760 ) ( 214480 * )
+ NEW Metal2 ( 205520 224560 ) ( * 235760 )
+ NEW Metal2 ( 205520 224560 ) ( 206640 * )
+ NEW Metal2 ( 217840 246960 ) ( * 248080 )
+ NEW Metal2 ( 216720 246960 ) ( 217840 * )
+ NEW Metal2 ( 216720 233520 ) ( * 246960 )
+ NEW Metal2 ( 215600 233520 ) ( 216720 * )
+ NEW Metal3 ( 217840 248080 ) ( 231280 * )
+ NEW Metal1 ( 215600 233520 ) Via1_VV
+ NEW Metal2 ( 214480 235760 ) Via2_VH
+ NEW Metal2 ( 205520 235760 ) Via2_VH
+ NEW Metal1 ( 206640 224560 ) Via1_VV
+ NEW Metal1 ( 217840 248080 ) Via1_VV
+ NEW Metal1 ( 231280 248080 ) Via1_VV
+ NEW Metal2 ( 231280 248080 ) Via2_VH
+ NEW Metal2 ( 217840 248080 ) Via2_VH
+ NEW Metal2 ( 231280 248080 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 217840 248080 ) RECT ( -280 -1040 280 0 ) ;
+ - _0297_ ( _0861_ A3 ) ( _0860_ Z ) + USE SIGNAL
+ + ROUTED Metal2 ( 304080 137200 ) ( * 150640 )
+ NEW Metal1 ( 304080 137200 ) Via1_VV
+ NEW Metal1 ( 304080 150640 ) Via1_VV ;
+ - _0298_ ( _1057_ A1 ) ( _0864_ A1 ) ( _0861_ ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 296240 134960 ) ( * 138320 )
+ NEW Metal3 ( 296240 134960 ) ( 308560 * )
+ NEW Metal2 ( 322000 112560 ) ( * 123760 )
+ NEW Metal2 ( 322000 123760 ) ( 323120 * )
+ NEW Metal2 ( 323120 123760 ) ( * 132720 )
+ NEW Metal3 ( 323120 132720 ) ( 324240 * )
+ NEW Metal3 ( 324240 132720 ) ( * 134960 )
+ NEW Metal3 ( 308560 134960 ) ( 324240 * )
+ NEW Metal1 ( 308560 134960 ) Via1_VV
+ NEW Metal2 ( 308560 134960 ) Via2_VH
+ NEW Metal1 ( 296240 138320 ) Via1_VV
+ NEW Metal2 ( 296240 134960 ) Via2_VH
+ NEW Metal1 ( 322000 112560 ) Via1_VV
+ NEW Metal2 ( 323120 132720 ) Via2_VH
+ NEW Metal2 ( 308560 134960 ) RECT ( -280 -660 280 0 ) ;
+ - _0299_ ( _0863_ B1 ) ( _0862_ ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 307440 108080 ) ( 308560 * )
+ NEW Metal2 ( 308560 108080 ) ( * 112560 )
+ NEW Metal1 ( 307440 108080 ) Via1_VV
+ NEW Metal1 ( 308560 112560 ) Via1_HV ;
+ - _0300_ ( _0864_ A2 ) ( _0863_ ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 320880 111440 ) ( * 112560 )
+ NEW Metal2 ( 316400 111440 ) ( 320880 * )
+ NEW Metal1 ( 316400 111440 ) Via1_VV
+ NEW Metal1 ( 320880 112560 ) Via1_VV ;
+ - _0301_ ( _0872_ A2 ) ( _0867_ A2 ) ( _0866_ ZN ) + USE SIGNAL
+ + ROUTED Metal3 ( 214480 279440 ) ( 224560 * )
+ NEW Metal2 ( 224560 279440 ) ( * 292880 )
+ NEW Metal2 ( 214480 279440 ) ( * 283920 )
+ NEW Metal2 ( 195440 283920 ) ( * 291760 )
+ NEW Metal3 ( 195440 283920 ) ( 214480 * )
+ NEW Metal1 ( 214480 279440 ) Via1_VV
+ NEW Metal2 ( 214480 279440 ) Via2_VH
+ NEW Metal2 ( 224560 279440 ) Via2_VH
+ NEW Metal1 ( 224560 292880 ) Via1_HV
+ NEW Metal2 ( 214480 283920 ) Via2_VH
+ NEW Metal2 ( 195440 283920 ) Via2_VH
+ NEW Metal1 ( 195440 291760 ) Via1_VV
+ NEW Metal2 ( 214480 279440 ) RECT ( -280 -660 280 0 ) ;
+ - _0302_ ( _0869_ A2 ) ( _0868_ ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 363440 286160 ) ( * 299600 )
+ NEW Metal2 ( 363440 299600 ) ( 364560 * )
+ NEW Metal1 ( 363440 286160 ) Via1_VV
+ NEW Metal1 ( 364560 299600 ) Via1_VV ;
+ - _0303_ ( ANTENNA__0871__I I ) ( _0871_ I ) ( _0870_ Z ) + USE SIGNAL
+ + ROUTED Metal2 ( 145040 224560 ) ( * 234640 )
+ NEW Metal2 ( 190960 276080 ) ( 197680 * )
+ NEW Metal2 ( 140560 223440 ) ( * 224560 )
+ NEW Metal2 ( 140560 224560 ) ( 145040 * )
+ NEW Metal3 ( 145040 234640 ) ( 190960 * )
+ NEW Metal2 ( 190960 234640 ) ( * 276080 )
+ NEW Metal1 ( 145040 224560 ) Via1_VV
+ NEW Metal2 ( 145040 234640 ) Via2_VH
+ NEW Metal1 ( 197680 276080 ) Via1_HV
+ NEW Metal1 ( 140560 223440 ) Via1_VV
+ NEW Metal2 ( 190960 234640 ) Via2_VH ;
+ - _0304_ ( _0873_ I ) ( _0872_ Z ) + USE SIGNAL
+ + ROUTED Metal3 ( 167440 294000 ) ( 192080 * )
+ NEW Metal1 ( 167440 294000 ) Via1_HV
+ NEW Metal2 ( 167440 294000 ) Via2_VH
+ NEW Metal1 ( 192080 294000 ) Via1_HV
+ NEW Metal2 ( 192080 294000 ) Via2_VH
+ NEW Metal2 ( 167440 294000 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 192080 294000 ) RECT ( -280 -660 280 0 ) ;
+ - _0305_ ( _0875_ I ) ( _0874_ Z ) + USE SIGNAL
+ + ROUTED Metal3 ( 444080 273840 ) ( 474320 * )
+ NEW Metal2 ( 474320 270480 ) ( * 273840 )
+ NEW Metal2 ( 444080 257040 ) ( 445200 * )
+ NEW Metal2 ( 444080 257040 ) ( * 273840 )
+ NEW Metal2 ( 444080 273840 ) Via2_VH
+ NEW Metal2 ( 474320 273840 ) Via2_VH
+ NEW Metal1 ( 474320 270480 ) Via1_VV
+ NEW Metal1 ( 445200 257040 ) Via1_VV ;
+ - _0306_ ( _0877_ I ) ( _0876_ Z ) + USE SIGNAL
+ + ROUTED Metal2 ( 483280 270480 ) ( * 271600 )
+ NEW Metal3 ( 460880 271600 ) ( 483280 * )
+ NEW Metal1 ( 483280 270480 ) Via1_VV
+ NEW Metal2 ( 483280 271600 ) Via2_VH
+ NEW Metal1 ( 460880 271600 ) Via1_VV
+ NEW Metal2 ( 460880 271600 ) Via2_VH
+ NEW Metal2 ( 460880 271600 ) RECT ( -280 -660 280 0 ) ;
+ - _0307_ ( ANTENNA__0879__I I ) ( ANTENNA__0889__A1 I ) ( ANTENNA__1023__I I ) ( ANTENNA__1044__I I ) ( ANTENNA__1062__I I ) ( ANTENNA__1177__B I ) ( ANTENNA__1227__B I )
+ ( _1227_ B ) ( _1177_ B ) ( _1062_ I ) ( _1044_ I ) ( _1023_ I ) ( _0889_ A1 ) ( _0879_ I ) ( _0878_ Z ) + USE SIGNAL
+ + ROUTED Metal3 ( 279440 207760 ) ( 283920 * )
+ NEW Metal2 ( 509040 221200 ) ( * 278320 )
+ NEW Metal3 ( 505680 221200 ) ( 509040 * )
+ NEW Metal3 ( 509040 283920 ) ( 521360 * )
+ NEW Metal2 ( 509040 278320 ) ( * 283920 )
+ NEW Metal3 ( 523600 496720 ) ( 529200 * )
+ NEW Metal2 ( 529200 448560 ) ( * 496720 )
+ NEW Metal2 ( 529200 448560 ) ( 531440 * )
+ NEW Metal2 ( 519120 496720 ) ( * 497840 )
+ NEW Metal3 ( 519120 496720 ) ( 523600 * )
+ NEW Metal3 ( 449680 465360 ) ( 529200 * )
+ NEW Metal2 ( 440720 465360 ) ( * 466480 )
+ NEW Metal3 ( 440720 465360 ) ( 449680 * )
+ NEW Metal3 ( 297360 411600 ) ( 310800 * )
+ NEW Metal3 ( 310800 409360 ) ( * 411600 )
+ NEW Metal2 ( 531440 436800 ) ( * 448560 )
+ NEW Metal2 ( 521360 283920 ) ( * 319200 )
+ NEW Metal3 ( 521360 332080 ) ( 530320 * )
+ NEW Metal2 ( 530320 332080 ) ( * 436800 )
+ NEW Metal2 ( 530320 436800 ) ( 531440 * )
+ NEW Metal3 ( 516880 332080 ) ( 521360 * )
+ NEW Metal2 ( 520240 319200 ) ( 521360 * )
+ NEW Metal2 ( 520240 319200 ) ( * 332080 )
+ NEW Metal2 ( 520240 332080 ) ( 521360 * )
+ NEW Metal2 ( 438480 409360 ) ( * 413840 )
+ NEW Metal2 ( 438480 413840 ) ( 440720 * )
+ NEW Metal2 ( 440720 413840 ) ( * 465360 )
+ NEW Metal3 ( 283920 207760 ) ( 319200 * )
+ NEW Metal3 ( 319200 206640 ) ( * 207760 )
+ NEW Metal2 ( 571760 287280 ) ( * 288400 )
+ NEW Metal3 ( 521360 288400 ) ( 571760 * )
+ NEW Metal3 ( 310800 409360 ) ( 438480 * )
+ NEW Metal3 ( 504000 221200 ) ( 505680 * )
+ NEW Metal3 ( 504000 220080 ) ( * 221200 )
+ NEW Metal3 ( 501200 220080 ) ( 504000 * )
+ NEW Metal2 ( 501200 208880 ) ( * 220080 )
+ NEW Metal3 ( 470960 208880 ) ( 501200 * )
+ NEW Metal3 ( 470960 206640 ) ( * 208880 )
+ NEW Metal2 ( 495600 220080 ) ( * 221200 )
+ NEW Metal3 ( 495600 220080 ) ( 501200 * )
+ NEW Metal3 ( 319200 206640 ) ( 470960 * )
+ NEW Metal1 ( 283920 207760 ) Via1_VV
+ NEW Metal2 ( 283920 207760 ) Via2_VH
+ NEW Metal1 ( 279440 207760 ) Via1_HV
+ NEW Metal2 ( 279440 207760 ) Via2_VH
+ NEW Metal1 ( 505680 221200 ) Via1_VV
+ NEW Metal2 ( 505680 221200 ) Via2_VH
+ NEW Metal1 ( 509040 278320 ) Via1_HV
+ NEW Metal2 ( 509040 221200 ) Via2_VH
+ NEW Metal1 ( 521360 283920 ) Via1_VV
+ NEW Metal2 ( 521360 283920 ) Via2_VH
+ NEW Metal2 ( 509040 283920 ) Via2_VH
+ NEW Metal2 ( 521360 288400 ) Via2_VH
+ NEW Metal1 ( 523600 496720 ) Via1_VV
+ NEW Metal2 ( 523600 496720 ) Via2_VH
+ NEW Metal2 ( 529200 496720 ) Via2_VH
+ NEW Metal1 ( 519120 497840 ) Via1_VV
+ NEW Metal2 ( 519120 496720 ) Via2_VH
+ NEW Metal1 ( 449680 465360 ) Via1_VV
+ NEW Metal2 ( 449680 465360 ) Via2_VH
+ NEW Metal2 ( 529200 465360 ) Via2_VH
+ NEW Metal1 ( 440720 466480 ) Via1_HV
+ NEW Metal2 ( 440720 465360 ) Via2_VH
+ NEW Metal1 ( 310800 411600 ) Via1_VV
+ NEW Metal2 ( 310800 411600 ) Via2_VH
+ NEW Metal1 ( 297360 411600 ) Via1_HV
+ NEW Metal2 ( 297360 411600 ) Via2_VH
+ NEW Metal1 ( 521360 332080 ) Via1_VV
+ NEW Metal2 ( 521360 332080 ) Via2_VH
+ NEW Metal2 ( 530320 332080 ) Via2_VH
+ NEW Metal1 ( 516880 332080 ) Via1_VV
+ NEW Metal2 ( 516880 332080 ) Via2_VH
+ NEW Metal2 ( 438480 409360 ) Via2_VH
+ NEW Metal1 ( 571760 287280 ) Via1_VV
+ NEW Metal2 ( 571760 288400 ) Via2_VH
+ NEW Metal2 ( 501200 220080 ) Via2_VH
+ NEW Metal2 ( 501200 208880 ) Via2_VH
+ NEW Metal1 ( 495600 221200 ) Via1_VV
+ NEW Metal2 ( 495600 220080 ) Via2_VH
+ NEW Metal2 ( 283920 207760 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 279440 207760 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 505680 221200 ) RECT ( -280 0 280 660 )
+ NEW Metal2 ( 521360 283920 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 521360 288400 ) RECT ( -280 -1040 280 0 )
+ NEW Metal2 ( 523600 496720 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 449680 465360 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 529200 465360 ) RECT ( -280 -1040 280 0 )
+ NEW Metal2 ( 310800 411600 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 297360 411600 ) RECT ( -280 0 280 660 )
+ NEW Metal2 ( 521360 332080 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 516880 332080 ) RECT ( -280 -660 280 0 ) ;
+ - _0308_ ( ANTENNA__0885__A1 I ) ( ANTENNA__0929__A1 I ) ( ANTENNA__1009__I I ) ( ANTENNA__1018__I I ) ( ANTENNA__1065__A1 I ) ( ANTENNA__1282__B I ) ( ANTENNA__1310__B I )
+ ( _1310_ B ) ( _1282_ B ) ( _1065_ A1 ) ( _1018_ I ) ( _1009_ I ) ( _0929_ A1 ) ( _0885_ A1 ) ( _0879_ ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 287280 159600 ) ( * 174160 )
+ NEW Metal3 ( 287280 161840 ) ( 301840 * )
+ NEW Metal2 ( 238000 383600 ) ( * 425040 )
+ NEW Metal3 ( 238000 383600 ) ( 244720 * )
+ NEW Metal2 ( 244720 327600 ) ( * 383600 )
+ NEW Metal3 ( 238000 425040 ) ( 260400 * )
+ NEW Metal2 ( 298480 412720 ) ( * 425040 )
+ NEW Metal3 ( 260400 425040 ) ( 298480 * )
+ NEW Metal2 ( 298480 403760 ) ( * 412720 )
+ NEW Metal2 ( 178640 294000 ) ( * 302960 )
+ NEW Metal2 ( 177520 302960 ) ( 178640 * )
+ NEW Metal3 ( 178640 287280 ) ( 185360 * )
+ NEW Metal2 ( 178640 287280 ) ( * 294000 )
+ NEW Metal3 ( 333200 254800 ) ( 342160 * )
+ NEW Metal3 ( 326480 254800 ) ( 333200 * )
+ NEW Metal3 ( 167440 327600 ) ( 177520 * )
+ NEW Metal3 ( 161840 327600 ) ( 167440 * )
+ NEW Metal2 ( 177520 302960 ) ( * 327600 )
+ NEW Metal3 ( 177520 327600 ) ( 244720 * )
+ NEW Metal2 ( 330960 201600 ) ( * 254800 )
+ NEW Metal2 ( 326480 161840 ) ( * 170800 )
+ NEW Metal2 ( 326480 170800 ) ( 327600 * )
+ NEW Metal2 ( 327600 170800 ) ( * 201600 )
+ NEW Metal2 ( 327600 201600 ) ( 330960 * )
+ NEW Metal3 ( 301840 161840 ) ( 326480 * )
+ NEW Metal2 ( 339920 382480 ) ( * 386960 )
+ NEW Metal2 ( 339920 382480 ) ( 343280 * )
+ NEW Metal2 ( 343280 367920 ) ( * 382480 )
+ NEW Metal2 ( 342160 367920 ) ( 343280 * )
+ NEW Metal2 ( 342160 382480 ) ( * 395920 )
+ NEW Metal2 ( 342160 395920 ) ( * 403760 )
+ NEW Metal3 ( 298480 403760 ) ( 342160 * )
+ NEW Metal2 ( 342160 254800 ) ( * 367920 )
+ NEW Metal3 ( 221200 174160 ) ( 231280 * )
+ NEW Metal3 ( 231280 174160 ) ( 287280 * )
+ NEW Metal1 ( 287280 159600 ) Via1_VV
+ NEW Metal2 ( 287280 174160 ) Via2_VH
+ NEW Metal1 ( 301840 161840 ) Via1_VV
+ NEW Metal2 ( 301840 161840 ) Via2_VH
+ NEW Metal2 ( 287280 161840 ) Via2_VH
+ NEW Metal1 ( 238000 425040 ) Via1_VV
+ NEW Metal2 ( 238000 383600 ) Via2_VH
+ NEW Metal2 ( 244720 383600 ) Via2_VH
+ NEW Metal2 ( 244720 327600 ) Via2_VH
+ NEW Metal1 ( 260400 425040 ) Via1_VV
+ NEW Metal2 ( 260400 425040 ) Via2_VH
+ NEW Metal2 ( 238000 425040 ) Via2_VH
+ NEW Metal1 ( 298480 412720 ) Via1_HV
+ NEW Metal2 ( 298480 425040 ) Via2_VH
+ NEW Metal2 ( 298480 403760 ) Via2_VH
+ NEW Metal1 ( 178640 294000 ) Via1_HV
+ NEW Metal1 ( 185360 287280 ) Via1_VV
+ NEW Metal2 ( 185360 287280 ) Via2_VH
+ NEW Metal2 ( 178640 287280 ) Via2_VH
+ NEW Metal1 ( 333200 254800 ) Via1_HV
+ NEW Metal2 ( 333200 254800 ) Via2_VH
+ NEW Metal2 ( 342160 254800 ) Via2_VH
+ NEW Metal1 ( 326480 254800 ) Via1_VV
+ NEW Metal2 ( 326480 254800 ) Via2_VH
+ NEW Metal2 ( 330960 254800 ) Via2_VH
+ NEW Metal2 ( 177520 327600 ) Via2_VH
+ NEW Metal1 ( 167440 327600 ) Via1_VV
+ NEW Metal2 ( 167440 327600 ) Via2_VH
+ NEW Metal1 ( 161840 327600 ) Via1_VV
+ NEW Metal2 ( 161840 327600 ) Via2_VH
+ NEW Metal2 ( 326480 161840 ) Via2_VH
+ NEW Metal1 ( 339920 386960 ) Via1_VV
+ NEW Metal1 ( 342160 395920 ) Via1_VV
+ NEW Metal2 ( 342160 403760 ) Via2_VH
+ NEW Metal1 ( 231280 174160 ) Via1_VV
+ NEW Metal2 ( 231280 174160 ) Via2_VH
+ NEW Metal1 ( 221200 174160 ) Via1_VV
+ NEW Metal2 ( 221200 174160 ) Via2_VH
+ NEW Metal2 ( 301840 161840 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 287280 161840 ) RECT ( -280 -1040 280 0 )
+ NEW Metal2 ( 260400 425040 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 238000 425040 ) RECT ( -280 -1040 280 0 )
+ NEW Metal2 ( 185360 287280 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 333200 254800 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 326480 254800 ) RECT ( -280 -660 280 0 )
+ NEW Metal3 ( 330960 254800 ) RECT ( -1040 -280 0 280 )
+ NEW Metal2 ( 167440 327600 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 161840 327600 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 231280 174160 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 221200 174160 ) RECT ( -280 -660 280 0 ) ;
+ - _0309_ ( _0895_ A2 ) ( _0894_ A2 ) ( _0893_ A1 ) ( _0881_ A2 ) ( _0880_ Z ) + USE SIGNAL
+ + ROUTED Metal3 ( 258160 246960 ) ( 268240 * )
+ NEW Metal3 ( 206640 246960 ) ( 258160 * )
+ NEW Metal3 ( 197680 246960 ) ( 206640 * )
+ NEW Metal2 ( 203280 246960 ) ( * 254800 )
+ NEW Metal1 ( 258160 246960 ) Via1_VV
+ NEW Metal2 ( 258160 246960 ) Via2_VH
+ NEW Metal1 ( 268240 246960 ) Via1_HV
+ NEW Metal2 ( 268240 246960 ) Via2_VH
+ NEW Metal1 ( 206640 246960 ) Via1_VV
+ NEW Metal2 ( 206640 246960 ) Via2_VH
+ NEW Metal1 ( 197680 246960 ) Via1_VV
+ NEW Metal2 ( 197680 246960 ) Via2_VH
+ NEW Metal1 ( 203280 254800 ) Via1_VV
+ NEW Metal2 ( 203280 246960 ) Via2_VH
+ NEW Metal2 ( 258160 246960 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 268240 246960 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 206640 246960 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 197680 246960 ) RECT ( -280 -660 280 0 )
+ NEW Metal3 ( 203280 246960 ) RECT ( -1040 -280 0 280 ) ;
+ - _0310_ ( _0900_ A2 ) ( _0899_ A2 ) ( _0898_ A1 ) ( _0882_ A2 ) ( _0881_ Z ) + USE SIGNAL
+ + ROUTED Metal2 ( 186480 230160 ) ( * 231280 )
+ NEW Metal2 ( 184240 231280 ) ( 186480 * )
+ NEW Metal2 ( 184240 231280 ) ( * 244720 )
+ NEW Metal3 ( 184240 238000 ) ( 201040 * )
+ NEW Metal2 ( 203280 238000 ) ( * 244720 )
+ NEW Metal2 ( 201040 238000 ) ( 203280 * )
+ NEW Metal2 ( 206640 232400 ) ( * 238000 )
+ NEW Metal3 ( 201040 238000 ) ( 206640 * )
+ NEW Metal1 ( 186480 230160 ) Via1_VV
+ NEW Metal1 ( 184240 244720 ) Via1_VV
+ NEW Metal1 ( 201040 238000 ) Via1_VV
+ NEW Metal2 ( 201040 238000 ) Via2_VH
+ NEW Metal2 ( 184240 238000 ) Via2_VH
+ NEW Metal1 ( 203280 244720 ) Via1_HV
+ NEW Metal1 ( 206640 232400 ) Via1_VV
+ NEW Metal2 ( 206640 238000 ) Via2_VH
+ NEW Metal2 ( 201040 238000 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 184240 238000 ) RECT ( -280 -1040 280 0 ) ;
+ - _0311_ ( _0904_ A2 ) ( _0883_ A2 ) ( _0882_ ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 210000 231280 ) ( 211120 * )
+ NEW Metal2 ( 211120 214480 ) ( * 231280 )
+ NEW Metal2 ( 208880 214480 ) ( 211120 * )
+ NEW Metal2 ( 211120 231280 ) ( 214480 * )
+ NEW Metal1 ( 210000 231280 ) Via1_VV
+ NEW Metal1 ( 208880 214480 ) Via1_VV
+ NEW Metal1 ( 214480 231280 ) Via1_VV ;
+ - _0312_ ( _0888_ A3 ) ( _0884_ A3 ) ( _0883_ ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 221200 201040 ) ( * 203280 )
+ NEW Metal3 ( 215600 203280 ) ( 221200 * )
+ NEW Metal2 ( 215600 203280 ) ( * 229040 )
+ NEW Metal2 ( 221200 185360 ) ( 223440 * )
+ NEW Metal2 ( 221200 185360 ) ( * 201040 )
+ NEW Metal1 ( 221200 201040 ) Via1_VV
+ NEW Metal2 ( 221200 203280 ) Via2_VH
+ NEW Metal2 ( 215600 203280 ) Via2_VH
+ NEW Metal1 ( 215600 229040 ) Via1_VV
+ NEW Metal1 ( 223440 185360 ) Via1_HV ;
+ - _0313_ ( ANTENNA__0885__A2 I ) ( ANTENNA__1060__A1 I ) ( ANTENNA__1068__A2 I ) ( ANTENNA__1076__A2 I ) ( ANTENNA__1080__A2 I ) ( ANTENNA__1085__A2 I ) ( ANTENNA__1089__A2 I )
+ ( _1089_ A2 ) ( _1085_ A2 ) ( _1080_ A2 ) ( _1076_ A2 ) ( _1068_ A2 ) ( _1060_ A1 ) ( _0885_ A2 ) ( _0884_ ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 277200 160720 ) ( * 170800 )
+ NEW Metal2 ( 221200 143920 ) ( 229040 * )
+ NEW Metal2 ( 261520 142800 ) ( 263760 * )
+ NEW Metal2 ( 263760 142800 ) ( * 149520 )
+ NEW Metal2 ( 263760 149520 ) ( 266000 * )
+ NEW Metal2 ( 268240 139440 ) ( * 142800 )
+ NEW Metal2 ( 266000 142800 ) ( 268240 * )
+ NEW Metal2 ( 266000 142800 ) ( * 149520 )
+ NEW Metal2 ( 242480 117040 ) ( * 121520 )
+ NEW Metal3 ( 227920 117040 ) ( 242480 * )
+ NEW Metal2 ( 227920 117040 ) ( * 143920 )
+ NEW Metal2 ( 232400 114800 ) ( * 117040 )
+ NEW Metal2 ( 236880 114800 ) ( * 117040 )
+ NEW Metal2 ( 248080 113680 ) ( * 117040 )
+ NEW Metal3 ( 242480 117040 ) ( 248080 * )
+ NEW Metal2 ( 221200 143920 ) ( * 151200 )
+ NEW Metal2 ( 266000 170800 ) ( 267120 * )
+ NEW Metal2 ( 266000 168560 ) ( * 170800 )
+ NEW Metal2 ( 254800 171920 ) ( * 174160 )
+ NEW Metal3 ( 254800 171920 ) ( 267120 * )
+ NEW Metal3 ( 267120 170800 ) ( * 171920 )
+ NEW Metal2 ( 248080 171920 ) ( * 174160 )
+ NEW Metal3 ( 248080 171920 ) ( 254800 * )
+ NEW Metal2 ( 242480 171920 ) ( * 182000 )
+ NEW Metal3 ( 242480 171920 ) ( 248080 * )
+ NEW Metal2 ( 226800 171920 ) ( * 174160 )
+ NEW Metal3 ( 226800 171920 ) ( 242480 * )
+ NEW Metal2 ( 222320 171920 ) ( * 175280 )
+ NEW Metal3 ( 222320 171920 ) ( 226800 * )
+ NEW Metal2 ( 221200 151200 ) ( 222320 * )
+ NEW Metal2 ( 222320 151200 ) ( * 171920 )
+ NEW Metal2 ( 218960 154000 ) ( 221200 * )
+ NEW Metal2 ( 221200 151200 ) ( * 154000 )
+ NEW Metal2 ( 266000 149520 ) ( * 168560 )
+ NEW Metal3 ( 267120 170800 ) ( 277200 * )
+ NEW Metal1 ( 277200 160720 ) Via1_VV
+ NEW Metal2 ( 277200 170800 ) Via2_VH
+ NEW Metal1 ( 229040 143920 ) Via1_VV
+ NEW Metal1 ( 261520 142800 ) Via1_VV
+ NEW Metal1 ( 268240 139440 ) Via1_VV
+ NEW Metal1 ( 242480 121520 ) Via1_VV
+ NEW Metal2 ( 242480 117040 ) Via2_VH
+ NEW Metal2 ( 227920 117040 ) Via2_VH
+ NEW Metal1 ( 232400 114800 ) Via1_VV
+ NEW Metal2 ( 232400 117040 ) Via2_VH
+ NEW Metal1 ( 236880 114800 ) Via1_VV
+ NEW Metal2 ( 236880 117040 ) Via2_VH
+ NEW Metal1 ( 248080 113680 ) Via1_HV
+ NEW Metal2 ( 248080 117040 ) Via2_VH
+ NEW Metal1 ( 266000 168560 ) Via1_VV
+ NEW Metal2 ( 267120 170800 ) Via2_VH
+ NEW Metal1 ( 254800 174160 ) Via1_VV
+ NEW Metal2 ( 254800 171920 ) Via2_VH
+ NEW Metal1 ( 248080 174160 ) Via1_VV
+ NEW Metal2 ( 248080 171920 ) Via2_VH
+ NEW Metal1 ( 242480 182000 ) Via1_HV
+ NEW Metal2 ( 242480 171920 ) Via2_VH
+ NEW Metal1 ( 226800 174160 ) Via1_VV
+ NEW Metal2 ( 226800 171920 ) Via2_VH
+ NEW Metal1 ( 222320 175280 ) Via1_VV
+ NEW Metal2 ( 222320 171920 ) Via2_VH
+ NEW Metal1 ( 218960 154000 ) Via1_VV
+ NEW Metal3 ( 232400 117040 ) RECT ( -1040 -280 0 280 )
+ NEW Metal3 ( 236880 117040 ) RECT ( -1040 -280 0 280 ) ;
+ - _0314_ ( _0886_ I ) ( _0885_ ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 218960 170800 ) ( 220080 * )
+ NEW Metal2 ( 218960 170800 ) ( * 174160 )
+ NEW Metal1 ( 220080 170800 ) Via1_VV
+ NEW Metal1 ( 218960 174160 ) Via1_VV ;
+ - _0315_ ( ANTENNA__0887__A2 I ) ( ANTENNA__0893__A2 I ) ( ANTENNA__0896__A2 I ) ( ANTENNA__0898__A2 I ) ( ANTENNA__0901__A2 I ) ( ANTENNA__0906__A1 I ) ( ANTENNA__0910__A1 I )
+ ( ANTENNA__1066__B1 I ) ( ANTENNA__1071__B1 I ) ( ANTENNA__1074__B1 I ) ( _1074_ B1 ) ( _1071_ B1 ) ( _1066_ B1 ) ( _0910_ A1 ) ( _0906_ A1 )
+ ( _0901_ A2 ) ( _0898_ A2 ) ( _0896_ A2 ) ( _0893_ A2 ) ( _0887_ A2 ) ( _0886_ Z ) + USE SIGNAL
+ + ROUTED Metal2 ( 270480 83440 ) ( * 84000 )
+ NEW Metal2 ( 277200 123760 ) ( * 133840 )
+ NEW Metal3 ( 249200 133840 ) ( 277200 * )
+ NEW Metal2 ( 289520 120400 ) ( * 121520 )
+ NEW Metal3 ( 277200 120400 ) ( 289520 * )
+ NEW Metal2 ( 277200 120400 ) ( * 123760 )
+ NEW Metal2 ( 287280 114800 ) ( * 119280 )
+ NEW Metal3 ( 287280 119280 ) ( * 120400 )
+ NEW Metal2 ( 297360 108080 ) ( * 120400 )
+ NEW Metal3 ( 289520 120400 ) ( 297360 * )
+ NEW Metal2 ( 276080 95760 ) ( 278320 * )
+ NEW Metal2 ( 278320 95760 ) ( * 100240 )
+ NEW Metal2 ( 277200 100240 ) ( 278320 * )
+ NEW Metal2 ( 277200 100240 ) ( * 120400 )
+ NEW Metal2 ( 270480 84000 ) ( 276080 * )
+ NEW Metal2 ( 276080 84000 ) ( * 95760 )
+ NEW Metal3 ( 225680 169680 ) ( 249200 * )
+ NEW Metal2 ( 208880 169680 ) ( * 174160 )
+ NEW Metal3 ( 208880 169680 ) ( 225680 * )
+ NEW Metal3 ( 203280 174160 ) ( 208880 * )
+ NEW Metal3 ( 195440 205520 ) ( 202160 * )
+ NEW Metal2 ( 202160 174160 ) ( * 205520 )
+ NEW Metal2 ( 202160 174160 ) ( 203280 * )
+ NEW Metal2 ( 186480 205520 ) ( * 207760 )
+ NEW Metal3 ( 186480 205520 ) ( 195440 * )
+ NEW Metal2 ( 179760 205520 ) ( * 214480 )
+ NEW Metal3 ( 179760 205520 ) ( 186480 * )
+ NEW Metal2 ( 183120 220080 ) ( * 223440 )
+ NEW Metal2 ( 182000 220080 ) ( 183120 * )
+ NEW Metal2 ( 182000 214480 ) ( * 220080 )
+ NEW Metal2 ( 179760 214480 ) ( 182000 * )
+ NEW Metal2 ( 249200 169680 ) ( * 230160 )
+ NEW Metal3 ( 249200 229040 ) ( 257040 * )
+ NEW Metal2 ( 178640 245840 ) ( 179760 * )
+ NEW Metal2 ( 179760 231280 ) ( * 245840 )
+ NEW Metal2 ( 178640 231280 ) ( 179760 * )
+ NEW Metal2 ( 178640 214480 ) ( * 231280 )
+ NEW Metal2 ( 178640 214480 ) ( 179760 * )
+ NEW Metal3 ( 179760 244720 ) ( 186480 * )
+ NEW Metal2 ( 249200 230160 ) ( * 245840 )
+ NEW Metal3 ( 249200 244720 ) ( 260400 * )
+ NEW Metal2 ( 183120 244720 ) ( * 252560 )
+ NEW Metal2 ( 192080 244720 ) ( * 254800 )
+ NEW Metal3 ( 186480 244720 ) ( 192080 * )
+ NEW Metal2 ( 249200 133840 ) ( * 169680 )
+ NEW Metal1 ( 270480 83440 ) Via1_VV
+ NEW Metal1 ( 277200 123760 ) Via1_VV
+ NEW Metal2 ( 277200 133840 ) Via2_VH
+ NEW Metal2 ( 249200 133840 ) Via2_VH
+ NEW Metal1 ( 289520 121520 ) Via1_VV
+ NEW Metal2 ( 289520 120400 ) Via2_VH
+ NEW Metal2 ( 277200 120400 ) Via2_VH
+ NEW Metal1 ( 287280 114800 ) Via1_VV
+ NEW Metal2 ( 287280 119280 ) Via2_VH
+ NEW Metal1 ( 297360 108080 ) Via1_VV
+ NEW Metal2 ( 297360 120400 ) Via2_VH
+ NEW Metal1 ( 276080 95760 ) Via1_VV
+ NEW Metal1 ( 225680 169680 ) Via1_VV
+ NEW Metal2 ( 225680 169680 ) Via2_VH
+ NEW Metal2 ( 249200 169680 ) Via2_VH
+ NEW Metal1 ( 208880 174160 ) Via1_VV
+ NEW Metal2 ( 208880 169680 ) Via2_VH
+ NEW Metal1 ( 203280 174160 ) Via1_VV
+ NEW Metal2 ( 203280 174160 ) Via2_VH
+ NEW Metal2 ( 208880 174160 ) Via2_VH
+ NEW Metal1 ( 195440 205520 ) Via1_VV
+ NEW Metal2 ( 195440 205520 ) Via2_VH
+ NEW Metal2 ( 202160 205520 ) Via2_VH
+ NEW Metal1 ( 186480 207760 ) Via1_VV
+ NEW Metal2 ( 186480 205520 ) Via2_VH
+ NEW Metal1 ( 179760 214480 ) Via1_VV
+ NEW Metal2 ( 179760 205520 ) Via2_VH
+ NEW Metal1 ( 183120 223440 ) Via1_VV
+ NEW Metal1 ( 249200 230160 ) Via1_VV
+ NEW Metal1 ( 257040 229040 ) Via1_VV
+ NEW Metal2 ( 257040 229040 ) Via2_VH
+ NEW Metal2 ( 249200 229040 ) Via2_VH
+ NEW Metal1 ( 178640 245840 ) Via1_VV
+ NEW Metal1 ( 186480 244720 ) Via1_VV
+ NEW Metal2 ( 186480 244720 ) Via2_VH
+ NEW Metal2 ( 179760 244720 ) Via2_VH
+ NEW Metal1 ( 249200 245840 ) Via1_VV
+ NEW Metal1 ( 260400 244720 ) Via1_VV
+ NEW Metal2 ( 260400 244720 ) Via2_VH
+ NEW Metal2 ( 249200 244720 ) Via2_VH
+ NEW Metal1 ( 183120 252560 ) Via1_VV
+ NEW Metal2 ( 183120 244720 ) Via2_VH
+ NEW Metal1 ( 192080 254800 ) Via1_VV
+ NEW Metal2 ( 192080 244720 ) Via2_VH
+ NEW Metal2 ( 225680 169680 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 203280 174160 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 208880 174160 ) RECT ( -280 -1040 280 0 )
+ NEW Metal2 ( 195440 205520 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 257040 229040 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 249200 229040 ) RECT ( -280 -1040 280 0 )
+ NEW Metal2 ( 186480 244720 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 179760 244720 ) RECT ( -280 -1040 280 0 )
+ NEW Metal2 ( 260400 244720 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 249200 244720 ) RECT ( -280 -1040 280 0 )
+ NEW Metal3 ( 183120 244720 ) RECT ( -1040 -280 0 280 ) ;
+ - _0316_ ( _1093_ A1 ) ( _1091_ A2 ) ( _1063_ A2 ) ( _0889_ A2 ) ( _0888_ Z ) + USE SIGNAL
+ + ROUTED Metal2 ( 276080 201600 ) ( * 206640 )
+ NEW Metal2 ( 274960 201600 ) ( 276080 * )
+ NEW Metal2 ( 274960 192080 ) ( * 201600 )
+ NEW Metal3 ( 270480 192080 ) ( 274960 * )
+ NEW Metal2 ( 280560 201040 ) ( * 201600 )
+ NEW Metal2 ( 276080 201600 ) ( 280560 * )
+ NEW Metal2 ( 280560 185360 ) ( * 201040 )
+ NEW Metal2 ( 225680 192080 ) ( * 197680 )
+ NEW Metal3 ( 225680 192080 ) ( 270480 * )
+ NEW Metal1 ( 276080 206640 ) Via1_VV
+ NEW Metal1 ( 270480 192080 ) Via1_HV
+ NEW Metal2 ( 270480 192080 ) Via2_VH
+ NEW Metal2 ( 274960 192080 ) Via2_VH
+ NEW Metal1 ( 280560 201040 ) Via1_VV
+ NEW Metal1 ( 280560 185360 ) Via1_VV
+ NEW Metal2 ( 225680 192080 ) Via2_VH
+ NEW Metal1 ( 225680 197680 ) Via1_HV
+ NEW Metal2 ( 270480 192080 ) RECT ( -280 -660 280 0 ) ;
+ - _0317_ ( ANTENNA__0890__B I ) ( ANTENNA__0902__B I ) ( ANTENNA__0907__B I ) ( _0907_ B ) ( _0902_ B ) ( _0890_ B ) ( _0889_ ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 269360 211120 ) ( * 215600 )
+ NEW Metal2 ( 277200 208880 ) ( * 211120 )
+ NEW Metal3 ( 269360 211120 ) ( 277200 * )
+ NEW Metal2 ( 277200 214480 ) ( 279440 * )
+ NEW Metal2 ( 277200 211120 ) ( * 214480 )
+ NEW Metal2 ( 198800 211120 ) ( * 214480 )
+ NEW Metal2 ( 196560 214480 ) ( * 223440 )
+ NEW Metal2 ( 196560 214480 ) ( 198800 * )
+ NEW Metal2 ( 196560 202160 ) ( * 214480 )
+ NEW Metal3 ( 196560 193200 ) ( 206640 * )
+ NEW Metal2 ( 196560 193200 ) ( * 202160 )
+ NEW Metal3 ( 198800 211120 ) ( 269360 * )
+ NEW Metal1 ( 269360 215600 ) Via1_HV
+ NEW Metal2 ( 269360 211120 ) Via2_VH
+ NEW Metal1 ( 277200 208880 ) Via1_VV
+ NEW Metal2 ( 277200 211120 ) Via2_VH
+ NEW Metal1 ( 279440 214480 ) Via1_VV
+ NEW Metal1 ( 198800 214480 ) Via1_VV
+ NEW Metal2 ( 198800 211120 ) Via2_VH
+ NEW Metal1 ( 196560 223440 ) Via1_HV
+ NEW Metal1 ( 196560 202160 ) Via1_VV
+ NEW Metal1 ( 206640 193200 ) Via1_VV
+ NEW Metal2 ( 206640 193200 ) Via2_VH
+ NEW Metal2 ( 196560 193200 ) Via2_VH
+ NEW Metal2 ( 206640 193200 ) RECT ( -280 -660 280 0 ) ;
+ - _0318_ ( _0891_ B ) ( _0890_ ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 272720 217840 ) ( 273840 * )
+ NEW Metal2 ( 272720 217840 ) ( * 231280 )
+ NEW Metal1 ( 273840 217840 ) Via1_VV
+ NEW Metal1 ( 272720 231280 ) Via1_VV ;
+ - _0319_ ( _0893_ A3 ) ( _0892_ ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 260400 246960 ) ( 261520 * )
+ NEW Metal2 ( 260400 246960 ) ( * 261520 )
+ NEW Metal3 ( 260400 261520 ) ( 268240 * )
+ NEW Metal1 ( 261520 246960 ) Via1_VV
+ NEW Metal2 ( 260400 261520 ) Via2_VH
+ NEW Metal1 ( 268240 261520 ) Via1_VV
+ NEW Metal2 ( 268240 261520 ) Via2_VH
+ NEW Metal2 ( 268240 261520 ) RECT ( -280 -660 280 0 ) ;
+ - _0320_ ( _0897_ A2 ) ( _0896_ A1 ) ( _0894_ Z ) + USE SIGNAL
+ + ROUTED Metal3 ( 189840 257040 ) ( 199920 * )
+ NEW Metal2 ( 192080 241360 ) ( 193200 * )
+ NEW Metal2 ( 193200 241360 ) ( * 257040 )
+ NEW Metal1 ( 189840 257040 ) Via1_VV
+ NEW Metal2 ( 189840 257040 ) Via2_VH
+ NEW Metal1 ( 199920 257040 ) Via1_HV
+ NEW Metal2 ( 199920 257040 ) Via2_VH
+ NEW Metal1 ( 192080 241360 ) Via1_VV
+ NEW Metal2 ( 193200 257040 ) Via2_VH
+ NEW Metal2 ( 189840 257040 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 199920 257040 ) RECT ( -280 -660 280 0 )
+ NEW Metal3 ( 193200 257040 ) RECT ( -1040 -280 0 280 ) ;
+ - _0321_ ( _0896_ A3 ) ( _0895_ ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 194320 245840 ) ( * 254800 )
+ NEW Metal1 ( 194320 245840 ) Via1_HV
+ NEW Metal1 ( 194320 254800 ) Via1_HV ;
+ - _0322_ ( _0898_ A3 ) ( _0897_ ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 188720 241360 ) ( * 246960 )
+ NEW Metal1 ( 188720 241360 ) Via1_VV
+ NEW Metal1 ( 188720 246960 ) Via1_HV ;
+ - _0323_ ( _0905_ A2 ) ( _0903_ A2 ) ( _0902_ A2 ) ( _0901_ A1 ) ( _0899_ Z ) + USE SIGNAL
+ + ROUTED Metal3 ( 168560 223440 ) ( 180880 * )
+ NEW Metal2 ( 182000 229040 ) ( 183120 * )
+ NEW Metal2 ( 182000 223440 ) ( * 229040 )
+ NEW Metal2 ( 180880 223440 ) ( 182000 * )
+ NEW Metal2 ( 185360 216720 ) ( * 221200 )
+ NEW Metal2 ( 184240 221200 ) ( 185360 * )
+ NEW Metal2 ( 184240 221200 ) ( * 223440 )
+ NEW Metal3 ( 180880 223440 ) ( 184240 * )
+ NEW Metal3 ( 184240 223440 ) ( 190960 * )
+ NEW Metal1 ( 180880 223440 ) Via1_VV
+ NEW Metal2 ( 180880 223440 ) Via2_VH
+ NEW Metal1 ( 168560 223440 ) Via1_VV
+ NEW Metal2 ( 168560 223440 ) Via2_VH
+ NEW Metal1 ( 183120 229040 ) Via1_HV
+ NEW Metal1 ( 185360 216720 ) Via1_VV
+ NEW Metal2 ( 184240 223440 ) Via2_VH
+ NEW Metal1 ( 190960 223440 ) Via1_VV
+ NEW Metal2 ( 190960 223440 ) Via2_VH
+ NEW Metal2 ( 180880 223440 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 168560 223440 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 190960 223440 ) RECT ( -280 -660 280 0 ) ;
+ - _0324_ ( _0901_ A3 ) ( _0900_ ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 185360 223440 ) ( 187600 * )
+ NEW Metal2 ( 187600 223440 ) ( * 232400 )
+ NEW Metal2 ( 187600 232400 ) ( 193200 * )
+ NEW Metal2 ( 193200 232400 ) ( * 240240 )
+ NEW Metal2 ( 193200 240240 ) ( 197680 * )
+ NEW Metal1 ( 185360 223440 ) Via1_HV
+ NEW Metal1 ( 197680 240240 ) Via1_HV ;
+ - _0325_ ( _0903_ B ) ( _0902_ ZN ) + USE SIGNAL
+ + ROUTED Metal3 ( 174160 222320 ) ( 192080 * )
+ NEW Metal1 ( 192080 222320 ) Via1_VV
+ NEW Metal2 ( 192080 222320 ) Via2_VH
+ NEW Metal1 ( 174160 222320 ) Via1_VV
+ NEW Metal2 ( 174160 222320 ) Via2_VH
+ NEW Metal2 ( 192080 222320 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 174160 222320 ) RECT ( -280 -660 280 0 ) ;
+ - _0326_ ( _0909_ A2 ) ( _0908_ A2 ) ( _0907_ A2 ) ( _0906_ A2 ) ( _0904_ ZN ) + USE SIGNAL
+ + ROUTED Metal3 ( 201040 202160 ) ( 205520 * )
+ NEW Metal2 ( 205520 202160 ) ( * 213360 )
+ NEW Metal2 ( 188720 202160 ) ( * 207760 )
+ NEW Metal3 ( 188720 202160 ) ( 201040 * )
+ NEW Metal2 ( 195440 192080 ) ( * 202160 )
+ NEW Metal2 ( 199920 185360 ) ( * 186480 )
+ NEW Metal2 ( 195440 186480 ) ( 199920 * )
+ NEW Metal2 ( 195440 186480 ) ( * 192080 )
+ NEW Metal1 ( 201040 202160 ) Via1_VV
+ NEW Metal2 ( 201040 202160 ) Via2_VH
+ NEW Metal2 ( 205520 202160 ) Via2_VH
+ NEW Metal1 ( 205520 213360 ) Via1_VV
+ NEW Metal1 ( 188720 207760 ) Via1_VV
+ NEW Metal2 ( 188720 202160 ) Via2_VH
+ NEW Metal1 ( 195440 192080 ) Via1_VV
+ NEW Metal2 ( 195440 202160 ) Via2_VH
+ NEW Metal1 ( 199920 185360 ) Via1_VV
+ NEW Metal2 ( 201040 202160 ) RECT ( -280 -660 280 0 )
+ NEW Metal3 ( 195440 202160 ) RECT ( -1040 -280 0 280 ) ;
+ - _0327_ ( _0906_ A3 ) ( _0905_ ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 187600 210000 ) ( 189840 * )
+ NEW Metal2 ( 187600 210000 ) ( * 217840 )
+ NEW Metal1 ( 189840 210000 ) Via1_VV
+ NEW Metal1 ( 187600 217840 ) Via1_VV ;
+ - _0328_ ( _0908_ B ) ( _0907_ ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 199920 192080 ) ( * 198800 )
+ NEW Metal1 ( 199920 192080 ) Via1_VV
+ NEW Metal1 ( 199920 198800 ) Via1_VV ;
+ - _0329_ ( _0910_ A2 ) ( _0909_ ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 201040 178640 ) ( * 183120 )
+ NEW Metal1 ( 201040 178640 ) Via1_VV
+ NEW Metal1 ( 201040 183120 ) Via1_VV ;
+ - _0330_ ( ANTENNA__0928__A1 I ) ( _0928_ A1 ) ( _0911_ ZN ) + USE SIGNAL
+ + ROUTED Metal3 ( 98000 316400 ) ( 111440 * )
+ NEW Metal2 ( 111440 283920 ) ( * 316400 )
+ NEW Metal2 ( 111440 283920 ) ( 115920 * )
+ NEW Metal2 ( 115920 234640 ) ( * 283920 )
+ NEW Metal2 ( 114800 234640 ) ( 115920 * )
+ NEW Metal2 ( 114800 224560 ) ( * 234640 )
+ NEW Metal2 ( 109200 316400 ) ( 111440 * )
+ NEW Metal1 ( 98000 316400 ) Via1_VV
+ NEW Metal2 ( 98000 316400 ) Via2_VH
+ NEW Metal2 ( 111440 316400 ) Via2_VH
+ NEW Metal1 ( 114800 224560 ) Via1_VV
+ NEW Metal1 ( 109200 316400 ) Via1_VV
+ NEW Metal2 ( 98000 316400 ) RECT ( -280 -660 280 0 ) ;
+ - _0331_ ( _0915_ A1 ) ( _0912_ ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 113680 311920 ) ( 115920 * )
+ NEW Metal2 ( 115920 311920 ) ( * 317520 )
+ NEW Metal1 ( 113680 311920 ) Via1_VV
+ NEW Metal1 ( 115920 317520 ) Via1_VV ;
+ - _0332_ ( _0914_ A4 ) ( _0913_ ZN ) + USE SIGNAL
+ + ROUTED Metal3 ( 87920 338800 ) ( 101360 * )
+ NEW Metal1 ( 101360 338800 ) Via1_VV
+ NEW Metal2 ( 101360 338800 ) Via2_VH
+ NEW Metal1 ( 87920 338800 ) Via1_VV
+ NEW Metal2 ( 87920 338800 ) Via2_VH
+ NEW Metal2 ( 101360 338800 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 87920 338800 ) RECT ( -280 -660 280 0 ) ;
+ - _0333_ ( _0915_ A3 ) ( _0914_ Z ) + USE SIGNAL
+ + ROUTED Metal2 ( 119280 319760 ) ( * 336560 )
+ NEW Metal3 ( 96880 336560 ) ( 119280 * )
+ NEW Metal2 ( 96880 336560 ) ( * 338800 )
+ NEW Metal1 ( 119280 319760 ) Via1_VV
+ NEW Metal2 ( 119280 336560 ) Via2_VH
+ NEW Metal2 ( 96880 336560 ) Via2_VH
+ NEW Metal1 ( 96880 338800 ) Via1_VV ;
+ - _0334_ ( _0928_ A2 ) ( _0915_ ZN ) + USE SIGNAL
+ + ROUTED Metal3 ( 106960 317520 ) ( 114800 * )
+ NEW Metal1 ( 106960 317520 ) Via1_VV
+ NEW Metal2 ( 106960 317520 ) Via2_VH
+ NEW Metal1 ( 114800 317520 ) Via1_VV
+ NEW Metal2 ( 114800 317520 ) Via2_VH
+ NEW Metal2 ( 106960 317520 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 114800 317520 ) RECT ( -280 -660 280 0 ) ;
+ - _0335_ ( _1006_ A2 ) ( _0917_ A3 ) ( _0916_ ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 56560 306320 ) ( * 309680 )
+ NEW Metal3 ( 56560 306320 ) ( 76720 * )
+ NEW Metal2 ( 76720 304080 ) ( * 306320 )
+ NEW Metal2 ( 62160 325360 ) ( 63280 * )
+ NEW Metal2 ( 62160 306320 ) ( * 325360 )
+ NEW Metal1 ( 56560 309680 ) Via1_VV
+ NEW Metal2 ( 56560 306320 ) Via2_VH
+ NEW Metal2 ( 76720 306320 ) Via2_VH
+ NEW Metal1 ( 76720 304080 ) Via1_VV
+ NEW Metal2 ( 62160 306320 ) Via2_VH
+ NEW Metal1 ( 63280 325360 ) Via1_VV
+ NEW Metal3 ( 62160 306320 ) RECT ( -1040 -280 0 280 ) ;
+ - _0336_ ( _0918_ A3 ) ( _0917_ ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 67760 320880 ) ( 68880 * )
+ NEW Metal2 ( 68880 320880 ) ( * 324240 )
+ NEW Metal2 ( 67760 318640 ) ( * 320880 )
+ NEW Metal2 ( 101360 309680 ) ( * 318640 )
+ NEW Metal3 ( 67760 318640 ) ( 101360 * )
+ NEW Metal2 ( 67760 318640 ) Via2_VH
+ NEW Metal1 ( 68880 324240 ) Via1_VV
+ NEW Metal1 ( 101360 309680 ) Via1_HV
+ NEW Metal2 ( 101360 318640 ) Via2_VH ;
+ - _0337_ ( _0928_ A3 ) ( _0918_ ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 102480 311920 ) ( 103600 * )
+ NEW Metal2 ( 103600 311920 ) ( * 315280 )
+ NEW Metal2 ( 103600 315280 ) ( 104720 * )
+ NEW Metal1 ( 102480 311920 ) Via1_VV
+ NEW Metal1 ( 104720 315280 ) Via1_VV ;
+ - _0338_ ( _0933_ A1 ) ( _0922_ A1 ) ( _0919_ ZN ) + USE SIGNAL
+ + ROUTED Metal3 ( 119280 199920 ) ( 138320 * )
+ NEW Metal2 ( 138320 193200 ) ( * 199920 )
+ NEW Metal2 ( 108080 199920 ) ( * 201040 )
+ NEW Metal3 ( 108080 199920 ) ( 119280 * )
+ NEW Metal2 ( 119280 199920 ) ( * 207760 )
+ NEW Metal1 ( 119280 207760 ) Via1_VV
+ NEW Metal2 ( 119280 199920 ) Via2_VH
+ NEW Metal2 ( 138320 199920 ) Via2_VH
+ NEW Metal1 ( 138320 193200 ) Via1_VV
+ NEW Metal1 ( 108080 201040 ) Via1_VV
+ NEW Metal2 ( 108080 199920 ) Via2_VH ;
+ - _0339_ ( _0922_ A2 ) ( _0920_ ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 109200 194320 ) ( * 195440 )
+ NEW Metal2 ( 105840 195440 ) ( 109200 * )
+ NEW Metal2 ( 105840 195440 ) ( * 199920 )
+ NEW Metal1 ( 109200 194320 ) Via1_VV
+ NEW Metal1 ( 105840 199920 ) Via1_HV ;
+ - _0340_ ( _0949_ A3 ) ( _0922_ A3 ) ( _0921_ Z ) + USE SIGNAL
+ + ROUTED Metal2 ( 76720 194320 ) ( * 199920 )
+ NEW Metal3 ( 86800 199920 ) ( 102480 * )
+ NEW Metal3 ( 76720 199920 ) ( 86800 * )
+ NEW Metal1 ( 76720 194320 ) Via1_HV
+ NEW Metal2 ( 76720 199920 ) Via2_VH
+ NEW Metal1 ( 86800 199920 ) Via1_VV
+ NEW Metal2 ( 86800 199920 ) Via2_VH
+ NEW Metal1 ( 102480 199920 ) Via1_VV
+ NEW Metal2 ( 102480 199920 ) Via2_VH
+ NEW Metal2 ( 86800 199920 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 102480 199920 ) RECT ( -280 -660 280 0 ) ;
+ - _0341_ ( _0927_ A1 ) ( _0922_ ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 105840 201600 ) ( * 223440 )
+ NEW Metal2 ( 105840 201600 ) ( 106960 * )
+ NEW Metal2 ( 106960 198800 ) ( * 201600 )
+ NEW Metal1 ( 105840 223440 ) Via1_VV
+ NEW Metal1 ( 106960 198800 ) Via1_HV ;
+ - _0342_ ( _0969_ A1 ) ( _0963_ A1 ) ( _0925_ A1 ) ( _0923_ ZN ) + USE SIGNAL
+ + ROUTED Metal3 ( 87920 248080 ) ( 102480 * )
+ NEW Metal2 ( 96880 239120 ) ( * 248080 )
+ NEW Metal3 ( 81200 248080 ) ( 87920 * )
+ NEW Metal1 ( 81200 248080 ) Via1_VV
+ NEW Metal2 ( 81200 248080 ) Via2_VH
+ NEW Metal1 ( 87920 248080 ) Via1_VV
+ NEW Metal2 ( 87920 248080 ) Via2_VH
+ NEW Metal1 ( 102480 248080 ) Via1_HV
+ NEW Metal2 ( 102480 248080 ) Via2_VH
+ NEW Metal1 ( 96880 239120 ) Via1_VV
+ NEW Metal2 ( 96880 248080 ) Via2_VH
+ NEW Metal2 ( 81200 248080 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 87920 248080 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 102480 248080 ) RECT ( -280 -660 280 0 )
+ NEW Metal3 ( 96880 248080 ) RECT ( -1040 -280 0 280 ) ;
+ - _0343_ ( _0969_ A2 ) ( _0965_ A1 ) ( _0925_ A3 ) ( _0924_ ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 98000 254800 ) ( * 257040 )
+ NEW Metal3 ( 98000 257040 ) ( 109200 * )
+ NEW Metal2 ( 109200 257040 ) ( * 260400 )
+ NEW Metal2 ( 101360 246960 ) ( * 252560 )
+ NEW Metal2 ( 100240 252560 ) ( 101360 * )
+ NEW Metal2 ( 100240 252560 ) ( * 257040 )
+ NEW Metal2 ( 101360 239120 ) ( * 246960 )
+ NEW Metal1 ( 98000 254800 ) Via1_HV
+ NEW Metal2 ( 98000 257040 ) Via2_VH
+ NEW Metal2 ( 109200 257040 ) Via2_VH
+ NEW Metal1 ( 109200 260400 ) Via1_VV
+ NEW Metal1 ( 101360 246960 ) Via1_HV
+ NEW Metal2 ( 100240 257040 ) Via2_VH
+ NEW Metal1 ( 101360 239120 ) Via1_VV
+ NEW Metal3 ( 100240 257040 ) RECT ( -1040 -280 0 280 ) ;
+ - _0344_ ( _0927_ A2 ) ( _0925_ ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 103600 225680 ) ( * 226800 )
+ NEW Metal3 ( 95760 226800 ) ( 103600 * )
+ NEW Metal2 ( 95760 226800 ) ( * 236880 )
+ NEW Metal1 ( 103600 225680 ) Via1_VV
+ NEW Metal2 ( 103600 226800 ) Via2_VH
+ NEW Metal2 ( 95760 226800 ) Via2_VH
+ NEW Metal1 ( 95760 236880 ) Via1_VV ;
+ - _0345_ ( _0927_ A3 ) ( _0926_ ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 93520 207760 ) ( * 223440 )
+ NEW Metal3 ( 93520 223440 ) ( 101360 * )
+ NEW Metal1 ( 93520 207760 ) Via1_VV
+ NEW Metal2 ( 93520 223440 ) Via2_VH
+ NEW Metal1 ( 101360 223440 ) Via1_HV
+ NEW Metal2 ( 101360 223440 ) Via2_VH
+ NEW Metal2 ( 101360 223440 ) RECT ( -280 -660 280 0 ) ;
+ - _0346_ ( ANTENNA__0928__A4 I ) ( _0928_ A4 ) ( _0927_ ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 102480 314160 ) ( * 316400 )
+ NEW Metal3 ( 102480 309680 ) ( * 314160 )
+ NEW Metal2 ( 102480 304080 ) ( * 309680 )
+ NEW Metal2 ( 102480 304080 ) ( 103600 * )
+ NEW Metal2 ( 103600 296240 ) ( * 304080 )
+ NEW Metal2 ( 102480 296240 ) ( 103600 * )
+ NEW Metal2 ( 102480 281680 ) ( * 296240 )
+ NEW Metal2 ( 102480 281680 ) ( 103600 * )
+ NEW Metal2 ( 103600 245840 ) ( * 281680 )
+ NEW Metal2 ( 102480 245840 ) ( 103600 * )
+ NEW Metal2 ( 102480 221200 ) ( * 245840 )
+ NEW Metal2 ( 118160 308560 ) ( * 309680 )
+ NEW Metal2 ( 118160 309680 ) ( 119280 * )
+ NEW Metal3 ( 102480 309680 ) ( 119280 * )
+ NEW Metal1 ( 102480 316400 ) Via1_VV
+ NEW Metal2 ( 102480 314160 ) Via2_VH
+ NEW Metal2 ( 102480 309680 ) Via2_VH
+ NEW Metal1 ( 102480 221200 ) Via1_VV
+ NEW Metal1 ( 118160 308560 ) Via1_VV
+ NEW Metal2 ( 119280 309680 ) Via2_VH ;
+ - _0347_ ( ANTENNA__0929__A2 I ) ( ANTENNA__1324__A1 I ) ( _1324_ A1 ) ( _0929_ A2 ) ( _0928_ ZN ) + USE SIGNAL
+ + ROUTED Metal3 ( 103600 324240 ) ( 155120 * )
+ NEW Metal2 ( 103600 319760 ) ( * 324240 )
+ NEW Metal2 ( 162960 324240 ) ( * 325360 )
+ NEW Metal3 ( 155120 324240 ) ( 162960 * )
+ NEW Metal2 ( 170800 343280 ) ( * 355600 )
+ NEW Metal2 ( 168560 343280 ) ( 170800 * )
+ NEW Metal2 ( 168560 335440 ) ( * 343280 )
+ NEW Metal3 ( 162960 335440 ) ( 168560 * )
+ NEW Metal2 ( 162960 325360 ) ( * 335440 )
+ NEW Metal2 ( 170800 355600 ) ( 179760 * )
+ NEW Metal1 ( 155120 324240 ) Via1_VV
+ NEW Metal2 ( 155120 324240 ) Via2_VH
+ NEW Metal2 ( 103600 324240 ) Via2_VH
+ NEW Metal1 ( 103600 319760 ) Via1_VV
+ NEW Metal1 ( 162960 325360 ) Via1_VV
+ NEW Metal2 ( 162960 324240 ) Via2_VH
+ NEW Metal1 ( 170800 355600 ) Via1_VV
+ NEW Metal2 ( 168560 335440 ) Via2_VH
+ NEW Metal2 ( 162960 335440 ) Via2_VH
+ NEW Metal1 ( 179760 355600 ) Via1_VV
+ NEW Metal2 ( 155120 324240 ) RECT ( -280 -660 280 0 ) ;
+ - _0348_ ( ANTENNA__0930__I I ) ( ANTENNA__0951__I I ) ( ANTENNA__0975__C I ) ( ANTENNA__0982__B I ) ( ANTENNA__0989__I I ) ( _0989_ I ) ( _0982_ B )
+ ( _0975_ C ) ( _0951_ I ) ( _0930_ I ) ( _0929_ ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 83440 324240 ) ( * 332080 )
+ NEW Metal3 ( 103600 292880 ) ( 126000 * )
+ NEW Metal2 ( 103600 292880 ) ( * 294000 )
+ NEW Metal2 ( 142800 292880 ) ( * 301840 )
+ NEW Metal3 ( 126000 292880 ) ( 142800 * )
+ NEW Metal3 ( 142800 301840 ) ( 149520 * )
+ NEW Metal3 ( 149520 301840 ) ( 159600 * )
+ NEW Metal2 ( 156240 343280 ) ( * 347760 )
+ NEW Metal2 ( 154000 347760 ) ( 156240 * )
+ NEW Metal2 ( 156240 327600 ) ( 159600 * )
+ NEW Metal2 ( 156240 327600 ) ( * 343280 )
+ NEW Metal2 ( 98000 319760 ) ( * 324240 )
+ NEW Metal3 ( 98000 319760 ) ( 119280 * )
+ NEW Metal3 ( 85680 324240 ) ( 98000 * )
+ NEW Metal2 ( 90160 324240 ) ( * 330960 )
+ NEW Metal2 ( 83440 324240 ) ( 85680 * )
+ NEW Metal4 ( 119280 292880 ) ( * 319760 )
+ NEW Metal2 ( 159600 301840 ) ( * 327600 )
+ NEW Metal1 ( 83440 332080 ) Via1_VV
+ NEW Metal1 ( 126000 292880 ) Via1_VV
+ NEW Metal2 ( 126000 292880 ) Via2_VH
+ NEW Metal2 ( 103600 292880 ) Via2_VH
+ NEW Metal1 ( 103600 294000 ) Via1_VV
+ NEW Metal1 ( 142800 301840 ) Via1_HV
+ NEW Metal2 ( 142800 292880 ) Via2_VH
+ NEW Metal1 ( 149520 301840 ) Via1_VV
+ NEW Metal2 ( 149520 301840 ) Via2_VH
+ NEW Metal2 ( 142800 301840 ) Via2_VH
+ NEW Metal3 ( 119280 292880 ) Via3_HV
+ NEW Metal2 ( 159600 301840 ) Via2_VH
+ NEW Metal1 ( 156240 343280 ) Via1_VV
+ NEW Metal1 ( 154000 347760 ) Via1_VV
+ NEW Metal1 ( 159600 327600 ) Via1_VV
+ NEW Metal1 ( 98000 324240 ) Via1_VV
+ NEW Metal2 ( 98000 319760 ) Via2_VH
+ NEW Metal3 ( 119280 319760 ) Via3_HV
+ NEW Metal1 ( 85680 324240 ) Via1_VV
+ NEW Metal2 ( 85680 324240 ) Via2_VH
+ NEW Metal2 ( 98000 324240 ) Via2_VH
+ NEW Metal1 ( 90160 330960 ) Via1_VV
+ NEW Metal2 ( 90160 324240 ) Via2_VH
+ NEW Metal2 ( 126000 292880 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 149520 301840 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 142800 301840 ) RECT ( -280 -1040 280 0 )
+ NEW Metal3 ( 119280 292880 ) RECT ( -1040 -280 0 280 )
+ NEW Metal2 ( 85680 324240 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 98000 324240 ) RECT ( -280 -1040 280 0 )
+ NEW Metal3 ( 90160 324240 ) RECT ( -1040 -280 0 280 ) ;
+ - _0349_ ( ANTENNA__0931__A2 I ) ( ANTENNA__0933__A2 I ) ( ANTENNA__0936__A1 I ) ( ANTENNA__0939__A1 I ) ( ANTENNA__0942__A1 I ) ( ANTENNA__0945__A1 I ) ( ANTENNA__0947__A1 I )
+ ( ANTENNA__0950__A1 I ) ( ANTENNA__0966__A1 I ) ( ANTENNA__1008__B I ) ( _1008_ B ) ( _0966_ A1 ) ( _0950_ A1 ) ( _0947_ A1 ) ( _0945_ A1 )
+ ( _0942_ A1 ) ( _0939_ A1 ) ( _0936_ A1 ) ( _0933_ A2 ) ( _0931_ A2 ) ( _0930_ Z ) + USE SIGNAL
+ + ROUTED Metal2 ( 58800 285040 ) ( * 286160 )
+ NEW Metal3 ( 58800 286160 ) ( 68880 * )
+ NEW Metal2 ( 68880 184240 ) ( * 197680 )
+ NEW Metal3 ( 68880 184240 ) ( 81200 * )
+ NEW Metal2 ( 81200 184240 ) ( * 189840 )
+ NEW Metal2 ( 65520 177520 ) ( * 184240 )
+ NEW Metal3 ( 65520 184240 ) ( 68880 * )
+ NEW Metal3 ( 58800 175280 ) ( 65520 * )
+ NEW Metal2 ( 65520 175280 ) ( * 177520 )
+ NEW Metal2 ( 81200 170800 ) ( * 184240 )
+ NEW Metal2 ( 58800 162960 ) ( 59920 * )
+ NEW Metal2 ( 58800 162960 ) ( * 175280 )
+ NEW Metal2 ( 68880 161840 ) ( * 175280 )
+ NEW Metal3 ( 65520 175280 ) ( 68880 * )
+ NEW Metal2 ( 98000 286160 ) ( * 292880 )
+ NEW Metal2 ( 99120 264880 ) ( * 286160 )
+ NEW Metal2 ( 98000 286160 ) ( 99120 * )
+ NEW Metal2 ( 106960 255920 ) ( * 264880 )
+ NEW Metal3 ( 99120 264880 ) ( 106960 * )
+ NEW Metal2 ( 112560 208880 ) ( 113680 * )
+ NEW Metal2 ( 113680 208880 ) ( * 227920 )
+ NEW Metal2 ( 112560 227920 ) ( 113680 * )
+ NEW Metal2 ( 112560 227920 ) ( * 252560 )
+ NEW Metal3 ( 106960 252560 ) ( 112560 * )
+ NEW Metal2 ( 106960 252560 ) ( * 255920 )
+ NEW Metal3 ( 113680 210000 ) ( 121520 * )
+ NEW Metal3 ( 68880 286160 ) ( 98000 * )
+ NEW Metal2 ( 117040 201600 ) ( * 210000 )
+ NEW Metal2 ( 118160 184240 ) ( * 201600 )
+ NEW Metal2 ( 117040 201600 ) ( 118160 * )
+ NEW Metal3 ( 118160 184240 ) ( 124880 * )
+ NEW Metal2 ( 117040 168560 ) ( 118160 * )
+ NEW Metal2 ( 118160 168560 ) ( * 184240 )
+ NEW Metal3 ( 110320 168560 ) ( 117040 * )
+ NEW Metal3 ( 96880 169680 ) ( 110320 * )
+ NEW Metal3 ( 110320 168560 ) ( * 169680 )
+ NEW Metal2 ( 85680 168560 ) ( * 169680 )
+ NEW Metal3 ( 85680 169680 ) ( 96880 * )
+ NEW Metal3 ( 85680 169680 ) ( * 170800 )
+ NEW Metal2 ( 99120 155120 ) ( * 169680 )
+ NEW Metal2 ( 104720 154000 ) ( * 155120 )
+ NEW Metal2 ( 99120 155120 ) ( 104720 * )
+ NEW Metal3 ( 81200 170800 ) ( 85680 * )
+ NEW Metal1 ( 68880 286160 ) Via1_VV
+ NEW Metal2 ( 68880 286160 ) Via2_VH
+ NEW Metal1 ( 58800 285040 ) Via1_VV
+ NEW Metal2 ( 58800 286160 ) Via2_VH
+ NEW Metal1 ( 68880 197680 ) Via1_VV
+ NEW Metal2 ( 68880 184240 ) Via2_VH
+ NEW Metal2 ( 81200 184240 ) Via2_VH
+ NEW Metal1 ( 81200 189840 ) Via1_VV
+ NEW Metal1 ( 65520 177520 ) Via1_VV
+ NEW Metal2 ( 65520 184240 ) Via2_VH
+ NEW Metal1 ( 58800 175280 ) Via1_VV
+ NEW Metal2 ( 58800 175280 ) Via2_VH
+ NEW Metal2 ( 65520 175280 ) Via2_VH
+ NEW Metal2 ( 81200 170800 ) Via2_VH
+ NEW Metal1 ( 59920 162960 ) Via1_VV
+ NEW Metal1 ( 68880 161840 ) Via1_VV
+ NEW Metal2 ( 68880 175280 ) Via2_VH
+ NEW Metal1 ( 98000 292880 ) Via1_VV
+ NEW Metal2 ( 98000 286160 ) Via2_VH
+ NEW Metal1 ( 99120 264880 ) Via1_VV
+ NEW Metal1 ( 106960 255920 ) Via1_VV
+ NEW Metal2 ( 106960 264880 ) Via2_VH
+ NEW Metal2 ( 99120 264880 ) Via2_VH
+ NEW Metal1 ( 112560 208880 ) Via1_VV
+ NEW Metal2 ( 112560 252560 ) Via2_VH
+ NEW Metal2 ( 106960 252560 ) Via2_VH
+ NEW Metal1 ( 121520 210000 ) Via1_VV
+ NEW Metal2 ( 121520 210000 ) Via2_VH
+ NEW Metal2 ( 113680 210000 ) Via2_VH
+ NEW Metal2 ( 117040 210000 ) Via2_VH
+ NEW Metal1 ( 118160 184240 ) Via1_VV
+ NEW Metal1 ( 124880 184240 ) Via1_VV
+ NEW Metal2 ( 124880 184240 ) Via2_VH
+ NEW Metal2 ( 118160 184240 ) Via2_VH
+ NEW Metal1 ( 117040 168560 ) Via1_VV
+ NEW Metal1 ( 110320 168560 ) Via1_VV
+ NEW Metal2 ( 110320 168560 ) Via2_VH
+ NEW Metal2 ( 117040 168560 ) Via2_VH
+ NEW Metal1 ( 96880 169680 ) Via1_VV
+ NEW Metal2 ( 96880 169680 ) Via2_VH
+ NEW Metal1 ( 85680 168560 ) Via1_VV
+ NEW Metal2 ( 85680 169680 ) Via2_VH
+ NEW Metal1 ( 99120 155120 ) Via1_VV
+ NEW Metal2 ( 99120 169680 ) Via2_VH
+ NEW Metal1 ( 104720 154000 ) Via1_VV
+ NEW Metal2 ( 68880 286160 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 58800 175280 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 99120 264880 ) RECT ( -280 -1040 280 0 )
+ NEW Metal2 ( 121520 210000 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 113680 210000 ) RECT ( -280 -1040 280 0 )
+ NEW Metal3 ( 117040 210000 ) RECT ( -1040 -280 0 280 )
+ NEW Metal2 ( 124880 184240 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 118160 184240 ) RECT ( -280 -1040 280 0 )
+ NEW Metal2 ( 110320 168560 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 117040 168560 ) RECT ( -280 -1040 280 0 )
+ NEW Metal2 ( 96880 169680 ) RECT ( -280 -660 280 0 )
+ NEW Metal3 ( 99120 169680 ) RECT ( -1040 -280 0 280 ) ;
+ - _0350_ ( _0935_ A2 ) ( _0934_ A2 ) ( _0933_ A3 ) ( _0932_ Z ) + USE SIGNAL
+ + ROUTED Metal2 ( 119280 194320 ) ( * 197680 )
+ NEW Metal3 ( 119280 194320 ) ( 146160 * )
+ NEW Metal2 ( 126000 178640 ) ( * 194320 )
+ NEW Metal2 ( 122640 194320 ) ( * 207760 )
+ NEW Metal1 ( 122640 207760 ) Via1_VV
+ NEW Metal1 ( 119280 197680 ) Via1_HV
+ NEW Metal2 ( 119280 194320 ) Via2_VH
+ NEW Metal1 ( 146160 194320 ) Via1_VV
+ NEW Metal2 ( 146160 194320 ) Via2_VH
+ NEW Metal2 ( 122640 194320 ) Via2_VH
+ NEW Metal1 ( 126000 178640 ) Via1_VV
+ NEW Metal2 ( 126000 194320 ) Via2_VH
+ NEW Metal2 ( 146160 194320 ) RECT ( -280 -660 280 0 )
+ NEW Metal3 ( 122640 194320 ) RECT ( -1040 -280 0 280 )
+ NEW Metal3 ( 126000 194320 ) RECT ( -1040 -280 0 280 ) ;
+ - _0351_ ( _0938_ A2 ) ( _0936_ A2 ) ( _0934_ Z ) + USE SIGNAL
+ + ROUTED Metal2 ( 127120 178640 ) ( 129360 * )
+ NEW Metal2 ( 127120 178640 ) ( * 182000 )
+ NEW Metal3 ( 129360 178640 ) ( 137200 * )
+ NEW Metal1 ( 129360 178640 ) Via1_HV
+ NEW Metal1 ( 127120 182000 ) Via1_VV
+ NEW Metal1 ( 137200 178640 ) Via1_VV
+ NEW Metal2 ( 137200 178640 ) Via2_VH
+ NEW Metal2 ( 129360 178640 ) Via2_VH
+ NEW Metal2 ( 137200 178640 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 129360 178640 ) RECT ( -280 -1040 280 0 ) ;
+ - _0352_ ( _0936_ A3 ) ( _0935_ ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 129360 184240 ) ( * 189840 )
+ NEW Metal3 ( 129360 189840 ) ( 147280 * )
+ NEW Metal1 ( 129360 184240 ) Via1_HV
+ NEW Metal2 ( 129360 189840 ) Via2_VH
+ NEW Metal1 ( 147280 189840 ) Via1_VV
+ NEW Metal2 ( 147280 189840 ) Via2_VH
+ NEW Metal2 ( 147280 189840 ) RECT ( -280 -660 280 0 ) ;
+ - _0353_ ( _0949_ A4 ) ( _0941_ A2 ) ( _0940_ A2 ) ( _0939_ A2 ) ( _0937_ Z ) + USE SIGNAL
+ + ROUTED Metal2 ( 83440 178640 ) ( * 199920 )
+ NEW Metal2 ( 104720 178640 ) ( * 179760 )
+ NEW Metal3 ( 104720 179760 ) ( 117040 * )
+ NEW Metal2 ( 117040 179760 ) ( * 189840 )
+ NEW Metal2 ( 93520 178640 ) ( * 179760 )
+ NEW Metal3 ( 93520 179760 ) ( 104720 * )
+ NEW Metal3 ( 93520 178640 ) ( * 179760 )
+ NEW Metal2 ( 119280 167440 ) ( * 178640 )
+ NEW Metal3 ( 119280 178640 ) ( * 179760 )
+ NEW Metal3 ( 117040 179760 ) ( 119280 * )
+ NEW Metal3 ( 83440 178640 ) ( 93520 * )
+ NEW Metal1 ( 83440 199920 ) Via1_HV
+ NEW Metal2 ( 83440 178640 ) Via2_VH
+ NEW Metal1 ( 104720 178640 ) Via1_VV
+ NEW Metal2 ( 104720 179760 ) Via2_VH
+ NEW Metal2 ( 117040 179760 ) Via2_VH
+ NEW Metal1 ( 117040 189840 ) Via1_VV
+ NEW Metal1 ( 93520 178640 ) Via1_VV
+ NEW Metal2 ( 93520 179760 ) Via2_VH
+ NEW Metal1 ( 119280 167440 ) Via1_VV
+ NEW Metal2 ( 119280 178640 ) Via2_VH ;
+ - _0354_ ( _0939_ A3 ) ( _0938_ ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 121520 168560 ) ( * 174160 )
+ NEW Metal3 ( 121520 174160 ) ( 138320 * )
+ NEW Metal1 ( 121520 168560 ) Via1_HV
+ NEW Metal2 ( 121520 174160 ) Via2_VH
+ NEW Metal1 ( 138320 174160 ) Via1_VV
+ NEW Metal2 ( 138320 174160 ) Via2_VH
+ NEW Metal2 ( 138320 174160 ) RECT ( -280 -660 280 0 ) ;
+ - _0355_ ( _0944_ A2 ) ( _0943_ A2 ) ( _0942_ A2 ) ( _0940_ Z ) + USE SIGNAL
+ + ROUTED Metal3 ( 67760 166320 ) ( 78960 * )
+ NEW Metal2 ( 87920 168560 ) ( * 174160 )
+ NEW Metal2 ( 87920 174160 ) ( 90160 * )
+ NEW Metal2 ( 87920 166320 ) ( * 168560 )
+ NEW Metal3 ( 78960 166320 ) ( 87920 * )
+ NEW Metal1 ( 78960 166320 ) Via1_VV
+ NEW Metal2 ( 78960 166320 ) Via2_VH
+ NEW Metal1 ( 67760 166320 ) Via1_VV
+ NEW Metal2 ( 67760 166320 ) Via2_VH
+ NEW Metal1 ( 87920 168560 ) Via1_VV
+ NEW Metal1 ( 90160 174160 ) Via1_HV
+ NEW Metal2 ( 87920 166320 ) Via2_VH
+ NEW Metal2 ( 78960 166320 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 67760 166320 ) RECT ( -280 -660 280 0 ) ;
+ - _0356_ ( _0942_ A3 ) ( _0941_ ZN ) + USE SIGNAL
+ + ROUTED Metal3 ( 90160 168560 ) ( 103600 * )
+ NEW Metal2 ( 103600 168560 ) ( * 174160 )
+ NEW Metal1 ( 90160 168560 ) Via1_HV
+ NEW Metal2 ( 90160 168560 ) Via2_VH
+ NEW Metal2 ( 103600 168560 ) Via2_VH
+ NEW Metal1 ( 103600 174160 ) Via1_VV
+ NEW Metal2 ( 90160 168560 ) RECT ( -280 -660 280 0 ) ;
+ - _0357_ ( _0948_ A2 ) ( _0946_ A2 ) ( _0945_ A2 ) ( _0943_ Z ) + USE SIGNAL
+ + ROUTED Metal2 ( 59920 183120 ) ( * 190960 )
+ NEW Metal2 ( 64400 170800 ) ( * 175280 )
+ NEW Metal2 ( 59920 175280 ) ( 64400 * )
+ NEW Metal2 ( 59920 175280 ) ( * 183120 )
+ NEW Metal2 ( 62160 162960 ) ( * 175280 )
+ NEW Metal1 ( 59920 183120 ) Via1_HV
+ NEW Metal1 ( 59920 190960 ) Via1_VV
+ NEW Metal1 ( 64400 170800 ) Via1_HV
+ NEW Metal1 ( 62160 162960 ) Via1_VV ;
+ - _0358_ ( _0945_ A3 ) ( _0944_ ZN ) + USE SIGNAL
+ + ROUTED Metal3 ( 63280 162960 ) ( 75600 * )
+ NEW Metal2 ( 75600 162960 ) ( * 166320 )
+ NEW Metal1 ( 63280 162960 ) Via1_VV
+ NEW Metal2 ( 63280 162960 ) Via2_VH
+ NEW Metal2 ( 75600 162960 ) Via2_VH
+ NEW Metal1 ( 75600 166320 ) Via1_VV
+ NEW Metal2 ( 63280 162960 ) RECT ( -280 -660 280 0 ) ;
+ - _0359_ ( _0947_ A2 ) ( _0946_ ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 61040 178640 ) ( * 182000 )
+ NEW Metal1 ( 61040 178640 ) Via1_VV
+ NEW Metal1 ( 61040 182000 ) Via1_HV ;
+ - _0360_ ( _0950_ A2 ) ( _0948_ ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 61040 193200 ) ( * 197680 )
+ NEW Metal3 ( 61040 197680 ) ( 71120 * )
+ NEW Metal1 ( 61040 193200 ) Via1_VV
+ NEW Metal2 ( 61040 197680 ) Via2_VH
+ NEW Metal1 ( 71120 197680 ) Via1_VV
+ NEW Metal2 ( 71120 197680 ) Via2_VH
+ NEW Metal2 ( 71120 197680 ) RECT ( -280 -660 280 0 ) ;
+ - _0361_ ( _0962_ A4 ) ( _0953_ A2 ) ( _0952_ A2 ) ( _0950_ A3 ) ( _0949_ Z ) + USE SIGNAL
+ + ROUTED Metal2 ( 72240 231280 ) ( * 232400 )
+ NEW Metal2 ( 83440 216720 ) ( * 232400 )
+ NEW Metal2 ( 80080 202160 ) ( 82320 * )
+ NEW Metal2 ( 82320 202160 ) ( * 216720 )
+ NEW Metal2 ( 82320 216720 ) ( 83440 * )
+ NEW Metal2 ( 80080 201600 ) ( * 202160 )
+ NEW Metal2 ( 73360 199920 ) ( * 201600 )
+ NEW Metal2 ( 73360 201600 ) ( 80080 * )
+ NEW Metal3 ( 72240 232400 ) ( 103600 * )
+ NEW Metal1 ( 72240 231280 ) Via1_VV
+ NEW Metal2 ( 72240 232400 ) Via2_VH
+ NEW Metal1 ( 83440 216720 ) Via1_VV
+ NEW Metal2 ( 83440 232400 ) Via2_VH
+ NEW Metal1 ( 80080 202160 ) Via1_VV
+ NEW Metal1 ( 73360 199920 ) Via1_HV
+ NEW Metal1 ( 103600 232400 ) Via1_HV
+ NEW Metal2 ( 103600 232400 ) Via2_VH
+ NEW Metal3 ( 83440 232400 ) RECT ( -1040 -280 0 280 )
+ NEW Metal2 ( 103600 232400 ) RECT ( -280 -660 280 0 ) ;
+ - _0362_ ( ANTENNA__0954__A1 I ) ( ANTENNA__0957__A1 I ) ( ANTENNA__0960__A1 I ) ( ANTENNA__0964__A1 I ) ( ANTENNA__0970__A1 I ) ( ANTENNA__0973__A1 I ) ( ANTENNA__0978__A1 I )
+ ( ANTENNA__0981__A1 I ) ( ANTENNA__0987__A1 I ) ( ANTENNA__0996__A1 I ) ( _0996_ A1 ) ( _0987_ A1 ) ( _0981_ A1 ) ( _0978_ A1 ) ( _0973_ A1 )
+ ( _0970_ A1 ) ( _0964_ A1 ) ( _0960_ A1 ) ( _0957_ A1 ) ( _0954_ A1 ) ( _0951_ Z ) + USE SIGNAL
+ + ROUTED Metal2 ( 66640 246960 ) ( * 251440 )
+ NEW Metal2 ( 66640 240240 ) ( 67760 * )
+ NEW Metal2 ( 66640 240240 ) ( * 246960 )
+ NEW Metal3 ( 67760 240240 ) ( 73360 * )
+ NEW Metal3 ( 54320 244720 ) ( 66640 * )
+ NEW Metal2 ( 54320 233520 ) ( 55440 * )
+ NEW Metal2 ( 54320 233520 ) ( * 244720 )
+ NEW Metal3 ( 46480 231280 ) ( 54320 * )
+ NEW Metal2 ( 54320 231280 ) ( * 233520 )
+ NEW Metal2 ( 73360 215600 ) ( * 240240 )
+ NEW Metal2 ( 77840 208880 ) ( * 213360 )
+ NEW Metal2 ( 73360 213360 ) ( 77840 * )
+ NEW Metal2 ( 73360 213360 ) ( * 215600 )
+ NEW Metal2 ( 62160 347760 ) ( * 348880 )
+ NEW Metal3 ( 62160 347760 ) ( 67760 * )
+ NEW Metal2 ( 113680 239120 ) ( 114800 * )
+ NEW Metal2 ( 113680 239120 ) ( * 251440 )
+ NEW Metal3 ( 114800 239120 ) ( 124880 * )
+ NEW Metal2 ( 130480 251440 ) ( * 276080 )
+ NEW Metal3 ( 113680 251440 ) ( 130480 * )
+ NEW Metal2 ( 126000 269360 ) ( * 283920 )
+ NEW Metal2 ( 126000 269360 ) ( 130480 * )
+ NEW Metal2 ( 95760 301840 ) ( * 302960 )
+ NEW Metal3 ( 95760 302960 ) ( 124880 * )
+ NEW Metal2 ( 124880 283920 ) ( * 302960 )
+ NEW Metal2 ( 124880 283920 ) ( 126000 * )
+ NEW Metal2 ( 102480 301840 ) ( * 302960 )
+ NEW Metal2 ( 101360 302960 ) ( 102480 * )
+ NEW Metal3 ( 124880 302960 ) ( 128240 * )
+ NEW Metal3 ( 66640 251440 ) ( 113680 * )
+ NEW Metal2 ( 100240 351120 ) ( 101360 * )
+ NEW Metal2 ( 101360 351120 ) ( * 355600 )
+ NEW Metal2 ( 101360 355600 ) ( 104720 * )
+ NEW Metal2 ( 95760 334320 ) ( * 351120 )
+ NEW Metal3 ( 95760 351120 ) ( 100240 * )
+ NEW Metal2 ( 93520 347760 ) ( 95760 * )
+ NEW Metal3 ( 118160 330960 ) ( 128240 * )
+ NEW Metal3 ( 67760 347760 ) ( 93520 * )
+ NEW Metal2 ( 95760 302960 ) ( * 334320 )
+ NEW Metal2 ( 128240 302960 ) ( * 333200 )
+ NEW Metal1 ( 66640 246960 ) Via1_VV
+ NEW Metal2 ( 66640 251440 ) Via2_VH
+ NEW Metal1 ( 67760 240240 ) Via1_VV
+ NEW Metal1 ( 73360 240240 ) Via1_VV
+ NEW Metal2 ( 73360 240240 ) Via2_VH
+ NEW Metal2 ( 67760 240240 ) Via2_VH
+ NEW Metal1 ( 54320 244720 ) Via1_VV
+ NEW Metal2 ( 54320 244720 ) Via2_VH
+ NEW Metal2 ( 66640 244720 ) Via2_VH
+ NEW Metal1 ( 55440 233520 ) Via1_VV
+ NEW Metal1 ( 46480 231280 ) Via1_VV
+ NEW Metal2 ( 46480 231280 ) Via2_VH
+ NEW Metal2 ( 54320 231280 ) Via2_VH
+ NEW Metal1 ( 73360 215600 ) Via1_VV
+ NEW Metal1 ( 77840 208880 ) Via1_VV
+ NEW Metal1 ( 67760 347760 ) Via1_VV
+ NEW Metal2 ( 67760 347760 ) Via2_VH
+ NEW Metal1 ( 62160 348880 ) Via1_VV
+ NEW Metal2 ( 62160 347760 ) Via2_VH
+ NEW Metal1 ( 114800 239120 ) Via1_VV
+ NEW Metal2 ( 113680 251440 ) Via2_VH
+ NEW Metal1 ( 124880 239120 ) Via1_VV
+ NEW Metal2 ( 124880 239120 ) Via2_VH
+ NEW Metal2 ( 114800 239120 ) Via2_VH
+ NEW Metal1 ( 130480 276080 ) Via1_VV
+ NEW Metal2 ( 130480 251440 ) Via2_VH
+ NEW Metal1 ( 126000 283920 ) Via1_VV
+ NEW Metal1 ( 95760 301840 ) Via1_VV
+ NEW Metal2 ( 95760 302960 ) Via2_VH
+ NEW Metal2 ( 124880 302960 ) Via2_VH
+ NEW Metal1 ( 102480 301840 ) Via1_VV
+ NEW Metal2 ( 101360 302960 ) Via2_VH
+ NEW Metal2 ( 128240 302960 ) Via2_VH
+ NEW Metal1 ( 100240 351120 ) Via1_VV
+ NEW Metal1 ( 104720 355600 ) Via1_VV
+ NEW Metal1 ( 95760 334320 ) Via1_VV
+ NEW Metal2 ( 95760 351120 ) Via2_VH
+ NEW Metal2 ( 100240 351120 ) Via2_VH
+ NEW Metal2 ( 93520 347760 ) Via2_VH
+ NEW Metal1 ( 128240 333200 ) Via1_VV
+ NEW Metal1 ( 118160 330960 ) Via1_VV
+ NEW Metal2 ( 118160 330960 ) Via2_VH
+ NEW Metal2 ( 128240 330960 ) Via2_VH
+ NEW Metal2 ( 73360 240240 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 67760 240240 ) RECT ( -280 -1040 280 0 )
+ NEW Metal2 ( 54320 244720 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 66640 244720 ) RECT ( -280 -1040 280 0 )
+ NEW Metal2 ( 46480 231280 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 67760 347760 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 124880 239120 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 114800 239120 ) RECT ( -280 -1040 280 0 )
+ NEW Metal3 ( 101360 302960 ) RECT ( -1040 -280 0 280 )
+ NEW Metal2 ( 100240 351120 ) RECT ( -280 -1040 280 0 )
+ NEW Metal2 ( 118160 330960 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 128240 330960 ) RECT ( -280 -1040 280 0 ) ;
+ - _0363_ ( _0954_ A2 ) ( _0952_ ZN ) + USE SIGNAL
+ + ROUTED Metal3 ( 71120 213360 ) ( 80080 * )
+ NEW Metal1 ( 71120 213360 ) Via1_VV
+ NEW Metal2 ( 71120 213360 ) Via2_VH
+ NEW Metal1 ( 80080 213360 ) Via1_VV
+ NEW Metal2 ( 80080 213360 ) Via2_VH
+ NEW Metal2 ( 71120 213360 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 80080 213360 ) RECT ( -280 -660 280 0 ) ;
+ - _0364_ ( _0956_ A2 ) ( _0955_ A2 ) ( _0954_ A3 ) ( _0953_ Z ) + USE SIGNAL
+ + ROUTED Metal2 ( 61040 225680 ) ( * 229040 )
+ NEW Metal3 ( 61040 229040 ) ( 68880 * )
+ NEW Metal2 ( 68880 215600 ) ( * 229040 )
+ NEW Metal2 ( 50960 215600 ) ( * 229040 )
+ NEW Metal3 ( 50960 229040 ) ( 61040 * )
+ NEW Metal1 ( 61040 225680 ) Via1_VV
+ NEW Metal2 ( 61040 229040 ) Via2_VH
+ NEW Metal1 ( 68880 229040 ) Via1_HV
+ NEW Metal2 ( 68880 229040 ) Via2_VH
+ NEW Metal1 ( 68880 215600 ) Via1_HV
+ NEW Metal1 ( 50960 215600 ) Via1_VV
+ NEW Metal2 ( 50960 229040 ) Via2_VH
+ NEW Metal2 ( 68880 229040 ) RECT ( -280 -660 280 0 ) ;
+ - _0365_ ( _0957_ A2 ) ( _0955_ ZN ) + USE SIGNAL
+ + ROUTED Metal3 ( 48720 225680 ) ( 57680 * )
+ NEW Metal2 ( 48720 225680 ) ( * 229040 )
+ NEW Metal1 ( 57680 225680 ) Via1_VV
+ NEW Metal2 ( 57680 225680 ) Via2_VH
+ NEW Metal2 ( 48720 225680 ) Via2_VH
+ NEW Metal1 ( 48720 229040 ) Via1_VV
+ NEW Metal2 ( 57680 225680 ) RECT ( -280 -660 280 0 ) ;
+ - _0366_ ( _0959_ A2 ) ( _0958_ A2 ) ( _0957_ A3 ) ( _0956_ Z ) + USE SIGNAL
+ + ROUTED Metal3 ( 46480 239120 ) ( 59920 * )
+ NEW Metal2 ( 49840 231280 ) ( 50960 * )
+ NEW Metal2 ( 49840 231280 ) ( * 239120 )
+ NEW Metal2 ( 47600 216720 ) ( 49840 * )
+ NEW Metal2 ( 49840 216720 ) ( * 231280 )
+ NEW Metal1 ( 46480 239120 ) Via1_VV
+ NEW Metal2 ( 46480 239120 ) Via2_VH
+ NEW Metal1 ( 59920 239120 ) Via1_VV
+ NEW Metal2 ( 59920 239120 ) Via2_VH
+ NEW Metal1 ( 50960 231280 ) Via1_HV
+ NEW Metal2 ( 49840 239120 ) Via2_VH
+ NEW Metal1 ( 47600 216720 ) Via1_HV
+ NEW Metal2 ( 46480 239120 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 59920 239120 ) RECT ( -280 -660 280 0 )
+ NEW Metal3 ( 49840 239120 ) RECT ( -1040 -280 0 280 ) ;
+ - _0367_ ( _0960_ A2 ) ( _0958_ ZN ) + USE SIGNAL
+ + ROUTED Metal3 ( 49840 241360 ) ( 56560 * )
+ NEW Metal2 ( 56560 241360 ) ( * 244720 )
+ NEW Metal1 ( 49840 241360 ) Via1_VV
+ NEW Metal2 ( 49840 241360 ) Via2_VH
+ NEW Metal2 ( 56560 241360 ) Via2_VH
+ NEW Metal1 ( 56560 244720 ) Via1_VV
+ NEW Metal2 ( 49840 241360 ) RECT ( -280 -660 280 0 ) ;
+ - _0368_ ( _0961_ A2 ) ( _0960_ A3 ) ( _0959_ Z ) + USE SIGNAL
+ + ROUTED Metal2 ( 58800 246960 ) ( * 260400 )
+ NEW Metal2 ( 58800 260400 ) ( 65520 * )
+ NEW Metal2 ( 63280 241360 ) ( * 260400 )
+ NEW Metal1 ( 58800 246960 ) Via1_HV
+ NEW Metal1 ( 65520 260400 ) Via1_VV
+ NEW Metal1 ( 63280 241360 ) Via1_HV ;
+ - _0369_ ( _0964_ A2 ) ( _0961_ ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 68880 246960 ) ( * 260400 )
+ NEW Metal1 ( 68880 246960 ) Via1_VV
+ NEW Metal1 ( 68880 260400 ) Via1_VV ;
+ - _0370_ ( _0969_ A4 ) ( _0963_ A2 ) ( _0962_ ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 128240 230160 ) ( * 248080 )
+ NEW Metal3 ( 90160 244720 ) ( 128240 * )
+ NEW Metal1 ( 128240 230160 ) Via1_HV
+ NEW Metal1 ( 128240 248080 ) Via1_VV
+ NEW Metal1 ( 90160 244720 ) Via1_VV
+ NEW Metal2 ( 90160 244720 ) Via2_VH
+ NEW Metal2 ( 128240 244720 ) Via2_VH
+ NEW Metal2 ( 90160 244720 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 128240 244720 ) RECT ( -280 -1040 280 0 ) ;
+ - _0371_ ( _0967_ A2 ) ( _0965_ A2 ) ( _0964_ A3 ) ( _0963_ ZN ) + USE SIGNAL
+ + ROUTED Metal3 ( 99120 255920 ) ( 111440 * )
+ NEW Metal2 ( 111440 254800 ) ( * 255920 )
+ NEW Metal2 ( 86800 245840 ) ( * 250320 )
+ NEW Metal2 ( 86800 250320 ) ( 87920 * )
+ NEW Metal2 ( 87920 250320 ) ( * 255920 )
+ NEW Metal3 ( 87920 255920 ) ( 99120 * )
+ NEW Metal3 ( 70000 245840 ) ( 86800 * )
+ NEW Metal1 ( 70000 245840 ) Via1_VV
+ NEW Metal2 ( 70000 245840 ) Via2_VH
+ NEW Metal1 ( 99120 255920 ) Via1_HV
+ NEW Metal2 ( 99120 255920 ) Via2_VH
+ NEW Metal2 ( 111440 255920 ) Via2_VH
+ NEW Metal1 ( 111440 254800 ) Via1_VV
+ NEW Metal1 ( 86800 245840 ) Via1_HV
+ NEW Metal2 ( 87920 255920 ) Via2_VH
+ NEW Metal2 ( 86800 245840 ) Via2_VH
+ NEW Metal2 ( 70000 245840 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 99120 255920 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 86800 245840 ) RECT ( -280 -1040 280 0 ) ;
+ - _0372_ ( _0966_ A2 ) ( _0965_ Z ) + USE SIGNAL
+ + ROUTED Metal2 ( 101360 255920 ) ( 102480 * )
+ NEW Metal2 ( 101360 255920 ) ( * 260400 )
+ NEW Metal1 ( 102480 255920 ) Via1_VV
+ NEW Metal1 ( 101360 260400 ) Via1_VV ;
+ - _0373_ ( _0970_ A2 ) ( _0967_ ZN ) + USE SIGNAL
+ + ROUTED Metal3 ( 114800 241360 ) ( 122640 * )
+ NEW Metal2 ( 114800 241360 ) ( * 252560 )
+ NEW Metal1 ( 122640 241360 ) Via1_VV
+ NEW Metal2 ( 122640 241360 ) Via2_VH
+ NEW Metal2 ( 114800 241360 ) Via2_VH
+ NEW Metal1 ( 114800 252560 ) Via1_VV
+ NEW Metal2 ( 122640 241360 ) RECT ( -280 -660 280 0 ) ;
+ - _0374_ ( _0969_ A3 ) ( _0968_ ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 110320 241360 ) ( * 246960 )
+ NEW Metal3 ( 110320 246960 ) ( 122640 * )
+ NEW Metal1 ( 110320 241360 ) Via1_VV
+ NEW Metal2 ( 110320 246960 ) Via2_VH
+ NEW Metal1 ( 122640 246960 ) Via1_VV
+ NEW Metal2 ( 122640 246960 ) Via2_VH
+ NEW Metal2 ( 122640 246960 ) RECT ( -280 -660 280 0 ) ;
+ - _0375_ ( _0977_ A4 ) ( _0972_ A2 ) ( _0971_ A2 ) ( _0970_ A3 ) ( _0969_ ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 121520 241360 ) ( * 245840 )
+ NEW Metal2 ( 120400 245840 ) ( * 276080 )
+ NEW Metal2 ( 120400 245840 ) ( 121520 * )
+ NEW Metal3 ( 120400 276080 ) ( 140560 * )
+ NEW Metal2 ( 120400 276080 ) ( * 301840 )
+ NEW Metal1 ( 121520 241360 ) Via1_VV
+ NEW Metal1 ( 121520 245840 ) Via1_VV
+ NEW Metal1 ( 120400 276080 ) Via1_VV
+ NEW Metal1 ( 140560 276080 ) Via1_VV
+ NEW Metal2 ( 140560 276080 ) Via2_VH
+ NEW Metal2 ( 120400 276080 ) Via2_VH
+ NEW Metal1 ( 120400 301840 ) Via1_VV
+ NEW Metal2 ( 140560 276080 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 120400 276080 ) RECT ( -280 -1040 280 0 ) ;
+ - _0376_ ( _0973_ A2 ) ( _0971_ ZN ) + USE SIGNAL
+ + ROUTED Metal3 ( 132720 277200 ) ( 141680 * )
+ NEW Metal1 ( 141680 277200 ) Via1_VV
+ NEW Metal2 ( 141680 277200 ) Via2_VH
+ NEW Metal1 ( 132720 277200 ) Via1_VV
+ NEW Metal2 ( 132720 277200 ) Via2_VH
+ NEW Metal2 ( 141680 277200 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 132720 277200 ) RECT ( -280 -660 280 0 ) ;
+ - _0377_ ( _0976_ A2 ) ( _0975_ A2 ) ( _0974_ A2 ) ( _0973_ A3 ) ( _0972_ Z ) + USE SIGNAL
+ + ROUTED Metal2 ( 134960 295120 ) ( * 300720 )
+ NEW Metal2 ( 134960 300720 ) ( 137200 * )
+ NEW Metal3 ( 121520 294000 ) ( 134960 * )
+ NEW Metal2 ( 134960 294000 ) ( * 295120 )
+ NEW Metal2 ( 122640 280560 ) ( 123760 * )
+ NEW Metal2 ( 122640 280560 ) ( * 294000 )
+ NEW Metal2 ( 121520 294000 ) ( 122640 * )
+ NEW Metal2 ( 134960 278320 ) ( * 294000 )
+ NEW Metal1 ( 134960 295120 ) Via1_VV
+ NEW Metal1 ( 137200 300720 ) Via1_VV
+ NEW Metal1 ( 121520 294000 ) Via1_VV
+ NEW Metal2 ( 121520 294000 ) Via2_VH
+ NEW Metal2 ( 134960 294000 ) Via2_VH
+ NEW Metal1 ( 123760 280560 ) Via1_HV
+ NEW Metal1 ( 134960 278320 ) Via1_HV
+ NEW Metal2 ( 121520 294000 ) RECT ( -280 -660 280 0 ) ;
+ - _0378_ ( _0975_ B ) ( _0974_ ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 138320 292880 ) ( * 295120 )
+ NEW Metal2 ( 138320 295120 ) ( 140560 * )
+ NEW Metal2 ( 140560 295120 ) ( * 301840 )
+ NEW Metal2 ( 140560 301840 ) ( 141680 * )
+ NEW Metal1 ( 138320 292880 ) Via1_HV
+ NEW Metal1 ( 141680 301840 ) Via1_VV ;
+ - _0379_ ( _0978_ A2 ) ( _0976_ ZN ) + USE SIGNAL
+ + ROUTED Metal3 ( 104720 296240 ) ( 118160 * )
+ NEW Metal2 ( 104720 296240 ) ( * 301840 )
+ NEW Metal1 ( 118160 296240 ) Via1_VV
+ NEW Metal2 ( 118160 296240 ) Via2_VH
+ NEW Metal2 ( 104720 296240 ) Via2_VH
+ NEW Metal1 ( 104720 301840 ) Via1_VV
+ NEW Metal2 ( 118160 296240 ) RECT ( -280 -660 280 0 ) ;
+ - _0380_ ( _0986_ A4 ) ( _0980_ A2 ) ( _0979_ A2 ) ( _0978_ A3 ) ( _0977_ Z ) + USE SIGNAL
+ + ROUTED Metal2 ( 106960 301840 ) ( 108080 * )
+ NEW Metal3 ( 108080 301840 ) ( 122640 * )
+ NEW Metal2 ( 126000 301840 ) ( * 316400 )
+ NEW Metal3 ( 122640 301840 ) ( 126000 * )
+ NEW Metal2 ( 108080 325360 ) ( * 326480 )
+ NEW Metal2 ( 105840 326480 ) ( 108080 * )
+ NEW Metal2 ( 105840 326480 ) ( * 333200 )
+ NEW Metal2 ( 104720 333200 ) ( 105840 * )
+ NEW Metal2 ( 108080 301840 ) ( * 325360 )
+ NEW Metal1 ( 106960 301840 ) Via1_HV
+ NEW Metal1 ( 122640 301840 ) Via1_VV
+ NEW Metal2 ( 122640 301840 ) Via2_VH
+ NEW Metal2 ( 108080 301840 ) Via2_VH
+ NEW Metal1 ( 126000 316400 ) Via1_VV
+ NEW Metal2 ( 126000 301840 ) Via2_VH
+ NEW Metal1 ( 108080 325360 ) Via1_VV
+ NEW Metal1 ( 104720 333200 ) Via1_HV
+ NEW Metal2 ( 122640 301840 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 108080 301840 ) RECT ( -280 -1040 280 0 ) ;
+ - _0381_ ( _0981_ A2 ) ( _0979_ ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 127120 318640 ) ( * 319200 )
+ NEW Metal2 ( 126000 319200 ) ( 127120 * )
+ NEW Metal2 ( 126000 319200 ) ( * 333200 )
+ NEW Metal1 ( 127120 318640 ) Via1_VV
+ NEW Metal1 ( 126000 333200 ) Via1_VV ;
+ - _0382_ ( _0985_ A2 ) ( _0983_ A2 ) ( _0982_ A2 ) ( _0981_ A3 ) ( _0980_ Z ) + USE SIGNAL
+ + ROUTED Metal2 ( 123760 327600 ) ( * 333200 )
+ NEW Metal3 ( 111440 327600 ) ( 123760 * )
+ NEW Metal2 ( 112560 327600 ) ( * 347760 )
+ NEW Metal2 ( 111440 327600 ) ( 112560 * )
+ NEW Metal2 ( 136080 346640 ) ( 137200 * )
+ NEW Metal2 ( 136080 333200 ) ( * 346640 )
+ NEW Metal3 ( 123760 333200 ) ( 136080 * )
+ NEW Metal2 ( 148400 335440 ) ( * 347760 )
+ NEW Metal3 ( 136080 335440 ) ( 148400 * )
+ NEW Metal1 ( 123760 333200 ) Via1_HV
+ NEW Metal2 ( 123760 327600 ) Via2_VH
+ NEW Metal1 ( 111440 327600 ) Via1_HV
+ NEW Metal2 ( 111440 327600 ) Via2_VH
+ NEW Metal1 ( 112560 347760 ) Via1_VV
+ NEW Metal1 ( 137200 346640 ) Via1_VV
+ NEW Metal2 ( 136080 333200 ) Via2_VH
+ NEW Metal2 ( 123760 333200 ) Via2_VH
+ NEW Metal1 ( 148400 347760 ) Via1_VV
+ NEW Metal2 ( 148400 335440 ) Via2_VH
+ NEW Metal2 ( 136080 335440 ) Via2_VH
+ NEW Metal2 ( 111440 327600 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 123760 333200 ) RECT ( -280 -1040 280 0 )
+ NEW Metal2 ( 136080 335440 ) RECT ( -280 -1040 280 0 ) ;
+ - _0383_ ( _0983_ B ) ( _0982_ ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 143920 348880 ) ( * 350000 )
+ NEW Metal2 ( 143920 350000 ) ( 149520 * )
+ NEW Metal1 ( 143920 348880 ) Via1_VV
+ NEW Metal1 ( 149520 350000 ) Via1_VV ;
+ - _0384_ ( _0984_ I ) ( _0983_ ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 137200 350000 ) ( 138320 * )
+ NEW Metal2 ( 137200 350000 ) ( * 363440 )
+ NEW Metal1 ( 138320 350000 ) Via1_VV
+ NEW Metal1 ( 137200 363440 ) Via1_VV ;
+ - _0385_ ( _0987_ A2 ) ( _0985_ ZN ) + USE SIGNAL
+ + ROUTED Metal3 ( 98000 348880 ) ( 111440 * )
+ NEW Metal1 ( 111440 348880 ) Via1_VV
+ NEW Metal2 ( 111440 348880 ) Via2_VH
+ NEW Metal1 ( 98000 348880 ) Via1_VV
+ NEW Metal2 ( 98000 348880 ) Via2_VH
+ NEW Metal2 ( 111440 348880 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 98000 348880 ) RECT ( -280 -660 280 0 ) ;
+ - _0386_ ( _0998_ A4 ) ( _0995_ A4 ) ( _0990_ A2 ) ( _0988_ A2 ) ( _0987_ A3 ) ( _0986_ Z ) + USE SIGNAL
+ + ROUTED Metal3 ( 65520 341040 ) ( 78960 * )
+ NEW Metal2 ( 65520 333200 ) ( * 341040 )
+ NEW Metal2 ( 72240 341040 ) ( * 354480 )
+ NEW Metal2 ( 76720 350000 ) ( * 362320 )
+ NEW Metal2 ( 100240 335440 ) ( * 346640 )
+ NEW Metal3 ( 95760 346640 ) ( 100240 * )
+ NEW Metal3 ( 95760 346640 ) ( * 350000 )
+ NEW Metal3 ( 72240 350000 ) ( 96880 * )
+ NEW Metal1 ( 78960 341040 ) Via1_HV
+ NEW Metal2 ( 78960 341040 ) Via2_VH
+ NEW Metal2 ( 65520 341040 ) Via2_VH
+ NEW Metal1 ( 65520 333200 ) Via1_HV
+ NEW Metal1 ( 72240 354480 ) Via1_VV
+ NEW Metal2 ( 72240 341040 ) Via2_VH
+ NEW Metal2 ( 72240 350000 ) Via2_VH
+ NEW Metal1 ( 76720 362320 ) Via1_VV
+ NEW Metal2 ( 76720 350000 ) Via2_VH
+ NEW Metal1 ( 96880 350000 ) Via1_VV
+ NEW Metal2 ( 96880 350000 ) Via2_VH
+ NEW Metal1 ( 100240 335440 ) Via1_VV
+ NEW Metal2 ( 100240 346640 ) Via2_VH
+ NEW Metal2 ( 78960 341040 ) RECT ( -280 0 280 660 )
+ NEW Metal3 ( 72240 341040 ) RECT ( -1040 -280 0 280 )
+ NEW Metal2 ( 72240 350000 ) RECT ( -280 -1040 280 0 )
+ NEW Metal3 ( 76720 350000 ) RECT ( -1040 -280 0 280 )
+ NEW Metal2 ( 96880 350000 ) RECT ( -280 -660 280 0 ) ;
+ - _0387_ ( _0994_ A2 ) ( _0993_ A2 ) ( _0992_ A2 ) ( _0991_ A1 ) ( _0988_ Z ) + USE SIGNAL
+ + ROUTED Metal2 ( 68880 358960 ) ( * 362320 )
+ NEW Metal2 ( 63280 356720 ) ( * 362320 )
+ NEW Metal3 ( 63280 362320 ) ( 68880 * )
+ NEW Metal3 ( 59920 362320 ) ( 63280 * )
+ NEW Metal2 ( 44240 362320 ) ( * 363440 )
+ NEW Metal3 ( 44240 362320 ) ( 59920 * )
+ NEW Metal3 ( 68880 362320 ) ( 84560 * )
+ NEW Metal1 ( 68880 358960 ) Via1_HV
+ NEW Metal2 ( 68880 362320 ) Via2_VH
+ NEW Metal1 ( 63280 356720 ) Via1_VV
+ NEW Metal2 ( 63280 362320 ) Via2_VH
+ NEW Metal1 ( 59920 362320 ) Via1_VV
+ NEW Metal2 ( 59920 362320 ) Via2_VH
+ NEW Metal1 ( 44240 363440 ) Via1_VV
+ NEW Metal2 ( 44240 362320 ) Via2_VH
+ NEW Metal1 ( 84560 362320 ) Via1_VV
+ NEW Metal2 ( 84560 362320 ) Via2_VH
+ NEW Metal2 ( 59920 362320 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 84560 362320 ) RECT ( -280 -660 280 0 ) ;
+ - _0388_ ( _1004_ B ) ( _1001_ A1 ) ( _0992_ B ) ( _0990_ B ) ( _0989_ ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 70000 314160 ) ( * 316400 )
+ NEW Metal3 ( 70000 314160 ) ( 80080 * )
+ NEW Metal2 ( 64400 310800 ) ( * 314160 )
+ NEW Metal3 ( 64400 314160 ) ( 70000 * )
+ NEW Metal2 ( 80080 314160 ) ( * 319200 )
+ NEW Metal2 ( 82320 319200 ) ( * 330960 )
+ NEW Metal2 ( 80080 319200 ) ( 82320 * )
+ NEW Metal2 ( 72240 356720 ) ( * 362320 )
+ NEW Metal3 ( 72240 356720 ) ( 82320 * )
+ NEW Metal2 ( 82320 330960 ) ( * 356720 )
+ NEW Metal3 ( 66640 364560 ) ( 72240 * )
+ NEW Metal2 ( 72240 362320 ) ( * 364560 )
+ NEW Metal1 ( 70000 316400 ) Via1_VV
+ NEW Metal2 ( 70000 314160 ) Via2_VH
+ NEW Metal2 ( 80080 314160 ) Via2_VH
+ NEW Metal1 ( 64400 310800 ) Via1_VV
+ NEW Metal2 ( 64400 314160 ) Via2_VH
+ NEW Metal1 ( 82320 330960 ) Via1_VV
+ NEW Metal1 ( 72240 362320 ) Via1_VV
+ NEW Metal2 ( 72240 356720 ) Via2_VH
+ NEW Metal2 ( 82320 356720 ) Via2_VH
+ NEW Metal1 ( 66640 364560 ) Via1_VV
+ NEW Metal2 ( 66640 364560 ) Via2_VH
+ NEW Metal2 ( 72240 364560 ) Via2_VH
+ NEW Metal2 ( 66640 364560 ) RECT ( -280 -660 280 0 ) ;
+ - _0389_ ( _0991_ A2 ) ( _0990_ ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 75600 364560 ) ( 77840 * )
+ NEW Metal2 ( 77840 363440 ) ( * 364560 )
+ NEW Metal2 ( 77840 363440 ) ( 82320 * )
+ NEW Metal1 ( 75600 364560 ) Via1_VV
+ NEW Metal1 ( 82320 363440 ) Via1_VV ;
+ - _0390_ ( _0993_ B ) ( _0992_ ZN ) + USE SIGNAL
+ + ROUTED Metal3 ( 49840 363440 ) ( 61040 * )
+ NEW Metal1 ( 61040 363440 ) Via1_VV
+ NEW Metal2 ( 61040 363440 ) Via2_VH
+ NEW Metal1 ( 49840 363440 ) Via1_VV
+ NEW Metal2 ( 49840 363440 ) Via2_VH
+ NEW Metal2 ( 61040 363440 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 49840 363440 ) RECT ( -280 -660 280 0 ) ;
+ - _0391_ ( _0996_ A2 ) ( _0994_ ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 59920 351120 ) ( * 358960 )
+ NEW Metal1 ( 59920 351120 ) Via1_VV
+ NEW Metal1 ( 59920 358960 ) Via1_VV ;
+ - _0392_ ( _1006_ A4 ) ( _1000_ A2 ) ( _0996_ A3 ) ( _0995_ Z ) + USE SIGNAL
+ + ROUTED Metal3 ( 49840 317520 ) ( 59920 * )
+ NEW Metal2 ( 52080 310800 ) ( * 317520 )
+ NEW Metal2 ( 61040 335440 ) ( * 348880 )
+ NEW Metal2 ( 58800 348880 ) ( 61040 * )
+ NEW Metal2 ( 59920 335440 ) ( 61040 * )
+ NEW Metal2 ( 59920 317520 ) ( * 335440 )
+ NEW Metal1 ( 49840 317520 ) Via1_VV
+ NEW Metal2 ( 49840 317520 ) Via2_VH
+ NEW Metal2 ( 59920 317520 ) Via2_VH
+ NEW Metal1 ( 52080 310800 ) Via1_VV
+ NEW Metal2 ( 52080 317520 ) Via2_VH
+ NEW Metal1 ( 61040 335440 ) Via1_VV
+ NEW Metal1 ( 58800 348880 ) Via1_VV
+ NEW Metal2 ( 49840 317520 ) RECT ( -280 -660 280 0 )
+ NEW Metal3 ( 52080 317520 ) RECT ( -1040 -280 0 280 ) ;
+ - _0393_ ( _1007_ A1 ) ( _1004_ A1 ) ( _0999_ A1 ) ( _0997_ ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 66640 310800 ) ( * 315280 )
+ NEW Metal3 ( 66640 315280 ) ( 77840 * )
+ NEW Metal2 ( 68880 301840 ) ( * 310800 )
+ NEW Metal2 ( 66640 310800 ) ( 68880 * )
+ NEW Metal2 ( 64400 296240 ) ( * 299600 )
+ NEW Metal2 ( 64400 299600 ) ( 66640 * )
+ NEW Metal2 ( 66640 299600 ) ( * 301840 )
+ NEW Metal2 ( 66640 301840 ) ( 68880 * )
+ NEW Metal1 ( 66640 310800 ) Via1_VV
+ NEW Metal2 ( 66640 315280 ) Via2_VH
+ NEW Metal1 ( 77840 315280 ) Via1_VV
+ NEW Metal2 ( 77840 315280 ) Via2_VH
+ NEW Metal1 ( 68880 301840 ) Via1_VV
+ NEW Metal1 ( 64400 296240 ) Via1_VV
+ NEW Metal2 ( 77840 315280 ) RECT ( -280 -660 280 0 ) ;
+ - _0394_ ( _1007_ A3 ) ( _1004_ A3 ) ( _0999_ A2 ) ( _0998_ ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 72240 304080 ) ( * 307440 )
+ NEW Metal3 ( 63280 304080 ) ( 72240 * )
+ NEW Metal2 ( 78960 304080 ) ( * 316400 )
+ NEW Metal3 ( 72240 304080 ) ( 78960 * )
+ NEW Metal2 ( 78960 316400 ) ( * 338800 )
+ NEW Metal1 ( 72240 307440 ) Via1_VV
+ NEW Metal2 ( 72240 304080 ) Via2_VH
+ NEW Metal1 ( 63280 304080 ) Via1_VV
+ NEW Metal2 ( 63280 304080 ) Via2_VH
+ NEW Metal1 ( 78960 316400 ) Via1_VV
+ NEW Metal2 ( 78960 304080 ) Via2_VH
+ NEW Metal1 ( 78960 338800 ) Via1_VV
+ NEW Metal2 ( 63280 304080 ) RECT ( -280 -660 280 0 ) ;
+ - _0395_ ( _1001_ A2 ) ( _0999_ ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 75600 317520 ) ( * 318640 )
+ NEW Metal2 ( 68880 318640 ) ( 75600 * )
+ NEW Metal2 ( 68880 317520 ) ( * 318640 )
+ NEW Metal1 ( 75600 317520 ) Via1_VV
+ NEW Metal1 ( 68880 317520 ) Via1_VV ;
+ - _0396_ ( _1005_ A2 ) ( _1001_ A3 ) ( _1000_ ZN ) + USE SIGNAL
+ + ROUTED Metal3 ( 46480 316400 ) ( 67760 * )
+ NEW Metal2 ( 76720 309680 ) ( 77840 * )
+ NEW Metal2 ( 76720 309680 ) ( * 316400 )
+ NEW Metal3 ( 67760 316400 ) ( 76720 * )
+ NEW Metal1 ( 67760 316400 ) Via1_VV
+ NEW Metal2 ( 67760 316400 ) Via2_VH
+ NEW Metal1 ( 46480 316400 ) Via1_VV
+ NEW Metal2 ( 46480 316400 ) Via2_VH
+ NEW Metal1 ( 77840 309680 ) Via1_VV
+ NEW Metal2 ( 76720 316400 ) Via2_VH
+ NEW Metal2 ( 67760 316400 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 46480 316400 ) RECT ( -280 -660 280 0 ) ;
+ - _0397_ ( _1002_ I ) ( _1001_ Z ) + USE SIGNAL
+ + ROUTED Metal3 ( 27440 318640 ) ( 63280 * )
+ NEW Metal2 ( 27440 318640 ) ( * 333200 )
+ NEW Metal1 ( 63280 318640 ) Via1_HV
+ NEW Metal2 ( 63280 318640 ) Via2_VH
+ NEW Metal2 ( 27440 318640 ) Via2_VH
+ NEW Metal1 ( 27440 333200 ) Via1_HV
+ NEW Metal2 ( 63280 318640 ) RECT ( -280 -660 280 0 ) ;
+ - _0398_ ( _1007_ A2 ) ( _1005_ A1 ) ( _1004_ A2 ) ( _1003_ ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 65520 304080 ) ( * 307440 )
+ NEW Metal3 ( 46480 307440 ) ( 65520 * )
+ NEW Metal3 ( 65520 307440 ) ( 70000 * )
+ NEW Metal2 ( 81200 307440 ) ( * 309680 )
+ NEW Metal3 ( 70000 307440 ) ( 81200 * )
+ NEW Metal1 ( 65520 304080 ) Via1_VV
+ NEW Metal2 ( 65520 307440 ) Via2_VH
+ NEW Metal1 ( 46480 307440 ) Via1_VV
+ NEW Metal2 ( 46480 307440 ) Via2_VH
+ NEW Metal1 ( 70000 307440 ) Via1_VV
+ NEW Metal2 ( 70000 307440 ) Via2_VH
+ NEW Metal1 ( 81200 309680 ) Via1_VV
+ NEW Metal2 ( 81200 307440 ) Via2_VH
+ NEW Metal2 ( 46480 307440 ) RECT ( -280 0 280 660 )
+ NEW Metal2 ( 70000 307440 ) RECT ( -280 -660 280 0 ) ;
+ - _0399_ ( _1005_ B ) ( _1004_ ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 73360 309680 ) ( * 311920 )
+ NEW Metal3 ( 73360 309680 ) ( 83440 * )
+ NEW Metal1 ( 73360 311920 ) Via1_VV
+ NEW Metal2 ( 73360 309680 ) Via2_VH
+ NEW Metal1 ( 83440 309680 ) Via1_VV
+ NEW Metal2 ( 83440 309680 ) Via2_VH
+ NEW Metal2 ( 83440 309680 ) RECT ( -280 -660 280 0 ) ;
+ - _0400_ ( _1008_ A1 ) ( _1006_ ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 61040 285040 ) ( * 308560 )
+ NEW Metal2 ( 59920 308560 ) ( 61040 * )
+ NEW Metal1 ( 61040 285040 ) Via1_VV
+ NEW Metal1 ( 59920 308560 ) Via1_VV ;
+ - _0401_ ( _1008_ A2 ) ( _1007_ ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 62160 286160 ) ( 64400 * )
+ NEW Metal2 ( 62160 286160 ) ( * 299600 )
+ NEW Metal1 ( 64400 286160 ) Via1_VV
+ NEW Metal1 ( 62160 299600 ) Via1_VV ;
+ - _0402_ ( ANTENNA__1010__A2 I ) ( ANTENNA__1012__A2 I ) ( ANTENNA__1014__A2 I ) ( ANTENNA__1016__A2 I ) ( ANTENNA__1111__C I ) ( ANTENNA__1120__A1 I ) ( ANTENNA__1163__C I )
+ ( ANTENNA__1173__A1 I ) ( ANTENNA__1214__C I ) ( ANTENNA__1223__A1 I ) ( _1223_ A1 ) ( _1214_ C ) ( _1173_ A1 ) ( _1163_ C ) ( _1120_ A1 )
+ ( _1111_ C ) ( _1016_ A2 ) ( _1014_ A2 ) ( _1012_ A2 ) ( _1010_ A2 ) ( _1009_ Z ) + USE SIGNAL
+ + ROUTED Metal3 ( 300720 272720 ) ( 310800 * )
+ NEW Metal2 ( 310800 272720 ) ( * 277200 )
+ NEW Metal2 ( 316400 249200 ) ( * 272720 )
+ NEW Metal3 ( 310800 272720 ) ( 316400 * )
+ NEW Metal3 ( 310800 249200 ) ( 316400 * )
+ NEW Metal2 ( 310800 241360 ) ( * 249200 )
+ NEW Metal3 ( 299600 241360 ) ( 310800 * )
+ NEW Metal2 ( 294000 241360 ) ( * 244720 )
+ NEW Metal3 ( 294000 241360 ) ( 299600 * )
+ NEW Metal2 ( 305200 224560 ) ( 306320 * )
+ NEW Metal2 ( 305200 224560 ) ( * 241360 )
+ NEW Metal3 ( 450800 309680 ) ( 456400 * )
+ NEW Metal2 ( 450800 308560 ) ( * 309680 )
+ NEW Metal3 ( 478800 295120 ) ( 482160 * )
+ NEW Metal2 ( 478800 295120 ) ( * 304080 )
+ NEW Metal3 ( 450800 304080 ) ( 478800 * )
+ NEW Metal3 ( 482160 295120 ) ( 487760 * )
+ NEW Metal2 ( 447440 500080 ) ( * 504560 )
+ NEW Metal2 ( 447440 500080 ) ( 450800 * )
+ NEW Metal3 ( 447440 504560 ) ( 457520 * )
+ NEW Metal2 ( 447440 504560 ) ( * 519120 )
+ NEW Metal2 ( 479920 515760 ) ( * 519120 )
+ NEW Metal3 ( 447440 519120 ) ( 479920 * )
+ NEW Metal2 ( 494480 515760 ) ( * 519120 )
+ NEW Metal3 ( 479920 519120 ) ( 494480 * )
+ NEW Metal2 ( 450800 309680 ) ( * 500080 )
+ NEW Metal2 ( 337680 255920 ) ( * 257040 )
+ NEW Metal3 ( 337680 257040 ) ( 355600 * )
+ NEW Metal3 ( 355600 257040 ) ( * 258160 )
+ NEW Metal2 ( 337680 249200 ) ( * 255920 )
+ NEW Metal3 ( 316400 249200 ) ( 337680 * )
+ NEW Metal2 ( 414960 515760 ) ( * 519120 )
+ NEW Metal2 ( 404880 514640 ) ( * 519120 )
+ NEW Metal3 ( 404880 519120 ) ( 414960 * )
+ NEW Metal3 ( 363440 519120 ) ( 404880 * )
+ NEW Metal3 ( 357840 519120 ) ( 363440 * )
+ NEW Metal3 ( 414960 519120 ) ( 447440 * )
+ NEW Metal3 ( 355600 258160 ) ( 450800 * )
+ NEW Metal2 ( 450800 258160 ) ( * 308560 )
+ NEW Metal1 ( 300720 272720 ) Via1_VV
+ NEW Metal2 ( 300720 272720 ) Via2_VH
+ NEW Metal2 ( 310800 272720 ) Via2_VH
+ NEW Metal1 ( 310800 277200 ) Via1_VV
+ NEW Metal1 ( 316400 249200 ) Via1_VV
+ NEW Metal2 ( 316400 272720 ) Via2_VH
+ NEW Metal1 ( 310800 249200 ) Via1_VV
+ NEW Metal2 ( 310800 249200 ) Via2_VH
+ NEW Metal2 ( 316400 249200 ) Via2_VH
+ NEW Metal1 ( 310800 241360 ) Via1_VV
+ NEW Metal1 ( 299600 241360 ) Via1_VV
+ NEW Metal2 ( 299600 241360 ) Via2_VH
+ NEW Metal2 ( 310800 241360 ) Via2_VH
+ NEW Metal1 ( 294000 244720 ) Via1_VV
+ NEW Metal2 ( 294000 241360 ) Via2_VH
+ NEW Metal1 ( 306320 224560 ) Via1_VV
+ NEW Metal2 ( 305200 241360 ) Via2_VH
+ NEW Metal1 ( 450800 308560 ) Via1_VV
+ NEW Metal1 ( 456400 309680 ) Via1_HV
+ NEW Metal2 ( 456400 309680 ) Via2_VH
+ NEW Metal2 ( 450800 309680 ) Via2_VH
+ NEW Metal1 ( 482160 295120 ) Via1_VV
+ NEW Metal2 ( 482160 295120 ) Via2_VH
+ NEW Metal2 ( 478800 295120 ) Via2_VH
+ NEW Metal2 ( 478800 304080 ) Via2_VH
+ NEW Metal2 ( 450800 304080 ) Via2_VH
+ NEW Metal1 ( 487760 295120 ) Via1_VV
+ NEW Metal2 ( 487760 295120 ) Via2_VH
+ NEW Metal1 ( 447440 504560 ) Via1_VV
+ NEW Metal1 ( 457520 504560 ) Via1_HV
+ NEW Metal2 ( 457520 504560 ) Via2_VH
+ NEW Metal2 ( 447440 504560 ) Via2_VH
+ NEW Metal2 ( 447440 519120 ) Via2_VH
+ NEW Metal1 ( 479920 515760 ) Via1_VV
+ NEW Metal2 ( 479920 519120 ) Via2_VH
+ NEW Metal1 ( 494480 515760 ) Via1_VV
+ NEW Metal2 ( 494480 519120 ) Via2_VH
+ NEW Metal1 ( 337680 255920 ) Via1_VV
+ NEW Metal2 ( 337680 257040 ) Via2_VH
+ NEW Metal2 ( 337680 249200 ) Via2_VH
+ NEW Metal1 ( 414960 515760 ) Via1_VV
+ NEW Metal2 ( 414960 519120 ) Via2_VH
+ NEW Metal1 ( 404880 514640 ) Via1_HV
+ NEW Metal2 ( 404880 519120 ) Via2_VH
+ NEW Metal1 ( 363440 519120 ) Via1_VV
+ NEW Metal2 ( 363440 519120 ) Via2_VH
+ NEW Metal1 ( 357840 519120 ) Via1_VV
+ NEW Metal2 ( 357840 519120 ) Via2_VH
+ NEW Metal2 ( 450800 258160 ) Via2_VH
+ NEW Metal2 ( 300720 272720 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 310800 249200 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 316400 249200 ) RECT ( -280 -1040 280 0 )
+ NEW Metal2 ( 299600 241360 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 310800 241360 ) RECT ( -280 -1040 280 0 )
+ NEW Metal3 ( 305200 241360 ) RECT ( -1040 -280 0 280 )
+ NEW Metal2 ( 456400 309680 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 482160 295120 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 450800 304080 ) RECT ( -280 -1040 280 0 )
+ NEW Metal2 ( 487760 295120 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 457520 504560 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 447440 504560 ) RECT ( -280 -1040 280 0 )
+ NEW Metal2 ( 363440 519120 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 357840 519120 ) RECT ( -280 -660 280 0 ) ;
+ - _0403_ ( _1011_ I ) ( _1010_ Z ) + USE SIGNAL
+ + ROUTED Metal3 ( 302960 238000 ) ( 319760 * )
+ NEW Metal1 ( 302960 238000 ) Via1_HV
+ NEW Metal2 ( 302960 238000 ) Via2_VH
+ NEW Metal1 ( 319760 238000 ) Via1_VV
+ NEW Metal2 ( 319760 238000 ) Via2_VH
+ NEW Metal2 ( 302960 238000 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 319760 238000 ) RECT ( -280 -660 280 0 ) ;
+ - _0404_ ( _1013_ I ) ( _1012_ Z ) + USE SIGNAL
+ + ROUTED Metal2 ( 317520 223440 ) ( * 236880 )
+ NEW Metal2 ( 314160 236880 ) ( 317520 * )
+ NEW Metal1 ( 317520 223440 ) Via1_VV
+ NEW Metal1 ( 314160 236880 ) Via1_HV ;
+ - _0405_ ( _1015_ I ) ( _1014_ Z ) + USE SIGNAL
+ + ROUTED Metal2 ( 304080 269360 ) ( 311920 * )
+ NEW Metal1 ( 311920 269360 ) Via1_VV
+ NEW Metal1 ( 304080 269360 ) Via1_HV ;
+ - _0406_ ( _1017_ I ) ( _1016_ Z ) + USE SIGNAL
+ + ROUTED Metal3 ( 297360 246960 ) ( 302960 * )
+ NEW Metal1 ( 302960 246960 ) Via1_VV
+ NEW Metal2 ( 302960 246960 ) Via2_VH
+ NEW Metal1 ( 297360 246960 ) Via1_HV
+ NEW Metal2 ( 297360 246960 ) Via2_VH
+ NEW Metal2 ( 302960 246960 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 297360 246960 ) RECT ( -280 -660 280 0 ) ;
+ - _0407_ ( ANTENNA__1019__A2 I ) ( ANTENNA__1021__A2 I ) ( ANTENNA__1026__A1 I ) ( ANTENNA__1137__B I ) ( ANTENNA__1190__B I ) ( ANTENNA__1242__B I ) ( ANTENNA__1274__A1 I )
+ ( ANTENNA__1329__B I ) ( ANTENNA__1338__A1 I ) ( ANTENNA__1347__A1 I ) ( _1347_ A1 ) ( _1338_ A1 ) ( _1329_ B ) ( _1274_ A1 ) ( _1242_ B )
+ ( _1190_ B ) ( _1137_ B ) ( _1026_ A1 ) ( _1021_ A2 ) ( _1019_ A2 ) ( _1018_ Z ) + USE SIGNAL
+ + ROUTED Metal2 ( 300720 252560 ) ( * 254800 )
+ NEW Metal3 ( 300720 252560 ) ( 308560 * )
+ NEW Metal2 ( 454160 436800 ) ( * 442960 )
+ NEW Metal2 ( 447440 365680 ) ( 448560 * )
+ NEW Metal2 ( 448560 365680 ) ( * 374640 )
+ NEW Metal3 ( 448560 364560 ) ( 454160 * )
+ NEW Metal2 ( 448560 364560 ) ( * 365680 )
+ NEW Metal2 ( 453040 436800 ) ( 454160 * )
+ NEW Metal2 ( 453040 430640 ) ( * 436800 )
+ NEW Metal3 ( 444080 430640 ) ( 453040 * )
+ NEW Metal2 ( 444080 430640 ) ( * 449680 )
+ NEW Metal2 ( 177520 397040 ) ( 178640 * )
+ NEW Metal2 ( 177520 397040 ) ( * 403760 )
+ NEW Metal2 ( 183120 372400 ) ( * 374640 )
+ NEW Metal2 ( 178640 374640 ) ( 183120 * )
+ NEW Metal2 ( 178640 374640 ) ( * 397040 )
+ NEW Metal2 ( 183120 372400 ) ( 187600 * )
+ NEW Metal2 ( 187600 372400 ) ( * 374640 )
+ NEW Metal2 ( 183120 341040 ) ( * 372400 )
+ NEW Metal2 ( 183120 343280 ) ( 187600 * )
+ NEW Metal2 ( 183120 292880 ) ( * 341040 )
+ NEW Metal2 ( 374640 374640 ) ( * 376880 )
+ NEW Metal3 ( 324240 376880 ) ( 374640 * )
+ NEW Metal3 ( 324240 374640 ) ( * 376880 )
+ NEW Metal2 ( 390320 374640 ) ( * 376880 )
+ NEW Metal3 ( 374640 376880 ) ( 390320 * )
+ NEW Metal2 ( 401520 406000 ) ( * 425040 )
+ NEW Metal2 ( 398160 406000 ) ( 401520 * )
+ NEW Metal2 ( 398160 374640 ) ( * 406000 )
+ NEW Metal2 ( 401520 425040 ) ( * 430640 )
+ NEW Metal2 ( 408240 430640 ) ( * 434000 )
+ NEW Metal3 ( 187600 374640 ) ( 324240 * )
+ NEW Metal3 ( 390320 374640 ) ( 448560 * )
+ NEW Metal3 ( 401520 430640 ) ( 444080 * )
+ NEW Metal3 ( 183120 255920 ) ( 226800 * )
+ NEW Metal3 ( 226800 255920 ) ( 234640 * )
+ NEW Metal2 ( 233520 240240 ) ( 234640 * )
+ NEW Metal2 ( 234640 240240 ) ( * 255920 )
+ NEW Metal2 ( 227920 238000 ) ( * 239120 )
+ NEW Metal2 ( 226800 239120 ) ( 227920 * )
+ NEW Metal2 ( 226800 239120 ) ( * 255920 )
+ NEW Metal2 ( 183120 255920 ) ( * 292880 )
+ NEW Metal3 ( 234640 252560 ) ( 300720 * )
+ NEW Metal1 ( 300720 254800 ) Via1_VV
+ NEW Metal2 ( 300720 252560 ) Via2_VH
+ NEW Metal1 ( 308560 252560 ) Via1_VV
+ NEW Metal2 ( 308560 252560 ) Via2_VH
+ NEW Metal1 ( 444080 449680 ) Via1_VV
+ NEW Metal1 ( 454160 442960 ) Via1_VV
+ NEW Metal1 ( 447440 365680 ) Via1_VV
+ NEW Metal2 ( 448560 374640 ) Via2_VH
+ NEW Metal1 ( 454160 364560 ) Via1_VV
+ NEW Metal2 ( 454160 364560 ) Via2_VH
+ NEW Metal2 ( 448560 364560 ) Via2_VH
+ NEW Metal2 ( 444080 430640 ) Via2_VH
+ NEW Metal2 ( 453040 430640 ) Via2_VH
+ NEW Metal1 ( 183120 292880 ) Via1_VV
+ NEW Metal1 ( 178640 397040 ) Via1_VV
+ NEW Metal1 ( 177520 403760 ) Via1_HV
+ NEW Metal1 ( 183120 372400 ) Via1_VV
+ NEW Metal1 ( 187600 372400 ) Via1_VV
+ NEW Metal2 ( 187600 374640 ) Via2_VH
+ NEW Metal1 ( 183120 341040 ) Via1_VV
+ NEW Metal1 ( 187600 343280 ) Via1_VV
+ NEW Metal1 ( 374640 374640 ) Via1_VV
+ NEW Metal2 ( 374640 376880 ) Via2_VH
+ NEW Metal1 ( 390320 374640 ) Via1_VV
+ NEW Metal2 ( 390320 376880 ) Via2_VH
+ NEW Metal2 ( 390320 374640 ) Via2_VH
+ NEW Metal1 ( 401520 425040 ) Via1_VV
+ NEW Metal2 ( 398160 374640 ) Via2_VH
+ NEW Metal2 ( 401520 430640 ) Via2_VH
+ NEW Metal1 ( 408240 434000 ) Via1_VV
+ NEW Metal2 ( 408240 430640 ) Via2_VH
+ NEW Metal1 ( 226800 255920 ) Via1_VV
+ NEW Metal2 ( 226800 255920 ) Via2_VH
+ NEW Metal2 ( 183120 255920 ) Via2_VH
+ NEW Metal1 ( 234640 255920 ) Via1_VV
+ NEW Metal2 ( 234640 255920 ) Via2_VH
+ NEW Metal1 ( 233520 240240 ) Via1_VV
+ NEW Metal1 ( 227920 238000 ) Via1_VV
+ NEW Metal2 ( 234640 252560 ) Via2_VH
+ NEW Metal2 ( 308560 252560 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 454160 364560 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 390320 374640 ) RECT ( -280 -1040 280 0 )
+ NEW Metal3 ( 398160 374640 ) RECT ( -1040 -280 0 280 )
+ NEW Metal3 ( 408240 430640 ) RECT ( -1040 -280 0 280 )
+ NEW Metal2 ( 226800 255920 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 234640 255920 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 234640 252560 ) RECT ( -280 -1040 280 0 ) ;
+ - _0408_ ( _1020_ I ) ( _1019_ Z ) + USE SIGNAL
+ + ROUTED Metal3 ( 238000 269360 ) ( 285040 * )
+ NEW Metal2 ( 238000 257040 ) ( * 269360 )
+ NEW Metal2 ( 238000 269360 ) Via2_VH
+ NEW Metal1 ( 285040 269360 ) Via1_VV
+ NEW Metal2 ( 285040 269360 ) Via2_VH
+ NEW Metal1 ( 238000 257040 ) Via1_HV
+ NEW Metal2 ( 285040 269360 ) RECT ( -280 -660 280 0 ) ;
+ - _0409_ ( _1022_ I ) ( _1021_ Z ) + USE SIGNAL
+ + ROUTED Metal2 ( 304080 254800 ) ( 314160 * )
+ NEW Metal1 ( 314160 254800 ) Via1_VV
+ NEW Metal1 ( 304080 254800 ) Via1_HV ;
+ - _0410_ ( ANTENNA__1024__I I ) ( ANTENNA__1031__I I ) ( ANTENNA__1093__C I ) ( ANTENNA__1124__B I ) ( ANTENNA__1169__A1 I ) ( ANTENNA__1218__A1 I ) ( ANTENNA__1270__C I )
+ ( ANTENNA__1281__C I ) ( ANTENNA__1340__B I ) ( ANTENNA__1349__A1 I ) ( _1349_ A1 ) ( _1340_ B ) ( _1281_ C ) ( _1270_ C ) ( _1218_ A1 )
+ ( _1169_ A1 ) ( _1124_ B ) ( _1093_ C ) ( _1031_ I ) ( _1024_ I ) ( _1023_ Z ) + USE SIGNAL
+ + ROUTED Metal2 ( 297360 217840 ) ( * 236880 )
+ NEW Metal2 ( 292880 236880 ) ( 297360 * )
+ NEW Metal2 ( 288400 215600 ) ( * 217840 )
+ NEW Metal2 ( 288400 217840 ) ( 297360 * )
+ NEW Metal2 ( 445200 311920 ) ( * 315280 )
+ NEW Metal2 ( 445200 315280 ) ( 446320 * )
+ NEW Metal3 ( 446320 315280 ) ( 454160 * )
+ NEW Metal2 ( 445200 464240 ) ( * 465360 )
+ NEW Metal2 ( 445200 464240 ) ( 448560 * )
+ NEW Metal2 ( 456400 469840 ) ( * 487760 )
+ NEW Metal3 ( 448560 469840 ) ( 456400 * )
+ NEW Metal2 ( 448560 464240 ) ( * 469840 )
+ NEW Metal2 ( 456400 487760 ) ( * 495600 )
+ NEW Metal3 ( 473200 490000 ) ( * 491120 )
+ NEW Metal3 ( 456400 491120 ) ( 473200 * )
+ NEW Metal3 ( 283920 193200 ) ( 289520 * )
+ NEW Metal2 ( 276080 193200 ) ( * 197680 )
+ NEW Metal3 ( 276080 193200 ) ( 283920 * )
+ NEW Metal2 ( 289520 193200 ) ( * 217840 )
+ NEW Metal2 ( 288400 353360 ) ( * 355600 )
+ NEW Metal2 ( 277200 348880 ) ( * 352240 )
+ NEW Metal3 ( 277200 352240 ) ( 288400 * )
+ NEW Metal3 ( 288400 352240 ) ( * 353360 )
+ NEW Metal2 ( 292880 236880 ) ( * 353360 )
+ NEW Metal2 ( 446320 315280 ) ( * 319200 )
+ NEW Metal2 ( 449680 393680 ) ( * 403760 )
+ NEW Metal2 ( 445200 393680 ) ( 449680 * )
+ NEW Metal2 ( 445200 344400 ) ( * 393680 )
+ NEW Metal2 ( 445200 344400 ) ( 447440 * )
+ NEW Metal2 ( 447440 319200 ) ( * 344400 )
+ NEW Metal2 ( 446320 319200 ) ( 447440 * )
+ NEW Metal3 ( 440720 403760 ) ( 449680 * )
+ NEW Metal2 ( 440720 403760 ) ( * 407120 )
+ NEW Metal2 ( 448560 403760 ) ( 449680 * )
+ NEW Metal2 ( 448560 403760 ) ( * 464240 )
+ NEW Metal2 ( 392560 316400 ) ( 393680 * )
+ NEW Metal2 ( 393680 311920 ) ( * 316400 )
+ NEW Metal3 ( 393680 311920 ) ( 400400 * )
+ NEW Metal3 ( 400400 311920 ) ( 445200 * )
+ NEW Metal2 ( 376880 495600 ) ( * 496720 )
+ NEW Metal2 ( 356720 495600 ) ( * 497840 )
+ NEW Metal3 ( 356720 495600 ) ( 376880 * )
+ NEW Metal3 ( 376880 495600 ) ( 456400 * )
+ NEW Metal3 ( 288400 353360 ) ( 319200 * )
+ NEW Metal3 ( 319200 354480 ) ( 358960 * )
+ NEW Metal3 ( 319200 353360 ) ( * 354480 )
+ NEW Metal2 ( 365680 362320 ) ( 366800 * )
+ NEW Metal2 ( 366800 354480 ) ( * 362320 )
+ NEW Metal3 ( 358960 354480 ) ( 366800 * )
+ NEW Metal2 ( 388080 395920 ) ( 389200 * )
+ NEW Metal2 ( 388080 362320 ) ( * 395920 )
+ NEW Metal3 ( 366800 362320 ) ( 388080 * )
+ NEW Metal2 ( 408240 397040 ) ( * 403760 )
+ NEW Metal3 ( 389200 397040 ) ( 408240 * )
+ NEW Metal2 ( 389200 395920 ) ( * 397040 )
+ NEW Metal2 ( 408240 403760 ) ( * 407120 )
+ NEW Metal3 ( 408240 407120 ) ( 440720 * )
+ NEW Metal1 ( 297360 217840 ) Via1_VV
+ NEW Metal1 ( 288400 215600 ) Via1_HV
+ NEW Metal1 ( 445200 315280 ) Via1_VV
+ NEW Metal2 ( 445200 311920 ) Via2_VH
+ NEW Metal1 ( 454160 315280 ) Via1_VV
+ NEW Metal2 ( 454160 315280 ) Via2_VH
+ NEW Metal2 ( 446320 315280 ) Via2_VH
+ NEW Metal1 ( 445200 465360 ) Via1_VV
+ NEW Metal1 ( 456400 487760 ) Via1_VV
+ NEW Metal2 ( 456400 469840 ) Via2_VH
+ NEW Metal2 ( 448560 469840 ) Via2_VH
+ NEW Metal2 ( 456400 495600 ) Via2_VH
+ NEW Metal1 ( 473200 490000 ) Via1_VV
+ NEW Metal2 ( 473200 490000 ) Via2_VH
+ NEW Metal2 ( 456400 491120 ) Via2_VH
+ NEW Metal1 ( 283920 193200 ) Via1_VV
+ NEW Metal2 ( 283920 193200 ) Via2_VH
+ NEW Metal2 ( 289520 193200 ) Via2_VH
+ NEW Metal1 ( 276080 197680 ) Via1_VV
+ NEW Metal2 ( 276080 193200 ) Via2_VH
+ NEW Metal1 ( 288400 355600 ) Via1_VV
+ NEW Metal2 ( 288400 353360 ) Via2_VH
+ NEW Metal1 ( 277200 348880 ) Via1_VV
+ NEW Metal2 ( 277200 352240 ) Via2_VH
+ NEW Metal2 ( 292880 353360 ) Via2_VH
+ NEW Metal1 ( 449680 403760 ) Via1_VV
+ NEW Metal1 ( 440720 403760 ) Via1_HV
+ NEW Metal2 ( 440720 403760 ) Via2_VH
+ NEW Metal2 ( 449680 403760 ) Via2_VH
+ NEW Metal2 ( 440720 407120 ) Via2_VH
+ NEW Metal1 ( 400400 311920 ) Via1_VV
+ NEW Metal2 ( 400400 311920 ) Via2_VH
+ NEW Metal1 ( 392560 316400 ) Via1_VV
+ NEW Metal2 ( 393680 311920 ) Via2_VH
+ NEW Metal1 ( 376880 496720 ) Via1_VV
+ NEW Metal2 ( 376880 495600 ) Via2_VH
+ NEW Metal1 ( 356720 497840 ) Via1_VV
+ NEW Metal2 ( 356720 495600 ) Via2_VH
+ NEW Metal1 ( 358960 354480 ) Via1_VV
+ NEW Metal2 ( 358960 354480 ) Via2_VH
+ NEW Metal1 ( 365680 362320 ) Via1_VV
+ NEW Metal2 ( 366800 354480 ) Via2_VH
+ NEW Metal1 ( 389200 395920 ) Via1_VV
+ NEW Metal2 ( 388080 362320 ) Via2_VH
+ NEW Metal2 ( 366800 362320 ) Via2_VH
+ NEW Metal1 ( 408240 403760 ) Via1_VV
+ NEW Metal2 ( 408240 397040 ) Via2_VH
+ NEW Metal2 ( 389200 397040 ) Via2_VH
+ NEW Metal2 ( 408240 407120 ) Via2_VH
+ NEW Metal2 ( 454160 315280 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 446320 315280 ) RECT ( -280 -1040 280 0 )
+ NEW Metal2 ( 473200 490000 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 456400 491120 ) RECT ( -280 -1040 280 0 )
+ NEW Metal2 ( 283920 193200 ) RECT ( -280 -660 280 0 )
+ NEW Metal3 ( 292880 353360 ) RECT ( -1040 -280 0 280 )
+ NEW Metal2 ( 440720 403760 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 449680 403760 ) RECT ( -280 -1040 280 0 )
+ NEW Metal2 ( 400400 311920 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 358960 354480 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 366800 362320 ) RECT ( -280 -1040 280 0 ) ;
+ - _0411_ ( ANTENNA__1025__A2 I ) ( ANTENNA__1034__A1 I ) ( ANTENNA__1036__A2 I ) ( ANTENNA__1038__A2 I ) ( ANTENNA__1040__A2 I ) ( ANTENNA__1041__A2 I ) ( ANTENNA__1054__A1 I )
+ ( ANTENNA__1069__A1 I ) ( ANTENNA__1077__A1 I ) ( ANTENNA__1081__A1 I ) ( _1081_ A1 ) ( _1077_ A1 ) ( _1069_ A1 ) ( _1054_ A1 ) ( _1041_ A2 )
+ ( _1040_ A2 ) ( _1038_ A2 ) ( _1036_ A2 ) ( _1034_ A1 ) ( _1025_ A2 ) ( _1024_ Z ) + USE SIGNAL
+ + ROUTED Metal2 ( 246960 108080 ) ( * 111440 )
+ NEW Metal2 ( 235760 108080 ) ( * 111440 )
+ NEW Metal3 ( 235760 111440 ) ( 246960 * )
+ NEW Metal3 ( 222320 111440 ) ( 235760 * )
+ NEW Metal3 ( 215600 111440 ) ( 222320 * )
+ NEW Metal2 ( 220080 142800 ) ( 222320 * )
+ NEW Metal2 ( 222320 111440 ) ( * 142800 )
+ NEW Metal3 ( 292880 214480 ) ( 323120 * )
+ NEW Metal2 ( 323120 201600 ) ( * 214480 )
+ NEW Metal2 ( 335440 175280 ) ( * 179760 )
+ NEW Metal3 ( 324240 179760 ) ( 335440 * )
+ NEW Metal2 ( 324240 179760 ) ( * 201600 )
+ NEW Metal2 ( 323120 201600 ) ( 324240 * )
+ NEW Metal2 ( 341040 177520 ) ( * 179760 )
+ NEW Metal3 ( 335440 179760 ) ( 341040 * )
+ NEW Metal2 ( 327600 123760 ) ( 329840 * )
+ NEW Metal2 ( 329840 123760 ) ( * 170800 )
+ NEW Metal3 ( 329840 170800 ) ( 335440 * )
+ NEW Metal2 ( 335440 170800 ) ( * 175280 )
+ NEW Metal2 ( 333200 115920 ) ( * 123760 )
+ NEW Metal2 ( 329840 123760 ) ( 333200 * )
+ NEW Metal2 ( 333200 111440 ) ( * 115920 )
+ NEW Metal2 ( 339920 106960 ) ( * 111440 )
+ NEW Metal3 ( 333200 111440 ) ( 339920 * )
+ NEW Metal2 ( 344400 108080 ) ( * 111440 )
+ NEW Metal3 ( 339920 111440 ) ( 344400 * )
+ NEW Metal2 ( 335440 100240 ) ( * 111440 )
+ NEW Metal2 ( 339920 100240 ) ( 341040 * )
+ NEW Metal2 ( 339920 100240 ) ( * 106960 )
+ NEW Metal2 ( 327600 99120 ) ( * 101360 )
+ NEW Metal3 ( 327600 101360 ) ( 335440 * )
+ NEW Metal3 ( 341040 99120 ) ( 353360 * )
+ NEW Metal2 ( 341040 99120 ) ( * 100240 )
+ NEW Metal3 ( 246960 111440 ) ( 333200 * )
+ NEW Metal3 ( 214480 151760 ) ( 220080 * )
+ NEW Metal3 ( 245840 221200 ) ( 255920 * )
+ NEW Metal2 ( 255920 214480 ) ( * 221200 )
+ NEW Metal2 ( 238000 221200 ) ( * 222320 )
+ NEW Metal3 ( 238000 221200 ) ( 245840 * )
+ NEW Metal2 ( 241360 223440 ) ( * 230160 )
+ NEW Metal2 ( 238000 223440 ) ( 241360 * )
+ NEW Metal2 ( 238000 222320 ) ( * 223440 )
+ NEW Metal2 ( 220080 142800 ) ( * 151760 )
+ NEW Metal3 ( 255920 214480 ) ( 292880 * )
+ NEW Metal1 ( 292880 214480 ) Via1_VV
+ NEW Metal2 ( 292880 214480 ) Via2_VH
+ NEW Metal1 ( 246960 108080 ) Via1_VV
+ NEW Metal2 ( 246960 111440 ) Via2_VH
+ NEW Metal1 ( 235760 108080 ) Via1_VV
+ NEW Metal2 ( 235760 111440 ) Via2_VH
+ NEW Metal1 ( 222320 111440 ) Via1_VV
+ NEW Metal2 ( 222320 111440 ) Via2_VH
+ NEW Metal1 ( 215600 111440 ) Via1_VV
+ NEW Metal2 ( 215600 111440 ) Via2_VH
+ NEW Metal1 ( 220080 142800 ) Via1_VV
+ NEW Metal2 ( 323120 214480 ) Via2_VH
+ NEW Metal1 ( 335440 175280 ) Via1_VV
+ NEW Metal2 ( 335440 179760 ) Via2_VH
+ NEW Metal2 ( 324240 179760 ) Via2_VH
+ NEW Metal1 ( 341040 177520 ) Via1_VV
+ NEW Metal2 ( 341040 179760 ) Via2_VH
+ NEW Metal1 ( 327600 123760 ) Via1_VV
+ NEW Metal2 ( 329840 170800 ) Via2_VH
+ NEW Metal2 ( 335440 170800 ) Via2_VH
+ NEW Metal1 ( 333200 115920 ) Via1_VV
+ NEW Metal2 ( 333200 111440 ) Via2_VH
+ NEW Metal1 ( 339920 106960 ) Via1_VV
+ NEW Metal2 ( 339920 111440 ) Via2_VH
+ NEW Metal1 ( 344400 108080 ) Via1_VV
+ NEW Metal2 ( 344400 111440 ) Via2_VH
+ NEW Metal1 ( 335440 100240 ) Via1_VV
+ NEW Metal2 ( 335440 111440 ) Via2_VH
+ NEW Metal1 ( 341040 100240 ) Via1_VV
+ NEW Metal1 ( 327600 99120 ) Via1_VV
+ NEW Metal2 ( 327600 101360 ) Via2_VH
+ NEW Metal2 ( 335440 101360 ) Via2_VH
+ NEW Metal1 ( 353360 99120 ) Via1_VV
+ NEW Metal2 ( 353360 99120 ) Via2_VH
+ NEW Metal2 ( 341040 99120 ) Via2_VH
+ NEW Metal2 ( 220080 151760 ) Via2_VH
+ NEW Metal1 ( 214480 151760 ) Via1_VV
+ NEW Metal2 ( 214480 151760 ) Via2_VH
+ NEW Metal1 ( 255920 214480 ) Via1_VV
+ NEW Metal2 ( 255920 214480 ) Via2_VH
+ NEW Metal1 ( 245840 221200 ) Via1_VV
+ NEW Metal2 ( 245840 221200 ) Via2_VH
+ NEW Metal2 ( 255920 221200 ) Via2_VH
+ NEW Metal1 ( 238000 222320 ) Via1_VV
+ NEW Metal2 ( 238000 221200 ) Via2_VH
+ NEW Metal1 ( 241360 230160 ) Via1_VV
+ NEW Metal2 ( 292880 214480 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 222320 111440 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 215600 111440 ) RECT ( -280 -660 280 0 )
+ NEW Metal3 ( 335440 111440 ) RECT ( -1040 -280 0 280 )
+ NEW Metal2 ( 335440 101360 ) RECT ( -280 -1040 280 0 )
+ NEW Metal2 ( 353360 99120 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 214480 151760 ) RECT ( -280 0 280 660 )
+ NEW Metal2 ( 255920 214480 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 245840 221200 ) RECT ( -280 -660 280 0 ) ;
+ - _0412_ ( _1027_ A2 ) ( _1026_ ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 227920 241360 ) ( 229040 * )
+ NEW Metal2 ( 229040 241360 ) ( * 244720 )
+ NEW Metal1 ( 227920 241360 ) Via1_VV
+ NEW Metal1 ( 229040 244720 ) Via1_VV ;
+ - _0413_ ( _1029_ A1 ) ( _1028_ ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 230160 210000 ) ( * 216720 )
+ NEW Metal3 ( 230160 216720 ) ( 244720 * )
+ NEW Metal1 ( 230160 210000 ) Via1_VV
+ NEW Metal2 ( 230160 216720 ) Via2_VH
+ NEW Metal1 ( 244720 216720 ) Via1_VV
+ NEW Metal2 ( 244720 216720 ) Via2_VH
+ NEW Metal2 ( 244720 216720 ) RECT ( -280 -660 280 0 ) ;
+ - _0414_ ( _1033_ A2 ) ( _1032_ A1 ) ( _1029_ ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 227920 215600 ) ( 229040 * )
+ NEW Metal2 ( 227920 215600 ) ( * 222320 )
+ NEW Metal2 ( 226800 222320 ) ( 227920 * )
+ NEW Metal3 ( 229040 215600 ) ( 242480 * )
+ NEW Metal1 ( 229040 215600 ) Via1_VV
+ NEW Metal1 ( 226800 222320 ) Via1_VV
+ NEW Metal1 ( 242480 215600 ) Via1_VV
+ NEW Metal2 ( 242480 215600 ) Via2_VH
+ NEW Metal2 ( 229040 215600 ) Via2_VH
+ NEW Metal2 ( 242480 215600 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 229040 215600 ) RECT ( -280 -1040 280 0 ) ;
+ - _0415_ ( _1032_ A2 ) ( _1030_ ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 220080 215600 ) ( 222320 * )
+ NEW Metal2 ( 222320 215600 ) ( * 223440 )
+ NEW Metal1 ( 220080 215600 ) Via1_VV
+ NEW Metal1 ( 222320 223440 ) Via1_VV ;
+ - _0416_ ( ANTENNA__1032__B I ) ( ANTENNA__1043__B I ) ( ANTENNA__1048__B I ) ( ANTENNA__1050__B I ) ( ANTENNA__1086__A1 I ) ( ANTENNA__1090__A1 I ) ( ANTENNA__1194__A1 I )
+ ( ANTENNA__1199__A1 I ) ( ANTENNA__1326__A1 I ) ( ANTENNA__1334__A1 I ) ( _1334_ A1 ) ( _1326_ A1 ) ( _1199_ A1 ) ( _1194_ A1 ) ( _1090_ A1 )
+ ( _1086_ A1 ) ( _1050_ B ) ( _1048_ B ) ( _1043_ B ) ( _1032_ B ) ( _1031_ Z ) + USE SIGNAL
+ + ROUTED Metal2 ( 318640 173040 ) ( * 174160 )
+ NEW Metal2 ( 244720 130480 ) ( * 131600 )
+ NEW Metal1 ( 241360 131600 ) ( 244720 * )
+ NEW Metal2 ( 241360 131600 ) ( * 143920 )
+ NEW Metal3 ( 226800 406000 ) ( 232400 * )
+ NEW Metal2 ( 224560 365680 ) ( 225680 * )
+ NEW Metal2 ( 225680 365680 ) ( * 406000 )
+ NEW Metal2 ( 225680 406000 ) ( 226800 * )
+ NEW Metal3 ( 218960 363440 ) ( 224560 * )
+ NEW Metal2 ( 224560 363440 ) ( * 365680 )
+ NEW Metal2 ( 225680 319200 ) ( 229040 * )
+ NEW Metal2 ( 225680 319200 ) ( * 365680 )
+ NEW Metal3 ( 513520 427280 ) ( 518000 * )
+ NEW Metal3 ( 463120 411600 ) ( 513520 * )
+ NEW Metal2 ( 513520 411600 ) ( * 427280 )
+ NEW Metal3 ( 454160 411600 ) ( 463120 * )
+ NEW Metal2 ( 445200 404880 ) ( * 410480 )
+ NEW Metal3 ( 445200 410480 ) ( * 411600 )
+ NEW Metal3 ( 445200 411600 ) ( 454160 * )
+ NEW Metal2 ( 319760 168560 ) ( 323120 * )
+ NEW Metal2 ( 319760 168560 ) ( * 174160 )
+ NEW Metal2 ( 336560 161840 ) ( * 169680 )
+ NEW Metal3 ( 319760 169680 ) ( 336560 * )
+ NEW Metal2 ( 342160 138320 ) ( * 162960 )
+ NEW Metal1 ( 336560 162960 ) ( 342160 * )
+ NEW Metal2 ( 343280 137200 ) ( 346640 * )
+ NEW Metal2 ( 343280 137200 ) ( * 138320 )
+ NEW Metal2 ( 342160 138320 ) ( 343280 * )
+ NEW Metal3 ( 333200 130480 ) ( 342160 * )
+ NEW Metal2 ( 342160 130480 ) ( * 138320 )
+ NEW Metal2 ( 324240 129360 ) ( * 130480 )
+ NEW Metal3 ( 324240 130480 ) ( 333200 * )
+ NEW Metal2 ( 318640 174160 ) ( 319760 * )
+ NEW Metal3 ( 232400 406000 ) ( 319200 * )
+ NEW Metal3 ( 319200 404880 ) ( * 406000 )
+ NEW Metal3 ( 319200 404880 ) ( 445200 * )
+ NEW Metal2 ( 230160 233520 ) ( 231280 * )
+ NEW Metal2 ( 230160 233520 ) ( * 246960 )
+ NEW Metal2 ( 229040 246960 ) ( 230160 * )
+ NEW Metal2 ( 229040 223440 ) ( 230160 * )
+ NEW Metal2 ( 230160 223440 ) ( * 233520 )
+ NEW Metal2 ( 241360 175280 ) ( * 197680 )
+ NEW Metal2 ( 240240 197680 ) ( 241360 * )
+ NEW Metal2 ( 240240 197680 ) ( * 218960 )
+ NEW Metal3 ( 230160 218960 ) ( 240240 * )
+ NEW Metal2 ( 230160 218960 ) ( * 223440 )
+ NEW Metal2 ( 245840 170800 ) ( * 175280 )
+ NEW Metal3 ( 241360 175280 ) ( 245840 * )
+ NEW Metal2 ( 229040 246960 ) ( * 319200 )
+ NEW Metal2 ( 241360 143920 ) ( * 175280 )
+ NEW Metal3 ( 245840 173040 ) ( 318640 * )
+ NEW Metal2 ( 318640 173040 ) Via2_VH
+ NEW Metal1 ( 241360 143920 ) Via1_VV
+ NEW Metal1 ( 244720 130480 ) Via1_VV
+ NEW Metal1 ( 244720 131600 ) Via1_HV
+ NEW Metal1 ( 241360 131600 ) Via1_HV
+ NEW Metal1 ( 232400 406000 ) Via1_VV
+ NEW Metal2 ( 232400 406000 ) Via2_VH
+ NEW Metal1 ( 226800 406000 ) Via1_VV
+ NEW Metal2 ( 226800 406000 ) Via2_VH
+ NEW Metal1 ( 224560 365680 ) Via1_VV
+ NEW Metal1 ( 218960 363440 ) Via1_VV
+ NEW Metal2 ( 218960 363440 ) Via2_VH
+ NEW Metal2 ( 224560 363440 ) Via2_VH
+ NEW Metal1 ( 513520 427280 ) Via1_HV
+ NEW Metal2 ( 513520 427280 ) Via2_VH
+ NEW Metal1 ( 518000 427280 ) Via1_VV
+ NEW Metal2 ( 518000 427280 ) Via2_VH
+ NEW Metal1 ( 463120 411600 ) Via1_HV
+ NEW Metal2 ( 463120 411600 ) Via2_VH
+ NEW Metal2 ( 513520 411600 ) Via2_VH
+ NEW Metal1 ( 454160 411600 ) Via1_VV
+ NEW Metal2 ( 454160 411600 ) Via2_VH
+ NEW Metal1 ( 445200 404880 ) Via1_VV
+ NEW Metal2 ( 445200 410480 ) Via2_VH
+ NEW Metal2 ( 445200 404880 ) Via2_VH
+ NEW Metal1 ( 323120 168560 ) Via1_VV
+ NEW Metal1 ( 336560 161840 ) Via1_VV
+ NEW Metal2 ( 336560 169680 ) Via2_VH
+ NEW Metal2 ( 319760 169680 ) Via2_VH
+ NEW Metal1 ( 342160 138320 ) Via1_VV
+ NEW Metal1 ( 342160 162960 ) Via1_HV
+ NEW Metal1 ( 336560 162960 ) Via1_HV
+ NEW Metal1 ( 346640 137200 ) Via1_VV
+ NEW Metal1 ( 333200 130480 ) Via1_VV
+ NEW Metal2 ( 333200 130480 ) Via2_VH
+ NEW Metal2 ( 342160 130480 ) Via2_VH
+ NEW Metal1 ( 324240 129360 ) Via1_VV
+ NEW Metal2 ( 324240 130480 ) Via2_VH
+ NEW Metal1 ( 231280 233520 ) Via1_VV
+ NEW Metal1 ( 229040 223440 ) Via1_VV
+ NEW Metal1 ( 241360 175280 ) Via1_VV
+ NEW Metal2 ( 240240 218960 ) Via2_VH
+ NEW Metal2 ( 230160 218960 ) Via2_VH
+ NEW Metal1 ( 245840 170800 ) Via1_VV
+ NEW Metal2 ( 245840 175280 ) Via2_VH
+ NEW Metal2 ( 241360 175280 ) Via2_VH
+ NEW Metal2 ( 245840 173040 ) Via2_VH
+ NEW Metal2 ( 232400 406000 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 226800 406000 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 218960 363440 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 513520 427280 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 518000 427280 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 463120 411600 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 454160 411600 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 445200 404880 ) RECT ( -280 -1040 280 0 )
+ NEW Metal2 ( 319760 169680 ) RECT ( -280 -1040 280 0 )
+ NEW Metal2 ( 336560 162960 ) RECT ( -280 -1040 280 0 )
+ NEW Metal2 ( 333200 130480 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 241360 175280 ) RECT ( -280 -1040 280 0 )
+ NEW Metal2 ( 245840 173040 ) RECT ( -280 -1040 280 0 ) ;
+ - _0417_ ( _1034_ A2 ) ( _1033_ Z ) + USE SIGNAL
+ + ROUTED Metal2 ( 238000 216720 ) ( 239120 * )
+ NEW Metal2 ( 239120 216720 ) ( * 222320 )
+ NEW Metal2 ( 239120 222320 ) ( 243600 * )
+ NEW Metal1 ( 238000 216720 ) Via1_VV
+ NEW Metal1 ( 243600 222320 ) Via1_VV ;
+ - _0418_ ( _1070_ A4 ) ( _1055_ A2 ) ( _1036_ A1 ) ( _1035_ ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 285040 96880 ) ( * 103600 )
+ NEW Metal3 ( 285040 96880 ) ( 298480 * )
+ NEW Metal3 ( 267120 96880 ) ( 285040 * )
+ NEW Metal3 ( 298480 96880 ) ( 333200 * )
+ NEW Metal1 ( 298480 96880 ) Via1_HV
+ NEW Metal2 ( 298480 96880 ) Via2_VH
+ NEW Metal1 ( 285040 103600 ) Via1_VV
+ NEW Metal2 ( 285040 96880 ) Via2_VH
+ NEW Metal1 ( 267120 96880 ) Via1_VV
+ NEW Metal2 ( 267120 96880 ) Via2_VH
+ NEW Metal1 ( 333200 96880 ) Via1_VV
+ NEW Metal2 ( 333200 96880 ) Via2_VH
+ NEW Metal2 ( 298480 96880 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 267120 96880 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 333200 96880 ) RECT ( -280 -660 280 0 ) ;
+ - _0419_ ( ANTENNA__1038__A1 I ) ( ANTENNA__1055__A1 I ) ( ANTENNA__1066__B2 I ) ( ANTENNA__1070__A3 I ) ( _1070_ A3 ) ( _1066_ B2 ) ( _1055_ A1 )
+ ( _1038_ A1 ) ( _1037_ ZN ) + USE SIGNAL
+ + ROUTED Metal3 ( 287280 98000 ) ( 304080 * )
+ NEW Metal2 ( 291760 92400 ) ( * 98000 )
+ NEW Metal3 ( 285040 84560 ) ( 291760 * )
+ NEW Metal2 ( 291760 84560 ) ( * 92400 )
+ NEW Metal3 ( 273840 98000 ) ( 287280 * )
+ NEW Metal2 ( 281680 98000 ) ( * 105840 )
+ NEW Metal2 ( 282800 111440 ) ( 283920 * )
+ NEW Metal2 ( 282800 105840 ) ( * 111440 )
+ NEW Metal2 ( 281680 105840 ) ( 282800 * )
+ NEW Metal2 ( 343280 96880 ) ( * 98000 )
+ NEW Metal3 ( 343280 98000 ) ( 348880 * )
+ NEW Metal3 ( 304080 98000 ) ( 343280 * )
+ NEW Metal1 ( 304080 98000 ) Via1_HV
+ NEW Metal2 ( 304080 98000 ) Via2_VH
+ NEW Metal1 ( 287280 98000 ) Via1_VV
+ NEW Metal2 ( 287280 98000 ) Via2_VH
+ NEW Metal1 ( 291760 92400 ) Via1_VV
+ NEW Metal2 ( 291760 98000 ) Via2_VH
+ NEW Metal1 ( 285040 84560 ) Via1_VV
+ NEW Metal2 ( 285040 84560 ) Via2_VH
+ NEW Metal2 ( 291760 84560 ) Via2_VH
+ NEW Metal1 ( 273840 98000 ) Via1_VV
+ NEW Metal2 ( 273840 98000 ) Via2_VH
+ NEW Metal1 ( 281680 105840 ) Via1_HV
+ NEW Metal2 ( 281680 98000 ) Via2_VH
+ NEW Metal1 ( 283920 111440 ) Via1_VV
+ NEW Metal1 ( 343280 96880 ) Via1_VV
+ NEW Metal2 ( 343280 98000 ) Via2_VH
+ NEW Metal1 ( 348880 98000 ) Via1_VV
+ NEW Metal2 ( 348880 98000 ) Via2_VH
+ NEW Metal2 ( 304080 98000 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 287280 98000 ) RECT ( -280 -660 280 0 )
+ NEW Metal3 ( 291760 98000 ) RECT ( -1040 -280 0 280 )
+ NEW Metal2 ( 285040 84560 ) RECT ( -280 0 280 660 )
+ NEW Metal2 ( 273840 98000 ) RECT ( -280 -660 280 0 )
+ NEW Metal3 ( 281680 98000 ) RECT ( -1040 -280 0 280 )
+ NEW Metal2 ( 348880 98000 ) RECT ( -280 -660 280 0 ) ;
+ - _0420_ ( _1070_ A2 ) ( _1040_ A1 ) ( _1039_ ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 315280 98000 ) ( * 100240 )
+ NEW Metal3 ( 315280 100240 ) ( 319200 * )
+ NEW Metal3 ( 322000 99120 ) ( 330960 * )
+ NEW Metal2 ( 330960 99120 ) ( * 111440 )
+ NEW Metal3 ( 319200 99120 ) ( * 100240 )
+ NEW Metal3 ( 319200 99120 ) ( 322000 * )
+ NEW Metal1 ( 315280 98000 ) Via1_HV
+ NEW Metal2 ( 315280 100240 ) Via2_VH
+ NEW Metal1 ( 322000 99120 ) Via1_VV
+ NEW Metal2 ( 322000 99120 ) Via2_VH
+ NEW Metal2 ( 330960 99120 ) Via2_VH
+ NEW Metal1 ( 330960 111440 ) Via1_VV
+ NEW Metal2 ( 322000 99120 ) RECT ( -280 -660 280 0 ) ;
+ - _0421_ ( _1043_ A2 ) ( _1042_ ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 311920 123760 ) ( * 129360 )
+ NEW Metal2 ( 311920 129360 ) ( 317520 * )
+ NEW Metal1 ( 311920 123760 ) Via1_VV
+ NEW Metal1 ( 317520 129360 ) Via1_VV ;
+ - _0422_ ( ANTENNA__1046__A1 I ) ( ANTENNA__1052__B I ) ( ANTENNA__1143__B I ) ( ANTENNA__1152__A1 I ) ( ANTENNA__1203__A1 I ) ( ANTENNA__1247__B I ) ( ANTENNA__1255__A1 I )
+ ( ANTENNA__1307__A1 I ) ( ANTENNA__1309__A1 I ) ( ANTENNA__1345__A1 I ) ( _1345_ A1 ) ( _1309_ A1 ) ( _1307_ A1 ) ( _1255_ A1 ) ( _1247_ B )
+ ( _1203_ A1 ) ( _1152_ A1 ) ( _1143_ B ) ( _1052_ B ) ( _1046_ A1 ) ( _1044_ Z ) + USE SIGNAL
+ + ROUTED Metal3 ( 268240 449680 ) ( 277200 * )
+ NEW Metal3 ( 277200 448560 ) ( * 449680 )
+ NEW Metal3 ( 258160 449680 ) ( 268240 * )
+ NEW Metal2 ( 277200 449680 ) ( * 464240 )
+ NEW Metal2 ( 285040 468720 ) ( * 472080 )
+ NEW Metal2 ( 277200 468720 ) ( 285040 * )
+ NEW Metal2 ( 277200 464240 ) ( * 468720 )
+ NEW Metal2 ( 255920 327600 ) ( * 353360 )
+ NEW Metal2 ( 255920 353360 ) ( 257040 * )
+ NEW Metal2 ( 257040 353360 ) ( * 357840 )
+ NEW Metal2 ( 255920 357840 ) ( 257040 * )
+ NEW Metal2 ( 255920 357840 ) ( * 395920 )
+ NEW Metal2 ( 254800 395920 ) ( 255920 * )
+ NEW Metal2 ( 254800 395920 ) ( * 422800 )
+ NEW Metal2 ( 254800 422800 ) ( 258160 * )
+ NEW Metal3 ( 235760 323120 ) ( 255920 * )
+ NEW Metal2 ( 255920 323120 ) ( * 327600 )
+ NEW Metal2 ( 258160 422800 ) ( * 449680 )
+ NEW Metal2 ( 501200 403760 ) ( 502320 * )
+ NEW Metal2 ( 502320 363440 ) ( * 403760 )
+ NEW Metal3 ( 493360 363440 ) ( 502320 * )
+ NEW Metal2 ( 502320 403760 ) ( 505680 * )
+ NEW Metal3 ( 504560 410480 ) ( 519120 * )
+ NEW Metal2 ( 504560 403760 ) ( * 410480 )
+ NEW Metal2 ( 526960 402640 ) ( * 410480 )
+ NEW Metal3 ( 519120 410480 ) ( 526960 * )
+ NEW Metal2 ( 526960 410480 ) ( * 425040 )
+ NEW Metal2 ( 535920 419440 ) ( * 427280 )
+ NEW Metal3 ( 526960 419440 ) ( 535920 * )
+ NEW Metal3 ( 438480 402640 ) ( * 403760 )
+ NEW Metal3 ( 438480 402640 ) ( 451920 * )
+ NEW Metal3 ( 451920 402640 ) ( * 403760 )
+ NEW Metal3 ( 451920 403760 ) ( 501200 * )
+ NEW Metal3 ( 374640 440720 ) ( 422800 * )
+ NEW Metal2 ( 348880 440720 ) ( * 442960 )
+ NEW Metal3 ( 348880 440720 ) ( 374640 * )
+ NEW Metal2 ( 348880 442960 ) ( * 448560 )
+ NEW Metal3 ( 277200 448560 ) ( 348880 * )
+ NEW Metal2 ( 344400 188720 ) ( * 189840 )
+ NEW Metal2 ( 339920 188720 ) ( * 190960 )
+ NEW Metal3 ( 339920 188720 ) ( 344400 * )
+ NEW Metal3 ( 335440 155120 ) ( 344400 * )
+ NEW Metal2 ( 344400 155120 ) ( * 188720 )
+ NEW Metal2 ( 327600 152880 ) ( * 155120 )
+ NEW Metal3 ( 327600 155120 ) ( 335440 * )
+ NEW Metal2 ( 430640 410480 ) ( * 418320 )
+ NEW Metal2 ( 430640 410480 ) ( 431760 * )
+ NEW Metal2 ( 431760 403760 ) ( * 410480 )
+ NEW Metal2 ( 421680 418320 ) ( * 419440 )
+ NEW Metal3 ( 421680 418320 ) ( 430640 * )
+ NEW Metal2 ( 421680 419440 ) ( 422800 * )
+ NEW Metal2 ( 422800 419440 ) ( * 440720 )
+ NEW Metal3 ( 431760 403760 ) ( 438480 * )
+ NEW Metal2 ( 498960 224560 ) ( 500080 * )
+ NEW Metal2 ( 498960 213360 ) ( * 224560 )
+ NEW Metal2 ( 493360 213360 ) ( 498960 * )
+ NEW Metal2 ( 493360 188720 ) ( * 213360 )
+ NEW Metal2 ( 492240 239120 ) ( 493360 * )
+ NEW Metal2 ( 492240 224560 ) ( * 239120 )
+ NEW Metal3 ( 492240 224560 ) ( 498960 * )
+ NEW Metal3 ( 344400 188720 ) ( 493360 * )
+ NEW Metal2 ( 493360 239120 ) ( * 363440 )
+ NEW Metal1 ( 268240 449680 ) Via1_VV
+ NEW Metal2 ( 268240 449680 ) Via2_VH
+ NEW Metal1 ( 258160 449680 ) Via1_VV
+ NEW Metal2 ( 258160 449680 ) Via2_VH
+ NEW Metal1 ( 277200 464240 ) Via1_VV
+ NEW Metal2 ( 277200 449680 ) Via2_VH
+ NEW Metal1 ( 285040 472080 ) Via1_VV
+ NEW Metal1 ( 255920 327600 ) Via1_VV
+ NEW Metal1 ( 235760 323120 ) Via1_VV
+ NEW Metal2 ( 235760 323120 ) Via2_VH
+ NEW Metal2 ( 255920 323120 ) Via2_VH
+ NEW Metal1 ( 501200 403760 ) Via1_VV
+ NEW Metal2 ( 502320 363440 ) Via2_VH
+ NEW Metal2 ( 493360 363440 ) Via2_VH
+ NEW Metal1 ( 505680 403760 ) Via1_VV
+ NEW Metal1 ( 519120 410480 ) Via1_VV
+ NEW Metal2 ( 519120 410480 ) Via2_VH
+ NEW Metal2 ( 504560 410480 ) Via2_VH
+ NEW Metal1 ( 526960 402640 ) Via1_VV
+ NEW Metal2 ( 526960 410480 ) Via2_VH
+ NEW Metal1 ( 526960 425040 ) Via1_VV
+ NEW Metal1 ( 535920 427280 ) Via1_VV
+ NEW Metal2 ( 535920 419440 ) Via2_VH
+ NEW Metal2 ( 526960 419440 ) Via2_VH
+ NEW Metal2 ( 501200 403760 ) Via2_VH
+ NEW Metal1 ( 374640 440720 ) Via1_VV
+ NEW Metal2 ( 374640 440720 ) Via2_VH
+ NEW Metal2 ( 422800 440720 ) Via2_VH
+ NEW Metal1 ( 348880 442960 ) Via1_VV
+ NEW Metal2 ( 348880 440720 ) Via2_VH
+ NEW Metal2 ( 348880 448560 ) Via2_VH
+ NEW Metal1 ( 344400 189840 ) Via1_VV
+ NEW Metal2 ( 344400 188720 ) Via2_VH
+ NEW Metal1 ( 339920 190960 ) Via1_VV
+ NEW Metal2 ( 339920 188720 ) Via2_VH
+ NEW Metal1 ( 335440 155120 ) Via1_VV
+ NEW Metal2 ( 335440 155120 ) Via2_VH
+ NEW Metal2 ( 344400 155120 ) Via2_VH
+ NEW Metal1 ( 327600 152880 ) Via1_VV
+ NEW Metal2 ( 327600 155120 ) Via2_VH
+ NEW Metal1 ( 430640 418320 ) Via1_VV
+ NEW Metal2 ( 431760 403760 ) Via2_VH
+ NEW Metal1 ( 421680 419440 ) Via1_VV
+ NEW Metal2 ( 421680 418320 ) Via2_VH
+ NEW Metal2 ( 430640 418320 ) Via2_VH
+ NEW Metal1 ( 500080 224560 ) Via1_HV
+ NEW Metal2 ( 493360 188720 ) Via2_VH
+ NEW Metal2 ( 492240 224560 ) Via2_VH
+ NEW Metal2 ( 498960 224560 ) Via2_VH
+ NEW Metal2 ( 268240 449680 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 258160 449680 ) RECT ( -280 -660 280 0 )
+ NEW Metal3 ( 277200 449680 ) RECT ( -1040 -280 0 280 )
+ NEW Metal2 ( 235760 323120 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 519120 410480 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 526960 419440 ) RECT ( -280 -1040 280 0 )
+ NEW Metal2 ( 501200 403760 ) RECT ( -280 -1040 280 0 )
+ NEW Metal2 ( 374640 440720 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 335440 155120 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 430640 418320 ) RECT ( -280 -1040 280 0 )
+ NEW Metal2 ( 498960 224560 ) RECT ( -280 -1040 280 0 ) ;
+ - _0423_ ( _1046_ A3 ) ( _1045_ ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 326480 139440 ) ( * 152880 )
+ NEW Metal2 ( 324240 152880 ) ( 326480 * )
+ NEW Metal1 ( 326480 139440 ) Via1_VV
+ NEW Metal1 ( 324240 152880 ) Via1_VV ;
+ - _0424_ ( _1048_ A2 ) ( _1047_ ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 336560 138320 ) ( * 142800 )
+ NEW Metal3 ( 309680 142800 ) ( 336560 * )
+ NEW Metal1 ( 309680 142800 ) Via1_VV
+ NEW Metal2 ( 309680 142800 ) Via2_VH
+ NEW Metal1 ( 336560 138320 ) Via1_VV
+ NEW Metal2 ( 336560 142800 ) Via2_VH
+ NEW Metal2 ( 309680 142800 ) RECT ( -280 -660 280 0 ) ;
+ - _0425_ ( _1050_ A2 ) ( _1049_ ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 328720 160720 ) ( * 168560 )
+ NEW Metal1 ( 328720 160720 ) Via1_VV
+ NEW Metal1 ( 328720 168560 ) Via1_VV ;
+ - _0426_ ( _1052_ A2 ) ( _1051_ ZN ) + USE SIGNAL
+ + ROUTED Metal3 ( 323120 176400 ) ( 334320 * )
+ NEW Metal2 ( 334320 176400 ) ( * 190960 )
+ NEW Metal1 ( 323120 176400 ) Via1_VV
+ NEW Metal2 ( 323120 176400 ) Via2_VH
+ NEW Metal2 ( 334320 176400 ) Via2_VH
+ NEW Metal1 ( 334320 190960 ) Via1_VV
+ NEW Metal2 ( 323120 176400 ) RECT ( -280 -660 280 0 ) ;
+ - _0427_ ( _1054_ A2 ) ( _1053_ Z ) + USE SIGNAL
+ + ROUTED Metal2 ( 333200 178640 ) ( * 190960 )
+ NEW Metal2 ( 328720 190960 ) ( 333200 * )
+ NEW Metal1 ( 333200 178640 ) Via1_VV
+ NEW Metal1 ( 328720 190960 ) Via1_VV ;
+ - _0428_ ( _1067_ A2 ) ( _1066_ A2 ) ( _1056_ A2 ) ( _1055_ ZN ) + USE SIGNAL
+ + ROUTED Metal3 ( 283920 105840 ) ( 316400 * )
+ NEW Metal2 ( 280560 100240 ) ( * 105840 )
+ NEW Metal3 ( 280560 105840 ) ( 283920 * )
+ NEW Metal3 ( 266000 105840 ) ( 280560 * )
+ NEW Metal1 ( 283920 105840 ) Via1_VV
+ NEW Metal2 ( 283920 105840 ) Via2_VH
+ NEW Metal1 ( 316400 105840 ) Via1_VV
+ NEW Metal2 ( 316400 105840 ) Via2_VH
+ NEW Metal1 ( 280560 100240 ) Via1_VV
+ NEW Metal2 ( 280560 105840 ) Via2_VH
+ NEW Metal1 ( 266000 105840 ) Via1_VV
+ NEW Metal2 ( 266000 105840 ) Via2_VH
+ NEW Metal2 ( 283920 105840 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 316400 105840 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 266000 105840 ) RECT ( -280 -660 280 0 ) ;
+ - _0429_ ( _1071_ A1 ) ( _1057_ A2 ) ( _1056_ ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 295120 105840 ) ( * 137200 )
+ NEW Metal3 ( 295120 108080 ) ( 319760 * )
+ NEW Metal1 ( 295120 105840 ) Via1_VV
+ NEW Metal1 ( 295120 137200 ) Via1_VV
+ NEW Metal2 ( 295120 108080 ) Via2_VH
+ NEW Metal1 ( 319760 108080 ) Via1_VV
+ NEW Metal2 ( 319760 108080 ) Via2_VH
+ NEW Metal2 ( 295120 108080 ) RECT ( -280 -1040 280 0 )
+ NEW Metal2 ( 319760 108080 ) RECT ( -280 -660 280 0 ) ;
+ - _0430_ ( _1058_ A2 ) ( _1057_ ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 298480 139440 ) ( * 140560 )
+ NEW Metal2 ( 296240 140560 ) ( 298480 * )
+ NEW Metal2 ( 296240 140560 ) ( * 143920 )
+ NEW Metal1 ( 298480 139440 ) Via1_VV
+ NEW Metal1 ( 296240 143920 ) Via1_VV ;
+ - _0431_ ( _1059_ I ) ( _1058_ ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 297360 147280 ) ( 298480 * )
+ NEW Metal2 ( 298480 147280 ) ( * 159600 )
+ NEW Metal2 ( 297360 159600 ) ( 298480 * )
+ NEW Metal1 ( 297360 147280 ) Via1_VV
+ NEW Metal1 ( 297360 159600 ) Via1_VV ;
+ - _0432_ ( _1093_ A2 ) ( _1060_ A2 ) ( _1059_ ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 278320 161840 ) ( * 198800 )
+ NEW Metal3 ( 278320 162960 ) ( 296240 * )
+ NEW Metal1 ( 278320 161840 ) Via1_VV
+ NEW Metal1 ( 278320 198800 ) Via1_VV
+ NEW Metal1 ( 296240 162960 ) Via1_VV
+ NEW Metal2 ( 296240 162960 ) Via2_VH
+ NEW Metal2 ( 278320 162960 ) Via2_VH
+ NEW Metal2 ( 296240 162960 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 278320 162960 ) RECT ( -280 -1040 280 0 ) ;
+ - _0433_ ( ANTENNA__1061__A2 I ) ( ANTENNA__1065__A2 I ) ( ANTENNA__1068__B1 I ) ( ANTENNA__1076__B1 I ) ( ANTENNA__1080__B1 I ) ( ANTENNA__1085__B1 I ) ( ANTENNA__1089__B1 I )
+ ( _1089_ B1 ) ( _1085_ B1 ) ( _1080_ B1 ) ( _1076_ B1 ) ( _1068_ B1 ) ( _1065_ A2 ) ( _1061_ A2 ) ( _1060_ ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 252560 113680 ) ( * 121520 )
+ NEW Metal3 ( 239120 121520 ) ( 252560 * )
+ NEW Metal2 ( 259280 114800 ) ( * 121520 )
+ NEW Metal3 ( 252560 121520 ) ( 259280 * )
+ NEW Metal2 ( 259280 121520 ) ( 260400 * )
+ NEW Metal2 ( 264880 121520 ) ( * 142800 )
+ NEW Metal3 ( 259280 121520 ) ( 264880 * )
+ NEW Metal2 ( 232400 131600 ) ( * 142800 )
+ NEW Metal2 ( 232400 131600 ) ( 233520 * )
+ NEW Metal2 ( 233520 121520 ) ( * 131600 )
+ NEW Metal3 ( 233520 121520 ) ( 239120 * )
+ NEW Metal3 ( 264880 142800 ) ( 276080 * )
+ NEW Metal2 ( 280560 142800 ) ( * 159600 )
+ NEW Metal3 ( 276080 142800 ) ( 280560 * )
+ NEW Metal2 ( 280560 151760 ) ( 282800 * )
+ NEW Metal2 ( 280560 159600 ) ( 286160 * )
+ NEW Metal2 ( 280560 159600 ) ( * 169680 )
+ NEW Metal2 ( 269360 169680 ) ( * 174160 )
+ NEW Metal2 ( 274960 169680 ) ( * 174160 )
+ NEW Metal2 ( 280560 169680 ) ( * 175280 )
+ NEW Metal2 ( 258160 170800 ) ( * 174160 )
+ NEW Metal3 ( 239120 170800 ) ( 258160 * )
+ NEW Metal3 ( 258160 169680 ) ( * 170800 )
+ NEW Metal3 ( 258160 169680 ) ( 280560 * )
+ NEW Metal1 ( 252560 113680 ) Via1_VV
+ NEW Metal2 ( 252560 121520 ) Via2_VH
+ NEW Metal1 ( 239120 121520 ) Via1_VV
+ NEW Metal2 ( 239120 121520 ) Via2_VH
+ NEW Metal1 ( 259280 114800 ) Via1_VV
+ NEW Metal2 ( 259280 121520 ) Via2_VH
+ NEW Metal1 ( 260400 121520 ) Via1_VV
+ NEW Metal1 ( 264880 142800 ) Via1_VV
+ NEW Metal2 ( 264880 121520 ) Via2_VH
+ NEW Metal1 ( 232400 142800 ) Via1_VV
+ NEW Metal2 ( 233520 121520 ) Via2_VH
+ NEW Metal1 ( 276080 142800 ) Via1_VV
+ NEW Metal2 ( 276080 142800 ) Via2_VH
+ NEW Metal2 ( 264880 142800 ) Via2_VH
+ NEW Metal1 ( 280560 159600 ) Via1_VV
+ NEW Metal2 ( 280560 142800 ) Via2_VH
+ NEW Metal1 ( 282800 151760 ) Via1_VV
+ NEW Metal1 ( 286160 159600 ) Via1_VV
+ NEW Metal2 ( 280560 169680 ) Via2_VH
+ NEW Metal1 ( 269360 174160 ) Via1_VV
+ NEW Metal2 ( 269360 169680 ) Via2_VH
+ NEW Metal1 ( 274960 174160 ) Via1_VV
+ NEW Metal2 ( 274960 169680 ) Via2_VH
+ NEW Metal1 ( 280560 175280 ) Via1_VV
+ NEW Metal1 ( 258160 174160 ) Via1_VV
+ NEW Metal2 ( 258160 170800 ) Via2_VH
+ NEW Metal1 ( 239120 170800 ) Via1_VV
+ NEW Metal2 ( 239120 170800 ) Via2_VH
+ NEW Metal2 ( 239120 121520 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 276080 142800 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 264880 142800 ) RECT ( -280 -1040 280 0 )
+ NEW Metal3 ( 269360 169680 ) RECT ( -1040 -280 0 280 )
+ NEW Metal3 ( 274960 169680 ) RECT ( -1040 -280 0 280 )
+ NEW Metal2 ( 239120 170800 ) RECT ( -280 -660 280 0 ) ;
+ - _0434_ ( _1063_ B ) ( _1061_ ZN ) + USE SIGNAL
+ + ROUTED Metal3 ( 282800 177520 ) ( 285040 * )
+ NEW Metal3 ( 285040 177520 ) ( * 178640 )
+ NEW Metal2 ( 285040 178640 ) ( * 182000 )
+ NEW Metal1 ( 282800 177520 ) Via1_HV
+ NEW Metal2 ( 282800 177520 ) Via2_VH
+ NEW Metal2 ( 285040 178640 ) Via2_VH
+ NEW Metal1 ( 285040 182000 ) Via1_VV
+ NEW Metal2 ( 282800 177520 ) RECT ( -280 -660 280 0 ) ;
+ - _0435_ ( ANTENNA__1063__C I ) ( ANTENNA__1115__A1 I ) ( ANTENNA__1147__C I ) ( ANTENNA__1155__C I ) ( ANTENNA__1206__C I ) ( ANTENNA__1250__C I ) ( ANTENNA__1258__C I )
+ ( ANTENNA__1277__C I ) ( ANTENNA__1300__A1 I ) ( ANTENNA__1304__C I ) ( _1304_ C ) ( _1300_ A1 ) ( _1277_ C ) ( _1258_ C ) ( _1250_ C )
+ ( _1206_ C ) ( _1155_ C ) ( _1147_ C ) ( _1115_ A1 ) ( _1063_ C ) ( _1062_ Z ) + USE SIGNAL
+ + ROUTED Metal3 ( 305200 456400 ) ( 310800 * )
+ NEW Metal2 ( 512400 277200 ) ( 514640 * )
+ NEW Metal2 ( 534800 458640 ) ( * 459760 )
+ NEW Metal3 ( 521360 459760 ) ( 534800 * )
+ NEW Metal2 ( 521360 439600 ) ( * 459760 )
+ NEW Metal2 ( 520240 439600 ) ( 521360 * )
+ NEW Metal2 ( 520240 438480 ) ( * 439600 )
+ NEW Metal2 ( 519120 438480 ) ( 520240 * )
+ NEW Metal3 ( 534800 459760 ) ( 547120 * )
+ NEW Metal2 ( 297360 177520 ) ( * 183120 )
+ NEW Metal3 ( 288400 184240 ) ( 297360 * )
+ NEW Metal2 ( 297360 183120 ) ( * 184240 )
+ NEW Metal3 ( 295120 428400 ) ( 305200 * )
+ NEW Metal3 ( 283920 428400 ) ( 295120 * )
+ NEW Metal2 ( 305200 428400 ) ( * 458640 )
+ NEW Metal2 ( 512400 201600 ) ( * 277200 )
+ NEW Metal2 ( 511280 178640 ) ( * 201600 )
+ NEW Metal2 ( 511280 201600 ) ( 512400 * )
+ NEW Metal2 ( 514640 277200 ) ( * 319200 )
+ NEW Metal4 ( 437360 350000 ) ( * 435120 )
+ NEW Metal3 ( 437360 388080 ) ( 475440 * )
+ NEW Metal3 ( 475440 388080 ) ( 487760 * )
+ NEW Metal2 ( 518000 374640 ) ( * 375760 )
+ NEW Metal3 ( 518000 375760 ) ( * 378000 )
+ NEW Metal3 ( 505680 378000 ) ( 518000 * )
+ NEW Metal2 ( 505680 378000 ) ( * 386960 )
+ NEW Metal3 ( 487760 386960 ) ( 505680 * )
+ NEW Metal3 ( 487760 386960 ) ( * 388080 )
+ NEW Metal2 ( 519120 434000 ) ( 521360 * )
+ NEW Metal2 ( 521360 417200 ) ( * 434000 )
+ NEW Metal2 ( 521360 417200 ) ( 522480 * )
+ NEW Metal2 ( 522480 393680 ) ( * 417200 )
+ NEW Metal2 ( 521360 393680 ) ( 522480 * )
+ NEW Metal2 ( 521360 378000 ) ( * 393680 )
+ NEW Metal3 ( 518000 378000 ) ( 521360 * )
+ NEW Metal2 ( 529200 372400 ) ( * 378000 )
+ NEW Metal3 ( 521360 378000 ) ( 529200 * )
+ NEW Metal2 ( 514640 319200 ) ( 518000 * )
+ NEW Metal2 ( 518000 319200 ) ( * 374640 )
+ NEW Metal2 ( 519120 434000 ) ( * 438480 )
+ NEW Metal3 ( 310800 456400 ) ( 319200 * )
+ NEW Metal3 ( 409360 487760 ) ( 422800 * )
+ NEW Metal2 ( 422800 457520 ) ( * 487760 )
+ NEW Metal2 ( 422800 457520 ) ( 423920 * )
+ NEW Metal2 ( 423920 450800 ) ( * 457520 )
+ NEW Metal2 ( 423920 450800 ) ( 425040 * )
+ NEW Metal3 ( 402640 488880 ) ( 409360 * )
+ NEW Metal3 ( 409360 487760 ) ( * 488880 )
+ NEW Metal2 ( 358960 458640 ) ( * 460880 )
+ NEW Metal3 ( 358960 460880 ) ( 402640 * )
+ NEW Metal2 ( 402640 460880 ) ( * 488880 )
+ NEW Metal2 ( 355600 460880 ) ( * 465360 )
+ NEW Metal3 ( 355600 460880 ) ( 358960 * )
+ NEW Metal3 ( 319200 456400 ) ( * 460880 )
+ NEW Metal3 ( 319200 460880 ) ( 355600 * )
+ NEW Metal3 ( 297360 177520 ) ( 319200 * )
+ NEW Metal3 ( 319200 177520 ) ( * 178640 )
+ NEW Metal3 ( 436800 435120 ) ( 437360 * )
+ NEW Metal2 ( 398160 348880 ) ( * 350000 )
+ NEW Metal2 ( 401520 343280 ) ( * 350000 )
+ NEW Metal3 ( 428400 434000 ) ( 436800 * )
+ NEW Metal3 ( 436800 434000 ) ( * 435120 )
+ NEW Metal2 ( 423920 434000 ) ( * 435120 )
+ NEW Metal3 ( 423920 434000 ) ( 428400 * )
+ NEW Metal2 ( 423920 435120 ) ( 425040 * )
+ NEW Metal2 ( 425040 435120 ) ( * 450800 )
+ NEW Metal3 ( 398160 350000 ) ( 437360 * )
+ NEW Metal3 ( 319200 178640 ) ( 511280 * )
+ NEW Metal1 ( 305200 458640 ) Via1_HV
+ NEW Metal1 ( 310800 456400 ) Via1_VV
+ NEW Metal2 ( 310800 456400 ) Via2_VH
+ NEW Metal2 ( 305200 456400 ) Via2_VH
+ NEW Metal1 ( 512400 277200 ) Via1_HV
+ NEW Metal1 ( 534800 458640 ) Via1_HV
+ NEW Metal2 ( 534800 459760 ) Via2_VH
+ NEW Metal2 ( 521360 459760 ) Via2_VH
+ NEW Metal1 ( 547120 459760 ) Via1_VV
+ NEW Metal2 ( 547120 459760 ) Via2_VH
+ NEW Metal1 ( 297360 183120 ) Via1_VV
+ NEW Metal2 ( 297360 177520 ) Via2_VH
+ NEW Metal1 ( 288400 184240 ) Via1_HV
+ NEW Metal2 ( 288400 184240 ) Via2_VH
+ NEW Metal2 ( 297360 184240 ) Via2_VH
+ NEW Metal1 ( 295120 428400 ) Via1_VV
+ NEW Metal2 ( 295120 428400 ) Via2_VH
+ NEW Metal2 ( 305200 428400 ) Via2_VH
+ NEW Metal1 ( 283920 428400 ) Via1_VV
+ NEW Metal2 ( 283920 428400 ) Via2_VH
+ NEW Metal2 ( 511280 178640 ) Via2_VH
+ NEW Metal3 ( 437360 350000 ) Via3_HV
+ NEW Metal3 ( 437360 435120 ) Via3_HV
+ NEW Metal1 ( 475440 388080 ) Via1_HV
+ NEW Metal2 ( 475440 388080 ) Via2_VH
+ NEW Metal3 ( 437360 388080 ) Via3_HV
+ NEW Metal1 ( 487760 388080 ) Via1_VV
+ NEW Metal2 ( 487760 388080 ) Via2_VH
+ NEW Metal1 ( 518000 374640 ) Via1_VV
+ NEW Metal2 ( 518000 375760 ) Via2_VH
+ NEW Metal2 ( 505680 378000 ) Via2_VH
+ NEW Metal2 ( 505680 386960 ) Via2_VH
+ NEW Metal2 ( 521360 378000 ) Via2_VH
+ NEW Metal1 ( 529200 372400 ) Via1_HV
+ NEW Metal2 ( 529200 378000 ) Via2_VH
+ NEW Metal1 ( 409360 487760 ) Via1_VV
+ NEW Metal2 ( 409360 487760 ) Via2_VH
+ NEW Metal2 ( 422800 487760 ) Via2_VH
+ NEW Metal1 ( 402640 488880 ) Via1_VV
+ NEW Metal2 ( 402640 488880 ) Via2_VH
+ NEW Metal1 ( 358960 458640 ) Via1_HV
+ NEW Metal2 ( 358960 460880 ) Via2_VH
+ NEW Metal2 ( 402640 460880 ) Via2_VH
+ NEW Metal1 ( 355600 465360 ) Via1_VV
+ NEW Metal2 ( 355600 460880 ) Via2_VH
+ NEW Metal1 ( 398160 348880 ) Via1_HV
+ NEW Metal2 ( 398160 350000 ) Via2_VH
+ NEW Metal1 ( 401520 343280 ) Via1_VV
+ NEW Metal2 ( 401520 350000 ) Via2_VH
+ NEW Metal1 ( 428400 434000 ) Via1_VV
+ NEW Metal2 ( 428400 434000 ) Via2_VH
+ NEW Metal1 ( 423920 435120 ) Via1_HV
+ NEW Metal2 ( 423920 434000 ) Via2_VH
+ NEW Metal2 ( 310800 456400 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 305200 456400 ) RECT ( -280 -1040 280 0 )
+ NEW Metal2 ( 547120 459760 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 288400 184240 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 295120 428400 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 283920 428400 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 475440 388080 ) RECT ( -280 0 280 660 )
+ NEW Metal4 ( 437360 388080 ) RECT ( -280 -1040 280 0 )
+ NEW Metal2 ( 487760 388080 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 409360 487760 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 402640 488880 ) RECT ( -280 -660 280 0 )
+ NEW Metal3 ( 401520 350000 ) RECT ( -1040 -280 0 280 )
+ NEW Metal2 ( 428400 434000 ) RECT ( -280 -660 280 0 ) ;
+ - _0436_ ( _1066_ A1 ) ( _1064_ ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 276080 98000 ) ( 277200 * )
+ NEW Metal2 ( 276080 98000 ) ( * 103600 )
+ NEW Metal1 ( 277200 98000 ) Via1_HV
+ NEW Metal1 ( 276080 103600 ) Via1_VV ;
+ - _0437_ ( _1074_ A1 ) ( _1071_ A2 ) ( _1066_ A3 ) ( _1065_ ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 287280 121520 ) ( * 123760 )
+ NEW Metal2 ( 287280 123760 ) ( 289520 * )
+ NEW Metal2 ( 289520 123760 ) ( * 158480 )
+ NEW Metal2 ( 292880 105840 ) ( * 126000 )
+ NEW Metal2 ( 289520 126000 ) ( 292880 * )
+ NEW Metal2 ( 282800 100240 ) ( * 101360 )
+ NEW Metal3 ( 282800 101360 ) ( 292880 * )
+ NEW Metal2 ( 292880 101360 ) ( * 105840 )
+ NEW Metal1 ( 287280 121520 ) Via1_VV
+ NEW Metal1 ( 289520 158480 ) Via1_VV
+ NEW Metal1 ( 292880 105840 ) Via1_VV
+ NEW Metal1 ( 282800 100240 ) Via1_VV
+ NEW Metal2 ( 282800 101360 ) Via2_VH
+ NEW Metal2 ( 292880 101360 ) Via2_VH ;
+ - _0438_ ( _1068_ B2 ) ( _1067_ Z ) + USE SIGNAL
+ + ROUTED Metal2 ( 254800 106960 ) ( 257040 * )
+ NEW Metal2 ( 254800 106960 ) ( * 112560 )
+ NEW Metal1 ( 257040 106960 ) Via1_VV
+ NEW Metal1 ( 254800 112560 ) Via1_VV ;
+ - _0439_ ( _1069_ A2 ) ( _1068_ ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 238000 103600 ) ( 240240 * )
+ NEW Metal1 ( 240240 103600 ) ( 251440 * )
+ NEW Metal2 ( 251440 103600 ) ( * 111440 )
+ NEW Metal1 ( 238000 103600 ) Via1_VV
+ NEW Metal1 ( 240240 103600 ) Via1_HV
+ NEW Metal1 ( 251440 103600 ) Via1_HV
+ NEW Metal1 ( 251440 111440 ) Via1_VV ;
+ - _0440_ ( _1073_ A2 ) ( _1072_ A2 ) ( _1071_ A3 ) ( _1070_ ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 290640 95760 ) ( * 103600 )
+ NEW Metal3 ( 290640 95760 ) ( 299600 * )
+ NEW Metal2 ( 299600 128240 ) ( 301840 * )
+ NEW Metal2 ( 301840 95760 ) ( * 128240 )
+ NEW Metal2 ( 299600 95760 ) ( 301840 * )
+ NEW Metal2 ( 286160 133840 ) ( * 134960 )
+ NEW Metal3 ( 286160 133840 ) ( 299600 * )
+ NEW Metal2 ( 299600 128240 ) ( * 133840 )
+ NEW Metal1 ( 290640 103600 ) Via1_VV
+ NEW Metal2 ( 290640 95760 ) Via2_VH
+ NEW Metal1 ( 299600 95760 ) Via1_HV
+ NEW Metal2 ( 299600 95760 ) Via2_VH
+ NEW Metal1 ( 299600 128240 ) Via1_VV
+ NEW Metal1 ( 286160 134960 ) Via1_VV
+ NEW Metal2 ( 286160 133840 ) Via2_VH
+ NEW Metal2 ( 299600 133840 ) Via2_VH
+ NEW Metal2 ( 299600 95760 ) RECT ( -280 -660 280 0 ) ;
+ - _0441_ ( _1074_ A2 ) ( _1072_ ZN ) + USE SIGNAL
+ + ROUTED Metal3 ( 285040 121520 ) ( 298480 * )
+ NEW Metal2 ( 298480 121520 ) ( * 127120 )
+ NEW Metal1 ( 285040 121520 ) Via1_VV
+ NEW Metal2 ( 285040 121520 ) Via2_VH
+ NEW Metal2 ( 298480 121520 ) Via2_VH
+ NEW Metal1 ( 298480 127120 ) Via1_VV
+ NEW Metal2 ( 285040 121520 ) RECT ( -280 -660 280 0 ) ;
+ - _0442_ ( _1083_ A3 ) ( _1078_ A2 ) ( _1075_ A2 ) ( _1074_ A3 ) ( _1073_ Z ) + USE SIGNAL
+ + ROUTED Metal2 ( 245840 136080 ) ( * 137200 )
+ NEW Metal3 ( 231280 136080 ) ( 245840 * )
+ NEW Metal2 ( 231280 130480 ) ( * 136080 )
+ NEW Metal2 ( 258160 136080 ) ( * 137200 )
+ NEW Metal3 ( 245840 136080 ) ( 258160 * )
+ NEW Metal3 ( 258160 136080 ) ( 282800 * )
+ NEW Metal2 ( 282800 121520 ) ( * 136080 )
+ NEW Metal1 ( 245840 137200 ) Via1_VV
+ NEW Metal2 ( 245840 136080 ) Via2_VH
+ NEW Metal2 ( 231280 136080 ) Via2_VH
+ NEW Metal1 ( 231280 130480 ) Via1_HV
+ NEW Metal1 ( 258160 137200 ) Via1_VV
+ NEW Metal2 ( 258160 136080 ) Via2_VH
+ NEW Metal1 ( 282800 136080 ) Via1_HV
+ NEW Metal2 ( 282800 136080 ) Via2_VH
+ NEW Metal1 ( 282800 121520 ) Via1_VV
+ NEW Metal2 ( 282800 136080 ) RECT ( -280 -660 280 0 ) ;
+ - _0443_ ( _1076_ B2 ) ( _1075_ Z ) + USE SIGNAL
+ + ROUTED Metal2 ( 238000 121520 ) ( * 128240 )
+ NEW Metal2 ( 238000 128240 ) ( 239120 * )
+ NEW Metal1 ( 238000 121520 ) Via1_VV
+ NEW Metal1 ( 239120 128240 ) Via1_VV ;
+ - _0444_ ( _1077_ A2 ) ( _1076_ ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 224560 115920 ) ( * 120400 )
+ NEW Metal3 ( 224560 120400 ) ( 240240 * )
+ NEW Metal1 ( 224560 115920 ) Via1_VV
+ NEW Metal2 ( 224560 120400 ) Via2_VH
+ NEW Metal1 ( 240240 120400 ) Via1_VV
+ NEW Metal2 ( 240240 120400 ) Via2_VH
+ NEW Metal2 ( 240240 120400 ) RECT ( -280 -660 280 0 ) ;
+ - _0445_ ( _1079_ A2 ) ( _1078_ ZN ) + USE SIGNAL
+ + ROUTED Metal3 ( 235760 137200 ) ( 242480 * )
+ NEW Metal1 ( 242480 137200 ) Via1_VV
+ NEW Metal2 ( 242480 137200 ) Via2_VH
+ NEW Metal1 ( 235760 137200 ) Via1_VV
+ NEW Metal2 ( 235760 137200 ) Via2_VH
+ NEW Metal2 ( 242480 137200 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 235760 137200 ) RECT ( -280 -660 280 0 ) ;
+ - _0446_ ( _1080_ B2 ) ( _1079_ ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 234640 134960 ) ( * 143920 )
+ NEW Metal1 ( 234640 134960 ) Via1_HV
+ NEW Metal1 ( 234640 143920 ) Via1_VV ;
+ - _0447_ ( _1081_ A2 ) ( _1080_ ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 222320 146160 ) ( 229040 * )
+ NEW Metal1 ( 229040 146160 ) Via1_HV
+ NEW Metal1 ( 222320 146160 ) Via1_VV ;
+ - _0448_ ( _1087_ A1 ) ( _1084_ A1 ) ( _1082_ ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 263760 152880 ) ( * 158480 )
+ NEW Metal3 ( 263760 152880 ) ( 273840 * )
+ NEW Metal1 ( 273840 152880 ) Via1_VV
+ NEW Metal2 ( 273840 152880 ) Via2_VH
+ NEW Metal1 ( 263760 152880 ) Via1_HV
+ NEW Metal2 ( 263760 152880 ) Via2_VH
+ NEW Metal1 ( 263760 158480 ) Via1_VV
+ NEW Metal2 ( 273840 152880 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 263760 152880 ) RECT ( -280 -660 280 0 ) ;
+ - _0449_ ( _1087_ A2 ) ( _1084_ A2 ) ( _1083_ ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 260400 151760 ) ( * 159600 )
+ NEW Metal2 ( 260400 159600 ) ( 261520 * )
+ NEW Metal2 ( 260400 136080 ) ( * 151760 )
+ NEW Metal1 ( 260400 136080 ) Via1_VV
+ NEW Metal1 ( 260400 151760 ) Via1_HV
+ NEW Metal1 ( 261520 159600 ) Via1_VV ;
+ - _0450_ ( _1085_ B2 ) ( _1084_ Z ) + USE SIGNAL
+ + ROUTED Metal2 ( 267120 145040 ) ( 268240 * )
+ NEW Metal2 ( 268240 145040 ) ( * 151760 )
+ NEW Metal1 ( 267120 145040 ) Via1_HV
+ NEW Metal1 ( 268240 151760 ) Via1_VV ;
+ - _0451_ ( _1086_ A2 ) ( _1085_ ZN ) + USE SIGNAL
+ + ROUTED Metal3 ( 243600 146160 ) ( 261520 * )
+ NEW Metal1 ( 261520 146160 ) Via1_HV
+ NEW Metal2 ( 261520 146160 ) Via2_VH
+ NEW Metal1 ( 243600 146160 ) Via1_VV
+ NEW Metal2 ( 243600 146160 ) Via2_VH
+ NEW Metal2 ( 261520 146160 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 243600 146160 ) RECT ( -280 -660 280 0 ) ;
+ - _0452_ ( _1091_ A3 ) ( _1088_ A2 ) ( _1087_ ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 266000 171920 ) ( * 183120 )
+ NEW Metal2 ( 264880 171920 ) ( 266000 * )
+ NEW Metal2 ( 264880 162960 ) ( * 171920 )
+ NEW Metal2 ( 267120 183120 ) ( * 192080 )
+ NEW Metal2 ( 266000 183120 ) ( 267120 * )
+ NEW Metal1 ( 266000 183120 ) Via1_HV
+ NEW Metal1 ( 264880 162960 ) Via1_VV
+ NEW Metal1 ( 267120 192080 ) Via1_VV ;
+ - _0453_ ( _1089_ B2 ) ( _1088_ Z ) + USE SIGNAL
+ + ROUTED Metal2 ( 259280 176400 ) ( * 183120 )
+ NEW Metal2 ( 257040 183120 ) ( 259280 * )
+ NEW Metal1 ( 259280 176400 ) Via1_VV
+ NEW Metal1 ( 257040 183120 ) Via1_VV ;
+ - _0454_ ( _1090_ A2 ) ( _1089_ ZN ) + USE SIGNAL
+ + ROUTED Metal3 ( 243600 177520 ) ( 254800 * )
+ NEW Metal1 ( 254800 177520 ) Via1_HV
+ NEW Metal2 ( 254800 177520 ) Via2_VH
+ NEW Metal1 ( 243600 177520 ) Via1_VV
+ NEW Metal2 ( 243600 177520 ) Via2_VH
+ NEW Metal2 ( 254800 177520 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 243600 177520 ) RECT ( -280 -660 280 0 ) ;
+ - _0455_ ( _1093_ B1 ) ( _1091_ ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 273840 194320 ) ( * 199920 )
+ NEW Metal1 ( 273840 194320 ) Via1_VV
+ NEW Metal1 ( 273840 199920 ) Via1_HV ;
+ - _0456_ ( _1093_ B2 ) ( _1092_ ZN ) + USE SIGNAL
+ + ROUTED Metal3 ( 271600 194320 ) ( 296240 * )
+ NEW Metal2 ( 271600 194320 ) ( * 199920 )
+ NEW Metal1 ( 296240 194320 ) Via1_VV
+ NEW Metal2 ( 296240 194320 ) Via2_VH
+ NEW Metal2 ( 271600 194320 ) Via2_VH
+ NEW Metal1 ( 271600 199920 ) Via1_HV
+ NEW Metal2 ( 296240 194320 ) RECT ( -280 -660 280 0 ) ;
+ - _0457_ ( _1095_ A3 ) ( _1094_ ZN ) + USE SIGNAL
+ + ROUTED Metal3 ( 216720 301840 ) ( 222320 * )
+ NEW Metal2 ( 216720 301840 ) ( * 307440 )
+ NEW Metal1 ( 222320 301840 ) Via1_HV
+ NEW Metal2 ( 222320 301840 ) Via2_VH
+ NEW Metal2 ( 216720 301840 ) Via2_VH
+ NEW Metal1 ( 216720 307440 ) Via1_VV
+ NEW Metal2 ( 222320 301840 ) RECT ( -280 -660 280 0 ) ;
+ - _0458_ ( _1142_ A1 ) ( _1097_ A4 ) ( _1096_ Z ) + USE SIGNAL
+ + ROUTED Metal2 ( 402640 436800 ) ( * 451920 )
+ NEW Metal2 ( 403760 426160 ) ( * 432880 )
+ NEW Metal2 ( 403760 426160 ) ( 408240 * )
+ NEW Metal2 ( 402640 436800 ) ( 403760 * )
+ NEW Metal2 ( 403760 432880 ) ( * 436800 )
+ NEW Metal1 ( 402640 451920 ) Via1_VV
+ NEW Metal1 ( 403760 432880 ) Via1_VV
+ NEW Metal1 ( 408240 426160 ) Via1_VV ;
+ - _0459_ ( _1266_ A2 ) ( _1098_ B ) ( _1097_ ZN ) + USE SIGNAL
+ + ROUTED Metal3 ( 360080 453040 ) ( 371280 * )
+ NEW Metal2 ( 360080 453040 ) ( * 488880 )
+ NEW Metal2 ( 358960 488880 ) ( 360080 * )
+ NEW Metal2 ( 388080 442960 ) ( * 453040 )
+ NEW Metal3 ( 371280 453040 ) ( 388080 * )
+ NEW Metal1 ( 371280 453040 ) Via1_HV
+ NEW Metal2 ( 371280 453040 ) Via2_VH
+ NEW Metal2 ( 360080 453040 ) Via2_VH
+ NEW Metal1 ( 358960 488880 ) Via1_VV
+ NEW Metal1 ( 388080 442960 ) Via1_HV
+ NEW Metal2 ( 388080 453040 ) Via2_VH
+ NEW Metal2 ( 371280 453040 ) RECT ( -280 -660 280 0 ) ;
+ - _0460_ ( _1099_ A2 ) ( _1098_ ZN ) + USE SIGNAL
+ + ROUTED Metal3 ( 367920 488880 ) ( 375760 * )
+ NEW Metal2 ( 367920 487760 ) ( * 488880 )
+ NEW Metal1 ( 375760 488880 ) Via1_VV
+ NEW Metal2 ( 375760 488880 ) Via2_VH
+ NEW Metal2 ( 367920 488880 ) Via2_VH
+ NEW Metal1 ( 367920 487760 ) Via1_VV
+ NEW Metal2 ( 375760 488880 ) RECT ( -280 -660 280 0 ) ;
+ - _0461_ ( _1109_ A2 ) ( _1108_ A1 ) ( _1099_ ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 383600 488880 ) ( 384720 * )
+ NEW Metal2 ( 383600 488880 ) ( * 505680 )
+ NEW Metal3 ( 383600 505680 ) ( 406000 * )
+ NEW Metal2 ( 379120 490000 ) ( 383600 * )
+ NEW Metal1 ( 384720 488880 ) Via1_VV
+ NEW Metal2 ( 383600 505680 ) Via2_VH
+ NEW Metal1 ( 406000 505680 ) Via1_HV
+ NEW Metal2 ( 406000 505680 ) Via2_VH
+ NEW Metal1 ( 379120 490000 ) Via1_VV
+ NEW Metal2 ( 406000 505680 ) RECT ( -280 -660 280 0 ) ;
+ - _0462_ ( _1102_ A1 ) ( _1100_ ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 365680 238000 ) ( * 252560 )
+ NEW Metal2 ( 364560 252560 ) ( 365680 * )
+ NEW Metal2 ( 364560 252560 ) ( * 268240 )
+ NEW Metal2 ( 362320 268240 ) ( 364560 * )
+ NEW Metal1 ( 365680 238000 ) Via1_VV
+ NEW Metal1 ( 362320 268240 ) Via1_VV ;
+ - _0463_ ( _1102_ A2 ) ( _1101_ ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 364560 232400 ) ( * 238000 )
+ NEW Metal2 ( 363440 232400 ) ( 364560 * )
+ NEW Metal1 ( 364560 238000 ) Via1_VV
+ NEW Metal1 ( 363440 232400 ) Via1_VV ;
+ - _0464_ ( _1106_ A3 ) ( _1102_ ZN ) + USE SIGNAL
+ + ROUTED Metal3 ( 367920 239120 ) ( 375760 * )
+ NEW Metal1 ( 367920 239120 ) Via1_VV
+ NEW Metal2 ( 367920 239120 ) Via2_VH
+ NEW Metal1 ( 375760 239120 ) Via1_HV
+ NEW Metal2 ( 375760 239120 ) Via2_VH
+ NEW Metal2 ( 367920 239120 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 375760 239120 ) RECT ( -280 -660 280 0 ) ;
+ - _0465_ ( _1105_ A1 ) ( _1103_ ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 374640 87920 ) ( 376880 * )
+ NEW Metal2 ( 376880 87920 ) ( * 158480 )
+ NEW Metal1 ( 374640 87920 ) Via1_VV
+ NEW Metal1 ( 376880 158480 ) Via1_VV ;
+ - _0466_ ( _1105_ A2 ) ( _1104_ ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 376880 160720 ) ( 378000 * )
+ NEW Metal2 ( 376880 160720 ) ( * 170800 )
+ NEW Metal1 ( 378000 160720 ) Via1_VV
+ NEW Metal1 ( 376880 170800 ) Via1_VV ;
+ - _0467_ ( _1106_ A4 ) ( _1105_ ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 371280 223440 ) ( 376880 * )
+ NEW Metal2 ( 376880 223440 ) ( * 238000 )
+ NEW Metal2 ( 371280 160720 ) ( 374640 * )
+ NEW Metal2 ( 371280 160720 ) ( * 223440 )
+ NEW Metal1 ( 376880 238000 ) Via1_HV
+ NEW Metal1 ( 374640 160720 ) Via1_VV ;
+ - _0468_ ( ANTENNA__1107__I I ) ( ANTENNA__1135__A2 I ) ( ANTENNA__1188__A2 I ) ( ANTENNA__1211__A1 I ) ( ANTENNA__1266__A3 I ) ( ANTENNA__1295__A2 I ) ( ANTENNA__1323__A2 I )
+ ( _1323_ A2 ) ( _1295_ A2 ) ( _1266_ A3 ) ( _1211_ A1 ) ( _1188_ A2 ) ( _1135_ A2 ) ( _1107_ I ) ( _1106_ ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 457520 464240 ) ( * 466480 )
+ NEW Metal2 ( 455280 466480 ) ( * 472080 )
+ NEW Metal2 ( 455280 466480 ) ( 457520 * )
+ NEW Metal3 ( 444080 350000 ) ( 447440 * )
+ NEW Metal2 ( 444080 350000 ) ( * 386960 )
+ NEW Metal2 ( 457520 348880 ) ( * 350000 )
+ NEW Metal3 ( 447440 350000 ) ( 457520 * )
+ NEW Metal2 ( 447440 350000 ) ( 448560 * )
+ NEW Metal2 ( 476560 334320 ) ( * 350000 )
+ NEW Metal3 ( 457520 350000 ) ( 476560 * )
+ NEW Metal2 ( 477680 327600 ) ( * 334320 )
+ NEW Metal2 ( 476560 334320 ) ( 477680 * )
+ NEW Metal2 ( 385840 454160 ) ( * 466480 )
+ NEW Metal2 ( 385840 454160 ) ( 386960 * )
+ NEW Metal2 ( 386960 441840 ) ( * 454160 )
+ NEW Metal3 ( 385840 467600 ) ( 414960 * )
+ NEW Metal2 ( 385840 466480 ) ( * 467600 )
+ NEW Metal2 ( 418320 459760 ) ( * 467600 )
+ NEW Metal3 ( 414960 467600 ) ( 418320 * )
+ NEW Metal2 ( 427280 459760 ) ( * 460880 )
+ NEW Metal1 ( 418320 460880 ) ( 427280 * )
+ NEW Metal2 ( 429520 460880 ) ( * 467600 )
+ NEW Metal2 ( 427280 460880 ) ( 429520 * )
+ NEW Metal3 ( 429520 464240 ) ( 457520 * )
+ NEW Metal2 ( 432880 395920 ) ( 434000 * )
+ NEW Metal2 ( 431760 390320 ) ( 432880 * )
+ NEW Metal2 ( 432880 390320 ) ( * 395920 )
+ NEW Metal2 ( 432880 386960 ) ( * 390320 )
+ NEW Metal2 ( 432880 395920 ) ( * 464240 )
+ NEW Metal3 ( 432880 386960 ) ( 444080 * )
+ NEW Metal3 ( 409360 240240 ) ( 448560 * )
+ NEW Metal2 ( 448560 240240 ) ( * 350000 )
+ NEW Metal1 ( 457520 466480 ) Via1_VV
+ NEW Metal2 ( 457520 464240 ) Via2_VH
+ NEW Metal1 ( 455280 472080 ) Via1_VV
+ NEW Metal1 ( 447440 350000 ) Via1_VV
+ NEW Metal2 ( 447440 350000 ) Via2_VH
+ NEW Metal2 ( 444080 350000 ) Via2_VH
+ NEW Metal2 ( 444080 386960 ) Via2_VH
+ NEW Metal1 ( 457520 348880 ) Via1_HV
+ NEW Metal2 ( 457520 350000 ) Via2_VH
+ NEW Metal1 ( 476560 334320 ) Via1_VV
+ NEW Metal2 ( 476560 350000 ) Via2_VH
+ NEW Metal1 ( 477680 327600 ) Via1_VV
+ NEW Metal1 ( 385840 466480 ) Via1_VV
+ NEW Metal1 ( 386960 441840 ) Via1_HV
+ NEW Metal1 ( 414960 467600 ) Via1_VV
+ NEW Metal2 ( 414960 467600 ) Via2_VH
+ NEW Metal2 ( 385840 467600 ) Via2_VH
+ NEW Metal1 ( 418320 459760 ) Via1_VV
+ NEW Metal2 ( 418320 467600 ) Via2_VH
+ NEW Metal1 ( 427280 459760 ) Via1_VV
+ NEW Metal1 ( 427280 460880 ) Via1_HV
+ NEW Metal1 ( 418320 460880 ) Via1_HV
+ NEW Metal1 ( 429520 467600 ) Via1_HV
+ NEW Metal2 ( 429520 464240 ) Via2_VH
+ NEW Metal2 ( 432880 464240 ) Via2_VH
+ NEW Metal1 ( 434000 395920 ) Via1_VV
+ NEW Metal1 ( 431760 390320 ) Via1_VV
+ NEW Metal2 ( 432880 386960 ) Via2_VH
+ NEW Metal2 ( 448560 240240 ) Via2_VH
+ NEW Metal1 ( 409360 240240 ) Via1_HV
+ NEW Metal2 ( 409360 240240 ) Via2_VH
+ NEW Metal2 ( 447440 350000 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 414960 467600 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 418320 460880 ) RECT ( -280 -1040 280 0 )
+ NEW Metal2 ( 429520 464240 ) RECT ( -280 -1040 280 0 )
+ NEW Metal3 ( 432880 464240 ) RECT ( -1040 -280 0 280 )
+ NEW Metal2 ( 409360 240240 ) RECT ( -280 -660 280 0 ) ;
+ - _0469_ ( ANTENNA__1108__A2 I ) ( ANTENNA__1109__A3 I ) ( ANTENNA__1138__A2 I ) ( ANTENNA__1139__I I ) ( ANTENNA__1160__A1 I ) ( ANTENNA__1161__A2 I ) ( ANTENNA__1191__A2 I )
+ ( ANTENNA__1212__A2 I ) ( ANTENNA__1241__A2 I ) ( ANTENNA__1243__A2 I ) ( _1243_ A2 ) ( _1241_ A2 ) ( _1212_ A2 ) ( _1191_ A2 ) ( _1161_ A2 )
+ ( _1160_ A1 ) ( _1139_ I ) ( _1138_ A2 ) ( _1109_ A3 ) ( _1108_ A2 ) ( _1107_ Z ) + USE SIGNAL
+ + ROUTED Metal2 ( 465360 315280 ) ( 466480 * )
+ NEW Metal2 ( 466480 307440 ) ( * 315280 )
+ NEW Metal1 ( 466480 307440 ) ( 469840 * )
+ NEW Metal2 ( 469840 307440 ) ( * 308560 )
+ NEW Metal2 ( 468720 497840 ) ( 469840 * )
+ NEW Metal2 ( 468720 497840 ) ( * 505680 )
+ NEW Metal2 ( 467600 514640 ) ( 468720 * )
+ NEW Metal2 ( 467600 505680 ) ( * 514640 )
+ NEW Metal2 ( 467600 505680 ) ( 468720 * )
+ NEW Metal2 ( 468720 514640 ) ( * 519120 )
+ NEW Metal3 ( 469840 497840 ) ( 486640 * )
+ NEW Metal2 ( 437360 449680 ) ( 438480 * )
+ NEW Metal3 ( 438480 450800 ) ( 447440 * )
+ NEW Metal2 ( 438480 449680 ) ( * 450800 )
+ NEW Metal2 ( 467600 356720 ) ( 468720 * )
+ NEW Metal2 ( 468720 320880 ) ( * 356720 )
+ NEW Metal2 ( 465360 320880 ) ( 468720 * )
+ NEW Metal2 ( 465360 361200 ) ( * 362320 )
+ NEW Metal2 ( 465360 361200 ) ( 467600 * )
+ NEW Metal2 ( 467600 356720 ) ( * 361200 )
+ NEW Metal2 ( 446320 370160 ) ( * 372400 )
+ NEW Metal3 ( 446320 370160 ) ( 465360 * )
+ NEW Metal2 ( 465360 362320 ) ( * 370160 )
+ NEW Metal2 ( 440720 370160 ) ( * 371280 )
+ NEW Metal3 ( 440720 370160 ) ( 446320 * )
+ NEW Metal2 ( 439600 394800 ) ( 440720 * )
+ NEW Metal2 ( 440720 371280 ) ( * 394800 )
+ NEW Metal2 ( 439600 394800 ) ( * 406000 )
+ NEW Metal2 ( 437360 427280 ) ( * 449680 )
+ NEW Metal2 ( 465360 315280 ) ( * 320880 )
+ NEW Metal2 ( 385840 486640 ) ( * 488880 )
+ NEW Metal2 ( 383600 486640 ) ( 385840 * )
+ NEW Metal3 ( 385840 487760 ) ( 390320 * )
+ NEW Metal2 ( 408240 503440 ) ( * 504560 )
+ NEW Metal3 ( 402640 503440 ) ( 408240 * )
+ NEW Metal3 ( 402640 502320 ) ( * 503440 )
+ NEW Metal3 ( 391440 502320 ) ( 402640 * )
+ NEW Metal2 ( 391440 487760 ) ( * 502320 )
+ NEW Metal2 ( 390320 487760 ) ( 391440 * )
+ NEW Metal3 ( 408240 505680 ) ( 425040 * )
+ NEW Metal2 ( 408240 504560 ) ( * 505680 )
+ NEW Metal3 ( 425040 505680 ) ( 468720 * )
+ NEW Metal2 ( 383600 427280 ) ( 384720 * )
+ NEW Metal3 ( 384720 427280 ) ( 425040 * )
+ NEW Metal2 ( 425040 406000 ) ( * 427280 )
+ NEW Metal2 ( 430640 403760 ) ( * 406000 )
+ NEW Metal2 ( 383600 427280 ) ( * 486640 )
+ NEW Metal3 ( 425040 406000 ) ( 439600 * )
+ NEW Metal3 ( 425040 427280 ) ( 437360 * )
+ NEW Metal1 ( 465360 315280 ) Via1_VV
+ NEW Metal1 ( 466480 307440 ) Via1_HV
+ NEW Metal1 ( 469840 307440 ) Via1_HV
+ NEW Metal1 ( 469840 308560 ) Via1_VV
+ NEW Metal1 ( 469840 497840 ) Via1_HV
+ NEW Metal2 ( 468720 505680 ) Via2_VH
+ NEW Metal1 ( 468720 514640 ) Via1_VV
+ NEW Metal1 ( 468720 519120 ) Via1_VV
+ NEW Metal1 ( 486640 497840 ) Via1_VV
+ NEW Metal2 ( 486640 497840 ) Via2_VH
+ NEW Metal2 ( 469840 497840 ) Via2_VH
+ NEW Metal1 ( 438480 449680 ) Via1_VV
+ NEW Metal1 ( 447440 450800 ) Via1_VV
+ NEW Metal2 ( 447440 450800 ) Via2_VH
+ NEW Metal2 ( 438480 450800 ) Via2_VH
+ NEW Metal1 ( 467600 356720 ) Via1_VV
+ NEW Metal1 ( 465360 362320 ) Via1_VV
+ NEW Metal1 ( 446320 372400 ) Via1_VV
+ NEW Metal2 ( 446320 370160 ) Via2_VH
+ NEW Metal2 ( 465360 370160 ) Via2_VH
+ NEW Metal1 ( 440720 371280 ) Via1_VV
+ NEW Metal2 ( 440720 370160 ) Via2_VH
+ NEW Metal1 ( 439600 394800 ) Via1_VV
+ NEW Metal2 ( 439600 406000 ) Via2_VH
+ NEW Metal2 ( 437360 427280 ) Via2_VH
+ NEW Metal1 ( 385840 488880 ) Via1_VV
+ NEW Metal1 ( 390320 487760 ) Via1_VV
+ NEW Metal2 ( 390320 487760 ) Via2_VH
+ NEW Metal2 ( 385840 487760 ) Via2_VH
+ NEW Metal1 ( 408240 504560 ) Via1_VV
+ NEW Metal2 ( 408240 503440 ) Via2_VH
+ NEW Metal2 ( 391440 502320 ) Via2_VH
+ NEW Metal1 ( 425040 505680 ) Via1_VV
+ NEW Metal2 ( 425040 505680 ) Via2_VH
+ NEW Metal2 ( 408240 505680 ) Via2_VH
+ NEW Metal1 ( 384720 427280 ) Via1_VV
+ NEW Metal1 ( 425040 427280 ) Via1_VV
+ NEW Metal2 ( 425040 427280 ) Via2_VH
+ NEW Metal2 ( 384720 427280 ) Via2_VH
+ NEW Metal1 ( 425040 406000 ) Via1_VV
+ NEW Metal2 ( 425040 406000 ) Via2_VH
+ NEW Metal1 ( 430640 403760 ) Via1_HV
+ NEW Metal2 ( 430640 406000 ) Via2_VH
+ NEW Metal2 ( 486640 497840 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 469840 497840 ) RECT ( -280 -1040 280 0 )
+ NEW Metal2 ( 447440 450800 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 390320 487760 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 385840 487760 ) RECT ( -280 -1040 280 0 )
+ NEW Metal2 ( 425040 505680 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 425040 427280 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 384720 427280 ) RECT ( -280 -1040 280 0 )
+ NEW Metal2 ( 425040 406000 ) RECT ( -280 -1040 280 0 )
+ NEW Metal3 ( 430640 406000 ) RECT ( -1040 -280 0 280 ) ;
+ - _0470_ ( _1122_ A2 ) ( _1114_ B ) ( _1112_ A2 ) ( _1111_ A2 ) ( _1108_ ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 384720 505680 ) ( 385840 * )
+ NEW Metal2 ( 385840 492240 ) ( * 505680 )
+ NEW Metal2 ( 384720 492240 ) ( 385840 * )
+ NEW Metal2 ( 398160 501200 ) ( * 504560 )
+ NEW Metal3 ( 385840 501200 ) ( 398160 * )
+ NEW Metal2 ( 402640 500080 ) ( * 501200 )
+ NEW Metal3 ( 398160 501200 ) ( 402640 * )
+ NEW Metal2 ( 399280 504560 ) ( * 513520 )
+ NEW Metal2 ( 398160 504560 ) ( 399280 * )
+ NEW Metal1 ( 384720 505680 ) Via1_VV
+ NEW Metal1 ( 384720 492240 ) Via1_VV
+ NEW Metal1 ( 398160 504560 ) Via1_VV
+ NEW Metal2 ( 398160 501200 ) Via2_VH
+ NEW Metal2 ( 385840 501200 ) Via2_VH
+ NEW Metal1 ( 402640 500080 ) Via1_VV
+ NEW Metal2 ( 402640 501200 ) Via2_VH
+ NEW Metal1 ( 399280 513520 ) Via1_VV
+ NEW Metal2 ( 385840 501200 ) RECT ( -280 -1040 280 0 ) ;
+ - _0471_ ( _1119_ B2 ) ( _1110_ A2 ) ( _1109_ ZN ) + USE SIGNAL
+ + ROUTED Metal3 ( 390320 511280 ) ( 402640 * )
+ NEW Metal2 ( 402640 507920 ) ( * 511280 )
+ NEW Metal2 ( 390320 511280 ) ( * 520240 )
+ NEW Metal1 ( 390320 511280 ) Via1_VV
+ NEW Metal2 ( 390320 511280 ) Via2_VH
+ NEW Metal2 ( 402640 511280 ) Via2_VH
+ NEW Metal1 ( 402640 507920 ) Via1_VV
+ NEW Metal1 ( 390320 520240 ) Via1_VV
+ NEW Metal2 ( 390320 511280 ) RECT ( -280 -660 280 0 ) ;
+ - _0472_ ( _1111_ B ) ( _1110_ ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 402640 514640 ) ( * 519120 )
+ NEW Metal2 ( 393680 519120 ) ( 402640 * )
+ NEW Metal1 ( 402640 514640 ) Via1_VV
+ NEW Metal1 ( 393680 519120 ) Via1_VV ;
+ - _0473_ ( _1116_ A1 ) ( _1112_ ZN ) + USE SIGNAL
+ + ROUTED Metal3 ( 403760 500080 ) ( 414960 * )
+ NEW Metal2 ( 414960 500080 ) ( * 503440 )
+ NEW Metal1 ( 403760 500080 ) Via1_VV
+ NEW Metal2 ( 403760 500080 ) Via2_VH
+ NEW Metal2 ( 414960 500080 ) Via2_VH
+ NEW Metal1 ( 414960 503440 ) Via1_VV
+ NEW Metal2 ( 403760 500080 ) RECT ( -280 -660 280 0 ) ;
+ - _0474_ ( _1122_ A3 ) ( _1118_ A2 ) ( _1114_ A2 ) ( _1113_ Z ) + USE SIGNAL
+ + ROUTED Metal2 ( 388080 492240 ) ( * 495600 )
+ NEW Metal3 ( 388080 492240 ) ( 413840 * )
+ NEW Metal2 ( 392560 492240 ) ( * 504560 )
+ NEW Metal2 ( 386960 495600 ) ( * 505680 )
+ NEW Metal2 ( 386960 495600 ) ( 388080 * )
+ NEW Metal1 ( 388080 495600 ) Via1_VV
+ NEW Metal2 ( 388080 492240 ) Via2_VH
+ NEW Metal1 ( 413840 492240 ) Via1_VV
+ NEW Metal2 ( 413840 492240 ) Via2_VH
+ NEW Metal1 ( 392560 504560 ) Via1_VV
+ NEW Metal2 ( 392560 492240 ) Via2_VH
+ NEW Metal1 ( 386960 505680 ) Via1_HV
+ NEW Metal2 ( 413840 492240 ) RECT ( -280 -660 280 0 )
+ NEW Metal3 ( 392560 492240 ) RECT ( -1040 -280 0 280 ) ;
+ - _0475_ ( _1124_ A1 ) ( _1119_ A2 ) ( _1115_ A2 ) ( _1114_ ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 383600 509040 ) ( * 513520 )
+ NEW Metal2 ( 380240 509040 ) ( 383600 * )
+ NEW Metal2 ( 380240 498960 ) ( * 509040 )
+ NEW Metal3 ( 357840 498960 ) ( 380240 * )
+ NEW Metal3 ( 380240 503440 ) ( 393680 * )
+ NEW Metal2 ( 400400 492240 ) ( * 503440 )
+ NEW Metal3 ( 393680 503440 ) ( 400400 * )
+ NEW Metal1 ( 383600 513520 ) Via1_VV
+ NEW Metal2 ( 380240 498960 ) Via2_VH
+ NEW Metal1 ( 357840 498960 ) Via1_VV
+ NEW Metal2 ( 357840 498960 ) Via2_VH
+ NEW Metal1 ( 393680 503440 ) Via1_VV
+ NEW Metal2 ( 393680 503440 ) Via2_VH
+ NEW Metal2 ( 380240 503440 ) Via2_VH
+ NEW Metal1 ( 400400 492240 ) Via1_VV
+ NEW Metal2 ( 400400 503440 ) Via2_VH
+ NEW Metal2 ( 357840 498960 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 393680 503440 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 380240 503440 ) RECT ( -280 -1040 280 0 ) ;
+ - _0476_ ( _1116_ A2 ) ( _1115_ ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 401520 491120 ) ( * 498960 )
+ NEW Metal3 ( 401520 498960 ) ( 413840 * )
+ NEW Metal2 ( 413840 498960 ) ( * 504560 )
+ NEW Metal1 ( 401520 491120 ) Via1_VV
+ NEW Metal2 ( 401520 498960 ) Via2_VH
+ NEW Metal2 ( 413840 498960 ) Via2_VH
+ NEW Metal1 ( 413840 504560 ) Via1_VV ;
+ - _0477_ ( _1132_ A2 ) ( _1130_ A2 ) ( _1118_ A1 ) ( _1117_ ZN ) + USE SIGNAL
+ + ROUTED Metal3 ( 389200 482160 ) ( 404880 * )
+ NEW Metal2 ( 404880 473200 ) ( * 482160 )
+ NEW Metal2 ( 397040 482160 ) ( * 495600 )
+ NEW Metal2 ( 389200 496720 ) ( 390320 * )
+ NEW Metal2 ( 389200 482160 ) ( * 496720 )
+ NEW Metal1 ( 389200 482160 ) Via1_VV
+ NEW Metal2 ( 389200 482160 ) Via2_VH
+ NEW Metal2 ( 404880 482160 ) Via2_VH
+ NEW Metal1 ( 404880 473200 ) Via1_HV
+ NEW Metal1 ( 397040 495600 ) Via1_VV
+ NEW Metal2 ( 397040 482160 ) Via2_VH
+ NEW Metal1 ( 390320 496720 ) Via1_VV
+ NEW Metal2 ( 389200 482160 ) RECT ( -280 -660 280 0 )
+ NEW Metal3 ( 397040 482160 ) RECT ( -1040 -280 0 280 ) ;
+ - _0478_ ( _1119_ B1 ) ( _1118_ Z ) + USE SIGNAL
+ + ROUTED Metal2 ( 384720 500080 ) ( * 502320 )
+ NEW Metal3 ( 384720 502320 ) ( 389200 * )
+ NEW Metal2 ( 389200 502320 ) ( * 512400 )
+ NEW Metal2 ( 388080 512400 ) ( 389200 * )
+ NEW Metal1 ( 384720 500080 ) Via1_HV
+ NEW Metal2 ( 384720 502320 ) Via2_VH
+ NEW Metal2 ( 389200 502320 ) Via2_VH
+ NEW Metal1 ( 388080 512400 ) Via1_VV ;
+ - _0479_ ( _1120_ A2 ) ( _1119_ ZN ) + USE SIGNAL
+ + ROUTED Metal3 ( 364560 515760 ) ( 384720 * )
+ NEW Metal2 ( 364560 515760 ) ( * 520240 )
+ NEW Metal1 ( 384720 515760 ) Via1_VV
+ NEW Metal2 ( 384720 515760 ) Via2_VH
+ NEW Metal2 ( 364560 515760 ) Via2_VH
+ NEW Metal1 ( 364560 520240 ) Via1_VV
+ NEW Metal2 ( 384720 515760 ) RECT ( -280 -660 280 0 ) ;
+ - _0480_ ( _1125_ A1 ) ( _1121_ ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 345520 500080 ) ( * 504560 )
+ NEW Metal3 ( 345520 504560 ) ( 358960 * )
+ NEW Metal1 ( 345520 500080 ) Via1_VV
+ NEW Metal2 ( 345520 504560 ) Via2_VH
+ NEW Metal1 ( 358960 504560 ) Via1_VV
+ NEW Metal2 ( 358960 504560 ) Via2_VH
+ NEW Metal2 ( 358960 504560 ) RECT ( -280 -660 280 0 ) ;
+ - _0481_ ( _1125_ A2 ) ( _1122_ ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 343280 500080 ) ( * 502320 )
+ NEW Metal3 ( 343280 502320 ) ( 381360 * )
+ NEW Metal2 ( 381360 502320 ) ( * 504560 )
+ NEW Metal1 ( 343280 500080 ) Via1_VV
+ NEW Metal2 ( 343280 502320 ) Via2_VH
+ NEW Metal2 ( 381360 502320 ) Via2_VH
+ NEW Metal1 ( 381360 504560 ) Via1_VV ;
+ - _0482_ ( _1124_ A2 ) ( _1123_ ZN ) + USE SIGNAL
+ + ROUTED Metal3 ( 362320 497840 ) ( 367920 * )
+ NEW Metal1 ( 362320 497840 ) Via1_VV
+ NEW Metal2 ( 362320 497840 ) Via2_VH
+ NEW Metal1 ( 367920 497840 ) Via1_VV
+ NEW Metal2 ( 367920 497840 ) Via2_VH
+ NEW Metal2 ( 362320 497840 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 367920 497840 ) RECT ( -280 -660 280 0 ) ;
+ - _0483_ ( _1126_ A2 ) ( _1125_ B ) ( _1124_ ZN ) + USE SIGNAL
+ + ROUTED Metal3 ( 350000 497840 ) ( 360080 * )
+ NEW Metal2 ( 348880 492240 ) ( 350000 * )
+ NEW Metal2 ( 350000 492240 ) ( * 497840 )
+ NEW Metal1 ( 350000 497840 ) Via1_VV
+ NEW Metal2 ( 350000 497840 ) Via2_VH
+ NEW Metal1 ( 360080 497840 ) Via1_VV
+ NEW Metal2 ( 360080 497840 ) Via2_VH
+ NEW Metal1 ( 348880 492240 ) Via1_VV
+ NEW Metal2 ( 350000 497840 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 360080 497840 ) RECT ( -280 -660 280 0 ) ;
+ - _0484_ ( _1127_ I ) ( _1126_ Z ) + USE SIGNAL
+ + ROUTED Metal2 ( 325360 483280 ) ( * 487760 )
+ NEW Metal3 ( 325360 487760 ) ( 345520 * )
+ NEW Metal1 ( 325360 483280 ) Via1_VV
+ NEW Metal2 ( 325360 487760 ) Via2_VH
+ NEW Metal1 ( 345520 487760 ) Via1_HV
+ NEW Metal2 ( 345520 487760 ) Via2_VH
+ NEW Metal2 ( 345520 487760 ) RECT ( -280 -660 280 0 ) ;
+ - _0485_ ( _1132_ B2 ) ( _1130_ B2 ) ( _1128_ ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 389200 460880 ) ( * 474320 )
+ NEW Metal2 ( 395920 474320 ) ( * 479920 )
+ NEW Metal2 ( 389200 474320 ) ( 395920 * )
+ NEW Metal1 ( 389200 474320 ) Via1_HV
+ NEW Metal1 ( 389200 460880 ) Via1_VV
+ NEW Metal1 ( 395920 479920 ) Via1_VV ;
+ - _0486_ ( _1130_ C ) ( _1129_ Z ) + USE SIGNAL
+ + ROUTED Metal2 ( 371280 467600 ) ( * 470960 )
+ NEW Metal3 ( 371280 470960 ) ( 399280 * )
+ NEW Metal2 ( 399280 470960 ) ( * 473200 )
+ NEW Metal1 ( 371280 467600 ) Via1_VV
+ NEW Metal2 ( 371280 470960 ) Via2_VH
+ NEW Metal2 ( 399280 470960 ) Via2_VH
+ NEW Metal1 ( 399280 473200 ) Via1_HV ;
+ - _0487_ ( _1136_ A1 ) ( _1130_ ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 398160 467600 ) ( * 472080 )
+ NEW Metal1 ( 398160 467600 ) Via1_HV
+ NEW Metal1 ( 398160 472080 ) Via1_HV ;
+ - _0488_ ( _1134_ A1 ) ( _1131_ Z ) + USE SIGNAL
+ + ROUTED Metal3 ( 380240 474320 ) ( 417200 * )
+ NEW Metal1 ( 417200 474320 ) Via1_VV
+ NEW Metal2 ( 417200 474320 ) Via2_VH
+ NEW Metal1 ( 380240 474320 ) Via1_VV
+ NEW Metal2 ( 380240 474320 ) Via2_VH
+ NEW Metal2 ( 417200 474320 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 380240 474320 ) RECT ( -280 -660 280 0 ) ;
+ - _0489_ ( _1134_ A2 ) ( _1132_ ZN ) + USE SIGNAL
+ + ROUTED Metal3 ( 378000 476560 ) ( 390320 * )
+ NEW Metal2 ( 390320 476560 ) ( * 481040 )
+ NEW Metal1 ( 378000 476560 ) Via1_VV
+ NEW Metal2 ( 378000 476560 ) Via2_VH
+ NEW Metal2 ( 390320 476560 ) Via2_VH
+ NEW Metal1 ( 390320 481040 ) Via1_VV
+ NEW Metal2 ( 378000 476560 ) RECT ( -280 -660 280 0 ) ;
+ - _0490_ ( _1134_ A3 ) ( _1133_ Z ) + USE SIGNAL
+ + ROUTED Metal3 ( 364560 474320 ) ( 375760 * )
+ NEW Metal1 ( 364560 474320 ) Via1_VV
+ NEW Metal2 ( 364560 474320 ) Via2_VH
+ NEW Metal1 ( 375760 474320 ) Via1_HV
+ NEW Metal2 ( 375760 474320 ) Via2_VH
+ NEW Metal2 ( 364560 474320 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 375760 474320 ) RECT ( -280 -660 280 0 ) ;
+ - _0491_ ( _1136_ A2 ) ( _1134_ ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 381360 469840 ) ( * 473200 )
+ NEW Metal3 ( 381360 469840 ) ( 397040 * )
+ NEW Metal2 ( 397040 466480 ) ( * 469840 )
+ NEW Metal1 ( 381360 473200 ) Via1_VV
+ NEW Metal2 ( 381360 469840 ) Via2_VH
+ NEW Metal2 ( 397040 469840 ) Via2_VH
+ NEW Metal1 ( 397040 466480 ) Via1_HV ;
+ - _0492_ ( _1136_ B ) ( _1135_ ZN ) + USE SIGNAL
+ + ROUTED Metal3 ( 382480 466480 ) ( 391440 * )
+ NEW Metal1 ( 391440 466480 ) Via1_HV
+ NEW Metal2 ( 391440 466480 ) Via2_VH
+ NEW Metal1 ( 382480 466480 ) Via1_VV
+ NEW Metal2 ( 382480 466480 ) Via2_VH
+ NEW Metal2 ( 391440 466480 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 382480 466480 ) RECT ( -280 -660 280 0 ) ;
+ - _0493_ ( ANTENNA__1137__A2 I ) ( ANTENNA__1142__A2 I ) ( ANTENNA__1146__B1 I ) ( ANTENNA__1149__A1 I ) ( ANTENNA__1151__A1 I ) ( ANTENNA__1154__A1 I ) ( _1154_ A1 )
+ ( _1151_ A1 ) ( _1149_ A1 ) ( _1146_ B1 ) ( _1142_ A2 ) ( _1137_ A2 ) ( _1136_ ZN ) + USE SIGNAL
+ + ROUTED Metal3 ( 401520 465360 ) ( 407120 * )
+ NEW Metal2 ( 379120 458640 ) ( * 465360 )
+ NEW Metal3 ( 379120 465360 ) ( 401520 * )
+ NEW Metal3 ( 366800 459760 ) ( 379120 * )
+ NEW Metal2 ( 361200 442960 ) ( * 459760 )
+ NEW Metal3 ( 361200 459760 ) ( 366800 * )
+ NEW Metal2 ( 418320 449680 ) ( * 450800 )
+ NEW Metal3 ( 418320 449680 ) ( 427280 * )
+ NEW Metal2 ( 379120 436800 ) ( * 458640 )
+ NEW Metal2 ( 374640 436800 ) ( 379120 * )
+ NEW Metal2 ( 374640 436240 ) ( * 436800 )
+ NEW Metal2 ( 379120 428400 ) ( * 436800 )
+ NEW Metal3 ( 379120 425040 ) ( 397040 * )
+ NEW Metal2 ( 379120 425040 ) ( * 428400 )
+ NEW Metal3 ( 397040 425040 ) ( 410480 * )
+ NEW Metal3 ( 410480 425040 ) ( 427280 * )
+ NEW Metal2 ( 427280 428400 ) ( 429520 * )
+ NEW Metal2 ( 427280 421680 ) ( * 425040 )
+ NEW Metal2 ( 427280 425040 ) ( * 449680 )
+ NEW Metal1 ( 401520 465360 ) Via1_HV
+ NEW Metal2 ( 401520 465360 ) Via2_VH
+ NEW Metal1 ( 407120 465360 ) Via1_VV
+ NEW Metal2 ( 407120 465360 ) Via2_VH
+ NEW Metal1 ( 379120 458640 ) Via1_VV
+ NEW Metal2 ( 379120 465360 ) Via2_VH
+ NEW Metal1 ( 366800 459760 ) Via1_VV
+ NEW Metal2 ( 366800 459760 ) Via2_VH
+ NEW Metal2 ( 379120 459760 ) Via2_VH
+ NEW Metal1 ( 361200 442960 ) Via1_VV
+ NEW Metal2 ( 361200 459760 ) Via2_VH
+ NEW Metal1 ( 427280 449680 ) Via1_VV
+ NEW Metal1 ( 418320 450800 ) Via1_VV
+ NEW Metal2 ( 418320 449680 ) Via2_VH
+ NEW Metal2 ( 427280 449680 ) Via2_VH
+ NEW Metal1 ( 374640 436240 ) Via1_VV
+ NEW Metal1 ( 379120 428400 ) Via1_VV
+ NEW Metal1 ( 397040 425040 ) Via1_VV
+ NEW Metal2 ( 397040 425040 ) Via2_VH
+ NEW Metal2 ( 379120 425040 ) Via2_VH
+ NEW Metal1 ( 410480 425040 ) Via1_VV
+ NEW Metal2 ( 410480 425040 ) Via2_VH
+ NEW Metal2 ( 427280 425040 ) Via2_VH
+ NEW Metal1 ( 429520 428400 ) Via1_VV
+ NEW Metal1 ( 427280 421680 ) Via1_VV
+ NEW Metal2 ( 401520 465360 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 407120 465360 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 366800 459760 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 379120 459760 ) RECT ( -280 -1040 280 0 )
+ NEW Metal2 ( 427280 449680 ) RECT ( -280 -1040 280 0 )
+ NEW Metal2 ( 397040 425040 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 410480 425040 ) RECT ( -280 -660 280 0 ) ;
+ - _0494_ ( _1138_ B ) ( _1137_ ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 391440 427280 ) ( 398160 * )
+ NEW Metal1 ( 398160 427280 ) Via1_VV
+ NEW Metal1 ( 391440 427280 ) Via1_VV ;
+ - _0495_ ( ANTENNA__1140__A2 I ) ( ANTENNA__1146__A2 I ) ( ANTENNA__1151__B I ) ( ANTENNA__1193__A2 I ) ( ANTENNA__1198__A2 I ) ( ANTENNA__1202__B I ) ( ANTENNA__1244__A2 I )
+ ( ANTENNA__1249__A2 I ) ( ANTENNA__1254__B I ) ( _1254_ B ) ( _1249_ A2 ) ( _1244_ A2 ) ( _1202_ B ) ( _1198_ A2 ) ( _1193_ A2 )
+ ( _1151_ B ) ( _1146_ A2 ) ( _1140_ A2 ) ( _1139_ ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 525840 442960 ) ( * 456400 )
+ NEW Metal2 ( 525840 442960 ) ( 526960 * )
+ NEW Metal2 ( 509040 437360 ) ( * 440720 )
+ NEW Metal2 ( 506800 440720 ) ( 509040 * )
+ NEW Metal3 ( 509040 435120 ) ( 526960 * )
+ NEW Metal3 ( 501200 435120 ) ( 509040 * )
+ NEW Metal2 ( 513520 406000 ) ( 514640 * )
+ NEW Metal2 ( 514640 406000 ) ( * 435120 )
+ NEW Metal2 ( 521360 395920 ) ( * 406000 )
+ NEW Metal2 ( 514640 406000 ) ( 521360 * )
+ NEW Metal2 ( 483280 404880 ) ( 485520 * )
+ NEW Metal2 ( 483280 404880 ) ( * 420560 )
+ NEW Metal3 ( 483280 420560 ) ( 514640 * )
+ NEW Metal2 ( 475440 403760 ) ( 481040 * )
+ NEW Metal2 ( 481040 403760 ) ( * 404880 )
+ NEW Metal2 ( 481040 404880 ) ( 483280 * )
+ NEW Metal2 ( 456400 420560 ) ( * 425040 )
+ NEW Metal3 ( 456400 420560 ) ( 483280 * )
+ NEW Metal2 ( 447440 420560 ) ( * 425040 )
+ NEW Metal3 ( 447440 420560 ) ( 456400 * )
+ NEW Metal2 ( 479920 374640 ) ( * 403760 )
+ NEW Metal2 ( 465360 374640 ) ( * 375760 )
+ NEW Metal3 ( 465360 375760 ) ( 479920 * )
+ NEW Metal3 ( 509040 435120 ) ( * 437360 )
+ NEW Metal2 ( 526960 435120 ) ( * 442960 )
+ NEW Metal2 ( 375760 428400 ) ( * 435120 )
+ NEW Metal2 ( 420560 427280 ) ( * 428400 )
+ NEW Metal3 ( 375760 428400 ) ( 420560 * )
+ NEW Metal2 ( 420560 428400 ) ( 421680 * )
+ NEW Metal3 ( 421680 436240 ) ( 431760 * )
+ NEW Metal2 ( 434000 428400 ) ( * 436240 )
+ NEW Metal3 ( 431760 436240 ) ( 434000 * )
+ NEW Metal2 ( 434000 423920 ) ( * 428400 )
+ NEW Metal2 ( 434000 404880 ) ( * 423920 )
+ NEW Metal2 ( 421680 428400 ) ( * 450800 )
+ NEW Metal2 ( 431760 436240 ) ( * 449680 )
+ NEW Metal3 ( 434000 423920 ) ( 447440 * )
+ NEW Metal1 ( 525840 442960 ) Via1_VV
+ NEW Metal1 ( 525840 456400 ) Via1_VV
+ NEW Metal2 ( 509040 437360 ) Via2_VH
+ NEW Metal1 ( 506800 440720 ) Via1_VV
+ NEW Metal2 ( 526960 435120 ) Via2_VH
+ NEW Metal1 ( 501200 435120 ) Via1_VV
+ NEW Metal2 ( 501200 435120 ) Via2_VH
+ NEW Metal1 ( 513520 406000 ) Via1_VV
+ NEW Metal2 ( 514640 435120 ) Via2_VH
+ NEW Metal1 ( 521360 395920 ) Via1_VV
+ NEW Metal1 ( 485520 404880 ) Via1_VV
+ NEW Metal2 ( 483280 420560 ) Via2_VH
+ NEW Metal2 ( 514640 420560 ) Via2_VH
+ NEW Metal1 ( 475440 403760 ) Via1_VV
+ NEW Metal1 ( 456400 425040 ) Via1_VV
+ NEW Metal2 ( 456400 420560 ) Via2_VH
+ NEW Metal1 ( 447440 425040 ) Via1_VV
+ NEW Metal2 ( 447440 420560 ) Via2_VH
+ NEW Metal2 ( 447440 423920 ) Via2_VH
+ NEW Metal1 ( 479920 374640 ) Via1_VV
+ NEW Metal1 ( 465360 374640 ) Via1_VV
+ NEW Metal2 ( 465360 375760 ) Via2_VH
+ NEW Metal2 ( 479920 375760 ) Via2_VH
+ NEW Metal1 ( 421680 450800 ) Via1_VV
+ NEW Metal1 ( 431760 449680 ) Via1_VV
+ NEW Metal1 ( 375760 428400 ) Via1_VV
+ NEW Metal1 ( 375760 435120 ) Via1_VV
+ NEW Metal1 ( 420560 427280 ) Via1_VV
+ NEW Metal2 ( 420560 428400 ) Via2_VH
+ NEW Metal2 ( 375760 428400 ) Via2_VH
+ NEW Metal2 ( 431760 436240 ) Via2_VH
+ NEW Metal2 ( 421680 436240 ) Via2_VH
+ NEW Metal1 ( 434000 428400 ) Via1_VV
+ NEW Metal2 ( 434000 436240 ) Via2_VH
+ NEW Metal2 ( 434000 423920 ) Via2_VH
+ NEW Metal1 ( 434000 404880 ) Via1_VV
+ NEW Metal2 ( 501200 435120 ) RECT ( -280 -660 280 0 )
+ NEW Metal3 ( 514640 435120 ) RECT ( -1040 -280 0 280 )
+ NEW Metal2 ( 514640 420560 ) RECT ( -280 -1040 280 0 )
+ NEW Metal2 ( 447440 423920 ) RECT ( -280 -1040 280 0 )
+ NEW Metal2 ( 479920 375760 ) RECT ( -280 -1040 280 0 )
+ NEW Metal2 ( 375760 428400 ) RECT ( -280 -1040 280 0 )
+ NEW Metal2 ( 421680 436240 ) RECT ( -280 -1040 280 0 ) ;
+ - _0496_ ( _1143_ A1 ) ( _1140_ ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 418320 420560 ) ( 419440 * )
+ NEW Metal2 ( 418320 420560 ) ( * 425040 )
+ NEW Metal2 ( 417200 425040 ) ( 418320 * )
+ NEW Metal1 ( 419440 420560 ) Via1_VV
+ NEW Metal1 ( 417200 425040 ) Via1_VV ;
+ - _0497_ ( _1148_ A2 ) ( _1147_ A2 ) ( _1142_ A3 ) ( _1141_ ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 392560 460880 ) ( 395920 * )
+ NEW Metal3 ( 392560 435120 ) ( 416080 * )
+ NEW Metal2 ( 392560 435120 ) ( * 436240 )
+ NEW Metal2 ( 412720 426160 ) ( * 434000 )
+ NEW Metal3 ( 412720 434000 ) ( * 435120 )
+ NEW Metal2 ( 392560 436240 ) ( * 460880 )
+ NEW Metal1 ( 395920 460880 ) Via1_VV
+ NEW Metal1 ( 392560 436240 ) Via1_VV
+ NEW Metal1 ( 416080 435120 ) Via1_VV
+ NEW Metal2 ( 416080 435120 ) Via2_VH
+ NEW Metal2 ( 392560 435120 ) Via2_VH
+ NEW Metal1 ( 412720 426160 ) Via1_VV
+ NEW Metal2 ( 412720 434000 ) Via2_VH
+ NEW Metal2 ( 416080 435120 ) RECT ( -280 -660 280 0 ) ;
+ - _0498_ ( _1143_ A2 ) ( _1142_ ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 416080 420560 ) ( * 422800 )
+ NEW Metal2 ( 411600 422800 ) ( 416080 * )
+ NEW Metal2 ( 411600 422800 ) ( * 428400 )
+ NEW Metal1 ( 416080 420560 ) Via1_VV
+ NEW Metal1 ( 411600 428400 ) Via1_VV ;
+ - _0499_ ( _1148_ A1 ) ( _1147_ A1 ) ( _1144_ ZN ) + USE SIGNAL
+ + ROUTED Metal3 ( 390320 436240 ) ( 412720 * )
+ NEW Metal3 ( 412720 436240 ) ( 418320 * )
+ NEW Metal2 ( 412720 436240 ) ( * 456400 )
+ NEW Metal1 ( 412720 456400 ) Via1_VV
+ NEW Metal2 ( 412720 436240 ) Via2_VH
+ NEW Metal1 ( 390320 436240 ) Via1_VV
+ NEW Metal2 ( 390320 436240 ) Via2_VH
+ NEW Metal1 ( 418320 436240 ) Via1_HV
+ NEW Metal2 ( 418320 436240 ) Via2_VH
+ NEW Metal2 ( 390320 436240 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 418320 436240 ) RECT ( -280 -660 280 0 ) ;
+ - _0500_ ( _1146_ B2 ) ( _1145_ ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 416080 451920 ) ( * 459760 )
+ NEW Metal2 ( 408240 459760 ) ( 416080 * )
+ NEW Metal1 ( 416080 451920 ) Via1_VV
+ NEW Metal1 ( 408240 459760 ) Via1_VV ;
+ - _0501_ ( _1147_ B ) ( _1146_ ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 419440 436800 ) ( * 449680 )
+ NEW Metal2 ( 419440 436800 ) ( 420560 * )
+ NEW Metal2 ( 420560 435120 ) ( * 436800 )
+ NEW Metal1 ( 419440 449680 ) Via1_VV
+ NEW Metal1 ( 420560 435120 ) Via1_VV ;
+ - _0502_ ( _1153_ A2 ) ( _1150_ A2 ) ( _1149_ A2 ) ( _1148_ ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 358960 442960 ) ( * 448560 )
+ NEW Metal2 ( 363440 427280 ) ( * 432880 )
+ NEW Metal3 ( 363440 432880 ) ( 389200 * )
+ NEW Metal3 ( 358960 432880 ) ( 363440 * )
+ NEW Metal2 ( 358960 432880 ) ( * 442960 )
+ NEW Metal1 ( 358960 442960 ) Via1_VV
+ NEW Metal1 ( 358960 448560 ) Via1_VV
+ NEW Metal1 ( 363440 427280 ) Via1_VV
+ NEW Metal2 ( 363440 432880 ) Via2_VH
+ NEW Metal1 ( 389200 432880 ) Via1_VV
+ NEW Metal2 ( 389200 432880 ) Via2_VH
+ NEW Metal2 ( 358960 432880 ) Via2_VH
+ NEW Metal2 ( 389200 432880 ) RECT ( -280 -660 280 0 ) ;
+ - _0503_ ( _1152_ A2 ) ( _1149_ ZN ) + USE SIGNAL
+ + ROUTED Metal3 ( 351120 442960 ) ( 360080 * )
+ NEW Metal1 ( 360080 442960 ) Via1_VV
+ NEW Metal2 ( 360080 442960 ) Via2_VH
+ NEW Metal1 ( 351120 442960 ) Via1_VV
+ NEW Metal2 ( 351120 442960 ) Via2_VH
+ NEW Metal2 ( 360080 442960 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 351120 442960 ) RECT ( -280 -660 280 0 ) ;
+ - _0504_ ( _1151_ A2 ) ( _1150_ ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 366800 427280 ) ( * 435120 )
+ NEW Metal2 ( 366800 435120 ) ( 370160 * )
+ NEW Metal1 ( 366800 427280 ) Via1_VV
+ NEW Metal1 ( 370160 435120 ) Via1_VV ;
+ - _0505_ ( _1155_ A2 ) ( _1152_ A3 ) ( _1151_ ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 353360 437360 ) ( * 442960 )
+ NEW Metal3 ( 353360 437360 ) ( 372400 * )
+ NEW Metal2 ( 353360 453040 ) ( * 457520 )
+ NEW Metal2 ( 353360 453040 ) ( 355600 * )
+ NEW Metal2 ( 355600 442960 ) ( * 453040 )
+ NEW Metal2 ( 353360 442960 ) ( 355600 * )
+ NEW Metal1 ( 353360 442960 ) Via1_HV
+ NEW Metal2 ( 353360 437360 ) Via2_VH
+ NEW Metal1 ( 372400 437360 ) Via1_VV
+ NEW Metal2 ( 372400 437360 ) Via2_VH
+ NEW Metal1 ( 353360 457520 ) Via1_VV
+ NEW Metal2 ( 372400 437360 ) RECT ( -280 0 280 660 ) ;
+ - _0506_ ( _1154_ A2 ) ( _1153_ Z ) + USE SIGNAL
+ + ROUTED Metal2 ( 362320 453040 ) ( * 457520 )
+ NEW Metal3 ( 362320 457520 ) ( 375760 * )
+ NEW Metal1 ( 362320 453040 ) Via1_HV
+ NEW Metal2 ( 362320 457520 ) Via2_VH
+ NEW Metal1 ( 375760 457520 ) Via1_VV
+ NEW Metal2 ( 375760 457520 ) Via2_VH
+ NEW Metal2 ( 375760 457520 ) RECT ( -280 -660 280 0 ) ;
+ - _0507_ ( _1155_ B ) ( _1154_ ZN ) + USE SIGNAL
+ + ROUTED Metal3 ( 357840 458640 ) ( 376880 * )
+ NEW Metal1 ( 376880 458640 ) Via1_VV
+ NEW Metal2 ( 376880 458640 ) Via2_VH
+ NEW Metal1 ( 357840 458640 ) Via1_VV
+ NEW Metal2 ( 357840 458640 ) Via2_VH
+ NEW Metal2 ( 376880 458640 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 357840 458640 ) RECT ( -280 -660 280 0 ) ;
+ - _0508_ ( _1157_ A3 ) ( _1156_ Z ) + USE SIGNAL
+ + ROUTED Metal2 ( 505680 453040 ) ( 509040 * )
+ NEW Metal2 ( 509040 453040 ) ( * 459760 )
+ NEW Metal2 ( 509040 459760 ) ( 511280 * )
+ NEW Metal1 ( 505680 453040 ) Via1_VV
+ NEW Metal1 ( 511280 459760 ) Via1_HV ;
+ - _0509_ ( ANTENNA__1158__B I ) ( ANTENNA__1295__A3 I ) ( _1295_ A3 ) ( _1158_ B ) ( _1157_ ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 498960 466480 ) ( * 479920 )
+ NEW Metal3 ( 498960 481040 ) ( 512400 * )
+ NEW Metal2 ( 498960 479920 ) ( * 481040 )
+ NEW Metal2 ( 514640 460880 ) ( * 466480 )
+ NEW Metal3 ( 498960 466480 ) ( 514640 * )
+ NEW Metal2 ( 435120 459760 ) ( * 466480 )
+ NEW Metal2 ( 432880 466480 ) ( 435120 * )
+ NEW Metal3 ( 435120 466480 ) ( 498960 * )
+ NEW Metal1 ( 498960 479920 ) Via1_VV
+ NEW Metal2 ( 498960 466480 ) Via2_VH
+ NEW Metal1 ( 512400 481040 ) Via1_VV
+ NEW Metal2 ( 512400 481040 ) Via2_VH
+ NEW Metal2 ( 498960 481040 ) Via2_VH
+ NEW Metal1 ( 514640 460880 ) Via1_HV
+ NEW Metal2 ( 514640 466480 ) Via2_VH
+ NEW Metal1 ( 435120 459760 ) Via1_VV
+ NEW Metal1 ( 432880 466480 ) Via1_HV
+ NEW Metal2 ( 435120 466480 ) Via2_VH
+ NEW Metal2 ( 512400 481040 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 435120 466480 ) RECT ( -280 -1040 280 0 ) ;
+ - _0510_ ( _1159_ A2 ) ( _1158_ ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 498960 488880 ) ( 500080 * )
+ NEW Metal2 ( 500080 479920 ) ( * 488880 )
+ NEW Metal1 ( 498960 488880 ) Via1_VV
+ NEW Metal1 ( 500080 479920 ) Via1_VV ;
+ - _0511_ ( _1161_ A3 ) ( _1160_ A2 ) ( _1159_ ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 473200 492240 ) ( * 497840 )
+ NEW Metal3 ( 473200 492240 ) ( 497840 * )
+ NEW Metal2 ( 469840 500080 ) ( * 513520 )
+ NEW Metal2 ( 469840 500080 ) ( 470960 * )
+ NEW Metal2 ( 470960 497840 ) ( * 500080 )
+ NEW Metal2 ( 470960 497840 ) ( 473200 * )
+ NEW Metal1 ( 473200 497840 ) Via1_VV
+ NEW Metal2 ( 473200 492240 ) Via2_VH
+ NEW Metal1 ( 497840 492240 ) Via1_VV
+ NEW Metal2 ( 497840 492240 ) Via2_VH
+ NEW Metal1 ( 469840 513520 ) Via1_VV
+ NEW Metal2 ( 497840 492240 ) RECT ( -280 -660 280 0 ) ;
+ - _0512_ ( _1175_ A2 ) ( _1168_ B ) ( _1164_ A2 ) ( _1163_ A2 ) ( _1160_ ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 494480 505680 ) ( * 506800 )
+ NEW Metal3 ( 494480 506800 ) ( 502320 * )
+ NEW Metal2 ( 468720 507920 ) ( * 511280 )
+ NEW Metal3 ( 468720 507920 ) ( 494480 * )
+ NEW Metal3 ( 494480 506800 ) ( * 507920 )
+ NEW Metal2 ( 463120 505680 ) ( * 507920 )
+ NEW Metal3 ( 463120 507920 ) ( 468720 * )
+ NEW Metal2 ( 456400 500080 ) ( * 507920 )
+ NEW Metal3 ( 456400 507920 ) ( 463120 * )
+ NEW Metal1 ( 494480 505680 ) Via1_VV
+ NEW Metal2 ( 494480 506800 ) Via2_VH
+ NEW Metal1 ( 502320 506800 ) Via1_VV
+ NEW Metal2 ( 502320 506800 ) Via2_VH
+ NEW Metal1 ( 468720 511280 ) Via1_VV
+ NEW Metal2 ( 468720 507920 ) Via2_VH
+ NEW Metal1 ( 463120 505680 ) Via1_VV
+ NEW Metal2 ( 463120 507920 ) Via2_VH
+ NEW Metal1 ( 456400 500080 ) Via1_VV
+ NEW Metal2 ( 456400 507920 ) Via2_VH
+ NEW Metal2 ( 502320 506800 ) RECT ( -280 -660 280 0 ) ;
+ - _0513_ ( _1172_ B2 ) ( _1162_ A2 ) ( _1161_ ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 466480 500080 ) ( * 520240 )
+ NEW Metal2 ( 463120 520240 ) ( 466480 * )
+ NEW Metal3 ( 466480 506800 ) ( 474320 * )
+ NEW Metal1 ( 466480 500080 ) Via1_VV
+ NEW Metal1 ( 463120 520240 ) Via1_VV
+ NEW Metal1 ( 474320 506800 ) Via1_VV
+ NEW Metal2 ( 474320 506800 ) Via2_VH
+ NEW Metal2 ( 466480 506800 ) Via2_VH
+ NEW Metal2 ( 474320 506800 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 466480 506800 ) RECT ( -280 -1040 280 0 ) ;
+ - _0514_ ( _1163_ B ) ( _1162_ ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 459760 504560 ) ( * 519120 )
+ NEW Metal1 ( 459760 504560 ) Via1_VV
+ NEW Metal1 ( 459760 519120 ) Via1_VV ;
+ - _0515_ ( _1170_ A1 ) ( _1164_ ZN ) + USE SIGNAL
+ + ROUTED Metal3 ( 446320 488880 ) ( 457520 * )
+ NEW Metal2 ( 457520 488880 ) ( * 496720 )
+ NEW Metal1 ( 446320 488880 ) Via1_VV
+ NEW Metal2 ( 446320 488880 ) Via2_VH
+ NEW Metal2 ( 457520 488880 ) Via2_VH
+ NEW Metal1 ( 457520 496720 ) Via1_VV
+ NEW Metal2 ( 446320 488880 ) RECT ( -280 -660 280 0 ) ;
+ - _0516_ ( _1187_ A2 ) ( _1171_ A2 ) ( _1167_ A1 ) ( _1165_ ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 474320 478800 ) ( * 479920 )
+ NEW Metal2 ( 469840 478800 ) ( 474320 * )
+ NEW Metal2 ( 469840 467600 ) ( * 478800 )
+ NEW Metal2 ( 482160 486640 ) ( * 487760 )
+ NEW Metal3 ( 474320 486640 ) ( 482160 * )
+ NEW Metal2 ( 474320 479920 ) ( * 486640 )
+ NEW Metal2 ( 479920 486640 ) ( * 497840 )
+ NEW Metal1 ( 474320 479920 ) Via1_VV
+ NEW Metal1 ( 469840 467600 ) Via1_HV
+ NEW Metal1 ( 482160 487760 ) Via1_VV
+ NEW Metal2 ( 482160 486640 ) Via2_VH
+ NEW Metal2 ( 474320 486640 ) Via2_VH
+ NEW Metal1 ( 479920 497840 ) Via1_HV
+ NEW Metal2 ( 479920 486640 ) Via2_VH
+ NEW Metal3 ( 479920 486640 ) RECT ( -1040 -280 0 280 ) ;
+ - _0517_ ( _1187_ B1 ) ( _1186_ B1 ) ( _1171_ A3 ) ( _1167_ A2 ) ( _1166_ ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 475440 464240 ) ( * 466480 )
+ NEW Metal3 ( 475440 464240 ) ( 483280 * )
+ NEW Metal2 ( 483280 458640 ) ( * 464240 )
+ NEW Metal2 ( 481040 464240 ) ( * 488880 )
+ NEW Metal3 ( 468720 487760 ) ( 481040 * )
+ NEW Metal2 ( 481040 497840 ) ( 482160 * )
+ NEW Metal2 ( 481040 488880 ) ( * 497840 )
+ NEW Metal1 ( 475440 466480 ) Via1_HV
+ NEW Metal2 ( 475440 464240 ) Via2_VH
+ NEW Metal2 ( 483280 464240 ) Via2_VH
+ NEW Metal1 ( 483280 458640 ) Via1_HV
+ NEW Metal1 ( 481040 488880 ) Via1_VV
+ NEW Metal2 ( 481040 464240 ) Via2_VH
+ NEW Metal1 ( 468720 487760 ) Via1_VV
+ NEW Metal2 ( 468720 487760 ) Via2_VH
+ NEW Metal2 ( 481040 487760 ) Via2_VH
+ NEW Metal1 ( 482160 497840 ) Via1_HV
+ NEW Metal3 ( 481040 464240 ) RECT ( -1040 -280 0 280 )
+ NEW Metal2 ( 468720 487760 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 481040 487760 ) RECT ( -280 -1040 280 0 ) ;
+ - _0518_ ( _1175_ A3 ) ( _1168_ A2 ) ( _1167_ ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 484400 505680 ) ( 487760 * )
+ NEW Metal2 ( 484400 490000 ) ( * 505680 )
+ NEW Metal3 ( 487760 505680 ) ( 500080 * )
+ NEW Metal1 ( 487760 505680 ) Via1_VV
+ NEW Metal1 ( 484400 490000 ) Via1_VV
+ NEW Metal1 ( 500080 505680 ) Via1_HV
+ NEW Metal2 ( 500080 505680 ) Via2_VH
+ NEW Metal2 ( 487760 505680 ) Via2_VH
+ NEW Metal2 ( 500080 505680 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 487760 505680 ) RECT ( -280 -1040 280 0 ) ;
+ - _0519_ ( _1177_ A1 ) ( _1172_ A2 ) ( _1169_ A2 ) ( _1168_ ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 481040 500080 ) ( * 504560 )
+ NEW Metal2 ( 478800 500080 ) ( 481040 * )
+ NEW Metal2 ( 478800 495600 ) ( * 500080 )
+ NEW Metal3 ( 458640 495600 ) ( 478800 * )
+ NEW Metal2 ( 458640 492240 ) ( * 495600 )
+ NEW Metal3 ( 481040 503440 ) ( 490000 * )
+ NEW Metal3 ( 490000 497840 ) ( 515760 * )
+ NEW Metal2 ( 490000 497840 ) ( * 503440 )
+ NEW Metal1 ( 481040 504560 ) Via1_VV
+ NEW Metal2 ( 478800 495600 ) Via2_VH
+ NEW Metal2 ( 458640 495600 ) Via2_VH
+ NEW Metal1 ( 458640 492240 ) Via1_VV
+ NEW Metal1 ( 490000 503440 ) Via1_VV
+ NEW Metal2 ( 490000 503440 ) Via2_VH
+ NEW Metal2 ( 481040 503440 ) Via2_VH
+ NEW Metal1 ( 515760 497840 ) Via1_VV
+ NEW Metal2 ( 515760 497840 ) Via2_VH
+ NEW Metal2 ( 490000 497840 ) Via2_VH
+ NEW Metal2 ( 490000 503440 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 481040 503440 ) RECT ( -280 -1040 280 0 )
+ NEW Metal2 ( 515760 497840 ) RECT ( -280 -660 280 0 ) ;
+ - _0520_ ( _1170_ A2 ) ( _1169_ ZN ) + USE SIGNAL
+ + ROUTED Metal3 ( 447440 490000 ) ( 455280 * )
+ NEW Metal2 ( 455280 490000 ) ( * 491120 )
+ NEW Metal1 ( 447440 490000 ) Via1_VV
+ NEW Metal2 ( 447440 490000 ) Via2_VH
+ NEW Metal2 ( 455280 490000 ) Via2_VH
+ NEW Metal1 ( 455280 491120 ) Via1_HV
+ NEW Metal2 ( 447440 490000 ) RECT ( -280 -660 280 0 ) ;
+ - _0521_ ( _1172_ B1 ) ( _1171_ ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 476560 500080 ) ( * 505680 )
+ NEW Metal1 ( 476560 505680 ) Via1_VV
+ NEW Metal1 ( 476560 500080 ) Via1_VV ;
+ - _0522_ ( _1173_ A2 ) ( _1172_ ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 478800 506800 ) ( 479920 * )
+ NEW Metal2 ( 478800 506800 ) ( * 513520 )
+ NEW Metal1 ( 479920 506800 ) Via1_VV
+ NEW Metal1 ( 478800 513520 ) Via1_VV ;
+ - _0523_ ( _1178_ A1 ) ( _1174_ ZN ) + USE SIGNAL
+ + ROUTED Metal3 ( 515760 504560 ) ( 524720 * )
+ NEW Metal1 ( 515760 504560 ) Via1_VV
+ NEW Metal2 ( 515760 504560 ) Via2_VH
+ NEW Metal1 ( 524720 504560 ) Via1_VV
+ NEW Metal2 ( 524720 504560 ) Via2_VH
+ NEW Metal2 ( 515760 504560 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 524720 504560 ) RECT ( -280 -660 280 0 ) ;
+ - _0524_ ( _1178_ A2 ) ( _1175_ ZN ) + USE SIGNAL
+ + ROUTED Metal3 ( 505680 504560 ) ( 513520 * )
+ NEW Metal1 ( 505680 504560 ) Via1_VV
+ NEW Metal2 ( 505680 504560 ) Via2_VH
+ NEW Metal1 ( 513520 504560 ) Via1_VV
+ NEW Metal2 ( 513520 504560 ) Via2_VH
+ NEW Metal2 ( 505680 504560 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 513520 504560 ) RECT ( -280 -660 280 0 ) ;
+ - _0525_ ( _1177_ A2 ) ( _1176_ ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 512400 497840 ) ( * 498960 )
+ NEW Metal3 ( 506800 498960 ) ( 512400 * )
+ NEW Metal1 ( 512400 497840 ) Via1_VV
+ NEW Metal2 ( 512400 498960 ) Via2_VH
+ NEW Metal1 ( 506800 498960 ) Via1_VV
+ NEW Metal2 ( 506800 498960 ) Via2_VH
+ NEW Metal2 ( 506800 498960 ) RECT ( -280 -660 280 0 ) ;
+ - _0526_ ( _1179_ A2 ) ( _1178_ B ) ( _1177_ ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 514640 492240 ) ( * 496720 )
+ NEW Metal3 ( 514640 492240 ) ( 523600 * )
+ NEW Metal2 ( 518000 492240 ) ( * 503440 )
+ NEW Metal1 ( 514640 496720 ) Via1_VV
+ NEW Metal2 ( 514640 492240 ) Via2_VH
+ NEW Metal1 ( 523600 492240 ) Via1_VV
+ NEW Metal2 ( 523600 492240 ) Via2_VH
+ NEW Metal1 ( 518000 503440 ) Via1_VV
+ NEW Metal2 ( 518000 492240 ) Via2_VH
+ NEW Metal2 ( 523600 492240 ) RECT ( -280 -660 280 0 )
+ NEW Metal3 ( 518000 492240 ) RECT ( -1040 -280 0 280 ) ;
+ - _0527_ ( _1180_ I ) ( _1179_ Z ) + USE SIGNAL
+ + ROUTED Metal3 ( 526960 483280 ) ( 532560 * )
+ NEW Metal2 ( 526960 483280 ) ( * 487760 )
+ NEW Metal1 ( 532560 483280 ) Via1_VV
+ NEW Metal2 ( 532560 483280 ) Via2_VH
+ NEW Metal2 ( 526960 483280 ) Via2_VH
+ NEW Metal1 ( 526960 487760 ) Via1_HV
+ NEW Metal2 ( 532560 483280 ) RECT ( -280 -660 280 0 ) ;
+ - _0528_ ( _1186_ A2 ) ( _1184_ A2 ) ( _1181_ ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 496720 473200 ) ( * 479920 )
+ NEW Metal2 ( 487760 479920 ) ( 496720 * )
+ NEW Metal2 ( 497840 458640 ) ( * 463120 )
+ NEW Metal2 ( 496720 463120 ) ( 497840 * )
+ NEW Metal2 ( 496720 463120 ) ( * 473200 )
+ NEW Metal1 ( 496720 473200 ) Via1_HV
+ NEW Metal1 ( 487760 479920 ) Via1_VV
+ NEW Metal1 ( 497840 458640 ) Via1_HV ;
+ - _0529_ ( _1184_ B2 ) ( _1182_ ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 473200 474320 ) ( 478800 * )
+ NEW Metal1 ( 478800 474320 ) Via1_HV
+ NEW Metal1 ( 473200 474320 ) Via1_VV ;
+ - _0530_ ( _1184_ C ) ( _1183_ Z ) + USE SIGNAL
+ + ROUTED Metal3 ( 493360 473200 ) ( 506800 * )
+ NEW Metal1 ( 493360 473200 ) Via1_HV
+ NEW Metal2 ( 493360 473200 ) Via2_VH
+ NEW Metal1 ( 506800 473200 ) Via1_VV
+ NEW Metal2 ( 506800 473200 ) Via2_VH
+ NEW Metal2 ( 493360 473200 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 506800 473200 ) RECT ( -280 -660 280 0 ) ;
+ - _0531_ ( _1189_ A1 ) ( _1184_ ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 475440 457520 ) ( 477680 * )
+ NEW Metal2 ( 477680 457520 ) ( * 472080 )
+ NEW Metal1 ( 475440 457520 ) Via1_HV
+ NEW Metal1 ( 477680 472080 ) Via1_VV ;
+ - _0532_ ( _1186_ C ) ( _1185_ ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 493360 458640 ) ( * 466480 )
+ NEW Metal2 ( 493360 466480 ) ( 495600 * )
+ NEW Metal1 ( 493360 458640 ) Via1_HV
+ NEW Metal1 ( 495600 466480 ) Via1_VV ;
+ - _0533_ ( _1187_ C ) ( _1186_ ZN ) + USE SIGNAL
+ + ROUTED Metal3 ( 476560 467600 ) ( 484400 * )
+ NEW Metal2 ( 484400 460880 ) ( * 467600 )
+ NEW Metal1 ( 476560 467600 ) Via1_HV
+ NEW Metal2 ( 476560 467600 ) Via2_VH
+ NEW Metal2 ( 484400 467600 ) Via2_VH
+ NEW Metal1 ( 484400 460880 ) Via1_VV
+ NEW Metal2 ( 476560 467600 ) RECT ( -280 -660 280 0 ) ;
+ - _0534_ ( _1189_ A2 ) ( _1187_ ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 469840 458640 ) ( * 465360 )
+ NEW Metal1 ( 469840 458640 ) Via1_HV
+ NEW Metal1 ( 469840 465360 ) Via1_HV ;
+ - _0535_ ( _1189_ B ) ( _1188_ ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 460880 458640 ) ( * 466480 )
+ NEW Metal2 ( 460880 458640 ) ( 464240 * )
+ NEW Metal1 ( 460880 466480 ) Via1_VV
+ NEW Metal1 ( 464240 458640 ) Via1_HV ;
+ - _0536_ ( ANTENNA__1190__A2 I ) ( ANTENNA__1193__B1 I ) ( ANTENNA__1198__B1 I ) ( ANTENNA__1200__A1 I ) ( ANTENNA__1202__A1 I ) ( ANTENNA__1205__A1 I ) ( _1205_ A1 )
+ ( _1202_ A1 ) ( _1200_ A1 ) ( _1198_ B1 ) ( _1193_ B1 ) ( _1190_ A2 ) ( _1189_ ZN ) + USE SIGNAL
+ + ROUTED Metal3 ( 539280 450800 ) ( 550480 * )
+ NEW Metal2 ( 544880 444080 ) ( * 450800 )
+ NEW Metal2 ( 538160 442960 ) ( 539280 * )
+ NEW Metal2 ( 539280 442960 ) ( * 450800 )
+ NEW Metal3 ( 524720 442960 ) ( 538160 * )
+ NEW Metal2 ( 515760 442960 ) ( * 449680 )
+ NEW Metal3 ( 515760 442960 ) ( 524720 * )
+ NEW Metal3 ( 504560 437360 ) ( * 440720 )
+ NEW Metal3 ( 504560 440720 ) ( 515760 * )
+ NEW Metal3 ( 515760 440720 ) ( * 442960 )
+ NEW Metal3 ( 488880 440720 ) ( 504560 * )
+ NEW Metal2 ( 466480 441840 ) ( * 456400 )
+ NEW Metal3 ( 466480 441840 ) ( 488880 * )
+ NEW Metal3 ( 488880 440720 ) ( * 441840 )
+ NEW Metal2 ( 465360 444080 ) ( 466480 * )
+ NEW Metal2 ( 463120 449680 ) ( 466480 * )
+ NEW Metal3 ( 460880 441840 ) ( 466480 * )
+ NEW Metal2 ( 459760 427280 ) ( 460880 * )
+ NEW Metal2 ( 460880 427280 ) ( * 441840 )
+ NEW Metal2 ( 504560 436240 ) ( * 437360 )
+ NEW Metal1 ( 539280 450800 ) Via1_VV
+ NEW Metal2 ( 539280 450800 ) Via2_VH
+ NEW Metal1 ( 550480 450800 ) Via1_VV
+ NEW Metal2 ( 550480 450800 ) Via2_VH
+ NEW Metal1 ( 544880 444080 ) Via1_VV
+ NEW Metal2 ( 544880 450800 ) Via2_VH
+ NEW Metal1 ( 538160 442960 ) Via1_VV
+ NEW Metal1 ( 524720 442960 ) Via1_VV
+ NEW Metal2 ( 524720 442960 ) Via2_VH
+ NEW Metal2 ( 538160 442960 ) Via2_VH
+ NEW Metal1 ( 515760 449680 ) Via1_VV
+ NEW Metal2 ( 515760 442960 ) Via2_VH
+ NEW Metal2 ( 504560 437360 ) Via2_VH
+ NEW Metal1 ( 488880 440720 ) Via1_VV
+ NEW Metal2 ( 488880 440720 ) Via2_VH
+ NEW Metal1 ( 466480 456400 ) Via1_HV
+ NEW Metal2 ( 466480 441840 ) Via2_VH
+ NEW Metal1 ( 465360 444080 ) Via1_VV
+ NEW Metal1 ( 463120 449680 ) Via1_VV
+ NEW Metal2 ( 460880 441840 ) Via2_VH
+ NEW Metal1 ( 460880 441840 ) Via1_VV
+ NEW Metal1 ( 504560 436240 ) Via1_VV
+ NEW Metal1 ( 459760 427280 ) Via1_VV
+ NEW Metal2 ( 539280 450800 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 550480 450800 ) RECT ( -280 -660 280 0 )
+ NEW Metal3 ( 544880 450800 ) RECT ( -1040 -280 0 280 )
+ NEW Metal2 ( 524720 442960 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 538160 442960 ) RECT ( -280 -1040 280 0 )
+ NEW Metal2 ( 488880 440720 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 460880 441840 ) RECT ( -280 -1040 280 0 ) ;
+ - _0537_ ( _1191_ B ) ( _1190_ ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 459760 444080 ) ( * 448560 )
+ NEW Metal1 ( 455280 448560 ) ( 459760 * )
+ NEW Metal2 ( 455280 448560 ) ( * 450800 )
+ NEW Metal2 ( 454160 450800 ) ( 455280 * )
+ NEW Metal1 ( 459760 444080 ) Via1_VV
+ NEW Metal1 ( 459760 448560 ) Via1_HV
+ NEW Metal1 ( 455280 448560 ) Via1_HV
+ NEW Metal1 ( 454160 450800 ) Via1_VV ;
+ - _0538_ ( _1193_ B2 ) ( _1192_ Z ) + USE SIGNAL
+ + ROUTED Metal3 ( 462000 437360 ) ( 474320 * )
+ NEW Metal2 ( 462000 427280 ) ( * 437360 )
+ NEW Metal2 ( 474320 436240 ) ( * 437360 )
+ NEW Metal2 ( 462000 437360 ) Via2_VH
+ NEW Metal2 ( 474320 437360 ) Via2_VH
+ NEW Metal1 ( 474320 436240 ) Via1_VV
+ NEW Metal1 ( 462000 427280 ) Via1_HV ;
+ - _0539_ ( _1194_ A2 ) ( _1193_ ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 458640 413840 ) ( 459760 * )
+ NEW Metal2 ( 458640 413840 ) ( * 425040 )
+ NEW Metal1 ( 459760 413840 ) Via1_VV
+ NEW Metal1 ( 458640 425040 ) Via1_VV ;
+ - _0540_ ( _1204_ A2 ) ( _1201_ A2 ) ( _1200_ A2 ) ( _1197_ A1 ) ( _1195_ Z ) + USE SIGNAL
+ + ROUTED Metal3 ( 502320 441840 ) ( 513520 * )
+ NEW Metal2 ( 513520 437360 ) ( 514640 * )
+ NEW Metal2 ( 513520 437360 ) ( * 441840 )
+ NEW Metal3 ( 513520 448560 ) ( 526960 * )
+ NEW Metal2 ( 513520 441840 ) ( * 448560 )
+ NEW Metal2 ( 533680 442960 ) ( * 448560 )
+ NEW Metal3 ( 526960 448560 ) ( 533680 * )
+ NEW Metal1 ( 513520 441840 ) Via1_VV
+ NEW Metal2 ( 513520 441840 ) Via2_VH
+ NEW Metal1 ( 502320 441840 ) Via1_HV
+ NEW Metal2 ( 502320 441840 ) Via2_VH
+ NEW Metal1 ( 514640 437360 ) Via1_VV
+ NEW Metal1 ( 526960 448560 ) Via1_VV
+ NEW Metal2 ( 526960 448560 ) Via2_VH
+ NEW Metal2 ( 513520 448560 ) Via2_VH
+ NEW Metal1 ( 533680 442960 ) Via1_VV
+ NEW Metal2 ( 533680 448560 ) Via2_VH
+ NEW Metal2 ( 513520 441840 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 502320 441840 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 526960 448560 ) RECT ( -280 -660 280 0 ) ;
+ - _0541_ ( _1197_ A2 ) ( _1196_ ZN ) + USE SIGNAL
+ + ROUTED Metal3 ( 500080 428400 ) ( 512400 * )
+ NEW Metal2 ( 512400 428400 ) ( * 432880 )
+ NEW Metal1 ( 500080 428400 ) Via1_VV
+ NEW Metal2 ( 500080 428400 ) Via2_VH
+ NEW Metal2 ( 512400 428400 ) Via2_VH
+ NEW Metal1 ( 512400 432880 ) Via1_VV
+ NEW Metal2 ( 500080 428400 ) RECT ( -280 -660 280 0 ) ;
+ - _0542_ ( _1198_ B2 ) ( _1197_ ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 506800 435120 ) ( 513520 * )
+ NEW Metal1 ( 513520 435120 ) Via1_VV
+ NEW Metal1 ( 506800 435120 ) Via1_HV ;
+ - _0543_ ( _1199_ A2 ) ( _1198_ ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 510160 429520 ) ( * 430640 )
+ NEW Metal3 ( 503440 430640 ) ( 510160 * )
+ NEW Metal2 ( 503440 430640 ) ( * 434000 )
+ NEW Metal1 ( 510160 429520 ) Via1_VV
+ NEW Metal2 ( 510160 430640 ) Via2_VH
+ NEW Metal2 ( 503440 430640 ) Via2_VH
+ NEW Metal1 ( 503440 434000 ) Via1_VV ;
+ - _0544_ ( _1203_ A2 ) ( _1200_ ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 537040 429520 ) ( 538160 * )
+ NEW Metal2 ( 537040 429520 ) ( * 440720 )
+ NEW Metal1 ( 537040 440720 ) Via1_VV
+ NEW Metal1 ( 538160 429520 ) Via1_VV ;
+ - _0545_ ( _1202_ A2 ) ( _1201_ ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 516880 442960 ) ( 520240 * )
+ NEW Metal1 ( 520240 442960 ) Via1_VV
+ NEW Metal1 ( 516880 442960 ) Via1_VV ;
+ - _0546_ ( _1206_ A2 ) ( _1203_ A3 ) ( _1202_ ZN ) + USE SIGNAL
+ + ROUTED Metal3 ( 522480 444080 ) ( 542640 * )
+ NEW Metal2 ( 540400 427280 ) ( 542640 * )
+ NEW Metal2 ( 542640 427280 ) ( * 457520 )
+ NEW Metal1 ( 542640 457520 ) Via1_VV
+ NEW Metal1 ( 522480 444080 ) Via1_VV
+ NEW Metal2 ( 522480 444080 ) Via2_VH
+ NEW Metal2 ( 542640 444080 ) Via2_VH
+ NEW Metal1 ( 540400 427280 ) Via1_HV
+ NEW Metal2 ( 522480 444080 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 542640 444080 ) RECT ( -280 -1040 280 0 ) ;
+ - _0547_ ( _1205_ A2 ) ( _1204_ Z ) + USE SIGNAL
+ + ROUTED Metal2 ( 530320 450800 ) ( 534800 * )
+ NEW Metal1 ( 534800 450800 ) Via1_VV
+ NEW Metal1 ( 530320 450800 ) Via1_HV ;
+ - _0548_ ( _1206_ B ) ( _1205_ ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 538160 453040 ) ( 539280 * )
+ NEW Metal2 ( 539280 453040 ) ( * 458640 )
+ NEW Metal2 ( 538160 458640 ) ( 539280 * )
+ NEW Metal1 ( 538160 453040 ) Via1_VV
+ NEW Metal1 ( 538160 458640 ) Via1_VV ;
+ - _0549_ ( _1246_ A1 ) ( _1208_ A4 ) ( _1207_ Z ) + USE SIGNAL
+ + ROUTED Metal2 ( 501200 390320 ) ( * 398160 )
+ NEW Metal1 ( 491120 398160 ) ( 501200 * )
+ NEW Metal2 ( 491120 394800 ) ( * 398160 )
+ NEW Metal2 ( 488880 394800 ) ( 491120 * )
+ NEW Metal2 ( 496720 373520 ) ( * 398160 )
+ NEW Metal1 ( 501200 390320 ) Via1_HV
+ NEW Metal1 ( 501200 398160 ) Via1_HV
+ NEW Metal1 ( 491120 398160 ) Via1_HV
+ NEW Metal1 ( 488880 394800 ) Via1_VV
+ NEW Metal1 ( 496720 373520 ) Via1_HV
+ NEW Metal1 ( 496720 398160 ) Via1_HV
+ NEW Metal1 ( 496720 398160 ) RECT ( -1260 -230 0 230 ) ;
+ - _0550_ ( _1323_ A3 ) ( _1209_ B ) ( _1208_ ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 505680 335440 ) ( * 343280 )
+ NEW Metal2 ( 505680 343280 ) ( 509040 * )
+ NEW Metal2 ( 509040 343280 ) ( * 374640 )
+ NEW Metal2 ( 509040 374640 ) ( 510160 * )
+ NEW Metal3 ( 459760 347760 ) ( 509040 * )
+ NEW Metal1 ( 505680 335440 ) Via1_VV
+ NEW Metal1 ( 510160 374640 ) Via1_HV
+ NEW Metal1 ( 459760 347760 ) Via1_VV
+ NEW Metal2 ( 459760 347760 ) Via2_VH
+ NEW Metal2 ( 509040 347760 ) Via2_VH
+ NEW Metal2 ( 459760 347760 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 509040 347760 ) RECT ( -280 -1040 280 0 ) ;
+ - _0551_ ( _1210_ A2 ) ( _1209_ ZN ) + USE SIGNAL
+ + ROUTED Metal3 ( 467600 332080 ) ( 496720 * )
+ NEW Metal2 ( 496720 330960 ) ( * 332080 )
+ NEW Metal1 ( 467600 332080 ) Via1_VV
+ NEW Metal2 ( 467600 332080 ) Via2_VH
+ NEW Metal2 ( 496720 332080 ) Via2_VH
+ NEW Metal1 ( 496720 330960 ) Via1_VV
+ NEW Metal2 ( 467600 332080 ) RECT ( -280 -660 280 0 ) ;
+ - _0552_ ( _1212_ A3 ) ( _1211_ A2 ) ( _1210_ ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 468720 317520 ) ( * 319200 )
+ NEW Metal3 ( 464240 326480 ) ( 476560 * )
+ NEW Metal2 ( 464240 326480 ) ( * 330960 )
+ NEW Metal2 ( 468720 319200 ) ( 473200 * )
+ NEW Metal2 ( 473200 319200 ) ( * 326480 )
+ NEW Metal1 ( 468720 317520 ) Via1_VV
+ NEW Metal1 ( 476560 326480 ) Via1_VV
+ NEW Metal2 ( 476560 326480 ) Via2_VH
+ NEW Metal2 ( 464240 326480 ) Via2_VH
+ NEW Metal1 ( 464240 330960 ) Via1_VV
+ NEW Metal2 ( 473200 326480 ) Via2_VH
+ NEW Metal2 ( 476560 326480 ) RECT ( -280 -660 280 0 )
+ NEW Metal3 ( 473200 326480 ) RECT ( -1040 -280 0 280 ) ;
+ - _0553_ ( _1225_ A2 ) ( _1217_ B ) ( _1215_ A2 ) ( _1214_ A2 ) ( _1211_ ZN ) + USE SIGNAL
+ + ROUTED Metal3 ( 492240 319760 ) ( 505680 * )
+ NEW Metal2 ( 477680 319760 ) ( * 323120 )
+ NEW Metal3 ( 477680 319760 ) ( 492240 * )
+ NEW Metal3 ( 464240 322000 ) ( 477680 * )
+ NEW Metal2 ( 465360 322000 ) ( * 325360 )
+ NEW Metal2 ( 464240 322000 ) ( 465360 * )
+ NEW Metal2 ( 464240 311920 ) ( * 322000 )
+ NEW Metal2 ( 492240 317520 ) ( * 319760 )
+ NEW Metal2 ( 505680 317520 ) ( * 319760 )
+ NEW Metal1 ( 464240 311920 ) Via1_VV
+ NEW Metal1 ( 492240 317520 ) Via1_VV
+ NEW Metal1 ( 505680 317520 ) Via1_VV
+ NEW Metal2 ( 492240 319760 ) Via2_VH
+ NEW Metal2 ( 505680 319760 ) Via2_VH
+ NEW Metal1 ( 477680 323120 ) Via1_VV
+ NEW Metal2 ( 477680 319760 ) Via2_VH
+ NEW Metal2 ( 464240 322000 ) Via2_VH
+ NEW Metal2 ( 477680 322000 ) Via2_VH
+ NEW Metal1 ( 465360 325360 ) Via1_VV
+ NEW Metal2 ( 477680 322000 ) RECT ( -280 -1040 280 0 ) ;
+ - _0554_ ( _1222_ B2 ) ( _1213_ A2 ) ( _1212_ ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 463120 301840 ) ( 465360 * )
+ NEW Metal2 ( 463120 301840 ) ( * 313040 )
+ NEW Metal2 ( 462000 313040 ) ( 463120 * )
+ NEW Metal2 ( 462000 313040 ) ( * 315280 )
+ NEW Metal3 ( 465360 302960 ) ( 477680 * )
+ NEW Metal2 ( 465360 301840 ) ( * 302960 )
+ NEW Metal1 ( 465360 301840 ) Via1_VV
+ NEW Metal1 ( 462000 315280 ) Via1_VV
+ NEW Metal1 ( 477680 302960 ) Via1_VV
+ NEW Metal2 ( 477680 302960 ) Via2_VH
+ NEW Metal2 ( 465360 302960 ) Via2_VH
+ NEW Metal2 ( 477680 302960 ) RECT ( -280 -660 280 0 ) ;
+ - _0555_ ( _1214_ B ) ( _1213_ ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 459760 301840 ) ( 462000 * )
+ NEW Metal2 ( 459760 301840 ) ( * 309680 )
+ NEW Metal1 ( 462000 301840 ) Via1_VV
+ NEW Metal1 ( 459760 309680 ) Via1_HV ;
+ - _0556_ ( _1219_ A1 ) ( _1215_ ZN ) + USE SIGNAL
+ + ROUTED Metal3 ( 446320 327600 ) ( 466480 * )
+ NEW Metal2 ( 446320 327600 ) ( * 330960 )
+ NEW Metal1 ( 466480 327600 ) Via1_VV
+ NEW Metal2 ( 466480 327600 ) Via2_VH
+ NEW Metal2 ( 446320 327600 ) Via2_VH
+ NEW Metal1 ( 446320 330960 ) Via1_VV
+ NEW Metal2 ( 466480 327600 ) RECT ( -280 -660 280 0 ) ;
+ - _0557_ ( _1225_ A3 ) ( _1217_ A2 ) ( _1216_ Z ) + USE SIGNAL
+ + ROUTED Metal2 ( 497840 315280 ) ( * 316400 )
+ NEW Metal3 ( 486640 315280 ) ( 497840 * )
+ NEW Metal2 ( 503440 315280 ) ( * 317520 )
+ NEW Metal3 ( 497840 315280 ) ( 503440 * )
+ NEW Metal1 ( 497840 316400 ) Via1_VV
+ NEW Metal2 ( 497840 315280 ) Via2_VH
+ NEW Metal1 ( 486640 315280 ) Via1_HV
+ NEW Metal2 ( 486640 315280 ) Via2_VH
+ NEW Metal1 ( 503440 317520 ) Via1_HV
+ NEW Metal2 ( 503440 315280 ) Via2_VH
+ NEW Metal2 ( 486640 315280 ) RECT ( -280 -660 280 0 ) ;
+ - _0558_ ( ANTENNA__1218__A2 I ) ( ANTENNA__1222__A2 I ) ( ANTENNA__1227__A1 I ) ( _1227_ A1 ) ( _1222_ A2 ) ( _1218_ A2 ) ( _1217_ ZN ) + USE SIGNAL
+ + ROUTED Metal3 ( 447440 316400 ) ( 472080 * )
+ NEW Metal3 ( 472080 316400 ) ( 496720 * )
+ NEW Metal2 ( 490000 302960 ) ( * 316400 )
+ NEW Metal2 ( 484400 301840 ) ( * 305200 )
+ NEW Metal3 ( 484400 305200 ) ( 490000 * )
+ NEW Metal3 ( 513520 316400 ) ( * 317520 )
+ NEW Metal3 ( 496720 316400 ) ( 513520 * )
+ NEW Metal2 ( 513520 317520 ) ( * 319200 )
+ NEW Metal2 ( 513520 333200 ) ( * 339920 )
+ NEW Metal2 ( 512400 319200 ) ( 513520 * )
+ NEW Metal2 ( 512400 319200 ) ( * 327600 )
+ NEW Metal2 ( 512400 327600 ) ( 513520 * )
+ NEW Metal2 ( 513520 327600 ) ( * 333200 )
+ NEW Metal1 ( 472080 316400 ) Via1_VV
+ NEW Metal2 ( 472080 316400 ) Via2_VH
+ NEW Metal1 ( 447440 316400 ) Via1_VV
+ NEW Metal2 ( 447440 316400 ) Via2_VH
+ NEW Metal1 ( 496720 316400 ) Via1_VV
+ NEW Metal2 ( 496720 316400 ) Via2_VH
+ NEW Metal1 ( 490000 302960 ) Via1_VV
+ NEW Metal2 ( 490000 316400 ) Via2_VH
+ NEW Metal1 ( 484400 301840 ) Via1_VV
+ NEW Metal2 ( 484400 305200 ) Via2_VH
+ NEW Metal2 ( 490000 305200 ) Via2_VH
+ NEW Metal2 ( 513520 317520 ) Via2_VH
+ NEW Metal1 ( 513520 333200 ) Via1_VV
+ NEW Metal1 ( 513520 339920 ) Via1_VV
+ NEW Metal2 ( 472080 316400 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 447440 316400 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 496720 316400 ) RECT ( -280 -660 280 0 )
+ NEW Metal3 ( 490000 316400 ) RECT ( -1040 -280 0 280 )
+ NEW Metal2 ( 490000 305200 ) RECT ( -280 -1040 280 0 ) ;
+ - _0559_ ( _1219_ A2 ) ( _1218_ ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 445200 318640 ) ( * 332080 )
+ NEW Metal1 ( 445200 318640 ) Via1_HV
+ NEW Metal1 ( 445200 332080 ) Via1_VV ;
+ - _0560_ ( _1221_ A2 ) ( _1220_ ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 485520 308560 ) ( * 309680 )
+ NEW Metal2 ( 479920 308560 ) ( 485520 * )
+ NEW Metal1 ( 485520 309680 ) Via1_VV
+ NEW Metal1 ( 479920 308560 ) Via1_HV ;
+ - _0561_ ( _1222_ B1 ) ( _1221_ ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 481040 301840 ) ( * 304080 )
+ NEW Metal3 ( 481040 304080 ) ( 486640 * )
+ NEW Metal2 ( 486640 304080 ) ( * 307440 )
+ NEW Metal1 ( 481040 301840 ) Via1_HV
+ NEW Metal2 ( 481040 304080 ) Via2_VH
+ NEW Metal2 ( 486640 304080 ) Via2_VH
+ NEW Metal1 ( 486640 307440 ) Via1_VV ;
+ - _0562_ ( _1223_ A2 ) ( _1222_ ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 481040 295120 ) ( * 297360 )
+ NEW Metal2 ( 481040 297360 ) ( 483280 * )
+ NEW Metal2 ( 483280 297360 ) ( * 299600 )
+ NEW Metal1 ( 481040 295120 ) Via1_VV
+ NEW Metal1 ( 483280 299600 ) Via1_VV ;
+ - _0563_ ( _1237_ A2 ) ( _1232_ A2 ) ( _1228_ A1 ) ( _1224_ ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 507920 337680 ) ( * 338800 )
+ NEW Metal2 ( 507920 337680 ) ( 509040 * )
+ NEW Metal2 ( 509040 326480 ) ( * 337680 )
+ NEW Metal2 ( 509040 326480 ) ( 510160 * )
+ NEW Metal2 ( 510160 325360 ) ( * 326480 )
+ NEW Metal3 ( 502320 341040 ) ( 507920 * )
+ NEW Metal2 ( 507920 338800 ) ( * 341040 )
+ NEW Metal2 ( 502320 341040 ) ( * 346640 )
+ NEW Metal1 ( 507920 338800 ) Via1_VV
+ NEW Metal1 ( 510160 325360 ) Via1_VV
+ NEW Metal1 ( 502320 341040 ) Via1_HV
+ NEW Metal2 ( 502320 341040 ) Via2_VH
+ NEW Metal2 ( 507920 341040 ) Via2_VH
+ NEW Metal1 ( 502320 346640 ) Via1_VV
+ NEW Metal2 ( 502320 341040 ) RECT ( -280 -660 280 0 ) ;
+ - _0564_ ( _1228_ A2 ) ( _1225_ ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 507920 319760 ) ( 509040 * )
+ NEW Metal2 ( 507920 319760 ) ( * 325360 )
+ NEW Metal1 ( 509040 319760 ) Via1_VV
+ NEW Metal1 ( 507920 325360 ) Via1_VV ;
+ - _0565_ ( _1227_ A2 ) ( _1226_ ZN ) + USE SIGNAL
+ + ROUTED Metal3 ( 501200 327600 ) ( 511280 * )
+ NEW Metal2 ( 511280 327600 ) ( * 332080 )
+ NEW Metal1 ( 501200 327600 ) Via1_VV
+ NEW Metal2 ( 501200 327600 ) Via2_VH
+ NEW Metal2 ( 511280 327600 ) Via2_VH
+ NEW Metal1 ( 511280 332080 ) Via1_VV
+ NEW Metal2 ( 501200 327600 ) RECT ( -280 -660 280 0 ) ;
+ - _0566_ ( _1229_ A2 ) ( _1228_ B ) ( _1227_ ZN ) + USE SIGNAL
+ + ROUTED Metal3 ( 512400 333200 ) ( 537040 * )
+ NEW Metal2 ( 514640 325360 ) ( * 333200 )
+ NEW Metal1 ( 512400 333200 ) Via1_VV
+ NEW Metal2 ( 512400 333200 ) Via2_VH
+ NEW Metal1 ( 537040 333200 ) Via1_VV
+ NEW Metal2 ( 537040 333200 ) Via2_VH
+ NEW Metal1 ( 514640 325360 ) Via1_VV
+ NEW Metal2 ( 514640 333200 ) Via2_VH
+ NEW Metal2 ( 512400 333200 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 537040 333200 ) RECT ( -280 -660 280 0 )
+ NEW Metal3 ( 514640 333200 ) RECT ( -1040 -280 0 280 ) ;
+ - _0567_ ( _1230_ I ) ( _1229_ Z ) + USE SIGNAL
+ + ROUTED Metal3 ( 520240 335440 ) ( 540400 * )
+ NEW Metal2 ( 520240 335440 ) ( * 341040 )
+ NEW Metal1 ( 540400 335440 ) Via1_HV
+ NEW Metal2 ( 540400 335440 ) Via2_VH
+ NEW Metal2 ( 520240 335440 ) Via2_VH
+ NEW Metal1 ( 520240 341040 ) Via1_HV
+ NEW Metal2 ( 540400 335440 ) RECT ( -280 -660 280 0 ) ;
+ - _0568_ ( _1251_ A1 ) ( _1250_ A1 ) ( _1238_ A1 ) ( _1232_ B2 ) ( _1231_ ZN ) + USE SIGNAL
+ + ROUTED Metal3 ( 481040 374640 ) ( 486640 * )
+ NEW Metal2 ( 481040 374640 ) ( * 388080 )
+ NEW Metal2 ( 500080 363440 ) ( * 374640 )
+ NEW Metal3 ( 486640 374640 ) ( 500080 * )
+ NEW Metal2 ( 486640 348880 ) ( * 360080 )
+ NEW Metal2 ( 485520 360080 ) ( 486640 * )
+ NEW Metal2 ( 485520 360080 ) ( * 364560 )
+ NEW Metal2 ( 485520 364560 ) ( 486640 * )
+ NEW Metal2 ( 486640 364560 ) ( * 374640 )
+ NEW Metal3 ( 486640 342160 ) ( 495600 * )
+ NEW Metal2 ( 486640 342160 ) ( * 348880 )
+ NEW Metal1 ( 486640 374640 ) Via1_VV
+ NEW Metal2 ( 486640 374640 ) Via2_VH
+ NEW Metal2 ( 481040 374640 ) Via2_VH
+ NEW Metal1 ( 481040 388080 ) Via1_HV
+ NEW Metal1 ( 500080 363440 ) Via1_VV
+ NEW Metal2 ( 500080 374640 ) Via2_VH
+ NEW Metal1 ( 486640 348880 ) Via1_VV
+ NEW Metal1 ( 495600 342160 ) Via1_VV
+ NEW Metal2 ( 495600 342160 ) Via2_VH
+ NEW Metal2 ( 486640 342160 ) Via2_VH
+ NEW Metal2 ( 486640 374640 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 495600 342160 ) RECT ( -280 -660 280 0 ) ;
+ - _0569_ ( _1240_ A1 ) ( _1232_ ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 483280 352240 ) ( * 357840 )
+ NEW Metal3 ( 483280 352240 ) ( 498960 * )
+ NEW Metal2 ( 498960 343280 ) ( * 352240 )
+ NEW Metal1 ( 483280 357840 ) Via1_VV
+ NEW Metal2 ( 483280 352240 ) Via2_VH
+ NEW Metal2 ( 498960 352240 ) Via2_VH
+ NEW Metal1 ( 498960 343280 ) Via1_VV ;
+ - _0570_ ( _1238_ B1 ) ( _1235_ A2 ) ( _1233_ ZN ) + USE SIGNAL
+ + ROUTED Metal3 ( 473200 343280 ) ( 484400 * )
+ NEW Metal2 ( 484400 343280 ) ( * 348880 )
+ NEW Metal1 ( 484400 343280 ) Via1_VV
+ NEW Metal2 ( 484400 343280 ) Via2_VH
+ NEW Metal1 ( 473200 343280 ) Via1_VV
+ NEW Metal2 ( 473200 343280 ) Via2_VH
+ NEW Metal1 ( 484400 348880 ) Via1_VV
+ NEW Metal2 ( 484400 343280 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 473200 343280 ) RECT ( -280 -660 280 0 ) ;
+ - _0571_ ( _1237_ B2 ) ( _1235_ B2 ) ( _1234_ ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 477680 342160 ) ( 478800 * )
+ NEW Metal2 ( 477680 342160 ) ( * 354480 )
+ NEW Metal3 ( 477680 348880 ) ( 495600 * )
+ NEW Metal1 ( 478800 342160 ) Via1_VV
+ NEW Metal1 ( 477680 354480 ) Via1_VV
+ NEW Metal1 ( 495600 348880 ) Via1_VV
+ NEW Metal2 ( 495600 348880 ) Via2_VH
+ NEW Metal2 ( 477680 348880 ) Via2_VH
+ NEW Metal2 ( 495600 348880 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 477680 348880 ) RECT ( -280 -1040 280 0 ) ;
+ - _0572_ ( _1240_ A2 ) ( _1235_ ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 484400 339920 ) ( 485520 * )
+ NEW Metal2 ( 485520 339920 ) ( * 356720 )
+ NEW Metal1 ( 484400 339920 ) Via1_HV
+ NEW Metal1 ( 485520 356720 ) Via1_HV ;
+ - _0573_ ( _1239_ A1 ) ( _1236_ Z ) + USE SIGNAL
+ + ROUTED Metal2 ( 513520 351120 ) ( 514640 * )
+ NEW Metal2 ( 514640 351120 ) ( * 355600 )
+ NEW Metal1 ( 513520 351120 ) Via1_VV
+ NEW Metal1 ( 514640 355600 ) Via1_VV ;
+ - _0574_ ( _1239_ A2 ) ( _1237_ ZN ) + USE SIGNAL
+ + ROUTED Metal3 ( 501200 348880 ) ( 511280 * )
+ NEW Metal1 ( 501200 348880 ) Via1_VV
+ NEW Metal2 ( 501200 348880 ) Via2_VH
+ NEW Metal1 ( 511280 348880 ) Via1_VV
+ NEW Metal2 ( 511280 348880 ) Via2_VH
+ NEW Metal2 ( 501200 348880 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 511280 348880 ) RECT ( -280 -660 280 0 ) ;
+ - _0575_ ( _1239_ A3 ) ( _1238_ ZN ) + USE SIGNAL
+ + ROUTED Metal3 ( 487760 350000 ) ( 510160 * )
+ NEW Metal1 ( 487760 350000 ) Via1_VV
+ NEW Metal2 ( 487760 350000 ) Via2_VH
+ NEW Metal1 ( 510160 350000 ) Via1_VV
+ NEW Metal2 ( 510160 350000 ) Via2_VH
+ NEW Metal2 ( 487760 350000 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 510160 350000 ) RECT ( -280 -660 280 0 ) ;
+ - _0576_ ( _1240_ A3 ) ( _1239_ ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 488880 356720 ) ( 490000 * )
+ NEW Metal2 ( 490000 346640 ) ( * 356720 )
+ NEW Metal3 ( 490000 346640 ) ( 510160 * )
+ NEW Metal1 ( 488880 356720 ) Via1_VV
+ NEW Metal2 ( 490000 346640 ) Via2_VH
+ NEW Metal1 ( 510160 346640 ) Via1_VV
+ NEW Metal2 ( 510160 346640 ) Via2_VH
+ NEW Metal2 ( 510160 346640 ) RECT ( -280 -660 280 0 ) ;
+ - _0577_ ( _1241_ A3 ) ( _1240_ ZN ) + USE SIGNAL
+ + ROUTED Metal3 ( 466480 356720 ) ( 482160 * )
+ NEW Metal1 ( 466480 356720 ) Via1_VV
+ NEW Metal2 ( 466480 356720 ) Via2_VH
+ NEW Metal1 ( 482160 356720 ) Via1_VV
+ NEW Metal2 ( 482160 356720 ) Via2_VH
+ NEW Metal2 ( 466480 356720 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 482160 356720 ) RECT ( -280 -660 280 0 ) ;
+ - _0578_ ( ANTENNA__1242__A2 I ) ( ANTENNA__1246__A2 I ) ( ANTENNA__1249__B1 I ) ( ANTENNA__1252__A1 I ) ( ANTENNA__1254__A1 I ) ( ANTENNA__1257__A1 I ) ( _1257_ A1 )
+ ( _1254_ A1 ) ( _1252_ A1 ) ( _1249_ B1 ) ( _1246_ A2 ) ( _1242_ A2 ) ( _1241_ Z ) + USE SIGNAL
+ + ROUTED Metal2 ( 460880 362320 ) ( 462000 * )
+ NEW Metal2 ( 462000 358960 ) ( * 362320 )
+ NEW Metal2 ( 469840 365680 ) ( * 366800 )
+ NEW Metal1 ( 463120 366800 ) ( 469840 * )
+ NEW Metal2 ( 462000 366800 ) ( 463120 * )
+ NEW Metal2 ( 462000 362320 ) ( * 366800 )
+ NEW Metal2 ( 468720 371280 ) ( 469840 * )
+ NEW Metal2 ( 469840 366800 ) ( * 371280 )
+ NEW Metal2 ( 476560 371280 ) ( * 372400 )
+ NEW Metal3 ( 469840 371280 ) ( 476560 * )
+ NEW Metal2 ( 485520 393680 ) ( 486640 * )
+ NEW Metal2 ( 485520 371280 ) ( * 393680 )
+ NEW Metal3 ( 476560 371280 ) ( 485520 * )
+ NEW Metal3 ( 486640 393680 ) ( 494480 * )
+ NEW Metal3 ( 494480 390320 ) ( 505680 * )
+ NEW Metal2 ( 494480 390320 ) ( * 393680 )
+ NEW Metal2 ( 511280 393680 ) ( 512400 * )
+ NEW Metal2 ( 511280 390320 ) ( * 393680 )
+ NEW Metal3 ( 505680 390320 ) ( 511280 * )
+ NEW Metal3 ( 511280 389200 ) ( 514640 * )
+ NEW Metal3 ( 511280 389200 ) ( * 390320 )
+ NEW Metal2 ( 515760 365680 ) ( 516880 * )
+ NEW Metal2 ( 516880 365680 ) ( * 389200 )
+ NEW Metal3 ( 514640 389200 ) ( 516880 * )
+ NEW Metal2 ( 516880 395920 ) ( 519120 * )
+ NEW Metal2 ( 516880 389200 ) ( * 395920 )
+ NEW Metal2 ( 524720 364560 ) ( * 365680 )
+ NEW Metal3 ( 516880 365680 ) ( 524720 * )
+ NEW Metal1 ( 460880 362320 ) Via1_VV
+ NEW Metal1 ( 462000 358960 ) Via1_HV
+ NEW Metal1 ( 469840 365680 ) Via1_VV
+ NEW Metal1 ( 469840 366800 ) Via1_HV
+ NEW Metal1 ( 463120 366800 ) Via1_HV
+ NEW Metal1 ( 468720 371280 ) Via1_VV
+ NEW Metal1 ( 476560 372400 ) Via1_VV
+ NEW Metal2 ( 476560 371280 ) Via2_VH
+ NEW Metal2 ( 469840 371280 ) Via2_VH
+ NEW Metal1 ( 486640 393680 ) Via1_VV
+ NEW Metal2 ( 485520 371280 ) Via2_VH
+ NEW Metal1 ( 494480 393680 ) Via1_VV
+ NEW Metal2 ( 494480 393680 ) Via2_VH
+ NEW Metal2 ( 486640 393680 ) Via2_VH
+ NEW Metal1 ( 505680 390320 ) Via1_VV
+ NEW Metal2 ( 505680 390320 ) Via2_VH
+ NEW Metal2 ( 494480 390320 ) Via2_VH
+ NEW Metal1 ( 512400 393680 ) Via1_VV
+ NEW Metal2 ( 511280 390320 ) Via2_VH
+ NEW Metal1 ( 514640 389200 ) Via1_VV
+ NEW Metal2 ( 514640 389200 ) Via2_VH
+ NEW Metal1 ( 515760 365680 ) Via1_VV
+ NEW Metal2 ( 516880 389200 ) Via2_VH
+ NEW Metal1 ( 519120 395920 ) Via1_VV
+ NEW Metal1 ( 524720 364560 ) Via1_VV
+ NEW Metal2 ( 524720 365680 ) Via2_VH
+ NEW Metal2 ( 516880 365680 ) Via2_VH
+ NEW Metal2 ( 469840 371280 ) RECT ( -280 -1040 280 0 )
+ NEW Metal2 ( 494480 393680 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 486640 393680 ) RECT ( -280 -1040 280 0 )
+ NEW Metal2 ( 505680 390320 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 514640 389200 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 516880 365680 ) RECT ( -280 -1040 280 0 ) ;
+ - _0579_ ( _1243_ B ) ( _1242_ ZN ) + USE SIGNAL
+ + ROUTED Metal3 ( 451920 365680 ) ( 459760 * )
+ NEW Metal2 ( 451920 365680 ) ( * 372400 )
+ NEW Metal1 ( 459760 365680 ) Via1_VV
+ NEW Metal2 ( 459760 365680 ) Via2_VH
+ NEW Metal2 ( 451920 365680 ) Via2_VH
+ NEW Metal1 ( 451920 372400 ) Via1_VV
+ NEW Metal2 ( 459760 365680 ) RECT ( -280 -660 280 0 ) ;
+ - _0580_ ( _1247_ A1 ) ( _1244_ ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 488880 406000 ) ( 495600 * )
+ NEW Metal2 ( 495600 403760 ) ( * 406000 )
+ NEW Metal2 ( 495600 403760 ) ( 497840 * )
+ NEW Metal1 ( 488880 406000 ) Via1_VV
+ NEW Metal1 ( 497840 403760 ) Via1_VV ;
+ - _0581_ ( _1251_ A2 ) ( _1250_ A2 ) ( _1246_ A3 ) ( _1245_ ZN ) + USE SIGNAL
+ + ROUTED Metal3 ( 482160 364560 ) ( 497840 * )
+ NEW Metal2 ( 482160 388080 ) ( 483280 * )
+ NEW Metal2 ( 482160 364560 ) ( * 388080 )
+ NEW Metal2 ( 483280 388080 ) ( * 395920 )
+ NEW Metal1 ( 482160 364560 ) Via1_VV
+ NEW Metal2 ( 482160 364560 ) Via2_VH
+ NEW Metal1 ( 497840 364560 ) Via1_VV
+ NEW Metal2 ( 497840 364560 ) Via2_VH
+ NEW Metal1 ( 483280 388080 ) Via1_VV
+ NEW Metal1 ( 483280 395920 ) Via1_VV
+ NEW Metal2 ( 482160 364560 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 497840 364560 ) RECT ( -280 -660 280 0 ) ;
+ - _0582_ ( _1247_ A2 ) ( _1246_ ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 490000 398160 ) ( * 403760 )
+ NEW Metal2 ( 490000 403760 ) ( 494480 * )
+ NEW Metal1 ( 490000 398160 ) Via1_VV
+ NEW Metal1 ( 494480 403760 ) Via1_VV ;
+ - _0583_ ( _1249_ B2 ) ( _1248_ ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 474320 373520 ) ( * 378000 )
+ NEW Metal2 ( 469840 378000 ) ( 474320 * )
+ NEW Metal1 ( 474320 373520 ) Via1_VV
+ NEW Metal1 ( 469840 378000 ) Via1_VV ;
+ - _0584_ ( _1250_ B ) ( _1249_ ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 477680 374640 ) ( * 385840 )
+ NEW Metal1 ( 477680 374640 ) Via1_VV
+ NEW Metal1 ( 477680 385840 ) Via1_HV ;
+ - _0585_ ( _1256_ A2 ) ( _1253_ A2 ) ( _1252_ A2 ) ( _1251_ ZN ) + USE SIGNAL
+ + ROUTED Metal3 ( 501200 388080 ) ( 510160 * )
+ NEW Metal2 ( 501200 366800 ) ( * 388080 )
+ NEW Metal2 ( 513520 382480 ) ( 514640 * )
+ NEW Metal2 ( 513520 382480 ) ( * 388080 )
+ NEW Metal3 ( 510160 388080 ) ( 513520 * )
+ NEW Metal2 ( 503440 388080 ) ( * 394800 )
+ NEW Metal1 ( 510160 388080 ) Via1_VV
+ NEW Metal2 ( 510160 388080 ) Via2_VH
+ NEW Metal2 ( 501200 388080 ) Via2_VH
+ NEW Metal1 ( 501200 366800 ) Via1_VV
+ NEW Metal1 ( 514640 382480 ) Via1_VV
+ NEW Metal2 ( 513520 388080 ) Via2_VH
+ NEW Metal1 ( 503440 394800 ) Via1_VV
+ NEW Metal2 ( 503440 388080 ) Via2_VH
+ NEW Metal2 ( 510160 388080 ) RECT ( -280 -660 280 0 )
+ NEW Metal3 ( 503440 388080 ) RECT ( -1040 -280 0 280 ) ;
+ - _0586_ ( _1255_ A2 ) ( _1252_ ZN ) + USE SIGNAL
+ + ROUTED Metal3 ( 513520 390320 ) ( 524720 * )
+ NEW Metal2 ( 524720 390320 ) ( * 401520 )
+ NEW Metal1 ( 513520 390320 ) Via1_VV
+ NEW Metal2 ( 513520 390320 ) Via2_VH
+ NEW Metal2 ( 524720 390320 ) Via2_VH
+ NEW Metal1 ( 524720 401520 ) Via1_VV
+ NEW Metal2 ( 513520 390320 ) RECT ( -280 -660 280 0 ) ;
+ - _0587_ ( _1254_ A2 ) ( _1253_ ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 506800 395920 ) ( 515760 * )
+ NEW Metal1 ( 515760 395920 ) Via1_VV
+ NEW Metal1 ( 506800 395920 ) Via1_VV ;
+ - _0588_ ( _1258_ A2 ) ( _1255_ A3 ) ( _1254_ ZN ) + USE SIGNAL
+ + ROUTED Metal3 ( 519120 393680 ) ( 523600 * )
+ NEW Metal2 ( 523600 373520 ) ( * 393680 )
+ NEW Metal2 ( 523600 393680 ) ( * 403760 )
+ NEW Metal1 ( 519120 393680 ) Via1_VV
+ NEW Metal2 ( 519120 393680 ) Via2_VH
+ NEW Metal2 ( 523600 393680 ) Via2_VH
+ NEW Metal1 ( 523600 373520 ) Via1_VV
+ NEW Metal1 ( 523600 403760 ) Via1_VV
+ NEW Metal2 ( 519120 393680 ) RECT ( -280 -660 280 0 ) ;
+ - _0589_ ( _1257_ A2 ) ( _1256_ Z ) + USE SIGNAL
+ + ROUTED Metal2 ( 520240 364560 ) ( 521360 * )
+ NEW Metal2 ( 520240 364560 ) ( * 378000 )
+ NEW Metal2 ( 518000 378000 ) ( 520240 * )
+ NEW Metal1 ( 521360 364560 ) Via1_VV
+ NEW Metal1 ( 518000 378000 ) Via1_HV ;
+ - _0590_ ( _1258_ B ) ( _1257_ ZN ) + USE SIGNAL
+ + ROUTED Metal3 ( 522480 362320 ) ( 528080 * )
+ NEW Metal2 ( 528080 362320 ) ( * 370160 )
+ NEW Metal1 ( 522480 362320 ) Via1_VV
+ NEW Metal2 ( 522480 362320 ) Via2_VH
+ NEW Metal2 ( 528080 362320 ) Via2_VH
+ NEW Metal1 ( 528080 370160 ) Via1_VV
+ NEW Metal2 ( 522480 362320 ) RECT ( -280 -660 280 0 ) ;
+ - _0591_ ( _1282_ A2 ) ( _1268_ A2 ) ( _1267_ A2 ) ( _1259_ ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 379120 390320 ) ( * 394800 )
+ NEW Metal2 ( 379120 390320 ) ( 383600 * )
+ NEW Metal2 ( 383600 380240 ) ( * 390320 )
+ NEW Metal3 ( 348880 394800 ) ( 379120 * )
+ NEW Metal3 ( 337680 394800 ) ( 348880 * )
+ NEW Metal1 ( 379120 394800 ) Via1_VV
+ NEW Metal1 ( 383600 380240 ) Via1_HV
+ NEW Metal1 ( 348880 394800 ) Via1_VV
+ NEW Metal2 ( 348880 394800 ) Via2_VH
+ NEW Metal2 ( 379120 394800 ) Via2_VH
+ NEW Metal1 ( 337680 394800 ) Via1_HV
+ NEW Metal2 ( 337680 394800 ) Via2_VH
+ NEW Metal2 ( 348880 394800 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 379120 394800 ) RECT ( -280 -1040 280 0 )
+ NEW Metal2 ( 337680 394800 ) RECT ( -280 -660 280 0 ) ;
+ - _0592_ ( _1261_ A3 ) ( _1260_ ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 361200 342160 ) ( * 351120 )
+ NEW Metal2 ( 360080 351120 ) ( 361200 * )
+ NEW Metal2 ( 360080 351120 ) ( * 356720 )
+ NEW Metal2 ( 358960 356720 ) ( 360080 * )
+ NEW Metal2 ( 358960 356720 ) ( * 362320 )
+ NEW Metal1 ( 361200 342160 ) Via1_VV
+ NEW Metal1 ( 358960 362320 ) Via1_VV ;
+ - _0593_ ( _1262_ A3 ) ( _1261_ ZN ) + USE SIGNAL
+ + ROUTED Metal3 ( 366800 338800 ) ( 371280 * )
+ NEW Metal2 ( 371280 325360 ) ( * 338800 )
+ NEW Metal1 ( 366800 338800 ) Via1_VV
+ NEW Metal2 ( 366800 338800 ) Via2_VH
+ NEW Metal2 ( 371280 338800 ) Via2_VH
+ NEW Metal1 ( 371280 325360 ) Via1_HV
+ NEW Metal2 ( 366800 338800 ) RECT ( -280 -660 280 0 ) ;
+ - _0594_ ( _1349_ A2 ) ( _1277_ A2 ) ( _1265_ A1 ) ( _1262_ ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 391440 346640 ) ( * 347760 )
+ NEW Metal2 ( 384720 346640 ) ( 391440 * )
+ NEW Metal2 ( 384720 346640 ) ( * 364560 )
+ NEW Metal2 ( 383600 327600 ) ( * 346640 )
+ NEW Metal2 ( 383600 346640 ) ( 384720 * )
+ NEW Metal3 ( 383600 319760 ) ( 394800 * )
+ NEW Metal2 ( 383600 319760 ) ( * 327600 )
+ NEW Metal1 ( 391440 347760 ) Via1_VV
+ NEW Metal1 ( 384720 364560 ) Via1_VV
+ NEW Metal1 ( 383600 327600 ) Via1_VV
+ NEW Metal1 ( 394800 319760 ) Via1_VV
+ NEW Metal2 ( 394800 319760 ) Via2_VH
+ NEW Metal2 ( 383600 319760 ) Via2_VH
+ NEW Metal2 ( 394800 319760 ) RECT ( -280 0 280 660 ) ;
+ - _0595_ ( _1280_ A1 ) ( _1264_ A3 ) ( _1263_ ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 382480 348880 ) ( * 353360 )
+ NEW Metal3 ( 382480 353360 ) ( 388080 * )
+ NEW Metal2 ( 388080 353360 ) ( * 357840 )
+ NEW Metal2 ( 380240 343280 ) ( * 344400 )
+ NEW Metal2 ( 380240 344400 ) ( 382480 * )
+ NEW Metal2 ( 382480 344400 ) ( * 348880 )
+ NEW Metal1 ( 382480 348880 ) Via1_VV
+ NEW Metal2 ( 382480 353360 ) Via2_VH
+ NEW Metal2 ( 388080 353360 ) Via2_VH
+ NEW Metal1 ( 388080 357840 ) Via1_VV
+ NEW Metal1 ( 380240 343280 ) Via1_VV ;
+ - _0596_ ( _1352_ A2 ) ( _1350_ A2 ) ( _1272_ A2 ) ( _1265_ A2 ) ( _1264_ ZN ) + USE SIGNAL
+ + ROUTED Metal3 ( 397040 324240 ) ( 416080 * )
+ NEW Metal2 ( 416080 324240 ) ( * 325360 )
+ NEW Metal2 ( 397040 324240 ) ( * 358960 )
+ NEW Metal3 ( 389200 364560 ) ( 397040 * )
+ NEW Metal2 ( 397040 358960 ) ( * 364560 )
+ NEW Metal2 ( 402640 364560 ) ( * 372400 )
+ NEW Metal3 ( 397040 364560 ) ( 402640 * )
+ NEW Metal1 ( 397040 324240 ) Via1_HV
+ NEW Metal2 ( 397040 324240 ) Via2_VH
+ NEW Metal2 ( 416080 324240 ) Via2_VH
+ NEW Metal1 ( 416080 325360 ) Via1_VV
+ NEW Metal1 ( 397040 358960 ) Via1_VV
+ NEW Metal1 ( 389200 364560 ) Via1_VV
+ NEW Metal2 ( 389200 364560 ) Via2_VH
+ NEW Metal2 ( 397040 364560 ) Via2_VH
+ NEW Metal1 ( 402640 372400 ) Via1_VV
+ NEW Metal2 ( 402640 364560 ) Via2_VH
+ NEW Metal2 ( 397040 324240 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 389200 364560 ) RECT ( -280 -660 280 0 ) ;
+ - _0597_ ( _1269_ A2 ) ( _1267_ B ) ( _1265_ ZN ) + USE SIGNAL
+ + ROUTED Metal3 ( 373520 366800 ) ( 382480 * )
+ NEW Metal2 ( 373520 366800 ) ( * 388080 )
+ NEW Metal2 ( 408240 366800 ) ( * 379120 )
+ NEW Metal3 ( 382480 366800 ) ( 408240 * )
+ NEW Metal1 ( 382480 366800 ) Via1_HV
+ NEW Metal2 ( 382480 366800 ) Via2_VH
+ NEW Metal2 ( 373520 366800 ) Via2_VH
+ NEW Metal1 ( 373520 388080 ) Via1_VV
+ NEW Metal1 ( 408240 379120 ) Via1_HV
+ NEW Metal2 ( 408240 366800 ) Via2_VH
+ NEW Metal2 ( 382480 366800 ) RECT ( -280 -660 280 0 ) ;
+ - _0598_ ( ANTENNA__1267__C I ) ( ANTENNA__1270__B2 I ) ( ANTENNA__1272__A1 I ) ( ANTENNA__1277__A1 I ) ( _1277_ A1 ) ( _1272_ A1 ) ( _1270_ B2 )
+ ( _1267_ C ) ( _1266_ ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 393680 395920 ) ( * 404880 )
+ NEW Metal2 ( 390320 404880 ) ( 393680 * )
+ NEW Metal2 ( 390320 404880 ) ( * 429520 )
+ NEW Metal2 ( 390320 429520 ) ( 391440 * )
+ NEW Metal3 ( 393680 380240 ) ( 404880 * )
+ NEW Metal2 ( 393680 380240 ) ( * 395920 )
+ NEW Metal2 ( 400400 374640 ) ( 401520 * )
+ NEW Metal2 ( 400400 374640 ) ( * 380240 )
+ NEW Metal2 ( 414960 380240 ) ( * 386960 )
+ NEW Metal3 ( 404880 380240 ) ( 414960 * )
+ NEW Metal3 ( 414960 380240 ) ( 421680 * )
+ NEW Metal2 ( 409360 365680 ) ( * 380240 )
+ NEW Metal3 ( 394800 348880 ) ( 409360 * )
+ NEW Metal2 ( 409360 348880 ) ( * 365680 )
+ NEW Metal2 ( 407120 343280 ) ( * 348880 )
+ NEW Metal2 ( 391440 429520 ) ( * 444080 )
+ NEW Metal1 ( 391440 444080 ) Via1_HV
+ NEW Metal1 ( 393680 395920 ) Via1_HV
+ NEW Metal1 ( 404880 380240 ) Via1_HV
+ NEW Metal2 ( 404880 380240 ) Via2_VH
+ NEW Metal2 ( 393680 380240 ) Via2_VH
+ NEW Metal1 ( 401520 374640 ) Via1_VV
+ NEW Metal2 ( 400400 380240 ) Via2_VH
+ NEW Metal1 ( 414960 386960 ) Via1_VV
+ NEW Metal2 ( 414960 380240 ) Via2_VH
+ NEW Metal1 ( 421680 380240 ) Via1_VV
+ NEW Metal2 ( 421680 380240 ) Via2_VH
+ NEW Metal1 ( 409360 365680 ) Via1_VV
+ NEW Metal2 ( 409360 380240 ) Via2_VH
+ NEW Metal1 ( 394800 348880 ) Via1_VV
+ NEW Metal2 ( 394800 348880 ) Via2_VH
+ NEW Metal2 ( 409360 348880 ) Via2_VH
+ NEW Metal1 ( 407120 343280 ) Via1_VV
+ NEW Metal2 ( 407120 348880 ) Via2_VH
+ NEW Metal2 ( 404880 380240 ) RECT ( -280 -660 280 0 )
+ NEW Metal3 ( 400400 380240 ) RECT ( -1040 -280 0 280 )
+ NEW Metal2 ( 421680 380240 ) RECT ( -280 -660 280 0 )
+ NEW Metal3 ( 409360 380240 ) RECT ( -1040 -280 0 280 )
+ NEW Metal2 ( 394800 348880 ) RECT ( -280 -660 280 0 )
+ NEW Metal3 ( 407120 348880 ) RECT ( -1040 -280 0 280 ) ;
+ - _0599_ ( ANTENNA__1270__A2 I ) ( ANTENNA__1271__A2 I ) ( ANTENNA__1273__A3 I ) ( ANTENNA__1278__A4 I ) ( ANTENNA__1281__B2 I ) ( _1281_ B2 ) ( _1278_ A4 )
+ ( _1273_ A3 ) ( _1271_ A2 ) ( _1270_ A2 ) ( _1267_ ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 416080 382480 ) ( * 402640 )
+ NEW Metal2 ( 414960 402640 ) ( 416080 * )
+ NEW Metal2 ( 414960 374640 ) ( 416080 * )
+ NEW Metal2 ( 416080 374640 ) ( * 382480 )
+ NEW Metal2 ( 386960 385840 ) ( * 395920 )
+ NEW Metal3 ( 386960 385840 ) ( 416080 * )
+ NEW Metal2 ( 385840 372400 ) ( 386960 * )
+ NEW Metal2 ( 386960 372400 ) ( * 385840 )
+ NEW Metal3 ( 367920 374640 ) ( 386960 * )
+ NEW Metal2 ( 362320 386960 ) ( 363440 * )
+ NEW Metal2 ( 363440 374640 ) ( * 386960 )
+ NEW Metal3 ( 363440 374640 ) ( 367920 * )
+ NEW Metal2 ( 353360 385840 ) ( * 388080 )
+ NEW Metal3 ( 353360 385840 ) ( 363440 * )
+ NEW Metal2 ( 367920 358960 ) ( * 374640 )
+ NEW Metal3 ( 363440 357840 ) ( 367920 * )
+ NEW Metal2 ( 367920 357840 ) ( * 358960 )
+ NEW Metal3 ( 355600 347760 ) ( 363440 * )
+ NEW Metal2 ( 363440 347760 ) ( * 357840 )
+ NEW Metal1 ( 416080 382480 ) Via1_HV
+ NEW Metal1 ( 414960 402640 ) Via1_VV
+ NEW Metal1 ( 414960 374640 ) Via1_VV
+ NEW Metal1 ( 386960 395920 ) Via1_VV
+ NEW Metal2 ( 386960 385840 ) Via2_VH
+ NEW Metal2 ( 416080 385840 ) Via2_VH
+ NEW Metal1 ( 385840 372400 ) Via1_VV
+ NEW Metal1 ( 367920 374640 ) Via1_VV
+ NEW Metal2 ( 367920 374640 ) Via2_VH
+ NEW Metal2 ( 386960 374640 ) Via2_VH
+ NEW Metal1 ( 362320 386960 ) Via1_VV
+ NEW Metal2 ( 363440 374640 ) Via2_VH
+ NEW Metal1 ( 353360 388080 ) Via1_VV
+ NEW Metal2 ( 353360 385840 ) Via2_VH
+ NEW Metal2 ( 363440 385840 ) Via2_VH
+ NEW Metal1 ( 367920 358960 ) Via1_VV
+ NEW Metal1 ( 363440 357840 ) Via1_VV
+ NEW Metal2 ( 363440 357840 ) Via2_VH
+ NEW Metal2 ( 367920 357840 ) Via2_VH
+ NEW Metal1 ( 355600 347760 ) Via1_VV
+ NEW Metal2 ( 355600 347760 ) Via2_VH
+ NEW Metal2 ( 363440 347760 ) Via2_VH
+ NEW Metal2 ( 416080 385840 ) RECT ( -280 -1040 280 0 )
+ NEW Metal2 ( 367920 374640 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 386960 374640 ) RECT ( -280 -1040 280 0 )
+ NEW Metal2 ( 363440 385840 ) RECT ( -280 -1040 280 0 )
+ NEW Metal2 ( 363440 357840 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 355600 347760 ) RECT ( -280 -660 280 0 ) ;
+ - _0600_ ( _1269_ A1 ) ( _1268_ ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 371280 388080 ) ( * 393680 )
+ NEW Metal3 ( 371280 393680 ) ( 378000 * )
+ NEW Metal1 ( 371280 388080 ) Via1_VV
+ NEW Metal2 ( 371280 393680 ) Via2_VH
+ NEW Metal1 ( 378000 393680 ) Via1_VV
+ NEW Metal2 ( 378000 393680 ) Via2_VH
+ NEW Metal2 ( 378000 393680 ) RECT ( -280 -660 280 0 ) ;
+ - _0601_ ( _1270_ B1 ) ( _1269_ ZN ) + USE SIGNAL
+ + ROUTED Metal3 ( 372400 390320 ) ( 391440 * )
+ NEW Metal2 ( 391440 390320 ) ( * 394800 )
+ NEW Metal1 ( 372400 390320 ) Via1_VV
+ NEW Metal2 ( 372400 390320 ) Via2_VH
+ NEW Metal2 ( 391440 390320 ) Via2_VH
+ NEW Metal1 ( 391440 394800 ) Via1_HV
+ NEW Metal2 ( 372400 390320 ) RECT ( -280 -660 280 0 ) ;
+ - _0602_ ( _1275_ A2 ) ( _1271_ ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 350000 372400 ) ( * 388080 )
+ NEW Metal1 ( 350000 372400 ) Via1_VV
+ NEW Metal1 ( 350000 388080 ) Via1_VV ;
+ - _0603_ ( _1280_ B ) ( _1274_ A2 ) ( _1272_ ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 392560 369040 ) ( * 372400 )
+ NEW Metal3 ( 385840 369040 ) ( 392560 * )
+ NEW Metal2 ( 385840 348880 ) ( * 369040 )
+ NEW Metal2 ( 401520 369040 ) ( * 370160 )
+ NEW Metal3 ( 392560 369040 ) ( 401520 * )
+ NEW Metal1 ( 392560 372400 ) Via1_HV
+ NEW Metal2 ( 392560 369040 ) Via2_VH
+ NEW Metal2 ( 385840 369040 ) Via2_VH
+ NEW Metal1 ( 385840 348880 ) Via1_HV
+ NEW Metal1 ( 401520 370160 ) Via1_VV
+ NEW Metal2 ( 401520 369040 ) Via2_VH ;
+ - _0604_ ( _1276_ A2 ) ( _1274_ A3 ) ( _1273_ ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 395920 364560 ) ( * 372400 )
+ NEW Metal3 ( 383600 370160 ) ( 395920 * )
+ NEW Metal1 ( 395920 372400 ) Via1_VV
+ NEW Metal1 ( 395920 364560 ) Via1_VV
+ NEW Metal1 ( 383600 370160 ) Via1_VV
+ NEW Metal2 ( 383600 370160 ) Via2_VH
+ NEW Metal2 ( 395920 370160 ) Via2_VH
+ NEW Metal2 ( 383600 370160 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 395920 370160 ) RECT ( -280 -1040 280 0 ) ;
+ - _0605_ ( _1275_ B ) ( _1274_ ZN ) + USE SIGNAL
+ + ROUTED Metal3 ( 356720 372400 ) ( 389200 * )
+ NEW Metal1 ( 356720 372400 ) Via1_VV
+ NEW Metal2 ( 356720 372400 ) Via2_VH
+ NEW Metal1 ( 389200 372400 ) Via1_VV
+ NEW Metal2 ( 389200 372400 ) Via2_VH
+ NEW Metal2 ( 356720 372400 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 389200 372400 ) RECT ( -280 -660 280 0 ) ;
+ - _0606_ ( _1277_ B ) ( _1276_ Z ) + USE SIGNAL
+ + ROUTED Metal2 ( 394800 351120 ) ( 395920 * )
+ NEW Metal2 ( 394800 351120 ) ( * 363440 )
+ NEW Metal1 ( 395920 351120 ) Via1_VV
+ NEW Metal1 ( 394800 363440 ) Via1_VV ;
+ - _0607_ ( _1281_ A2 ) ( _1278_ ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 356720 351120 ) ( * 355600 )
+ NEW Metal1 ( 356720 351120 ) Via1_VV
+ NEW Metal1 ( 356720 355600 ) Via1_VV ;
+ - _0608_ ( _1280_ A2 ) ( _1279_ ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 380240 348880 ) ( * 356720 )
+ NEW Metal2 ( 378000 356720 ) ( 380240 * )
+ NEW Metal1 ( 380240 348880 ) Via1_VV
+ NEW Metal1 ( 378000 356720 ) Via1_VV ;
+ - _0609_ ( _1281_ B1 ) ( _1280_ ZN ) + USE SIGNAL
+ + ROUTED Metal3 ( 362320 350000 ) ( 381360 * )
+ NEW Metal2 ( 362320 350000 ) ( * 356720 )
+ NEW Metal2 ( 361200 356720 ) ( 362320 * )
+ NEW Metal1 ( 381360 350000 ) Via1_VV
+ NEW Metal2 ( 381360 350000 ) Via2_VH
+ NEW Metal2 ( 362320 350000 ) Via2_VH
+ NEW Metal1 ( 361200 356720 ) Via1_HV
+ NEW Metal2 ( 381360 350000 ) RECT ( -280 -660 280 0 ) ;
+ - _0610_ ( _1293_ A1 ) ( _1289_ B ) ( _1286_ A1 ) ( _1282_ ZN ) + USE SIGNAL
+ + ROUTED Metal3 ( 320880 393680 ) ( 347760 * )
+ NEW Metal2 ( 320880 390320 ) ( * 393680 )
+ NEW Metal2 ( 333200 393680 ) ( * 410480 )
+ NEW Metal2 ( 358960 393680 ) ( * 409360 )
+ NEW Metal3 ( 347760 393680 ) ( 358960 * )
+ NEW Metal1 ( 347760 393680 ) Via1_VV
+ NEW Metal2 ( 347760 393680 ) Via2_VH
+ NEW Metal2 ( 320880 393680 ) Via2_VH
+ NEW Metal1 ( 320880 390320 ) Via1_VV
+ NEW Metal1 ( 333200 410480 ) Via1_VV
+ NEW Metal2 ( 333200 393680 ) Via2_VH
+ NEW Metal1 ( 358960 409360 ) Via1_VV
+ NEW Metal2 ( 358960 393680 ) Via2_VH
+ NEW Metal2 ( 347760 393680 ) RECT ( -280 -660 280 0 )
+ NEW Metal3 ( 333200 393680 ) RECT ( -1040 -280 0 280 ) ;
+ - _0611_ ( _1284_ A3 ) ( _1283_ ZN ) + USE SIGNAL
+ + ROUTED Metal3 ( 273840 404880 ) ( 283920 * )
+ NEW Metal1 ( 273840 404880 ) Via1_VV
+ NEW Metal2 ( 273840 404880 ) Via2_VH
+ NEW Metal1 ( 283920 404880 ) Via1_VV
+ NEW Metal2 ( 283920 404880 ) Via2_VH
+ NEW Metal2 ( 273840 404880 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 283920 404880 ) RECT ( -280 -660 280 0 ) ;
+ - _0612_ ( ANTENNA__1285__A2 I ) ( ANTENNA__1287__A3 I ) ( ANTENNA__1288__A2 I ) ( ANTENNA__1297__A2 I ) ( ANTENNA__1299__A1 I ) ( ANTENNA__1302__A1 I ) ( _1302_ A1 )
+ ( _1299_ A1 ) ( _1297_ A2 ) ( _1288_ A2 ) ( _1287_ A3 ) ( _1285_ A2 ) ( _1284_ ZN ) + USE SIGNAL
+ + ROUTED Metal3 ( 298480 440720 ) ( 308560 * )
+ NEW Metal3 ( 288400 440720 ) ( 298480 * )
+ NEW Metal2 ( 280560 440720 ) ( * 442960 )
+ NEW Metal3 ( 280560 440720 ) ( 288400 * )
+ NEW Metal2 ( 279440 440720 ) ( 280560 * )
+ NEW Metal3 ( 272720 437360 ) ( 279440 * )
+ NEW Metal2 ( 308560 436800 ) ( * 440720 )
+ NEW Metal3 ( 301840 418320 ) ( 315280 * )
+ NEW Metal2 ( 301840 406000 ) ( * 418320 )
+ NEW Metal2 ( 308560 436800 ) ( 313040 * )
+ NEW Metal2 ( 313040 418320 ) ( * 436800 )
+ NEW Metal2 ( 279440 435120 ) ( * 440720 )
+ NEW Metal3 ( 315280 418320 ) ( 319200 * )
+ NEW Metal2 ( 337680 406000 ) ( * 412720 )
+ NEW Metal3 ( 337680 412720 ) ( 343280 * )
+ NEW Metal2 ( 332080 412720 ) ( * 425040 )
+ NEW Metal3 ( 332080 412720 ) ( 337680 * )
+ NEW Metal2 ( 324240 426160 ) ( 325360 * )
+ NEW Metal2 ( 324240 419440 ) ( * 426160 )
+ NEW Metal3 ( 324240 419440 ) ( 332080 * )
+ NEW Metal2 ( 320880 419440 ) ( * 420560 )
+ NEW Metal3 ( 320880 419440 ) ( 324240 * )
+ NEW Metal3 ( 319200 418320 ) ( * 419440 )
+ NEW Metal3 ( 319200 419440 ) ( 320880 * )
+ NEW Metal1 ( 308560 440720 ) Via1_VV
+ NEW Metal1 ( 298480 440720 ) Via1_VV
+ NEW Metal2 ( 298480 440720 ) Via2_VH
+ NEW Metal2 ( 308560 440720 ) Via2_VH
+ NEW Metal1 ( 288400 440720 ) Via1_VV
+ NEW Metal2 ( 288400 440720 ) Via2_VH
+ NEW Metal1 ( 280560 442960 ) Via1_VV
+ NEW Metal2 ( 280560 440720 ) Via2_VH
+ NEW Metal1 ( 272720 437360 ) Via1_VV
+ NEW Metal2 ( 272720 437360 ) Via2_VH
+ NEW Metal2 ( 279440 437360 ) Via2_VH
+ NEW Metal1 ( 315280 418320 ) Via1_VV
+ NEW Metal2 ( 315280 418320 ) Via2_VH
+ NEW Metal2 ( 301840 418320 ) Via2_VH
+ NEW Metal1 ( 301840 406000 ) Via1_VV
+ NEW Metal2 ( 313040 418320 ) Via2_VH
+ NEW Metal1 ( 279440 435120 ) Via1_VV
+ NEW Metal1 ( 337680 406000 ) Via1_VV
+ NEW Metal2 ( 337680 412720 ) Via2_VH
+ NEW Metal1 ( 343280 412720 ) Via1_HV
+ NEW Metal2 ( 343280 412720 ) Via2_VH
+ NEW Metal1 ( 332080 425040 ) Via1_VV
+ NEW Metal2 ( 332080 412720 ) Via2_VH
+ NEW Metal1 ( 325360 426160 ) Via1_VV
+ NEW Metal2 ( 324240 419440 ) Via2_VH
+ NEW Metal2 ( 332080 419440 ) Via2_VH
+ NEW Metal1 ( 320880 420560 ) Via1_VV
+ NEW Metal2 ( 320880 419440 ) Via2_VH
+ NEW Metal2 ( 298480 440720 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 308560 440720 ) RECT ( -280 -1040 280 0 )
+ NEW Metal2 ( 288400 440720 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 272720 437360 ) RECT ( -280 0 280 660 )
+ NEW Metal2 ( 279440 437360 ) RECT ( -280 0 280 1040 )
+ NEW Metal2 ( 315280 418320 ) RECT ( -280 -660 280 0 )
+ NEW Metal3 ( 313040 418320 ) RECT ( -1040 -280 0 280 )
+ NEW Metal2 ( 343280 412720 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 332080 419440 ) RECT ( -280 -1040 280 0 ) ;
+ - _0613_ ( _1286_ A2 ) ( _1285_ ZN ) + USE SIGNAL
+ + ROUTED Metal3 ( 351120 410480 ) ( 356720 * )
+ NEW Metal1 ( 356720 410480 ) Via1_VV
+ NEW Metal2 ( 356720 410480 ) Via2_VH
+ NEW Metal1 ( 351120 410480 ) Via1_VV
+ NEW Metal2 ( 351120 410480 ) Via2_VH
+ NEW Metal2 ( 356720 410480 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 351120 410480 ) RECT ( -280 -660 280 0 ) ;
+ - _0614_ ( _1292_ A2 ) ( _1290_ A1 ) ( _1287_ ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 317520 402640 ) ( * 412720 )
+ NEW Metal2 ( 322000 412720 ) ( * 417200 )
+ NEW Metal3 ( 317520 412720 ) ( 322000 * )
+ NEW Metal1 ( 317520 402640 ) Via1_HV
+ NEW Metal2 ( 317520 412720 ) Via2_VH
+ NEW Metal1 ( 322000 412720 ) Via1_VV
+ NEW Metal1 ( 322000 417200 ) Via1_VV
+ NEW Metal2 ( 322000 412720 ) Via2_VH
+ NEW Metal2 ( 322000 412720 ) RECT ( -280 -1040 280 0 ) ;
+ - _0615_ ( _1289_ A2 ) ( _1288_ ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 327600 411600 ) ( 328720 * )
+ NEW Metal2 ( 328720 411600 ) ( * 425040 )
+ NEW Metal1 ( 327600 411600 ) Via1_VV
+ NEW Metal1 ( 328720 425040 ) Via1_VV ;
+ - _0616_ ( _1290_ A2 ) ( _1289_ ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 326480 409360 ) ( 328720 * )
+ NEW Metal2 ( 326480 409360 ) ( * 411600 )
+ NEW Metal3 ( 319760 411600 ) ( 326480 * )
+ NEW Metal1 ( 328720 409360 ) Via1_VV
+ NEW Metal2 ( 326480 411600 ) Via2_VH
+ NEW Metal1 ( 319760 411600 ) Via1_VV
+ NEW Metal2 ( 319760 411600 ) Via2_VH
+ NEW Metal2 ( 319760 411600 ) RECT ( -280 -660 280 0 ) ;
+ - _0617_ ( _1291_ I ) ( _1290_ Z ) + USE SIGNAL
+ + ROUTED Metal2 ( 316400 413840 ) ( * 426160 )
+ NEW Metal2 ( 315280 426160 ) ( 316400 * )
+ NEW Metal1 ( 316400 413840 ) Via1_HV
+ NEW Metal1 ( 315280 426160 ) Via1_VV ;
+ - _0618_ ( _1293_ A2 ) ( _1292_ Z ) + USE SIGNAL
+ + ROUTED Metal2 ( 318640 389200 ) ( * 403760 )
+ NEW Metal2 ( 318640 403760 ) ( 322000 * )
+ NEW Metal1 ( 318640 389200 ) Via1_VV
+ NEW Metal1 ( 322000 403760 ) Via1_VV ;
+ - _0619_ ( _1310_ A2 ) ( _1296_ A2 ) ( _1294_ ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 242480 427280 ) ( * 434000 )
+ NEW Metal2 ( 242480 427280 ) ( 246960 * )
+ NEW Metal1 ( 242480 427280 ) Via1_VV
+ NEW Metal1 ( 242480 434000 ) Via1_HV
+ NEW Metal1 ( 246960 427280 ) Via1_VV ;
+ - _0620_ ( ANTENNA__1296__B I ) ( ANTENNA__1299__A2 I ) ( ANTENNA__1302__A2 I ) ( _1302_ A2 ) ( _1299_ A2 ) ( _1296_ B ) ( _1295_ ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 297360 442960 ) ( * 444080 )
+ NEW Metal3 ( 297360 444080 ) ( 304080 * )
+ NEW Metal3 ( 278320 444080 ) ( 297360 * )
+ NEW Metal2 ( 276080 444080 ) ( * 449680 )
+ NEW Metal2 ( 276080 444080 ) ( 278320 * )
+ NEW Metal3 ( 255920 436240 ) ( 278320 * )
+ NEW Metal2 ( 250320 435120 ) ( * 436240 )
+ NEW Metal3 ( 250320 436240 ) ( 255920 * )
+ NEW Metal2 ( 278320 436240 ) ( * 444080 )
+ NEW Metal2 ( 426160 444080 ) ( * 451920 )
+ NEW Metal2 ( 426160 451920 ) ( 427280 * )
+ NEW Metal2 ( 427280 451920 ) ( * 454160 )
+ NEW Metal2 ( 426160 454160 ) ( 427280 * )
+ NEW Metal2 ( 426160 454160 ) ( * 468720 )
+ NEW Metal3 ( 304080 444080 ) ( 426160 * )
+ NEW Metal1 ( 304080 444080 ) Via1_VV
+ NEW Metal2 ( 304080 444080 ) Via2_VH
+ NEW Metal1 ( 297360 442960 ) Via1_VV
+ NEW Metal2 ( 297360 444080 ) Via2_VH
+ NEW Metal1 ( 278320 444080 ) Via1_VV
+ NEW Metal2 ( 278320 444080 ) Via2_VH
+ NEW Metal1 ( 276080 449680 ) Via1_VV
+ NEW Metal1 ( 255920 436240 ) Via1_VV
+ NEW Metal2 ( 255920 436240 ) Via2_VH
+ NEW Metal2 ( 278320 436240 ) Via2_VH
+ NEW Metal1 ( 250320 435120 ) Via1_HV
+ NEW Metal2 ( 250320 436240 ) Via2_VH
+ NEW Metal2 ( 426160 444080 ) Via2_VH
+ NEW Metal1 ( 426160 468720 ) Via1_HV
+ NEW Metal2 ( 304080 444080 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 278320 444080 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 255920 436240 ) RECT ( -280 -660 280 0 ) ;
+ - _0621_ ( ANTENNA__1297__A3 I ) ( ANTENNA__1298__A2 I ) ( ANTENNA__1340__A2 I ) ( ANTENNA__1341__A2 I ) ( ANTENNA__1343__A2 I ) ( ANTENNA__1344__A3 I ) ( _1344_ A3 )
+ ( _1343_ A2 ) ( _1341_ A2 ) ( _1340_ A2 ) ( _1298_ A2 ) ( _1297_ A3 ) ( _1296_ ZN ) + USE SIGNAL
+ + ROUTED Metal3 ( 278320 434000 ) ( 290640 * )
+ NEW Metal3 ( 268240 434000 ) ( 278320 * )
+ NEW Metal3 ( 263760 434000 ) ( 268240 * )
+ NEW Metal3 ( 248080 434000 ) ( 263760 * )
+ NEW Metal2 ( 242480 357840 ) ( 243600 * )
+ NEW Metal2 ( 242480 357840 ) ( * 421680 )
+ NEW Metal3 ( 242480 421680 ) ( 248080 * )
+ NEW Metal2 ( 248080 421680 ) ( * 434000 )
+ NEW Metal2 ( 254800 355600 ) ( 255920 * )
+ NEW Metal2 ( 254800 352240 ) ( * 355600 )
+ NEW Metal3 ( 243600 352240 ) ( 254800 * )
+ NEW Metal2 ( 243600 352240 ) ( * 357840 )
+ NEW Metal2 ( 254800 350000 ) ( * 352240 )
+ NEW Metal2 ( 250320 350000 ) ( * 352240 )
+ NEW Metal2 ( 268240 353360 ) ( * 355600 )
+ NEW Metal3 ( 268240 352240 ) ( * 353360 )
+ NEW Metal3 ( 254800 352240 ) ( 268240 * )
+ NEW Metal2 ( 260400 348880 ) ( * 352240 )
+ NEW Metal2 ( 270480 348880 ) ( * 352240 )
+ NEW Metal3 ( 268240 352240 ) ( 270480 * )
+ NEW Metal3 ( 238000 342160 ) ( 243600 * )
+ NEW Metal2 ( 243600 342160 ) ( * 352240 )
+ NEW Metal1 ( 278320 434000 ) Via1_VV
+ NEW Metal2 ( 278320 434000 ) Via2_VH
+ NEW Metal1 ( 290640 434000 ) Via1_VV
+ NEW Metal2 ( 290640 434000 ) Via2_VH
+ NEW Metal1 ( 268240 434000 ) Via1_VV
+ NEW Metal2 ( 268240 434000 ) Via2_VH
+ NEW Metal1 ( 263760 434000 ) Via1_VV
+ NEW Metal2 ( 263760 434000 ) Via2_VH
+ NEW Metal1 ( 248080 434000 ) Via1_HV
+ NEW Metal2 ( 248080 434000 ) Via2_VH
+ NEW Metal1 ( 243600 357840 ) Via1_VV
+ NEW Metal2 ( 242480 421680 ) Via2_VH
+ NEW Metal2 ( 248080 421680 ) Via2_VH
+ NEW Metal1 ( 255920 355600 ) Via1_VV
+ NEW Metal2 ( 254800 352240 ) Via2_VH
+ NEW Metal2 ( 243600 352240 ) Via2_VH
+ NEW Metal1 ( 254800 350000 ) Via1_VV
+ NEW Metal1 ( 250320 350000 ) Via1_VV
+ NEW Metal2 ( 250320 352240 ) Via2_VH
+ NEW Metal1 ( 268240 355600 ) Via1_VV
+ NEW Metal2 ( 268240 353360 ) Via2_VH
+ NEW Metal1 ( 260400 348880 ) Via1_VV
+ NEW Metal2 ( 260400 352240 ) Via2_VH
+ NEW Metal1 ( 270480 348880 ) Via1_VV
+ NEW Metal2 ( 270480 352240 ) Via2_VH
+ NEW Metal1 ( 238000 342160 ) Via1_VV
+ NEW Metal2 ( 238000 342160 ) Via2_VH
+ NEW Metal2 ( 243600 342160 ) Via2_VH
+ NEW Metal2 ( 278320 434000 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 290640 434000 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 268240 434000 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 263760 434000 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 248080 434000 ) RECT ( -280 -660 280 0 )
+ NEW Metal3 ( 250320 352240 ) RECT ( -1040 -280 0 280 )
+ NEW Metal3 ( 260400 352240 ) RECT ( -1040 -280 0 280 )
+ NEW Metal2 ( 238000 342160 ) RECT ( -280 -660 280 0 ) ;
+ - _0622_ ( _1300_ A2 ) ( _1297_ ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 281680 429520 ) ( 282800 * )
+ NEW Metal2 ( 282800 429520 ) ( * 432880 )
+ NEW Metal1 ( 281680 429520 ) Via1_VV
+ NEW Metal1 ( 282800 432880 ) Via1_VV ;
+ - _0623_ ( _1306_ A3 ) ( _1305_ A2 ) ( _1304_ A2 ) ( _1303_ B ) ( _1300_ A3 ) ( _1298_ Z ) + USE SIGNAL
+ + ROUTED Metal2 ( 283920 450800 ) ( * 457520 )
+ NEW Metal2 ( 281680 450800 ) ( 283920 * )
+ NEW Metal3 ( 281680 437360 ) ( 294000 * )
+ NEW Metal3 ( 283920 450800 ) ( 298480 * )
+ NEW Metal2 ( 298480 450800 ) ( * 457520 )
+ NEW Metal2 ( 281680 436800 ) ( * 450800 )
+ NEW Metal2 ( 279440 429520 ) ( 280560 * )
+ NEW Metal2 ( 280560 429520 ) ( * 436800 )
+ NEW Metal2 ( 280560 436800 ) ( 281680 * )
+ NEW Metal1 ( 281680 450800 ) Via1_VV
+ NEW Metal1 ( 283920 457520 ) Via1_VV
+ NEW Metal1 ( 294000 437360 ) Via1_HV
+ NEW Metal2 ( 294000 437360 ) Via2_VH
+ NEW Metal2 ( 281680 437360 ) Via2_VH
+ NEW Metal1 ( 298480 450800 ) Via1_VV
+ NEW Metal2 ( 298480 450800 ) Via2_VH
+ NEW Metal2 ( 283920 450800 ) Via2_VH
+ NEW Metal1 ( 298480 457520 ) Via1_VV
+ NEW Metal1 ( 279440 429520 ) Via1_VV
+ NEW Metal2 ( 294000 437360 ) RECT ( -280 0 280 660 )
+ NEW Metal2 ( 281680 437360 ) RECT ( -280 0 280 1040 )
+ NEW Metal2 ( 298480 450800 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 283920 450800 ) RECT ( -280 -1040 280 0 ) ;
+ - _0624_ ( _1309_ A2 ) ( _1300_ A4 ) ( _1299_ Z ) + USE SIGNAL
+ + ROUTED Metal2 ( 274960 445200 ) ( * 448560 )
+ NEW Metal3 ( 266000 448560 ) ( 274960 * )
+ NEW Metal2 ( 274960 436800 ) ( * 445200 )
+ NEW Metal2 ( 277200 427280 ) ( * 436800 )
+ NEW Metal2 ( 274960 436800 ) ( 277200 * )
+ NEW Metal1 ( 274960 445200 ) Via1_HV
+ NEW Metal2 ( 274960 448560 ) Via2_VH
+ NEW Metal1 ( 266000 448560 ) Via1_VV
+ NEW Metal2 ( 266000 448560 ) Via2_VH
+ NEW Metal1 ( 277200 427280 ) Via1_HV
+ NEW Metal2 ( 266000 448560 ) RECT ( -280 -660 280 0 ) ;
+ - _0625_ ( _1301_ I ) ( _1300_ ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 271600 425040 ) ( * 426160 )
+ NEW Metal2 ( 271600 425040 ) ( 278320 * )
+ NEW Metal1 ( 271600 426160 ) Via1_VV
+ NEW Metal1 ( 278320 425040 ) Via1_VV ;
+ - _0626_ ( _1303_ A2 ) ( _1302_ ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 300720 442960 ) ( 301840 * )
+ NEW Metal2 ( 301840 442960 ) ( * 450800 )
+ NEW Metal2 ( 301840 450800 ) ( 304080 * )
+ NEW Metal1 ( 300720 442960 ) Via1_VV
+ NEW Metal1 ( 304080 450800 ) Via1_VV ;
+ - _0627_ ( _1304_ B ) ( _1303_ ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 301840 453040 ) ( * 458640 )
+ NEW Metal2 ( 301840 458640 ) ( 302960 * )
+ NEW Metal1 ( 301840 453040 ) Via1_VV
+ NEW Metal1 ( 302960 458640 ) Via1_VV ;
+ - _0628_ ( _1307_ A2 ) ( _1305_ ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 282800 453040 ) ( * 458640 )
+ NEW Metal2 ( 279440 458640 ) ( 282800 * )
+ NEW Metal2 ( 279440 458640 ) ( * 464240 )
+ NEW Metal1 ( 282800 453040 ) Via1_VV
+ NEW Metal1 ( 279440 464240 ) Via1_VV ;
+ - _0629_ ( _1308_ A2 ) ( _1307_ A3 ) ( _1306_ Z ) + USE SIGNAL
+ + ROUTED Metal2 ( 278320 456400 ) ( 279440 * )
+ NEW Metal2 ( 278320 456400 ) ( * 466480 )
+ NEW Metal2 ( 278320 466480 ) ( 280560 * )
+ NEW Metal3 ( 269360 459760 ) ( 278320 * )
+ NEW Metal1 ( 279440 456400 ) Via1_HV
+ NEW Metal1 ( 280560 466480 ) Via1_VV
+ NEW Metal1 ( 269360 459760 ) Via1_HV
+ NEW Metal2 ( 269360 459760 ) Via2_VH
+ NEW Metal2 ( 278320 459760 ) Via2_VH
+ NEW Metal2 ( 269360 459760 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 278320 459760 ) RECT ( -280 -1040 280 0 ) ;
+ - _0630_ ( _1309_ A3 ) ( _1308_ ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 263760 450800 ) ( * 459760 )
+ NEW Metal1 ( 263760 450800 ) Via1_HV
+ NEW Metal1 ( 263760 459760 ) Via1_VV ;
+ - _0631_ ( _1322_ A1 ) ( _1318_ A1 ) ( _1315_ A1 ) ( _1310_ ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 241360 427280 ) ( * 436240 )
+ NEW Metal3 ( 229040 436240 ) ( 241360 * )
+ NEW Metal3 ( 188720 436240 ) ( 196560 * )
+ NEW Metal3 ( 196560 436240 ) ( 229040 * )
+ NEW Metal1 ( 229040 436240 ) Via1_VV
+ NEW Metal2 ( 229040 436240 ) Via2_VH
+ NEW Metal1 ( 241360 427280 ) Via1_VV
+ NEW Metal2 ( 241360 436240 ) Via2_VH
+ NEW Metal1 ( 196560 436240 ) Via1_VV
+ NEW Metal2 ( 196560 436240 ) Via2_VH
+ NEW Metal1 ( 188720 436240 ) Via1_VV
+ NEW Metal2 ( 188720 436240 ) Via2_VH
+ NEW Metal2 ( 229040 436240 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 196560 436240 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 188720 436240 ) RECT ( -280 -660 280 0 ) ;
+ - _0632_ ( _1312_ A3 ) ( _1311_ ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 192080 397040 ) ( 198800 * )
+ NEW Metal2 ( 192080 395920 ) ( * 397040 )
+ NEW Metal1 ( 198800 397040 ) Via1_HV
+ NEW Metal1 ( 192080 395920 ) Via1_VV ;
+ - _0633_ ( _1317_ A2 ) ( _1316_ A3 ) ( _1313_ I ) ( _1312_ ZN ) + USE SIGNAL
+ + ROUTED Metal3 ( 204400 435120 ) ( 214480 * )
+ NEW Metal2 ( 204400 416080 ) ( * 435120 )
+ NEW Metal2 ( 202160 403760 ) ( * 416080 )
+ NEW Metal2 ( 201600 403760 ) ( 202160 * )
+ NEW Metal2 ( 197680 416080 ) ( * 418320 )
+ NEW Metal2 ( 201040 398160 ) ( * 402640 )
+ NEW Metal2 ( 201040 402640 ) ( 201600 * )
+ NEW Metal2 ( 201600 402640 ) ( * 403760 )
+ NEW Metal2 ( 197680 416080 ) ( 204400 * )
+ NEW Metal1 ( 204400 435120 ) Via1_VV
+ NEW Metal2 ( 204400 435120 ) Via2_VH
+ NEW Metal1 ( 214480 435120 ) Via1_VV
+ NEW Metal2 ( 214480 435120 ) Via2_VH
+ NEW Metal1 ( 197680 418320 ) Via1_VV
+ NEW Metal1 ( 201040 398160 ) Via1_HV
+ NEW Metal2 ( 204400 435120 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 214480 435120 ) RECT ( -280 -660 280 0 ) ;
+ - _0634_ ( _1331_ A1 ) ( _1328_ A1 ) ( _1314_ A2 ) ( _1313_ ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 195440 421680 ) ( 196560 * )
+ NEW Metal2 ( 195440 421680 ) ( * 427280 )
+ NEW Metal2 ( 188720 411600 ) ( * 421680 )
+ NEW Metal2 ( 188720 421680 ) ( 195440 * )
+ NEW Metal2 ( 196560 406000 ) ( 201040 * )
+ NEW Metal2 ( 196560 406000 ) ( * 421680 )
+ NEW Metal1 ( 196560 421680 ) Via1_VV
+ NEW Metal1 ( 195440 427280 ) Via1_VV
+ NEW Metal1 ( 188720 411600 ) Via1_VV
+ NEW Metal1 ( 201040 406000 ) Via1_VV ;
+ - _0635_ ( _1315_ A2 ) ( _1314_ Z ) + USE SIGNAL
+ + ROUTED Metal2 ( 186480 428400 ) ( * 432880 )
+ NEW Metal1 ( 186480 428400 ) Via1_VV
+ NEW Metal1 ( 186480 432880 ) Via1_VV ;
+ - _0636_ ( _1321_ A2 ) ( _1319_ A1 ) ( _1316_ ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 218960 439600 ) ( 221200 * )
+ NEW Metal2 ( 221200 439600 ) ( * 442960 )
+ NEW Metal2 ( 221200 442960 ) ( 222320 * )
+ NEW Metal2 ( 221200 428400 ) ( * 432880 )
+ NEW Metal2 ( 218960 432880 ) ( 221200 * )
+ NEW Metal2 ( 218960 432880 ) ( * 439600 )
+ NEW Metal1 ( 222320 442960 ) Via1_VV
+ NEW Metal1 ( 221200 432880 ) Via1_VV
+ NEW Metal1 ( 221200 428400 ) Via1_HV ;
+ - _0637_ ( _1318_ A2 ) ( _1317_ ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 198800 437360 ) ( 205520 * )
+ NEW Metal2 ( 198800 436240 ) ( * 437360 )
+ NEW Metal1 ( 205520 437360 ) Via1_VV
+ NEW Metal1 ( 198800 436240 ) Via1_VV ;
+ - _0638_ ( _1319_ A2 ) ( _1318_ ZN ) + USE SIGNAL
+ + ROUTED Metal3 ( 201600 442960 ) ( 220080 * )
+ NEW Metal3 ( 195440 441840 ) ( 201600 * )
+ NEW Metal3 ( 201600 441840 ) ( * 442960 )
+ NEW Metal2 ( 195440 434000 ) ( * 441840 )
+ NEW Metal1 ( 220080 442960 ) Via1_VV
+ NEW Metal2 ( 220080 442960 ) Via2_VH
+ NEW Metal2 ( 195440 441840 ) Via2_VH
+ NEW Metal1 ( 195440 434000 ) Via1_HV
+ NEW Metal2 ( 220080 442960 ) RECT ( -280 -660 280 0 ) ;
+ - _0639_ ( _1320_ I ) ( _1319_ Z ) + USE SIGNAL
+ + ROUTED Metal2 ( 216720 445200 ) ( * 446320 )
+ NEW Metal2 ( 213360 446320 ) ( 216720 * )
+ NEW Metal2 ( 213360 446320 ) ( * 450800 )
+ NEW Metal1 ( 216720 445200 ) Via1_HV
+ NEW Metal1 ( 213360 450800 ) Via1_HV ;
+ - _0640_ ( _1322_ A2 ) ( _1321_ Z ) + USE SIGNAL
+ + ROUTED Metal2 ( 229040 428400 ) ( * 432880 )
+ NEW Metal2 ( 226800 432880 ) ( 229040 * )
+ NEW Metal1 ( 229040 428400 ) Via1_VV
+ NEW Metal1 ( 226800 432880 ) Via1_VV ;
+ - _0641_ ( ANTENNA__1324__A2 I ) ( _1324_ A2 ) ( _1323_ ZN ) + USE SIGNAL
+ + ROUTED Metal3 ( 182000 356720 ) ( 196560 * )
+ NEW Metal3 ( 201600 351120 ) ( * 352240 )
+ NEW Metal3 ( 196560 352240 ) ( 201600 * )
+ NEW Metal2 ( 196560 352240 ) ( * 356720 )
+ NEW Metal3 ( 201600 351120 ) ( 454160 * )
+ NEW Metal1 ( 454160 351120 ) Via1_VV
+ NEW Metal2 ( 454160 351120 ) Via2_VH
+ NEW Metal1 ( 196560 356720 ) Via1_VV
+ NEW Metal2 ( 196560 356720 ) Via2_VH
+ NEW Metal1 ( 182000 356720 ) Via1_VV
+ NEW Metal2 ( 182000 356720 ) Via2_VH
+ NEW Metal2 ( 196560 352240 ) Via2_VH
+ NEW Metal2 ( 454160 351120 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 196560 356720 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 182000 356720 ) RECT ( -280 -660 280 0 ) ;
+ - _0642_ ( _1337_ B2 ) ( _1331_ A2 ) ( _1328_ A2 ) ( _1327_ A2 ) ( _1325_ A2 ) ( _1324_ Z ) + USE SIGNAL
+ + ROUTED Metal2 ( 194320 358960 ) ( * 364560 )
+ NEW Metal2 ( 185360 358960 ) ( 194320 * )
+ NEW Metal2 ( 188720 358960 ) ( * 380240 )
+ NEW Metal2 ( 190960 397040 ) ( * 401520 )
+ NEW Metal2 ( 187600 397040 ) ( 190960 * )
+ NEW Metal2 ( 187600 380240 ) ( * 397040 )
+ NEW Metal2 ( 187600 380240 ) ( 188720 * )
+ NEW Metal2 ( 199920 401520 ) ( * 403760 )
+ NEW Metal2 ( 190960 401520 ) ( 199920 * )
+ NEW Metal2 ( 185360 397040 ) ( * 410480 )
+ NEW Metal2 ( 185360 397040 ) ( 187600 * )
+ NEW Metal1 ( 194320 364560 ) Via1_VV
+ NEW Metal1 ( 185360 358960 ) Via1_HV
+ NEW Metal1 ( 188720 380240 ) Via1_VV
+ NEW Metal1 ( 190960 401520 ) Via1_VV
+ NEW Metal1 ( 199920 403760 ) Via1_VV
+ NEW Metal1 ( 185360 410480 ) Via1_VV ;
+ - _0643_ ( _1326_ A2 ) ( _1325_ Z ) + USE SIGNAL
+ + ROUTED Metal3 ( 203280 363440 ) ( 216720 * )
+ NEW Metal1 ( 203280 363440 ) Via1_VV
+ NEW Metal2 ( 203280 363440 ) Via2_VH
+ NEW Metal1 ( 216720 363440 ) Via1_VV
+ NEW Metal2 ( 216720 363440 ) Via2_VH
+ NEW Metal2 ( 203280 363440 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 216720 363440 ) RECT ( -280 -660 280 0 ) ;
+ - _0644_ ( _1328_ B ) ( _1327_ ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 190960 406000 ) ( 192080 * )
+ NEW Metal2 ( 190960 406000 ) ( * 410480 )
+ NEW Metal1 ( 192080 406000 ) Via1_VV
+ NEW Metal1 ( 190960 410480 ) Via1_VV ;
+ - _0645_ ( _1330_ A2 ) ( _1329_ A2 ) ( _1328_ ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 186480 412720 ) ( * 419440 )
+ NEW Metal2 ( 184240 419440 ) ( 186480 * )
+ NEW Metal2 ( 183120 406000 ) ( 184240 * )
+ NEW Metal2 ( 184240 406000 ) ( * 419440 )
+ NEW Metal1 ( 186480 412720 ) Via1_VV
+ NEW Metal1 ( 184240 419440 ) Via1_VV
+ NEW Metal1 ( 183120 406000 ) Via1_VV ;
+ - _0646_ ( _1330_ B ) ( _1329_ ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 178640 406000 ) ( 182000 * )
+ NEW Metal2 ( 178640 406000 ) ( * 419440 )
+ NEW Metal1 ( 182000 406000 ) Via1_VV
+ NEW Metal1 ( 178640 419440 ) Via1_VV ;
+ - _0647_ ( _1337_ A2 ) ( _1332_ A3 ) ( _1331_ ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 203280 393680 ) ( * 403760 )
+ NEW Metal2 ( 203280 393680 ) ( 204400 * )
+ NEW Metal2 ( 204400 386960 ) ( * 393680 )
+ NEW Metal2 ( 203280 403760 ) ( 206640 * )
+ NEW Metal2 ( 195440 380240 ) ( 196560 * )
+ NEW Metal2 ( 196560 380240 ) ( * 386960 )
+ NEW Metal3 ( 196560 386960 ) ( 204400 * )
+ NEW Metal1 ( 203280 403760 ) Via1_VV
+ NEW Metal2 ( 204400 386960 ) Via2_VH
+ NEW Metal1 ( 206640 403760 ) Via1_VV
+ NEW Metal1 ( 195440 380240 ) Via1_VV
+ NEW Metal2 ( 196560 386960 ) Via2_VH ;
+ - _0648_ ( _1333_ A2 ) ( _1332_ ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 213360 401520 ) ( 214480 * )
+ NEW Metal2 ( 214480 388080 ) ( * 401520 )
+ NEW Metal1 ( 213360 401520 ) Via1_VV
+ NEW Metal1 ( 214480 388080 ) Via1_VV ;
+ - _0649_ ( _1334_ A2 ) ( _1333_ Z ) + USE SIGNAL
+ + ROUTED Metal2 ( 223440 389200 ) ( 224560 * )
+ NEW Metal2 ( 224560 389200 ) ( * 401520 )
+ NEW Metal1 ( 223440 389200 ) Via1_VV
+ NEW Metal1 ( 224560 401520 ) Via1_VV ;
+ - _0650_ ( _1336_ A2 ) ( _1335_ ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 190960 386960 ) ( * 389200 )
+ NEW Metal2 ( 190960 389200 ) ( 199920 * )
+ NEW Metal1 ( 190960 386960 ) Via1_HV
+ NEW Metal1 ( 199920 389200 ) Via1_VV ;
+ - _0651_ ( _1337_ B1 ) ( _1336_ Z ) + USE SIGNAL
+ + ROUTED Metal2 ( 192080 380240 ) ( * 386960 )
+ NEW Metal2 ( 192080 386960 ) ( 195440 * )
+ NEW Metal1 ( 192080 380240 ) Via1_HV
+ NEW Metal1 ( 195440 386960 ) Via1_VV ;
+ - _0652_ ( _1338_ A2 ) ( _1337_ ZN ) + USE SIGNAL
+ + ROUTED Metal3 ( 180880 372400 ) ( 194320 * )
+ NEW Metal2 ( 194320 372400 ) ( * 378000 )
+ NEW Metal1 ( 180880 372400 ) Via1_VV
+ NEW Metal2 ( 180880 372400 ) Via2_VH
+ NEW Metal2 ( 194320 372400 ) Via2_VH
+ NEW Metal1 ( 194320 378000 ) Via1_VV
+ NEW Metal2 ( 180880 372400 ) RECT ( -280 -660 280 0 ) ;
+ - _0653_ ( _1339_ I ) ( _1338_ Z ) + USE SIGNAL
+ + ROUTED Metal3 ( 164080 372400 ) ( 177520 * )
+ NEW Metal1 ( 164080 372400 ) Via1_VV
+ NEW Metal2 ( 164080 372400 ) Via2_VH
+ NEW Metal1 ( 177520 372400 ) Via1_HV
+ NEW Metal2 ( 177520 372400 ) Via2_VH
+ NEW Metal2 ( 164080 372400 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 177520 372400 ) RECT ( -280 -660 280 0 ) ;
+ - _0654_ ( _1341_ B ) ( _1340_ ZN ) + USE SIGNAL
+ + ROUTED Metal3 ( 267120 348880 ) ( 272720 * )
+ NEW Metal1 ( 267120 348880 ) Via1_VV
+ NEW Metal2 ( 267120 348880 ) Via2_VH
+ NEW Metal1 ( 272720 348880 ) Via1_VV
+ NEW Metal2 ( 272720 348880 ) Via2_VH
+ NEW Metal2 ( 267120 348880 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 272720 348880 ) RECT ( -280 -660 280 0 ) ;
+ - _0655_ ( _1342_ I ) ( _1341_ ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 261520 334320 ) ( * 346640 )
+ NEW Metal1 ( 261520 334320 ) Via1_VV
+ NEW Metal1 ( 261520 346640 ) Via1_VV ;
+ - _0656_ ( _1345_ A2 ) ( _1343_ ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 238000 325360 ) ( * 326480 )
+ NEW Metal3 ( 238000 326480 ) ( 242480 * )
+ NEW Metal2 ( 242480 326480 ) ( * 355600 )
+ NEW Metal1 ( 238000 325360 ) Via1_VV
+ NEW Metal2 ( 238000 326480 ) Via2_VH
+ NEW Metal2 ( 242480 326480 ) Via2_VH
+ NEW Metal1 ( 242480 355600 ) Via1_VV ;
+ - _0657_ ( _1346_ A2 ) ( _1345_ A3 ) ( _1344_ Z ) + USE SIGNAL
+ + ROUTED Metal2 ( 233520 343280 ) ( * 348880 )
+ NEW Metal3 ( 203280 348880 ) ( 233520 * )
+ NEW Metal2 ( 236880 323120 ) ( 239120 * )
+ NEW Metal2 ( 236880 323120 ) ( * 325360 )
+ NEW Metal2 ( 235760 325360 ) ( 236880 * )
+ NEW Metal2 ( 235760 325360 ) ( * 343280 )
+ NEW Metal2 ( 233520 343280 ) ( 235760 * )
+ NEW Metal1 ( 233520 343280 ) Via1_HV
+ NEW Metal2 ( 233520 348880 ) Via2_VH
+ NEW Metal1 ( 203280 348880 ) Via1_VV
+ NEW Metal2 ( 203280 348880 ) Via2_VH
+ NEW Metal1 ( 239120 323120 ) Via1_VV
+ NEW Metal2 ( 203280 348880 ) RECT ( -280 -660 280 0 ) ;
+ - _0658_ ( _1347_ A2 ) ( _1346_ Z ) + USE SIGNAL
+ + ROUTED Metal3 ( 180880 341040 ) ( 194320 * )
+ NEW Metal2 ( 194320 341040 ) ( * 347760 )
+ NEW Metal1 ( 180880 341040 ) Via1_VV
+ NEW Metal2 ( 180880 341040 ) Via2_VH
+ NEW Metal2 ( 194320 341040 ) Via2_VH
+ NEW Metal1 ( 194320 347760 ) Via1_VV
+ NEW Metal2 ( 180880 341040 ) RECT ( -280 -660 280 0 ) ;
+ - _0659_ ( _1348_ I ) ( _1347_ Z ) + USE SIGNAL
+ + ROUTED Metal2 ( 169680 341040 ) ( 177520 * )
+ NEW Metal1 ( 169680 341040 ) Via1_VV
+ NEW Metal1 ( 177520 341040 ) Via1_HV ;
+ - _0660_ ( _1354_ A1 ) ( _1351_ A1 ) ( _1349_ Z ) + USE SIGNAL
+ + ROUTED Metal2 ( 395920 309680 ) ( * 318640 )
+ NEW Metal2 ( 395920 318640 ) ( 398160 * )
+ NEW Metal3 ( 398160 325360 ) ( 408240 * )
+ NEW Metal2 ( 398160 318640 ) ( * 325360 )
+ NEW Metal1 ( 398160 318640 ) Via1_VV
+ NEW Metal1 ( 395920 309680 ) Via1_HV
+ NEW Metal2 ( 398160 325360 ) Via2_VH
+ NEW Metal1 ( 408240 325360 ) Via1_HV
+ NEW Metal2 ( 408240 325360 ) Via2_VH
+ NEW Metal2 ( 408240 325360 ) RECT ( -280 0 280 660 ) ;
+ - _0661_ ( _1351_ A2 ) ( _1350_ ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 391440 310800 ) ( 392560 * )
+ NEW Metal2 ( 391440 310800 ) ( * 323120 )
+ NEW Metal1 ( 392560 310800 ) Via1_VV
+ NEW Metal1 ( 391440 323120 ) Via1_HV ;
+ - _0662_ ( _1353_ A2 ) ( _1352_ ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 419440 327600 ) ( * 333200 )
+ NEW Metal3 ( 404880 333200 ) ( 419440 * )
+ NEW Metal1 ( 419440 327600 ) Via1_VV
+ NEW Metal2 ( 419440 333200 ) Via2_VH
+ NEW Metal1 ( 404880 333200 ) Via1_HV
+ NEW Metal2 ( 404880 333200 ) Via2_VH
+ NEW Metal2 ( 404880 333200 ) RECT ( -280 -660 280 0 ) ;
+ - _0663_ ( _1354_ A2 ) ( _1353_ Z ) + USE SIGNAL
+ + ROUTED Metal2 ( 404880 326480 ) ( 406000 * )
+ NEW Metal2 ( 406000 326480 ) ( * 332080 )
+ NEW Metal2 ( 406000 332080 ) ( 407120 * )
+ NEW Metal1 ( 404880 326480 ) Via1_VV
+ NEW Metal1 ( 407120 332080 ) Via1_VV ;
+ - _0664_ ( _1362_ A1 ) ( _1355_ ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 476560 225680 ) ( * 231280 )
+ NEW Metal2 ( 476560 231280 ) ( 479920 * )
+ NEW Metal1 ( 476560 225680 ) Via1_VV
+ NEW Metal1 ( 479920 231280 ) Via1_HV ;
+ - _0665_ ( ANTENNA__1362__A2 I ) ( _1362_ A2 ) ( _1356_ ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 476560 123760 ) ( 477680 * )
+ NEW Metal2 ( 482160 225680 ) ( * 231280 )
+ NEW Metal2 ( 482160 225680 ) ( 483280 * )
+ NEW Metal2 ( 483280 194320 ) ( * 225680 )
+ NEW Metal2 ( 477680 194320 ) ( 483280 * )
+ NEW Metal2 ( 477680 233520 ) ( * 236880 )
+ NEW Metal2 ( 477680 233520 ) ( 481040 * )
+ NEW Metal2 ( 481040 231280 ) ( * 233520 )
+ NEW Metal2 ( 481040 231280 ) ( 482160 * )
+ NEW Metal2 ( 477680 123760 ) ( * 194320 )
+ NEW Metal1 ( 476560 123760 ) Via1_VV
+ NEW Metal1 ( 482160 231280 ) Via1_VV
+ NEW Metal1 ( 477680 236880 ) Via1_VV ;
+ - _0666_ ( _1360_ A1 ) ( _1358_ A2 ) ( _1357_ ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 546000 233520 ) ( * 241360 )
+ NEW Metal2 ( 554960 241360 ) ( 556080 * )
+ NEW Metal2 ( 554960 241360 ) ( * 244720 )
+ NEW Metal3 ( 546000 241360 ) ( 554960 * )
+ NEW Metal2 ( 546000 241360 ) Via2_VH
+ NEW Metal1 ( 546000 233520 ) Via1_VV
+ NEW Metal1 ( 556080 241360 ) Via1_VV
+ NEW Metal1 ( 554960 244720 ) Via1_VV
+ NEW Metal2 ( 554960 241360 ) Via2_VH
+ NEW Metal2 ( 554960 241360 ) RECT ( -280 -1040 280 0 ) ;
+ - _0667_ ( _1361_ A2 ) ( _1358_ ZN ) + USE SIGNAL
+ + ROUTED Metal3 ( 547120 239120 ) ( 557200 * )
+ NEW Metal1 ( 547120 239120 ) Via1_VV
+ NEW Metal2 ( 547120 239120 ) Via2_VH
+ NEW Metal1 ( 557200 239120 ) Via1_VV
+ NEW Metal2 ( 557200 239120 ) Via2_VH
+ NEW Metal2 ( 547120 239120 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 557200 239120 ) RECT ( -280 -660 280 0 ) ;
+ - _0668_ ( _1361_ A3 ) ( _1359_ ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 549360 241360 ) ( * 245840 )
+ NEW Metal2 ( 547120 245840 ) ( 549360 * )
+ NEW Metal1 ( 549360 241360 ) Via1_VV
+ NEW Metal1 ( 547120 245840 ) Via1_VV ;
+ - _0669_ ( _1361_ B ) ( _1360_ ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 541520 238000 ) ( 542640 * )
+ NEW Metal2 ( 542640 230160 ) ( * 238000 )
+ NEW Metal1 ( 541520 238000 ) Via1_VV
+ NEW Metal1 ( 542640 230160 ) Via1_VV ;
+ - _0670_ ( _1362_ A3 ) ( _1361_ ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 544880 232400 ) ( * 238000 )
+ NEW Metal3 ( 483280 232400 ) ( 544880 * )
+ NEW Metal1 ( 544880 238000 ) Via1_VV
+ NEW Metal2 ( 544880 232400 ) Via2_VH
+ NEW Metal1 ( 483280 232400 ) Via1_VV
+ NEW Metal2 ( 483280 232400 ) Via2_VH
+ NEW Metal2 ( 483280 232400 ) RECT ( -280 -660 280 0 ) ;
+ - _0671_ ( ANTENNA__1363__I I ) ( _1363_ I ) ( _1362_ Z ) + USE SIGNAL
+ + ROUTED Metal3 ( 379120 222320 ) ( 386400 * )
+ NEW Metal2 ( 388080 217840 ) ( * 221200 )
+ NEW Metal3 ( 388080 221200 ) ( 487760 * )
+ NEW Metal2 ( 487760 221200 ) ( * 229040 )
+ NEW Metal3 ( 386400 221200 ) ( * 222320 )
+ NEW Metal3 ( 386400 221200 ) ( 388080 * )
+ NEW Metal1 ( 379120 222320 ) Via1_VV
+ NEW Metal2 ( 379120 222320 ) Via2_VH
+ NEW Metal1 ( 388080 217840 ) Via1_VV
+ NEW Metal2 ( 388080 221200 ) Via2_VH
+ NEW Metal2 ( 487760 221200 ) Via2_VH
+ NEW Metal1 ( 487760 229040 ) Via1_HV
+ NEW Metal2 ( 379120 222320 ) RECT ( -280 -660 280 0 ) ;
+ - clknet_0_wb_clk_i ( ANTENNA_clkbuf_4_0_0_wb_clk_i_I I ) ( ANTENNA_clkbuf_4_1_0_wb_clk_i_I I ) ( ANTENNA_clkbuf_4_2_0_wb_clk_i_I I ) ( ANTENNA_clkbuf_4_3_0_wb_clk_i_I I ) ( ANTENNA_clkbuf_4_4_0_wb_clk_i_I I ) ( ANTENNA_clkbuf_4_5_0_wb_clk_i_I I ) ( ANTENNA_clkbuf_4_6_0_wb_clk_i_I I )
+ ( ANTENNA_clkbuf_4_7_0_wb_clk_i_I I ) ( ANTENNA_clkbuf_4_8_0_wb_clk_i_I I ) ( ANTENNA_clkbuf_4_9_0_wb_clk_i_I I ) ( ANTENNA_clkbuf_4_10_0_wb_clk_i_I I ) ( ANTENNA_clkbuf_4_11_0_wb_clk_i_I I ) ( ANTENNA_clkbuf_4_12_0_wb_clk_i_I I ) ( ANTENNA_clkbuf_4_13_0_wb_clk_i_I I ) ( ANTENNA_clkbuf_4_14_0_wb_clk_i_I I )
+ ( ANTENNA_clkbuf_4_15_0_wb_clk_i_I I ) ( clkbuf_4_15_0_wb_clk_i I ) ( clkbuf_4_14_0_wb_clk_i I ) ( clkbuf_4_13_0_wb_clk_i I ) ( clkbuf_4_12_0_wb_clk_i I ) ( clkbuf_4_11_0_wb_clk_i I ) ( clkbuf_4_10_0_wb_clk_i I ) ( clkbuf_4_9_0_wb_clk_i I )
+ ( clkbuf_4_8_0_wb_clk_i I ) ( clkbuf_4_7_0_wb_clk_i I ) ( clkbuf_4_6_0_wb_clk_i I ) ( clkbuf_4_5_0_wb_clk_i I ) ( clkbuf_4_4_0_wb_clk_i I ) ( clkbuf_4_3_0_wb_clk_i I ) ( clkbuf_4_2_0_wb_clk_i I ) ( clkbuf_4_1_0_wb_clk_i I )
+ ( clkbuf_4_0_0_wb_clk_i I ) ( clkbuf_0_wb_clk_i Z ) + USE CLOCK
+ + ROUTED Metal3 ( 224560 333200 ) ( 249200 * )
+ NEW Metal2 ( 240240 371280 ) ( 241360 * )
+ NEW Metal2 ( 241360 333200 ) ( * 371280 )
+ NEW Metal3 ( 221200 380240 ) ( 240240 * )
+ NEW Metal2 ( 240240 371280 ) ( * 380240 )
+ NEW Metal2 ( 470960 380240 ) ( * 393680 )
+ NEW Metal2 ( 470960 380240 ) ( 474320 * )
+ NEW Metal2 ( 470960 393680 ) ( * 427280 )
+ NEW Metal3 ( 442960 425040 ) ( 470960 * )
+ NEW Metal2 ( 442960 419440 ) ( * 425040 )
+ NEW Metal2 ( 324240 208880 ) ( * 300720 )
+ NEW Metal3 ( 324240 301840 ) ( 366800 * )
+ NEW Metal2 ( 389200 271600 ) ( * 285040 )
+ NEW Metal3 ( 365680 285040 ) ( 389200 * )
+ NEW Metal2 ( 365680 285040 ) ( * 301840 )
+ NEW Metal2 ( 365680 301840 ) ( 366800 * )
+ NEW Metal3 ( 389200 270480 ) ( 394800 * )
+ NEW Metal2 ( 389200 270480 ) ( * 271600 )
+ NEW Metal3 ( 394800 270480 ) ( 465360 * )
+ NEW Metal2 ( 150640 198800 ) ( * 199920 )
+ NEW Metal2 ( 150640 333200 ) ( * 339920 )
+ NEW Metal2 ( 147280 327600 ) ( * 333200 )
+ NEW Metal3 ( 147280 333200 ) ( 150640 * )
+ NEW Metal2 ( 142800 325360 ) ( * 327600 )
+ NEW Metal2 ( 142800 327600 ) ( 147280 * )
+ NEW Metal3 ( 126000 341040 ) ( 150640 * )
+ NEW Metal2 ( 150640 339920 ) ( * 341040 )
+ NEW Metal3 ( 150640 333200 ) ( 224560 * )
+ NEW Metal2 ( 366800 301840 ) ( * 319200 )
+ NEW Metal3 ( 363440 393680 ) ( 369040 * )
+ NEW Metal2 ( 369040 319200 ) ( * 393680 )
+ NEW Metal2 ( 366800 319200 ) ( 369040 * )
+ NEW Metal3 ( 369040 388080 ) ( 379120 * )
+ NEW Metal2 ( 376880 398160 ) ( * 418320 )
+ NEW Metal2 ( 375760 398160 ) ( 376880 * )
+ NEW Metal2 ( 375760 388080 ) ( * 398160 )
+ NEW Metal3 ( 376880 419440 ) ( 382480 * )
+ NEW Metal2 ( 376880 418320 ) ( * 419440 )
+ NEW Metal3 ( 249200 333200 ) ( 324240 * )
+ NEW Metal2 ( 324240 300720 ) ( * 333200 )
+ NEW Metal3 ( 382480 419440 ) ( 442960 * )
+ NEW Metal2 ( 241360 207760 ) ( * 208880 )
+ NEW Metal3 ( 241360 208880 ) ( 266000 * )
+ NEW Metal3 ( 229040 152880 ) ( 252560 * )
+ NEW Metal2 ( 157360 170800 ) ( * 185360 )
+ NEW Metal3 ( 157360 185360 ) ( 251440 * )
+ NEW Metal2 ( 251440 185360 ) ( 252560 * )
+ NEW Metal2 ( 155120 198800 ) ( 156240 * )
+ NEW Metal2 ( 156240 185360 ) ( * 198800 )
+ NEW Metal2 ( 156240 185360 ) ( 157360 * )
+ NEW Metal2 ( 157360 168560 ) ( * 170800 )
+ NEW Metal3 ( 132720 168560 ) ( 157360 * )
+ NEW Metal2 ( 150640 198800 ) ( 155120 * )
+ NEW Metal2 ( 252560 146160 ) ( * 208880 )
+ NEW Metal3 ( 266000 208880 ) ( 324240 * )
+ NEW Metal3 ( 394800 207760 ) ( 459760 * )
+ NEW Metal3 ( 459760 207760 ) ( 465360 * )
+ NEW Metal2 ( 465360 207760 ) ( * 262640 )
+ NEW Metal3 ( 380240 207760 ) ( 394800 * )
+ NEW Metal2 ( 465360 262640 ) ( * 270480 )
+ NEW Metal1 ( 465360 270480 ) Via1_VV
+ NEW Metal2 ( 465360 270480 ) Via2_VH
+ NEW Metal1 ( 252560 146160 ) Via1_VV
+ NEW Metal1 ( 249200 333200 ) Via1_VV
+ NEW Metal2 ( 249200 333200 ) Via2_VH
+ NEW Metal1 ( 224560 333200 ) Via1_HV
+ NEW Metal2 ( 224560 333200 ) Via2_VH
+ NEW Metal1 ( 240240 371280 ) Via1_VV
+ NEW Metal2 ( 241360 333200 ) Via2_VH
+ NEW Metal1 ( 221200 380240 ) Via1_HV
+ NEW Metal2 ( 221200 380240 ) Via2_VH
+ NEW Metal2 ( 240240 380240 ) Via2_VH
+ NEW Metal1 ( 470960 393680 ) Via1_VV
+ NEW Metal1 ( 474320 380240 ) Via1_HV
+ NEW Metal1 ( 470960 427280 ) Via1_HV
+ NEW Metal1 ( 442960 425040 ) Via1_VV
+ NEW Metal2 ( 442960 425040 ) Via2_VH
+ NEW Metal2 ( 470960 425040 ) Via2_VH
+ NEW Metal2 ( 442960 419440 ) Via2_VH
+ NEW Metal1 ( 324240 300720 ) Via1_HV
+ NEW Metal2 ( 324240 208880 ) Via2_VH
+ NEW Metal2 ( 366800 301840 ) Via2_VH
+ NEW Metal2 ( 324240 301840 ) Via2_VH
+ NEW Metal1 ( 389200 271600 ) Via1_VV
+ NEW Metal2 ( 389200 285040 ) Via2_VH
+ NEW Metal2 ( 365680 285040 ) Via2_VH
+ NEW Metal1 ( 394800 270480 ) Via1_HV
+ NEW Metal2 ( 394800 270480 ) Via2_VH
+ NEW Metal2 ( 389200 270480 ) Via2_VH
+ NEW Metal1 ( 380240 207760 ) Via1_VV
+ NEW Metal2 ( 380240 207760 ) Via2_VH
+ NEW Metal1 ( 150640 199920 ) Via1_HV
+ NEW Metal1 ( 132720 168560 ) Via1_HV
+ NEW Metal2 ( 132720 168560 ) Via2_VH
+ NEW Metal1 ( 150640 339920 ) Via1_VV
+ NEW Metal2 ( 150640 333200 ) Via2_VH
+ NEW Metal1 ( 147280 327600 ) Via1_VV
+ NEW Metal2 ( 147280 333200 ) Via2_VH
+ NEW Metal1 ( 142800 325360 ) Via1_HV
+ NEW Metal1 ( 126000 341040 ) Via1_HV
+ NEW Metal2 ( 126000 341040 ) Via2_VH
+ NEW Metal2 ( 150640 341040 ) Via2_VH
+ NEW Metal1 ( 363440 393680 ) Via1_VV
+ NEW Metal2 ( 363440 393680 ) Via2_VH
+ NEW Metal2 ( 369040 393680 ) Via2_VH
+ NEW Metal1 ( 379120 388080 ) Via1_HV
+ NEW Metal2 ( 379120 388080 ) Via2_VH
+ NEW Metal2 ( 369040 388080 ) Via2_VH
+ NEW Metal1 ( 376880 418320 ) Via1_VV
+ NEW Metal2 ( 375760 388080 ) Via2_VH
+ NEW Metal1 ( 382480 419440 ) Via1_HV
+ NEW Metal2 ( 382480 419440 ) Via2_VH
+ NEW Metal2 ( 376880 419440 ) Via2_VH
+ NEW Metal2 ( 324240 333200 ) Via2_VH
+ NEW Metal1 ( 266000 208880 ) Via1_VV
+ NEW Metal2 ( 266000 208880 ) Via2_VH
+ NEW Metal1 ( 241360 207760 ) Via1_HV
+ NEW Metal2 ( 241360 208880 ) Via2_VH
+ NEW Metal2 ( 252560 208880 ) Via2_VH
+ NEW Metal1 ( 229040 152880 ) Via1_HV
+ NEW Metal2 ( 229040 152880 ) Via2_VH
+ NEW Metal2 ( 252560 152880 ) Via2_VH
+ NEW Metal1 ( 157360 170800 ) Via1_VV
+ NEW Metal2 ( 157360 185360 ) Via2_VH
+ NEW Metal2 ( 251440 185360 ) Via2_VH
+ NEW Metal1 ( 155120 198800 ) Via1_VV
+ NEW Metal2 ( 157360 168560 ) Via2_VH
+ NEW Metal1 ( 394800 207760 ) Via1_HV
+ NEW Metal2 ( 394800 207760 ) Via2_VH
+ NEW Metal1 ( 459760 207760 ) Via1_VV
+ NEW Metal2 ( 459760 207760 ) Via2_VH
+ NEW Metal1 ( 465360 207760 ) Via1_HV
+ NEW Metal2 ( 465360 207760 ) Via2_VH
+ NEW Metal1 ( 465360 262640 ) Via1_HV
+ NEW Metal2 ( 465360 270480 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 249200 333200 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 224560 333200 ) RECT ( -280 -660 280 0 )
+ NEW Metal3 ( 241360 333200 ) RECT ( -1040 -280 0 280 )
+ NEW Metal2 ( 221200 380240 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 442960 425040 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 470960 425040 ) RECT ( -280 -1040 280 0 )
+ NEW Metal2 ( 324240 301840 ) RECT ( -280 -1040 280 0 )
+ NEW Metal2 ( 394800 270480 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 380240 207760 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 132720 168560 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 126000 341040 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 363440 393680 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 379120 388080 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 369040 388080 ) RECT ( -280 -1040 280 0 )
+ NEW Metal3 ( 375760 388080 ) RECT ( -1040 -280 0 280 )
+ NEW Metal2 ( 382480 419440 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 266000 208880 ) RECT ( -280 -660 280 0 )
+ NEW Metal3 ( 252560 208880 ) RECT ( -1040 -280 0 280 )
+ NEW Metal2 ( 229040 152880 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 252560 152880 ) RECT ( -280 -1040 280 0 )
+ NEW Metal2 ( 394800 207760 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 459760 207760 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 465360 207760 ) RECT ( -280 -660 280 0 ) ;
+ - clknet_4_0_0_wb_clk_i ( ANTENNA__1391__CLK I ) ( ANTENNA__1390__CLK I ) ( ANTENNA__1389__CLK I ) ( ANTENNA__1388__CLK I ) ( ANTENNA__1387__CLK I ) ( ANTENNA__1385__CLK I ) ( ANTENNA__1383__CLK I )
+ ( ANTENNA__1382__CLK I ) ( ANTENNA__1368__CLK I ) ( _1368_ CLK ) ( _1382_ CLK ) ( _1383_ CLK ) ( _1385_ CLK ) ( _1387_ CLK ) ( _1388_ CLK )
+ ( _1389_ CLK ) ( _1390_ CLK ) ( _1391_ CLK ) ( clkbuf_4_0_0_wb_clk_i Z ) + USE CLOCK
+ + ROUTED Metal2 ( 49840 177520 ) ( * 184240 )
+ NEW Metal2 ( 47600 184240 ) ( 49840 * )
+ NEW Metal2 ( 47600 152880 ) ( 48720 * )
+ NEW Metal2 ( 48720 152880 ) ( * 177520 )
+ NEW Metal2 ( 48720 177520 ) ( 49840 * )
+ NEW Metal3 ( 48720 160720 ) ( 77840 * )
+ NEW Metal2 ( 77840 155120 ) ( 80080 * )
+ NEW Metal2 ( 77840 155120 ) ( * 160720 )
+ NEW Metal2 ( 147280 90160 ) ( 151760 * )
+ NEW Metal2 ( 150640 90160 ) ( * 151760 )
+ NEW Metal2 ( 150640 151760 ) ( * 167440 )
+ NEW Metal2 ( 150640 167440 ) ( * 174160 )
+ NEW Metal2 ( 124880 146160 ) ( 126000 * )
+ NEW Metal2 ( 126000 146160 ) ( * 151760 )
+ NEW Metal3 ( 126000 151760 ) ( 150640 * )
+ NEW Metal2 ( 118160 151760 ) ( * 152880 )
+ NEW Metal3 ( 118160 151760 ) ( 126000 * )
+ NEW Metal2 ( 111440 151760 ) ( * 158480 )
+ NEW Metal3 ( 111440 151760 ) ( 118160 * )
+ NEW Metal2 ( 92400 145040 ) ( * 151760 )
+ NEW Metal3 ( 92400 151760 ) ( 111440 * )
+ NEW Metal2 ( 92400 151760 ) ( * 155120 )
+ NEW Metal3 ( 80080 155120 ) ( 92400 * )
+ NEW Metal2 ( 164080 174160 ) ( * 176400 )
+ NEW Metal3 ( 158480 174160 ) ( 164080 * )
+ NEW Metal2 ( 164080 176400 ) ( * 184240 )
+ NEW Metal2 ( 164080 183120 ) ( 168560 * )
+ NEW Metal2 ( 155120 174160 ) ( * 189840 )
+ NEW Metal2 ( 161840 184240 ) ( * 192080 )
+ NEW Metal2 ( 161840 184240 ) ( 164080 * )
+ NEW Metal3 ( 150640 174160 ) ( 158480 * )
+ NEW Metal1 ( 49840 177520 ) Via1_VV
+ NEW Metal1 ( 47600 184240 ) Via1_HV
+ NEW Metal1 ( 47600 152880 ) Via1_HV
+ NEW Metal1 ( 77840 160720 ) Via1_HV
+ NEW Metal2 ( 77840 160720 ) Via2_VH
+ NEW Metal2 ( 48720 160720 ) Via2_VH
+ NEW Metal1 ( 80080 155120 ) Via1_VV
+ NEW Metal2 ( 80080 155120 ) Via2_VH
+ NEW Metal1 ( 147280 90160 ) Via1_HV
+ NEW Metal1 ( 151760 90160 ) Via1_VV
+ NEW Metal1 ( 150640 151760 ) Via1_VV
+ NEW Metal1 ( 150640 167440 ) Via1_HV
+ NEW Metal2 ( 150640 174160 ) Via2_VH
+ NEW Metal1 ( 124880 146160 ) Via1_VV
+ NEW Metal2 ( 126000 151760 ) Via2_VH
+ NEW Metal2 ( 150640 151760 ) Via2_VH
+ NEW Metal1 ( 118160 152880 ) Via1_HV
+ NEW Metal2 ( 118160 151760 ) Via2_VH
+ NEW Metal1 ( 111440 158480 ) Via1_VV
+ NEW Metal2 ( 111440 151760 ) Via2_VH
+ NEW Metal1 ( 92400 145040 ) Via1_HV
+ NEW Metal2 ( 92400 151760 ) Via2_VH
+ NEW Metal2 ( 92400 155120 ) Via2_VH
+ NEW Metal1 ( 158480 174160 ) Via1_VV
+ NEW Metal2 ( 158480 174160 ) Via2_VH
+ NEW Metal1 ( 164080 176400 ) Via1_HV
+ NEW Metal2 ( 164080 174160 ) Via2_VH
+ NEW Metal1 ( 164080 184240 ) Via1_HV
+ NEW Metal1 ( 168560 183120 ) Via1_VV
+ NEW Metal1 ( 155120 189840 ) Via1_VV
+ NEW Metal2 ( 155120 174160 ) Via2_VH
+ NEW Metal1 ( 161840 192080 ) Via1_HV
+ NEW Metal2 ( 77840 160720 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 48720 160720 ) RECT ( -280 -1040 280 0 )
+ NEW Metal2 ( 80080 155120 ) RECT ( -280 -1040 280 0 )
+ NEW Metal2 ( 150640 151760 ) RECT ( -280 -1040 280 0 )
+ NEW Metal2 ( 158480 174160 ) RECT ( -280 -660 280 0 )
+ NEW Metal3 ( 155120 174160 ) RECT ( -1040 -280 0 280 ) ;
+ - clknet_4_10_0_wb_clk_i ( ANTENNA__1505__CLK I ) ( ANTENNA__1503__CLK I ) ( ANTENNA__1502__CLK I ) ( ANTENNA__1500__CLK I ) ( ANTENNA__1371__CLK I ) ( ANTENNA__1370__CLK I ) ( ANTENNA__1369__CLK I )
+ ( ANTENNA__1364__CLK I ) ( _1364_ CLK ) ( _1369_ CLK ) ( _1370_ CLK ) ( _1371_ CLK ) ( _1500_ CLK ) ( _1502_ CLK ) ( _1503_ CLK )
+ ( _1505_ CLK ) ( clkbuf_4_10_0_wb_clk_i Z ) + USE CLOCK
+ + ROUTED Metal2 ( 514640 214480 ) ( * 215600 )
+ NEW Metal3 ( 509040 214480 ) ( 514640 * )
+ NEW Metal2 ( 526960 208880 ) ( * 214480 )
+ NEW Metal3 ( 514640 214480 ) ( 526960 * )
+ NEW Metal3 ( 526960 207760 ) ( 534800 * )
+ NEW Metal2 ( 526960 207760 ) ( * 208880 )
+ NEW Metal3 ( 442960 90160 ) ( 475440 * )
+ NEW Metal2 ( 455280 101360 ) ( * 113680 )
+ NEW Metal2 ( 453040 101360 ) ( 455280 * )
+ NEW Metal2 ( 453040 90160 ) ( * 101360 )
+ NEW Metal2 ( 488880 90160 ) ( * 111440 )
+ NEW Metal3 ( 475440 90160 ) ( 488880 * )
+ NEW Metal3 ( 476560 136080 ) ( 486640 * )
+ NEW Metal2 ( 486640 111440 ) ( * 136080 )
+ NEW Metal2 ( 486640 111440 ) ( 488880 * )
+ NEW Metal2 ( 444080 136080 ) ( * 137200 )
+ NEW Metal3 ( 444080 136080 ) ( 476560 * )
+ NEW Metal2 ( 472080 198800 ) ( 473200 * )
+ NEW Metal2 ( 473200 182000 ) ( * 198800 )
+ NEW Metal2 ( 473200 182000 ) ( 474320 * )
+ NEW Metal2 ( 473200 208880 ) ( 476560 * )
+ NEW Metal2 ( 473200 198800 ) ( * 208880 )
+ NEW Metal2 ( 481040 208880 ) ( * 221200 )
+ NEW Metal2 ( 476560 208880 ) ( 481040 * )
+ NEW Metal2 ( 495600 229040 ) ( * 231280 )
+ NEW Metal3 ( 481040 229040 ) ( 495600 * )
+ NEW Metal2 ( 481040 221200 ) ( * 229040 )
+ NEW Metal2 ( 493360 231280 ) ( * 236880 )
+ NEW Metal2 ( 493360 231280 ) ( 495600 * )
+ NEW Metal2 ( 446320 229040 ) ( * 231280 )
+ NEW Metal3 ( 446320 229040 ) ( 481040 * )
+ NEW Metal3 ( 439600 199920 ) ( 473200 * )
+ NEW Metal2 ( 474320 136080 ) ( * 182000 )
+ NEW Metal3 ( 481040 214480 ) ( 509040 * )
+ NEW Metal1 ( 509040 214480 ) Via1_VV
+ NEW Metal2 ( 509040 214480 ) Via2_VH
+ NEW Metal1 ( 514640 215600 ) Via1_HV
+ NEW Metal2 ( 514640 214480 ) Via2_VH
+ NEW Metal1 ( 526960 208880 ) Via1_VV
+ NEW Metal2 ( 526960 214480 ) Via2_VH
+ NEW Metal1 ( 534800 207760 ) Via1_HV
+ NEW Metal2 ( 534800 207760 ) Via2_VH
+ NEW Metal2 ( 526960 207760 ) Via2_VH
+ NEW Metal1 ( 475440 90160 ) Via1_VV
+ NEW Metal2 ( 475440 90160 ) Via2_VH
+ NEW Metal1 ( 442960 90160 ) Via1_HV
+ NEW Metal2 ( 442960 90160 ) Via2_VH
+ NEW Metal1 ( 455280 113680 ) Via1_HV
+ NEW Metal2 ( 453040 90160 ) Via2_VH
+ NEW Metal1 ( 488880 111440 ) Via1_VV
+ NEW Metal2 ( 488880 90160 ) Via2_VH
+ NEW Metal1 ( 476560 136080 ) Via1_VV
+ NEW Metal2 ( 476560 136080 ) Via2_VH
+ NEW Metal2 ( 486640 136080 ) Via2_VH
+ NEW Metal1 ( 444080 137200 ) Via1_HV
+ NEW Metal2 ( 444080 136080 ) Via2_VH
+ NEW Metal2 ( 474320 136080 ) Via2_VH
+ NEW Metal1 ( 472080 198800 ) Via1_VV
+ NEW Metal1 ( 476560 208880 ) Via1_HV
+ NEW Metal1 ( 481040 221200 ) Via1_VV
+ NEW Metal1 ( 495600 231280 ) Via1_HV
+ NEW Metal2 ( 495600 229040 ) Via2_VH
+ NEW Metal2 ( 481040 229040 ) Via2_VH
+ NEW Metal1 ( 493360 236880 ) Via1_VV
+ NEW Metal2 ( 481040 214480 ) Via2_VH
+ NEW Metal1 ( 446320 231280 ) Via1_HV
+ NEW Metal2 ( 446320 229040 ) Via2_VH
+ NEW Metal1 ( 439600 199920 ) Via1_HV
+ NEW Metal2 ( 439600 199920 ) Via2_VH
+ NEW Metal2 ( 473200 199920 ) Via2_VH
+ NEW Metal2 ( 509040 214480 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 534800 207760 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 475440 90160 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 442960 90160 ) RECT ( -280 -660 280 0 )
+ NEW Metal3 ( 453040 90160 ) RECT ( -1040 -280 0 280 )
+ NEW Metal2 ( 476560 136080 ) RECT ( -280 -660 280 0 )
+ NEW Metal3 ( 474320 136080 ) RECT ( -1040 -280 0 280 )
+ NEW Metal2 ( 481040 214480 ) RECT ( -280 -1040 280 0 )
+ NEW Metal2 ( 439600 199920 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 473200 199920 ) RECT ( -280 -1040 280 0 ) ;
+ - clknet_4_11_0_wb_clk_i ( ANTENNA__1511__CLK I ) ( ANTENNA__1507__CLK I ) ( ANTENNA__1506__CLK I ) ( ANTENNA__1499__CLK I ) ( ANTENNA__1498__CLK I ) ( ANTENNA__1469__CLK I ) ( ANTENNA__1467__CLK I )
+ ( ANTENNA__1441__CLK I ) ( ANTENNA__1374__CLK I ) ( ANTENNA__1373__CLK I ) ( ANTENNA__1365__CLK I ) ( _1365_ CLK ) ( _1373_ CLK ) ( _1374_ CLK ) ( _1441_ CLK )
+ ( _1467_ CLK ) ( _1469_ CLK ) ( _1498_ CLK ) ( _1499_ CLK ) ( _1506_ CLK ) ( _1507_ CLK ) ( _1511_ CLK ) ( clkbuf_4_11_0_wb_clk_i Z ) + USE CLOCK
+ + ROUTED Metal2 ( 473200 286160 ) ( * 292880 )
+ NEW Metal2 ( 473200 286160 ) ( 478800 * )
+ NEW Metal2 ( 478800 277200 ) ( 485520 * )
+ NEW Metal2 ( 505680 246960 ) ( * 249200 )
+ NEW Metal2 ( 511280 268240 ) ( * 283920 )
+ NEW Metal2 ( 514640 264880 ) ( * 268240 )
+ NEW Metal3 ( 511280 268240 ) ( 514640 * )
+ NEW Metal2 ( 515760 283920 ) ( 516880 * )
+ NEW Metal2 ( 515760 268240 ) ( * 283920 )
+ NEW Metal2 ( 514640 268240 ) ( 515760 * )
+ NEW Metal2 ( 515760 278320 ) ( 519120 * )
+ NEW Metal2 ( 520240 262640 ) ( * 268240 )
+ NEW Metal3 ( 514640 268240 ) ( 520240 * )
+ NEW Metal2 ( 522480 288400 ) ( * 294000 )
+ NEW Metal1 ( 515760 288400 ) ( 522480 * )
+ NEW Metal2 ( 515760 283920 ) ( * 288400 )
+ NEW Metal3 ( 520240 268240 ) ( 525840 * )
+ NEW Metal2 ( 435120 278320 ) ( * 294000 )
+ NEW Metal3 ( 435120 278320 ) ( 451920 * )
+ NEW Metal2 ( 492240 268800 ) ( * 270480 )
+ NEW Metal3 ( 445200 262640 ) ( 456400 * )
+ NEW Metal2 ( 456400 254800 ) ( * 262640 )
+ NEW Metal2 ( 473200 261520 ) ( * 262640 )
+ NEW Metal3 ( 456400 262640 ) ( 473200 * )
+ NEW Metal3 ( 473200 262640 ) ( 478800 * )
+ NEW Metal2 ( 490000 254800 ) ( * 262640 )
+ NEW Metal3 ( 478800 262640 ) ( 490000 * )
+ NEW Metal2 ( 490000 268800 ) ( 492240 * )
+ NEW Metal2 ( 490000 262640 ) ( * 268800 )
+ NEW Metal3 ( 490000 262640 ) ( 494480 * )
+ NEW Metal2 ( 486640 249200 ) ( * 254800 )
+ NEW Metal2 ( 486640 254800 ) ( 490000 * )
+ NEW Metal2 ( 494480 249200 ) ( * 262640 )
+ NEW Metal2 ( 494480 249200 ) ( 500080 * )
+ NEW Metal2 ( 492240 268240 ) ( * 268800 )
+ NEW Metal2 ( 445200 262640 ) ( * 278320 )
+ NEW Metal2 ( 478800 262640 ) ( * 286160 )
+ NEW Metal2 ( 500080 249200 ) ( 505680 * )
+ NEW Metal3 ( 492240 268240 ) ( 511280 * )
+ NEW Metal1 ( 451920 278320 ) Via1_HV
+ NEW Metal2 ( 451920 278320 ) Via2_VH
+ NEW Metal2 ( 445200 278320 ) Via2_VH
+ NEW Metal1 ( 478800 286160 ) Via1_HV
+ NEW Metal1 ( 473200 292880 ) Via1_VV
+ NEW Metal1 ( 485520 277200 ) Via1_VV
+ NEW Metal1 ( 492240 270480 ) Via1_HV
+ NEW Metal1 ( 505680 246960 ) Via1_HV
+ NEW Metal1 ( 511280 283920 ) Via1_VV
+ NEW Metal2 ( 511280 268240 ) Via2_VH
+ NEW Metal1 ( 514640 264880 ) Via1_VV
+ NEW Metal2 ( 514640 268240 ) Via2_VH
+ NEW Metal1 ( 516880 283920 ) Via1_VV
+ NEW Metal1 ( 519120 278320 ) Via1_HV
+ NEW Metal1 ( 520240 262640 ) Via1_HV
+ NEW Metal2 ( 520240 268240 ) Via2_VH
+ NEW Metal1 ( 522480 294000 ) Via1_HV
+ NEW Metal1 ( 522480 288400 ) Via1_HV
+ NEW Metal1 ( 515760 288400 ) Via1_HV
+ NEW Metal1 ( 525840 268240 ) Via1_VV
+ NEW Metal2 ( 525840 268240 ) Via2_VH
+ NEW Metal2 ( 435120 278320 ) Via2_VH
+ NEW Metal1 ( 435120 294000 ) Via1_HV
+ NEW Metal1 ( 445200 262640 ) Via1_HV
+ NEW Metal1 ( 456400 262640 ) Via1_VV
+ NEW Metal2 ( 456400 262640 ) Via2_VH
+ NEW Metal2 ( 445200 262640 ) Via2_VH
+ NEW Metal1 ( 456400 254800 ) Via1_HV
+ NEW Metal1 ( 473200 261520 ) Via1_HV
+ NEW Metal2 ( 473200 262640 ) Via2_VH
+ NEW Metal2 ( 478800 262640 ) Via2_VH
+ NEW Metal1 ( 490000 254800 ) Via1_HV
+ NEW Metal2 ( 490000 262640 ) Via2_VH
+ NEW Metal1 ( 494480 262640 ) Via1_VV
+ NEW Metal2 ( 494480 262640 ) Via2_VH
+ NEW Metal1 ( 486640 249200 ) Via1_VV
+ NEW Metal1 ( 494480 249200 ) Via1_VV
+ NEW Metal1 ( 500080 249200 ) Via1_VV
+ NEW Metal2 ( 492240 268240 ) Via2_VH
+ NEW Metal2 ( 451920 278320 ) RECT ( -280 -660 280 0 )
+ NEW Metal3 ( 445200 278320 ) RECT ( -1040 -280 0 280 )
+ NEW Metal2 ( 525840 268240 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 456400 262640 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 445200 262640 ) RECT ( -280 -1040 280 0 )
+ NEW Metal2 ( 494480 262640 ) RECT ( -280 -660 280 0 ) ;
+ - clknet_4_12_0_wb_clk_i ( ANTENNA__1508__CLK I ) ( ANTENNA__1483__CLK I ) ( ANTENNA__1481__CLK I ) ( ANTENNA__1480__CLK I ) ( ANTENNA__1478__CLK I ) ( ANTENNA__1472__CLK I ) ( ANTENNA__1447__CLK I )
+ ( _1447_ CLK ) ( _1472_ CLK ) ( _1478_ CLK ) ( _1480_ CLK ) ( _1481_ CLK ) ( _1483_ CLK ) ( _1508_ CLK ) ( clkbuf_4_12_0_wb_clk_i Z ) + USE CLOCK
+ + ROUTED Metal2 ( 338800 325360 ) ( * 333200 )
+ NEW Metal3 ( 335440 325360 ) ( 338800 * )
+ NEW Metal2 ( 370160 333200 ) ( * 339920 )
+ NEW Metal3 ( 338800 333200 ) ( 370160 * )
+ NEW Metal3 ( 339920 380240 ) ( 370160 * )
+ NEW Metal2 ( 370160 339920 ) ( * 380240 )
+ NEW Metal3 ( 370160 380240 ) ( 374640 * )
+ NEW Metal3 ( 327600 386960 ) ( 338800 * )
+ NEW Metal2 ( 338800 380240 ) ( * 386960 )
+ NEW Metal2 ( 338800 380240 ) ( 339920 * )
+ NEW Metal2 ( 327600 386960 ) ( * 395920 )
+ NEW Metal2 ( 351120 380240 ) ( * 403760 )
+ NEW Metal2 ( 375760 403760 ) ( * 411600 )
+ NEW Metal3 ( 351120 403760 ) ( 375760 * )
+ NEW Metal2 ( 390320 380240 ) ( * 386960 )
+ NEW Metal3 ( 374640 380240 ) ( 390320 * )
+ NEW Metal3 ( 375760 403760 ) ( 394800 * )
+ NEW Metal3 ( 394800 403760 ) ( 419440 * )
+ NEW Metal2 ( 423920 365680 ) ( * 402640 )
+ NEW Metal3 ( 419440 402640 ) ( 423920 * )
+ NEW Metal3 ( 419440 402640 ) ( * 403760 )
+ NEW Metal2 ( 427280 356720 ) ( * 365680 )
+ NEW Metal2 ( 423920 365680 ) ( 427280 * )
+ NEW Metal3 ( 300720 325360 ) ( 335440 * )
+ NEW Metal3 ( 297360 395920 ) ( 327600 * )
+ NEW Metal1 ( 297360 395920 ) Via1_HV
+ NEW Metal2 ( 297360 395920 ) Via2_VH
+ NEW Metal1 ( 300720 325360 ) Via1_HV
+ NEW Metal2 ( 300720 325360 ) Via2_VH
+ NEW Metal1 ( 335440 325360 ) Via1_VV
+ NEW Metal2 ( 335440 325360 ) Via2_VH
+ NEW Metal1 ( 338800 333200 ) Via1_HV
+ NEW Metal2 ( 338800 325360 ) Via2_VH
+ NEW Metal1 ( 370160 339920 ) Via1_VV
+ NEW Metal2 ( 370160 333200 ) Via2_VH
+ NEW Metal2 ( 338800 333200 ) Via2_VH
+ NEW Metal1 ( 339920 380240 ) Via1_HV
+ NEW Metal2 ( 339920 380240 ) Via2_VH
+ NEW Metal2 ( 370160 380240 ) Via2_VH
+ NEW Metal1 ( 374640 380240 ) Via1_VV
+ NEW Metal2 ( 374640 380240 ) Via2_VH
+ NEW Metal1 ( 327600 386960 ) Via1_VV
+ NEW Metal2 ( 327600 386960 ) Via2_VH
+ NEW Metal2 ( 338800 386960 ) Via2_VH
+ NEW Metal2 ( 327600 395920 ) Via2_VH
+ NEW Metal1 ( 351120 403760 ) Via1_HV
+ NEW Metal2 ( 351120 380240 ) Via2_VH
+ NEW Metal1 ( 375760 411600 ) Via1_HV
+ NEW Metal2 ( 375760 403760 ) Via2_VH
+ NEW Metal2 ( 351120 403760 ) Via2_VH
+ NEW Metal1 ( 390320 386960 ) Via1_HV
+ NEW Metal2 ( 390320 380240 ) Via2_VH
+ NEW Metal1 ( 394800 403760 ) Via1_VV
+ NEW Metal2 ( 394800 403760 ) Via2_VH
+ NEW Metal1 ( 419440 403760 ) Via1_VV
+ NEW Metal2 ( 419440 403760 ) Via2_VH
+ NEW Metal1 ( 423920 365680 ) Via1_VV
+ NEW Metal2 ( 423920 402640 ) Via2_VH
+ NEW Metal1 ( 427280 356720 ) Via1_HV
+ NEW Metal2 ( 297360 395920 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 300720 325360 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 335440 325360 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 338800 333200 ) RECT ( -280 -1040 280 0 )
+ NEW Metal2 ( 339920 380240 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 374640 380240 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 327600 386960 ) RECT ( -280 -660 280 0 )
+ NEW Metal3 ( 351120 380240 ) RECT ( -1040 -280 0 280 )
+ NEW Metal2 ( 351120 403760 ) RECT ( -280 -1040 280 0 )
+ NEW Metal2 ( 394800 403760 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 419440 403760 ) RECT ( -280 -660 280 0 ) ;
+ - clknet_4_13_0_wb_clk_i ( ANTENNA__1485__CLK I ) ( ANTENNA__1482__CLK I ) ( ANTENNA__1477__CLK I ) ( ANTENNA__1451__CLK I ) ( ANTENNA__1450__CLK I ) ( ANTENNA__1446__CLK I ) ( ANTENNA__1445__CLK I )
+ ( ANTENNA__1444__CLK I ) ( ANTENNA__1442__CLK I ) ( _1442_ CLK ) ( _1444_ CLK ) ( _1445_ CLK ) ( _1446_ CLK ) ( _1450_ CLK ) ( _1451_ CLK )
+ ( _1477_ CLK ) ( _1482_ CLK ) ( _1485_ CLK ) ( clkbuf_4_13_0_wb_clk_i Z ) + USE CLOCK
+ + ROUTED Metal2 ( 311920 490000 ) ( * 505680 )
+ NEW Metal2 ( 300720 435120 ) ( * 437360 )
+ NEW Metal2 ( 330960 437360 ) ( * 440720 )
+ NEW Metal2 ( 319760 437360 ) ( * 458640 )
+ NEW Metal2 ( 322000 458640 ) ( * 466480 )
+ NEW Metal2 ( 319760 458640 ) ( 322000 * )
+ NEW Metal2 ( 322000 465360 ) ( 327600 * )
+ NEW Metal2 ( 398160 521360 ) ( * 528080 )
+ NEW Metal2 ( 395920 528080 ) ( 398160 * )
+ NEW Metal3 ( 379120 521360 ) ( 398160 * )
+ NEW Metal2 ( 374640 506800 ) ( * 521360 )
+ NEW Metal3 ( 374640 521360 ) ( 379120 * )
+ NEW Metal3 ( 348880 513520 ) ( 374640 * )
+ NEW Metal2 ( 325360 505680 ) ( * 513520 )
+ NEW Metal3 ( 325360 513520 ) ( 348880 * )
+ NEW Metal2 ( 342160 484400 ) ( * 513520 )
+ NEW Metal3 ( 342160 453040 ) ( 350000 * )
+ NEW Metal2 ( 342160 453040 ) ( * 484400 )
+ NEW Metal3 ( 300720 437360 ) ( 336560 * )
+ NEW Metal3 ( 311920 505680 ) ( 325360 * )
+ NEW Metal2 ( 336560 436800 ) ( * 437360 )
+ NEW Metal2 ( 402640 403760 ) ( 403760 * )
+ NEW Metal2 ( 402640 395920 ) ( * 403760 )
+ NEW Metal2 ( 400400 395920 ) ( 402640 * )
+ NEW Metal2 ( 402640 403760 ) ( * 418320 )
+ NEW Metal3 ( 381360 434000 ) ( 402640 * )
+ NEW Metal2 ( 402640 418320 ) ( * 434000 )
+ NEW Metal3 ( 350000 434000 ) ( 381360 * )
+ NEW Metal2 ( 337680 434000 ) ( * 435120 )
+ NEW Metal3 ( 337680 434000 ) ( 350000 * )
+ NEW Metal2 ( 336560 436800 ) ( 337680 * )
+ NEW Metal2 ( 337680 435120 ) ( * 436800 )
+ NEW Metal2 ( 350000 434000 ) ( * 453040 )
+ NEW Metal2 ( 311920 505680 ) Via2_VH
+ NEW Metal1 ( 311920 490000 ) Via1_HV
+ NEW Metal2 ( 300720 437360 ) Via2_VH
+ NEW Metal1 ( 300720 435120 ) Via1_HV
+ NEW Metal2 ( 336560 437360 ) Via2_VH
+ NEW Metal1 ( 330960 440720 ) Via1_VV
+ NEW Metal2 ( 330960 437360 ) Via2_VH
+ NEW Metal1 ( 319760 458640 ) Via1_HV
+ NEW Metal2 ( 319760 437360 ) Via2_VH
+ NEW Metal1 ( 322000 466480 ) Via1_HV
+ NEW Metal1 ( 327600 465360 ) Via1_VV
+ NEW Metal1 ( 398160 521360 ) Via1_HV
+ NEW Metal1 ( 395920 528080 ) Via1_VV
+ NEW Metal1 ( 379120 521360 ) Via1_VV
+ NEW Metal2 ( 379120 521360 ) Via2_VH
+ NEW Metal2 ( 398160 521360 ) Via2_VH
+ NEW Metal1 ( 374640 506800 ) Via1_VV
+ NEW Metal2 ( 374640 521360 ) Via2_VH
+ NEW Metal1 ( 348880 513520 ) Via1_HV
+ NEW Metal2 ( 348880 513520 ) Via2_VH
+ NEW Metal2 ( 374640 513520 ) Via2_VH
+ NEW Metal1 ( 325360 505680 ) Via1_HV
+ NEW Metal2 ( 325360 513520 ) Via2_VH
+ NEW Metal2 ( 325360 505680 ) Via2_VH
+ NEW Metal1 ( 342160 484400 ) Via1_VV
+ NEW Metal2 ( 342160 513520 ) Via2_VH
+ NEW Metal1 ( 350000 453040 ) Via1_VV
+ NEW Metal2 ( 350000 453040 ) Via2_VH
+ NEW Metal2 ( 342160 453040 ) Via2_VH
+ NEW Metal1 ( 403760 403760 ) Via1_VV
+ NEW Metal1 ( 400400 395920 ) Via1_HV
+ NEW Metal1 ( 402640 418320 ) Via1_HV
+ NEW Metal1 ( 381360 434000 ) Via1_VV
+ NEW Metal2 ( 381360 434000 ) Via2_VH
+ NEW Metal2 ( 402640 434000 ) Via2_VH
+ NEW Metal2 ( 350000 434000 ) Via2_VH
+ NEW Metal1 ( 337680 435120 ) Via1_HV
+ NEW Metal2 ( 337680 434000 ) Via2_VH
+ NEW Metal3 ( 330960 437360 ) RECT ( -1040 -280 0 280 )
+ NEW Metal3 ( 319760 437360 ) RECT ( 0 -280 1040 280 )
+ NEW Metal2 ( 379120 521360 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 398160 521360 ) RECT ( -280 -1040 280 0 )
+ NEW Metal2 ( 348880 513520 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 374640 513520 ) RECT ( -280 -1040 280 0 )
+ NEW Metal2 ( 325360 505680 ) RECT ( -280 -1040 280 0 )
+ NEW Metal3 ( 342160 513520 ) RECT ( -1040 -280 0 280 )
+ NEW Metal2 ( 350000 453040 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 381360 434000 ) RECT ( -280 -660 280 0 ) ;
+ - clknet_4_14_0_wb_clk_i ( ANTENNA__1513__CLK I ) ( ANTENNA__1479__CLK I ) ( ANTENNA__1476__CLK I ) ( ANTENNA__1475__CLK I ) ( ANTENNA__1474__CLK I ) ( ANTENNA__1473__CLK I ) ( ANTENNA__1471__CLK I )
+ ( ANTENNA__1470__CLK I ) ( ANTENNA__1468__CLK I ) ( _1468_ CLK ) ( _1470_ CLK ) ( _1471_ CLK ) ( _1473_ CLK ) ( _1474_ CLK ) ( _1475_ CLK )
+ ( _1476_ CLK ) ( _1479_ CLK ) ( _1513_ CLK ) ( clkbuf_4_14_0_wb_clk_i Z ) + USE CLOCK
+ + ROUTED Metal3 ( 519120 318640 ) ( 524720 * )
+ NEW Metal2 ( 439600 346640 ) ( * 388080 )
+ NEW Metal2 ( 439600 346640 ) ( 440720 * )
+ NEW Metal2 ( 475440 392560 ) ( * 393680 )
+ NEW Metal3 ( 439600 392560 ) ( 475440 * )
+ NEW Metal2 ( 439600 388080 ) ( * 392560 )
+ NEW Metal2 ( 491120 381360 ) ( * 392560 )
+ NEW Metal3 ( 475440 392560 ) ( 491120 * )
+ NEW Metal2 ( 500080 392560 ) ( * 411600 )
+ NEW Metal3 ( 491120 392560 ) ( 500080 * )
+ NEW Metal3 ( 500080 409360 ) ( 505680 * )
+ NEW Metal3 ( 491120 381360 ) ( 522480 * )
+ NEW Metal2 ( 523600 350000 ) ( 524720 * )
+ NEW Metal2 ( 523600 350000 ) ( * 364560 )
+ NEW Metal2 ( 522480 364560 ) ( 523600 * )
+ NEW Metal2 ( 522480 364560 ) ( * 381360 )
+ NEW Metal2 ( 531440 352240 ) ( * 355600 )
+ NEW Metal3 ( 523600 352240 ) ( 531440 * )
+ NEW Metal2 ( 534800 355600 ) ( * 364560 )
+ NEW Metal2 ( 531440 355600 ) ( 534800 * )
+ NEW Metal2 ( 550480 381360 ) ( * 388080 )
+ NEW Metal3 ( 522480 381360 ) ( 550480 * )
+ NEW Metal2 ( 531440 336560 ) ( * 352240 )
+ NEW Metal2 ( 549360 325360 ) ( * 336560 )
+ NEW Metal3 ( 524720 336560 ) ( 531440 * )
+ NEW Metal2 ( 459760 334320 ) ( * 336560 )
+ NEW Metal2 ( 524720 318640 ) ( * 336560 )
+ NEW Metal3 ( 432880 317520 ) ( 438480 * )
+ NEW Metal2 ( 432880 317520 ) ( * 319200 )
+ NEW Metal2 ( 436240 346640 ) ( * 348880 )
+ NEW Metal2 ( 436240 336560 ) ( * 346640 )
+ NEW Metal2 ( 431760 325360 ) ( * 336560 )
+ NEW Metal3 ( 431760 336560 ) ( 436240 * )
+ NEW Metal2 ( 431760 319200 ) ( 432880 * )
+ NEW Metal2 ( 431760 319200 ) ( * 325360 )
+ NEW Metal3 ( 436240 336560 ) ( 459760 * )
+ NEW Metal3 ( 436240 346640 ) ( 440720 * )
+ NEW Metal2 ( 556080 336560 ) ( * 341040 )
+ NEW Metal3 ( 531440 336560 ) ( 556080 * )
+ NEW Metal1 ( 438480 317520 ) Via1_VV
+ NEW Metal2 ( 438480 317520 ) Via2_VH
+ NEW Metal1 ( 519120 318640 ) Via1_VV
+ NEW Metal2 ( 519120 318640 ) Via2_VH
+ NEW Metal2 ( 524720 318640 ) Via2_VH
+ NEW Metal1 ( 440720 346640 ) Via1_VV
+ NEW Metal2 ( 440720 346640 ) Via2_VH
+ NEW Metal1 ( 439600 388080 ) Via1_HV
+ NEW Metal1 ( 475440 393680 ) Via1_VV
+ NEW Metal2 ( 475440 392560 ) Via2_VH
+ NEW Metal2 ( 439600 392560 ) Via2_VH
+ NEW Metal1 ( 491120 381360 ) Via1_HV
+ NEW Metal2 ( 491120 392560 ) Via2_VH
+ NEW Metal1 ( 500080 411600 ) Via1_HV
+ NEW Metal2 ( 500080 392560 ) Via2_VH
+ NEW Metal1 ( 505680 409360 ) Via1_VV
+ NEW Metal2 ( 505680 409360 ) Via2_VH
+ NEW Metal2 ( 500080 409360 ) Via2_VH
+ NEW Metal1 ( 522480 381360 ) Via1_VV
+ NEW Metal2 ( 522480 381360 ) Via2_VH
+ NEW Metal2 ( 491120 381360 ) Via2_VH
+ NEW Metal1 ( 524720 350000 ) Via1_VV
+ NEW Metal1 ( 531440 355600 ) Via1_VV
+ NEW Metal2 ( 531440 352240 ) Via2_VH
+ NEW Metal2 ( 523600 352240 ) Via2_VH
+ NEW Metal1 ( 534800 364560 ) Via1_HV
+ NEW Metal1 ( 550480 388080 ) Via1_HV
+ NEW Metal2 ( 550480 381360 ) Via2_VH
+ NEW Metal2 ( 531440 336560 ) Via2_VH
+ NEW Metal1 ( 549360 325360 ) Via1_HV
+ NEW Metal2 ( 549360 336560 ) Via2_VH
+ NEW Metal2 ( 524720 336560 ) Via2_VH
+ NEW Metal1 ( 459760 334320 ) Via1_VV
+ NEW Metal2 ( 459760 336560 ) Via2_VH
+ NEW Metal2 ( 432880 317520 ) Via2_VH
+ NEW Metal1 ( 432880 317520 ) Via1_HV
+ NEW Metal2 ( 436240 346640 ) Via2_VH
+ NEW Metal1 ( 436240 348880 ) Via1_HV
+ NEW Metal2 ( 436240 336560 ) Via2_VH
+ NEW Metal1 ( 431760 325360 ) Via1_HV
+ NEW Metal2 ( 431760 336560 ) Via2_VH
+ NEW Metal2 ( 556080 336560 ) Via2_VH
+ NEW Metal1 ( 556080 341040 ) Via1_HV
+ NEW Metal2 ( 438480 317520 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 519120 318640 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 440720 346640 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 505680 409360 ) RECT ( -280 0 280 660 )
+ NEW Metal2 ( 500080 409360 ) RECT ( -280 -1040 280 0 )
+ NEW Metal2 ( 522480 381360 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 491120 381360 ) RECT ( -280 -1040 280 0 )
+ NEW Metal2 ( 523600 352240 ) RECT ( -280 -1040 280 0 )
+ NEW Metal3 ( 549360 336560 ) RECT ( -1040 -280 0 280 )
+ NEW Metal2 ( 432880 317520 ) RECT ( -280 -1040 280 0 ) ;
+ - clknet_4_15_0_wb_clk_i ( ANTENNA__1461__CLK I ) ( ANTENNA__1460__CLK I ) ( ANTENNA__1459__CLK I ) ( ANTENNA__1458__CLK I ) ( ANTENNA__1457__CLK I ) ( ANTENNA__1456__CLK I ) ( ANTENNA__1455__CLK I )
+ ( ANTENNA__1454__CLK I ) ( ANTENNA__1453__CLK I ) ( ANTENNA__1452__CLK I ) ( ANTENNA__1449__CLK I ) ( ANTENNA__1448__CLK I ) ( ANTENNA__1443__CLK I ) ( _1443_ CLK ) ( _1448_ CLK )
+ ( _1449_ CLK ) ( _1452_ CLK ) ( _1453_ CLK ) ( _1454_ CLK ) ( _1455_ CLK ) ( _1456_ CLK ) ( _1457_ CLK ) ( _1458_ CLK )
+ ( _1459_ CLK ) ( _1460_ CLK ) ( _1461_ CLK ) ( clkbuf_4_15_0_wb_clk_i Z ) + USE CLOCK
+ + ROUTED Metal3 ( 476560 515760 ) ( 485520 * )
+ NEW Metal2 ( 476560 515760 ) ( * 521360 )
+ NEW Metal3 ( 485520 515760 ) ( 505680 * )
+ NEW Metal2 ( 509040 515760 ) ( * 519120 )
+ NEW Metal3 ( 505680 515760 ) ( 509040 * )
+ NEW Metal2 ( 511280 513520 ) ( * 515760 )
+ NEW Metal2 ( 509040 515760 ) ( 511280 * )
+ NEW Metal2 ( 531440 500080 ) ( * 515760 )
+ NEW Metal3 ( 509040 515760 ) ( 531440 * )
+ NEW Metal2 ( 534800 490000 ) ( * 500080 )
+ NEW Metal2 ( 531440 500080 ) ( 534800 * )
+ NEW Metal2 ( 528080 466480 ) ( * 500080 )
+ NEW Metal2 ( 528080 500080 ) ( 531440 * )
+ NEW Metal2 ( 521360 464240 ) ( * 465360 )
+ NEW Metal1 ( 521360 464240 ) ( 524720 * )
+ NEW Metal2 ( 524720 464240 ) ( 528080 * )
+ NEW Metal2 ( 528080 464240 ) ( * 466480 )
+ NEW Metal2 ( 521360 438480 ) ( 523600 * )
+ NEW Metal2 ( 523600 438480 ) ( * 464240 )
+ NEW Metal2 ( 523600 464240 ) ( 524720 * )
+ NEW Metal2 ( 523600 438480 ) ( 525840 * )
+ NEW Metal2 ( 458640 453040 ) ( 459760 * )
+ NEW Metal2 ( 459760 453040 ) ( * 484400 )
+ NEW Metal3 ( 446320 442960 ) ( 458640 * )
+ NEW Metal2 ( 458640 442960 ) ( * 453040 )
+ NEW Metal3 ( 438480 437360 ) ( 446320 * )
+ NEW Metal3 ( 458640 442960 ) ( 474320 * )
+ NEW Metal2 ( 474320 442960 ) ( 475440 * )
+ NEW Metal2 ( 444080 497840 ) ( * 498960 )
+ NEW Metal2 ( 444080 497840 ) ( 449680 * )
+ NEW Metal2 ( 475440 436800 ) ( * 442960 )
+ NEW Metal2 ( 477680 428400 ) ( 478800 * )
+ NEW Metal2 ( 477680 428400 ) ( * 436800 )
+ NEW Metal2 ( 475440 436800 ) ( 477680 * )
+ NEW Metal2 ( 481040 421680 ) ( * 428400 )
+ NEW Metal2 ( 478800 428400 ) ( 481040 * )
+ NEW Metal2 ( 495600 419440 ) ( * 421680 )
+ NEW Metal3 ( 481040 421680 ) ( 495600 * )
+ NEW Metal2 ( 525840 421680 ) ( * 435120 )
+ NEW Metal3 ( 495600 421680 ) ( 525840 * )
+ NEW Metal2 ( 529200 419440 ) ( * 421680 )
+ NEW Metal3 ( 525840 421680 ) ( 529200 * )
+ NEW Metal2 ( 520240 436240 ) ( 521360 * )
+ NEW Metal2 ( 445200 412720 ) ( 446320 * )
+ NEW Metal2 ( 446320 412720 ) ( * 419440 )
+ NEW Metal2 ( 439600 411600 ) ( * 412720 )
+ NEW Metal2 ( 439600 412720 ) ( 445200 * )
+ NEW Metal2 ( 438480 435120 ) ( * 437360 )
+ NEW Metal2 ( 446320 419440 ) ( * 442960 )
+ NEW Metal2 ( 521360 436240 ) ( * 438480 )
+ NEW Metal2 ( 525840 435120 ) ( * 438480 )
+ NEW Metal2 ( 434000 498960 ) ( * 513520 )
+ NEW Metal2 ( 435120 482160 ) ( * 498960 )
+ NEW Metal3 ( 435120 484400 ) ( 467600 * )
+ NEW Metal2 ( 434000 498960 ) ( 444080 * )
+ NEW Metal1 ( 485520 515760 ) Via1_VV
+ NEW Metal2 ( 485520 515760 ) Via2_VH
+ NEW Metal2 ( 476560 515760 ) Via2_VH
+ NEW Metal1 ( 476560 521360 ) Via1_HV
+ NEW Metal1 ( 505680 515760 ) Via1_VV
+ NEW Metal2 ( 505680 515760 ) Via2_VH
+ NEW Metal1 ( 509040 519120 ) Via1_VV
+ NEW Metal2 ( 509040 515760 ) Via2_VH
+ NEW Metal1 ( 511280 513520 ) Via1_HV
+ NEW Metal1 ( 531440 500080 ) Via1_VV
+ NEW Metal2 ( 531440 515760 ) Via2_VH
+ NEW Metal1 ( 534800 490000 ) Via1_HV
+ NEW Metal1 ( 528080 466480 ) Via1_HV
+ NEW Metal1 ( 521360 465360 ) Via1_VV
+ NEW Metal1 ( 521360 464240 ) Via1_HV
+ NEW Metal1 ( 524720 464240 ) Via1_HV
+ NEW Metal1 ( 467600 484400 ) Via1_VV
+ NEW Metal2 ( 467600 484400 ) Via2_VH
+ NEW Metal1 ( 458640 453040 ) Via1_VV
+ NEW Metal2 ( 459760 484400 ) Via2_VH
+ NEW Metal1 ( 446320 442960 ) Via1_HV
+ NEW Metal2 ( 446320 442960 ) Via2_VH
+ NEW Metal2 ( 458640 442960 ) Via2_VH
+ NEW Metal2 ( 438480 437360 ) Via2_VH
+ NEW Metal2 ( 446320 437360 ) Via2_VH
+ NEW Metal1 ( 474320 442960 ) Via1_VV
+ NEW Metal2 ( 474320 442960 ) Via2_VH
+ NEW Metal1 ( 444080 497840 ) Via1_HV
+ NEW Metal1 ( 449680 497840 ) Via1_VV
+ NEW Metal1 ( 478800 428400 ) Via1_HV
+ NEW Metal1 ( 481040 421680 ) Via1_VV
+ NEW Metal1 ( 495600 419440 ) Via1_VV
+ NEW Metal2 ( 495600 421680 ) Via2_VH
+ NEW Metal2 ( 481040 421680 ) Via2_VH
+ NEW Metal1 ( 525840 435120 ) Via1_HV
+ NEW Metal2 ( 525840 421680 ) Via2_VH
+ NEW Metal1 ( 529200 419440 ) Via1_HV
+ NEW Metal2 ( 529200 421680 ) Via2_VH
+ NEW Metal1 ( 520240 436240 ) Via1_VV
+ NEW Metal1 ( 438480 435120 ) Via1_HV
+ NEW Metal1 ( 446320 419440 ) Via1_HV
+ NEW Metal1 ( 445200 412720 ) Via1_VV
+ NEW Metal1 ( 439600 411600 ) Via1_HV
+ NEW Metal1 ( 434000 513520 ) Via1_HV
+ NEW Metal1 ( 435120 482160 ) Via1_HV
+ NEW Metal2 ( 435120 484400 ) Via2_VH
+ NEW Metal2 ( 485520 515760 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 505680 515760 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 467600 484400 ) RECT ( -280 -660 280 0 )
+ NEW Metal3 ( 459760 484400 ) RECT ( -1040 -280 0 280 )
+ NEW Metal2 ( 446320 442960 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 446320 437360 ) RECT ( -280 0 280 1040 )
+ NEW Metal2 ( 474320 442960 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 481040 421680 ) RECT ( -280 -1040 280 0 )
+ NEW Metal2 ( 435120 484400 ) RECT ( -280 -1040 280 0 ) ;
+ - clknet_4_1_0_wb_clk_i ( ANTENNA__1396__CLK I ) ( ANTENNA__1395__CLK I ) ( ANTENNA__1394__CLK I ) ( ANTENNA__1393__CLK I ) ( ANTENNA__1392__CLK I ) ( ANTENNA__1386__CLK I ) ( ANTENNA__1381__CLK I )
+ ( ANTENNA__1380__CLK I ) ( ANTENNA__1379__CLK I ) ( ANTENNA__1378__CLK I ) ( _1378_ CLK ) ( _1379_ CLK ) ( _1380_ CLK ) ( _1381_ CLK ) ( _1386_ CLK )
+ ( _1392_ CLK ) ( _1393_ CLK ) ( _1394_ CLK ) ( _1395_ CLK ) ( _1396_ CLK ) ( clkbuf_4_1_0_wb_clk_i Z ) + USE CLOCK
+ + ROUTED Metal2 ( 19600 223440 ) ( * 246960 )
+ NEW Metal2 ( 49840 252560 ) ( 50960 * )
+ NEW Metal2 ( 50960 234640 ) ( * 252560 )
+ NEW Metal3 ( 19600 234640 ) ( 50960 * )
+ NEW Metal3 ( 50960 254800 ) ( 57680 * )
+ NEW Metal2 ( 50960 252560 ) ( * 254800 )
+ NEW Metal2 ( 59920 233520 ) ( * 234640 )
+ NEW Metal3 ( 50960 234640 ) ( 59920 * )
+ NEW Metal2 ( 66640 223440 ) ( * 234640 )
+ NEW Metal3 ( 59920 234640 ) ( 66640 * )
+ NEW Metal2 ( 64400 208880 ) ( * 223440 )
+ NEW Metal2 ( 64400 223440 ) ( 66640 * )
+ NEW Metal2 ( 33040 201600 ) ( * 234640 )
+ NEW Metal2 ( 33040 201600 ) ( 34160 * )
+ NEW Metal2 ( 34160 199920 ) ( * 201600 )
+ NEW Metal2 ( 150640 254800 ) ( * 262640 )
+ NEW Metal3 ( 143920 254800 ) ( 150640 * )
+ NEW Metal2 ( 149520 239120 ) ( * 254800 )
+ NEW Metal2 ( 149520 254800 ) ( 150640 * )
+ NEW Metal2 ( 142800 240240 ) ( 143920 * )
+ NEW Metal2 ( 143920 240240 ) ( * 254800 )
+ NEW Metal2 ( 139440 215600 ) ( * 240240 )
+ NEW Metal2 ( 139440 240240 ) ( 142800 * )
+ NEW Metal2 ( 140560 208880 ) ( * 215600 )
+ NEW Metal2 ( 139440 215600 ) ( 140560 * )
+ NEW Metal2 ( 136080 208880 ) ( * 210000 )
+ NEW Metal1 ( 136080 210000 ) ( 140560 * )
+ NEW Metal3 ( 104720 215600 ) ( 133840 * )
+ NEW Metal2 ( 133840 210000 ) ( * 215600 )
+ NEW Metal2 ( 133840 210000 ) ( 136080 * )
+ NEW Metal3 ( 98000 215600 ) ( 104720 * )
+ NEW Metal2 ( 89040 261520 ) ( 90160 * )
+ NEW Metal2 ( 89040 215600 ) ( * 261520 )
+ NEW Metal3 ( 89040 215600 ) ( 98000 * )
+ NEW Metal3 ( 66640 234640 ) ( 89040 * )
+ NEW Metal2 ( 136080 198800 ) ( * 208880 )
+ NEW Metal3 ( 170800 262640 ) ( 177520 * )
+ NEW Metal3 ( 150640 262640 ) ( 170800 * )
+ NEW Metal1 ( 19600 223440 ) Via1_HV
+ NEW Metal1 ( 19600 246960 ) Via1_HV
+ NEW Metal1 ( 49840 252560 ) Via1_VV
+ NEW Metal2 ( 50960 234640 ) Via2_VH
+ NEW Metal2 ( 19600 234640 ) Via2_VH
+ NEW Metal1 ( 57680 254800 ) Via1_HV
+ NEW Metal2 ( 57680 254800 ) Via2_VH
+ NEW Metal2 ( 50960 254800 ) Via2_VH
+ NEW Metal1 ( 59920 233520 ) Via1_VV
+ NEW Metal2 ( 59920 234640 ) Via2_VH
+ NEW Metal1 ( 66640 223440 ) Via1_HV
+ NEW Metal2 ( 66640 234640 ) Via2_VH
+ NEW Metal1 ( 64400 208880 ) Via1_VV
+ NEW Metal2 ( 33040 234640 ) Via2_VH
+ NEW Metal1 ( 34160 199920 ) Via1_HV
+ NEW Metal1 ( 150640 254800 ) Via1_HV
+ NEW Metal2 ( 150640 262640 ) Via2_VH
+ NEW Metal1 ( 143920 254800 ) Via1_VV
+ NEW Metal2 ( 143920 254800 ) Via2_VH
+ NEW Metal2 ( 150640 254800 ) Via2_VH
+ NEW Metal1 ( 149520 239120 ) Via1_HV
+ NEW Metal1 ( 142800 240240 ) Via1_VV
+ NEW Metal1 ( 139440 215600 ) Via1_HV
+ NEW Metal1 ( 140560 208880 ) Via1_VV
+ NEW Metal1 ( 136080 208880 ) Via1_VV
+ NEW Metal1 ( 136080 210000 ) Via1_HV
+ NEW Metal1 ( 140560 210000 ) Via1_HV
+ NEW Metal1 ( 104720 215600 ) Via1_HV
+ NEW Metal2 ( 104720 215600 ) Via2_VH
+ NEW Metal2 ( 133840 215600 ) Via2_VH
+ NEW Metal1 ( 98000 215600 ) Via1_VV
+ NEW Metal2 ( 98000 215600 ) Via2_VH
+ NEW Metal1 ( 90160 261520 ) Via1_VV
+ NEW Metal2 ( 89040 215600 ) Via2_VH
+ NEW Metal2 ( 89040 234640 ) Via2_VH
+ NEW Metal1 ( 136080 198800 ) Via1_HV
+ NEW Metal1 ( 170800 262640 ) Via1_VV
+ NEW Metal2 ( 170800 262640 ) Via2_VH
+ NEW Metal1 ( 177520 262640 ) Via1_HV
+ NEW Metal2 ( 177520 262640 ) Via2_VH
+ NEW Metal2 ( 19600 234640 ) RECT ( -280 -1040 280 0 )
+ NEW Metal2 ( 57680 254800 ) RECT ( -280 -660 280 0 )
+ NEW Metal3 ( 33040 234640 ) RECT ( -1040 -280 0 280 )
+ NEW Metal2 ( 143920 254800 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 150640 254800 ) RECT ( -280 -1040 280 0 )
+ NEW Metal2 ( 140560 210000 ) RECT ( -280 -1040 280 0 )
+ NEW Metal2 ( 104720 215600 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 98000 215600 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 89040 234640 ) RECT ( -280 -1040 280 0 )
+ NEW Metal2 ( 170800 262640 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 177520 262640 ) RECT ( -280 -660 280 0 ) ;
+ - clknet_4_2_0_wb_clk_i ( ANTENNA__1438__CLK I ) ( ANTENNA__1437__CLK I ) ( ANTENNA__1436__CLK I ) ( ANTENNA__1435__CLK I ) ( ANTENNA__1434__CLK I ) ( ANTENNA__1433__CLK I ) ( ANTENNA__1432__CLK I )
+ ( ANTENNA__1431__CLK I ) ( ANTENNA__1384__CLK I ) ( ANTENNA__1366__CLK I ) ( _1366_ CLK ) ( _1384_ CLK ) ( _1431_ CLK ) ( _1432_ CLK ) ( _1433_ CLK )
+ ( _1434_ CLK ) ( _1435_ CLK ) ( _1436_ CLK ) ( _1437_ CLK ) ( _1438_ CLK ) ( clkbuf_4_2_0_wb_clk_i Z ) + USE CLOCK
+ + ROUTED Metal2 ( 296240 90160 ) ( 297360 * )
+ NEW Metal3 ( 258160 90160 ) ( 296240 * )
+ NEW Metal3 ( 254800 90160 ) ( 258160 * )
+ NEW Metal3 ( 249200 90160 ) ( 254800 * )
+ NEW Metal3 ( 239120 90160 ) ( 249200 * )
+ NEW Metal2 ( 242480 90160 ) ( * 104720 )
+ NEW Metal3 ( 224560 98000 ) ( 242480 * )
+ NEW Metal2 ( 255920 119280 ) ( * 120400 )
+ NEW Metal2 ( 255920 119280 ) ( 258160 * )
+ NEW Metal2 ( 258160 90160 ) ( * 119280 )
+ NEW Metal2 ( 255920 120400 ) ( * 129360 )
+ NEW Metal2 ( 217840 127120 ) ( 218960 * )
+ NEW Metal2 ( 217840 98000 ) ( * 127120 )
+ NEW Metal3 ( 217840 98000 ) ( 224560 * )
+ NEW Metal2 ( 220080 127120 ) ( * 137200 )
+ NEW Metal2 ( 218960 127120 ) ( 220080 * )
+ NEW Metal2 ( 206640 90160 ) ( * 98000 )
+ NEW Metal3 ( 206640 98000 ) ( 217840 * )
+ NEW Metal3 ( 203280 121520 ) ( 217840 * )
+ NEW Metal3 ( 220080 133840 ) ( 233520 * )
+ NEW Metal3 ( 271600 168560 ) ( 276080 * )
+ NEW Metal2 ( 254800 83440 ) ( * 90160 )
+ NEW Metal2 ( 296240 83440 ) ( * 90160 )
+ NEW Metal2 ( 246960 151760 ) ( * 168560 )
+ NEW Metal3 ( 246960 168560 ) ( 258160 * )
+ NEW Metal3 ( 233520 151760 ) ( 246960 * )
+ NEW Metal2 ( 226800 151760 ) ( * 160720 )
+ NEW Metal3 ( 226800 151760 ) ( 233520 * )
+ NEW Metal3 ( 215600 160720 ) ( 226800 * )
+ NEW Metal2 ( 212240 160720 ) ( * 168560 )
+ NEW Metal3 ( 212240 160720 ) ( 215600 * )
+ NEW Metal2 ( 233520 133840 ) ( * 151760 )
+ NEW Metal3 ( 258160 168560 ) ( 271600 * )
+ NEW Metal1 ( 254800 83440 ) Via1_VV
+ NEW Metal1 ( 296240 83440 ) Via1_VV
+ NEW Metal1 ( 297360 90160 ) Via1_HV
+ NEW Metal1 ( 258160 90160 ) Via1_HV
+ NEW Metal2 ( 258160 90160 ) Via2_VH
+ NEW Metal2 ( 296240 90160 ) Via2_VH
+ NEW Metal2 ( 254800 90160 ) Via2_VH
+ NEW Metal1 ( 249200 90160 ) Via1_VV
+ NEW Metal2 ( 249200 90160 ) Via2_VH
+ NEW Metal1 ( 239120 90160 ) Via1_VV
+ NEW Metal2 ( 239120 90160 ) Via2_VH
+ NEW Metal1 ( 242480 104720 ) Via1_VV
+ NEW Metal2 ( 242480 90160 ) Via2_VH
+ NEW Metal1 ( 224560 98000 ) Via1_HV
+ NEW Metal2 ( 224560 98000 ) Via2_VH
+ NEW Metal2 ( 242480 98000 ) Via2_VH
+ NEW Metal1 ( 255920 120400 ) Via1_VV
+ NEW Metal1 ( 255920 129360 ) Via1_HV
+ NEW Metal1 ( 218960 127120 ) Via1_VV
+ NEW Metal2 ( 217840 98000 ) Via2_VH
+ NEW Metal1 ( 220080 137200 ) Via1_HV
+ NEW Metal1 ( 206640 90160 ) Via1_HV
+ NEW Metal2 ( 206640 98000 ) Via2_VH
+ NEW Metal1 ( 203280 121520 ) Via1_HV
+ NEW Metal2 ( 203280 121520 ) Via2_VH
+ NEW Metal2 ( 217840 121520 ) Via2_VH
+ NEW Metal2 ( 233520 133840 ) Via2_VH
+ NEW Metal2 ( 220080 133840 ) Via2_VH
+ NEW Metal1 ( 271600 168560 ) Via1_VV
+ NEW Metal2 ( 271600 168560 ) Via2_VH
+ NEW Metal1 ( 276080 168560 ) Via1_HV
+ NEW Metal2 ( 276080 168560 ) Via2_VH
+ NEW Metal1 ( 258160 168560 ) Via1_VV
+ NEW Metal2 ( 258160 168560 ) Via2_VH
+ NEW Metal1 ( 246960 151760 ) Via1_HV
+ NEW Metal2 ( 246960 168560 ) Via2_VH
+ NEW Metal2 ( 233520 151760 ) Via2_VH
+ NEW Metal2 ( 246960 151760 ) Via2_VH
+ NEW Metal1 ( 226800 160720 ) Via1_HV
+ NEW Metal2 ( 226800 151760 ) Via2_VH
+ NEW Metal1 ( 215600 160720 ) Via1_VV
+ NEW Metal2 ( 215600 160720 ) Via2_VH
+ NEW Metal2 ( 226800 160720 ) Via2_VH
+ NEW Metal1 ( 212240 168560 ) Via1_HV
+ NEW Metal2 ( 212240 160720 ) Via2_VH
+ NEW Metal2 ( 258160 90160 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 296240 90160 ) RECT ( -280 -1040 280 0 )
+ NEW Metal2 ( 249200 90160 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 239120 90160 ) RECT ( -280 -660 280 0 )
+ NEW Metal3 ( 242480 90160 ) RECT ( -1040 -280 0 280 )
+ NEW Metal2 ( 224560 98000 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 242480 98000 ) RECT ( -280 -1040 280 0 )
+ NEW Metal2 ( 203280 121520 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 217840 121520 ) RECT ( -280 -1040 280 0 )
+ NEW Metal2 ( 220080 133840 ) RECT ( -280 -1040 280 0 )
+ NEW Metal2 ( 271600 168560 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 276080 168560 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 258160 168560 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 246960 151760 ) RECT ( -280 0 280 1040 )
+ NEW Metal2 ( 215600 160720 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 226800 160720 ) RECT ( -280 -1040 280 0 ) ;
+ - clknet_4_3_0_wb_clk_i ( ANTENNA__1440__CLK I ) ( ANTENNA__1439__CLK I ) ( ANTENNA__1419__CLK I ) ( ANTENNA__1415__CLK I ) ( ANTENNA__1414__CLK I ) ( ANTENNA__1412__CLK I ) ( ANTENNA__1411__CLK I )
+ ( ANTENNA__1377__CLK I ) ( ANTENNA__1376__CLK I ) ( ANTENNA__1375__CLK I ) ( _1375_ CLK ) ( _1376_ CLK ) ( _1377_ CLK ) ( _1411_ CLK ) ( _1412_ CLK )
+ ( _1414_ CLK ) ( _1415_ CLK ) ( _1419_ CLK ) ( _1439_ CLK ) ( _1440_ CLK ) ( clkbuf_4_3_0_wb_clk_i Z ) + USE CLOCK
+ + ROUTED Metal2 ( 277200 234640 ) ( * 236880 )
+ NEW Metal3 ( 277200 234640 ) ( 286160 * )
+ NEW Metal2 ( 286160 261520 ) ( 287280 * )
+ NEW Metal2 ( 287280 234640 ) ( * 261520 )
+ NEW Metal2 ( 286160 234640 ) ( 287280 * )
+ NEW Metal2 ( 290640 261520 ) ( * 262640 )
+ NEW Metal2 ( 287280 261520 ) ( 290640 * )
+ NEW Metal2 ( 294000 233520 ) ( * 234640 )
+ NEW Metal3 ( 286160 234640 ) ( 294000 * )
+ NEW Metal2 ( 299600 231280 ) ( * 234640 )
+ NEW Metal3 ( 294000 234640 ) ( 299600 * )
+ NEW Metal2 ( 286160 201600 ) ( * 234640 )
+ NEW Metal2 ( 287280 199920 ) ( 288400 * )
+ NEW Metal2 ( 288400 193200 ) ( * 199920 )
+ NEW Metal2 ( 286160 201600 ) ( 287280 * )
+ NEW Metal2 ( 287280 199920 ) ( * 201600 )
+ NEW Metal2 ( 328720 239120 ) ( * 245840 )
+ NEW Metal2 ( 325360 245840 ) ( 328720 * )
+ NEW Metal2 ( 328720 234640 ) ( * 239120 )
+ NEW Metal2 ( 329840 223440 ) ( * 234640 )
+ NEW Metal2 ( 328720 234640 ) ( 329840 * )
+ NEW Metal2 ( 326480 217840 ) ( * 223440 )
+ NEW Metal2 ( 326480 223440 ) ( 329840 * )
+ NEW Metal3 ( 299600 234640 ) ( 328720 * )
+ NEW Metal3 ( 218960 262640 ) ( 257040 * )
+ NEW Metal2 ( 251440 255920 ) ( * 262640 )
+ NEW Metal2 ( 257040 254800 ) ( * 262640 )
+ NEW Metal2 ( 244720 239120 ) ( * 262640 )
+ NEW Metal2 ( 253680 224560 ) ( * 255920 )
+ NEW Metal2 ( 251440 255920 ) ( 253680 * )
+ NEW Metal3 ( 253680 223440 ) ( 259280 * )
+ NEW Metal2 ( 253680 223440 ) ( * 224560 )
+ NEW Metal2 ( 253680 208880 ) ( * 223440 )
+ NEW Metal3 ( 253680 201040 ) ( 260400 * )
+ NEW Metal2 ( 253680 201040 ) ( * 208880 )
+ NEW Metal2 ( 230160 192080 ) ( * 201040 )
+ NEW Metal3 ( 230160 201040 ) ( 253680 * )
+ NEW Metal3 ( 253680 234640 ) ( 277200 * )
+ NEW Metal1 ( 277200 236880 ) Via1_VV
+ NEW Metal2 ( 277200 234640 ) Via2_VH
+ NEW Metal2 ( 286160 234640 ) Via2_VH
+ NEW Metal1 ( 286160 261520 ) Via1_VV
+ NEW Metal1 ( 290640 262640 ) Via1_HV
+ NEW Metal1 ( 294000 233520 ) Via1_VV
+ NEW Metal2 ( 294000 234640 ) Via2_VH
+ NEW Metal1 ( 299600 231280 ) Via1_HV
+ NEW Metal2 ( 299600 234640 ) Via2_VH
+ NEW Metal1 ( 287280 199920 ) Via1_HV
+ NEW Metal1 ( 288400 193200 ) Via1_VV
+ NEW Metal1 ( 328720 239120 ) Via1_HV
+ NEW Metal1 ( 325360 245840 ) Via1_VV
+ NEW Metal2 ( 328720 234640 ) Via2_VH
+ NEW Metal1 ( 329840 223440 ) Via1_HV
+ NEW Metal1 ( 326480 217840 ) Via1_VV
+ NEW Metal1 ( 257040 262640 ) Via1_VV
+ NEW Metal2 ( 257040 262640 ) Via2_VH
+ NEW Metal1 ( 218960 262640 ) Via1_HV
+ NEW Metal2 ( 218960 262640 ) Via2_VH
+ NEW Metal1 ( 251440 255920 ) Via1_VV
+ NEW Metal2 ( 251440 262640 ) Via2_VH
+ NEW Metal1 ( 257040 254800 ) Via1_HV
+ NEW Metal1 ( 244720 239120 ) Via1_HV
+ NEW Metal2 ( 244720 262640 ) Via2_VH
+ NEW Metal1 ( 253680 224560 ) Via1_VV
+ NEW Metal1 ( 259280 223440 ) Via1_HV
+ NEW Metal2 ( 259280 223440 ) Via2_VH
+ NEW Metal2 ( 253680 223440 ) Via2_VH
+ NEW Metal2 ( 253680 234640 ) Via2_VH
+ NEW Metal1 ( 253680 208880 ) Via1_HV
+ NEW Metal1 ( 260400 201040 ) Via1_VV
+ NEW Metal2 ( 260400 201040 ) Via2_VH
+ NEW Metal2 ( 253680 201040 ) Via2_VH
+ NEW Metal1 ( 230160 192080 ) Via1_HV
+ NEW Metal2 ( 230160 201040 ) Via2_VH
+ NEW Metal2 ( 257040 262640 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 218960 262640 ) RECT ( -280 -660 280 0 )
+ NEW Metal3 ( 251440 262640 ) RECT ( -1040 -280 0 280 )
+ NEW Metal3 ( 244720 262640 ) RECT ( -1040 -280 0 280 )
+ NEW Metal2 ( 259280 223440 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 253680 234640 ) RECT ( -280 -1040 280 0 )
+ NEW Metal2 ( 260400 201040 ) RECT ( -280 -660 280 0 ) ;
+ - clknet_4_4_0_wb_clk_i ( ANTENNA__1410__CLK I ) ( ANTENNA__1409__CLK I ) ( ANTENNA__1408__CLK I ) ( ANTENNA__1401__CLK I ) ( ANTENNA__1400__CLK I ) ( ANTENNA__1399__CLK I ) ( ANTENNA__1398__CLK I )
+ ( ANTENNA__1397__CLK I ) ( _1397_ CLK ) ( _1398_ CLK ) ( _1399_ CLK ) ( _1400_ CLK ) ( _1401_ CLK ) ( _1408_ CLK ) ( _1409_ CLK )
+ ( _1410_ CLK ) ( clkbuf_4_4_0_wb_clk_i Z ) + USE CLOCK
+ + ROUTED Metal2 ( 43120 278320 ) ( * 280560 )
+ NEW Metal3 ( 43120 280560 ) ( 75600 * )
+ NEW Metal2 ( 56560 280560 ) ( * 299600 )
+ NEW Metal2 ( 53200 299600 ) ( 56560 * )
+ NEW Metal3 ( 19600 301840 ) ( 53200 * )
+ NEW Metal2 ( 19600 301840 ) ( * 325360 )
+ NEW Metal2 ( 53200 299600 ) ( * 324240 )
+ NEW Metal3 ( 123760 309680 ) ( 157360 * )
+ NEW Metal3 ( 118160 285040 ) ( 123760 * )
+ NEW Metal2 ( 123760 285040 ) ( * 309680 )
+ NEW Metal2 ( 121520 271600 ) ( * 285040 )
+ NEW Metal3 ( 121520 270480 ) ( 137200 * )
+ NEW Metal2 ( 121520 270480 ) ( * 271600 )
+ NEW Metal3 ( 117040 270480 ) ( 121520 * )
+ NEW Metal3 ( 137200 270480 ) ( 151760 * )
+ NEW Metal2 ( 146160 262640 ) ( * 270480 )
+ NEW Metal2 ( 85680 285040 ) ( * 286160 )
+ NEW Metal3 ( 85680 285040 ) ( 118160 * )
+ NEW Metal2 ( 84560 270480 ) ( * 285040 )
+ NEW Metal2 ( 84560 285040 ) ( 85680 * )
+ NEW Metal3 ( 75600 280560 ) ( 84560 * )
+ NEW Metal2 ( 123760 309680 ) ( * 324240 )
+ NEW Metal2 ( 151760 264880 ) ( * 270480 )
+ NEW Metal1 ( 75600 280560 ) Via1_VV
+ NEW Metal2 ( 75600 280560 ) Via2_VH
+ NEW Metal1 ( 43120 278320 ) Via1_HV
+ NEW Metal2 ( 43120 280560 ) Via2_VH
+ NEW Metal1 ( 56560 299600 ) Via1_VV
+ NEW Metal2 ( 56560 280560 ) Via2_VH
+ NEW Metal1 ( 19600 301840 ) Via1_HV
+ NEW Metal2 ( 19600 301840 ) Via2_VH
+ NEW Metal2 ( 53200 301840 ) Via2_VH
+ NEW Metal1 ( 53200 324240 ) Via1_VV
+ NEW Metal1 ( 19600 325360 ) Via1_HV
+ NEW Metal1 ( 123760 309680 ) Via1_VV
+ NEW Metal2 ( 123760 309680 ) Via2_VH
+ NEW Metal1 ( 157360 309680 ) Via1_HV
+ NEW Metal2 ( 157360 309680 ) Via2_VH
+ NEW Metal1 ( 118160 285040 ) Via1_VV
+ NEW Metal2 ( 118160 285040 ) Via2_VH
+ NEW Metal2 ( 123760 285040 ) Via2_VH
+ NEW Metal1 ( 121520 271600 ) Via1_VV
+ NEW Metal2 ( 121520 285040 ) Via2_VH
+ NEW Metal1 ( 137200 270480 ) Via1_HV
+ NEW Metal2 ( 137200 270480 ) Via2_VH
+ NEW Metal2 ( 121520 270480 ) Via2_VH
+ NEW Metal1 ( 117040 270480 ) Via1_VV
+ NEW Metal2 ( 117040 270480 ) Via2_VH
+ NEW Metal2 ( 151760 270480 ) Via2_VH
+ NEW Metal1 ( 146160 262640 ) Via1_HV
+ NEW Metal2 ( 146160 270480 ) Via2_VH
+ NEW Metal1 ( 85680 286160 ) Via1_HV
+ NEW Metal2 ( 85680 285040 ) Via2_VH
+ NEW Metal1 ( 84560 270480 ) Via1_HV
+ NEW Metal2 ( 84560 280560 ) Via2_VH
+ NEW Metal1 ( 123760 324240 ) Via1_HV
+ NEW Metal1 ( 151760 264880 ) Via1_VV
+ NEW Metal2 ( 75600 280560 ) RECT ( -280 -660 280 0 )
+ NEW Metal3 ( 56560 280560 ) RECT ( -1040 -280 0 280 )
+ NEW Metal2 ( 19600 301840 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 53200 301840 ) RECT ( -280 -1040 280 0 )
+ NEW Metal2 ( 123760 309680 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 157360 309680 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 118160 285040 ) RECT ( -280 -660 280 0 )
+ NEW Metal3 ( 121520 285040 ) RECT ( -1040 -280 0 280 )
+ NEW Metal2 ( 137200 270480 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 117040 270480 ) RECT ( -280 -660 280 0 )
+ NEW Metal3 ( 146160 270480 ) RECT ( -1040 -280 0 280 )
+ NEW Metal2 ( 84560 280560 ) RECT ( -280 -1040 280 0 ) ;
+ - clknet_4_5_0_wb_clk_i ( ANTENNA__1494__CLK I ) ( ANTENNA__1492__CLK I ) ( ANTENNA__1407__CLK I ) ( ANTENNA__1406__CLK I ) ( ANTENNA__1405__CLK I ) ( ANTENNA__1404__CLK I ) ( ANTENNA__1403__CLK I )
+ ( ANTENNA__1402__CLK I ) ( _1402_ CLK ) ( _1403_ CLK ) ( _1404_ CLK ) ( _1405_ CLK ) ( _1406_ CLK ) ( _1407_ CLK ) ( _1492_ CLK )
+ ( _1494_ CLK ) ( clkbuf_4_5_0_wb_clk_i Z ) + USE CLOCK
+ + ROUTED Metal2 ( 57680 372400 ) ( * 378000 )
+ NEW Metal3 ( 27440 372400 ) ( 57680 * )
+ NEW Metal2 ( 55440 343280 ) ( * 346640 )
+ NEW Metal2 ( 55440 346640 ) ( 57680 * )
+ NEW Metal2 ( 57680 346640 ) ( * 372400 )
+ NEW Metal3 ( 22960 341040 ) ( 55440 * )
+ NEW Metal2 ( 55440 341040 ) ( * 343280 )
+ NEW Metal2 ( 166320 333200 ) ( 170800 * )
+ NEW Metal3 ( 143920 339920 ) ( 166320 * )
+ NEW Metal2 ( 166320 333200 ) ( * 339920 )
+ NEW Metal2 ( 157360 339920 ) ( * 355600 )
+ NEW Metal2 ( 152880 355600 ) ( * 356720 )
+ NEW Metal2 ( 152880 355600 ) ( 157360 * )
+ NEW Metal2 ( 151760 380240 ) ( 152880 * )
+ NEW Metal2 ( 152880 356720 ) ( * 380240 )
+ NEW Metal3 ( 145040 380240 ) ( 151760 * )
+ NEW Metal3 ( 124880 365680 ) ( 150640 * )
+ NEW Metal2 ( 150640 365680 ) ( 152880 * )
+ NEW Metal2 ( 96880 365680 ) ( * 371280 )
+ NEW Metal3 ( 96880 365680 ) ( 124880 * )
+ NEW Metal2 ( 92400 364560 ) ( * 365680 )
+ NEW Metal3 ( 92400 365680 ) ( 96880 * )
+ NEW Metal2 ( 90160 365680 ) ( * 372400 )
+ NEW Metal2 ( 90160 365680 ) ( 92400 * )
+ NEW Metal2 ( 141680 380240 ) ( * 409360 )
+ NEW Metal3 ( 141680 380240 ) ( 145040 * )
+ NEW Metal2 ( 147280 409360 ) ( * 411600 )
+ NEW Metal2 ( 141680 409360 ) ( 147280 * )
+ NEW Metal3 ( 57680 372400 ) ( 90160 * )
+ NEW Metal1 ( 57680 378000 ) Via1_VV
+ NEW Metal2 ( 57680 372400 ) Via2_VH
+ NEW Metal1 ( 27440 372400 ) Via1_HV
+ NEW Metal2 ( 27440 372400 ) Via2_VH
+ NEW Metal1 ( 55440 343280 ) Via1_VV
+ NEW Metal1 ( 22960 341040 ) Via1_HV
+ NEW Metal2 ( 22960 341040 ) Via2_VH
+ NEW Metal2 ( 55440 341040 ) Via2_VH
+ NEW Metal1 ( 166320 333200 ) Via1_HV
+ NEW Metal1 ( 170800 333200 ) Via1_VV
+ NEW Metal1 ( 143920 339920 ) Via1_HV
+ NEW Metal2 ( 143920 339920 ) Via2_VH
+ NEW Metal2 ( 166320 339920 ) Via2_VH
+ NEW Metal1 ( 157360 355600 ) Via1_VV
+ NEW Metal2 ( 157360 339920 ) Via2_VH
+ NEW Metal1 ( 152880 356720 ) Via1_HV
+ NEW Metal1 ( 151760 380240 ) Via1_HV
+ NEW Metal1 ( 145040 380240 ) Via1_VV
+ NEW Metal2 ( 145040 380240 ) Via2_VH
+ NEW Metal2 ( 151760 380240 ) Via2_VH
+ NEW Metal1 ( 124880 365680 ) Via1_VV
+ NEW Metal2 ( 124880 365680 ) Via2_VH
+ NEW Metal2 ( 150640 365680 ) Via2_VH
+ NEW Metal1 ( 96880 371280 ) Via1_VV
+ NEW Metal2 ( 96880 365680 ) Via2_VH
+ NEW Metal1 ( 92400 364560 ) Via1_HV
+ NEW Metal2 ( 92400 365680 ) Via2_VH
+ NEW Metal1 ( 90160 372400 ) Via1_HV
+ NEW Metal2 ( 90160 372400 ) Via2_VH
+ NEW Metal1 ( 141680 409360 ) Via1_VV
+ NEW Metal2 ( 141680 380240 ) Via2_VH
+ NEW Metal1 ( 147280 411600 ) Via1_HV
+ NEW Metal2 ( 27440 372400 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 22960 341040 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 143920 339920 ) RECT ( -280 -660 280 0 )
+ NEW Metal3 ( 157360 339920 ) RECT ( -1040 -280 0 280 )
+ NEW Metal2 ( 145040 380240 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 151760 380240 ) RECT ( -280 -1040 280 0 )
+ NEW Metal2 ( 124880 365680 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 90160 372400 ) RECT ( -280 -1040 280 0 ) ;
+ - clknet_4_6_0_wb_clk_i ( ANTENNA__1510__CLK I ) ( ANTENNA__1509__CLK I ) ( ANTENNA__1496__CLK I ) ( ANTENNA__1495__CLK I ) ( ANTENNA__1420__CLK I ) ( ANTENNA__1418__CLK I ) ( ANTENNA__1417__CLK I )
+ ( ANTENNA__1413__CLK I ) ( ANTENNA__1372__CLK I ) ( _1372_ CLK ) ( _1413_ CLK ) ( _1417_ CLK ) ( _1418_ CLK ) ( _1420_ CLK ) ( _1495_ CLK )
+ ( _1496_ CLK ) ( _1509_ CLK ) ( _1510_ CLK ) ( clkbuf_4_6_0_wb_clk_i Z ) + USE CLOCK
+ + ROUTED Metal2 ( 317520 270480 ) ( * 277200 )
+ NEW Metal3 ( 255920 277200 ) ( 317520 * )
+ NEW Metal2 ( 257040 277200 ) ( * 286160 )
+ NEW Metal2 ( 255920 277200 ) ( 257040 * )
+ NEW Metal2 ( 255920 292880 ) ( 257040 * )
+ NEW Metal2 ( 257040 286160 ) ( * 292880 )
+ NEW Metal3 ( 240240 301840 ) ( 255920 * )
+ NEW Metal2 ( 255920 292880 ) ( * 301840 )
+ NEW Metal3 ( 233520 301840 ) ( 240240 * )
+ NEW Metal2 ( 245840 301840 ) ( * 308560 )
+ NEW Metal2 ( 269360 301840 ) ( * 317520 )
+ NEW Metal3 ( 255920 301840 ) ( 269360 * )
+ NEW Metal3 ( 223440 286160 ) ( 233520 * )
+ NEW Metal2 ( 233520 286160 ) ( * 301840 )
+ NEW Metal2 ( 240240 301840 ) ( * 319200 )
+ NEW Metal2 ( 240240 330960 ) ( * 334320 )
+ NEW Metal2 ( 240240 330960 ) ( 241360 * )
+ NEW Metal2 ( 241360 319200 ) ( * 330960 )
+ NEW Metal2 ( 240240 319200 ) ( 241360 * )
+ NEW Metal3 ( 240240 339920 ) ( 249200 * )
+ NEW Metal2 ( 240240 334320 ) ( * 339920 )
+ NEW Metal2 ( 245840 339920 ) ( * 348880 )
+ NEW Metal2 ( 249200 339920 ) ( * 355600 )
+ NEW Metal2 ( 257040 339920 ) ( * 341040 )
+ NEW Metal3 ( 249200 339920 ) ( 257040 * )
+ NEW Metal2 ( 189840 286160 ) ( * 299600 )
+ NEW Metal2 ( 185360 299600 ) ( * 301840 )
+ NEW Metal2 ( 185360 299600 ) ( 189840 * )
+ NEW Metal2 ( 189840 308560 ) ( 190960 * )
+ NEW Metal2 ( 189840 299600 ) ( * 308560 )
+ NEW Metal2 ( 185360 301840 ) ( * 317520 )
+ NEW Metal3 ( 189840 286160 ) ( 223440 * )
+ NEW Metal2 ( 317520 270480 ) ( 320880 * )
+ NEW Metal1 ( 317520 277200 ) Via1_VV
+ NEW Metal1 ( 255920 277200 ) Via1_VV
+ NEW Metal2 ( 255920 277200 ) Via2_VH
+ NEW Metal2 ( 317520 277200 ) Via2_VH
+ NEW Metal1 ( 257040 286160 ) Via1_HV
+ NEW Metal1 ( 255920 292880 ) Via1_VV
+ NEW Metal1 ( 240240 301840 ) Via1_HV
+ NEW Metal2 ( 240240 301840 ) Via2_VH
+ NEW Metal2 ( 255920 301840 ) Via2_VH
+ NEW Metal1 ( 233520 301840 ) Via1_VV
+ NEW Metal2 ( 233520 301840 ) Via2_VH
+ NEW Metal1 ( 245840 308560 ) Via1_VV
+ NEW Metal2 ( 245840 301840 ) Via2_VH
+ NEW Metal1 ( 269360 317520 ) Via1_HV
+ NEW Metal2 ( 269360 301840 ) Via2_VH
+ NEW Metal1 ( 223440 286160 ) Via1_HV
+ NEW Metal2 ( 223440 286160 ) Via2_VH
+ NEW Metal2 ( 233520 286160 ) Via2_VH
+ NEW Metal1 ( 240240 334320 ) Via1_HV
+ NEW Metal1 ( 249200 339920 ) Via1_VV
+ NEW Metal2 ( 249200 339920 ) Via2_VH
+ NEW Metal2 ( 240240 339920 ) Via2_VH
+ NEW Metal1 ( 245840 348880 ) Via1_HV
+ NEW Metal2 ( 245840 339920 ) Via2_VH
+ NEW Metal1 ( 249200 355600 ) Via1_VV
+ NEW Metal1 ( 257040 341040 ) Via1_HV
+ NEW Metal2 ( 257040 339920 ) Via2_VH
+ NEW Metal1 ( 189840 299600 ) Via1_VV
+ NEW Metal2 ( 189840 286160 ) Via2_VH
+ NEW Metal1 ( 185360 301840 ) Via1_HV
+ NEW Metal1 ( 190960 308560 ) Via1_VV
+ NEW Metal1 ( 185360 317520 ) Via1_HV
+ NEW Metal1 ( 320880 270480 ) Via1_HV
+ NEW Metal2 ( 255920 277200 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 317520 277200 ) RECT ( -280 -1040 280 0 )
+ NEW Metal2 ( 240240 301840 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 233520 301840 ) RECT ( -280 -660 280 0 )
+ NEW Metal3 ( 245840 301840 ) RECT ( -1040 -280 0 280 )
+ NEW Metal2 ( 223440 286160 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 249200 339920 ) RECT ( -280 -660 280 0 )
+ NEW Metal3 ( 245840 339920 ) RECT ( -1040 -280 0 280 ) ;
+ - clknet_4_7_0_wb_clk_i ( ANTENNA__1497__CLK I ) ( ANTENNA__1493__CLK I ) ( ANTENNA__1491__CLK I ) ( ANTENNA__1490__CLK I ) ( ANTENNA__1489__CLK I ) ( ANTENNA__1488__CLK I ) ( ANTENNA__1487__CLK I )
+ ( ANTENNA__1486__CLK I ) ( ANTENNA__1484__CLK I ) ( _1484_ CLK ) ( _1486_ CLK ) ( _1487_ CLK ) ( _1488_ CLK ) ( _1489_ CLK ) ( _1490_ CLK )
+ ( _1491_ CLK ) ( _1493_ CLK ) ( _1497_ CLK ) ( clkbuf_4_7_0_wb_clk_i Z ) + USE CLOCK
+ + ROUTED Metal2 ( 261520 482160 ) ( 266000 * )
+ NEW Metal3 ( 250320 459760 ) ( 261520 * )
+ NEW Metal2 ( 261520 459760 ) ( * 482160 )
+ NEW Metal2 ( 236880 453040 ) ( * 459760 )
+ NEW Metal3 ( 236880 459760 ) ( 250320 * )
+ NEW Metal2 ( 240240 442960 ) ( * 453040 )
+ NEW Metal2 ( 236880 453040 ) ( 240240 * )
+ NEW Metal2 ( 217840 458640 ) ( * 459760 )
+ NEW Metal3 ( 217840 459760 ) ( 236880 * )
+ NEW Metal3 ( 202160 453040 ) ( * 454160 )
+ NEW Metal3 ( 202160 454160 ) ( 217840 * )
+ NEW Metal2 ( 217840 454160 ) ( * 458640 )
+ NEW Metal2 ( 231280 355600 ) ( * 356720 )
+ NEW Metal2 ( 234640 355600 ) ( * 362320 )
+ NEW Metal3 ( 231280 355600 ) ( 234640 * )
+ NEW Metal2 ( 234640 362320 ) ( * 379120 )
+ NEW Metal2 ( 222320 355600 ) ( * 395920 )
+ NEW Metal2 ( 221200 419440 ) ( 222320 * )
+ NEW Metal2 ( 222320 395920 ) ( * 419440 )
+ NEW Metal3 ( 222320 409360 ) ( 251440 * )
+ NEW Metal3 ( 251440 409360 ) ( 255920 * )
+ NEW Metal2 ( 255920 406000 ) ( * 409360 )
+ NEW Metal2 ( 259280 409360 ) ( * 419440 )
+ NEW Metal3 ( 255920 409360 ) ( 259280 * )
+ NEW Metal2 ( 236880 428400 ) ( 240240 * )
+ NEW Metal2 ( 236880 409360 ) ( * 428400 )
+ NEW Metal2 ( 240240 428400 ) ( * 442960 )
+ NEW Metal2 ( 199920 442960 ) ( * 449680 )
+ NEW Metal3 ( 169680 442960 ) ( 199920 * )
+ NEW Metal2 ( 199920 449680 ) ( * 453040 )
+ NEW Metal3 ( 199920 453040 ) ( 202160 * )
+ NEW Metal3 ( 160720 355600 ) ( 190960 * )
+ NEW Metal2 ( 160720 348880 ) ( * 355600 )
+ NEW Metal3 ( 190960 355600 ) ( 231280 * )
+ NEW Metal1 ( 261520 482160 ) Via1_VV
+ NEW Metal1 ( 266000 482160 ) Via1_HV
+ NEW Metal1 ( 250320 459760 ) Via1_VV
+ NEW Metal2 ( 250320 459760 ) Via2_VH
+ NEW Metal2 ( 261520 459760 ) Via2_VH
+ NEW Metal1 ( 236880 453040 ) Via1_VV
+ NEW Metal2 ( 236880 459760 ) Via2_VH
+ NEW Metal1 ( 240240 442960 ) Via1_HV
+ NEW Metal1 ( 217840 458640 ) Via1_HV
+ NEW Metal2 ( 217840 459760 ) Via2_VH
+ NEW Metal2 ( 217840 454160 ) Via2_VH
+ NEW Metal1 ( 231280 356720 ) Via1_HV
+ NEW Metal2 ( 231280 355600 ) Via2_VH
+ NEW Metal1 ( 234640 362320 ) Via1_VV
+ NEW Metal2 ( 234640 355600 ) Via2_VH
+ NEW Metal1 ( 234640 379120 ) Via1_HV
+ NEW Metal1 ( 222320 395920 ) Via1_HV
+ NEW Metal2 ( 222320 355600 ) Via2_VH
+ NEW Metal1 ( 221200 419440 ) Via1_HV
+ NEW Metal1 ( 251440 409360 ) Via1_VV
+ NEW Metal2 ( 251440 409360 ) Via2_VH
+ NEW Metal2 ( 222320 409360 ) Via2_VH
+ NEW Metal1 ( 255920 409360 ) Via1_VV
+ NEW Metal2 ( 255920 409360 ) Via2_VH
+ NEW Metal1 ( 255920 406000 ) Via1_VV
+ NEW Metal1 ( 259280 419440 ) Via1_HV
+ NEW Metal2 ( 259280 409360 ) Via2_VH
+ NEW Metal2 ( 236880 409360 ) Via2_VH
+ NEW Metal1 ( 199920 449680 ) Via1_VV
+ NEW Metal2 ( 199920 442960 ) Via2_VH
+ NEW Metal1 ( 169680 442960 ) Via1_HV
+ NEW Metal2 ( 169680 442960 ) Via2_VH
+ NEW Metal2 ( 199920 453040 ) Via2_VH
+ NEW Metal1 ( 190960 355600 ) Via1_VV
+ NEW Metal2 ( 190960 355600 ) Via2_VH
+ NEW Metal2 ( 160720 355600 ) Via2_VH
+ NEW Metal1 ( 160720 348880 ) Via1_HV
+ NEW Metal2 ( 250320 459760 ) RECT ( -280 -660 280 0 )
+ NEW Metal3 ( 222320 355600 ) RECT ( -1040 -280 0 280 )
+ NEW Metal2 ( 251440 409360 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 222320 409360 ) RECT ( -280 -1040 280 0 )
+ NEW Metal2 ( 255920 409360 ) RECT ( -280 -660 280 0 )
+ NEW Metal3 ( 236880 409360 ) RECT ( -1040 -280 0 280 )
+ NEW Metal2 ( 169680 442960 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 190960 355600 ) RECT ( -280 -660 280 0 ) ;
+ - clknet_4_8_0_wb_clk_i ( ANTENNA__1514__CLK I ) ( ANTENNA__1501__CLK I ) ( ANTENNA__1464__CLK I ) ( ANTENNA__1430__CLK I ) ( ANTENNA__1429__CLK I ) ( ANTENNA__1428__CLK I ) ( ANTENNA__1427__CLK I )
+ ( ANTENNA__1426__CLK I ) ( ANTENNA__1425__CLK I ) ( ANTENNA__1424__CLK I ) ( ANTENNA__1423__CLK I ) ( ANTENNA__1422__CLK I ) ( ANTENNA__1421__CLK I ) ( _1421_ CLK ) ( _1422_ CLK )
+ ( _1423_ CLK ) ( _1424_ CLK ) ( _1425_ CLK ) ( _1426_ CLK ) ( _1427_ CLK ) ( _1428_ CLK ) ( _1429_ CLK ) ( _1430_ CLK )
+ ( _1464_ CLK ) ( _1501_ CLK ) ( _1514_ CLK ) ( clkbuf_4_8_0_wb_clk_i Z ) + USE CLOCK
+ + ROUTED Metal2 ( 375760 83440 ) ( * 84000 )
+ NEW Metal3 ( 336560 184240 ) ( 343280 * )
+ NEW Metal2 ( 336560 184240 ) ( * 199920 )
+ NEW Metal2 ( 339920 168560 ) ( * 184240 )
+ NEW Metal2 ( 337680 145040 ) ( * 168560 )
+ NEW Metal2 ( 337680 168560 ) ( 339920 * )
+ NEW Metal2 ( 352240 137200 ) ( * 145040 )
+ NEW Metal3 ( 337680 145040 ) ( 352240 * )
+ NEW Metal3 ( 352240 145040 ) ( 374640 * )
+ NEW Metal2 ( 374640 177520 ) ( * 184240 )
+ NEW Metal3 ( 343280 184240 ) ( 374640 * )
+ NEW Metal2 ( 374640 183120 ) ( 376880 * )
+ NEW Metal2 ( 385840 184240 ) ( * 192080 )
+ NEW Metal3 ( 374640 184240 ) ( 385840 * )
+ NEW Metal3 ( 374640 130480 ) ( 383600 * )
+ NEW Metal2 ( 374640 130480 ) ( * 145040 )
+ NEW Metal2 ( 364560 121520 ) ( * 130480 )
+ NEW Metal3 ( 364560 130480 ) ( 374640 * )
+ NEW Metal2 ( 374640 114800 ) ( * 130480 )
+ NEW Metal2 ( 338800 113680 ) ( * 145040 )
+ NEW Metal2 ( 337680 145040 ) ( 338800 * )
+ NEW Metal2 ( 374640 105840 ) ( * 114800 )
+ NEW Metal3 ( 367920 99120 ) ( 374640 * )
+ NEW Metal2 ( 374640 99120 ) ( * 105840 )
+ NEW Metal2 ( 337680 90160 ) ( 338800 * )
+ NEW Metal2 ( 338800 90160 ) ( * 113680 )
+ NEW Metal2 ( 373520 84000 ) ( 375760 * )
+ NEW Metal2 ( 373520 84000 ) ( * 99120 )
+ NEW Metal2 ( 373520 99120 ) ( 374640 * )
+ NEW Metal2 ( 395920 123760 ) ( 397040 * )
+ NEW Metal2 ( 395920 123760 ) ( * 130480 )
+ NEW Metal3 ( 383600 130480 ) ( 395920 * )
+ NEW Metal2 ( 407120 108080 ) ( * 123760 )
+ NEW Metal3 ( 397040 123760 ) ( 407120 * )
+ NEW Metal2 ( 407120 123760 ) ( 408240 * )
+ NEW Metal2 ( 419440 121520 ) ( * 123760 )
+ NEW Metal3 ( 407120 123760 ) ( 419440 * )
+ NEW Metal2 ( 338800 82320 ) ( * 90160 )
+ NEW Metal3 ( 382480 215600 ) ( 386400 * )
+ NEW Metal2 ( 418320 208880 ) ( 421680 * )
+ NEW Metal2 ( 421680 202160 ) ( * 208880 )
+ NEW Metal3 ( 392560 214480 ) ( 418320 * )
+ NEW Metal2 ( 418320 208880 ) ( * 214480 )
+ NEW Metal3 ( 386400 214480 ) ( * 215600 )
+ NEW Metal3 ( 386400 214480 ) ( 392560 * )
+ NEW Metal2 ( 386960 202160 ) ( * 214480 )
+ NEW Metal2 ( 386960 192080 ) ( 388080 * )
+ NEW Metal2 ( 386960 192080 ) ( * 202160 )
+ NEW Metal2 ( 385840 192080 ) ( 386960 * )
+ NEW Metal3 ( 370160 202160 ) ( 386960 * )
+ NEW Metal1 ( 375760 83440 ) Via1_VV
+ NEW Metal1 ( 338800 82320 ) Via1_HV
+ NEW Metal1 ( 382480 215600 ) Via1_HV
+ NEW Metal2 ( 382480 215600 ) Via2_VH
+ NEW Metal1 ( 370160 202160 ) Via1_VV
+ NEW Metal2 ( 370160 202160 ) Via2_VH
+ NEW Metal1 ( 343280 184240 ) Via1_HV
+ NEW Metal2 ( 343280 184240 ) Via2_VH
+ NEW Metal2 ( 336560 184240 ) Via2_VH
+ NEW Metal1 ( 336560 199920 ) Via1_HV
+ NEW Metal1 ( 339920 168560 ) Via1_HV
+ NEW Metal2 ( 339920 184240 ) Via2_VH
+ NEW Metal1 ( 337680 145040 ) Via1_HV
+ NEW Metal1 ( 352240 137200 ) Via1_HV
+ NEW Metal2 ( 352240 145040 ) Via2_VH
+ NEW Metal2 ( 337680 145040 ) Via2_VH
+ NEW Metal1 ( 374640 145040 ) Via1_VV
+ NEW Metal2 ( 374640 145040 ) Via2_VH
+ NEW Metal1 ( 374640 177520 ) Via1_VV
+ NEW Metal2 ( 374640 184240 ) Via2_VH
+ NEW Metal1 ( 376880 183120 ) Via1_VV
+ NEW Metal2 ( 385840 184240 ) Via2_VH
+ NEW Metal1 ( 383600 130480 ) Via1_VV
+ NEW Metal2 ( 383600 130480 ) Via2_VH
+ NEW Metal2 ( 374640 130480 ) Via2_VH
+ NEW Metal1 ( 364560 121520 ) Via1_HV
+ NEW Metal2 ( 364560 130480 ) Via2_VH
+ NEW Metal1 ( 374640 114800 ) Via1_VV
+ NEW Metal1 ( 338800 113680 ) Via1_HV
+ NEW Metal1 ( 374640 105840 ) Via1_HV
+ NEW Metal1 ( 367920 99120 ) Via1_VV
+ NEW Metal2 ( 367920 99120 ) Via2_VH
+ NEW Metal2 ( 374640 99120 ) Via2_VH
+ NEW Metal1 ( 337680 90160 ) Via1_HV
+ NEW Metal1 ( 397040 123760 ) Via1_VV
+ NEW Metal2 ( 395920 130480 ) Via2_VH
+ NEW Metal1 ( 407120 108080 ) Via1_VV
+ NEW Metal2 ( 407120 123760 ) Via2_VH
+ NEW Metal2 ( 397040 123760 ) Via2_VH
+ NEW Metal1 ( 408240 123760 ) Via1_VV
+ NEW Metal1 ( 419440 121520 ) Via1_HV
+ NEW Metal2 ( 419440 123760 ) Via2_VH
+ NEW Metal1 ( 418320 208880 ) Via1_HV
+ NEW Metal1 ( 421680 202160 ) Via1_VV
+ NEW Metal1 ( 392560 214480 ) Via1_VV
+ NEW Metal2 ( 392560 214480 ) Via2_VH
+ NEW Metal2 ( 418320 214480 ) Via2_VH
+ NEW Metal2 ( 386960 202160 ) Via2_VH
+ NEW Metal2 ( 386960 214480 ) Via2_VH
+ NEW Metal1 ( 388080 192080 ) Via1_HV
+ NEW Metal2 ( 382480 215600 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 370160 202160 ) RECT ( -280 0 280 660 )
+ NEW Metal2 ( 343280 184240 ) RECT ( -280 -660 280 0 )
+ NEW Metal3 ( 339920 184240 ) RECT ( -1040 -280 0 280 )
+ NEW Metal2 ( 337680 145040 ) RECT ( -280 -1040 280 0 )
+ NEW Metal2 ( 374640 145040 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 383600 130480 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 367920 99120 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 397040 123760 ) RECT ( -280 -1040 280 0 )
+ NEW Metal2 ( 392560 214480 ) RECT ( -280 -660 280 0 )
+ NEW Metal3 ( 386960 214480 ) RECT ( 0 -280 1040 280 ) ;
+ - clknet_4_9_0_wb_clk_i ( ANTENNA__1512__CLK I ) ( ANTENNA__1504__CLK I ) ( ANTENNA__1466__CLK I ) ( ANTENNA__1465__CLK I ) ( ANTENNA__1463__CLK I ) ( ANTENNA__1462__CLK I ) ( ANTENNA__1416__CLK I )
+ ( ANTENNA__1367__CLK I ) ( _1367_ CLK ) ( _1416_ CLK ) ( _1462_ CLK ) ( _1463_ CLK ) ( _1465_ CLK ) ( _1466_ CLK ) ( _1504_ CLK )
+ ( _1512_ CLK ) ( clkbuf_4_9_0_wb_clk_i Z ) + USE CLOCK
+ + ROUTED Metal3 ( 337680 262640 ) ( 371280 * )
+ NEW Metal2 ( 374640 255920 ) ( * 262640 )
+ NEW Metal3 ( 371280 262640 ) ( 374640 * )
+ NEW Metal3 ( 374640 254800 ) ( 385840 * )
+ NEW Metal2 ( 374640 254800 ) ( * 255920 )
+ NEW Metal2 ( 408240 271600 ) ( * 277200 )
+ NEW Metal2 ( 406000 271600 ) ( 408240 * )
+ NEW Metal3 ( 401520 286160 ) ( 407120 * )
+ NEW Metal2 ( 407120 277200 ) ( * 286160 )
+ NEW Metal2 ( 407120 277200 ) ( 408240 * )
+ NEW Metal2 ( 417200 278320 ) ( * 286160 )
+ NEW Metal3 ( 407120 286160 ) ( 417200 * )
+ NEW Metal3 ( 417200 286160 ) ( 434000 * )
+ NEW Metal2 ( 379120 231280 ) ( * 254800 )
+ NEW Metal2 ( 417200 286160 ) ( * 299600 )
+ NEW Metal2 ( 384720 301840 ) ( 385840 * )
+ NEW Metal2 ( 385840 286160 ) ( * 301840 )
+ NEW Metal3 ( 385840 286160 ) ( 401520 * )
+ NEW Metal2 ( 406000 268800 ) ( * 271600 )
+ NEW Metal2 ( 404880 254800 ) ( * 261520 )
+ NEW Metal2 ( 404880 268800 ) ( 406000 * )
+ NEW Metal2 ( 404880 261520 ) ( * 268800 )
+ NEW Metal2 ( 408240 249200 ) ( * 254800 )
+ NEW Metal3 ( 404880 254800 ) ( 408240 * )
+ NEW Metal2 ( 418320 246960 ) ( * 254800 )
+ NEW Metal3 ( 408240 254800 ) ( 418320 * )
+ NEW Metal3 ( 418320 254800 ) ( 423920 * )
+ NEW Metal2 ( 414960 233520 ) ( * 246960 )
+ NEW Metal2 ( 414960 246960 ) ( 418320 * )
+ NEW Metal3 ( 385840 254800 ) ( 404880 * )
+ NEW Metal1 ( 371280 262640 ) Via1_HV
+ NEW Metal2 ( 371280 262640 ) Via2_VH
+ NEW Metal1 ( 337680 262640 ) Via1_HV
+ NEW Metal2 ( 337680 262640 ) Via2_VH
+ NEW Metal1 ( 374640 255920 ) Via1_VV
+ NEW Metal2 ( 374640 262640 ) Via2_VH
+ NEW Metal1 ( 385840 254800 ) Via1_HV
+ NEW Metal2 ( 385840 254800 ) Via2_VH
+ NEW Metal2 ( 374640 254800 ) Via2_VH
+ NEW Metal1 ( 406000 271600 ) Via1_HV
+ NEW Metal1 ( 408240 277200 ) Via1_VV
+ NEW Metal1 ( 401520 286160 ) Via1_HV
+ NEW Metal2 ( 401520 286160 ) Via2_VH
+ NEW Metal2 ( 407120 286160 ) Via2_VH
+ NEW Metal1 ( 417200 278320 ) Via1_HV
+ NEW Metal2 ( 417200 286160 ) Via2_VH
+ NEW Metal1 ( 434000 286160 ) Via1_VV
+ NEW Metal2 ( 434000 286160 ) Via2_VH
+ NEW Metal1 ( 379120 231280 ) Via1_HV
+ NEW Metal2 ( 379120 254800 ) Via2_VH
+ NEW Metal1 ( 417200 299600 ) Via1_VV
+ NEW Metal1 ( 384720 301840 ) Via1_HV
+ NEW Metal2 ( 385840 286160 ) Via2_VH
+ NEW Metal1 ( 404880 261520 ) Via1_VV
+ NEW Metal2 ( 404880 254800 ) Via2_VH
+ NEW Metal1 ( 408240 249200 ) Via1_VV
+ NEW Metal2 ( 408240 254800 ) Via2_VH
+ NEW Metal1 ( 418320 246960 ) Via1_HV
+ NEW Metal2 ( 418320 254800 ) Via2_VH
+ NEW Metal1 ( 423920 254800 ) Via1_VV
+ NEW Metal2 ( 423920 254800 ) Via2_VH
+ NEW Metal1 ( 414960 233520 ) Via1_VV
+ NEW Metal2 ( 371280 262640 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 337680 262640 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 385840 254800 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 401520 286160 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 434000 286160 ) RECT ( -280 -660 280 0 )
+ NEW Metal3 ( 379120 254800 ) RECT ( -1040 -280 0 280 )
+ NEW Metal2 ( 423920 254800 ) RECT ( -280 -660 280 0 ) ;
+ - io_in[0] ( PIN io_in[0] ) + USE SIGNAL ;
+ - io_in[10] ( PIN io_in[10] ) ( ANTENNA_input1_I I ) ( input1 I ) + USE SIGNAL
+ + ROUTED Metal3 ( 580720 142800 ) ( 593040 * 0 )
+ NEW Metal3 ( 572880 142800 ) ( 580720 * )
+ NEW Metal1 ( 580720 142800 ) Via1_VV
+ NEW Metal2 ( 580720 142800 ) Via2_VH
+ NEW Metal1 ( 572880 142800 ) Via1_VV
+ NEW Metal2 ( 572880 142800 ) Via2_VH
+ NEW Metal2 ( 580720 142800 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 572880 142800 ) RECT ( -280 -660 280 0 ) ;
+ - io_in[11] ( PIN io_in[11] ) + USE SIGNAL ;
+ - io_in[12] ( PIN io_in[12] ) + USE SIGNAL ;
+ - io_in[13] ( PIN io_in[13] ) + USE SIGNAL ;
+ - io_in[14] ( PIN io_in[14] ) + USE SIGNAL ;
+ - io_in[15] ( PIN io_in[15] ) + USE SIGNAL ;
+ - io_in[16] ( PIN io_in[16] ) + USE SIGNAL ;
+ - io_in[17] ( PIN io_in[17] ) + USE SIGNAL ;
+ - io_in[18] ( PIN io_in[18] ) + USE SIGNAL ;
+ - io_in[19] ( PIN io_in[19] ) + USE SIGNAL ;
+ - io_in[1] ( PIN io_in[1] ) + USE SIGNAL ;
+ - io_in[20] ( PIN io_in[20] ) + USE SIGNAL ;
+ - io_in[21] ( PIN io_in[21] ) + USE SIGNAL ;
+ - io_in[22] ( PIN io_in[22] ) + USE SIGNAL ;
+ - io_in[23] ( PIN io_in[23] ) + USE SIGNAL ;
+ - io_in[24] ( PIN io_in[24] ) + USE SIGNAL ;
+ - io_in[25] ( PIN io_in[25] ) + USE SIGNAL ;
+ - io_in[26] ( PIN io_in[26] ) + USE SIGNAL ;
+ - io_in[27] ( PIN io_in[27] ) + USE SIGNAL ;
+ - io_in[28] ( PIN io_in[28] ) + USE SIGNAL ;
+ - io_in[29] ( PIN io_in[29] ) + USE SIGNAL ;
+ - io_in[2] ( PIN io_in[2] ) + USE SIGNAL ;
+ - io_in[30] ( PIN io_in[30] ) + USE SIGNAL ;
+ - io_in[31] ( PIN io_in[31] ) + USE SIGNAL ;
+ - io_in[32] ( PIN io_in[32] ) + USE SIGNAL ;
+ - io_in[33] ( PIN io_in[33] ) + USE SIGNAL ;
+ - io_in[34] ( PIN io_in[34] ) + USE SIGNAL ;
+ - io_in[35] ( PIN io_in[35] ) + USE SIGNAL ;
+ - io_in[36] ( PIN io_in[36] ) + USE SIGNAL ;
+ - io_in[37] ( PIN io_in[37] ) + USE SIGNAL ;
+ - io_in[3] ( PIN io_in[3] ) + USE SIGNAL ;
+ - io_in[4] ( PIN io_in[4] ) + USE SIGNAL ;
+ - io_in[5] ( PIN io_in[5] ) + USE SIGNAL ;
+ - io_in[6] ( PIN io_in[6] ) + USE SIGNAL ;
+ - io_in[7] ( PIN io_in[7] ) + USE SIGNAL ;
+ - io_in[8] ( PIN io_in[8] ) ( ANTENNA_input2_I I ) ( input2 I ) + USE SIGNAL
+ + ROUTED Metal2 ( 347760 562800 ) ( 348880 * )
+ NEW Metal2 ( 348880 562800 ) ( * 593040 0 )
+ NEW Metal2 ( 348880 562800 ) ( 352240 * )
+ NEW Metal1 ( 347760 562800 ) Via1_VV
+ NEW Metal1 ( 352240 562800 ) Via1_VV ;
+ - io_in[9] ( PIN io_in[9] ) ( ANTENNA_input3_I I ) ( input3 I ) + USE SIGNAL
+ + ROUTED Metal2 ( 388080 562800 ) ( 389200 * )
+ NEW Metal2 ( 389200 562800 ) ( * 593040 0 )
+ NEW Metal2 ( 389200 562800 ) ( 392560 * )
+ NEW Metal1 ( 388080 562800 ) Via1_VV
+ NEW Metal1 ( 392560 562800 ) Via1_VV ;
+ - io_out[11] ( PIN io_out[11] ) ( output5 Z ) + USE SIGNAL
+ + ROUTED Metal3 ( 7280 438480 0 ) ( 21840 * )
+ NEW Metal2 ( 21840 438480 ) ( * 441840 )
+ NEW Metal2 ( 21840 438480 ) Via2_VH
+ NEW Metal1 ( 21840 441840 ) Via1_HV ;
+ - io_out[12] ( PIN io_out[12] ) ( output6 Z ) + USE SIGNAL
+ + ROUTED Metal2 ( 578480 99120 ) ( * 100240 )
+ NEW Metal3 ( 578480 100240 ) ( 593040 * 0 )
+ NEW Metal1 ( 578480 99120 ) Via1_HV
+ NEW Metal2 ( 578480 100240 ) Via2_VH ;
+ - io_out[13] ( PIN io_out[13] ) ( output7 Z ) + USE SIGNAL
+ + ROUTED Metal3 ( 7280 310800 0 ) ( 21840 * )
+ NEW Metal2 ( 21840 310800 ) ( * 316400 )
+ NEW Metal2 ( 21840 310800 ) Via2_VH
+ NEW Metal1 ( 21840 316400 ) Via1_HV ;
+ - io_out[14] ( PIN io_out[14] ) ( output8 Z ) + USE SIGNAL
+ + ROUTED Metal3 ( 7280 21840 0 ) ( 21840 * )
+ NEW Metal2 ( 21840 21840 ) ( * 34160 )
+ NEW Metal2 ( 21840 21840 ) Via2_VH
+ NEW Metal1 ( 21840 34160 ) Via1_HV ;
+ - io_out[15] ( PIN io_out[15] ) ( output9 Z ) + USE SIGNAL
+ + ROUTED Metal2 ( 577360 438480 ) ( * 441840 )
+ NEW Metal3 ( 577360 438480 ) ( 593040 * 0 )
+ NEW Metal1 ( 577360 441840 ) Via1_HV
+ NEW Metal2 ( 577360 438480 ) Via2_VH ;
+ - io_out[16] ( PIN io_out[16] ) ( output10 Z ) + USE SIGNAL
+ + ROUTED Metal2 ( 519120 7280 0 ) ( * 34160 )
+ NEW Metal3 ( 519120 34160 ) ( 537040 * )
+ NEW Metal2 ( 519120 34160 ) Via2_VH
+ NEW Metal1 ( 537040 34160 ) Via1_HV
+ NEW Metal2 ( 537040 34160 ) Via2_VH
+ NEW Metal2 ( 537040 34160 ) RECT ( -280 -660 280 0 ) ;
+ - io_out[17] ( PIN io_out[17] ) ( output11 Z ) + USE SIGNAL
+ + ROUTED Metal2 ( 574000 475440 ) ( * 476560 )
+ NEW Metal3 ( 574000 476560 ) ( 593040 * 0 )
+ NEW Metal1 ( 574000 475440 ) Via1_HV
+ NEW Metal2 ( 574000 476560 ) Via2_VH ;
+ - io_out[18] ( PIN io_out[18] ) ( output12 Z ) + USE SIGNAL
+ + ROUTED Metal2 ( 318640 7280 ) ( * 36400 )
+ NEW Metal2 ( 311920 7280 ) ( 318640 * )
+ NEW Metal2 ( 311920 7280 ) ( * 8400 )
+ NEW Metal2 ( 310800 8400 ) ( 311920 * )
+ NEW Metal2 ( 310800 7280 0 ) ( * 8400 )
+ NEW Metal1 ( 318640 36400 ) Via1_HV ;
+ - net1 ( ANTENNA__1210__A1 I ) ( ANTENNA__1212__A1 I ) ( ANTENNA__1217__A1 I ) ( ANTENNA__1226__B I ) ( ANTENNA__1241__A1 I ) ( ANTENNA__1323__A1 I ) ( input1 Z )
+ ( _1323_ A1 ) ( _1241_ A1 ) ( _1226_ B ) ( _1217_ A1 ) ( _1212_ A1 ) ( _1210_ A1 ) + USE SIGNAL
+ + ROUTED Metal2 ( 467600 302960 ) ( 469840 * )
+ NEW Metal2 ( 513520 298480 ) ( * 315280 )
+ NEW Metal2 ( 510160 298480 ) ( 513520 * )
+ NEW Metal2 ( 510160 203280 ) ( * 298480 )
+ NEW Metal3 ( 510160 203280 ) ( 514640 * )
+ NEW Metal3 ( 500080 308560 ) ( 513520 * )
+ NEW Metal2 ( 495600 309680 ) ( * 317520 )
+ NEW Metal3 ( 495600 309680 ) ( 500080 * )
+ NEW Metal3 ( 500080 308560 ) ( * 309680 )
+ NEW Metal2 ( 514640 145040 ) ( * 203280 )
+ NEW Metal2 ( 467600 302960 ) ( * 319200 )
+ NEW Metal2 ( 469840 356720 ) ( * 362320 )
+ NEW Metal3 ( 469840 362320 ) ( 486640 * )
+ NEW Metal2 ( 464240 350000 ) ( * 353360 )
+ NEW Metal3 ( 464240 353360 ) ( 469840 * )
+ NEW Metal2 ( 469840 353360 ) ( * 356720 )
+ NEW Metal2 ( 455280 347760 ) ( * 353360 )
+ NEW Metal3 ( 455280 353360 ) ( 464240 * )
+ NEW Metal3 ( 469840 334320 ) ( 472080 * )
+ NEW Metal2 ( 469840 334320 ) ( * 353360 )
+ NEW Metal2 ( 466480 332080 ) ( * 334320 )
+ NEW Metal3 ( 466480 334320 ) ( 469840 * )
+ NEW Metal3 ( 463120 334320 ) ( 466480 * )
+ NEW Metal3 ( 467600 319200 ) ( * 319760 )
+ NEW Metal3 ( 463120 319760 ) ( 467600 * )
+ NEW Metal3 ( 475440 320880 ) ( 495600 * )
+ NEW Metal3 ( 475440 319760 ) ( * 320880 )
+ NEW Metal3 ( 467600 319760 ) ( 475440 * )
+ NEW Metal2 ( 495600 320880 ) ( * 325360 )
+ NEW Metal2 ( 463120 316400 ) ( * 334320 )
+ NEW Metal2 ( 495600 317520 ) ( * 320880 )
+ NEW Metal2 ( 577360 143920 ) ( * 145040 )
+ NEW Metal3 ( 514640 145040 ) ( 577360 * )
+ NEW Metal1 ( 469840 302960 ) Via1_VV
+ NEW Metal1 ( 513520 315280 ) Via1_VV
+ NEW Metal2 ( 510160 203280 ) Via2_VH
+ NEW Metal2 ( 514640 203280 ) Via2_VH
+ NEW Metal1 ( 500080 308560 ) Via1_VV
+ NEW Metal2 ( 500080 308560 ) Via2_VH
+ NEW Metal2 ( 513520 308560 ) Via2_VH
+ NEW Metal1 ( 495600 317520 ) Via1_VV
+ NEW Metal2 ( 495600 309680 ) Via2_VH
+ NEW Metal1 ( 463120 316400 ) Via1_VV
+ NEW Metal2 ( 514640 145040 ) Via2_VH
+ NEW Metal1 ( 469840 356720 ) Via1_HV
+ NEW Metal2 ( 469840 362320 ) Via2_VH
+ NEW Metal1 ( 486640 362320 ) Via1_VV
+ NEW Metal2 ( 486640 362320 ) Via2_VH
+ NEW Metal1 ( 464240 350000 ) Via1_VV
+ NEW Metal2 ( 464240 353360 ) Via2_VH
+ NEW Metal2 ( 469840 353360 ) Via2_VH
+ NEW Metal1 ( 455280 347760 ) Via1_VV
+ NEW Metal2 ( 455280 353360 ) Via2_VH
+ NEW Metal1 ( 472080 334320 ) Via1_VV
+ NEW Metal2 ( 472080 334320 ) Via2_VH
+ NEW Metal2 ( 469840 334320 ) Via2_VH
+ NEW Metal1 ( 466480 332080 ) Via1_VV
+ NEW Metal2 ( 466480 334320 ) Via2_VH
+ NEW Metal2 ( 463120 334320 ) Via2_VH
+ NEW Metal2 ( 467600 319200 ) Via2_VH
+ NEW Metal2 ( 463120 319760 ) Via2_VH
+ NEW Metal2 ( 495600 320880 ) Via2_VH
+ NEW Metal1 ( 495600 325360 ) Via1_VV
+ NEW Metal1 ( 577360 143920 ) Via1_HV
+ NEW Metal2 ( 577360 145040 ) Via2_VH
+ NEW Metal2 ( 500080 308560 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 513520 308560 ) RECT ( -280 -1040 280 0 )
+ NEW Metal2 ( 486640 362320 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 472080 334320 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 463120 319760 ) RECT ( -280 0 280 1040 ) ;
+ - net10 ( output10 I ) ( _0852_ Z ) + USE SIGNAL
+ + ROUTED Metal3 ( 513520 44240 ) ( 528080 * )
+ NEW Metal2 ( 528080 35280 ) ( * 44240 )
+ NEW Metal1 ( 513520 44240 ) Via1_VV
+ NEW Metal2 ( 513520 44240 ) Via2_VH
+ NEW Metal2 ( 528080 44240 ) Via2_VH
+ NEW Metal1 ( 528080 35280 ) Via1_HV
+ NEW Metal2 ( 513520 44240 ) RECT ( -280 -660 280 0 ) ;
+ - net11 ( ANTENNA_output11_I I ) ( output11 I ) ( _0854_ Z ) + USE SIGNAL
+ + ROUTED Metal2 ( 574000 316400 ) ( 575120 * )
+ NEW Metal2 ( 579600 465360 ) ( 580720 * )
+ NEW Metal2 ( 579600 465360 ) ( * 474320 )
+ NEW Metal2 ( 574000 316400 ) ( * 319200 )
+ NEW Metal2 ( 574000 319200 ) ( 579600 * )
+ NEW Metal2 ( 579600 319200 ) ( * 465360 )
+ NEW Metal1 ( 575120 316400 ) Via1_VV
+ NEW Metal1 ( 580720 465360 ) Via1_VV
+ NEW Metal1 ( 579600 474320 ) Via1_HV ;
+ - net12 ( output12 I ) ( _0856_ Z ) + USE SIGNAL
+ + ROUTED Metal2 ( 305200 35280 ) ( * 44240 )
+ NEW Metal2 ( 305200 35280 ) ( 311920 * )
+ NEW Metal1 ( 305200 44240 ) Via1_VV
+ NEW Metal1 ( 311920 35280 ) Via1_HV ;
+ - net13 ( PIN io_oeb[0] ) ( wrapped_vga_clock_13 ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 478800 562800 ) ( 479920 * )
+ NEW Metal2 ( 478800 562800 ) ( * 593040 0 )
+ NEW Metal1 ( 479920 562800 ) Via1_VV ;
+ - net14 ( PIN io_oeb[1] ) ( wrapped_vga_clock_14 ZN ) + USE SIGNAL
+ + ROUTED Metal3 ( 7280 290640 0 ) ( 18480 * )
+ NEW Metal2 ( 18480 290640 ) ( * 295120 )
+ NEW Metal2 ( 18480 290640 ) Via2_VH
+ NEW Metal1 ( 18480 295120 ) Via1_VV ;
+ - net15 ( PIN io_oeb[2] ) ( wrapped_vga_clock_15 ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 579600 562800 ) ( * 593040 0 )
+ NEW Metal1 ( 579600 562800 ) Via1_VV ;
+ - net16 ( PIN io_oeb[3] ) ( wrapped_vga_clock_16 ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 82320 562800 ) ( 83440 * )
+ NEW Metal2 ( 82320 562800 ) ( * 593040 0 )
+ NEW Metal1 ( 83440 562800 ) Via1_VV ;
+ - net17 ( PIN io_oeb[4] ) ( wrapped_vga_clock_17 ZN ) + USE SIGNAL
+ + ROUTED Metal3 ( 7280 391440 0 ) ( 18480 * )
+ NEW Metal2 ( 18480 391440 ) ( * 393680 )
+ NEW Metal2 ( 18480 391440 ) Via2_VH
+ NEW Metal1 ( 18480 393680 ) Via1_VV ;
+ - net18 ( PIN io_oeb[5] ) ( wrapped_vga_clock_18 ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 438480 7280 0 ) ( * 33040 )
+ NEW Metal2 ( 438480 33040 ) ( 439600 * )
+ NEW Metal1 ( 439600 33040 ) Via1_VV ;
+ - net19 ( PIN io_oeb[6] ) ( wrapped_vga_clock_19 ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 62160 7280 0 ) ( * 33040 )
+ NEW Metal2 ( 62160 33040 ) ( 63280 * )
+ NEW Metal1 ( 63280 33040 ) Via1_VV ;
+ - net2 ( ANTENNA__1099__A1 I ) ( ANTENNA__1109__A1 I ) ( ANTENNA__1114__A1 I ) ( ANTENNA__1123__B I ) ( ANTENNA__1135__A1 I ) ( ANTENNA__1266__A1 I ) ( input2 Z )
+ ( _1266_ A1 ) ( _1135_ A1 ) ( _1123_ B ) ( _1114_ A1 ) ( _1109_ A1 ) ( _1099_ A1 ) + USE SIGNAL
+ + ROUTED Metal2 ( 362320 506800 ) ( 364560 * )
+ NEW Metal3 ( 364560 500080 ) ( 371280 * )
+ NEW Metal2 ( 364560 500080 ) ( * 506800 )
+ NEW Metal2 ( 371280 484400 ) ( 372400 * )
+ NEW Metal2 ( 371280 484400 ) ( * 500080 )
+ NEW Metal3 ( 371280 487760 ) ( 376880 * )
+ NEW Metal2 ( 380240 484400 ) ( * 487760 )
+ NEW Metal3 ( 376880 487760 ) ( 380240 * )
+ NEW Metal3 ( 380240 488880 ) ( 394800 * )
+ NEW Metal3 ( 380240 487760 ) ( * 488880 )
+ NEW Metal2 ( 395920 504560 ) ( 397040 * )
+ NEW Metal2 ( 397040 498960 ) ( * 504560 )
+ NEW Metal2 ( 397040 498960 ) ( 398160 * )
+ NEW Metal2 ( 398160 488880 ) ( * 498960 )
+ NEW Metal3 ( 394800 488880 ) ( 398160 * )
+ NEW Metal2 ( 403760 503440 ) ( * 504560 )
+ NEW Metal2 ( 402640 504560 ) ( 403760 * )
+ NEW Metal3 ( 397040 504560 ) ( 402640 * )
+ NEW Metal2 ( 376880 468720 ) ( 378000 * )
+ NEW Metal2 ( 376880 468720 ) ( * 487760 )
+ NEW Metal3 ( 378000 468720 ) ( 384720 * )
+ NEW Metal3 ( 402640 504560 ) ( 420560 * )
+ NEW Metal2 ( 398160 442960 ) ( * 454160 )
+ NEW Metal3 ( 384720 454160 ) ( 398160 * )
+ NEW Metal2 ( 384720 454160 ) ( * 468720 )
+ NEW Metal2 ( 362320 506800 ) ( * 554400 )
+ NEW Metal2 ( 357840 554400 ) ( 362320 * )
+ NEW Metal2 ( 357840 554400 ) ( * 559440 )
+ NEW Metal1 ( 364560 506800 ) Via1_VV
+ NEW Metal1 ( 371280 500080 ) Via1_VV
+ NEW Metal2 ( 371280 500080 ) Via2_VH
+ NEW Metal2 ( 364560 500080 ) Via2_VH
+ NEW Metal1 ( 372400 484400 ) Via1_VV
+ NEW Metal1 ( 376880 487760 ) Via1_VV
+ NEW Metal2 ( 376880 487760 ) Via2_VH
+ NEW Metal2 ( 371280 487760 ) Via2_VH
+ NEW Metal1 ( 380240 484400 ) Via1_VV
+ NEW Metal2 ( 380240 487760 ) Via2_VH
+ NEW Metal1 ( 394800 488880 ) Via1_VV
+ NEW Metal2 ( 394800 488880 ) Via2_VH
+ NEW Metal1 ( 395920 504560 ) Via1_VV
+ NEW Metal2 ( 398160 488880 ) Via2_VH
+ NEW Metal1 ( 403760 503440 ) Via1_VV
+ NEW Metal2 ( 402640 504560 ) Via2_VH
+ NEW Metal2 ( 397040 504560 ) Via2_VH
+ NEW Metal1 ( 378000 468720 ) Via1_VV
+ NEW Metal1 ( 384720 468720 ) Via1_VV
+ NEW Metal2 ( 384720 468720 ) Via2_VH
+ NEW Metal2 ( 378000 468720 ) Via2_VH
+ NEW Metal1 ( 420560 504560 ) Via1_VV
+ NEW Metal2 ( 420560 504560 ) Via2_VH
+ NEW Metal1 ( 398160 442960 ) Via1_HV
+ NEW Metal2 ( 398160 454160 ) Via2_VH
+ NEW Metal2 ( 384720 454160 ) Via2_VH
+ NEW Metal1 ( 357840 559440 ) Via1_VV
+ NEW Metal2 ( 371280 500080 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 376880 487760 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 371280 487760 ) RECT ( -280 -1040 280 0 )
+ NEW Metal2 ( 394800 488880 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 397040 504560 ) RECT ( -280 -1040 280 0 )
+ NEW Metal2 ( 384720 468720 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 378000 468720 ) RECT ( -280 -1040 280 0 )
+ NEW Metal2 ( 420560 504560 ) RECT ( -280 -660 280 0 ) ;
+ - net20 ( PIN io_oeb[7] ) ( wrapped_vga_clock_20 ZN ) + USE SIGNAL
+ + ROUTED Metal3 ( 7280 250320 0 ) ( 18480 * )
+ NEW Metal2 ( 18480 250320 ) ( * 252560 )
+ NEW Metal2 ( 18480 250320 ) Via2_VH
+ NEW Metal1 ( 18480 252560 ) Via1_VV ;
+ - net21 ( PIN io_oeb[8] ) ( wrapped_vga_clock_21 ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 580720 8400 ) ( * 33040 )
+ NEW Metal3 ( 580720 8400 ) ( 593040 * )
+ NEW Metal3 ( 593040 2800 ) ( * 8400 )
+ NEW Metal3 ( 591920 2800 ) ( 593040 * )
+ NEW Metal3 ( 591920 1680 ) ( * 2800 )
+ NEW Metal3 ( 591920 1680 ) ( 593040 * 0 )
+ NEW Metal1 ( 580720 33040 ) Via1_VV
+ NEW Metal2 ( 580720 8400 ) Via2_VH ;
+ - net22 ( PIN io_oeb[9] ) ( wrapped_vga_clock_22 ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 553840 351120 ) ( * 357840 )
+ NEW Metal3 ( 553840 351120 ) ( 554400 * )
+ NEW Metal3 ( 554400 350000 ) ( * 351120 )
+ NEW Metal3 ( 554400 350000 ) ( 593040 * 0 )
+ NEW Metal3 ( 553840 357840 ) ( 580720 * )
+ NEW Metal2 ( 553840 351120 ) Via2_VH
+ NEW Metal2 ( 553840 357840 ) Via2_VH
+ NEW Metal1 ( 580720 357840 ) Via1_VV
+ NEW Metal2 ( 580720 357840 ) Via2_VH
+ NEW Metal2 ( 580720 357840 ) RECT ( -280 -660 280 0 ) ;
+ - net23 ( PIN io_oeb[10] ) ( wrapped_vga_clock_23 ZN ) + USE SIGNAL
+ + ROUTED Metal3 ( 580720 574000 ) ( 597520 * )
+ NEW Metal2 ( 597520 574000 ) ( * 593040 0 )
+ NEW Metal2 ( 580720 551600 ) ( * 574000 )
+ NEW Metal1 ( 580720 551600 ) Via1_VV
+ NEW Metal2 ( 580720 574000 ) Via2_VH
+ NEW Metal2 ( 597520 574000 ) Via2_VH ;
+ - net24 ( PIN io_oeb[11] ) ( wrapped_vga_clock_24 ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 580720 498960 ) ( * 503440 )
+ NEW Metal3 ( 580720 498960 ) ( 593040 * 0 )
+ NEW Metal1 ( 580720 503440 ) Via1_VV
+ NEW Metal2 ( 580720 498960 ) Via2_VH ;
+ - net25 ( PIN io_oeb[12] ) ( wrapped_vga_clock_25 ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 82320 7280 0 ) ( * 33040 )
+ NEW Metal2 ( 82320 33040 ) ( 83440 * )
+ NEW Metal1 ( 83440 33040 ) Via1_VV ;
+ - net26 ( PIN io_oeb[13] ) ( wrapped_vga_clock_26 ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 102480 562800 ) ( 103600 * )
+ NEW Metal2 ( 102480 562800 ) ( * 593040 0 )
+ NEW Metal1 ( 103600 562800 ) Via1_VV ;
+ - net27 ( PIN io_oeb[14] ) ( wrapped_vga_clock_27 ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 270480 7280 0 ) ( * 33040 )
+ NEW Metal2 ( 270480 33040 ) ( 271600 * )
+ NEW Metal1 ( 271600 33040 ) Via1_VV ;
+ - net28 ( PIN io_oeb[15] ) ( wrapped_vga_clock_28 ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 351120 7280 0 ) ( * 33040 )
+ NEW Metal2 ( 351120 33040 ) ( 352240 * )
+ NEW Metal1 ( 352240 33040 ) Via1_VV ;
+ - net29 ( PIN io_oeb[16] ) ( wrapped_vga_clock_29 ZN ) + USE SIGNAL
+ + ROUTED Metal3 ( 580720 519120 ) ( 593040 * 0 )
+ NEW Metal1 ( 580720 519120 ) Via1_VV
+ NEW Metal2 ( 580720 519120 ) Via2_VH
+ NEW Metal2 ( 580720 519120 ) RECT ( -280 -660 280 0 ) ;
+ - net3 ( ANTENNA__1159__A1 I ) ( ANTENNA__1161__A1 I ) ( ANTENNA__1168__A1 I ) ( ANTENNA__1176__B I ) ( ANTENNA__1188__A1 I ) ( ANTENNA__1295__A1 I ) ( input3 Z )
+ ( _1295_ A1 ) ( _1188_ A1 ) ( _1176_ B ) ( _1168_ A1 ) ( _1161_ A1 ) ( _1159_ A1 ) + USE SIGNAL
+ + ROUTED Metal2 ( 458640 459760 ) ( * 467600 )
+ NEW Metal3 ( 455280 459760 ) ( 458640 * )
+ NEW Metal2 ( 467600 492240 ) ( * 498960 )
+ NEW Metal2 ( 467600 492240 ) ( 469840 * )
+ NEW Metal2 ( 469840 485520 ) ( * 492240 )
+ NEW Metal2 ( 468720 485520 ) ( 469840 * )
+ NEW Metal2 ( 468720 467600 ) ( * 485520 )
+ NEW Metal3 ( 458640 467600 ) ( 468720 * )
+ NEW Metal2 ( 467600 498960 ) ( * 503440 )
+ NEW Metal3 ( 467600 504560 ) ( 492240 * )
+ NEW Metal3 ( 467600 503440 ) ( * 504560 )
+ NEW Metal2 ( 492240 500080 ) ( 494480 * )
+ NEW Metal2 ( 492240 500080 ) ( * 504560 )
+ NEW Metal2 ( 496720 488880 ) ( 497840 * )
+ NEW Metal2 ( 496720 488880 ) ( * 500080 )
+ NEW Metal2 ( 494480 500080 ) ( 496720 * )
+ NEW Metal2 ( 496720 497840 ) ( 501200 * )
+ NEW Metal2 ( 503440 491120 ) ( * 497840 )
+ NEW Metal2 ( 501200 497840 ) ( 503440 * )
+ NEW Metal3 ( 503440 491120 ) ( 507920 * )
+ NEW Metal3 ( 465360 516880 ) ( 467600 * )
+ NEW Metal2 ( 465360 504560 ) ( * 516880 )
+ NEW Metal3 ( 465360 504560 ) ( 467600 * )
+ NEW Metal2 ( 467600 516880 ) ( * 559440 )
+ NEW Metal2 ( 423920 459760 ) ( * 467600 )
+ NEW Metal3 ( 423920 459760 ) ( 455280 * )
+ NEW Metal3 ( 398160 559440 ) ( 467600 * )
+ NEW Metal1 ( 455280 459760 ) Via1_VV
+ NEW Metal2 ( 455280 459760 ) Via2_VH
+ NEW Metal1 ( 458640 467600 ) Via1_VV
+ NEW Metal2 ( 458640 459760 ) Via2_VH
+ NEW Metal1 ( 467600 498960 ) Via1_VV
+ NEW Metal2 ( 468720 467600 ) Via2_VH
+ NEW Metal2 ( 458640 467600 ) Via2_VH
+ NEW Metal1 ( 467600 503440 ) Via1_VV
+ NEW Metal1 ( 492240 504560 ) Via1_VV
+ NEW Metal2 ( 492240 504560 ) Via2_VH
+ NEW Metal2 ( 467600 503440 ) Via2_VH
+ NEW Metal1 ( 494480 500080 ) Via1_VV
+ NEW Metal1 ( 497840 488880 ) Via1_VV
+ NEW Metal1 ( 501200 497840 ) Via1_VV
+ NEW Metal1 ( 503440 491120 ) Via1_VV
+ NEW Metal1 ( 507920 491120 ) Via1_VV
+ NEW Metal2 ( 507920 491120 ) Via2_VH
+ NEW Metal2 ( 503440 491120 ) Via2_VH
+ NEW Metal2 ( 467600 516880 ) Via2_VH
+ NEW Metal2 ( 465360 516880 ) Via2_VH
+ NEW Metal2 ( 465360 504560 ) Via2_VH
+ NEW Metal2 ( 467600 559440 ) Via2_VH
+ NEW Metal1 ( 423920 459760 ) Via1_VV
+ NEW Metal2 ( 423920 459760 ) Via2_VH
+ NEW Metal1 ( 423920 467600 ) Via1_HV
+ NEW Metal1 ( 398160 559440 ) Via1_VV
+ NEW Metal2 ( 398160 559440 ) Via2_VH
+ NEW Metal2 ( 455280 459760 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 458640 467600 ) RECT ( -280 -1040 280 0 )
+ NEW Metal2 ( 492240 504560 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 467600 503440 ) RECT ( -280 -1040 280 0 )
+ NEW Metal2 ( 507920 491120 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 503440 491120 ) RECT ( -280 -1040 280 0 )
+ NEW Metal2 ( 423920 459760 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 398160 559440 ) RECT ( -280 -660 280 0 ) ;
+ - net30 ( PIN io_oeb[17] ) ( wrapped_vga_clock_30 ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 539280 7280 0 ) ( * 8400 )
+ NEW Metal2 ( 539280 8400 ) ( 540400 * )
+ NEW Metal2 ( 540400 7280 ) ( * 8400 )
+ NEW Metal2 ( 540400 7280 ) ( 546000 * )
+ NEW Metal2 ( 546000 7280 ) ( * 33040 )
+ NEW Metal1 ( 546000 33040 ) Via1_VV ;
+ - net31 ( PIN io_oeb[18] ) ( wrapped_vga_clock_31 ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 580720 391440 ) ( * 393680 )
+ NEW Metal3 ( 580720 391440 ) ( 593040 * 0 )
+ NEW Metal1 ( 580720 393680 ) Via1_VV
+ NEW Metal2 ( 580720 391440 ) Via2_VH ;
+ - net32 ( PIN io_oeb[19] ) ( wrapped_vga_clock_32 ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 250320 562800 ) ( 253680 * )
+ NEW Metal2 ( 250320 562800 ) ( * 593040 0 )
+ NEW Metal1 ( 253680 562800 ) Via1_VV ;
+ - net33 ( PIN io_oeb[20] ) ( wrapped_vga_clock_33 ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 142800 562800 ) ( 143920 * )
+ NEW Metal2 ( 142800 562800 ) ( * 593040 0 )
+ NEW Metal1 ( 143920 562800 ) Via1_VV ;
+ - net34 ( PIN io_oeb[21] ) ( wrapped_vga_clock_34 ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 310800 562800 ) ( 311920 * )
+ NEW Metal2 ( 310800 562800 ) ( * 593040 0 )
+ NEW Metal1 ( 311920 562800 ) Via1_VV ;
+ - net35 ( PIN io_oeb[22] ) ( wrapped_vga_clock_35 ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 478800 7280 0 ) ( * 33040 )
+ NEW Metal2 ( 478800 33040 ) ( 479920 * )
+ NEW Metal1 ( 479920 33040 ) Via1_VV ;
+ - net36 ( PIN io_oeb[23] ) ( wrapped_vga_clock_36 ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 183120 7280 0 ) ( * 33040 )
+ NEW Metal2 ( 183120 33040 ) ( 184240 * )
+ NEW Metal1 ( 184240 33040 ) Via1_VV ;
+ - net37 ( PIN io_oeb[24] ) ( wrapped_vga_clock_37 ZN ) + USE SIGNAL
+ + ROUTED Metal3 ( 580720 169680 ) ( 593040 * )
+ NEW Metal3 ( 593040 164080 ) ( * 169680 )
+ NEW Metal3 ( 591920 164080 ) ( 593040 * )
+ NEW Metal3 ( 591920 162960 ) ( * 164080 )
+ NEW Metal3 ( 591920 162960 ) ( 593040 * 0 )
+ NEW Metal1 ( 580720 169680 ) Via1_VV
+ NEW Metal2 ( 580720 169680 ) Via2_VH
+ NEW Metal2 ( 580720 169680 ) RECT ( -280 -660 280 0 ) ;
+ - net38 ( PIN io_oeb[25] ) ( wrapped_vga_clock_38 ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 162960 562800 ) ( 164080 * )
+ NEW Metal2 ( 162960 562800 ) ( * 593040 0 )
+ NEW Metal1 ( 164080 562800 ) Via1_VV ;
+ - net39 ( PIN io_oeb[26] ) ( wrapped_vga_clock_39 ZN ) + USE SIGNAL
+ + ROUTED Metal3 ( 580720 418320 ) ( * 420560 )
+ NEW Metal3 ( 580720 418320 ) ( 593040 * 0 )
+ NEW Metal1 ( 580720 420560 ) Via1_VV
+ NEW Metal2 ( 580720 420560 ) Via2_VH
+ NEW Metal2 ( 580720 420560 ) RECT ( -280 -660 280 0 ) ;
+ - net4 ( input4 Z ) ( _0878_ I ) + USE SIGNAL
+ + ROUTED Metal2 ( 577360 286160 ) ( * 295120 )
+ NEW Metal1 ( 577360 286160 ) Via1_VV
+ NEW Metal1 ( 577360 295120 ) Via1_VV ;
+ - net40 ( PIN io_oeb[27] ) ( wrapped_vga_clock_40 ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 42000 7280 0 ) ( * 33040 )
+ NEW Metal2 ( 42000 33040 ) ( 43120 * )
+ NEW Metal1 ( 43120 33040 ) Via1_VV ;
+ - net41 ( PIN io_oeb[28] ) ( wrapped_vga_clock_41 ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 559440 7280 0 ) ( * 8400 )
+ NEW Metal2 ( 559440 8400 ) ( 560560 * )
+ NEW Metal2 ( 560560 7280 ) ( * 8400 )
+ NEW Metal2 ( 560560 7280 ) ( 567280 * )
+ NEW Metal2 ( 567280 7280 ) ( * 33040 )
+ NEW Metal1 ( 567280 33040 ) Via1_VV ;
+ - net42 ( PIN io_oeb[29] ) ( wrapped_vga_clock_42 ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 580720 122640 ) ( * 127120 )
+ NEW Metal3 ( 580720 122640 ) ( 593040 * 0 )
+ NEW Metal1 ( 580720 127120 ) Via1_VV
+ NEW Metal2 ( 580720 122640 ) Via2_VH ;
+ - net43 ( PIN io_oeb[30] ) ( wrapped_vga_clock_43 ZN ) + USE SIGNAL
+ + ROUTED Metal3 ( 7280 498960 0 ) ( 18480 * )
+ NEW Metal2 ( 18480 498960 ) ( * 503440 )
+ NEW Metal2 ( 18480 498960 ) Via2_VH
+ NEW Metal1 ( 18480 503440 ) Via1_VV ;
+ - net44 ( PIN io_oeb[31] ) ( wrapped_vga_clock_44 ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 498960 7280 0 ) ( * 33040 )
+ NEW Metal2 ( 498960 33040 ) ( 500080 * )
+ NEW Metal1 ( 500080 33040 ) Via1_VV ;
+ - net45 ( PIN io_oeb[32] ) ( wrapped_vga_clock_45 ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 250320 7280 0 ) ( * 33040 )
+ NEW Metal2 ( 250320 33040 ) ( 253680 * )
+ NEW Metal1 ( 253680 33040 ) Via1_VV ;
+ - net46 ( PIN io_oeb[33] ) ( wrapped_vga_clock_46 ZN ) + USE SIGNAL
+ + ROUTED Metal3 ( 7280 478800 0 ) ( 18480 * )
+ NEW Metal2 ( 18480 478800 ) ( * 483280 )
+ NEW Metal2 ( 18480 478800 ) Via2_VH
+ NEW Metal1 ( 18480 483280 ) Via1_VV ;
+ - net47 ( PIN io_oeb[34] ) ( wrapped_vga_clock_47 ZN ) + USE SIGNAL
+ + ROUTED Metal3 ( 580720 456400 ) ( 593040 * 0 )
+ NEW Metal1 ( 580720 456400 ) Via1_VV
+ NEW Metal2 ( 580720 456400 ) Via2_VH
+ NEW Metal2 ( 580720 456400 ) RECT ( -280 -660 280 0 ) ;
+ - net48 ( PIN io_oeb[35] ) ( wrapped_vga_clock_48 ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 18480 268240 ) ( * 269360 )
+ NEW Metal3 ( 7280 269360 0 ) ( 18480 * )
+ NEW Metal1 ( 18480 268240 ) Via1_VV
+ NEW Metal2 ( 18480 269360 ) Via2_VH ;
+ - net49 ( PIN io_oeb[36] ) ( wrapped_vga_clock_49 ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 580720 42000 ) ( * 44240 )
+ NEW Metal3 ( 580720 42000 ) ( 593040 * 0 )
+ NEW Metal1 ( 580720 44240 ) Via1_VV
+ NEW Metal2 ( 580720 42000 ) Via2_VH ;
+ - net5 ( ANTENNA_output5_I I ) ( output5 I ) ( _0859_ ZN ) + USE SIGNAL
+ + ROUTED Metal3 ( 30800 442960 ) ( 35280 * )
+ NEW Metal2 ( 35280 246960 ) ( * 442960 )
+ NEW Metal3 ( 108080 245840 ) ( * 246960 )
+ NEW Metal3 ( 35280 246960 ) ( 108080 * )
+ NEW Metal3 ( 108080 245840 ) ( 215600 * )
+ NEW Metal2 ( 35280 246960 ) Via2_VH
+ NEW Metal1 ( 35280 442960 ) Via1_VV
+ NEW Metal2 ( 35280 442960 ) Via2_VH
+ NEW Metal1 ( 30800 442960 ) Via1_HV
+ NEW Metal2 ( 30800 442960 ) Via2_VH
+ NEW Metal1 ( 215600 245840 ) Via1_VV
+ NEW Metal2 ( 215600 245840 ) Via2_VH
+ NEW Metal2 ( 35280 442960 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 30800 442960 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 215600 245840 ) RECT ( -280 -660 280 0 ) ;
+ - net50 ( PIN io_oeb[37] ) ( wrapped_vga_clock_50 ZN ) + USE SIGNAL
+ + ROUTED Metal3 ( 7280 598640 0 ) ( 18480 * )
+ NEW Metal2 ( 18480 551600 ) ( * 598640 )
+ NEW Metal1 ( 18480 551600 ) Via1_VV
+ NEW Metal2 ( 18480 598640 ) Via2_VH ;
+ - net51 ( PIN io_out[0] ) ( wrapped_vga_clock_51 ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 580720 230160 ) ( * 232400 )
+ NEW Metal3 ( 580720 230160 ) ( 593040 * 0 )
+ NEW Metal1 ( 580720 232400 ) Via1_VV
+ NEW Metal2 ( 580720 230160 ) Via2_VH ;
+ - net52 ( PIN io_out[1] ) ( wrapped_vga_clock_52 ZN ) + USE SIGNAL
+ + ROUTED Metal3 ( 7280 230160 0 ) ( 18480 * )
+ NEW Metal2 ( 18480 230160 ) ( * 232400 )
+ NEW Metal2 ( 18480 230160 ) Via2_VH
+ NEW Metal1 ( 18480 232400 ) Via1_VV ;
+ - net53 ( PIN io_out[2] ) ( wrapped_vga_clock_53 ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 290640 7280 0 ) ( * 33040 )
+ NEW Metal2 ( 290640 33040 ) ( 292880 * )
+ NEW Metal1 ( 292880 33040 ) Via1_VV ;
+ - net54 ( PIN io_out[3] ) ( wrapped_vga_clock_54 ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 330960 7280 0 ) ( * 33040 )
+ NEW Metal2 ( 330960 33040 ) ( 332080 * )
+ NEW Metal1 ( 332080 33040 ) Via1_VV ;
+ - net55 ( PIN io_out[4] ) ( wrapped_vga_clock_55 ZN ) + USE SIGNAL
+ + ROUTED Metal3 ( 7280 142800 0 ) ( 18480 * )
+ NEW Metal1 ( 18480 142800 ) Via1_VV
+ NEW Metal2 ( 18480 142800 ) Via2_VH
+ NEW Metal2 ( 18480 142800 ) RECT ( -280 -660 280 0 ) ;
+ - net56 ( PIN io_out[5] ) ( wrapped_vga_clock_56 ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 458640 562800 ) ( 459760 * )
+ NEW Metal2 ( 458640 562800 ) ( * 593040 0 )
+ NEW Metal1 ( 459760 562800 ) Via1_VV ;
+ - net57 ( PIN io_out[6] ) ( wrapped_vga_clock_57 ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 21840 562800 ) ( 22960 * )
+ NEW Metal2 ( 21840 562800 ) ( * 593040 0 )
+ NEW Metal1 ( 22960 562800 ) Via1_VV ;
+ - net58 ( PIN io_out[7] ) ( wrapped_vga_clock_58 ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 122640 562800 ) ( 123760 * )
+ NEW Metal2 ( 122640 562800 ) ( * 593040 0 )
+ NEW Metal1 ( 123760 562800 ) Via1_VV ;
+ - net59 ( PIN io_out[8] ) ( wrapped_vga_clock_59 ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 418320 7280 0 ) ( * 33040 )
+ NEW Metal2 ( 418320 33040 ) ( 419440 * )
+ NEW Metal1 ( 419440 33040 ) Via1_VV ;
+ - net6 ( ANTENNA_output6_I I ) ( output6 I ) ( _0864_ ZN ) + USE SIGNAL
+ + ROUTED Metal3 ( 436800 99120 ) ( * 100240 )
+ NEW Metal3 ( 324240 100240 ) ( 436800 * )
+ NEW Metal2 ( 324240 100240 ) ( * 111440 )
+ NEW Metal2 ( 568400 98000 ) ( * 99120 )
+ NEW Metal3 ( 563920 99120 ) ( 568400 * )
+ NEW Metal3 ( 436800 99120 ) ( 563920 * )
+ NEW Metal2 ( 324240 100240 ) Via2_VH
+ NEW Metal1 ( 324240 111440 ) Via1_VV
+ NEW Metal1 ( 563920 99120 ) Via1_VV
+ NEW Metal2 ( 563920 99120 ) Via2_VH
+ NEW Metal1 ( 568400 98000 ) Via1_HV
+ NEW Metal2 ( 568400 99120 ) Via2_VH
+ NEW Metal2 ( 563920 99120 ) RECT ( -280 -660 280 0 ) ;
+ - net60 ( PIN io_out[9] ) ( wrapped_vga_clock_60 ZN ) + USE SIGNAL
+ + ROUTED Metal3 ( 7280 162960 0 ) ( 18480 * )
+ NEW Metal2 ( 18480 162960 ) ( * 169680 )
+ NEW Metal2 ( 18480 162960 ) Via2_VH
+ NEW Metal1 ( 18480 169680 ) Via1_VV ;
+ - net61 ( PIN io_out[10] ) ( wrapped_vga_clock_61 ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 458640 7280 0 ) ( * 33040 )
+ NEW Metal2 ( 458640 33040 ) ( 459760 * )
+ NEW Metal1 ( 459760 33040 ) Via1_VV ;
+ - net62 ( PIN io_out[19] ) ( wrapped_vga_clock_62 ZN ) + USE SIGNAL
+ + ROUTED Metal3 ( 7280 122640 0 ) ( 18480 * )
+ NEW Metal2 ( 18480 122640 ) ( * 127120 )
+ NEW Metal2 ( 18480 122640 ) Via2_VH
+ NEW Metal1 ( 18480 127120 ) Via1_VV ;
+ - net63 ( PIN io_out[20] ) ( wrapped_vga_clock_63 ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 1680 7280 0 ) ( * 8400 )
+ NEW Metal2 ( 1680 8400 ) ( 2800 * )
+ NEW Metal2 ( 2800 7280 ) ( * 8400 )
+ NEW Metal2 ( 2800 7280 ) ( 8400 * )
+ NEW Metal2 ( 8400 7280 ) ( * 22960 )
+ NEW Metal3 ( 8400 22960 ) ( 33040 * )
+ NEW Metal2 ( 33040 22960 ) ( * 44240 )
+ NEW Metal2 ( 8400 22960 ) Via2_VH
+ NEW Metal2 ( 33040 22960 ) Via2_VH
+ NEW Metal1 ( 33040 44240 ) Via1_VV ;
+ - net64 ( PIN io_out[21] ) ( wrapped_vga_clock_64 ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 391440 7280 0 ) ( * 33040 )
+ NEW Metal2 ( 391440 33040 ) ( 392560 * )
+ NEW Metal1 ( 392560 33040 ) Via1_VV ;
+ - net65 ( PIN io_out[22] ) ( wrapped_vga_clock_65 ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 42000 562800 ) ( 43120 * )
+ NEW Metal2 ( 42000 562800 ) ( * 593040 0 )
+ NEW Metal1 ( 43120 562800 ) Via1_VV ;
+ - net66 ( PIN io_out[23] ) ( wrapped_vga_clock_66 ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 230160 562800 ) ( 231280 * )
+ NEW Metal2 ( 230160 562800 ) ( * 593040 0 )
+ NEW Metal1 ( 231280 562800 ) Via1_VV ;
+ - net67 ( PIN io_out[24] ) ( wrapped_vga_clock_67 ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 418320 562800 ) ( 419440 * )
+ NEW Metal2 ( 418320 562800 ) ( * 593040 0 )
+ NEW Metal1 ( 419440 562800 ) Via1_VV ;
+ - net68 ( PIN io_out[25] ) ( wrapped_vga_clock_68 ZN ) + USE SIGNAL
+ + ROUTED Metal3 ( 7280 42000 0 ) ( 18480 * )
+ NEW Metal2 ( 18480 42000 ) ( * 48720 )
+ NEW Metal2 ( 18480 42000 ) Via2_VH
+ NEW Metal1 ( 18480 48720 ) Via1_VV ;
+ - net69 ( PIN io_out[26] ) ( wrapped_vga_clock_69 ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 102480 7280 0 ) ( * 33040 )
+ NEW Metal2 ( 102480 33040 ) ( 103600 * )
+ NEW Metal1 ( 103600 33040 ) Via1_VV ;
+ - net7 ( output7 I ) ( _0846_ Z ) + USE SIGNAL
+ + ROUTED Metal2 ( 27440 311920 ) ( 28560 * )
+ NEW Metal2 ( 28560 311920 ) ( * 317520 )
+ NEW Metal1 ( 27440 311920 ) Via1_VV
+ NEW Metal1 ( 28560 317520 ) Via1_HV ;
+ - net70 ( PIN io_out[27] ) ( wrapped_vga_clock_70 ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 21840 7280 0 ) ( * 17360 )
+ NEW Metal3 ( 21840 17360 ) ( 36400 * )
+ NEW Metal2 ( 36400 17360 ) ( * 33040 )
+ NEW Metal2 ( 21840 17360 ) Via2_VH
+ NEW Metal2 ( 36400 17360 ) Via2_VH
+ NEW Metal1 ( 36400 33040 ) Via1_VV ;
+ - net71 ( PIN io_out[28] ) ( wrapped_vga_clock_71 ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 498960 562800 ) ( 500080 * )
+ NEW Metal2 ( 498960 562800 ) ( * 593040 0 )
+ NEW Metal1 ( 500080 562800 ) Via1_VV ;
+ - net72 ( PIN io_out[29] ) ( wrapped_vga_clock_72 ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 371280 562800 ) ( 372400 * )
+ NEW Metal2 ( 371280 562800 ) ( * 593040 0 )
+ NEW Metal1 ( 372400 562800 ) Via1_VV ;
+ - net73 ( PIN io_out[30] ) ( wrapped_vga_clock_73 ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 567280 562800 ) ( * 593040 )
+ NEW Metal2 ( 560560 593040 ) ( 567280 * )
+ NEW Metal2 ( 560560 591920 ) ( * 593040 )
+ NEW Metal2 ( 559440 591920 ) ( 560560 * )
+ NEW Metal2 ( 559440 591920 ) ( * 593040 0 )
+ NEW Metal1 ( 567280 562800 ) Via1_VV ;
+ - net74 ( PIN io_out[31] ) ( wrapped_vga_clock_74 ZN ) + USE SIGNAL
+ + ROUTED Metal3 ( 580720 80080 ) ( 593040 * 0 )
+ NEW Metal1 ( 580720 80080 ) Via1_VV
+ NEW Metal2 ( 580720 80080 ) Via2_VH
+ NEW Metal2 ( 580720 80080 ) RECT ( -280 -660 280 0 ) ;
+ - net75 ( PIN io_out[32] ) ( wrapped_vga_clock_75 ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 29680 562800 ) ( * 570640 )
+ NEW Metal3 ( 29680 570640 ) ( * 571760 )
+ NEW Metal3 ( 7280 571760 ) ( 29680 * )
+ NEW Metal3 ( 7280 571760 ) ( * 576240 )
+ NEW Metal3 ( 7280 576240 ) ( 8400 * )
+ NEW Metal3 ( 8400 576240 ) ( * 577360 )
+ NEW Metal3 ( 7280 577360 0 ) ( 8400 * )
+ NEW Metal1 ( 29680 562800 ) Via1_VV
+ NEW Metal2 ( 29680 570640 ) Via2_VH ;
+ - net76 ( PIN io_out[33] ) ( wrapped_vga_clock_76 ZN ) + USE SIGNAL
+ + ROUTED Metal3 ( 7280 210000 0 ) ( 18480 * )
+ NEW Metal2 ( 18480 210000 ) ( * 216720 )
+ NEW Metal2 ( 18480 210000 ) Via2_VH
+ NEW Metal1 ( 18480 216720 ) Via1_VV ;
+ - net77 ( PIN io_out[34] ) ( wrapped_vga_clock_77 ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 122640 7280 0 ) ( * 33040 )
+ NEW Metal2 ( 122640 33040 ) ( 123760 * )
+ NEW Metal1 ( 123760 33040 ) Via1_VV ;
+ - net78 ( PIN io_out[35] ) ( wrapped_vga_clock_78 ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 210000 7280 0 ) ( * 8400 )
+ NEW Metal2 ( 210000 8400 ) ( 211120 * )
+ NEW Metal2 ( 211120 7280 ) ( * 8400 )
+ NEW Metal2 ( 211120 7280 ) ( 214480 * )
+ NEW Metal2 ( 214480 7280 ) ( * 33040 )
+ NEW Metal1 ( 214480 33040 ) Via1_VV ;
+ - net79 ( PIN io_out[36] ) ( wrapped_vga_clock_79 ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 18480 175280 ) ( * 180880 )
+ NEW Metal3 ( 7280 180880 0 ) ( 18480 * )
+ NEW Metal1 ( 18480 175280 ) Via1_VV
+ NEW Metal2 ( 18480 180880 ) Via2_VH ;
+ - net8 ( output8 I ) ( _0848_ Z ) + USE SIGNAL
+ + ROUTED Metal2 ( 27440 44240 ) ( 28560 * )
+ NEW Metal2 ( 28560 35280 ) ( * 44240 )
+ NEW Metal1 ( 27440 44240 ) Via1_VV
+ NEW Metal1 ( 28560 35280 ) Via1_HV ;
+ - net80 ( PIN io_out[37] ) ( wrapped_vga_clock_80 ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 580720 371280 ) ( * 373520 )
+ NEW Metal3 ( 580720 371280 ) ( 593040 * 0 )
+ NEW Metal1 ( 580720 373520 ) Via1_VV
+ NEW Metal2 ( 580720 371280 ) Via2_VH ;
+ - net9 ( output9 I ) ( _0850_ Z ) + USE SIGNAL
+ + ROUTED Metal2 ( 570640 426160 ) ( 571760 * )
+ NEW Metal2 ( 570640 426160 ) ( * 442960 )
+ NEW Metal1 ( 570640 442960 ) Via1_HV
+ NEW Metal1 ( 571760 426160 ) Via1_VV ;
+ - vga_clock.col_index\[0\] ( _1498_ D ) ( _1374_ Q ) + USE SIGNAL
+ + ROUTED Metal2 ( 528080 263760 ) ( * 271600 )
+ NEW Metal2 ( 521360 271600 ) ( 528080 * )
+ NEW Metal1 ( 528080 263760 ) Via1_HV
+ NEW Metal1 ( 521360 271600 ) Via1_HV ;
+ - vga_clock.col_index\[1\] ( _1499_ D ) ( _1373_ Q ) + USE SIGNAL
+ + ROUTED Metal2 ( 513520 248080 ) ( * 255920 )
+ NEW Metal2 ( 513520 255920 ) ( 519120 * )
+ NEW Metal1 ( 513520 248080 ) Via1_HV
+ NEW Metal1 ( 519120 255920 ) Via1_HV ;
+ - vga_clock.col_index_q\[0\] ( _1498_ Q ) ( _1359_ A2 ) ( _1357_ I ) + USE SIGNAL
+ + ROUTED Metal2 ( 548240 248080 ) ( 549360 * )
+ NEW Metal2 ( 549360 248080 ) ( * 261520 )
+ NEW Metal2 ( 549360 248080 ) ( 553840 * )
+ NEW Metal1 ( 548240 248080 ) Via1_VV
+ NEW Metal1 ( 549360 261520 ) Via1_HV
+ NEW Metal1 ( 553840 248080 ) Via1_VV ;
+ - vga_clock.col_index_q\[1\] ( _1499_ Q ) ( _1361_ A1 ) ( _1360_ A3 ) + USE SIGNAL
+ + ROUTED Metal3 ( 534800 239120 ) ( 543760 * )
+ NEW Metal2 ( 534800 239120 ) ( * 245840 )
+ NEW Metal2 ( 540400 231280 ) ( * 239120 )
+ NEW Metal1 ( 543760 239120 ) Via1_VV
+ NEW Metal2 ( 543760 239120 ) Via2_VH
+ NEW Metal2 ( 534800 239120 ) Via2_VH
+ NEW Metal1 ( 534800 245840 ) Via1_HV
+ NEW Metal1 ( 540400 231280 ) Via1_VV
+ NEW Metal2 ( 540400 239120 ) Via2_VH
+ NEW Metal2 ( 543760 239120 ) RECT ( -280 -660 280 0 )
+ NEW Metal3 ( 540400 239120 ) RECT ( -1040 -280 0 280 ) ;
+ - vga_clock.color\[0\] ( ANTENNA__0845__A1 I ) ( _1372_ Q ) ( _0845_ A1 ) + USE SIGNAL
+ + ROUTED Metal2 ( 31920 294000 ) ( * 295120 )
+ NEW Metal3 ( 31920 295120 ) ( 36400 * )
+ NEW Metal2 ( 156240 295120 ) ( * 302960 )
+ NEW Metal3 ( 36400 295120 ) ( 156240 * )
+ NEW Metal1 ( 36400 295120 ) Via1_VV
+ NEW Metal2 ( 36400 295120 ) Via2_VH
+ NEW Metal1 ( 31920 294000 ) Via1_VV
+ NEW Metal2 ( 31920 295120 ) Via2_VH
+ NEW Metal2 ( 156240 295120 ) Via2_VH
+ NEW Metal1 ( 156240 302960 ) Via1_HV
+ NEW Metal2 ( 36400 295120 ) RECT ( -280 -660 280 0 ) ;
+ - vga_clock.color\[1\] ( ANTENNA__0847__A1 I ) ( _1368_ Q ) ( _0847_ A1 ) + USE SIGNAL
+ + ROUTED Metal3 ( 33040 52080 ) ( 38640 * )
+ NEW Metal3 ( 38640 52080 ) ( 118160 * )
+ NEW Metal2 ( 118160 52080 ) ( * 89040 )
+ NEW Metal1 ( 38640 52080 ) Via1_VV
+ NEW Metal2 ( 38640 52080 ) Via2_VH
+ NEW Metal1 ( 33040 52080 ) Via1_VV
+ NEW Metal2 ( 33040 52080 ) Via2_VH
+ NEW Metal2 ( 118160 52080 ) Via2_VH
+ NEW Metal1 ( 118160 89040 ) Via1_HV
+ NEW Metal2 ( 38640 52080 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 33040 52080 ) RECT ( -280 -660 280 0 ) ;
+ - vga_clock.color\[2\] ( _1441_ Q ) ( _0849_ A1 ) + USE SIGNAL
+ + ROUTED Metal2 ( 551600 292880 ) ( * 308560 )
+ NEW Metal3 ( 551600 308560 ) ( 558320 * )
+ NEW Metal2 ( 551600 308560 ) Via2_VH
+ NEW Metal1 ( 551600 292880 ) Via1_HV
+ NEW Metal1 ( 558320 308560 ) Via1_VV
+ NEW Metal2 ( 558320 308560 ) Via2_VH
+ NEW Metal2 ( 558320 308560 ) RECT ( -280 -660 280 0 ) ;
+ - vga_clock.color\[3\] ( _1364_ Q ) ( _0851_ A1 ) + USE SIGNAL
+ + ROUTED Metal3 ( 470960 81200 ) ( 501200 * )
+ NEW Metal2 ( 501200 52080 ) ( * 81200 )
+ NEW Metal2 ( 470960 81200 ) ( * 89040 )
+ NEW Metal2 ( 470960 81200 ) Via2_VH
+ NEW Metal2 ( 501200 81200 ) Via2_VH
+ NEW Metal1 ( 501200 52080 ) Via1_VV
+ NEW Metal1 ( 470960 89040 ) Via1_HV ;
+ - vga_clock.color\[4\] ( _1365_ Q ) ( _0853_ A1 ) + USE SIGNAL
+ + ROUTED Metal2 ( 548240 277200 ) ( * 301840 )
+ NEW Metal3 ( 548240 301840 ) ( 558320 * )
+ NEW Metal2 ( 548240 301840 ) Via2_VH
+ NEW Metal1 ( 548240 277200 ) Via1_HV
+ NEW Metal1 ( 558320 301840 ) Via1_VV
+ NEW Metal2 ( 558320 301840 ) Via2_VH
+ NEW Metal2 ( 558320 301840 ) RECT ( -280 -660 280 0 ) ;
+ - vga_clock.color\[5\] ( ANTENNA__0855__A1 I ) ( _1366_ Q ) ( _0855_ A1 ) + USE SIGNAL
+ + ROUTED Metal2 ( 283920 52080 ) ( 285040 * )
+ NEW Metal3 ( 285040 52080 ) ( 296240 * )
+ NEW Metal3 ( 234640 89040 ) ( 283920 * )
+ NEW Metal2 ( 283920 52080 ) ( * 89040 )
+ NEW Metal1 ( 285040 52080 ) Via1_VV
+ NEW Metal1 ( 296240 52080 ) Via1_VV
+ NEW Metal2 ( 296240 52080 ) Via2_VH
+ NEW Metal2 ( 285040 52080 ) Via2_VH
+ NEW Metal1 ( 234640 89040 ) Via1_HV
+ NEW Metal2 ( 234640 89040 ) Via2_VH
+ NEW Metal2 ( 283920 89040 ) Via2_VH
+ NEW Metal2 ( 296240 52080 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 285040 52080 ) RECT ( -280 -1040 280 0 )
+ NEW Metal2 ( 234640 89040 ) RECT ( -280 -660 280 0 ) ;
+ - vga_clock.color_offset\[0\] ( _1495_ Q ) ( _1344_ A2 ) ( _1343_ A1 ) ( _1341_ A1 ) ( _1340_ A1 ) ( _0676_ I ) + USE SIGNAL
+ + ROUTED Metal2 ( 239120 342160 ) ( * 344400 )
+ NEW Metal3 ( 239120 344400 ) ( 242480 * )
+ NEW Metal3 ( 242480 344400 ) ( * 348880 )
+ NEW Metal3 ( 240240 348880 ) ( 242480 * )
+ NEW Metal2 ( 240240 348880 ) ( * 356720 )
+ NEW Metal2 ( 246960 326480 ) ( * 344400 )
+ NEW Metal3 ( 242480 344400 ) ( 246960 * )
+ NEW Metal2 ( 262640 344400 ) ( * 346640 )
+ NEW Metal3 ( 246960 344400 ) ( 262640 * )
+ NEW Metal2 ( 274960 344400 ) ( * 347760 )
+ NEW Metal3 ( 262640 344400 ) ( 274960 * )
+ NEW Metal2 ( 286160 339920 ) ( * 344400 )
+ NEW Metal3 ( 274960 344400 ) ( 286160 * )
+ NEW Metal1 ( 239120 342160 ) Via1_VV
+ NEW Metal2 ( 239120 344400 ) Via2_VH
+ NEW Metal2 ( 240240 348880 ) Via2_VH
+ NEW Metal1 ( 240240 356720 ) Via1_VV
+ NEW Metal1 ( 246960 326480 ) Via1_VV
+ NEW Metal2 ( 246960 344400 ) Via2_VH
+ NEW Metal1 ( 262640 346640 ) Via1_VV
+ NEW Metal2 ( 262640 344400 ) Via2_VH
+ NEW Metal1 ( 274960 347760 ) Via1_VV
+ NEW Metal2 ( 274960 344400 ) Via2_VH
+ NEW Metal1 ( 286160 339920 ) Via1_HV
+ NEW Metal2 ( 286160 344400 ) Via2_VH ;
+ - vga_clock.color_offset\[1\] ( _1496_ Q ) ( _1344_ A1 ) ( _1343_ B ) ( _0682_ A1 ) ( _0675_ A1 ) + USE SIGNAL
+ + ROUTED Metal2 ( 216720 346640 ) ( * 350000 )
+ NEW Metal3 ( 203280 346640 ) ( 216720 * )
+ NEW Metal2 ( 203280 330960 ) ( * 346640 )
+ NEW Metal2 ( 240240 342160 ) ( * 346640 )
+ NEW Metal3 ( 216720 346640 ) ( 240240 * )
+ NEW Metal2 ( 239120 346640 ) ( * 356720 )
+ NEW Metal2 ( 239120 346640 ) ( 240240 * )
+ NEW Metal2 ( 203280 317520 ) ( * 330960 )
+ NEW Metal1 ( 203280 317520 ) Via1_HV
+ NEW Metal1 ( 203280 330960 ) Via1_VV
+ NEW Metal1 ( 216720 350000 ) Via1_HV
+ NEW Metal2 ( 216720 346640 ) Via2_VH
+ NEW Metal2 ( 203280 346640 ) Via2_VH
+ NEW Metal1 ( 240240 342160 ) Via1_VV
+ NEW Metal2 ( 240240 346640 ) Via2_VH
+ NEW Metal1 ( 239120 356720 ) Via1_VV ;
+ - vga_clock.color_offset\[2\] ( _1497_ Q ) ( _1346_ A1 ) ( _0688_ A1 ) + USE SIGNAL
+ + ROUTED Metal2 ( 202160 343280 ) ( * 346640 )
+ NEW Metal2 ( 202160 327600 ) ( * 333200 )
+ NEW Metal2 ( 198800 348880 ) ( * 350000 )
+ NEW Metal2 ( 188720 350000 ) ( 198800 * )
+ NEW Metal2 ( 198800 346640 ) ( * 348880 )
+ NEW Metal2 ( 201040 326480 ) ( * 327600 )
+ NEW Metal2 ( 201040 333200 ) ( * 343280 )
+ NEW Metal2 ( 201040 327600 ) ( 202160 * )
+ NEW Metal2 ( 201040 333200 ) ( 202160 * )
+ NEW Metal2 ( 201040 343280 ) ( 202160 * )
+ NEW Metal2 ( 198800 346640 ) ( 202160 * )
+ NEW Metal1 ( 198800 348880 ) Via1_HV
+ NEW Metal1 ( 188720 350000 ) Via1_HV
+ NEW Metal1 ( 201040 326480 ) Via1_HV ;
+ - vga_clock.digit_0.char\[0\] ( _1508_ D ) ( _0810_ A2 ) ( _0673_ A1 ) ( _0672_ ZN ) + USE SIGNAL
+ + ROUTED Metal3 ( 289520 311920 ) ( 307440 * )
+ NEW Metal2 ( 279440 309680 ) ( * 311920 )
+ NEW Metal3 ( 279440 311920 ) ( 289520 * )
+ NEW Metal2 ( 307440 326480 ) ( * 352240 )
+ NEW Metal3 ( 307440 352240 ) ( 316400 * )
+ NEW Metal2 ( 316400 352240 ) ( * 356720 )
+ NEW Metal2 ( 307440 311920 ) ( * 326480 )
+ NEW Metal1 ( 289520 311920 ) Via1_VV
+ NEW Metal2 ( 289520 311920 ) Via2_VH
+ NEW Metal2 ( 307440 311920 ) Via2_VH
+ NEW Metal1 ( 279440 309680 ) Via1_HV
+ NEW Metal2 ( 279440 311920 ) Via2_VH
+ NEW Metal1 ( 307440 326480 ) Via1_HV
+ NEW Metal2 ( 307440 352240 ) Via2_VH
+ NEW Metal2 ( 316400 352240 ) Via2_VH
+ NEW Metal1 ( 316400 356720 ) Via1_HV
+ NEW Metal2 ( 289520 311920 ) RECT ( -280 -660 280 0 ) ;
+ - vga_clock.digit_0.char\[1\] ( ANTENNA__0675__A2 I ) ( ANTENNA__0682__A2 I ) ( ANTENNA__0781__A1 I ) ( ANTENNA__0788__A3 I ) ( ANTENNA__1509__D I ) ( _1509_ D ) ( _0788_ A3 )
+ ( _0781_ A1 ) ( _0682_ A2 ) ( _0675_ A2 ) ( _0674_ Z ) + USE SIGNAL
+ + ROUTED Metal3 ( 208880 318640 ) ( 287280 * )
+ NEW Metal3 ( 257040 362320 ) ( 268240 * )
+ NEW Metal2 ( 288400 350000 ) ( 289520 * )
+ NEW Metal2 ( 289520 350000 ) ( * 362320 )
+ NEW Metal3 ( 268240 362320 ) ( 289520 * )
+ NEW Metal2 ( 297360 342160 ) ( * 354480 )
+ NEW Metal3 ( 289520 354480 ) ( 297360 * )
+ NEW Metal2 ( 287280 350000 ) ( 288400 * )
+ NEW Metal2 ( 208880 319760 ) ( * 330960 )
+ NEW Metal2 ( 204400 330960 ) ( * 332080 )
+ NEW Metal2 ( 204400 330960 ) ( 208880 * )
+ NEW Metal3 ( 208880 317520 ) ( * 319760 )
+ NEW Metal2 ( 287280 318640 ) ( * 350000 )
+ NEW Metal3 ( 178640 317520 ) ( 193200 * )
+ NEW Metal3 ( 193200 317520 ) ( 198800 * )
+ NEW Metal3 ( 198800 317520 ) ( 208880 * )
+ NEW Metal2 ( 188720 317520 ) ( * 324240 )
+ NEW Metal2 ( 287280 318640 ) Via2_VH
+ NEW Metal1 ( 285040 318640 ) Via1_VV
+ NEW Metal2 ( 285040 318640 ) Via2_VH
+ NEW Metal1 ( 268240 362320 ) Via1_VV
+ NEW Metal2 ( 268240 362320 ) Via2_VH
+ NEW Metal1 ( 257040 362320 ) Via1_VV
+ NEW Metal2 ( 257040 362320 ) Via2_VH
+ NEW Metal1 ( 288400 350000 ) Via1_VV
+ NEW Metal2 ( 289520 362320 ) Via2_VH
+ NEW Metal1 ( 297360 342160 ) Via1_VV
+ NEW Metal2 ( 297360 354480 ) Via2_VH
+ NEW Metal2 ( 289520 354480 ) Via2_VH
+ NEW Metal1 ( 208880 330960 ) Via1_VV
+ NEW Metal2 ( 208880 319760 ) Via2_VH
+ NEW Metal1 ( 204400 332080 ) Via1_VV
+ NEW Metal1 ( 193200 317520 ) Via1_VV
+ NEW Metal2 ( 193200 317520 ) Via2_VH
+ NEW Metal1 ( 178640 317520 ) Via1_HV
+ NEW Metal2 ( 178640 317520 ) Via2_VH
+ NEW Metal2 ( 188720 317520 ) Via2_VH
+ NEW Metal1 ( 198800 317520 ) Via1_VV
+ NEW Metal2 ( 198800 317520 ) Via2_VH
+ NEW Metal1 ( 188720 324240 ) Via1_VV
+ NEW Metal2 ( 285040 318640 ) RECT ( -280 -660 280 0 )
+ NEW Metal3 ( 285040 318640 ) RECT ( -1040 -280 0 280 )
+ NEW Metal2 ( 268240 362320 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 257040 362320 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 289520 354480 ) RECT ( -280 -1040 280 0 )
+ NEW Metal2 ( 193200 317520 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 178640 317520 ) RECT ( -280 -660 280 0 )
+ NEW Metal3 ( 188720 317520 ) RECT ( -1040 -280 0 280 )
+ NEW Metal2 ( 198800 317520 ) RECT ( -280 -660 280 0 ) ;
+ - vga_clock.digit_0.char\[2\] ( ANTENNA__0688__A3 I ) ( ANTENNA__0777__A2 I ) ( ANTENNA__0780__A1 I ) ( ANTENNA__0781__A2 I ) ( ANTENNA__0795__A1 I ) ( ANTENNA__1510__D I ) ( _1510_ D )
+ ( _0795_ A1 ) ( _0781_ A2 ) ( _0780_ A1 ) ( _0777_ A2 ) ( _0688_ A3 ) ( _0687_ Z ) + USE SIGNAL
+ + ROUTED Metal3 ( 213360 325360 ) ( 227920 * )
+ NEW Metal3 ( 227920 325360 ) ( 261520 * )
+ NEW Metal3 ( 261520 319760 ) ( 274960 * )
+ NEW Metal2 ( 282800 319760 ) ( * 324240 )
+ NEW Metal3 ( 274960 319760 ) ( 282800 * )
+ NEW Metal3 ( 282800 324240 ) ( 294000 * )
+ NEW Metal2 ( 296240 324240 ) ( * 332080 )
+ NEW Metal3 ( 294000 324240 ) ( 296240 * )
+ NEW Metal2 ( 282800 324240 ) ( * 357840 )
+ NEW Metal2 ( 262640 357840 ) ( * 362320 )
+ NEW Metal3 ( 262640 357840 ) ( 282800 * )
+ NEW Metal2 ( 287280 357840 ) ( * 362320 )
+ NEW Metal3 ( 282800 357840 ) ( 287280 * )
+ NEW Metal2 ( 258160 362320 ) ( * 363440 )
+ NEW Metal2 ( 258160 362320 ) ( 262640 * )
+ NEW Metal2 ( 277200 357840 ) ( * 364560 )
+ NEW Metal2 ( 280560 370160 ) ( * 371280 )
+ NEW Metal2 ( 278320 370160 ) ( 280560 * )
+ NEW Metal2 ( 278320 364560 ) ( * 370160 )
+ NEW Metal2 ( 277200 364560 ) ( 278320 * )
+ NEW Metal2 ( 261520 318640 ) ( * 325360 )
+ NEW Metal2 ( 274960 317520 ) ( * 319760 )
+ NEW Metal1 ( 261520 318640 ) Via1_HV
+ NEW Metal1 ( 274960 317520 ) Via1_VV
+ NEW Metal1 ( 227920 325360 ) Via1_VV
+ NEW Metal2 ( 227920 325360 ) Via2_VH
+ NEW Metal1 ( 213360 325360 ) Via1_HV
+ NEW Metal2 ( 213360 325360 ) Via2_VH
+ NEW Metal2 ( 261520 325360 ) Via2_VH
+ NEW Metal2 ( 274960 319760 ) Via2_VH
+ NEW Metal2 ( 261520 319760 ) Via2_VH
+ NEW Metal1 ( 282800 324240 ) Via1_VV
+ NEW Metal2 ( 282800 319760 ) Via2_VH
+ NEW Metal1 ( 294000 324240 ) Via1_VV
+ NEW Metal2 ( 294000 324240 ) Via2_VH
+ NEW Metal2 ( 282800 324240 ) Via2_VH
+ NEW Metal1 ( 296240 332080 ) Via1_HV
+ NEW Metal2 ( 296240 324240 ) Via2_VH
+ NEW Metal1 ( 282800 357840 ) Via1_VV
+ NEW Metal1 ( 262640 362320 ) Via1_VV
+ NEW Metal2 ( 262640 357840 ) Via2_VH
+ NEW Metal2 ( 282800 357840 ) Via2_VH
+ NEW Metal1 ( 287280 362320 ) Via1_VV
+ NEW Metal2 ( 287280 357840 ) Via2_VH
+ NEW Metal1 ( 258160 363440 ) Via1_VV
+ NEW Metal1 ( 277200 364560 ) Via1_VV
+ NEW Metal2 ( 277200 357840 ) Via2_VH
+ NEW Metal1 ( 280560 371280 ) Via1_VV
+ NEW Metal2 ( 227920 325360 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 213360 325360 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 261520 319760 ) RECT ( -280 0 280 1040 )
+ NEW Metal2 ( 294000 324240 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 282800 324240 ) RECT ( -280 -1040 280 0 )
+ NEW Metal2 ( 282800 357840 ) RECT ( -280 -1040 280 0 )
+ NEW Metal3 ( 277200 357840 ) RECT ( -1040 -280 0 280 ) ;
+ - vga_clock.digit_0.char\[3\] ( ANTENNA__0785__C I ) ( ANTENNA__0798__A1 I ) ( ANTENNA__0874__A2 I ) ( ANTENNA__0876__A2 I ) ( ANTENNA__1511__D I ) ( _1511_ D ) ( _0876_ A2 )
+ ( _0874_ A2 ) ( _0798_ A1 ) ( _0785_ C ) ( _0776_ Z ) + USE SIGNAL
+ + ROUTED Metal2 ( 313040 295120 ) ( 314160 * )
+ NEW Metal2 ( 314160 257040 ) ( * 295120 )
+ NEW Metal2 ( 314160 295120 ) ( * 319200 )
+ NEW Metal3 ( 302960 356720 ) ( 311920 * )
+ NEW Metal2 ( 311920 319200 ) ( * 356720 )
+ NEW Metal2 ( 311920 319200 ) ( 314160 * )
+ NEW Metal2 ( 317520 356720 ) ( * 362320 )
+ NEW Metal3 ( 311920 356720 ) ( 317520 * )
+ NEW Metal2 ( 297360 356720 ) ( * 362320 )
+ NEW Metal3 ( 297360 356720 ) ( 302960 * )
+ NEW Metal2 ( 297360 362320 ) ( * 372400 )
+ NEW Metal3 ( 314160 257040 ) ( 319200 * )
+ NEW Metal3 ( 319200 255920 ) ( * 257040 )
+ NEW Metal2 ( 429520 255920 ) ( * 257040 )
+ NEW Metal3 ( 418320 257040 ) ( 429520 * )
+ NEW Metal3 ( 418320 255920 ) ( * 257040 )
+ NEW Metal3 ( 429520 257040 ) ( 441840 * )
+ NEW Metal2 ( 451920 257040 ) ( * 261520 )
+ NEW Metal3 ( 441840 257040 ) ( 451920 * )
+ NEW Metal2 ( 451920 249200 ) ( 453040 * )
+ NEW Metal2 ( 451920 249200 ) ( * 257040 )
+ NEW Metal2 ( 463120 255920 ) ( * 257040 )
+ NEW Metal3 ( 451920 257040 ) ( 463120 * )
+ NEW Metal3 ( 319200 255920 ) ( 418320 * )
+ NEW Metal2 ( 457520 257040 ) ( * 270480 )
+ NEW Metal1 ( 313040 295120 ) Via1_HV
+ NEW Metal2 ( 314160 257040 ) Via2_VH
+ NEW Metal1 ( 457520 270480 ) Via1_VV
+ NEW Metal1 ( 302960 356720 ) Via1_HV
+ NEW Metal2 ( 302960 356720 ) Via2_VH
+ NEW Metal2 ( 311920 356720 ) Via2_VH
+ NEW Metal1 ( 317520 362320 ) Via1_VV
+ NEW Metal2 ( 317520 356720 ) Via2_VH
+ NEW Metal1 ( 297360 362320 ) Via1_VV
+ NEW Metal2 ( 297360 356720 ) Via2_VH
+ NEW Metal1 ( 297360 372400 ) Via1_HV
+ NEW Metal1 ( 429520 255920 ) Via1_VV
+ NEW Metal2 ( 429520 257040 ) Via2_VH
+ NEW Metal1 ( 441840 257040 ) Via1_VV
+ NEW Metal2 ( 441840 257040 ) Via2_VH
+ NEW Metal1 ( 451920 261520 ) Via1_VV
+ NEW Metal2 ( 451920 257040 ) Via2_VH
+ NEW Metal1 ( 453040 249200 ) Via1_VV
+ NEW Metal1 ( 463120 255920 ) Via1_HV
+ NEW Metal2 ( 463120 257040 ) Via2_VH
+ NEW Metal2 ( 457520 257040 ) Via2_VH
+ NEW Metal2 ( 302960 356720 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 441840 257040 ) RECT ( -280 -660 280 0 )
+ NEW Metal3 ( 457520 257040 ) RECT ( -1040 -280 0 280 ) ;
+ - vga_clock.digit_0.digit_index\[0\] ( ANTENNA__0705__A1 I ) ( ANTENNA__0728__A1 I ) ( _1462_ Q ) ( _0728_ A1 ) ( _0705_ A1 ) + USE SIGNAL
+ + ROUTED Metal2 ( 446320 269360 ) ( * 277200 )
+ NEW Metal3 ( 446320 269360 ) ( 455280 * )
+ NEW Metal2 ( 465360 146160 ) ( * 149520 )
+ NEW Metal2 ( 460880 149520 ) ( 465360 * )
+ NEW Metal2 ( 454160 158480 ) ( 455280 * )
+ NEW Metal2 ( 455280 155120 ) ( 460880 * )
+ NEW Metal2 ( 455280 146160 ) ( * 158480 )
+ NEW Metal2 ( 455280 158480 ) ( * 269360 )
+ NEW Metal2 ( 460880 149520 ) ( * 155120 )
+ NEW Metal1 ( 446320 277200 ) Via1_HV
+ NEW Metal2 ( 446320 269360 ) Via2_VH
+ NEW Metal2 ( 455280 269360 ) Via2_VH
+ NEW Metal1 ( 455280 146160 ) Via1_VV
+ NEW Metal1 ( 465360 146160 ) Via1_VV
+ NEW Metal1 ( 454160 158480 ) Via1_VV
+ NEW Metal1 ( 460880 152880 ) Via1_HV
+ NEW Metal2 ( 460880 152880 ) RECT ( -280 -1040 280 0 ) ;
+ - vga_clock.digit_0.digit_index\[1\] ( ANTENNA__0702__A2 I ) ( ANTENNA__0707__I I ) ( _1463_ Q ) ( _0707_ I ) ( _0702_ A2 ) + USE SIGNAL
+ + ROUTED Metal2 ( 432880 139440 ) ( * 146160 )
+ NEW Metal3 ( 403760 146160 ) ( 432880 * )
+ NEW Metal2 ( 403760 146160 ) ( * 151200 )
+ NEW Metal2 ( 401520 155120 ) ( 402640 * )
+ NEW Metal2 ( 402640 155120 ) ( * 201040 )
+ NEW Metal2 ( 401520 201040 ) ( 402640 * )
+ NEW Metal2 ( 401520 201040 ) ( * 218960 )
+ NEW Metal2 ( 401520 218960 ) ( 402640 * )
+ NEW Metal2 ( 402640 218960 ) ( * 261520 )
+ NEW Metal2 ( 400400 261520 ) ( 402640 * )
+ NEW Metal2 ( 402640 151200 ) ( 403760 * )
+ NEW Metal2 ( 402640 151200 ) ( * 155120 )
+ NEW Metal2 ( 407120 151200 ) ( * 151760 )
+ NEW Metal2 ( 403760 151200 ) ( 407120 * )
+ NEW Metal1 ( 403760 146160 ) Via1_HV
+ NEW Metal1 ( 432880 139440 ) Via1_VV
+ NEW Metal2 ( 432880 146160 ) Via2_VH
+ NEW Metal2 ( 403760 146160 ) Via2_VH
+ NEW Metal1 ( 401520 155120 ) Via1_VV
+ NEW Metal1 ( 400400 261520 ) Via1_HV
+ NEW Metal1 ( 407120 151760 ) Via1_VV
+ NEW Metal2 ( 403760 146160 ) RECT ( -280 -1040 280 0 ) ;
+ - vga_clock.digit_0.digit_index\[2\] ( _1464_ Q ) ( _0730_ A1 ) ( _0709_ A1 ) ( _0700_ A1 ) + USE SIGNAL
+ + ROUTED Metal2 ( 429520 170800 ) ( * 171920 )
+ NEW Metal2 ( 426160 171920 ) ( 429520 * )
+ NEW Metal2 ( 426160 171920 ) ( * 185360 )
+ NEW Metal3 ( 417200 185360 ) ( 426160 * )
+ NEW Metal2 ( 417200 185360 ) ( * 193200 )
+ NEW Metal3 ( 429520 169680 ) ( 439600 * )
+ NEW Metal2 ( 429520 169680 ) ( * 170800 )
+ NEW Metal2 ( 429520 152880 ) ( * 169680 )
+ NEW Metal1 ( 429520 170800 ) Via1_VV
+ NEW Metal2 ( 426160 185360 ) Via2_VH
+ NEW Metal2 ( 417200 185360 ) Via2_VH
+ NEW Metal1 ( 417200 193200 ) Via1_HV
+ NEW Metal1 ( 439600 169680 ) Via1_HV
+ NEW Metal2 ( 439600 169680 ) Via2_VH
+ NEW Metal2 ( 429520 169680 ) Via2_VH
+ NEW Metal1 ( 429520 152880 ) Via1_HV
+ NEW Metal2 ( 439600 169680 ) RECT ( -280 -660 280 0 ) ;
+ - vga_clock.digit_0.digit_index\[3\] ( _1465_ Q ) ( _0726_ A1 ) ( _0714_ A1 ) ( _0713_ A1 ) + USE SIGNAL
+ + ROUTED Metal2 ( 423920 190960 ) ( * 202160 )
+ NEW Metal3 ( 408240 202160 ) ( 423920 * )
+ NEW Metal2 ( 408240 202160 ) ( * 230160 )
+ NEW Metal2 ( 422800 185360 ) ( 423920 * )
+ NEW Metal2 ( 423920 185360 ) ( * 190960 )
+ NEW Metal2 ( 432880 185360 ) ( * 202160 )
+ NEW Metal3 ( 423920 202160 ) ( 432880 * )
+ NEW Metal1 ( 423920 190960 ) Via1_VV
+ NEW Metal2 ( 423920 202160 ) Via2_VH
+ NEW Metal2 ( 408240 202160 ) Via2_VH
+ NEW Metal1 ( 408240 230160 ) Via1_HV
+ NEW Metal1 ( 422800 185360 ) Via1_VV
+ NEW Metal1 ( 432880 185360 ) Via1_HV
+ NEW Metal2 ( 432880 202160 ) Via2_VH ;
+ - vga_clock.digit_0.digit_index\[4\] ( _1466_ Q ) ( _0717_ A1 ) ( _0697_ A1 ) + USE SIGNAL
+ + ROUTED Metal2 ( 413840 223440 ) ( 416080 * )
+ NEW Metal2 ( 413840 223440 ) ( * 255920 )
+ NEW Metal2 ( 413840 255920 ) ( 414960 * )
+ NEW Metal3 ( 416080 217840 ) ( 420560 * )
+ NEW Metal2 ( 416080 217840 ) ( * 223440 )
+ NEW Metal1 ( 416080 223440 ) Via1_HV
+ NEW Metal1 ( 414960 255920 ) Via1_HV
+ NEW Metal1 ( 420560 217840 ) Via1_VV
+ NEW Metal2 ( 420560 217840 ) Via2_VH
+ NEW Metal2 ( 416080 217840 ) Via2_VH
+ NEW Metal2 ( 420560 217840 ) RECT ( -280 -660 280 0 ) ;
+ - vga_clock.digit_0.digit_index\[5\] ( _1367_ Q ) ( _0723_ A1 ) + USE SIGNAL
+ + ROUTED Metal2 ( 429520 280560 ) ( * 287280 )
+ NEW Metal2 ( 429520 280560 ) ( 434000 * )
+ NEW Metal2 ( 434000 216720 ) ( * 280560 )
+ NEW Metal1 ( 429520 287280 ) Via1_HV
+ NEW Metal1 ( 434000 216720 ) Via1_HV ;
+ - vga_clock.digit_0.number\[0\] ( ANTENNA__0820__A1 I ) ( ANTENNA__0829__A1 I ) ( ANTENNA__0868__A1 I ) ( ANTENNA__1462__D I ) ( _1462_ D ) ( _0868_ A1 ) ( _0829_ A1 )
+ ( _0820_ A1 ) ( _0793_ Z ) + USE SIGNAL
+ + ROUTED Metal3 ( 403760 279440 ) ( 425040 * )
+ NEW Metal2 ( 381360 279440 ) ( * 286160 )
+ NEW Metal3 ( 381360 279440 ) ( 403760 * )
+ NEW Metal3 ( 373520 279440 ) ( 381360 * )
+ NEW Metal2 ( 375760 279440 ) ( * 299600 )
+ NEW Metal3 ( 366800 299600 ) ( 375760 * )
+ NEW Metal3 ( 364560 294000 ) ( 375760 * )
+ NEW Metal2 ( 346640 287280 ) ( * 292880 )
+ NEW Metal3 ( 346640 292880 ) ( 364560 * )
+ NEW Metal3 ( 364560 292880 ) ( * 294000 )
+ NEW Metal2 ( 339920 292880 ) ( * 295120 )
+ NEW Metal3 ( 339920 292880 ) ( 346640 * )
+ NEW Metal1 ( 403760 279440 ) Via1_VV
+ NEW Metal2 ( 403760 279440 ) Via2_VH
+ NEW Metal1 ( 425040 279440 ) Via1_HV
+ NEW Metal2 ( 425040 279440 ) Via2_VH
+ NEW Metal1 ( 381360 286160 ) Via1_HV
+ NEW Metal2 ( 381360 279440 ) Via2_VH
+ NEW Metal1 ( 373520 279440 ) Via1_VV
+ NEW Metal2 ( 373520 279440 ) Via2_VH
+ NEW Metal1 ( 375760 299600 ) Via1_VV
+ NEW Metal2 ( 375760 279440 ) Via2_VH
+ NEW Metal1 ( 366800 299600 ) Via1_VV
+ NEW Metal2 ( 366800 299600 ) Via2_VH
+ NEW Metal2 ( 375760 299600 ) Via2_VH
+ NEW Metal1 ( 364560 294000 ) Via1_HV
+ NEW Metal2 ( 364560 294000 ) Via2_VH
+ NEW Metal2 ( 375760 294000 ) Via2_VH
+ NEW Metal1 ( 346640 287280 ) Via1_VV
+ NEW Metal2 ( 346640 292880 ) Via2_VH
+ NEW Metal1 ( 339920 295120 ) Via1_VV
+ NEW Metal2 ( 339920 292880 ) Via2_VH
+ NEW Metal2 ( 403760 279440 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 425040 279440 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 373520 279440 ) RECT ( -280 -660 280 0 )
+ NEW Metal3 ( 375760 279440 ) RECT ( -1040 -280 0 280 )
+ NEW Metal2 ( 366800 299600 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 375760 299600 ) RECT ( -280 -1040 280 0 )
+ NEW Metal2 ( 364560 294000 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 375760 294000 ) RECT ( -280 -1040 280 0 ) ;
+ - vga_clock.digit_0.number\[1\] ( _1463_ D ) ( _0868_ A2 ) ( _0829_ A2 ) ( _0827_ A1 ) ( _0806_ Z ) + USE SIGNAL
+ + ROUTED Metal2 ( 379120 260400 ) ( * 261520 )
+ NEW Metal3 ( 363440 260400 ) ( 379120 * )
+ NEW Metal2 ( 363440 254800 ) ( * 260400 )
+ NEW Metal2 ( 366800 260400 ) ( * 294000 )
+ NEW Metal2 ( 367920 294000 ) ( * 300720 )
+ NEW Metal2 ( 366800 294000 ) ( 367920 * )
+ NEW Metal2 ( 367920 300720 ) ( * 310800 )
+ NEW Metal1 ( 379120 261520 ) Via1_HV
+ NEW Metal2 ( 379120 260400 ) Via2_VH
+ NEW Metal2 ( 363440 260400 ) Via2_VH
+ NEW Metal1 ( 363440 254800 ) Via1_HV
+ NEW Metal1 ( 366800 294000 ) Via1_VV
+ NEW Metal2 ( 366800 260400 ) Via2_VH
+ NEW Metal1 ( 367920 300720 ) Via1_VV
+ NEW Metal1 ( 367920 310800 ) Via1_VV
+ NEW Metal3 ( 366800 260400 ) RECT ( -1040 -280 0 280 ) ;
+ - vga_clock.digit_0.x_block\[0\] ( ANTENNA__0876__A1 I ) ( ANTENNA__1100__A3 I ) ( ANTENNA__1506__D I ) ( _1506_ D ) ( _1415_ Q ) ( _1100_ A3 ) ( _0876_ A1 ) + USE SIGNAL
+ + ROUTED Metal2 ( 447440 271600 ) ( * 272720 )
+ NEW Metal2 ( 455280 271600 ) ( * 272720 )
+ NEW Metal3 ( 447440 272720 ) ( 455280 * )
+ NEW Metal2 ( 459760 272720 ) ( * 277200 )
+ NEW Metal3 ( 455280 272720 ) ( 459760 * )
+ NEW Metal2 ( 455280 272720 ) ( * 283920 )
+ NEW Metal2 ( 367920 271600 ) ( * 272720 )
+ NEW Metal3 ( 362320 272720 ) ( 367920 * )
+ NEW Metal3 ( 319760 261520 ) ( 367920 * )
+ NEW Metal2 ( 367920 261520 ) ( * 271600 )
+ NEW Metal3 ( 367920 272720 ) ( 447440 * )
+ NEW Metal1 ( 447440 271600 ) Via1_VV
+ NEW Metal2 ( 447440 272720 ) Via2_VH
+ NEW Metal1 ( 455280 271600 ) Via1_VV
+ NEW Metal2 ( 455280 272720 ) Via2_VH
+ NEW Metal1 ( 459760 277200 ) Via1_HV
+ NEW Metal2 ( 459760 272720 ) Via2_VH
+ NEW Metal1 ( 455280 283920 ) Via1_VV
+ NEW Metal1 ( 367920 271600 ) Via1_VV
+ NEW Metal2 ( 367920 272720 ) Via2_VH
+ NEW Metal1 ( 362320 272720 ) Via1_VV
+ NEW Metal2 ( 362320 272720 ) Via2_VH
+ NEW Metal1 ( 319760 261520 ) Via1_HV
+ NEW Metal2 ( 319760 261520 ) Via2_VH
+ NEW Metal2 ( 367920 261520 ) Via2_VH
+ NEW Metal2 ( 362320 272720 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 319760 261520 ) RECT ( -280 -660 280 0 ) ;
+ - vga_clock.digit_0.x_block\[1\] ( ANTENNA__0874__A1 I ) ( ANTENNA__1100__A2 I ) ( ANTENNA__1507__D I ) ( _1507_ D ) ( _1416_ Q ) ( _1100_ A2 ) ( _0874_ A1 ) + USE SIGNAL
+ + ROUTED Metal2 ( 365680 261520 ) ( * 270480 )
+ NEW Metal2 ( 361200 270480 ) ( 365680 * )
+ NEW Metal2 ( 374640 268240 ) ( * 269360 )
+ NEW Metal3 ( 365680 268240 ) ( 374640 * )
+ NEW Metal2 ( 420560 255920 ) ( * 268240 )
+ NEW Metal3 ( 420560 255920 ) ( 435120 * )
+ NEW Metal2 ( 437360 255920 ) ( * 261520 )
+ NEW Metal2 ( 435120 255920 ) ( 437360 * )
+ NEW Metal2 ( 437360 255920 ) ( 439600 * )
+ NEW Metal3 ( 374640 268240 ) ( 420560 * )
+ NEW Metal1 ( 365680 261520 ) Via1_HV
+ NEW Metal1 ( 361200 270480 ) Via1_VV
+ NEW Metal1 ( 374640 269360 ) Via1_VV
+ NEW Metal2 ( 374640 268240 ) Via2_VH
+ NEW Metal2 ( 365680 268240 ) Via2_VH
+ NEW Metal1 ( 420560 255920 ) Via1_VV
+ NEW Metal2 ( 420560 268240 ) Via2_VH
+ NEW Metal1 ( 435120 255920 ) Via1_VV
+ NEW Metal2 ( 435120 255920 ) Via2_VH
+ NEW Metal2 ( 420560 255920 ) Via2_VH
+ NEW Metal1 ( 437360 261520 ) Via1_HV
+ NEW Metal1 ( 439600 255920 ) Via1_VV
+ NEW Metal2 ( 365680 268240 ) RECT ( -280 -1040 280 0 )
+ NEW Metal2 ( 435120 255920 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 420560 255920 ) RECT ( -280 -1040 280 0 ) ;
+ - vga_clock.draw ( _1514_ Q ) ( _0843_ B ) + USE SIGNAL
+ + ROUTED Metal3 ( 325360 214480 ) ( 353360 * )
+ NEW Metal2 ( 325360 201040 ) ( * 214480 )
+ NEW Metal1 ( 353360 214480 ) Via1_HV
+ NEW Metal2 ( 353360 214480 ) Via2_VH
+ NEW Metal2 ( 325360 214480 ) Via2_VH
+ NEW Metal1 ( 325360 201040 ) Via1_VV
+ NEW Metal2 ( 353360 214480 ) RECT ( -280 -660 280 0 ) ;
+ - vga_clock.font_0.dout\[1\] ( _1369_ Q ) ( _1360_ A2 ) + USE SIGNAL
+ + ROUTED Metal2 ( 543760 214480 ) ( * 231280 )
+ NEW Metal1 ( 543760 214480 ) Via1_HV
+ NEW Metal1 ( 543760 231280 ) Via1_HV ;
+ - vga_clock.font_0.dout\[2\] ( _1370_ Q ) ( _1358_ A1 ) + USE SIGNAL
+ + ROUTED Metal2 ( 559440 208880 ) ( 563920 * )
+ NEW Metal2 ( 559440 208880 ) ( * 239120 )
+ NEW Metal1 ( 563920 208880 ) Via1_HV
+ NEW Metal1 ( 559440 239120 ) Via1_HV ;
+ - vga_clock.font_0.dout\[3\] ( _1371_ Q ) ( _1359_ A1 ) + USE SIGNAL
+ + ROUTED Metal2 ( 524720 230160 ) ( * 246960 )
+ NEW Metal3 ( 524720 246960 ) ( 544880 * )
+ NEW Metal1 ( 524720 230160 ) Via1_HV
+ NEW Metal2 ( 524720 246960 ) Via2_VH
+ NEW Metal1 ( 544880 246960 ) Via1_HV
+ NEW Metal2 ( 544880 246960 ) Via2_VH
+ NEW Metal2 ( 544880 246960 ) RECT ( -280 -660 280 0 ) ;
+ - vga_clock.hrs_d\[0\] ( ANTENNA__0792__I0 I ) ( ANTENNA__1262__A2 I ) ( ANTENNA__1350__A1 I ) ( ANTENNA__1352__A1 I ) ( _1512_ Q ) ( _1352_ A1 ) ( _1350_ A1 )
+ ( _1262_ A2 ) ( _0792_ I0 ) + USE SIGNAL
+ + ROUTED Metal2 ( 372400 311920 ) ( 373520 * )
+ NEW Metal3 ( 346640 319760 ) ( 373520 * )
+ NEW Metal2 ( 373520 319760 ) ( * 325360 )
+ NEW Metal3 ( 373520 330960 ) ( 385840 * )
+ NEW Metal2 ( 373520 325360 ) ( * 330960 )
+ NEW Metal2 ( 392560 325360 ) ( * 330960 )
+ NEW Metal3 ( 385840 330960 ) ( 392560 * )
+ NEW Metal3 ( 392560 323120 ) ( 412720 * )
+ NEW Metal2 ( 392560 323120 ) ( * 325360 )
+ NEW Metal2 ( 412720 323120 ) ( * 330960 )
+ NEW Metal2 ( 417200 323120 ) ( * 326480 )
+ NEW Metal3 ( 412720 323120 ) ( 417200 * )
+ NEW Metal2 ( 422800 323120 ) ( * 324240 )
+ NEW Metal3 ( 417200 323120 ) ( 422800 * )
+ NEW Metal2 ( 346640 310800 ) ( * 319760 )
+ NEW Metal2 ( 373520 311920 ) ( * 319760 )
+ NEW Metal2 ( 412720 302960 ) ( * 323120 )
+ NEW Metal1 ( 346640 310800 ) Via1_HV
+ NEW Metal1 ( 372400 311920 ) Via1_VV
+ NEW Metal1 ( 412720 302960 ) Via1_HV
+ NEW Metal2 ( 373520 319760 ) Via2_VH
+ NEW Metal2 ( 346640 319760 ) Via2_VH
+ NEW Metal1 ( 373520 325360 ) Via1_HV
+ NEW Metal1 ( 385840 330960 ) Via1_VV
+ NEW Metal2 ( 385840 330960 ) Via2_VH
+ NEW Metal2 ( 373520 330960 ) Via2_VH
+ NEW Metal1 ( 392560 325360 ) Via1_HV
+ NEW Metal2 ( 392560 330960 ) Via2_VH
+ NEW Metal2 ( 412720 323120 ) Via2_VH
+ NEW Metal2 ( 392560 323120 ) Via2_VH
+ NEW Metal1 ( 412720 330960 ) Via1_VV
+ NEW Metal1 ( 417200 326480 ) Via1_VV
+ NEW Metal2 ( 417200 323120 ) Via2_VH
+ NEW Metal1 ( 422800 324240 ) Via1_VV
+ NEW Metal2 ( 422800 323120 ) Via2_VH
+ NEW Metal2 ( 385840 330960 ) RECT ( -280 -660 280 0 ) ;
+ - vga_clock.hrs_d\[1\] ( _1513_ Q ) ( _1353_ A1 ) ( _0794_ I ) + USE SIGNAL
+ + ROUTED Metal3 ( 386960 318640 ) ( 403760 * )
+ NEW Metal2 ( 403760 318640 ) ( * 319200 )
+ NEW Metal2 ( 402640 319200 ) ( * 333200 )
+ NEW Metal2 ( 402640 319200 ) ( 403760 * )
+ NEW Metal1 ( 403760 318640 ) Via1_HV
+ NEW Metal2 ( 403760 318640 ) Via2_VH
+ NEW Metal1 ( 386960 318640 ) Via1_VV
+ NEW Metal2 ( 386960 318640 ) Via2_VH
+ NEW Metal1 ( 402640 333200 ) Via1_HV
+ NEW Metal2 ( 403760 318640 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 386960 318640 ) RECT ( -280 -660 280 0 ) ;
+ - vga_clock.hrs_u\[0\] ( _1477_ Q ) ( _0787_ I ) + USE SIGNAL
+ + ROUTED Metal2 ( 427280 397040 ) ( 428400 * )
+ NEW Metal2 ( 427280 390320 ) ( * 397040 )
+ NEW Metal1 ( 428400 397040 ) Via1_HV
+ NEW Metal1 ( 427280 390320 ) Via1_VV ;
+ - vga_clock.hrs_u\[1\] ( _1478_ Q ) ( _1278_ A2 ) ( _1273_ A1 ) ( _1263_ A2 ) ( _1260_ A1 ) ( _0802_ I ) + USE SIGNAL
+ + ROUTED Metal3 ( 360080 346640 ) ( 376880 * )
+ NEW Metal2 ( 376880 342160 ) ( * 346640 )
+ NEW Metal2 ( 361200 358960 ) ( * 364560 )
+ NEW Metal3 ( 361200 358960 ) ( 365680 * )
+ NEW Metal2 ( 365680 346640 ) ( * 358960 )
+ NEW Metal2 ( 361200 371280 ) ( 363440 * )
+ NEW Metal2 ( 361200 364560 ) ( * 371280 )
+ NEW Metal2 ( 380240 371280 ) ( * 373520 )
+ NEW Metal3 ( 363440 371280 ) ( 380240 * )
+ NEW Metal2 ( 366800 381360 ) ( 367920 * )
+ NEW Metal2 ( 366800 371280 ) ( * 381360 )
+ NEW Metal1 ( 360080 346640 ) Via1_VV
+ NEW Metal2 ( 360080 346640 ) Via2_VH
+ NEW Metal2 ( 376880 346640 ) Via2_VH
+ NEW Metal1 ( 376880 342160 ) Via1_VV
+ NEW Metal1 ( 361200 364560 ) Via1_HV
+ NEW Metal2 ( 361200 358960 ) Via2_VH
+ NEW Metal2 ( 365680 358960 ) Via2_VH
+ NEW Metal2 ( 365680 346640 ) Via2_VH
+ NEW Metal1 ( 363440 371280 ) Via1_VV
+ NEW Metal1 ( 380240 373520 ) Via1_VV
+ NEW Metal2 ( 380240 371280 ) Via2_VH
+ NEW Metal2 ( 363440 371280 ) Via2_VH
+ NEW Metal1 ( 367920 381360 ) Via1_HV
+ NEW Metal2 ( 366800 371280 ) Via2_VH
+ NEW Metal2 ( 360080 346640 ) RECT ( -280 -660 280 0 )
+ NEW Metal3 ( 365680 346640 ) RECT ( -1040 -280 0 280 )
+ NEW Metal2 ( 363440 371280 ) RECT ( -280 -1040 280 0 )
+ NEW Metal3 ( 366800 371280 ) RECT ( -1040 -280 0 280 ) ;
+ - vga_clock.hrs_u\[2\] ( ANTENNA__0810__A1 I ) ( ANTENNA__1261__A2 I ) ( ANTENNA__1264__A1 I ) ( ANTENNA__1276__A1 I ) ( ANTENNA__1278__A1 I ) ( ANTENNA__1279__A1 I ) ( _1479_ Q )
+ ( _1279_ A1 ) ( _1278_ A1 ) ( _1276_ A1 ) ( _1264_ A1 ) ( _1261_ A2 ) ( _0810_ A1 ) + USE SIGNAL
+ + ROUTED Metal2 ( 335440 358960 ) ( * 362320 )
+ NEW Metal3 ( 328720 358960 ) ( 335440 * )
+ NEW Metal3 ( 328720 357840 ) ( * 358960 )
+ NEW Metal2 ( 362320 344400 ) ( * 347760 )
+ NEW Metal3 ( 335440 344400 ) ( 362320 * )
+ NEW Metal2 ( 335440 344400 ) ( * 358960 )
+ NEW Metal2 ( 363440 343280 ) ( * 344400 )
+ NEW Metal2 ( 362320 344400 ) ( 363440 * )
+ NEW Metal2 ( 367920 344400 ) ( * 346640 )
+ NEW Metal3 ( 362320 344400 ) ( 367920 * )
+ NEW Metal2 ( 375760 344400 ) ( * 357840 )
+ NEW Metal3 ( 367920 344400 ) ( 375760 * )
+ NEW Metal2 ( 375760 357840 ) ( * 362320 )
+ NEW Metal2 ( 389200 343280 ) ( * 344400 )
+ NEW Metal3 ( 375760 344400 ) ( 389200 * )
+ NEW Metal2 ( 400400 344400 ) ( * 355600 )
+ NEW Metal3 ( 389200 344400 ) ( 400400 * )
+ NEW Metal2 ( 400400 355600 ) ( * 364560 )
+ NEW Metal2 ( 406000 344400 ) ( * 346640 )
+ NEW Metal3 ( 400400 344400 ) ( 406000 * )
+ NEW Metal2 ( 413840 362320 ) ( 414960 * )
+ NEW Metal2 ( 413840 344400 ) ( * 362320 )
+ NEW Metal3 ( 406000 344400 ) ( 413840 * )
+ NEW Metal2 ( 419440 354480 ) ( * 355600 )
+ NEW Metal1 ( 413840 354480 ) ( 419440 * )
+ NEW Metal3 ( 318640 357840 ) ( 328720 * )
+ NEW Metal1 ( 318640 357840 ) Via1_VV
+ NEW Metal2 ( 318640 357840 ) Via2_VH
+ NEW Metal1 ( 335440 362320 ) Via1_VV
+ NEW Metal2 ( 335440 358960 ) Via2_VH
+ NEW Metal1 ( 362320 347760 ) Via1_VV
+ NEW Metal2 ( 362320 344400 ) Via2_VH
+ NEW Metal2 ( 335440 344400 ) Via2_VH
+ NEW Metal1 ( 363440 343280 ) Via1_VV
+ NEW Metal1 ( 367920 346640 ) Via1_VV
+ NEW Metal2 ( 367920 344400 ) Via2_VH
+ NEW Metal1 ( 375760 357840 ) Via1_VV
+ NEW Metal2 ( 375760 344400 ) Via2_VH
+ NEW Metal1 ( 375760 362320 ) Via1_VV
+ NEW Metal1 ( 389200 343280 ) Via1_VV
+ NEW Metal2 ( 389200 344400 ) Via2_VH
+ NEW Metal1 ( 400400 355600 ) Via1_VV
+ NEW Metal2 ( 400400 344400 ) Via2_VH
+ NEW Metal1 ( 400400 364560 ) Via1_HV
+ NEW Metal1 ( 406000 346640 ) Via1_HV
+ NEW Metal2 ( 406000 344400 ) Via2_VH
+ NEW Metal1 ( 414960 362320 ) Via1_VV
+ NEW Metal2 ( 413840 344400 ) Via2_VH
+ NEW Metal1 ( 419440 355600 ) Via1_VV
+ NEW Metal1 ( 419440 354480 ) Via1_HV
+ NEW Metal1 ( 413840 354480 ) Via1_HV
+ NEW Metal2 ( 318640 357840 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 413840 354480 ) RECT ( -280 -1040 280 0 ) ;
+ - vga_clock.hrs_u\[3\] ( _1480_ Q ) ( _1263_ A1 ) ( _0817_ I ) + USE SIGNAL
+ + ROUTED Metal2 ( 376880 333200 ) ( 379120 * )
+ NEW Metal2 ( 379120 333200 ) ( * 342160 )
+ NEW Metal2 ( 378000 342160 ) ( 379120 * )
+ NEW Metal3 ( 367920 334320 ) ( 376880 * )
+ NEW Metal2 ( 376880 333200 ) ( * 334320 )
+ NEW Metal1 ( 376880 333200 ) Via1_VV
+ NEW Metal1 ( 378000 342160 ) Via1_VV
+ NEW Metal1 ( 367920 334320 ) Via1_HV
+ NEW Metal2 ( 367920 334320 ) Via2_VH
+ NEW Metal2 ( 376880 334320 ) Via2_VH
+ NEW Metal2 ( 367920 334320 ) RECT ( -280 -660 280 0 ) ;
+ - vga_clock.min_d\[0\] ( ANTENNA__0786__A1 I ) ( ANTENNA__1267__A1 I ) ( ANTENNA__1268__A1 I ) ( ANTENNA__1282__A1 I ) ( ANTENNA__1285__A1 I ) ( ANTENNA__1287__A2 I ) ( ANTENNA__1288__A1 I )
+ ( _1481_ Q ) ( _1288_ A1 ) ( _1287_ A2 ) ( _1285_ A1 ) ( _1282_ A1 ) ( _1268_ A1 ) ( _1267_ A1 ) ( _0786_ A1 ) + USE SIGNAL
+ + ROUTED Metal2 ( 390320 400400 ) ( * 402640 )
+ NEW Metal2 ( 390320 400400 ) ( 392560 * )
+ NEW Metal2 ( 392560 378000 ) ( * 400400 )
+ NEW Metal2 ( 392560 378000 ) ( 395920 * )
+ NEW Metal2 ( 395920 378000 ) ( * 380240 )
+ NEW Metal2 ( 385840 402640 ) ( 390320 * )
+ NEW Metal2 ( 380240 402640 ) ( 385840 * )
+ NEW Metal2 ( 376880 394800 ) ( * 395920 )
+ NEW Metal2 ( 376880 395920 ) ( 378000 * )
+ NEW Metal2 ( 378000 395920 ) ( * 402640 )
+ NEW Metal2 ( 378000 402640 ) ( 380240 * )
+ NEW Metal2 ( 353360 397040 ) ( 355600 * )
+ NEW Metal2 ( 355600 397040 ) ( * 406000 )
+ NEW Metal3 ( 355600 406000 ) ( 378000 * )
+ NEW Metal2 ( 378000 402640 ) ( * 406000 )
+ NEW Metal2 ( 346640 395920 ) ( * 406000 )
+ NEW Metal3 ( 346640 406000 ) ( 355600 * )
+ NEW Metal2 ( 346640 406000 ) ( * 411600 )
+ NEW Metal2 ( 353360 417200 ) ( * 418320 )
+ NEW Metal2 ( 353360 417200 ) ( 355600 * )
+ NEW Metal2 ( 355600 406000 ) ( * 417200 )
+ NEW Metal3 ( 335440 418320 ) ( 353360 * )
+ NEW Metal2 ( 337680 418320 ) ( * 425040 )
+ NEW Metal2 ( 323120 418320 ) ( * 419440 )
+ NEW Metal3 ( 323120 418320 ) ( 335440 * )
+ NEW Metal2 ( 326480 426160 ) ( * 428400 )
+ NEW Metal2 ( 323120 428400 ) ( 326480 * )
+ NEW Metal2 ( 323120 419440 ) ( * 428400 )
+ NEW Metal2 ( 343280 365680 ) ( 344400 * )
+ NEW Metal2 ( 344400 365680 ) ( * 395920 )
+ NEW Metal2 ( 344400 395920 ) ( 346640 * )
+ NEW Metal3 ( 329840 363440 ) ( 343280 * )
+ NEW Metal2 ( 343280 363440 ) ( * 365680 )
+ NEW Metal1 ( 390320 402640 ) Via1_VV
+ NEW Metal1 ( 395920 380240 ) Via1_HV
+ NEW Metal1 ( 385840 402640 ) Via1_VV
+ NEW Metal1 ( 380240 402640 ) Via1_HV
+ NEW Metal1 ( 376880 394800 ) Via1_VV
+ NEW Metal1 ( 353360 397040 ) Via1_VV
+ NEW Metal2 ( 355600 406000 ) Via2_VH
+ NEW Metal2 ( 378000 406000 ) Via2_VH
+ NEW Metal1 ( 346640 395920 ) Via1_VV
+ NEW Metal2 ( 346640 406000 ) Via2_VH
+ NEW Metal1 ( 346640 411600 ) Via1_HV
+ NEW Metal1 ( 353360 418320 ) Via1_VV
+ NEW Metal1 ( 335440 418320 ) Via1_VV
+ NEW Metal2 ( 335440 418320 ) Via2_VH
+ NEW Metal2 ( 353360 418320 ) Via2_VH
+ NEW Metal1 ( 337680 425040 ) Via1_VV
+ NEW Metal2 ( 337680 418320 ) Via2_VH
+ NEW Metal1 ( 323120 419440 ) Via1_HV
+ NEW Metal2 ( 323120 418320 ) Via2_VH
+ NEW Metal1 ( 326480 426160 ) Via1_VV
+ NEW Metal1 ( 343280 365680 ) Via1_VV
+ NEW Metal1 ( 329840 363440 ) Via1_VV
+ NEW Metal2 ( 329840 363440 ) Via2_VH
+ NEW Metal2 ( 343280 363440 ) Via2_VH
+ NEW Metal2 ( 335440 418320 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 353360 418320 ) RECT ( -280 -1040 280 0 )
+ NEW Metal3 ( 337680 418320 ) RECT ( -1040 -280 0 280 )
+ NEW Metal2 ( 329840 363440 ) RECT ( -280 -660 280 0 ) ;
+ - vga_clock.min_d\[1\] ( _1482_ Q ) ( _1287_ A1 ) ( _1259_ A2 ) ( _0800_ I ) + USE SIGNAL
+ + ROUTED Metal3 ( 327600 402640 ) ( 330960 * )
+ NEW Metal2 ( 330960 395920 ) ( * 402640 )
+ NEW Metal2 ( 325360 402640 ) ( * 420560 )
+ NEW Metal3 ( 325360 402640 ) ( 327600 * )
+ NEW Metal2 ( 327600 434000 ) ( 328720 * )
+ NEW Metal2 ( 327600 420560 ) ( * 434000 )
+ NEW Metal2 ( 325360 420560 ) ( 327600 * )
+ NEW Metal1 ( 327600 402640 ) Via1_VV
+ NEW Metal2 ( 327600 402640 ) Via2_VH
+ NEW Metal2 ( 330960 402640 ) Via2_VH
+ NEW Metal1 ( 330960 395920 ) Via1_HV
+ NEW Metal1 ( 325360 420560 ) Via1_VV
+ NEW Metal2 ( 325360 402640 ) Via2_VH
+ NEW Metal1 ( 328720 434000 ) Via1_HV
+ NEW Metal2 ( 327600 402640 ) RECT ( -280 -660 280 0 ) ;
+ - vga_clock.min_d\[2\] ( _1483_ Q ) ( _1292_ A1 ) ( _1259_ A1 ) ( _0811_ A1 ) + USE SIGNAL
+ + ROUTED Metal2 ( 315280 374640 ) ( * 403760 )
+ NEW Metal2 ( 325360 394800 ) ( * 397040 )
+ NEW Metal3 ( 325360 394800 ) ( 332080 * )
+ NEW Metal3 ( 315280 397040 ) ( 325360 * )
+ NEW Metal1 ( 315280 403760 ) Via1_HV
+ NEW Metal1 ( 315280 374640 ) Via1_VV
+ NEW Metal2 ( 315280 397040 ) Via2_VH
+ NEW Metal1 ( 325360 397040 ) Via1_HV
+ NEW Metal2 ( 325360 394800 ) Via2_VH
+ NEW Metal1 ( 332080 394800 ) Via1_HV
+ NEW Metal2 ( 332080 394800 ) Via2_VH
+ NEW Metal2 ( 325360 397040 ) Via2_VH
+ NEW Metal2 ( 315280 397040 ) RECT ( -280 -1040 280 0 )
+ NEW Metal2 ( 332080 394800 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 325360 397040 ) RECT ( -280 -1040 280 0 ) ;
+ - vga_clock.min_u\[0\] ( _1484_ Q ) ( _1298_ A1 ) ( _1297_ A1 ) ( _1284_ A2 ) ( _0785_ A1 ) + USE SIGNAL
+ + ROUTED Metal2 ( 292880 373520 ) ( * 403760 )
+ NEW Metal2 ( 289520 373520 ) ( 292880 * )
+ NEW Metal2 ( 288400 403760 ) ( * 418320 )
+ NEW Metal2 ( 288400 403760 ) ( 292880 * )
+ NEW Metal2 ( 288400 418320 ) ( * 434000 )
+ NEW Metal3 ( 281680 432880 ) ( 288400 * )
+ NEW Metal1 ( 292880 403760 ) Via1_VV
+ NEW Metal1 ( 289520 373520 ) Via1_HV
+ NEW Metal1 ( 288400 418320 ) Via1_HV
+ NEW Metal1 ( 288400 434000 ) Via1_VV
+ NEW Metal1 ( 281680 432880 ) Via1_VV
+ NEW Metal2 ( 281680 432880 ) Via2_VH
+ NEW Metal2 ( 288400 432880 ) Via2_VH
+ NEW Metal2 ( 281680 432880 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 288400 432880 ) RECT ( -280 -1040 280 0 ) ;
+ - vga_clock.min_u\[1\] ( ANTENNA__0796__A1 I ) ( ANTENNA__1283__A2 I ) ( ANTENNA__1303__A1 I ) ( ANTENNA__1304__A1 I ) ( ANTENNA__1305__A1 I ) ( ANTENNA__1306__A2 I ) ( _1485_ Q )
+ ( _1306_ A2 ) ( _1305_ A1 ) ( _1304_ A1 ) ( _1303_ A1 ) ( _1283_ A2 ) ( _0796_ A1 ) + USE SIGNAL
+ + ROUTED Metal2 ( 285040 450800 ) ( * 457520 )
+ NEW Metal3 ( 285040 453040 ) ( 292880 * )
+ NEW Metal2 ( 288400 453040 ) ( * 465360 )
+ NEW Metal2 ( 292880 465360 ) ( 294000 * )
+ NEW Metal2 ( 292880 453040 ) ( * 465360 )
+ NEW Metal2 ( 300720 451920 ) ( * 453040 )
+ NEW Metal3 ( 292880 453040 ) ( 300720 * )
+ NEW Metal2 ( 300720 453040 ) ( * 457520 )
+ NEW Metal2 ( 300720 457520 ) ( * 472080 )
+ NEW Metal3 ( 300720 453040 ) ( 313040 * )
+ NEW Metal3 ( 270480 403760 ) ( 285040 * )
+ NEW Metal3 ( 266000 403760 ) ( 270480 * )
+ NEW Metal2 ( 287280 388080 ) ( * 404880 )
+ NEW Metal2 ( 285040 404880 ) ( 287280 * )
+ NEW Metal3 ( 287280 388080 ) ( 297360 * )
+ NEW Metal2 ( 285040 403760 ) ( * 450800 )
+ NEW Metal1 ( 285040 450800 ) Via1_VV
+ NEW Metal1 ( 285040 457520 ) Via1_VV
+ NEW Metal1 ( 292880 453040 ) Via1_VV
+ NEW Metal2 ( 292880 453040 ) Via2_VH
+ NEW Metal2 ( 285040 453040 ) Via2_VH
+ NEW Metal1 ( 288400 465360 ) Via1_VV
+ NEW Metal2 ( 288400 453040 ) Via2_VH
+ NEW Metal1 ( 294000 465360 ) Via1_HV
+ NEW Metal1 ( 300720 451920 ) Via1_VV
+ NEW Metal2 ( 300720 453040 ) Via2_VH
+ NEW Metal1 ( 300720 457520 ) Via1_HV
+ NEW Metal1 ( 300720 472080 ) Via1_VV
+ NEW Metal1 ( 313040 453040 ) Via1_VV
+ NEW Metal2 ( 313040 453040 ) Via2_VH
+ NEW Metal1 ( 270480 403760 ) Via1_VV
+ NEW Metal2 ( 270480 403760 ) Via2_VH
+ NEW Metal2 ( 285040 403760 ) Via2_VH
+ NEW Metal1 ( 266000 403760 ) Via1_VV
+ NEW Metal2 ( 266000 403760 ) Via2_VH
+ NEW Metal1 ( 287280 388080 ) Via1_HV
+ NEW Metal1 ( 297360 388080 ) Via1_VV
+ NEW Metal2 ( 297360 388080 ) Via2_VH
+ NEW Metal2 ( 287280 388080 ) Via2_VH
+ NEW Metal2 ( 292880 453040 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 285040 453040 ) RECT ( -280 -1040 280 0 )
+ NEW Metal3 ( 288400 453040 ) RECT ( -1040 -280 0 280 )
+ NEW Metal2 ( 313040 453040 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 270480 403760 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 266000 403760 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 297360 388080 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 287280 388080 ) RECT ( -280 0 280 1040 ) ;
+ - vga_clock.min_u\[2\] ( ANTENNA__0808__A1 I ) ( ANTENNA__1284__A1 I ) ( ANTENNA__1305__B I ) ( ANTENNA__1306__A1 I ) ( _1486_ Q ) ( _1306_ A1 ) ( _1305_ B )
+ ( _1284_ A1 ) ( _0808_ A1 ) + USE SIGNAL
+ + ROUTED Metal2 ( 306320 449680 ) ( 308560 * )
+ NEW Metal2 ( 287280 449680 ) ( * 450800 )
+ NEW Metal3 ( 287280 449680 ) ( 306320 * )
+ NEW Metal2 ( 287280 450800 ) ( * 458640 )
+ NEW Metal2 ( 295120 449680 ) ( * 472080 )
+ NEW Metal2 ( 295120 472080 ) ( * 481040 )
+ NEW Metal2 ( 296240 403760 ) ( * 420560 )
+ NEW Metal3 ( 296240 420560 ) ( 306320 * )
+ NEW Metal3 ( 286160 397040 ) ( 296240 * )
+ NEW Metal2 ( 296240 397040 ) ( * 403760 )
+ NEW Metal2 ( 280560 394800 ) ( * 397040 )
+ NEW Metal3 ( 280560 397040 ) ( 286160 * )
+ NEW Metal2 ( 306320 412720 ) ( * 449680 )
+ NEW Metal1 ( 308560 449680 ) Via1_VV
+ NEW Metal1 ( 287280 450800 ) Via1_VV
+ NEW Metal2 ( 287280 449680 ) Via2_VH
+ NEW Metal2 ( 306320 449680 ) Via2_VH
+ NEW Metal1 ( 287280 458640 ) Via1_HV
+ NEW Metal1 ( 295120 472080 ) Via1_VV
+ NEW Metal2 ( 295120 449680 ) Via2_VH
+ NEW Metal1 ( 295120 481040 ) Via1_HV
+ NEW Metal1 ( 306320 412720 ) Via1_VV
+ NEW Metal1 ( 296240 403760 ) Via1_VV
+ NEW Metal2 ( 296240 420560 ) Via2_VH
+ NEW Metal2 ( 306320 420560 ) Via2_VH
+ NEW Metal1 ( 286160 397040 ) Via1_VV
+ NEW Metal2 ( 286160 397040 ) Via2_VH
+ NEW Metal2 ( 296240 397040 ) Via2_VH
+ NEW Metal1 ( 280560 394800 ) Via1_VV
+ NEW Metal2 ( 280560 397040 ) Via2_VH
+ NEW Metal2 ( 306320 449680 ) RECT ( -280 -1040 280 0 )
+ NEW Metal3 ( 295120 449680 ) RECT ( -1040 -280 0 280 )
+ NEW Metal2 ( 306320 420560 ) RECT ( -280 -1040 280 0 )
+ NEW Metal2 ( 286160 397040 ) RECT ( -280 -660 280 0 ) ;
+ - vga_clock.min_u\[3\] ( ANTENNA__0816__A1 I ) ( ANTENNA__1283__A1 I ) ( ANTENNA__1308__A1 I ) ( _1487_ Q ) ( _1308_ A1 ) ( _1283_ A1 ) ( _0816_ A1 ) + USE SIGNAL
+ + ROUTED Metal2 ( 271600 458640 ) ( * 465360 )
+ NEW Metal2 ( 269360 444080 ) ( 270480 * )
+ NEW Metal2 ( 270480 444080 ) ( * 458640 )
+ NEW Metal2 ( 270480 458640 ) ( 271600 * )
+ NEW Metal2 ( 270480 406000 ) ( 271600 * )
+ NEW Metal2 ( 270480 410480 ) ( 277200 * )
+ NEW Metal2 ( 279440 380240 ) ( 280560 * )
+ NEW Metal2 ( 279440 380240 ) ( * 410480 )
+ NEW Metal2 ( 277200 410480 ) ( 279440 * )
+ NEW Metal3 ( 279440 390320 ) ( 291760 * )
+ NEW Metal2 ( 270480 406000 ) ( * 444080 )
+ NEW Metal1 ( 271600 458640 ) Via1_HV
+ NEW Metal1 ( 271600 465360 ) Via1_VV
+ NEW Metal1 ( 269360 444080 ) Via1_HV
+ NEW Metal1 ( 271600 406000 ) Via1_VV
+ NEW Metal1 ( 277200 410480 ) Via1_VV
+ NEW Metal1 ( 280560 380240 ) Via1_HV
+ NEW Metal1 ( 291760 390320 ) Via1_VV
+ NEW Metal2 ( 291760 390320 ) Via2_VH
+ NEW Metal2 ( 279440 390320 ) Via2_VH
+ NEW Metal2 ( 291760 390320 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 279440 390320 ) RECT ( -280 -1040 280 0 ) ;
+ - vga_clock.pulse_hrs.comp\[0\] ( _1442_ Q ) ( _1132_ B1 ) ( _1130_ B1 ) ( _1113_ A2 ) ( _1112_ A1 ) ( _1111_ A1 ) ( _1110_ A1 ) + USE SIGNAL
+ + ROUTED Metal3 ( 401520 515760 ) ( 427280 * )
+ NEW Metal2 ( 427280 515760 ) ( * 522480 )
+ NEW Metal2 ( 391440 515760 ) ( * 519120 )
+ NEW Metal3 ( 391440 515760 ) ( 401520 * )
+ NEW Metal2 ( 404880 498960 ) ( * 505680 )
+ NEW Metal2 ( 403760 505680 ) ( 404880 * )
+ NEW Metal2 ( 403760 505680 ) ( * 515760 )
+ NEW Metal2 ( 412720 490000 ) ( 417200 * )
+ NEW Metal2 ( 412720 490000 ) ( * 492240 )
+ NEW Metal2 ( 411600 492240 ) ( 412720 * )
+ NEW Metal1 ( 406000 492240 ) ( 411600 * )
+ NEW Metal2 ( 404880 492240 ) ( 406000 * )
+ NEW Metal2 ( 404880 492240 ) ( * 498960 )
+ NEW Metal2 ( 393680 482160 ) ( * 487760 )
+ NEW Metal3 ( 393680 487760 ) ( 404880 * )
+ NEW Metal2 ( 404880 487760 ) ( * 492240 )
+ NEW Metal2 ( 400400 474320 ) ( * 487760 )
+ NEW Metal1 ( 401520 515760 ) Via1_VV
+ NEW Metal2 ( 401520 515760 ) Via2_VH
+ NEW Metal2 ( 427280 515760 ) Via2_VH
+ NEW Metal1 ( 427280 522480 ) Via1_HV
+ NEW Metal1 ( 391440 519120 ) Via1_VV
+ NEW Metal2 ( 391440 515760 ) Via2_VH
+ NEW Metal1 ( 404880 498960 ) Via1_VV
+ NEW Metal2 ( 403760 515760 ) Via2_VH
+ NEW Metal1 ( 417200 490000 ) Via1_VV
+ NEW Metal1 ( 411600 492240 ) Via1_HV
+ NEW Metal1 ( 406000 492240 ) Via1_HV
+ NEW Metal1 ( 393680 482160 ) Via1_VV
+ NEW Metal2 ( 393680 487760 ) Via2_VH
+ NEW Metal2 ( 404880 487760 ) Via2_VH
+ NEW Metal1 ( 400400 474320 ) Via1_HV
+ NEW Metal2 ( 400400 487760 ) Via2_VH
+ NEW Metal2 ( 401520 515760 ) RECT ( -280 -660 280 0 )
+ NEW Metal3 ( 403760 515760 ) RECT ( -1040 -280 0 280 )
+ NEW Metal3 ( 400400 487760 ) RECT ( -1040 -280 0 280 ) ;
+ - vga_clock.pulse_hrs.comp\[1\] ( _1443_ Q ) ( _1131_ A2 ) ( _1113_ A1 ) ( _1112_ B ) + USE SIGNAL
+ + ROUTED Metal2 ( 419440 474320 ) ( * 488880 )
+ NEW Metal2 ( 416080 492240 ) ( * 496720 )
+ NEW Metal2 ( 416080 492240 ) ( 418320 * )
+ NEW Metal2 ( 418320 488880 ) ( * 492240 )
+ NEW Metal2 ( 418320 488880 ) ( 419440 * )
+ NEW Metal2 ( 409360 496720 ) ( * 497840 )
+ NEW Metal2 ( 409360 496720 ) ( 416080 * )
+ NEW Metal1 ( 419440 488880 ) Via1_VV
+ NEW Metal1 ( 419440 474320 ) Via1_HV
+ NEW Metal1 ( 416080 496720 ) Via1_HV
+ NEW Metal1 ( 409360 497840 ) Via1_VV ;
+ - vga_clock.pulse_hrs.comp\[2\] ( _1444_ Q ) ( _1123_ A2 ) ( _1122_ A1 ) ( _1119_ A1 ) ( _1117_ I ) ( _1098_ A3 ) + USE SIGNAL
+ + ROUTED Metal2 ( 366800 492240 ) ( * 497840 )
+ NEW Metal2 ( 382480 504560 ) ( * 505680 )
+ NEW Metal3 ( 366800 504560 ) ( 382480 * )
+ NEW Metal2 ( 366800 497840 ) ( * 504560 )
+ NEW Metal2 ( 376880 504560 ) ( * 512400 )
+ NEW Metal2 ( 385840 507920 ) ( * 513520 )
+ NEW Metal2 ( 382480 507920 ) ( 385840 * )
+ NEW Metal2 ( 382480 505680 ) ( * 507920 )
+ NEW Metal3 ( 390320 498960 ) ( 395920 * )
+ NEW Metal2 ( 390320 498960 ) ( * 504560 )
+ NEW Metal3 ( 382480 504560 ) ( 390320 * )
+ NEW Metal1 ( 366800 497840 ) Via1_VV
+ NEW Metal1 ( 366800 492240 ) Via1_VV
+ NEW Metal1 ( 382480 505680 ) Via1_VV
+ NEW Metal2 ( 382480 504560 ) Via2_VH
+ NEW Metal2 ( 366800 504560 ) Via2_VH
+ NEW Metal1 ( 376880 512400 ) Via1_HV
+ NEW Metal2 ( 376880 504560 ) Via2_VH
+ NEW Metal1 ( 385840 513520 ) Via1_VV
+ NEW Metal1 ( 395920 498960 ) Via1_VV
+ NEW Metal2 ( 395920 498960 ) Via2_VH
+ NEW Metal2 ( 390320 498960 ) Via2_VH
+ NEW Metal2 ( 390320 504560 ) Via2_VH
+ NEW Metal3 ( 376880 504560 ) RECT ( -1040 -280 0 280 )
+ NEW Metal2 ( 395920 498960 ) RECT ( -280 -660 280 0 ) ;
+ - vga_clock.pulse_hrs.comp\[3\] ( _1445_ Q ) ( _1129_ A2 ) ( _1123_ A1 ) ( _1121_ I ) ( _1098_ A2 ) + USE SIGNAL
+ + ROUTED Metal2 ( 363440 490000 ) ( 364560 * )
+ NEW Metal2 ( 363440 465360 ) ( * 490000 )
+ NEW Metal2 ( 369040 485520 ) ( * 497840 )
+ NEW Metal2 ( 363440 485520 ) ( 369040 * )
+ NEW Metal2 ( 360080 500080 ) ( * 504560 )
+ NEW Metal2 ( 360080 500080 ) ( 363440 * )
+ NEW Metal2 ( 363440 490000 ) ( * 500080 )
+ NEW Metal2 ( 353360 506800 ) ( 360080 * )
+ NEW Metal2 ( 360080 504560 ) ( * 506800 )
+ NEW Metal1 ( 364560 490000 ) Via1_VV
+ NEW Metal1 ( 363440 465360 ) Via1_HV
+ NEW Metal1 ( 369040 497840 ) Via1_VV
+ NEW Metal1 ( 360080 504560 ) Via1_VV
+ NEW Metal1 ( 353360 506800 ) Via1_HV ;
+ - vga_clock.pulse_hrs.comp\[4\] ( _1446_ Q ) ( _1133_ A2 ) ( _1126_ A1 ) ( _1098_ A1 ) + USE SIGNAL
+ + ROUTED Metal2 ( 361200 475440 ) ( * 488880 )
+ NEW Metal3 ( 351120 490000 ) ( 361200 * )
+ NEW Metal2 ( 361200 488880 ) ( * 490000 )
+ NEW Metal2 ( 339920 490000 ) ( * 491120 )
+ NEW Metal3 ( 339920 490000 ) ( 351120 * )
+ NEW Metal1 ( 361200 488880 ) Via1_VV
+ NEW Metal1 ( 361200 475440 ) Via1_HV
+ NEW Metal1 ( 351120 490000 ) Via1_VV
+ NEW Metal2 ( 351120 490000 ) Via2_VH
+ NEW Metal2 ( 361200 490000 ) Via2_VH
+ NEW Metal1 ( 339920 491120 ) Via1_HV
+ NEW Metal2 ( 339920 490000 ) Via2_VH
+ NEW Metal2 ( 351120 490000 ) RECT ( -280 -660 280 0 ) ;
+ - vga_clock.pulse_hrs.count\[0\] ( _1447_ Q ) ( _1145_ A3 ) ( _1141_ A2 ) ( _1138_ A1 ) ( _1137_ A1 ) ( _1128_ I ) ( _1096_ A2 ) + USE SIGNAL
+ + ROUTED Metal2 ( 400400 458640 ) ( 401520 * )
+ NEW Metal2 ( 394800 458640 ) ( 400400 * )
+ NEW Metal3 ( 388080 458640 ) ( 394800 * )
+ NEW Metal2 ( 399280 412720 ) ( * 425040 )
+ NEW Metal3 ( 399280 412720 ) ( 404880 * )
+ NEW Metal2 ( 399280 432880 ) ( 400400 * )
+ NEW Metal2 ( 399280 425040 ) ( * 432880 )
+ NEW Metal2 ( 389200 418320 ) ( * 426160 )
+ NEW Metal3 ( 389200 418320 ) ( 399280 * )
+ NEW Metal2 ( 400400 432880 ) ( * 458640 )
+ NEW Metal1 ( 401520 458640 ) Via1_VV
+ NEW Metal1 ( 394800 458640 ) Via1_VV
+ NEW Metal1 ( 388080 458640 ) Via1_VV
+ NEW Metal2 ( 388080 458640 ) Via2_VH
+ NEW Metal2 ( 394800 458640 ) Via2_VH
+ NEW Metal1 ( 399280 425040 ) Via1_VV
+ NEW Metal2 ( 399280 412720 ) Via2_VH
+ NEW Metal1 ( 404880 412720 ) Via1_HV
+ NEW Metal2 ( 404880 412720 ) Via2_VH
+ NEW Metal1 ( 400400 432880 ) Via1_VV
+ NEW Metal1 ( 389200 426160 ) Via1_VV
+ NEW Metal2 ( 389200 418320 ) Via2_VH
+ NEW Metal2 ( 399280 418320 ) Via2_VH
+ NEW Metal2 ( 388080 458640 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 394800 458640 ) RECT ( -280 -1040 280 0 )
+ NEW Metal2 ( 404880 412720 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 399280 418320 ) RECT ( -280 -1040 280 0 ) ;
+ - vga_clock.pulse_hrs.count\[1\] ( _1448_ Q ) ( _1145_ A2 ) ( _1141_ A1 ) ( _1140_ A1 ) ( _1131_ A1 ) ( _1096_ A1 ) + USE SIGNAL
+ + ROUTED Metal3 ( 404880 458640 ) ( 421680 * )
+ NEW Metal2 ( 421680 458640 ) ( * 474320 )
+ NEW Metal3 ( 395920 456400 ) ( 404880 * )
+ NEW Metal3 ( 404880 456400 ) ( * 458640 )
+ NEW Metal3 ( 398160 432880 ) ( 404880 * )
+ NEW Metal2 ( 398160 432880 ) ( * 434000 )
+ NEW Metal2 ( 419440 426160 ) ( * 432880 )
+ NEW Metal3 ( 404880 432880 ) ( 419440 * )
+ NEW Metal2 ( 409360 412720 ) ( 410480 * )
+ NEW Metal2 ( 409360 412720 ) ( * 432880 )
+ NEW Metal2 ( 404880 432880 ) ( * 458640 )
+ NEW Metal1 ( 404880 458640 ) Via1_HV
+ NEW Metal2 ( 404880 458640 ) Via2_VH
+ NEW Metal2 ( 421680 458640 ) Via2_VH
+ NEW Metal1 ( 421680 474320 ) Via1_HV
+ NEW Metal1 ( 395920 456400 ) Via1_VV
+ NEW Metal2 ( 395920 456400 ) Via2_VH
+ NEW Metal2 ( 404880 432880 ) Via2_VH
+ NEW Metal2 ( 398160 432880 ) Via2_VH
+ NEW Metal1 ( 398160 434000 ) Via1_VV
+ NEW Metal1 ( 419440 426160 ) Via1_VV
+ NEW Metal2 ( 419440 432880 ) Via2_VH
+ NEW Metal1 ( 410480 412720 ) Via1_HV
+ NEW Metal2 ( 409360 432880 ) Via2_VH
+ NEW Metal2 ( 404880 458640 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 395920 456400 ) RECT ( -280 -660 280 0 )
+ NEW Metal3 ( 409360 432880 ) RECT ( -1040 -280 0 280 ) ;
+ - vga_clock.pulse_hrs.count\[2\] ( _1449_ Q ) ( _1146_ A1 ) ( _1145_ A1 ) ( _1144_ I ) ( _1132_ A1 ) ( _1130_ A1 ) ( _1097_ A3 ) + USE SIGNAL
+ + ROUTED Metal2 ( 406000 474320 ) ( * 477680 )
+ NEW Metal3 ( 391440 477680 ) ( 406000 * )
+ NEW Metal2 ( 391440 477680 ) ( * 482160 )
+ NEW Metal2 ( 406000 457520 ) ( 407120 * )
+ NEW Metal2 ( 406000 457520 ) ( * 474320 )
+ NEW Metal2 ( 407120 450800 ) ( 408240 * )
+ NEW Metal2 ( 407120 450800 ) ( * 457520 )
+ NEW Metal2 ( 413840 453040 ) ( * 457520 )
+ NEW Metal3 ( 407120 453040 ) ( 413840 * )
+ NEW Metal3 ( 420560 450800 ) ( * 453040 )
+ NEW Metal3 ( 413840 453040 ) ( 420560 * )
+ NEW Metal2 ( 417200 444080 ) ( * 453040 )
+ NEW Metal1 ( 406000 474320 ) Via1_HV
+ NEW Metal2 ( 406000 477680 ) Via2_VH
+ NEW Metal2 ( 391440 477680 ) Via2_VH
+ NEW Metal1 ( 391440 482160 ) Via1_VV
+ NEW Metal1 ( 407120 457520 ) Via1_VV
+ NEW Metal1 ( 408240 450800 ) Via1_HV
+ NEW Metal1 ( 413840 457520 ) Via1_VV
+ NEW Metal2 ( 413840 453040 ) Via2_VH
+ NEW Metal2 ( 407120 453040 ) Via2_VH
+ NEW Metal1 ( 420560 450800 ) Via1_VV
+ NEW Metal2 ( 420560 450800 ) Via2_VH
+ NEW Metal1 ( 417200 444080 ) Via1_VV
+ NEW Metal2 ( 417200 453040 ) Via2_VH
+ NEW Metal2 ( 407120 453040 ) RECT ( -280 -1040 280 0 )
+ NEW Metal2 ( 420560 450800 ) RECT ( -280 -660 280 0 )
+ NEW Metal3 ( 417200 453040 ) RECT ( -1040 -280 0 280 ) ;
+ - vga_clock.pulse_hrs.count\[3\] ( _1450_ Q ) ( _1153_ A1 ) ( _1150_ A1 ) ( _1149_ B ) ( _1129_ A1 ) ( _1097_ A2 ) + USE SIGNAL
+ + ROUTED Metal3 ( 356720 450800 ) ( 370160 * )
+ NEW Metal2 ( 364560 442960 ) ( * 450800 )
+ NEW Metal2 ( 364560 450800 ) ( * 466480 )
+ NEW Metal2 ( 364560 434000 ) ( 365680 * )
+ NEW Metal2 ( 364560 426160 ) ( * 434000 )
+ NEW Metal2 ( 364560 434000 ) ( * 442960 )
+ NEW Metal1 ( 356720 450800 ) Via1_VV
+ NEW Metal2 ( 356720 450800 ) Via2_VH
+ NEW Metal1 ( 370160 450800 ) Via1_HV
+ NEW Metal2 ( 370160 450800 ) Via2_VH
+ NEW Metal1 ( 364560 442960 ) Via1_VV
+ NEW Metal2 ( 364560 450800 ) Via2_VH
+ NEW Metal1 ( 364560 466480 ) Via1_HV
+ NEW Metal1 ( 365680 434000 ) Via1_HV
+ NEW Metal1 ( 364560 426160 ) Via1_VV
+ NEW Metal2 ( 356720 450800 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 370160 450800 ) RECT ( -280 -660 280 0 )
+ NEW Metal3 ( 364560 450800 ) RECT ( -1040 -280 0 280 ) ;
+ - vga_clock.pulse_hrs.count\[4\] ( _1451_ Q ) ( _1155_ A1 ) ( _1154_ B ) ( _1133_ A1 ) ( _1097_ A1 ) + USE SIGNAL
+ + ROUTED Metal2 ( 381360 457520 ) ( 382480 * )
+ NEW Metal2 ( 382480 451920 ) ( * 457520 )
+ NEW Metal2 ( 356720 456400 ) ( * 458640 )
+ NEW Metal3 ( 356720 456400 ) ( 382480 * )
+ NEW Metal2 ( 347760 456400 ) ( * 459760 )
+ NEW Metal3 ( 347760 456400 ) ( 356720 * )
+ NEW Metal2 ( 356720 474320 ) ( 357840 * )
+ NEW Metal2 ( 356720 458640 ) ( * 474320 )
+ NEW Metal1 ( 381360 457520 ) Via1_VV
+ NEW Metal1 ( 382480 451920 ) Via1_VV
+ NEW Metal1 ( 356720 458640 ) Via1_VV
+ NEW Metal2 ( 356720 456400 ) Via2_VH
+ NEW Metal2 ( 382480 456400 ) Via2_VH
+ NEW Metal1 ( 347760 459760 ) Via1_HV
+ NEW Metal2 ( 347760 456400 ) Via2_VH
+ NEW Metal1 ( 357840 474320 ) Via1_HV
+ NEW Metal2 ( 382480 456400 ) RECT ( -280 -1040 280 0 ) ;
+ - vga_clock.pulse_min.comp\[0\] ( _1452_ Q ) ( _1166_ I ) ( _1164_ A1 ) ( _1163_ A1 ) ( _1162_ A1 ) + USE SIGNAL
+ + ROUTED Metal2 ( 458640 500080 ) ( 465360 * )
+ NEW Metal2 ( 465360 490000 ) ( * 500080 )
+ NEW Metal2 ( 465360 490000 ) ( 467600 * )
+ NEW Metal2 ( 460880 500080 ) ( * 503440 )
+ NEW Metal2 ( 462000 500080 ) ( * 512400 )
+ NEW Metal2 ( 462000 512400 ) ( * 519120 )
+ NEW Metal1 ( 458640 500080 ) Via1_VV
+ NEW Metal1 ( 467600 490000 ) Via1_VV
+ NEW Metal1 ( 460880 503440 ) Via1_VV
+ NEW Metal1 ( 462000 512400 ) Via1_HV
+ NEW Metal1 ( 462000 519120 ) Via1_VV ;
+ - vga_clock.pulse_min.comp\[1\] ( _1453_ Q ) ( _1184_ B1 ) ( _1165_ I ) ( _1164_ B ) + USE SIGNAL
+ + ROUTED Metal2 ( 475440 477680 ) ( * 481040 )
+ NEW Metal3 ( 475440 477680 ) ( 488880 * )
+ NEW Metal2 ( 488880 474320 ) ( * 477680 )
+ NEW Metal2 ( 463120 477680 ) ( * 481040 )
+ NEW Metal3 ( 463120 477680 ) ( 475440 * )
+ NEW Metal2 ( 463120 481040 ) ( * 497840 )
+ NEW Metal1 ( 475440 481040 ) Via1_VV
+ NEW Metal2 ( 475440 477680 ) Via2_VH
+ NEW Metal2 ( 488880 477680 ) Via2_VH
+ NEW Metal1 ( 488880 474320 ) Via1_HV
+ NEW Metal1 ( 463120 481040 ) Via1_HV
+ NEW Metal2 ( 463120 477680 ) Via2_VH
+ NEW Metal1 ( 463120 497840 ) Via1_VV ;
+ - vga_clock.pulse_min.comp\[2\] ( _1454_ Q ) ( _1185_ A2 ) ( _1176_ A2 ) ( _1175_ A1 ) ( _1172_ A1 ) ( _1171_ A1 ) ( _1158_ A3 ) + USE SIGNAL
+ + ROUTED Metal2 ( 503440 479920 ) ( 506800 * )
+ NEW Metal2 ( 503440 465360 ) ( * 479920 )
+ NEW Metal2 ( 507920 497840 ) ( 509040 * )
+ NEW Metal2 ( 509040 479920 ) ( * 497840 )
+ NEW Metal3 ( 506800 479920 ) ( 509040 * )
+ NEW Metal2 ( 504560 506800 ) ( 506800 * )
+ NEW Metal2 ( 506800 504560 ) ( * 506800 )
+ NEW Metal2 ( 506800 504560 ) ( 509040 * )
+ NEW Metal2 ( 509040 497840 ) ( * 504560 )
+ NEW Metal2 ( 504560 506800 ) ( * 522480 )
+ NEW Metal2 ( 477680 479920 ) ( * 498960 )
+ NEW Metal3 ( 477680 479920 ) ( 506800 * )
+ NEW Metal2 ( 477680 503440 ) ( 478800 * )
+ NEW Metal2 ( 477680 498960 ) ( * 503440 )
+ NEW Metal1 ( 506800 479920 ) Via1_VV
+ NEW Metal1 ( 503440 465360 ) Via1_HV
+ NEW Metal1 ( 507920 497840 ) Via1_VV
+ NEW Metal2 ( 509040 479920 ) Via2_VH
+ NEW Metal2 ( 506800 479920 ) Via2_VH
+ NEW Metal1 ( 504560 506800 ) Via1_VV
+ NEW Metal1 ( 504560 522480 ) Via1_HV
+ NEW Metal1 ( 477680 498960 ) Via1_VV
+ NEW Metal2 ( 477680 479920 ) Via2_VH
+ NEW Metal1 ( 478800 503440 ) Via1_VV
+ NEW Metal2 ( 506800 479920 ) RECT ( -280 -1040 280 0 ) ;
+ - vga_clock.pulse_min.comp\[3\] ( _1455_ Q ) ( _1183_ A2 ) ( _1176_ A1 ) ( _1174_ I ) ( _1158_ A2 ) + USE SIGNAL
+ + ROUTED Metal2 ( 525840 506800 ) ( * 512400 )
+ NEW Metal3 ( 525840 512400 ) ( 540400 * )
+ NEW Metal2 ( 504560 500080 ) ( 505680 * )
+ NEW Metal2 ( 504560 500080 ) ( * 503440 )
+ NEW Metal3 ( 503440 503440 ) ( 504560 * )
+ NEW Metal3 ( 503440 503440 ) ( * 505680 )
+ NEW Metal3 ( 503440 505680 ) ( 525840 * )
+ NEW Metal2 ( 525840 505680 ) ( * 506800 )
+ NEW Metal2 ( 504560 482160 ) ( * 500080 )
+ NEW Metal2 ( 507920 474320 ) ( * 482160 )
+ NEW Metal2 ( 504560 482160 ) ( 507920 * )
+ NEW Metal1 ( 525840 506800 ) Via1_VV
+ NEW Metal2 ( 525840 512400 ) Via2_VH
+ NEW Metal1 ( 540400 512400 ) Via1_HV
+ NEW Metal2 ( 540400 512400 ) Via2_VH
+ NEW Metal1 ( 505680 500080 ) Via1_VV
+ NEW Metal2 ( 504560 503440 ) Via2_VH
+ NEW Metal2 ( 525840 505680 ) Via2_VH
+ NEW Metal1 ( 504560 482160 ) Via1_VV
+ NEW Metal1 ( 507920 474320 ) Via1_VV
+ NEW Metal2 ( 540400 512400 ) RECT ( -280 -660 280 0 ) ;
+ - vga_clock.pulse_min.comp\[4\] ( _1456_ Q ) ( _1181_ I ) ( _1179_ A1 ) ( _1158_ A1 ) + USE SIGNAL
+ + ROUTED Metal2 ( 521360 486640 ) ( * 490000 )
+ NEW Metal3 ( 501200 483280 ) ( 521360 * )
+ NEW Metal2 ( 521360 483280 ) ( * 486640 )
+ NEW Metal3 ( 486640 483280 ) ( 501200 * )
+ NEW Metal2 ( 563920 486640 ) ( * 491120 )
+ NEW Metal3 ( 521360 486640 ) ( 563920 * )
+ NEW Metal1 ( 521360 490000 ) Via1_VV
+ NEW Metal2 ( 521360 486640 ) Via2_VH
+ NEW Metal1 ( 501200 483280 ) Via1_VV
+ NEW Metal2 ( 501200 483280 ) Via2_VH
+ NEW Metal2 ( 521360 483280 ) Via2_VH
+ NEW Metal1 ( 486640 483280 ) Via1_VV
+ NEW Metal2 ( 486640 483280 ) Via2_VH
+ NEW Metal2 ( 563920 486640 ) Via2_VH
+ NEW Metal1 ( 563920 491120 ) Via1_HV
+ NEW Metal2 ( 501200 483280 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 486640 483280 ) RECT ( -280 -660 280 0 ) ;
+ - vga_clock.pulse_min.count\[0\] ( _1457_ Q ) ( _1196_ A2 ) ( _1195_ A3 ) ( _1192_ A2 ) ( _1191_ A1 ) ( _1190_ A1 ) ( _1187_ B2 )
+ ( _1186_ B2 ) ( _1156_ A3 ) + USE SIGNAL
+ + ROUTED Metal2 ( 497840 442960 ) ( 500080 * )
+ NEW Metal2 ( 500080 442960 ) ( * 448560 )
+ NEW Metal2 ( 500080 448560 ) ( 501200 * )
+ NEW Metal2 ( 482160 466480 ) ( 483280 * )
+ NEW Metal2 ( 482160 457520 ) ( * 466480 )
+ NEW Metal2 ( 481040 457520 ) ( 482160 * )
+ NEW Metal3 ( 451920 440720 ) ( 458640 * )
+ NEW Metal2 ( 451920 440720 ) ( * 450800 )
+ NEW Metal2 ( 467600 437360 ) ( * 440720 )
+ NEW Metal3 ( 458640 440720 ) ( 467600 * )
+ NEW Metal2 ( 481040 436800 ) ( * 457520 )
+ NEW Metal3 ( 483280 434000 ) ( 497840 * )
+ NEW Metal2 ( 481040 436800 ) ( 483280 * )
+ NEW Metal2 ( 483280 434000 ) ( * 436800 )
+ NEW Metal3 ( 467600 434000 ) ( 483280 * )
+ NEW Metal2 ( 467600 434000 ) ( * 437360 )
+ NEW Metal2 ( 497840 427280 ) ( * 442960 )
+ NEW Metal1 ( 497840 442960 ) Via1_VV
+ NEW Metal1 ( 501200 448560 ) Via1_VV
+ NEW Metal1 ( 481040 457520 ) Via1_HV
+ NEW Metal1 ( 483280 466480 ) Via1_HV
+ NEW Metal1 ( 458640 440720 ) Via1_VV
+ NEW Metal2 ( 458640 440720 ) Via2_VH
+ NEW Metal2 ( 451920 440720 ) Via2_VH
+ NEW Metal1 ( 451920 450800 ) Via1_VV
+ NEW Metal1 ( 467600 437360 ) Via1_HV
+ NEW Metal2 ( 467600 440720 ) Via2_VH
+ NEW Metal1 ( 497840 427280 ) Via1_VV
+ NEW Metal1 ( 483280 434000 ) Via1_HV
+ NEW Metal2 ( 483280 434000 ) Via2_VH
+ NEW Metal2 ( 497840 434000 ) Via2_VH
+ NEW Metal2 ( 467600 434000 ) Via2_VH
+ NEW Metal2 ( 458640 440720 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 483280 434000 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 497840 434000 ) RECT ( -280 -1040 280 0 ) ;
+ - vga_clock.pulse_min.count\[1\] ( ANTENNA__1156__A2 I ) ( ANTENNA__1182__I I ) ( ANTENNA__1187__A1 I ) ( ANTENNA__1192__A1 I ) ( ANTENNA__1193__A1 I ) ( ANTENNA__1195__A2 I ) ( ANTENNA__1196__A1 I )
+ ( _1458_ Q ) ( _1196_ A1 ) ( _1195_ A2 ) ( _1193_ A1 ) ( _1192_ A1 ) ( _1187_ A1 ) ( _1182_ I ) ( _1156_ A2 ) + USE SIGNAL
+ + ROUTED Metal2 ( 472080 472080 ) ( * 473200 )
+ NEW Metal2 ( 472080 472080 ) ( 473200 * )
+ NEW Metal3 ( 466480 472080 ) ( 472080 * )
+ NEW Metal2 ( 467600 466480 ) ( * 472080 )
+ NEW Metal2 ( 466480 472080 ) ( 467600 * )
+ NEW Metal3 ( 498960 450800 ) ( 513520 * )
+ NEW Metal2 ( 513520 450800 ) ( * 465360 )
+ NEW Metal2 ( 511280 465360 ) ( 513520 * )
+ NEW Metal2 ( 496720 442960 ) ( * 445200 )
+ NEW Metal2 ( 496720 445200 ) ( 498960 * )
+ NEW Metal2 ( 498960 445200 ) ( * 450800 )
+ NEW Metal2 ( 484400 444080 ) ( * 449680 )
+ NEW Metal2 ( 484400 449680 ) ( 487760 * )
+ NEW Metal2 ( 494480 436800 ) ( * 437360 )
+ NEW Metal2 ( 496720 436800 ) ( * 442960 )
+ NEW Metal2 ( 469840 436800 ) ( * 440720 )
+ NEW Metal2 ( 473200 436800 ) ( * 472080 )
+ NEW Metal3 ( 457520 421680 ) ( 475440 * )
+ NEW Metal2 ( 457520 421680 ) ( * 425040 )
+ NEW Metal2 ( 469840 421680 ) ( * 436800 )
+ NEW Metal2 ( 469840 436800 ) ( 473200 * )
+ NEW Metal3 ( 473200 435120 ) ( 478800 * )
+ NEW Metal2 ( 473200 435120 ) ( * 436800 )
+ NEW Metal3 ( 478800 435120 ) ( 486640 * )
+ NEW Metal2 ( 488880 421680 ) ( * 435120 )
+ NEW Metal2 ( 486640 435120 ) ( 488880 * )
+ NEW Metal2 ( 494480 435120 ) ( * 436800 )
+ NEW Metal3 ( 486640 435120 ) ( 494480 * )
+ NEW Metal2 ( 494480 436800 ) ( 496720 * )
+ NEW Metal2 ( 502320 425040 ) ( * 426160 )
+ NEW Metal3 ( 488880 425040 ) ( 502320 * )
+ NEW Metal2 ( 486640 435120 ) ( * 449680 )
+ NEW Metal1 ( 472080 473200 ) Via1_VV
+ NEW Metal1 ( 466480 472080 ) Via1_VV
+ NEW Metal2 ( 466480 472080 ) Via2_VH
+ NEW Metal2 ( 472080 472080 ) Via2_VH
+ NEW Metal1 ( 467600 466480 ) Via1_HV
+ NEW Metal1 ( 498960 450800 ) Via1_VV
+ NEW Metal2 ( 498960 450800 ) Via2_VH
+ NEW Metal2 ( 513520 450800 ) Via2_VH
+ NEW Metal1 ( 511280 465360 ) Via1_VV
+ NEW Metal1 ( 496720 442960 ) Via1_VV
+ NEW Metal1 ( 494480 437360 ) Via1_VV
+ NEW Metal1 ( 484400 444080 ) Via1_VV
+ NEW Metal1 ( 487760 449680 ) Via1_VV
+ NEW Metal1 ( 469840 440720 ) Via1_VV
+ NEW Metal1 ( 475440 421680 ) Via1_HV
+ NEW Metal2 ( 475440 421680 ) Via2_VH
+ NEW Metal2 ( 457520 421680 ) Via2_VH
+ NEW Metal1 ( 457520 425040 ) Via1_VV
+ NEW Metal2 ( 469840 421680 ) Via2_VH
+ NEW Metal1 ( 478800 435120 ) Via1_HV
+ NEW Metal2 ( 478800 435120 ) Via2_VH
+ NEW Metal2 ( 473200 435120 ) Via2_VH
+ NEW Metal2 ( 486640 435120 ) Via2_VH
+ NEW Metal1 ( 488880 421680 ) Via1_VV
+ NEW Metal2 ( 494480 435120 ) Via2_VH
+ NEW Metal1 ( 502320 426160 ) Via1_VV
+ NEW Metal2 ( 502320 425040 ) Via2_VH
+ NEW Metal2 ( 488880 425040 ) Via2_VH
+ NEW Metal2 ( 466480 472080 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 472080 472080 ) RECT ( -280 -1040 280 0 )
+ NEW Metal2 ( 498960 450800 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 475440 421680 ) RECT ( -280 -660 280 0 )
+ NEW Metal3 ( 469840 421680 ) RECT ( -1040 -280 0 280 )
+ NEW Metal2 ( 478800 435120 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 488880 425040 ) RECT ( -280 -1040 280 0 ) ;
+ - vga_clock.pulse_min.count\[2\] ( _1459_ Q ) ( _1198_ A1 ) ( _1196_ B ) ( _1195_ A1 ) ( _1185_ A1 ) ( _1157_ A2 ) + USE SIGNAL
+ + ROUTED Metal2 ( 504560 462000 ) ( * 466480 )
+ NEW Metal2 ( 504560 462000 ) ( 512400 * )
+ NEW Metal2 ( 512400 458640 ) ( * 462000 )
+ NEW Metal2 ( 502320 437360 ) ( * 439600 )
+ NEW Metal2 ( 502320 439600 ) ( 504560 * )
+ NEW Metal2 ( 504560 439600 ) ( * 462000 )
+ NEW Metal3 ( 495600 442960 ) ( 504560 * )
+ NEW Metal2 ( 503440 427280 ) ( * 428400 )
+ NEW Metal2 ( 502320 428400 ) ( 503440 * )
+ NEW Metal2 ( 501200 418320 ) ( * 428400 )
+ NEW Metal2 ( 501200 428400 ) ( 502320 * )
+ NEW Metal2 ( 502320 428400 ) ( * 437360 )
+ NEW Metal1 ( 504560 466480 ) Via1_HV
+ NEW Metal1 ( 512400 458640 ) Via1_HV
+ NEW Metal1 ( 502320 437360 ) Via1_VV
+ NEW Metal1 ( 495600 442960 ) Via1_VV
+ NEW Metal2 ( 495600 442960 ) Via2_VH
+ NEW Metal2 ( 504560 442960 ) Via2_VH
+ NEW Metal1 ( 503440 427280 ) Via1_VV
+ NEW Metal1 ( 501200 418320 ) Via1_HV
+ NEW Metal2 ( 495600 442960 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 504560 442960 ) RECT ( -280 -1040 280 0 ) ;
+ - vga_clock.pulse_min.count\[3\] ( ANTENNA__1156__A1 I ) ( ANTENNA__1183__A1 I ) ( ANTENNA__1200__B I ) ( ANTENNA__1201__A1 I ) ( ANTENNA__1204__A1 I ) ( _1460_ Q ) ( _1204_ A1 )
+ ( _1201_ A1 ) ( _1200_ B ) ( _1183_ A1 ) ( _1156_ A1 ) + USE SIGNAL
+ + ROUTED Metal2 ( 540400 440720 ) ( * 441840 )
+ NEW Metal3 ( 540400 440720 ) ( 549360 * )
+ NEW Metal2 ( 546000 440720 ) ( * 449680 )
+ NEW Metal3 ( 524720 449680 ) ( 546000 * )
+ NEW Metal3 ( 523600 437360 ) ( 540400 * )
+ NEW Metal2 ( 540400 437360 ) ( * 440720 )
+ NEW Metal2 ( 514640 440720 ) ( 515760 * )
+ NEW Metal2 ( 515760 437360 ) ( * 440720 )
+ NEW Metal3 ( 515760 437360 ) ( 523600 * )
+ NEW Metal3 ( 509040 449680 ) ( 524720 * )
+ NEW Metal3 ( 496720 449680 ) ( 509040 * )
+ NEW Metal2 ( 522480 449680 ) ( * 472080 )
+ NEW Metal3 ( 513520 474320 ) ( 522480 * )
+ NEW Metal2 ( 522480 472080 ) ( * 474320 )
+ NEW Metal2 ( 523600 428400 ) ( * 436240 )
+ NEW Metal3 ( 523600 436240 ) ( * 437360 )
+ NEW Metal3 ( 549360 440720 ) ( 554960 * )
+ NEW Metal2 ( 554960 434000 ) ( * 440720 )
+ NEW Metal1 ( 549360 440720 ) Via1_VV
+ NEW Metal2 ( 549360 440720 ) Via2_VH
+ NEW Metal1 ( 540400 441840 ) Via1_VV
+ NEW Metal2 ( 540400 440720 ) Via2_VH
+ NEW Metal1 ( 546000 449680 ) Via1_VV
+ NEW Metal2 ( 546000 440720 ) Via2_VH
+ NEW Metal1 ( 524720 449680 ) Via1_VV
+ NEW Metal2 ( 524720 449680 ) Via2_VH
+ NEW Metal2 ( 546000 449680 ) Via2_VH
+ NEW Metal2 ( 540400 437360 ) Via2_VH
+ NEW Metal1 ( 514640 440720 ) Via1_VV
+ NEW Metal2 ( 515760 437360 ) Via2_VH
+ NEW Metal1 ( 509040 449680 ) Via1_VV
+ NEW Metal2 ( 509040 449680 ) Via2_VH
+ NEW Metal1 ( 496720 449680 ) Via1_VV
+ NEW Metal2 ( 496720 449680 ) Via2_VH
+ NEW Metal1 ( 522480 472080 ) Via1_VV
+ NEW Metal2 ( 522480 449680 ) Via2_VH
+ NEW Metal1 ( 513520 474320 ) Via1_HV
+ NEW Metal2 ( 513520 474320 ) Via2_VH
+ NEW Metal2 ( 522480 474320 ) Via2_VH
+ NEW Metal1 ( 523600 428400 ) Via1_VV
+ NEW Metal2 ( 523600 436240 ) Via2_VH
+ NEW Metal2 ( 554960 440720 ) Via2_VH
+ NEW Metal1 ( 554960 434000 ) Via1_HV
+ NEW Metal2 ( 549360 440720 ) RECT ( -280 -660 280 0 )
+ NEW Metal3 ( 546000 440720 ) RECT ( -1040 -280 0 280 )
+ NEW Metal2 ( 524720 449680 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 546000 449680 ) RECT ( -280 -1040 280 0 )
+ NEW Metal2 ( 509040 449680 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 496720 449680 ) RECT ( -280 -660 280 0 )
+ NEW Metal3 ( 522480 449680 ) RECT ( -1040 -280 0 280 )
+ NEW Metal2 ( 513520 474320 ) RECT ( -280 -660 280 0 ) ;
+ - vga_clock.pulse_min.count\[4\] ( _1461_ Q ) ( _1206_ A1 ) ( _1205_ B ) ( _1186_ A1 ) ( _1184_ A1 ) ( _1157_ A1 ) + USE SIGNAL
+ + ROUTED Metal2 ( 502320 458640 ) ( * 474320 )
+ NEW Metal2 ( 500080 474320 ) ( 502320 * )
+ NEW Metal3 ( 502320 458640 ) ( 514640 * )
+ NEW Metal3 ( 514640 458640 ) ( 540400 * )
+ NEW Metal2 ( 540400 450800 ) ( * 458640 )
+ NEW Metal2 ( 556080 458640 ) ( * 465360 )
+ NEW Metal3 ( 540400 458640 ) ( 556080 * )
+ NEW Metal1 ( 502320 458640 ) Via1_VV
+ NEW Metal1 ( 500080 474320 ) Via1_HV
+ NEW Metal1 ( 514640 458640 ) Via1_HV
+ NEW Metal2 ( 514640 458640 ) Via2_VH
+ NEW Metal2 ( 502320 458640 ) Via2_VH
+ NEW Metal1 ( 540400 458640 ) Via1_HV
+ NEW Metal2 ( 540400 458640 ) Via2_VH
+ NEW Metal1 ( 540400 450800 ) Via1_VV
+ NEW Metal1 ( 556080 465360 ) Via1_HV
+ NEW Metal2 ( 556080 458640 ) Via2_VH
+ NEW Metal2 ( 514640 458640 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 502320 458640 ) RECT ( -280 -1040 280 0 )
+ NEW Metal2 ( 540400 458640 ) RECT ( -280 -660 280 0 ) ;
+ - vga_clock.pulse_sec.comp\[0\] ( ANTENNA__1213__A1 I ) ( ANTENNA__1214__A1 I ) ( ANTENNA__1215__A1 I ) ( ANTENNA__1216__A2 I ) ( ANTENNA__1220__A2 I ) ( ANTENNA__1235__B1 I ) ( ANTENNA__1237__B1 I )
+ ( _1467_ Q ) ( _1237_ B1 ) ( _1235_ B1 ) ( _1220_ A2 ) ( _1216_ A2 ) ( _1215_ A1 ) ( _1214_ A1 ) ( _1213_ A1 ) + USE SIGNAL
+ + ROUTED Metal3 ( 476560 308560 ) ( 494480 * )
+ NEW Metal3 ( 483280 308560 ) ( * 310800 )
+ NEW Metal2 ( 462000 309680 ) ( * 310800 )
+ NEW Metal3 ( 462000 309680 ) ( 476560 * )
+ NEW Metal3 ( 476560 308560 ) ( * 309680 )
+ NEW Metal2 ( 460880 310800 ) ( 462000 * )
+ NEW Metal2 ( 458640 302960 ) ( * 309680 )
+ NEW Metal3 ( 458640 309680 ) ( 462000 * )
+ NEW Metal2 ( 458640 299600 ) ( 464240 * )
+ NEW Metal2 ( 458640 299600 ) ( * 302960 )
+ NEW Metal2 ( 463120 292880 ) ( * 299600 )
+ NEW Metal2 ( 463120 295120 ) ( 467600 * )
+ NEW Metal2 ( 497840 350000 ) ( * 355600 )
+ NEW Metal2 ( 495600 355600 ) ( 497840 * )
+ NEW Metal2 ( 475440 350000 ) ( * 351120 )
+ NEW Metal3 ( 475440 351120 ) ( 497840 * )
+ NEW Metal2 ( 481040 343280 ) ( * 351120 )
+ NEW Metal2 ( 481040 327600 ) ( 483280 * )
+ NEW Metal2 ( 481040 327600 ) ( * 343280 )
+ NEW Metal2 ( 483280 327600 ) ( 487760 * )
+ NEW Metal2 ( 483280 319760 ) ( * 327600 )
+ NEW Metal3 ( 460880 323120 ) ( 467600 * )
+ NEW Metal2 ( 467600 323120 ) ( * 325360 )
+ NEW Metal2 ( 460880 310800 ) ( * 323120 )
+ NEW Metal2 ( 483280 310800 ) ( * 319760 )
+ NEW Metal1 ( 476560 308560 ) Via1_VV
+ NEW Metal2 ( 476560 308560 ) Via2_VH
+ NEW Metal1 ( 494480 308560 ) Via1_VV
+ NEW Metal2 ( 494480 308560 ) Via2_VH
+ NEW Metal2 ( 483280 310800 ) Via2_VH
+ NEW Metal1 ( 462000 310800 ) Via1_VV
+ NEW Metal2 ( 462000 309680 ) Via2_VH
+ NEW Metal1 ( 458640 302960 ) Via1_VV
+ NEW Metal2 ( 458640 309680 ) Via2_VH
+ NEW Metal1 ( 464240 299600 ) Via1_VV
+ NEW Metal1 ( 463120 292880 ) Via1_HV
+ NEW Metal1 ( 467600 295120 ) Via1_VV
+ NEW Metal1 ( 497840 350000 ) Via1_VV
+ NEW Metal1 ( 495600 355600 ) Via1_VV
+ NEW Metal1 ( 475440 350000 ) Via1_VV
+ NEW Metal2 ( 475440 351120 ) Via2_VH
+ NEW Metal2 ( 497840 351120 ) Via2_VH
+ NEW Metal1 ( 481040 343280 ) Via1_VV
+ NEW Metal2 ( 481040 351120 ) Via2_VH
+ NEW Metal1 ( 483280 327600 ) Via1_VV
+ NEW Metal1 ( 487760 327600 ) Via1_VV
+ NEW Metal1 ( 483280 319760 ) Via1_VV
+ NEW Metal2 ( 460880 323120 ) Via2_VH
+ NEW Metal2 ( 467600 323120 ) Via2_VH
+ NEW Metal1 ( 467600 325360 ) Via1_VV
+ NEW Metal2 ( 476560 308560 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 494480 308560 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 497840 351120 ) RECT ( -280 -1040 280 0 )
+ NEW Metal3 ( 481040 351120 ) RECT ( -1040 -280 0 280 ) ;
+ - vga_clock.pulse_sec.comp\[1\] ( _1468_ Q ) ( _1233_ I ) ( _1220_ A1 ) ( _1216_ A1 ) ( _1215_ B ) + USE SIGNAL
+ + ROUTED Metal2 ( 481040 311920 ) ( * 316400 )
+ NEW Metal2 ( 478800 311920 ) ( 481040 * )
+ NEW Metal3 ( 472080 325360 ) ( 481040 * )
+ NEW Metal2 ( 459760 324240 ) ( * 325360 )
+ NEW Metal3 ( 459760 325360 ) ( 472080 * )
+ NEW Metal2 ( 470960 339920 ) ( 472080 * )
+ NEW Metal2 ( 470960 325360 ) ( * 339920 )
+ NEW Metal2 ( 470960 325360 ) ( 472080 * )
+ NEW Metal2 ( 481040 316400 ) ( * 325360 )
+ NEW Metal1 ( 481040 316400 ) Via1_VV
+ NEW Metal1 ( 478800 311920 ) Via1_VV
+ NEW Metal1 ( 472080 325360 ) Via1_VV
+ NEW Metal2 ( 472080 325360 ) Via2_VH
+ NEW Metal2 ( 481040 325360 ) Via2_VH
+ NEW Metal1 ( 459760 324240 ) Via1_HV
+ NEW Metal2 ( 459760 325360 ) Via2_VH
+ NEW Metal1 ( 472080 339920 ) Via1_VV
+ NEW Metal2 ( 472080 325360 ) RECT ( -280 -660 280 0 ) ;
+ - vga_clock.pulse_sec.comp\[2\] ( _1469_ Q ) ( _1238_ A2 ) ( _1232_ B1 ) ( _1226_ A2 ) ( _1225_ A1 ) ( _1222_ A1 ) ( _1221_ A1 )
+ ( _1209_ A3 ) + USE SIGNAL
+ + ROUTED Metal2 ( 507920 317520 ) ( 509040 * )
+ NEW Metal2 ( 509040 287280 ) ( * 317520 )
+ NEW Metal2 ( 506800 287280 ) ( 509040 * )
+ NEW Metal3 ( 502320 317520 ) ( 507920 * )
+ NEW Metal3 ( 488880 317520 ) ( 502320 * )
+ NEW Metal2 ( 486640 311920 ) ( 487760 * )
+ NEW Metal2 ( 487760 311920 ) ( * 317520 )
+ NEW Metal2 ( 487760 317520 ) ( 488880 * )
+ NEW Metal2 ( 482160 301840 ) ( * 302960 )
+ NEW Metal3 ( 482160 302960 ) ( 487760 * )
+ NEW Metal2 ( 487760 302960 ) ( * 311920 )
+ NEW Metal2 ( 497840 335440 ) ( * 341040 )
+ NEW Metal2 ( 502320 327600 ) ( * 336560 )
+ NEW Metal2 ( 501200 336560 ) ( 502320 * )
+ NEW Metal2 ( 501200 336560 ) ( * 341040 )
+ NEW Metal2 ( 497840 341040 ) ( 501200 * )
+ NEW Metal2 ( 488880 317520 ) ( * 346640 )
+ NEW Metal2 ( 502320 317520 ) ( * 327600 )
+ NEW Metal1 ( 507920 317520 ) Via1_VV
+ NEW Metal1 ( 506800 287280 ) Via1_HV
+ NEW Metal2 ( 502320 317520 ) Via2_VH
+ NEW Metal2 ( 507920 317520 ) Via2_VH
+ NEW Metal2 ( 488880 317520 ) Via2_VH
+ NEW Metal1 ( 486640 311920 ) Via1_VV
+ NEW Metal1 ( 482160 301840 ) Via1_VV
+ NEW Metal2 ( 482160 302960 ) Via2_VH
+ NEW Metal2 ( 487760 302960 ) Via2_VH
+ NEW Metal1 ( 488880 346640 ) Via1_VV
+ NEW Metal1 ( 497840 335440 ) Via1_VV
+ NEW Metal1 ( 497840 341040 ) Via1_VV
+ NEW Metal1 ( 502320 327600 ) Via1_VV
+ NEW Metal2 ( 507920 317520 ) RECT ( -280 -1040 280 0 ) ;
+ - vga_clock.pulse_sec.comp\[3\] ( _1470_ Q ) ( _1226_ A1 ) ( _1224_ I ) ( _1209_ A2 ) + USE SIGNAL
+ + ROUTED Metal3 ( 500080 325360 ) ( 521360 * )
+ NEW Metal2 ( 521360 324240 ) ( * 325360 )
+ NEW Metal2 ( 500080 325360 ) ( * 333200 )
+ NEW Metal3 ( 509040 338800 ) ( * 339920 )
+ NEW Metal3 ( 500080 338800 ) ( 509040 * )
+ NEW Metal2 ( 500080 333200 ) ( * 338800 )
+ NEW Metal1 ( 500080 325360 ) Via1_VV
+ NEW Metal2 ( 500080 325360 ) Via2_VH
+ NEW Metal2 ( 521360 325360 ) Via2_VH
+ NEW Metal1 ( 521360 324240 ) Via1_HV
+ NEW Metal1 ( 500080 333200 ) Via1_VV
+ NEW Metal1 ( 509040 339920 ) Via1_VV
+ NEW Metal2 ( 509040 339920 ) Via2_VH
+ NEW Metal2 ( 500080 338800 ) Via2_VH
+ NEW Metal2 ( 500080 325360 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 509040 339920 ) RECT ( -280 -660 280 0 ) ;
+ - vga_clock.pulse_sec.comp\[4\] ( _1471_ Q ) ( _1236_ A2 ) ( _1229_ A1 ) ( _1209_ A1 ) + USE SIGNAL
+ + ROUTED Metal2 ( 503440 333200 ) ( 504560 * )
+ NEW Metal2 ( 504560 333200 ) ( * 355600 )
+ NEW Metal2 ( 504560 355600 ) ( 505680 * )
+ NEW Metal2 ( 528080 334320 ) ( * 339920 )
+ NEW Metal3 ( 504560 334320 ) ( 528080 * )
+ NEW Metal3 ( 528080 334320 ) ( 534800 * )
+ NEW Metal1 ( 503440 333200 ) Via1_VV
+ NEW Metal1 ( 505680 355600 ) Via1_HV
+ NEW Metal1 ( 528080 339920 ) Via1_HV
+ NEW Metal2 ( 528080 334320 ) Via2_VH
+ NEW Metal2 ( 504560 334320 ) Via2_VH
+ NEW Metal1 ( 534800 334320 ) Via1_VV
+ NEW Metal2 ( 534800 334320 ) Via2_VH
+ NEW Metal2 ( 504560 334320 ) RECT ( -280 -1040 280 0 )
+ NEW Metal2 ( 534800 334320 ) RECT ( -280 -660 280 0 ) ;
+ - vga_clock.pulse_sec.count\[0\] ( _1472_ Q ) ( _1248_ A3 ) ( _1245_ A2 ) ( _1243_ A1 ) ( _1242_ A1 ) ( _1234_ I ) ( _1207_ A2 ) + USE SIGNAL
+ + ROUTED Metal2 ( 464240 380240 ) ( * 385840 )
+ NEW Metal3 ( 464240 385840 ) ( 497840 * )
+ NEW Metal2 ( 478800 364560 ) ( * 367920 )
+ NEW Metal2 ( 475440 367920 ) ( 478800 * )
+ NEW Metal2 ( 475440 367920 ) ( * 385840 )
+ NEW Metal2 ( 458640 364560 ) ( * 380240 )
+ NEW Metal3 ( 458640 380240 ) ( 464240 * )
+ NEW Metal2 ( 476560 357840 ) ( * 367920 )
+ NEW Metal2 ( 456400 355600 ) ( * 364560 )
+ NEW Metal2 ( 456400 364560 ) ( 458640 * )
+ NEW Metal3 ( 449680 372400 ) ( 458640 * )
+ NEW Metal1 ( 464240 380240 ) Via1_HV
+ NEW Metal2 ( 464240 385840 ) Via2_VH
+ NEW Metal1 ( 497840 385840 ) Via1_VV
+ NEW Metal2 ( 497840 385840 ) Via2_VH
+ NEW Metal1 ( 478800 364560 ) Via1_VV
+ NEW Metal2 ( 475440 385840 ) Via2_VH
+ NEW Metal1 ( 458640 364560 ) Via1_VV
+ NEW Metal2 ( 458640 380240 ) Via2_VH
+ NEW Metal2 ( 464240 380240 ) Via2_VH
+ NEW Metal1 ( 476560 357840 ) Via1_VV
+ NEW Metal1 ( 456400 355600 ) Via1_HV
+ NEW Metal1 ( 449680 372400 ) Via1_VV
+ NEW Metal2 ( 449680 372400 ) Via2_VH
+ NEW Metal2 ( 458640 372400 ) Via2_VH
+ NEW Metal2 ( 497840 385840 ) RECT ( -280 -660 280 0 )
+ NEW Metal3 ( 475440 385840 ) RECT ( -1040 -280 0 280 )
+ NEW Metal2 ( 464240 380240 ) RECT ( -280 -1040 280 0 )
+ NEW Metal2 ( 449680 372400 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 458640 372400 ) RECT ( -280 -1040 280 0 ) ;
+ - vga_clock.pulse_sec.count\[1\] ( ANTENNA__1207__A1 I ) ( ANTENNA__1235__A1 I ) ( ANTENNA__1238__B2 I ) ( ANTENNA__1244__A1 I ) ( ANTENNA__1245__A1 I ) ( ANTENNA__1248__A2 I ) ( _1473_ Q )
+ ( _1248_ A2 ) ( _1245_ A1 ) ( _1244_ A1 ) ( _1238_ B2 ) ( _1235_ A1 ) ( _1207_ A1 ) + USE SIGNAL
+ + ROUTED Metal2 ( 479920 406000 ) ( * 412720 )
+ NEW Metal2 ( 472080 412720 ) ( 479920 * )
+ NEW Metal3 ( 479920 406000 ) ( 486640 * )
+ NEW Metal3 ( 486640 397040 ) ( 497840 * )
+ NEW Metal2 ( 486640 397040 ) ( * 406000 )
+ NEW Metal2 ( 495600 389200 ) ( * 397040 )
+ NEW Metal3 ( 466480 380240 ) ( 495600 * )
+ NEW Metal2 ( 495600 380240 ) ( * 389200 )
+ NEW Metal3 ( 459760 379120 ) ( 466480 * )
+ NEW Metal3 ( 466480 379120 ) ( * 380240 )
+ NEW Metal2 ( 488880 365680 ) ( 490000 * )
+ NEW Metal2 ( 488880 365680 ) ( * 380240 )
+ NEW Metal2 ( 479920 363440 ) ( * 370160 )
+ NEW Metal3 ( 479920 370160 ) ( 488880 * )
+ NEW Metal2 ( 482160 351120 ) ( * 353360 )
+ NEW Metal2 ( 479920 353360 ) ( 482160 * )
+ NEW Metal2 ( 479920 353360 ) ( * 363440 )
+ NEW Metal2 ( 470960 350000 ) ( * 351120 )
+ NEW Metal1 ( 470960 351120 ) ( 479920 * )
+ NEW Metal2 ( 479920 351120 ) ( * 353360 )
+ NEW Metal3 ( 467600 343280 ) ( 470960 * )
+ NEW Metal2 ( 470960 343280 ) ( * 350000 )
+ NEW Metal2 ( 482160 343280 ) ( 483280 * )
+ NEW Metal2 ( 482160 343280 ) ( * 351120 )
+ NEW Metal1 ( 479920 406000 ) Via1_VV
+ NEW Metal1 ( 472080 412720 ) Via1_HV
+ NEW Metal1 ( 486640 406000 ) Via1_VV
+ NEW Metal2 ( 486640 406000 ) Via2_VH
+ NEW Metal2 ( 479920 406000 ) Via2_VH
+ NEW Metal1 ( 497840 397040 ) Via1_VV
+ NEW Metal2 ( 497840 397040 ) Via2_VH
+ NEW Metal2 ( 486640 397040 ) Via2_VH
+ NEW Metal1 ( 495600 389200 ) Via1_VV
+ NEW Metal2 ( 495600 397040 ) Via2_VH
+ NEW Metal1 ( 466480 380240 ) Via1_HV
+ NEW Metal2 ( 466480 380240 ) Via2_VH
+ NEW Metal2 ( 495600 380240 ) Via2_VH
+ NEW Metal1 ( 459760 379120 ) Via1_VV
+ NEW Metal2 ( 459760 379120 ) Via2_VH
+ NEW Metal1 ( 490000 365680 ) Via1_VV
+ NEW Metal2 ( 488880 380240 ) Via2_VH
+ NEW Metal1 ( 479920 363440 ) Via1_VV
+ NEW Metal2 ( 479920 370160 ) Via2_VH
+ NEW Metal2 ( 488880 370160 ) Via2_VH
+ NEW Metal1 ( 482160 351120 ) Via1_VV
+ NEW Metal1 ( 470960 350000 ) Via1_VV
+ NEW Metal1 ( 470960 351120 ) Via1_HV
+ NEW Metal1 ( 479920 351120 ) Via1_HV
+ NEW Metal1 ( 467600 343280 ) Via1_VV
+ NEW Metal2 ( 467600 343280 ) Via2_VH
+ NEW Metal2 ( 470960 343280 ) Via2_VH
+ NEW Metal1 ( 483280 343280 ) Via1_VV
+ NEW Metal2 ( 486640 406000 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 479920 406000 ) RECT ( -280 -1040 280 0 )
+ NEW Metal2 ( 497840 397040 ) RECT ( -280 -660 280 0 )
+ NEW Metal3 ( 495600 397040 ) RECT ( -1040 -280 0 280 )
+ NEW Metal2 ( 466480 380240 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 459760 379120 ) RECT ( -280 -660 280 0 )
+ NEW Metal3 ( 488880 380240 ) RECT ( -1040 -280 0 280 )
+ NEW Metal2 ( 488880 370160 ) RECT ( -280 -1040 280 0 )
+ NEW Metal2 ( 467600 343280 ) RECT ( -280 -660 280 0 ) ;
+ - vga_clock.pulse_sec.count\[2\] ( _1474_ Q ) ( _1249_ A1 ) ( _1248_ A1 ) ( _1231_ I ) ( _1208_ A3 ) + USE SIGNAL
+ + ROUTED Metal3 ( 487760 372400 ) ( 495600 * )
+ NEW Metal3 ( 478800 372400 ) ( 487760 * )
+ NEW Metal2 ( 468720 373520 ) ( * 378000 )
+ NEW Metal3 ( 468720 372400 ) ( * 373520 )
+ NEW Metal3 ( 468720 372400 ) ( 478800 * )
+ NEW Metal2 ( 468720 378000 ) ( * 386960 )
+ NEW Metal1 ( 487760 372400 ) Via1_VV
+ NEW Metal2 ( 487760 372400 ) Via2_VH
+ NEW Metal1 ( 495600 372400 ) Via1_HV
+ NEW Metal2 ( 495600 372400 ) Via2_VH
+ NEW Metal1 ( 478800 372400 ) Via1_VV
+ NEW Metal2 ( 478800 372400 ) Via2_VH
+ NEW Metal1 ( 468720 378000 ) Via1_VV
+ NEW Metal2 ( 468720 373520 ) Via2_VH
+ NEW Metal1 ( 468720 386960 ) Via1_HV
+ NEW Metal2 ( 487760 372400 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 495600 372400 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 478800 372400 ) RECT ( -280 -660 280 0 ) ;
+ - vga_clock.pulse_sec.count\[3\] ( _1475_ Q ) ( _1256_ A1 ) ( _1253_ A1 ) ( _1252_ B ) ( _1237_ A1 ) ( _1232_ A1 ) ( _1208_ A2 ) + USE SIGNAL
+ + ROUTED Metal2 ( 500080 343280 ) ( * 346640 )
+ NEW Metal2 ( 504560 372400 ) ( 505680 * )
+ NEW Metal2 ( 504560 361200 ) ( * 372400 )
+ NEW Metal2 ( 500080 361200 ) ( 504560 * )
+ NEW Metal2 ( 500080 346640 ) ( * 361200 )
+ NEW Metal2 ( 511280 380240 ) ( 512400 * )
+ NEW Metal2 ( 511280 369040 ) ( * 380240 )
+ NEW Metal3 ( 504560 369040 ) ( 511280 * )
+ NEW Metal2 ( 515760 380240 ) ( * 388080 )
+ NEW Metal2 ( 512400 380240 ) ( 515760 * )
+ NEW Metal2 ( 504560 372400 ) ( * 393680 )
+ NEW Metal3 ( 515760 386960 ) ( 522480 * )
+ NEW Metal1 ( 500080 346640 ) Via1_VV
+ NEW Metal1 ( 500080 343280 ) Via1_VV
+ NEW Metal1 ( 505680 372400 ) Via1_HV
+ NEW Metal1 ( 512400 380240 ) Via1_VV
+ NEW Metal2 ( 511280 369040 ) Via2_VH
+ NEW Metal2 ( 504560 369040 ) Via2_VH
+ NEW Metal1 ( 515760 388080 ) Via1_VV
+ NEW Metal1 ( 504560 393680 ) Via1_VV
+ NEW Metal1 ( 522480 386960 ) Via1_HV
+ NEW Metal2 ( 522480 386960 ) Via2_VH
+ NEW Metal2 ( 515760 386960 ) Via2_VH
+ NEW Metal2 ( 504560 369040 ) RECT ( -280 -1040 280 0 )
+ NEW Metal2 ( 522480 386960 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 515760 386960 ) RECT ( -280 -1040 280 0 ) ;
+ - vga_clock.pulse_sec.count\[4\] ( _1476_ Q ) ( _1258_ A1 ) ( _1257_ B ) ( _1236_ A1 ) ( _1208_ A1 ) + USE SIGNAL
+ + ROUTED Metal2 ( 526960 364560 ) ( * 372400 )
+ NEW Metal2 ( 512400 364560 ) ( * 373520 )
+ NEW Metal3 ( 512400 364560 ) ( 526960 * )
+ NEW Metal2 ( 510160 356720 ) ( * 364560 )
+ NEW Metal2 ( 510160 364560 ) ( 512400 * )
+ NEW Metal2 ( 563920 364560 ) ( * 365680 )
+ NEW Metal3 ( 526960 364560 ) ( 563920 * )
+ NEW Metal1 ( 526960 364560 ) Via1_VV
+ NEW Metal2 ( 526960 364560 ) Via2_VH
+ NEW Metal1 ( 526960 372400 ) Via1_VV
+ NEW Metal1 ( 512400 373520 ) Via1_HV
+ NEW Metal2 ( 512400 364560 ) Via2_VH
+ NEW Metal1 ( 510160 356720 ) Via1_HV
+ NEW Metal2 ( 563920 364560 ) Via2_VH
+ NEW Metal1 ( 563920 365680 ) Via1_HV
+ NEW Metal2 ( 526960 364560 ) RECT ( -280 -660 280 0 ) ;
+ - vga_clock.sec_counter\[0\] ( _1385_ Q ) ( _0937_ A1 ) ( _0932_ A1 ) ( _0931_ A1 ) ( _0919_ A1 ) + USE SIGNAL
+ + ROUTED Metal2 ( 120400 146160 ) ( * 152880 )
+ NEW Metal3 ( 108080 152880 ) ( 120400 * )
+ NEW Metal3 ( 115920 192080 ) ( 127120 * )
+ NEW Metal2 ( 115920 152880 ) ( * 192080 )
+ NEW Metal2 ( 113680 192080 ) ( * 198800 )
+ NEW Metal2 ( 113680 192080 ) ( 115920 * )
+ NEW Metal2 ( 139440 190960 ) ( * 192080 )
+ NEW Metal3 ( 127120 192080 ) ( 139440 * )
+ NEW Metal1 ( 120400 146160 ) Via1_HV
+ NEW Metal2 ( 120400 152880 ) Via2_VH
+ NEW Metal1 ( 108080 152880 ) Via1_HV
+ NEW Metal2 ( 108080 152880 ) Via2_VH
+ NEW Metal1 ( 127120 192080 ) Via1_VV
+ NEW Metal2 ( 127120 192080 ) Via2_VH
+ NEW Metal2 ( 115920 192080 ) Via2_VH
+ NEW Metal2 ( 115920 152880 ) Via2_VH
+ NEW Metal1 ( 113680 198800 ) Via1_VV
+ NEW Metal1 ( 139440 190960 ) Via1_VV
+ NEW Metal2 ( 139440 192080 ) Via2_VH
+ NEW Metal2 ( 108080 152880 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 127120 192080 ) RECT ( -280 -660 280 0 )
+ NEW Metal3 ( 115920 152880 ) RECT ( -1040 -280 0 280 ) ;
+ - vga_clock.sec_counter\[10\] ( _1395_ Q ) ( _0962_ A3 ) ( _0959_ A1 ) ( _0958_ A1 ) ( _0925_ A2 ) + USE SIGNAL
+ + ROUTED Metal2 ( 57680 238000 ) ( * 239120 )
+ NEW Metal3 ( 48720 238000 ) ( 57680 * )
+ NEW Metal2 ( 47600 245840 ) ( 48720 * )
+ NEW Metal2 ( 48720 238000 ) ( * 245840 )
+ NEW Metal2 ( 99120 231280 ) ( * 236880 )
+ NEW Metal2 ( 99120 236880 ) ( * 238000 )
+ NEW Metal3 ( 57680 238000 ) ( 99120 * )
+ NEW Metal1 ( 57680 239120 ) Via1_VV
+ NEW Metal2 ( 57680 238000 ) Via2_VH
+ NEW Metal1 ( 48720 238000 ) Via1_VV
+ NEW Metal2 ( 48720 238000 ) Via2_VH
+ NEW Metal1 ( 47600 245840 ) Via1_HV
+ NEW Metal1 ( 99120 236880 ) Via1_VV
+ NEW Metal1 ( 99120 231280 ) Via1_HV
+ NEW Metal2 ( 99120 238000 ) Via2_VH
+ NEW Metal2 ( 48720 238000 ) RECT ( -280 -660 280 0 ) ;
+ - vga_clock.sec_counter\[11\] ( _1396_ Q ) ( _0961_ A1 ) ( _0923_ I ) + USE SIGNAL
+ + ROUTED Metal2 ( 80080 248080 ) ( * 262640 )
+ NEW Metal2 ( 86800 255920 ) ( * 262640 )
+ NEW Metal3 ( 68880 262640 ) ( 86800 * )
+ NEW Metal1 ( 68880 262640 ) Via1_HV
+ NEW Metal2 ( 68880 262640 ) Via2_VH
+ NEW Metal1 ( 80080 248080 ) Via1_VV
+ NEW Metal2 ( 80080 262640 ) Via2_VH
+ NEW Metal1 ( 86800 255920 ) Via1_HV
+ NEW Metal2 ( 86800 262640 ) Via2_VH
+ NEW Metal2 ( 68880 262640 ) RECT ( -280 0 280 660 )
+ NEW Metal3 ( 80080 262640 ) RECT ( -1040 -280 0 280 ) ;
+ - vga_clock.sec_counter\[12\] ( _1397_ Q ) ( _0967_ A1 ) ( _0924_ I ) + USE SIGNAL
+ + ROUTED Metal2 ( 110320 261520 ) ( * 262640 )
+ NEW Metal2 ( 110320 261520 ) ( 113680 * )
+ NEW Metal2 ( 113680 254800 ) ( * 261520 )
+ NEW Metal2 ( 113680 254800 ) ( 114800 * )
+ NEW Metal2 ( 112560 261520 ) ( * 271600 )
+ NEW Metal1 ( 110320 262640 ) Via1_VV
+ NEW Metal1 ( 114800 254800 ) Via1_VV
+ NEW Metal1 ( 112560 271600 ) Via1_HV ;
+ - vga_clock.sec_counter\[13\] ( _1398_ Q ) ( _0968_ I ) ( _0967_ B ) ( _0925_ A4 ) + USE SIGNAL
+ + ROUTED Metal2 ( 118160 254800 ) ( * 261520 )
+ NEW Metal2 ( 109200 240240 ) ( * 254800 )
+ NEW Metal3 ( 109200 254800 ) ( 118160 * )
+ NEW Metal2 ( 103600 239120 ) ( * 240240 )
+ NEW Metal2 ( 103600 240240 ) ( 109200 * )
+ NEW Metal1 ( 118160 254800 ) Via1_VV
+ NEW Metal1 ( 118160 261520 ) Via1_HV
+ NEW Metal1 ( 109200 240240 ) Via1_VV
+ NEW Metal2 ( 109200 254800 ) Via2_VH
+ NEW Metal2 ( 118160 254800 ) Via2_VH
+ NEW Metal1 ( 103600 239120 ) Via1_VV
+ NEW Metal2 ( 118160 254800 ) RECT ( -280 -1040 280 0 ) ;
+ - vga_clock.sec_counter\[14\] ( ANTENNA__0918__A1 I ) ( ANTENNA__0971__A1 I ) ( ANTENNA__0972__A1 I ) ( ANTENNA__0977__A1 I ) ( _1399_ Q ) ( _0977_ A1 ) ( _0972_ A1 )
+ ( _0971_ A1 ) ( _0918_ A1 ) + USE SIGNAL
+ + ROUTED Metal2 ( 148400 271600 ) ( * 277200 )
+ NEW Metal3 ( 148400 271600 ) ( 166320 * )
+ NEW Metal2 ( 143920 277200 ) ( * 278320 )
+ NEW Metal2 ( 143920 277200 ) ( 148400 * )
+ NEW Metal2 ( 127120 271600 ) ( * 272720 )
+ NEW Metal3 ( 127120 272720 ) ( 148400 * )
+ NEW Metal3 ( 148400 271600 ) ( * 272720 )
+ NEW Metal2 ( 118160 272720 ) ( * 277200 )
+ NEW Metal3 ( 118160 272720 ) ( 127120 * )
+ NEW Metal2 ( 126000 299600 ) ( 127120 * )
+ NEW Metal2 ( 127120 272720 ) ( * 299600 )
+ NEW Metal2 ( 112560 300720 ) ( * 301840 )
+ NEW Metal3 ( 112560 300720 ) ( 127120 * )
+ NEW Metal2 ( 127120 299600 ) ( * 300720 )
+ NEW Metal2 ( 109200 296240 ) ( * 300720 )
+ NEW Metal3 ( 109200 300720 ) ( 112560 * )
+ NEW Metal2 ( 105840 300720 ) ( * 307440 )
+ NEW Metal3 ( 105840 300720 ) ( 109200 * )
+ NEW Metal1 ( 148400 277200 ) Via1_VV
+ NEW Metal2 ( 148400 271600 ) Via2_VH
+ NEW Metal1 ( 166320 271600 ) Via1_HV
+ NEW Metal2 ( 166320 271600 ) Via2_VH
+ NEW Metal1 ( 143920 278320 ) Via1_HV
+ NEW Metal1 ( 127120 271600 ) Via1_VV
+ NEW Metal2 ( 127120 272720 ) Via2_VH
+ NEW Metal1 ( 118160 277200 ) Via1_VV
+ NEW Metal2 ( 118160 272720 ) Via2_VH
+ NEW Metal1 ( 126000 299600 ) Via1_VV
+ NEW Metal1 ( 112560 301840 ) Via1_VV
+ NEW Metal2 ( 112560 300720 ) Via2_VH
+ NEW Metal2 ( 127120 300720 ) Via2_VH
+ NEW Metal1 ( 109200 296240 ) Via1_VV
+ NEW Metal2 ( 109200 300720 ) Via2_VH
+ NEW Metal1 ( 105840 307440 ) Via1_VV
+ NEW Metal2 ( 105840 300720 ) Via2_VH
+ NEW Metal2 ( 166320 271600 ) RECT ( -280 -660 280 0 ) ;
+ - vga_clock.sec_counter\[15\] ( _1400_ Q ) ( _0977_ A2 ) ( _0976_ A1 ) ( _0975_ A1 ) ( _0974_ A1 ) ( _0912_ I ) + USE SIGNAL
+ + ROUTED Metal2 ( 113680 300720 ) ( * 308560 )
+ NEW Metal2 ( 112560 308560 ) ( 113680 * )
+ NEW Metal2 ( 115920 295120 ) ( 117040 * )
+ NEW Metal2 ( 115920 295120 ) ( * 300720 )
+ NEW Metal2 ( 113680 300720 ) ( 115920 * )
+ NEW Metal3 ( 113680 308560 ) ( 129360 * )
+ NEW Metal2 ( 139440 300720 ) ( * 308560 )
+ NEW Metal3 ( 129360 308560 ) ( 139440 * )
+ NEW Metal2 ( 137200 296240 ) ( 139440 * )
+ NEW Metal2 ( 139440 296240 ) ( * 300720 )
+ NEW Metal1 ( 113680 300720 ) Via1_HV
+ NEW Metal1 ( 112560 308560 ) Via1_VV
+ NEW Metal1 ( 117040 295120 ) Via1_VV
+ NEW Metal1 ( 129360 308560 ) Via1_HV
+ NEW Metal2 ( 129360 308560 ) Via2_VH
+ NEW Metal2 ( 113680 308560 ) Via2_VH
+ NEW Metal1 ( 139440 300720 ) Via1_HV
+ NEW Metal2 ( 139440 308560 ) Via2_VH
+ NEW Metal1 ( 137200 296240 ) Via1_VV
+ NEW Metal2 ( 129360 308560 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 113680 308560 ) RECT ( -280 -1040 280 0 ) ;
+ - vga_clock.sec_counter\[16\] ( _1401_ Q ) ( _0977_ A3 ) ( _0976_ B ) ( _0915_ A2 ) + USE SIGNAL
+ + ROUTED Metal2 ( 117040 300720 ) ( * 310800 )
+ NEW Metal2 ( 117040 310800 ) ( 118160 * )
+ NEW Metal2 ( 118160 310800 ) ( * 317520 )
+ NEW Metal2 ( 114800 295120 ) ( * 297360 )
+ NEW Metal3 ( 114800 297360 ) ( 117040 * )
+ NEW Metal2 ( 117040 297360 ) ( * 300720 )
+ NEW Metal2 ( 113680 287280 ) ( 114800 * )
+ NEW Metal2 ( 114800 287280 ) ( * 295120 )
+ NEW Metal1 ( 117040 300720 ) Via1_HV
+ NEW Metal1 ( 118160 317520 ) Via1_VV
+ NEW Metal1 ( 114800 295120 ) Via1_VV
+ NEW Metal2 ( 114800 297360 ) Via2_VH
+ NEW Metal2 ( 117040 297360 ) Via2_VH
+ NEW Metal1 ( 113680 287280 ) Via1_HV ;
+ - vga_clock.sec_counter\[17\] ( _1402_ Q ) ( _0986_ A1 ) ( _0980_ A1 ) ( _0979_ A1 ) ( _0918_ A2 ) + USE SIGNAL
+ + ROUTED Metal2 ( 129360 317520 ) ( 130480 * )
+ NEW Metal2 ( 103600 309680 ) ( * 310800 )
+ NEW Metal2 ( 103600 310800 ) ( 105840 * )
+ NEW Metal3 ( 130480 334320 ) ( 137200 * )
+ NEW Metal3 ( 110320 334320 ) ( 130480 * )
+ NEW Metal3 ( 105840 323120 ) ( 110320 * )
+ NEW Metal2 ( 110320 323120 ) ( * 334320 )
+ NEW Metal2 ( 105840 323120 ) ( * 324240 )
+ NEW Metal2 ( 105840 310800 ) ( * 323120 )
+ NEW Metal2 ( 130480 317520 ) ( * 334320 )
+ NEW Metal1 ( 129360 317520 ) Via1_HV
+ NEW Metal1 ( 103600 309680 ) Via1_VV
+ NEW Metal2 ( 130480 334320 ) Via2_VH
+ NEW Metal1 ( 137200 334320 ) Via1_HV
+ NEW Metal2 ( 137200 334320 ) Via2_VH
+ NEW Metal1 ( 110320 334320 ) Via1_VV
+ NEW Metal2 ( 110320 334320 ) Via2_VH
+ NEW Metal2 ( 105840 323120 ) Via2_VH
+ NEW Metal2 ( 110320 323120 ) Via2_VH
+ NEW Metal1 ( 105840 324240 ) Via1_VV
+ NEW Metal2 ( 137200 334320 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 110320 334320 ) RECT ( -280 -660 280 0 ) ;
+ - vga_clock.sec_counter\[18\] ( _1403_ Q ) ( _0986_ A3 ) ( _0985_ A1 ) ( _0983_ A1 ) ( _0982_ A1 ) ( _0914_ A2 ) + USE SIGNAL
+ + ROUTED Metal3 ( 139440 348880 ) ( 150640 * )
+ NEW Metal2 ( 123760 348880 ) ( * 355600 )
+ NEW Metal3 ( 123760 348880 ) ( 139440 * )
+ NEW Metal3 ( 109200 347760 ) ( 123760 * )
+ NEW Metal3 ( 123760 347760 ) ( * 348880 )
+ NEW Metal2 ( 105840 341040 ) ( * 347760 )
+ NEW Metal3 ( 105840 347760 ) ( 109200 * )
+ NEW Metal2 ( 106960 333200 ) ( * 341040 )
+ NEW Metal2 ( 105840 341040 ) ( 106960 * )
+ NEW Metal1 ( 139440 348880 ) Via1_VV
+ NEW Metal2 ( 139440 348880 ) Via2_VH
+ NEW Metal1 ( 150640 348880 ) Via1_VV
+ NEW Metal2 ( 150640 348880 ) Via2_VH
+ NEW Metal1 ( 123760 355600 ) Via1_HV
+ NEW Metal2 ( 123760 348880 ) Via2_VH
+ NEW Metal1 ( 109200 347760 ) Via1_VV
+ NEW Metal2 ( 109200 347760 ) Via2_VH
+ NEW Metal1 ( 105840 341040 ) Via1_VV
+ NEW Metal2 ( 105840 347760 ) Via2_VH
+ NEW Metal1 ( 106960 333200 ) Via1_VV
+ NEW Metal2 ( 139440 348880 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 150640 348880 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 109200 347760 ) RECT ( -280 -660 280 0 ) ;
+ - vga_clock.sec_counter\[19\] ( _1404_ Q ) ( _0986_ A2 ) ( _0985_ B ) ( _0914_ A1 ) + USE SIGNAL
+ + ROUTED Metal2 ( 108080 348880 ) ( * 350000 )
+ NEW Metal3 ( 108080 350000 ) ( 120400 * )
+ NEW Metal2 ( 120400 350000 ) ( * 365680 )
+ NEW Metal2 ( 108080 342160 ) ( * 348880 )
+ NEW Metal2 ( 108080 333200 ) ( * 342160 )
+ NEW Metal1 ( 108080 348880 ) Via1_VV
+ NEW Metal2 ( 108080 350000 ) Via2_VH
+ NEW Metal2 ( 120400 350000 ) Via2_VH
+ NEW Metal1 ( 120400 365680 ) Via1_HV
+ NEW Metal1 ( 108080 342160 ) Via1_VV
+ NEW Metal1 ( 108080 333200 ) Via1_VV ;
+ - vga_clock.sec_counter\[1\] ( _1386_ Q ) ( _0937_ A2 ) ( _0932_ A2 ) ( _0919_ A2 ) + USE SIGNAL
+ + ROUTED Metal2 ( 124880 192080 ) ( * 197680 )
+ NEW Metal3 ( 115920 197680 ) ( 124880 * )
+ NEW Metal3 ( 124880 197680 ) ( 132720 * )
+ NEW Metal2 ( 137200 194320 ) ( * 197680 )
+ NEW Metal3 ( 132720 197680 ) ( 137200 * )
+ NEW Metal2 ( 132720 197680 ) ( * 214480 )
+ NEW Metal1 ( 132720 214480 ) Via1_HV
+ NEW Metal1 ( 124880 192080 ) Via1_VV
+ NEW Metal2 ( 124880 197680 ) Via2_VH
+ NEW Metal1 ( 115920 197680 ) Via1_VV
+ NEW Metal2 ( 115920 197680 ) Via2_VH
+ NEW Metal2 ( 132720 197680 ) Via2_VH
+ NEW Metal1 ( 137200 194320 ) Via1_VV
+ NEW Metal2 ( 137200 197680 ) Via2_VH
+ NEW Metal2 ( 115920 197680 ) RECT ( -280 -660 280 0 ) ;
+ - vga_clock.sec_counter\[20\] ( _1405_ Q ) ( _0998_ A1 ) ( _0995_ A1 ) ( _0990_ A1 ) ( _0988_ A1 ) ( _0914_ A3 ) + USE SIGNAL
+ + ROUTED Metal2 ( 74480 364560 ) ( * 365680 )
+ NEW Metal3 ( 61040 365680 ) ( 74480 * )
+ NEW Metal2 ( 61040 365680 ) ( * 371280 )
+ NEW Metal2 ( 74480 356720 ) ( * 364560 )
+ NEW Metal2 ( 74480 353360 ) ( * 356720 )
+ NEW Metal2 ( 68880 341040 ) ( * 353360 )
+ NEW Metal3 ( 68880 353360 ) ( 74480 * )
+ NEW Metal2 ( 70000 333200 ) ( * 341040 )
+ NEW Metal2 ( 68880 341040 ) ( 70000 * )
+ NEW Metal2 ( 103600 341040 ) ( * 353360 )
+ NEW Metal3 ( 74480 353360 ) ( 103600 * )
+ NEW Metal1 ( 74480 364560 ) Via1_VV
+ NEW Metal2 ( 74480 365680 ) Via2_VH
+ NEW Metal2 ( 61040 365680 ) Via2_VH
+ NEW Metal1 ( 61040 371280 ) Via1_HV
+ NEW Metal1 ( 74480 356720 ) Via1_VV
+ NEW Metal2 ( 74480 353360 ) Via2_VH
+ NEW Metal1 ( 68880 341040 ) Via1_HV
+ NEW Metal2 ( 68880 353360 ) Via2_VH
+ NEW Metal1 ( 70000 333200 ) Via1_VV
+ NEW Metal1 ( 103600 341040 ) Via1_VV
+ NEW Metal2 ( 103600 353360 ) Via2_VH ;
+ - vga_clock.sec_counter\[21\] ( _1406_ Q ) ( _0998_ A2 ) ( _0995_ A2 ) ( _0994_ A1 ) ( _0993_ A1 ) ( _0992_ A1 ) ( _0913_ I ) + USE SIGNAL
+ + ROUTED Metal2 ( 75600 341040 ) ( * 342160 )
+ NEW Metal2 ( 68880 333200 ) ( * 336560 )
+ NEW Metal3 ( 68880 336560 ) ( 75600 * )
+ NEW Metal2 ( 75600 336560 ) ( * 341040 )
+ NEW Metal2 ( 58800 355600 ) ( * 356720 )
+ NEW Metal3 ( 58800 355600 ) ( 75600 * )
+ NEW Metal2 ( 75600 342160 ) ( * 355600 )
+ NEW Metal2 ( 62160 355600 ) ( * 362320 )
+ NEW Metal2 ( 55440 355600 ) ( * 371280 )
+ NEW Metal3 ( 55440 355600 ) ( 58800 * )
+ NEW Metal3 ( 47600 364560 ) ( 55440 * )
+ NEW Metal3 ( 75600 342160 ) ( 86800 * )
+ NEW Metal1 ( 75600 341040 ) Via1_HV
+ NEW Metal2 ( 75600 342160 ) Via2_VH
+ NEW Metal1 ( 68880 333200 ) Via1_VV
+ NEW Metal2 ( 68880 336560 ) Via2_VH
+ NEW Metal2 ( 75600 336560 ) Via2_VH
+ NEW Metal1 ( 58800 356720 ) Via1_VV
+ NEW Metal2 ( 58800 355600 ) Via2_VH
+ NEW Metal2 ( 75600 355600 ) Via2_VH
+ NEW Metal1 ( 62160 362320 ) Via1_VV
+ NEW Metal2 ( 62160 355600 ) Via2_VH
+ NEW Metal1 ( 55440 371280 ) Via1_HV
+ NEW Metal2 ( 55440 355600 ) Via2_VH
+ NEW Metal1 ( 47600 364560 ) Via1_VV
+ NEW Metal2 ( 47600 364560 ) Via2_VH
+ NEW Metal2 ( 55440 364560 ) Via2_VH
+ NEW Metal1 ( 86800 342160 ) Via1_VV
+ NEW Metal2 ( 86800 342160 ) Via2_VH
+ NEW Metal3 ( 62160 355600 ) RECT ( -1040 -280 0 280 )
+ NEW Metal2 ( 47600 364560 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 55440 364560 ) RECT ( -280 -1040 280 0 )
+ NEW Metal2 ( 86800 342160 ) RECT ( -280 -660 280 0 ) ;
+ - vga_clock.sec_counter\[22\] ( _1407_ Q ) ( _0998_ A3 ) ( _0995_ A3 ) ( _0994_ B ) ( _0917_ A2 ) + USE SIGNAL
+ + ROUTED Metal2 ( 50960 339920 ) ( * 348880 )
+ NEW Metal3 ( 50960 348880 ) ( 56560 * )
+ NEW Metal2 ( 56560 348880 ) ( * 356720 )
+ NEW Metal2 ( 66640 342160 ) ( * 348880 )
+ NEW Metal3 ( 56560 348880 ) ( 66640 * )
+ NEW Metal2 ( 66640 332080 ) ( * 342160 )
+ NEW Metal2 ( 65520 327600 ) ( 66640 * )
+ NEW Metal2 ( 66640 327600 ) ( * 332080 )
+ NEW Metal1 ( 50960 339920 ) Via1_HV
+ NEW Metal2 ( 50960 348880 ) Via2_VH
+ NEW Metal2 ( 56560 348880 ) Via2_VH
+ NEW Metal1 ( 56560 356720 ) Via1_VV
+ NEW Metal1 ( 66640 342160 ) Via1_HV
+ NEW Metal2 ( 66640 348880 ) Via2_VH
+ NEW Metal1 ( 66640 332080 ) Via1_HV
+ NEW Metal1 ( 65520 327600 ) Via1_VV ;
+ - vga_clock.sec_counter\[23\] ( _1408_ Q ) ( _1006_ A1 ) ( _1000_ A1 ) ( _0997_ I ) ( _0917_ A1 ) + USE SIGNAL
+ + ROUTED Metal2 ( 58800 302960 ) ( * 309680 )
+ NEW Metal3 ( 58800 302960 ) ( 62160 * )
+ NEW Metal2 ( 62160 301840 ) ( * 302960 )
+ NEW Metal2 ( 62160 301840 ) ( 63280 * )
+ NEW Metal2 ( 63280 295120 ) ( * 301840 )
+ NEW Metal3 ( 58800 309680 ) ( 65520 * )
+ NEW Metal2 ( 48720 315280 ) ( 49840 * )
+ NEW Metal2 ( 49840 309680 ) ( * 315280 )
+ NEW Metal3 ( 49840 309680 ) ( 58800 * )
+ NEW Metal3 ( 43120 315280 ) ( 48720 * )
+ NEW Metal2 ( 65520 309680 ) ( * 319200 )
+ NEW Metal2 ( 47600 323120 ) ( * 324240 )
+ NEW Metal2 ( 43120 323120 ) ( 47600 * )
+ NEW Metal2 ( 65520 319200 ) ( 66640 * )
+ NEW Metal2 ( 66640 319200 ) ( * 322000 )
+ NEW Metal2 ( 66640 322000 ) ( 67760 * )
+ NEW Metal2 ( 67760 322000 ) ( * 325360 )
+ NEW Metal2 ( 43120 315280 ) ( * 323120 )
+ NEW Metal1 ( 58800 309680 ) Via1_VV
+ NEW Metal2 ( 58800 302960 ) Via2_VH
+ NEW Metal2 ( 62160 302960 ) Via2_VH
+ NEW Metal1 ( 63280 295120 ) Via1_VV
+ NEW Metal2 ( 65520 309680 ) Via2_VH
+ NEW Metal2 ( 58800 309680 ) Via2_VH
+ NEW Metal1 ( 48720 315280 ) Via1_VV
+ NEW Metal2 ( 49840 309680 ) Via2_VH
+ NEW Metal2 ( 43120 315280 ) Via2_VH
+ NEW Metal2 ( 48720 315280 ) Via2_VH
+ NEW Metal1 ( 47600 324240 ) Via1_HV
+ NEW Metal1 ( 67760 325360 ) Via1_VV
+ NEW Metal2 ( 58800 309680 ) RECT ( -280 -1040 280 0 )
+ NEW Metal2 ( 48720 315280 ) RECT ( -280 -1040 280 0 ) ;
+ - vga_clock.sec_counter\[24\] ( _1409_ Q ) ( _1006_ A3 ) ( _1003_ I ) ( _0917_ A4 ) + USE SIGNAL
+ + ROUTED Metal3 ( 54320 311920 ) ( 61040 * )
+ NEW Metal2 ( 45360 310800 ) ( * 311920 )
+ NEW Metal3 ( 45360 311920 ) ( 54320 * )
+ NEW Metal3 ( 47600 302960 ) ( 54320 * )
+ NEW Metal2 ( 54320 302960 ) ( * 311920 )
+ NEW Metal2 ( 61040 311920 ) ( * 325360 )
+ NEW Metal1 ( 54320 311920 ) Via1_VV
+ NEW Metal2 ( 54320 311920 ) Via2_VH
+ NEW Metal2 ( 61040 311920 ) Via2_VH
+ NEW Metal1 ( 45360 310800 ) Via1_VV
+ NEW Metal2 ( 45360 311920 ) Via2_VH
+ NEW Metal1 ( 47600 302960 ) Via1_HV
+ NEW Metal2 ( 47600 302960 ) Via2_VH
+ NEW Metal2 ( 54320 302960 ) Via2_VH
+ NEW Metal1 ( 61040 325360 ) Via1_VV
+ NEW Metal2 ( 54320 311920 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 47600 302960 ) RECT ( -280 -660 280 0 ) ;
+ - vga_clock.sec_counter\[25\] ( _1410_ Q ) ( _1007_ B ) ( _0916_ I ) + USE SIGNAL
+ + ROUTED Metal2 ( 71120 277200 ) ( * 300720 )
+ NEW Metal2 ( 75600 301840 ) ( 77840 * )
+ NEW Metal2 ( 75600 300720 ) ( * 301840 )
+ NEW Metal2 ( 71120 300720 ) ( 75600 * )
+ NEW Metal1 ( 71120 300720 ) Via1_VV
+ NEW Metal1 ( 71120 277200 ) Via1_HV
+ NEW Metal1 ( 77840 301840 ) Via1_VV ;
+ - vga_clock.sec_counter\[2\] ( _1387_ Q ) ( _0937_ A4 ) ( _0935_ A1 ) ( _0934_ A1 ) ( _0920_ A2 ) + USE SIGNAL
+ + ROUTED Metal2 ( 134960 183120 ) ( * 186480 )
+ NEW Metal3 ( 134960 186480 ) ( 148400 * )
+ NEW Metal2 ( 148400 186480 ) ( * 189840 )
+ NEW Metal2 ( 121520 186480 ) ( * 192080 )
+ NEW Metal3 ( 121520 186480 ) ( 134960 * )
+ NEW Metal2 ( 123760 177520 ) ( * 186480 )
+ NEW Metal3 ( 112560 190960 ) ( 121520 * )
+ NEW Metal1 ( 134960 183120 ) Via1_HV
+ NEW Metal2 ( 134960 186480 ) Via2_VH
+ NEW Metal2 ( 148400 186480 ) Via2_VH
+ NEW Metal1 ( 148400 189840 ) Via1_VV
+ NEW Metal1 ( 121520 192080 ) Via1_HV
+ NEW Metal2 ( 121520 186480 ) Via2_VH
+ NEW Metal1 ( 123760 177520 ) Via1_VV
+ NEW Metal2 ( 123760 186480 ) Via2_VH
+ NEW Metal1 ( 112560 190960 ) Via1_VV
+ NEW Metal2 ( 112560 190960 ) Via2_VH
+ NEW Metal2 ( 121520 190960 ) Via2_VH
+ NEW Metal3 ( 123760 186480 ) RECT ( -1040 -280 0 280 )
+ NEW Metal2 ( 112560 190960 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 121520 190960 ) RECT ( -280 -1040 280 0 ) ;
+ - vga_clock.sec_counter\[3\] ( _1388_ Q ) ( _0938_ A1 ) ( _0937_ A3 ) ( _0920_ A1 ) + USE SIGNAL
+ + ROUTED Metal2 ( 139440 173040 ) ( * 174160 )
+ NEW Metal3 ( 139440 173040 ) ( 146160 * )
+ NEW Metal2 ( 146160 151760 ) ( * 173040 )
+ NEW Metal2 ( 122640 187600 ) ( * 190960 )
+ NEW Metal3 ( 122640 187600 ) ( 139440 * )
+ NEW Metal2 ( 139440 174160 ) ( * 187600 )
+ NEW Metal2 ( 110320 187600 ) ( * 189840 )
+ NEW Metal3 ( 110320 187600 ) ( 122640 * )
+ NEW Metal1 ( 139440 174160 ) Via1_VV
+ NEW Metal2 ( 139440 173040 ) Via2_VH
+ NEW Metal2 ( 146160 173040 ) Via2_VH
+ NEW Metal1 ( 146160 151760 ) Via1_HV
+ NEW Metal1 ( 122640 190960 ) Via1_HV
+ NEW Metal2 ( 122640 187600 ) Via2_VH
+ NEW Metal2 ( 139440 187600 ) Via2_VH
+ NEW Metal1 ( 110320 189840 ) Via1_VV
+ NEW Metal2 ( 110320 187600 ) Via2_VH ;
+ - vga_clock.sec_counter\[4\] ( _1389_ Q ) ( _0949_ A1 ) ( _0941_ A1 ) ( _0940_ A1 ) ( _0911_ A1 ) + USE SIGNAL
+ + ROUTED Metal2 ( 111440 211120 ) ( 112560 * )
+ NEW Metal2 ( 112560 211120 ) ( * 223440 )
+ NEW Metal3 ( 90160 198800 ) ( 111440 * )
+ NEW Metal2 ( 95760 177520 ) ( * 198800 )
+ NEW Metal3 ( 95760 176400 ) ( 101360 * )
+ NEW Metal2 ( 95760 176400 ) ( * 177520 )
+ NEW Metal2 ( 106960 161840 ) ( * 176400 )
+ NEW Metal3 ( 101360 176400 ) ( 106960 * )
+ NEW Metal2 ( 111440 198800 ) ( * 211120 )
+ NEW Metal1 ( 112560 223440 ) Via1_HV
+ NEW Metal1 ( 90160 198800 ) Via1_VV
+ NEW Metal2 ( 90160 198800 ) Via2_VH
+ NEW Metal2 ( 111440 198800 ) Via2_VH
+ NEW Metal1 ( 95760 177520 ) Via1_VV
+ NEW Metal2 ( 95760 198800 ) Via2_VH
+ NEW Metal1 ( 101360 176400 ) Via1_HV
+ NEW Metal2 ( 101360 176400 ) Via2_VH
+ NEW Metal2 ( 95760 176400 ) Via2_VH
+ NEW Metal1 ( 106960 161840 ) Via1_HV
+ NEW Metal2 ( 106960 176400 ) Via2_VH
+ NEW Metal2 ( 90160 198800 ) RECT ( -280 -660 280 0 )
+ NEW Metal3 ( 95760 198800 ) RECT ( -1040 -280 0 280 )
+ NEW Metal2 ( 101360 176400 ) RECT ( -280 -660 280 0 ) ;
+ - vga_clock.sec_counter\[5\] ( _1390_ Q ) ( _0949_ A2 ) ( _0944_ A1 ) ( _0943_ A1 ) ( _0926_ A1 ) + USE SIGNAL
+ + ROUTED Metal2 ( 76720 170800 ) ( * 179760 )
+ NEW Metal3 ( 70000 168560 ) ( 76720 * )
+ NEW Metal2 ( 76720 168560 ) ( * 170800 )
+ NEW Metal2 ( 75600 151760 ) ( 76720 * )
+ NEW Metal2 ( 76720 151760 ) ( * 168560 )
+ NEW Metal2 ( 91280 201600 ) ( * 205520 )
+ NEW Metal2 ( 87920 179760 ) ( * 199920 )
+ NEW Metal2 ( 87920 201600 ) ( 91280 * )
+ NEW Metal2 ( 87920 199920 ) ( * 201600 )
+ NEW Metal3 ( 76720 179760 ) ( 87920 * )
+ NEW Metal1 ( 76720 170800 ) Via1_VV
+ NEW Metal2 ( 76720 179760 ) Via2_VH
+ NEW Metal1 ( 70000 168560 ) Via1_VV
+ NEW Metal2 ( 70000 168560 ) Via2_VH
+ NEW Metal2 ( 76720 168560 ) Via2_VH
+ NEW Metal1 ( 75600 151760 ) Via1_HV
+ NEW Metal1 ( 91280 205520 ) Via1_VV
+ NEW Metal1 ( 87920 199920 ) Via1_VV
+ NEW Metal2 ( 87920 179760 ) Via2_VH
+ NEW Metal2 ( 70000 168560 ) RECT ( -280 -660 280 0 ) ;
+ - vga_clock.sec_counter\[6\] ( _1391_ Q ) ( _0948_ A1 ) ( _0946_ A1 ) ( _0921_ A2 ) + USE SIGNAL
+ + ROUTED Metal2 ( 55440 184240 ) ( * 185360 )
+ NEW Metal3 ( 18480 185360 ) ( 55440 * )
+ NEW Metal2 ( 18480 183120 ) ( * 185360 )
+ NEW Metal2 ( 62160 185360 ) ( * 192080 )
+ NEW Metal3 ( 55440 185360 ) ( 62160 * )
+ NEW Metal3 ( 62160 192080 ) ( 73360 * )
+ NEW Metal1 ( 55440 184240 ) Via1_HV
+ NEW Metal2 ( 55440 185360 ) Via2_VH
+ NEW Metal2 ( 18480 185360 ) Via2_VH
+ NEW Metal1 ( 18480 183120 ) Via1_HV
+ NEW Metal1 ( 62160 192080 ) Via1_VV
+ NEW Metal2 ( 62160 185360 ) Via2_VH
+ NEW Metal1 ( 73360 192080 ) Via1_VV
+ NEW Metal2 ( 73360 192080 ) Via2_VH
+ NEW Metal2 ( 62160 192080 ) Via2_VH
+ NEW Metal2 ( 73360 192080 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 62160 192080 ) RECT ( -280 -1040 280 0 ) ;
+ - vga_clock.sec_counter\[7\] ( _1392_ Q ) ( _0948_ B ) ( _0921_ A1 ) + USE SIGNAL
+ + ROUTED Metal2 ( 64400 192080 ) ( * 198800 )
+ NEW Metal2 ( 62160 198800 ) ( 64400 * )
+ NEW Metal3 ( 64400 193200 ) ( 71120 * )
+ NEW Metal1 ( 64400 192080 ) Via1_VV
+ NEW Metal1 ( 62160 198800 ) Via1_HV
+ NEW Metal1 ( 71120 193200 ) Via1_VV
+ NEW Metal2 ( 71120 193200 ) Via2_VH
+ NEW Metal2 ( 64400 193200 ) Via2_VH
+ NEW Metal2 ( 71120 193200 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 64400 193200 ) RECT ( -280 -1040 280 0 ) ;
+ - vga_clock.sec_counter\[8\] ( _1393_ Q ) ( _0962_ A1 ) ( _0953_ A1 ) ( _0952_ A1 ) ( _0911_ A2 ) + USE SIGNAL
+ + ROUTED Metal2 ( 81200 217840 ) ( * 230160 )
+ NEW Metal3 ( 74480 230160 ) ( 81200 * )
+ NEW Metal3 ( 95760 224560 ) ( 115920 * )
+ NEW Metal2 ( 115920 224560 ) ( * 232400 )
+ NEW Metal3 ( 81200 224560 ) ( 95760 * )
+ NEW Metal1 ( 81200 217840 ) Via1_VV
+ NEW Metal2 ( 81200 230160 ) Via2_VH
+ NEW Metal1 ( 74480 230160 ) Via1_VV
+ NEW Metal2 ( 74480 230160 ) Via2_VH
+ NEW Metal2 ( 81200 224560 ) Via2_VH
+ NEW Metal1 ( 95760 224560 ) Via1_HV
+ NEW Metal2 ( 95760 224560 ) Via2_VH
+ NEW Metal1 ( 115920 224560 ) Via1_VV
+ NEW Metal2 ( 115920 224560 ) Via2_VH
+ NEW Metal1 ( 115920 232400 ) Via1_HV
+ NEW Metal2 ( 74480 230160 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 81200 224560 ) RECT ( -280 -1040 280 0 )
+ NEW Metal2 ( 95760 224560 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 115920 224560 ) RECT ( -280 -660 280 0 ) ;
+ - vga_clock.sec_counter\[9\] ( ANTENNA__0926__A2 I ) ( ANTENNA__0955__A1 I ) ( ANTENNA__0956__A1 I ) ( ANTENNA__0962__A2 I ) ( _1394_ Q ) ( _0962_ A2 ) ( _0956_ A1 )
+ ( _0955_ A1 ) ( _0926_ A2 ) + USE SIGNAL
+ + ROUTED Metal2 ( 62160 217840 ) ( * 218960 )
+ NEW Metal2 ( 57680 217840 ) ( * 218960 )
+ NEW Metal3 ( 57680 218960 ) ( 62160 * )
+ NEW Metal2 ( 57680 218960 ) ( * 223440 )
+ NEW Metal2 ( 53200 215600 ) ( * 218960 )
+ NEW Metal3 ( 53200 218960 ) ( 57680 * )
+ NEW Metal2 ( 47600 218960 ) ( * 224560 )
+ NEW Metal3 ( 47600 218960 ) ( 53200 * )
+ NEW Metal3 ( 91280 231280 ) ( 113680 * )
+ NEW Metal2 ( 91280 218960 ) ( * 231280 )
+ NEW Metal2 ( 96880 208880 ) ( * 218960 )
+ NEW Metal3 ( 91280 218960 ) ( 96880 * )
+ NEW Metal2 ( 90160 207760 ) ( 91280 * )
+ NEW Metal2 ( 91280 207760 ) ( * 218960 )
+ NEW Metal3 ( 62160 218960 ) ( 91280 * )
+ NEW Metal1 ( 62160 217840 ) Via1_VV
+ NEW Metal2 ( 62160 218960 ) Via2_VH
+ NEW Metal1 ( 57680 217840 ) Via1_VV
+ NEW Metal2 ( 57680 218960 ) Via2_VH
+ NEW Metal1 ( 57680 223440 ) Via1_HV
+ NEW Metal1 ( 53200 215600 ) Via1_VV
+ NEW Metal2 ( 53200 218960 ) Via2_VH
+ NEW Metal1 ( 47600 224560 ) Via1_HV
+ NEW Metal2 ( 47600 218960 ) Via2_VH
+ NEW Metal1 ( 91280 231280 ) Via1_VV
+ NEW Metal2 ( 91280 231280 ) Via2_VH
+ NEW Metal1 ( 113680 231280 ) Via1_HV
+ NEW Metal2 ( 113680 231280 ) Via2_VH
+ NEW Metal2 ( 91280 218960 ) Via2_VH
+ NEW Metal1 ( 96880 208880 ) Via1_VV
+ NEW Metal2 ( 96880 218960 ) Via2_VH
+ NEW Metal1 ( 90160 207760 ) Via1_VV
+ NEW Metal2 ( 91280 231280 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 113680 231280 ) RECT ( -280 -660 280 0 ) ;
+ - vga_clock.sec_d\[0\] ( ANTENNA__0783__B2 I ) ( ANTENNA__1296__A1 I ) ( ANTENNA__1310__A1 I ) ( ANTENNA__1314__A1 I ) ( ANTENNA__1316__A2 I ) ( ANTENNA__1317__A1 I ) ( _1488_ Q )
+ ( _1317_ A1 ) ( _1316_ A2 ) ( _1314_ A1 ) ( _1310_ A1 ) ( _1296_ A1 ) ( _0783_ B2 ) + USE SIGNAL
+ + ROUTED Metal3 ( 202160 444080 ) ( 207760 * )
+ NEW Metal3 ( 207760 437360 ) ( 217840 * )
+ NEW Metal2 ( 232400 437360 ) ( * 440720 )
+ NEW Metal3 ( 217840 437360 ) ( 232400 * )
+ NEW Metal2 ( 245840 380240 ) ( 248080 * )
+ NEW Metal2 ( 245840 374640 ) ( * 380240 )
+ NEW Metal2 ( 233520 408240 ) ( * 409360 )
+ NEW Metal3 ( 233520 408240 ) ( 245840 * )
+ NEW Metal2 ( 245840 380240 ) ( * 408240 )
+ NEW Metal2 ( 240240 408240 ) ( * 425040 )
+ NEW Metal2 ( 232400 409360 ) ( 233520 * )
+ NEW Metal2 ( 232400 435120 ) ( 239120 * )
+ NEW Metal2 ( 207760 435120 ) ( 208880 * )
+ NEW Metal2 ( 208880 428400 ) ( * 435120 )
+ NEW Metal2 ( 207760 435120 ) ( * 444080 )
+ NEW Metal2 ( 232400 409360 ) ( * 437360 )
+ NEW Metal3 ( 197680 444080 ) ( 202160 * )
+ NEW Metal2 ( 193200 427280 ) ( * 428400 )
+ NEW Metal3 ( 193200 428400 ) ( 201040 * )
+ NEW Metal3 ( 201040 428400 ) ( 208880 * )
+ NEW Metal1 ( 202160 444080 ) Via1_VV
+ NEW Metal2 ( 202160 444080 ) Via2_VH
+ NEW Metal2 ( 207760 444080 ) Via2_VH
+ NEW Metal1 ( 217840 437360 ) Via1_VV
+ NEW Metal2 ( 217840 437360 ) Via2_VH
+ NEW Metal2 ( 207760 437360 ) Via2_VH
+ NEW Metal1 ( 232400 440720 ) Via1_VV
+ NEW Metal2 ( 232400 437360 ) Via2_VH
+ NEW Metal1 ( 248080 380240 ) Via1_VV
+ NEW Metal1 ( 245840 374640 ) Via1_VV
+ NEW Metal1 ( 233520 409360 ) Via1_VV
+ NEW Metal2 ( 233520 408240 ) Via2_VH
+ NEW Metal2 ( 245840 408240 ) Via2_VH
+ NEW Metal1 ( 240240 425040 ) Via1_VV
+ NEW Metal2 ( 240240 408240 ) Via2_VH
+ NEW Metal1 ( 239120 435120 ) Via1_HV
+ NEW Metal1 ( 208880 428400 ) Via1_VV
+ NEW Metal2 ( 208880 428400 ) Via2_VH
+ NEW Metal1 ( 207760 435120 ) Via1_VV
+ NEW Metal1 ( 197680 444080 ) Via1_HV
+ NEW Metal2 ( 197680 444080 ) Via2_VH
+ NEW Metal1 ( 201040 428400 ) Via1_VV
+ NEW Metal2 ( 201040 428400 ) Via2_VH
+ NEW Metal1 ( 193200 427280 ) Via1_HV
+ NEW Metal2 ( 193200 428400 ) Via2_VH
+ NEW Metal2 ( 202160 444080 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 217840 437360 ) RECT ( -280 0 280 660 )
+ NEW Metal2 ( 207760 437360 ) RECT ( -280 0 280 1040 )
+ NEW Metal3 ( 240240 408240 ) RECT ( -1040 -280 0 280 )
+ NEW Metal2 ( 208880 428400 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 197680 444080 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 201040 428400 ) RECT ( -280 -660 280 0 ) ;
+ - vga_clock.sec_d\[1\] ( ANTENNA__0797__A1 I ) ( ANTENNA__1294__A2 I ) ( ANTENNA__1316__A1 I ) ( ANTENNA__1317__B I ) ( _1489_ Q ) ( _1317_ B ) ( _1316_ A1 )
+ ( _1294_ A2 ) ( _0797_ A1 ) + USE SIGNAL
+ + ROUTED Metal2 ( 225680 440720 ) ( 226800 * )
+ NEW Metal2 ( 245840 436800 ) ( * 459760 )
+ NEW Metal3 ( 249200 393680 ) ( 254800 * )
+ NEW Metal2 ( 249200 389200 ) ( * 393680 )
+ NEW Metal2 ( 250320 416080 ) ( * 426160 )
+ NEW Metal2 ( 249200 416080 ) ( 250320 * )
+ NEW Metal2 ( 249200 393680 ) ( * 416080 )
+ NEW Metal2 ( 250320 425040 ) ( 254800 * )
+ NEW Metal2 ( 245840 436800 ) ( 249200 * )
+ NEW Metal2 ( 249200 430640 ) ( * 436800 )
+ NEW Metal2 ( 249200 430640 ) ( 250320 * )
+ NEW Metal2 ( 250320 426160 ) ( * 430640 )
+ NEW Metal3 ( 225680 435120 ) ( 245840 * )
+ NEW Metal2 ( 245840 435120 ) ( * 436800 )
+ NEW Metal2 ( 220080 435120 ) ( * 436240 )
+ NEW Metal3 ( 220080 435120 ) ( 225680 * )
+ NEW Metal2 ( 210000 434000 ) ( * 435120 )
+ NEW Metal3 ( 210000 434000 ) ( 220080 * )
+ NEW Metal3 ( 220080 434000 ) ( * 435120 )
+ NEW Metal2 ( 210000 435120 ) ( * 440720 )
+ NEW Metal2 ( 225680 435120 ) ( * 440720 )
+ NEW Metal1 ( 245840 459760 ) Via1_HV
+ NEW Metal1 ( 226800 440720 ) Via1_VV
+ NEW Metal1 ( 210000 440720 ) Via1_VV
+ NEW Metal1 ( 254800 393680 ) Via1_VV
+ NEW Metal2 ( 254800 393680 ) Via2_VH
+ NEW Metal2 ( 249200 393680 ) Via2_VH
+ NEW Metal1 ( 249200 389200 ) Via1_VV
+ NEW Metal1 ( 250320 426160 ) Via1_VV
+ NEW Metal1 ( 254800 425040 ) Via1_VV
+ NEW Metal2 ( 225680 435120 ) Via2_VH
+ NEW Metal2 ( 245840 435120 ) Via2_VH
+ NEW Metal1 ( 220080 436240 ) Via1_VV
+ NEW Metal2 ( 220080 435120 ) Via2_VH
+ NEW Metal1 ( 210000 435120 ) Via1_VV
+ NEW Metal2 ( 210000 434000 ) Via2_VH
+ NEW Metal2 ( 254800 393680 ) RECT ( -280 -660 280 0 ) ;
+ - vga_clock.sec_d\[2\] ( _1490_ Q ) ( _1321_ A1 ) ( _1294_ A1 ) ( _0807_ B2 ) + USE SIGNAL
+ + ROUTED Metal2 ( 249200 418320 ) ( * 420560 )
+ NEW Metal3 ( 249200 420560 ) ( 257040 * )
+ NEW Metal2 ( 257040 388080 ) ( * 420560 )
+ NEW Metal2 ( 249200 420560 ) ( * 425040 )
+ NEW Metal3 ( 224560 427280 ) ( 249200 * )
+ NEW Metal2 ( 249200 425040 ) ( * 427280 )
+ NEW Metal1 ( 249200 418320 ) Via1_HV
+ NEW Metal2 ( 249200 420560 ) Via2_VH
+ NEW Metal2 ( 257040 420560 ) Via2_VH
+ NEW Metal1 ( 257040 388080 ) Via1_VV
+ NEW Metal1 ( 249200 425040 ) Via1_VV
+ NEW Metal1 ( 224560 427280 ) Via1_HV
+ NEW Metal2 ( 224560 427280 ) Via2_VH
+ NEW Metal2 ( 249200 427280 ) Via2_VH
+ NEW Metal2 ( 224560 427280 ) RECT ( -280 -660 280 0 ) ;
+ - vga_clock.sec_u\[0\] ( ANTENNA__0783__A1 I ) ( ANTENNA__1312__A2 I ) ( ANTENNA__1325__A1 I ) ( ANTENNA__1327__A1 I ) ( ANTENNA__1332__A2 I ) ( ANTENNA__1335__A3 I ) ( _1491_ Q )
+ ( _1335_ A3 ) ( _1332_ A2 ) ( _1327_ A1 ) ( _1325_ A1 ) ( _1312_ A2 ) ( _0783_ A1 ) + USE SIGNAL
+ + ROUTED Metal2 ( 235760 374640 ) ( * 378000 )
+ NEW Metal3 ( 235760 378000 ) ( 252560 * )
+ NEW Metal3 ( 207760 378000 ) ( 235760 * )
+ NEW Metal2 ( 206640 388080 ) ( 207760 * )
+ NEW Metal2 ( 207760 378000 ) ( * 388080 )
+ NEW Metal2 ( 215600 378000 ) ( * 393680 )
+ NEW Metal2 ( 205520 395920 ) ( 206640 * )
+ NEW Metal2 ( 206640 388080 ) ( * 395920 )
+ NEW Metal2 ( 210000 395920 ) ( * 403760 )
+ NEW Metal2 ( 206640 395920 ) ( 210000 * )
+ NEW Metal2 ( 205520 409360 ) ( 207760 * )
+ NEW Metal2 ( 207760 403760 ) ( * 409360 )
+ NEW Metal2 ( 207760 403760 ) ( 210000 * )
+ NEW Metal2 ( 207760 365680 ) ( * 378000 )
+ NEW Metal2 ( 207760 364560 ) ( * 365680 )
+ NEW Metal2 ( 202160 355600 ) ( 203280 * )
+ NEW Metal2 ( 202160 355600 ) ( * 364560 )
+ NEW Metal2 ( 193200 406000 ) ( * 409360 )
+ NEW Metal3 ( 193200 409360 ) ( 197680 * )
+ NEW Metal3 ( 198800 364560 ) ( 207760 * )
+ NEW Metal3 ( 197680 409360 ) ( 205520 * )
+ NEW Metal1 ( 235760 374640 ) Via1_VV
+ NEW Metal2 ( 235760 378000 ) Via2_VH
+ NEW Metal1 ( 252560 378000 ) Via1_VV
+ NEW Metal2 ( 252560 378000 ) Via2_VH
+ NEW Metal1 ( 207760 378000 ) Via1_VV
+ NEW Metal2 ( 207760 378000 ) Via2_VH
+ NEW Metal1 ( 206640 388080 ) Via1_VV
+ NEW Metal1 ( 215600 393680 ) Via1_VV
+ NEW Metal2 ( 215600 378000 ) Via2_VH
+ NEW Metal1 ( 205520 395920 ) Via1_HV
+ NEW Metal1 ( 210000 403760 ) Via1_HV
+ NEW Metal1 ( 205520 409360 ) Via1_VV
+ NEW Metal2 ( 205520 409360 ) Via2_VH
+ NEW Metal1 ( 207760 365680 ) Via1_VV
+ NEW Metal2 ( 207760 364560 ) Via2_VH
+ NEW Metal1 ( 203280 355600 ) Via1_HV
+ NEW Metal2 ( 202160 364560 ) Via2_VH
+ NEW Metal1 ( 197680 409360 ) Via1_VV
+ NEW Metal2 ( 197680 409360 ) Via2_VH
+ NEW Metal1 ( 193200 406000 ) Via1_VV
+ NEW Metal2 ( 193200 409360 ) Via2_VH
+ NEW Metal1 ( 198800 364560 ) Via1_HV
+ NEW Metal2 ( 198800 364560 ) Via2_VH
+ NEW Metal2 ( 252560 378000 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 207760 378000 ) RECT ( -280 -660 280 0 )
+ NEW Metal3 ( 215600 378000 ) RECT ( -1040 -280 0 280 )
+ NEW Metal2 ( 205520 409360 ) RECT ( -280 -1040 280 0 )
+ NEW Metal3 ( 202160 364560 ) RECT ( 0 -280 1040 280 )
+ NEW Metal2 ( 197680 409360 ) RECT ( -280 0 280 660 )
+ NEW Metal2 ( 198800 364560 ) RECT ( -280 -660 280 0 ) ;
+ - vga_clock.sec_u\[1\] ( ANTENNA__0797__B2 I ) ( ANTENNA__1311__A2 I ) ( ANTENNA__1329__A1 I ) ( ANTENNA__1330__A1 I ) ( ANTENNA__1332__A1 I ) ( ANTENNA__1335__A2 I ) ( _1492_ Q )
+ ( _1335_ A2 ) ( _1332_ A1 ) ( _1330_ A1 ) ( _1329_ A1 ) ( _1311_ A2 ) ( _0797_ B2 ) + USE SIGNAL
+ + ROUTED Metal3 ( 230160 388080 ) ( 239120 * )
+ NEW Metal3 ( 203280 388080 ) ( 230160 * )
+ NEW Metal2 ( 212240 388080 ) ( * 404880 )
+ NEW Metal2 ( 208880 409360 ) ( 212240 * )
+ NEW Metal2 ( 212240 404880 ) ( * 409360 )
+ NEW Metal2 ( 208880 409360 ) ( * 418320 )
+ NEW Metal2 ( 202160 374640 ) ( * 378000 )
+ NEW Metal2 ( 180880 418320 ) ( * 419440 )
+ NEW Metal3 ( 180880 418320 ) ( 187600 * )
+ NEW Metal2 ( 176400 412720 ) ( * 418320 )
+ NEW Metal3 ( 176400 418320 ) ( 180880 * )
+ NEW Metal2 ( 188720 388080 ) ( * 394800 )
+ NEW Metal3 ( 183120 394800 ) ( 188720 * )
+ NEW Metal2 ( 180880 394800 ) ( * 403760 )
+ NEW Metal2 ( 180880 394800 ) ( 183120 * )
+ NEW Metal2 ( 201040 378000 ) ( * 388080 )
+ NEW Metal2 ( 198800 374640 ) ( 202160 * )
+ NEW Metal2 ( 201040 378000 ) ( 202160 * )
+ NEW Metal2 ( 201040 388080 ) ( 203280 * )
+ NEW Metal3 ( 188720 388080 ) ( 203280 * )
+ NEW Metal3 ( 187600 418320 ) ( 208880 * )
+ NEW Metal1 ( 230160 388080 ) Via1_VV
+ NEW Metal2 ( 230160 388080 ) Via2_VH
+ NEW Metal1 ( 239120 388080 ) Via1_VV
+ NEW Metal2 ( 239120 388080 ) Via2_VH
+ NEW Metal1 ( 203280 388080 ) Via1_HV
+ NEW Metal2 ( 203280 388080 ) Via2_VH
+ NEW Metal1 ( 212240 404880 ) Via1_VV
+ NEW Metal2 ( 212240 388080 ) Via2_VH
+ NEW Metal1 ( 208880 409360 ) Via1_VV
+ NEW Metal2 ( 208880 418320 ) Via2_VH
+ NEW Metal1 ( 202160 418320 ) Via1_VV
+ NEW Metal2 ( 202160 418320 ) Via2_VH
+ NEW Metal1 ( 187600 418320 ) Via1_VV
+ NEW Metal2 ( 187600 418320 ) Via2_VH
+ NEW Metal1 ( 180880 419440 ) Via1_VV
+ NEW Metal2 ( 180880 418320 ) Via2_VH
+ NEW Metal1 ( 176400 412720 ) Via1_HV
+ NEW Metal2 ( 176400 418320 ) Via2_VH
+ NEW Metal1 ( 188720 394800 ) Via1_VV
+ NEW Metal2 ( 188720 388080 ) Via2_VH
+ NEW Metal1 ( 183120 394800 ) Via1_VV
+ NEW Metal2 ( 183120 394800 ) Via2_VH
+ NEW Metal2 ( 188720 394800 ) Via2_VH
+ NEW Metal1 ( 180880 403760 ) Via1_VV
+ NEW Metal1 ( 198800 374640 ) Via1_VV
+ NEW Metal2 ( 230160 388080 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 239120 388080 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 203280 388080 ) RECT ( -280 -660 280 0 )
+ NEW Metal3 ( 212240 388080 ) RECT ( -1040 -280 0 280 )
+ NEW Metal2 ( 202160 418320 ) RECT ( -280 -660 280 0 )
+ NEW Metal3 ( 202160 418320 ) RECT ( 0 -280 1040 280 )
+ NEW Metal2 ( 187600 418320 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 183120 394800 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 188720 394800 ) RECT ( -280 -1040 280 0 ) ;
+ - vga_clock.sec_u\[2\] ( _1493_ Q ) ( _1335_ A1 ) ( _1333_ A1 ) ( _1312_ A1 ) ( _0807_ A1 ) + USE SIGNAL
+ + ROUTED Metal2 ( 250320 390320 ) ( * 397040 )
+ NEW Metal3 ( 250320 390320 ) ( 261520 * )
+ NEW Metal2 ( 218960 388080 ) ( * 390320 )
+ NEW Metal3 ( 218960 390320 ) ( 250320 * )
+ NEW Metal2 ( 202160 391440 ) ( * 395920 )
+ NEW Metal3 ( 202160 391440 ) ( 218960 * )
+ NEW Metal3 ( 218960 390320 ) ( * 391440 )
+ NEW Metal2 ( 202160 390320 ) ( * 391440 )
+ NEW Metal2 ( 201040 390320 ) ( 202160 * )
+ NEW Metal1 ( 250320 397040 ) Via1_HV
+ NEW Metal2 ( 250320 390320 ) Via2_VH
+ NEW Metal1 ( 261520 390320 ) Via1_VV
+ NEW Metal2 ( 261520 390320 ) Via2_VH
+ NEW Metal1 ( 218960 388080 ) Via1_HV
+ NEW Metal2 ( 218960 390320 ) Via2_VH
+ NEW Metal1 ( 202160 395920 ) Via1_HV
+ NEW Metal2 ( 202160 391440 ) Via2_VH
+ NEW Metal1 ( 201040 390320 ) Via1_VV
+ NEW Metal2 ( 261520 390320 ) RECT ( -280 -660 280 0 ) ;
+ - vga_clock.sec_u\[3\] ( _1494_ Q ) ( _1336_ A1 ) ( _1311_ A1 ) ( _0814_ I ) + USE SIGNAL
+ + ROUTED Metal2 ( 202160 381360 ) ( * 385840 )
+ NEW Metal2 ( 189840 385840 ) ( * 388080 )
+ NEW Metal2 ( 189840 388080 ) ( * 393680 )
+ NEW Metal2 ( 179760 381360 ) ( * 385840 )
+ NEW Metal3 ( 179760 385840 ) ( 189840 * )
+ NEW Metal3 ( 189840 385840 ) ( 202160 * )
+ NEW Metal1 ( 202160 381360 ) Via1_VV
+ NEW Metal2 ( 202160 385840 ) Via2_VH
+ NEW Metal1 ( 189840 388080 ) Via1_HV
+ NEW Metal2 ( 189840 385840 ) Via2_VH
+ NEW Metal1 ( 189840 393680 ) Via1_VV
+ NEW Metal1 ( 179760 381360 ) Via1_HV
+ NEW Metal2 ( 179760 385840 ) Via2_VH ;
+ - vga_clock.vga_0.hc\[0\] ( _1375_ Q ) ( _1010_ A1 ) ( _0892_ A2 ) ( _0891_ A2 ) ( _0890_ A2 ) ( _0887_ A1 ) ( _0880_ A2 ) + USE SIGNAL
+ + ROUTED Metal2 ( 272720 240240 ) ( 273840 * )
+ NEW Metal2 ( 273840 240240 ) ( * 248080 )
+ NEW Metal2 ( 274960 217840 ) ( * 240240 )
+ NEW Metal2 ( 273840 240240 ) ( 274960 * )
+ NEW Metal3 ( 274960 239120 ) ( 297360 * )
+ NEW Metal2 ( 267120 248080 ) ( * 262640 )
+ NEW Metal2 ( 267120 232400 ) ( * 248080 )
+ NEW Metal2 ( 259280 233520 ) ( * 235760 )
+ NEW Metal3 ( 259280 235760 ) ( 267120 * )
+ NEW Metal3 ( 267120 248080 ) ( 273840 * )
+ NEW Metal1 ( 273840 248080 ) Via1_VV
+ NEW Metal2 ( 273840 248080 ) Via2_VH
+ NEW Metal1 ( 272720 240240 ) Via1_HV
+ NEW Metal1 ( 274960 217840 ) Via1_VV
+ NEW Metal1 ( 297360 239120 ) Via1_VV
+ NEW Metal2 ( 297360 239120 ) Via2_VH
+ NEW Metal2 ( 274960 239120 ) Via2_VH
+ NEW Metal2 ( 267120 248080 ) Via2_VH
+ NEW Metal1 ( 267120 262640 ) Via1_VV
+ NEW Metal1 ( 267120 232400 ) Via1_VV
+ NEW Metal1 ( 259280 233520 ) Via1_VV
+ NEW Metal2 ( 259280 235760 ) Via2_VH
+ NEW Metal2 ( 267120 235760 ) Via2_VH
+ NEW Metal2 ( 273840 248080 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 297360 239120 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 274960 239120 ) RECT ( -280 -1040 280 0 )
+ NEW Metal2 ( 267120 235760 ) RECT ( -280 -1040 280 0 ) ;
+ - vga_clock.vga_0.hc\[1\] ( _1376_ Q ) ( _1012_ A1 ) ( _0892_ A1 ) ( _0891_ A1 ) ( _0890_ A1 ) ( _0880_ A1 ) + USE SIGNAL
+ + ROUTED Metal2 ( 274960 248080 ) ( * 264880 )
+ NEW Metal2 ( 270480 264880 ) ( 274960 * )
+ NEW Metal2 ( 270480 263760 ) ( * 264880 )
+ NEW Metal2 ( 270480 232400 ) ( * 263760 )
+ NEW Metal2 ( 270480 215600 ) ( 272720 * )
+ NEW Metal2 ( 270480 215600 ) ( * 232400 )
+ NEW Metal3 ( 270480 224560 ) ( 288400 * )
+ NEW Metal2 ( 308560 224560 ) ( * 239120 )
+ NEW Metal3 ( 288400 224560 ) ( 308560 * )
+ NEW Metal1 ( 274960 248080 ) Via1_VV
+ NEW Metal1 ( 270480 263760 ) Via1_VV
+ NEW Metal1 ( 270480 232400 ) Via1_VV
+ NEW Metal1 ( 272720 215600 ) Via1_VV
+ NEW Metal1 ( 288400 224560 ) Via1_HV
+ NEW Metal2 ( 288400 224560 ) Via2_VH
+ NEW Metal2 ( 270480 224560 ) Via2_VH
+ NEW Metal1 ( 308560 239120 ) Via1_VV
+ NEW Metal2 ( 308560 224560 ) Via2_VH
+ NEW Metal2 ( 288400 224560 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 270480 224560 ) RECT ( -280 -1040 280 0 ) ;
+ - vga_clock.vga_0.hc\[2\] ( _1377_ Q ) ( _1014_ A1 ) ( _0892_ B ) ( _0880_ A3 ) + USE SIGNAL
+ + ROUTED Metal3 ( 286160 255920 ) ( 299600 * )
+ NEW Metal2 ( 299600 255920 ) ( * 270480 )
+ NEW Metal2 ( 298480 270480 ) ( 299600 * )
+ NEW Metal2 ( 272720 255920 ) ( * 262640 )
+ NEW Metal3 ( 272720 255920 ) ( 286160 * )
+ NEW Metal2 ( 272720 248080 ) ( * 255920 )
+ NEW Metal1 ( 286160 255920 ) Via1_HV
+ NEW Metal2 ( 286160 255920 ) Via2_VH
+ NEW Metal2 ( 299600 255920 ) Via2_VH
+ NEW Metal1 ( 298480 270480 ) Via1_VV
+ NEW Metal1 ( 272720 262640 ) Via1_VV
+ NEW Metal2 ( 272720 255920 ) Via2_VH
+ NEW Metal1 ( 272720 248080 ) Via1_VV
+ NEW Metal2 ( 286160 255920 ) RECT ( -280 -660 280 0 ) ;
+ - vga_clock.vga_0.hc\[3\] ( ANTENNA__0857__A1 I ) ( ANTENNA__0894__A1 I ) ( ANTENNA__0895__A1 I ) ( ANTENNA__1016__A1 I ) ( _1378_ Q ) ( _1016_ A1 ) ( _0895_ A1 )
+ ( _0894_ A1 ) ( _0857_ A1 ) + USE SIGNAL
+ + ROUTED Metal3 ( 281680 246960 ) ( 291760 * )
+ NEW Metal2 ( 281680 246960 ) ( * 251440 )
+ NEW Metal2 ( 222320 252560 ) ( * 254800 )
+ NEW Metal3 ( 222320 251440 ) ( * 252560 )
+ NEW Metal2 ( 213360 252560 ) ( * 261520 )
+ NEW Metal3 ( 213360 252560 ) ( 222320 * )
+ NEW Metal3 ( 206640 261520 ) ( 213360 * )
+ NEW Metal2 ( 205520 255920 ) ( 206640 * )
+ NEW Metal2 ( 206640 255920 ) ( * 261520 )
+ NEW Metal2 ( 207760 240240 ) ( * 255920 )
+ NEW Metal2 ( 206640 255920 ) ( 207760 * )
+ NEW Metal3 ( 195440 249200 ) ( 207760 * )
+ NEW Metal2 ( 201040 233520 ) ( 202160 * )
+ NEW Metal2 ( 202160 233520 ) ( * 235760 )
+ NEW Metal3 ( 202160 235760 ) ( * 236880 )
+ NEW Metal3 ( 202160 236880 ) ( 207760 * )
+ NEW Metal2 ( 207760 236880 ) ( * 240240 )
+ NEW Metal3 ( 222320 251440 ) ( 281680 * )
+ NEW Metal1 ( 281680 246960 ) Via1_VV
+ NEW Metal2 ( 281680 246960 ) Via2_VH
+ NEW Metal1 ( 291760 246960 ) Via1_VV
+ NEW Metal2 ( 291760 246960 ) Via2_VH
+ NEW Metal2 ( 281680 251440 ) Via2_VH
+ NEW Metal1 ( 222320 254800 ) Via1_VV
+ NEW Metal2 ( 222320 252560 ) Via2_VH
+ NEW Metal1 ( 213360 261520 ) Via1_VV
+ NEW Metal2 ( 213360 252560 ) Via2_VH
+ NEW Metal1 ( 206640 261520 ) Via1_HV
+ NEW Metal2 ( 206640 261520 ) Via2_VH
+ NEW Metal2 ( 213360 261520 ) Via2_VH
+ NEW Metal1 ( 205520 255920 ) Via1_VV
+ NEW Metal1 ( 207760 240240 ) Via1_VV
+ NEW Metal1 ( 195440 249200 ) Via1_VV
+ NEW Metal2 ( 195440 249200 ) Via2_VH
+ NEW Metal2 ( 207760 249200 ) Via2_VH
+ NEW Metal1 ( 201040 233520 ) Via1_VV
+ NEW Metal2 ( 202160 235760 ) Via2_VH
+ NEW Metal2 ( 207760 236880 ) Via2_VH
+ NEW Metal2 ( 281680 246960 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 291760 246960 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 206640 261520 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 213360 261520 ) RECT ( -280 -1040 280 0 )
+ NEW Metal2 ( 195440 249200 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 207760 249200 ) RECT ( -280 -1040 280 0 ) ;
+ - vga_clock.vga_0.hc\[4\] ( _1379_ Q ) ( _1019_ A1 ) ( _0897_ A1 ) ( _0857_ A2 ) + USE SIGNAL
+ + ROUTED Metal3 ( 220080 254800 ) ( 232400 * )
+ NEW Metal2 ( 178640 254800 ) ( * 255920 )
+ NEW Metal3 ( 178640 254800 ) ( 220080 * )
+ NEW Metal2 ( 189840 238000 ) ( * 254800 )
+ NEW Metal1 ( 220080 254800 ) Via1_VV
+ NEW Metal2 ( 220080 254800 ) Via2_VH
+ NEW Metal1 ( 232400 254800 ) Via1_VV
+ NEW Metal2 ( 232400 254800 ) Via2_VH
+ NEW Metal1 ( 178640 255920 ) Via1_HV
+ NEW Metal2 ( 178640 254800 ) Via2_VH
+ NEW Metal1 ( 189840 238000 ) Via1_VV
+ NEW Metal2 ( 189840 254800 ) Via2_VH
+ NEW Metal2 ( 220080 254800 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 232400 254800 ) RECT ( -280 -660 280 0 )
+ NEW Metal3 ( 189840 254800 ) RECT ( -1040 -280 0 280 ) ;
+ - vga_clock.vga_0.hc\[5\] ( ANTENNA__0859__A1 I ) ( ANTENNA__0882__A1 I ) ( ANTENNA__0899__A1 I ) ( ANTENNA__0900__A1 I ) ( ANTENNA__1021__A1 I ) ( _1380_ Q ) ( _1021_ A1 )
+ ( _0900_ A1 ) ( _0899_ A1 ) ( _0882_ A1 ) ( _0859_ A1 ) + USE SIGNAL
+ + ROUTED Metal3 ( 286160 249200 ) ( 298480 * )
+ NEW Metal2 ( 298480 249200 ) ( * 254800 )
+ NEW Metal2 ( 213360 240240 ) ( 215600 * )
+ NEW Metal2 ( 213360 240240 ) ( * 248080 )
+ NEW Metal3 ( 213360 248080 ) ( * 249200 )
+ NEW Metal3 ( 213360 249200 ) ( 216720 * )
+ NEW Metal2 ( 207760 233520 ) ( 208880 * )
+ NEW Metal2 ( 208880 233520 ) ( * 240240 )
+ NEW Metal2 ( 208880 240240 ) ( 213360 * )
+ NEW Metal2 ( 198800 238000 ) ( * 239120 )
+ NEW Metal3 ( 198800 239120 ) ( 208880 * )
+ NEW Metal2 ( 195440 233520 ) ( * 238000 )
+ NEW Metal2 ( 195440 238000 ) ( 198800 * )
+ NEW Metal2 ( 188720 230160 ) ( * 231280 )
+ NEW Metal2 ( 188720 231280 ) ( 194320 * )
+ NEW Metal2 ( 194320 231280 ) ( * 233520 )
+ NEW Metal2 ( 194320 233520 ) ( 195440 * )
+ NEW Metal3 ( 183120 239120 ) ( 198800 * )
+ NEW Metal2 ( 178640 233520 ) ( * 239120 )
+ NEW Metal3 ( 178640 239120 ) ( 183120 * )
+ NEW Metal2 ( 177520 240240 ) ( 178640 * )
+ NEW Metal2 ( 178640 239120 ) ( * 240240 )
+ NEW Metal3 ( 216720 249200 ) ( 286160 * )
+ NEW Metal1 ( 286160 249200 ) Via1_VV
+ NEW Metal2 ( 286160 249200 ) Via2_VH
+ NEW Metal2 ( 298480 249200 ) Via2_VH
+ NEW Metal1 ( 298480 254800 ) Via1_VV
+ NEW Metal1 ( 216720 249200 ) Via1_VV
+ NEW Metal2 ( 216720 249200 ) Via2_VH
+ NEW Metal1 ( 215600 240240 ) Via1_VV
+ NEW Metal2 ( 213360 248080 ) Via2_VH
+ NEW Metal1 ( 207760 233520 ) Via1_VV
+ NEW Metal1 ( 198800 238000 ) Via1_VV
+ NEW Metal2 ( 198800 239120 ) Via2_VH
+ NEW Metal2 ( 208880 239120 ) Via2_VH
+ NEW Metal1 ( 195440 233520 ) Via1_VV
+ NEW Metal1 ( 188720 230160 ) Via1_VV
+ NEW Metal1 ( 183120 239120 ) Via1_VV
+ NEW Metal2 ( 183120 239120 ) Via2_VH
+ NEW Metal1 ( 178640 233520 ) Via1_VV
+ NEW Metal2 ( 178640 239120 ) Via2_VH
+ NEW Metal1 ( 177520 240240 ) Via1_HV
+ NEW Metal2 ( 286160 249200 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 216720 249200 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 208880 239120 ) RECT ( -280 -1040 280 0 )
+ NEW Metal2 ( 183120 239120 ) RECT ( -280 -660 280 0 ) ;
+ - vga_clock.vga_0.hc\[6\] ( _1381_ Q ) ( _1030_ A3 ) ( _1025_ A1 ) ( _0905_ A1 ) ( _0903_ A1 ) ( _0902_ A1 ) ( _0858_ A2 )
+ ( _0834_ A2 ) + USE SIGNAL
+ + ROUTED Metal2 ( 214480 216720 ) ( * 217840 )
+ NEW Metal3 ( 214480 217840 ) ( 235760 * )
+ NEW Metal2 ( 235760 217840 ) ( * 221200 )
+ NEW Metal2 ( 205520 220080 ) ( * 222320 )
+ NEW Metal3 ( 205520 220080 ) ( 210000 * )
+ NEW Metal3 ( 210000 217840 ) ( * 220080 )
+ NEW Metal3 ( 210000 217840 ) ( 214480 * )
+ NEW Metal2 ( 206640 207760 ) ( * 210000 )
+ NEW Metal3 ( 206640 210000 ) ( 214480 * )
+ NEW Metal2 ( 214480 210000 ) ( * 216720 )
+ NEW Metal2 ( 193200 217840 ) ( * 221200 )
+ NEW Metal3 ( 193200 217840 ) ( 205520 * )
+ NEW Metal3 ( 205520 217840 ) ( * 220080 )
+ NEW Metal2 ( 188720 216720 ) ( * 217840 )
+ NEW Metal3 ( 188720 217840 ) ( 193200 * )
+ NEW Metal2 ( 171920 217840 ) ( * 222320 )
+ NEW Metal3 ( 171920 217840 ) ( 188720 * )
+ NEW Metal2 ( 167440 214480 ) ( * 217840 )
+ NEW Metal3 ( 167440 217840 ) ( 171920 * )
+ NEW Metal1 ( 214480 216720 ) Via1_VV
+ NEW Metal2 ( 214480 217840 ) Via2_VH
+ NEW Metal2 ( 235760 217840 ) Via2_VH
+ NEW Metal1 ( 235760 221200 ) Via1_VV
+ NEW Metal1 ( 205520 222320 ) Via1_VV
+ NEW Metal2 ( 205520 220080 ) Via2_VH
+ NEW Metal1 ( 206640 207760 ) Via1_VV
+ NEW Metal2 ( 206640 210000 ) Via2_VH
+ NEW Metal2 ( 214480 210000 ) Via2_VH
+ NEW Metal1 ( 193200 221200 ) Via1_VV
+ NEW Metal2 ( 193200 217840 ) Via2_VH
+ NEW Metal1 ( 188720 216720 ) Via1_VV
+ NEW Metal2 ( 188720 217840 ) Via2_VH
+ NEW Metal1 ( 171920 222320 ) Via1_VV
+ NEW Metal2 ( 171920 217840 ) Via2_VH
+ NEW Metal1 ( 167440 214480 ) Via1_HV
+ NEW Metal2 ( 167440 217840 ) Via2_VH ;
+ - vga_clock.vga_0.hc\[7\] ( _1382_ Q ) ( _1030_ A2 ) ( _0905_ B ) ( _0858_ A1 ) ( _0834_ A1 ) + USE SIGNAL
+ + ROUTED Metal2 ( 190960 193200 ) ( * 215600 )
+ NEW Metal2 ( 189840 193200 ) ( 190960 * )
+ NEW Metal3 ( 190960 206640 ) ( 207760 * )
+ NEW Metal2 ( 216720 214480 ) ( * 215600 )
+ NEW Metal3 ( 207760 214480 ) ( 216720 * )
+ NEW Metal2 ( 207760 206640 ) ( * 214480 )
+ NEW Metal2 ( 207760 218960 ) ( * 221200 )
+ NEW Metal3 ( 207760 214480 ) ( * 218960 )
+ NEW Metal1 ( 190960 215600 ) Via1_VV
+ NEW Metal1 ( 189840 193200 ) Via1_HV
+ NEW Metal1 ( 207760 206640 ) Via1_VV
+ NEW Metal2 ( 207760 206640 ) Via2_VH
+ NEW Metal2 ( 190960 206640 ) Via2_VH
+ NEW Metal1 ( 216720 215600 ) Via1_HV
+ NEW Metal2 ( 216720 214480 ) Via2_VH
+ NEW Metal2 ( 207760 214480 ) Via2_VH
+ NEW Metal1 ( 207760 221200 ) Via1_VV
+ NEW Metal2 ( 207760 218960 ) Via2_VH
+ NEW Metal2 ( 207760 206640 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 190960 206640 ) RECT ( -280 -1040 280 0 ) ;
+ - vga_clock.vga_0.hc\[8\] ( _1383_ Q ) ( _1030_ A1 ) ( _1028_ I ) ( _0909_ A1 ) ( _0908_ A1 ) ( _0907_ A1 ) ( _0888_ A1 )
+ ( _0884_ A1 ) ( _0835_ A1 ) + USE SIGNAL
+ + ROUTED Metal2 ( 203280 185360 ) ( * 186480 )
+ NEW Metal3 ( 194320 186480 ) ( 203280 * )
+ NEW Metal2 ( 194320 177520 ) ( * 186480 )
+ NEW Metal3 ( 194320 190960 ) ( 198800 * )
+ NEW Metal2 ( 194320 186480 ) ( * 190960 )
+ NEW Metal2 ( 198800 190960 ) ( * 199920 )
+ NEW Metal3 ( 198800 199920 ) ( 217840 * )
+ NEW Metal2 ( 222320 201040 ) ( * 207760 )
+ NEW Metal3 ( 217840 201040 ) ( 222320 * )
+ NEW Metal3 ( 217840 199920 ) ( * 201040 )
+ NEW Metal2 ( 229040 201040 ) ( * 206640 )
+ NEW Metal2 ( 227920 201040 ) ( 229040 * )
+ NEW Metal3 ( 222320 201040 ) ( 227920 * )
+ NEW Metal2 ( 235760 184240 ) ( * 186480 )
+ NEW Metal3 ( 229040 186480 ) ( 235760 * )
+ NEW Metal2 ( 229040 186480 ) ( * 201040 )
+ NEW Metal2 ( 218960 208880 ) ( * 216160 )
+ NEW Metal2 ( 217840 208880 ) ( 218960 * )
+ NEW Metal2 ( 217840 199920 ) ( * 208880 )
+ NEW Metal1 ( 203280 185360 ) Via1_VV
+ NEW Metal2 ( 203280 186480 ) Via2_VH
+ NEW Metal2 ( 194320 186480 ) Via2_VH
+ NEW Metal1 ( 194320 177520 ) Via1_HV
+ NEW Metal1 ( 198800 190960 ) Via1_VV
+ NEW Metal2 ( 198800 190960 ) Via2_VH
+ NEW Metal2 ( 194320 190960 ) Via2_VH
+ NEW Metal1 ( 198800 199920 ) Via1_VV
+ NEW Metal1 ( 217840 199920 ) Via1_HV
+ NEW Metal2 ( 217840 199920 ) Via2_VH
+ NEW Metal2 ( 198800 199920 ) Via2_VH
+ NEW Metal1 ( 222320 207760 ) Via1_HV
+ NEW Metal2 ( 222320 201040 ) Via2_VH
+ NEW Metal1 ( 229040 206640 ) Via1_VV
+ NEW Metal2 ( 227920 201040 ) Via2_VH
+ NEW Metal1 ( 235760 184240 ) Via1_HV
+ NEW Metal2 ( 235760 186480 ) Via2_VH
+ NEW Metal2 ( 229040 186480 ) Via2_VH
+ NEW Metal1 ( 218960 216160 ) Via1_VV
+ NEW Metal2 ( 198800 190960 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 217840 199920 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 198800 199920 ) RECT ( -280 -1040 280 0 ) ;
+ - vga_clock.vga_0.hc\[9\] ( ANTENNA__0835__A2 I ) ( ANTENNA__0884__A2 I ) ( ANTENNA__0888__A2 I ) ( ANTENNA__0909__B I ) ( ANTENNA__1033__A1 I ) ( _1384_ Q ) ( _1033_ A1 )
+ ( _0909_ B ) ( _0888_ A2 ) ( _0884_ A2 ) ( _0835_ A2 ) + USE SIGNAL
+ + ROUTED Metal2 ( 195440 170800 ) ( * 183120 )
+ NEW Metal3 ( 182000 170800 ) ( 195440 * )
+ NEW Metal3 ( 195440 184240 ) ( 205520 * )
+ NEW Metal2 ( 195440 183120 ) ( * 184240 )
+ NEW Metal3 ( 205520 184240 ) ( 212240 * )
+ NEW Metal3 ( 212240 184240 ) ( 217840 * )
+ NEW Metal2 ( 212240 184240 ) ( * 198800 )
+ NEW Metal2 ( 207760 198800 ) ( 212240 * )
+ NEW Metal2 ( 220080 184240 ) ( * 199920 )
+ NEW Metal2 ( 217840 184240 ) ( 220080 * )
+ NEW Metal2 ( 218960 206640 ) ( 220080 * )
+ NEW Metal2 ( 220080 199920 ) ( * 206640 )
+ NEW Metal2 ( 218960 218960 ) ( * 221200 )
+ NEW Metal4 ( 218960 213360 ) ( * 218960 )
+ NEW Metal3 ( 218960 213360 ) ( 220080 * )
+ NEW Metal2 ( 220080 206640 ) ( * 213360 )
+ NEW Metal2 ( 231280 213360 ) ( * 215600 )
+ NEW Metal3 ( 220080 213360 ) ( 231280 * )
+ NEW Metal1 ( 195440 183120 ) Via1_VV
+ NEW Metal2 ( 195440 170800 ) Via2_VH
+ NEW Metal1 ( 182000 170800 ) Via1_HV
+ NEW Metal2 ( 182000 170800 ) Via2_VH
+ NEW Metal1 ( 205520 184240 ) Via1_VV
+ NEW Metal2 ( 205520 184240 ) Via2_VH
+ NEW Metal2 ( 195440 184240 ) Via2_VH
+ NEW Metal1 ( 212240 184240 ) Via1_VV
+ NEW Metal2 ( 212240 184240 ) Via2_VH
+ NEW Metal1 ( 217840 184240 ) Via1_HV
+ NEW Metal2 ( 217840 184240 ) Via2_VH
+ NEW Metal1 ( 212240 198800 ) Via1_VV
+ NEW Metal1 ( 207760 198800 ) Via1_VV
+ NEW Metal1 ( 220080 199920 ) Via1_VV
+ NEW Metal1 ( 218960 206640 ) Via1_VV
+ NEW Metal1 ( 218960 221200 ) Via1_VV
+ NEW Metal2 ( 218960 218960 ) Via2_VH
+ NEW Metal3 ( 218960 218960 ) Via3_HV
+ NEW Metal3 ( 218960 213360 ) Via3_HV
+ NEW Metal2 ( 220080 213360 ) Via2_VH
+ NEW Metal1 ( 231280 215600 ) Via1_HV
+ NEW Metal2 ( 231280 213360 ) Via2_VH
+ NEW Metal2 ( 182000 170800 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 205520 184240 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 212240 184240 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 217840 184240 ) RECT ( -280 -660 280 0 )
+ NEW Metal3 ( 218960 218960 ) RECT ( -660 -280 0 280 ) ;
+ - vga_clock.vga_0.vc\[0\] ( ANTENNA__0862__A2 I ) ( ANTENNA__1035__I I ) ( ANTENNA__1061__A1 I ) ( ANTENNA__1063__A1 I ) ( ANTENNA__1064__A2 I ) ( _1431_ Q ) ( _1064_ A2 )
+ ( _1063_ A1 ) ( _1061_ A1 ) ( _1035_ I ) ( _0862_ A2 ) + USE SIGNAL
+ + ROUTED Metal2 ( 278320 106960 ) ( * 111440 )
+ NEW Metal3 ( 278320 106960 ) ( 306320 * )
+ NEW Metal3 ( 272720 106960 ) ( 278320 * )
+ NEW Metal2 ( 266000 99120 ) ( 267120 * )
+ NEW Metal2 ( 267120 99120 ) ( * 106960 )
+ NEW Metal3 ( 267120 106960 ) ( 272720 * )
+ NEW Metal2 ( 261520 99120 ) ( 266000 * )
+ NEW Metal2 ( 305200 167440 ) ( * 168560 )
+ NEW Metal3 ( 279440 168560 ) ( 305200 * )
+ NEW Metal2 ( 279440 111440 ) ( * 168560 )
+ NEW Metal2 ( 278320 111440 ) ( 279440 * )
+ NEW Metal2 ( 282800 168560 ) ( * 174160 )
+ NEW Metal2 ( 288400 168560 ) ( * 174160 )
+ NEW Metal2 ( 292880 168560 ) ( * 183120 )
+ NEW Metal2 ( 281680 184240 ) ( 282800 * )
+ NEW Metal2 ( 281680 174160 ) ( * 184240 )
+ NEW Metal2 ( 281680 174160 ) ( 282800 * )
+ NEW Metal3 ( 306320 106960 ) ( 327600 * )
+ NEW Metal1 ( 306320 106960 ) Via1_VV
+ NEW Metal2 ( 306320 106960 ) Via2_VH
+ NEW Metal1 ( 278320 111440 ) Via1_VV
+ NEW Metal2 ( 278320 106960 ) Via2_VH
+ NEW Metal1 ( 272720 106960 ) Via1_VV
+ NEW Metal2 ( 272720 106960 ) Via2_VH
+ NEW Metal1 ( 266000 99120 ) Via1_VV
+ NEW Metal2 ( 267120 106960 ) Via2_VH
+ NEW Metal1 ( 261520 99120 ) Via1_VV
+ NEW Metal1 ( 305200 167440 ) Via1_HV
+ NEW Metal2 ( 305200 168560 ) Via2_VH
+ NEW Metal2 ( 279440 168560 ) Via2_VH
+ NEW Metal1 ( 282800 174160 ) Via1_VV
+ NEW Metal2 ( 282800 168560 ) Via2_VH
+ NEW Metal1 ( 288400 174160 ) Via1_VV
+ NEW Metal2 ( 288400 168560 ) Via2_VH
+ NEW Metal1 ( 292880 183120 ) Via1_VV
+ NEW Metal2 ( 292880 168560 ) Via2_VH
+ NEW Metal1 ( 282800 184240 ) Via1_HV
+ NEW Metal1 ( 327600 106960 ) Via1_VV
+ NEW Metal2 ( 327600 106960 ) Via2_VH
+ NEW Metal2 ( 306320 106960 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 272720 106960 ) RECT ( -280 -660 280 0 )
+ NEW Metal3 ( 282800 168560 ) RECT ( -1040 -280 0 280 )
+ NEW Metal3 ( 288400 168560 ) RECT ( -1040 -280 0 280 )
+ NEW Metal3 ( 292880 168560 ) RECT ( -1040 -280 0 280 )
+ NEW Metal2 ( 327600 106960 ) RECT ( -280 -660 280 0 ) ;
+ - vga_clock.vga_0.vc\[1\] ( _1432_ Q ) ( _1064_ A1 ) ( _1037_ I ) ( _0862_ A1 ) + USE SIGNAL
+ + ROUTED Metal2 ( 274960 100240 ) ( * 106960 )
+ NEW Metal3 ( 274960 100240 ) ( 308560 * )
+ NEW Metal2 ( 308560 100240 ) ( * 105840 )
+ NEW Metal2 ( 286160 89040 ) ( * 100240 )
+ NEW Metal2 ( 286160 82320 ) ( * 89040 )
+ NEW Metal1 ( 286160 82320 ) Via1_VV
+ NEW Metal1 ( 274960 106960 ) Via1_VV
+ NEW Metal2 ( 274960 100240 ) Via2_VH
+ NEW Metal2 ( 308560 100240 ) Via2_VH
+ NEW Metal1 ( 308560 105840 ) Via1_VV
+ NEW Metal1 ( 286160 89040 ) Via1_HV
+ NEW Metal2 ( 286160 100240 ) Via2_VH
+ NEW Metal3 ( 286160 100240 ) RECT ( -1040 -280 0 280 ) ;
+ - vga_clock.vga_0.vc\[2\] ( _1433_ Q ) ( _1068_ A1 ) ( _1067_ A1 ) ( _1056_ A1 ) ( _1039_ I ) ( _0863_ A2 ) + USE SIGNAL
+ + ROUTED Metal2 ( 313040 109200 ) ( * 113680 )
+ NEW Metal2 ( 263760 105840 ) ( * 109200 )
+ NEW Metal3 ( 263760 109200 ) ( 313040 * )
+ NEW Metal2 ( 250320 109200 ) ( * 111440 )
+ NEW Metal3 ( 250320 109200 ) ( 263760 * )
+ NEW Metal2 ( 252560 99120 ) ( * 109200 )
+ NEW Metal2 ( 320880 106960 ) ( * 109200 )
+ NEW Metal2 ( 320880 99120 ) ( * 106960 )
+ NEW Metal3 ( 313040 109200 ) ( 320880 * )
+ NEW Metal1 ( 313040 113680 ) Via1_VV
+ NEW Metal2 ( 313040 109200 ) Via2_VH
+ NEW Metal1 ( 263760 105840 ) Via1_HV
+ NEW Metal2 ( 263760 109200 ) Via2_VH
+ NEW Metal1 ( 250320 111440 ) Via1_VV
+ NEW Metal2 ( 250320 109200 ) Via2_VH
+ NEW Metal1 ( 252560 99120 ) Via1_HV
+ NEW Metal2 ( 252560 109200 ) Via2_VH
+ NEW Metal1 ( 320880 106960 ) Via1_VV
+ NEW Metal2 ( 320880 109200 ) Via2_VH
+ NEW Metal1 ( 320880 99120 ) Via1_VV
+ NEW Metal3 ( 252560 109200 ) RECT ( -1040 -280 0 280 ) ;
+ - vga_clock.vga_0.vc\[3\] ( _1434_ Q ) ( _1056_ B ) ( _1042_ A2 ) ( _1041_ A1 ) ( _0863_ A1 ) ( _0862_ B ) ( _0837_ I ) + USE SIGNAL
+ + ROUTED Metal2 ( 313040 104720 ) ( * 105840 )
+ NEW Metal2 ( 315280 104720 ) ( * 112560 )
+ NEW Metal3 ( 300720 112560 ) ( 315280 * )
+ NEW Metal2 ( 307440 121520 ) ( 308560 * )
+ NEW Metal2 ( 307440 112560 ) ( * 121520 )
+ NEW Metal3 ( 313040 104720 ) ( 319200 * )
+ NEW Metal3 ( 323120 105840 ) ( 336560 * )
+ NEW Metal3 ( 319200 104720 ) ( * 105840 )
+ NEW Metal3 ( 319200 105840 ) ( 323120 * )
+ NEW Metal2 ( 326480 89040 ) ( * 105840 )
+ NEW Metal1 ( 313040 105840 ) Via1_VV
+ NEW Metal2 ( 313040 104720 ) Via2_VH
+ NEW Metal1 ( 315280 112560 ) Via1_VV
+ NEW Metal2 ( 315280 104720 ) Via2_VH
+ NEW Metal1 ( 300720 112560 ) Via1_VV
+ NEW Metal2 ( 300720 112560 ) Via2_VH
+ NEW Metal2 ( 315280 112560 ) Via2_VH
+ NEW Metal1 ( 308560 121520 ) Via1_VV
+ NEW Metal2 ( 307440 112560 ) Via2_VH
+ NEW Metal1 ( 323120 105840 ) Via1_VV
+ NEW Metal2 ( 323120 105840 ) Via2_VH
+ NEW Metal1 ( 336560 105840 ) Via1_HV
+ NEW Metal2 ( 336560 105840 ) Via2_VH
+ NEW Metal1 ( 326480 89040 ) Via1_HV
+ NEW Metal2 ( 326480 105840 ) Via2_VH
+ NEW Metal3 ( 315280 104720 ) RECT ( -1040 -280 0 280 )
+ NEW Metal2 ( 300720 112560 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 315280 112560 ) RECT ( -280 -1040 280 0 )
+ NEW Metal3 ( 307440 112560 ) RECT ( -1040 -280 0 280 )
+ NEW Metal2 ( 323120 105840 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 336560 105840 ) RECT ( -280 -660 280 0 )
+ NEW Metal3 ( 326480 105840 ) RECT ( -1040 -280 0 280 ) ;
+ - vga_clock.vga_0.vc\[4\] ( _1435_ Q ) ( _1073_ A1 ) ( _1072_ A1 ) ( _1042_ A1 ) ( _0861_ A2 ) ( _0836_ I ) + USE SIGNAL
+ + ROUTED Metal3 ( 299600 122640 ) ( 309680 * )
+ NEW Metal2 ( 297360 122640 ) ( * 127120 )
+ NEW Metal3 ( 297360 122640 ) ( 299600 * )
+ NEW Metal2 ( 305200 134960 ) ( 306320 * )
+ NEW Metal2 ( 306320 122640 ) ( * 134960 )
+ NEW Metal2 ( 288400 127120 ) ( * 136080 )
+ NEW Metal3 ( 288400 127120 ) ( 297360 * )
+ NEW Metal2 ( 283920 127120 ) ( * 130480 )
+ NEW Metal3 ( 283920 127120 ) ( 288400 * )
+ NEW Metal1 ( 299600 122640 ) Via1_VV
+ NEW Metal2 ( 299600 122640 ) Via2_VH
+ NEW Metal1 ( 309680 122640 ) Via1_VV
+ NEW Metal2 ( 309680 122640 ) Via2_VH
+ NEW Metal1 ( 297360 127120 ) Via1_VV
+ NEW Metal2 ( 297360 122640 ) Via2_VH
+ NEW Metal1 ( 305200 134960 ) Via1_VV
+ NEW Metal2 ( 306320 122640 ) Via2_VH
+ NEW Metal1 ( 288400 136080 ) Via1_VV
+ NEW Metal2 ( 288400 127120 ) Via2_VH
+ NEW Metal2 ( 297360 127120 ) Via2_VH
+ NEW Metal1 ( 283920 130480 ) Via1_HV
+ NEW Metal2 ( 283920 127120 ) Via2_VH
+ NEW Metal2 ( 299600 122640 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 309680 122640 ) RECT ( -280 -660 280 0 )
+ NEW Metal3 ( 306320 122640 ) RECT ( -1040 -280 0 280 )
+ NEW Metal2 ( 297360 127120 ) RECT ( -280 -1040 280 0 ) ;
+ - vga_clock.vga_0.vc\[5\] ( ANTENNA__0839__A1 I ) ( ANTENNA__0860__A3 I ) ( ANTENNA__1045__A1 I ) ( ANTENNA__1075__A1 I ) ( ANTENNA__1076__A1 I ) ( ANTENNA__1078__A1 I ) ( ANTENNA__1083__A2 I )
+ ( _1436_ Q ) ( _1083_ A2 ) ( _1078_ A1 ) ( _1076_ A1 ) ( _1075_ A1 ) ( _1045_ A1 ) ( _0860_ A3 ) ( _0839_ A1 ) + USE SIGNAL
+ + ROUTED Metal2 ( 310800 130480 ) ( * 137200 )
+ NEW Metal2 ( 299600 137200 ) ( * 151760 )
+ NEW Metal3 ( 299600 137200 ) ( 310800 * )
+ NEW Metal2 ( 290640 150640 ) ( * 151760 )
+ NEW Metal3 ( 290640 150640 ) ( 299600 * )
+ NEW Metal3 ( 277200 137200 ) ( 299600 * )
+ NEW Metal3 ( 261520 137200 ) ( 277200 * )
+ NEW Metal2 ( 244720 137200 ) ( * 138320 )
+ NEW Metal3 ( 244720 137200 ) ( 261520 * )
+ NEW Metal2 ( 248080 123760 ) ( * 137200 )
+ NEW Metal3 ( 241360 123760 ) ( 248080 * )
+ NEW Metal2 ( 234640 123760 ) ( * 129360 )
+ NEW Metal3 ( 234640 123760 ) ( 241360 * )
+ NEW Metal2 ( 231280 120400 ) ( * 123760 )
+ NEW Metal3 ( 231280 123760 ) ( 234640 * )
+ NEW Metal2 ( 241360 114800 ) ( * 123760 )
+ NEW Metal2 ( 230160 108080 ) ( 231280 * )
+ NEW Metal2 ( 231280 108080 ) ( * 120400 )
+ NEW Metal3 ( 310800 137200 ) ( 319200 * )
+ NEW Metal2 ( 327600 130480 ) ( * 138320 )
+ NEW Metal2 ( 327600 130480 ) ( 328720 * )
+ NEW Metal3 ( 319760 136080 ) ( 327600 * )
+ NEW Metal3 ( 319200 136080 ) ( * 137200 )
+ NEW Metal3 ( 319200 136080 ) ( 319760 * )
+ NEW Metal1 ( 310800 130480 ) Via1_VV
+ NEW Metal2 ( 310800 137200 ) Via2_VH
+ NEW Metal1 ( 299600 151760 ) Via1_VV
+ NEW Metal2 ( 299600 137200 ) Via2_VH
+ NEW Metal1 ( 290640 151760 ) Via1_VV
+ NEW Metal2 ( 290640 150640 ) Via2_VH
+ NEW Metal2 ( 299600 150640 ) Via2_VH
+ NEW Metal1 ( 277200 137200 ) Via1_VV
+ NEW Metal2 ( 277200 137200 ) Via2_VH
+ NEW Metal1 ( 261520 137200 ) Via1_HV
+ NEW Metal2 ( 261520 137200 ) Via2_VH
+ NEW Metal1 ( 244720 138320 ) Via1_VV
+ NEW Metal2 ( 244720 137200 ) Via2_VH
+ NEW Metal1 ( 248080 123760 ) Via1_VV
+ NEW Metal2 ( 248080 137200 ) Via2_VH
+ NEW Metal1 ( 241360 123760 ) Via1_VV
+ NEW Metal2 ( 241360 123760 ) Via2_VH
+ NEW Metal2 ( 248080 123760 ) Via2_VH
+ NEW Metal1 ( 234640 129360 ) Via1_HV
+ NEW Metal2 ( 234640 123760 ) Via2_VH
+ NEW Metal1 ( 231280 120400 ) Via1_HV
+ NEW Metal2 ( 231280 123760 ) Via2_VH
+ NEW Metal1 ( 241360 114800 ) Via1_VV
+ NEW Metal1 ( 230160 108080 ) Via1_VV
+ NEW Metal1 ( 327600 138320 ) Via1_VV
+ NEW Metal1 ( 328720 130480 ) Via1_VV
+ NEW Metal1 ( 319760 136080 ) Via1_VV
+ NEW Metal2 ( 319760 136080 ) Via2_VH
+ NEW Metal2 ( 327600 136080 ) Via2_VH
+ NEW Metal2 ( 299600 150640 ) RECT ( -280 -1040 280 0 )
+ NEW Metal2 ( 277200 137200 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 261520 137200 ) RECT ( -280 -660 280 0 )
+ NEW Metal3 ( 248080 137200 ) RECT ( -1040 -280 0 280 )
+ NEW Metal2 ( 241360 123760 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 248080 123760 ) RECT ( -280 -1040 280 0 )
+ NEW Metal2 ( 319760 136080 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 327600 136080 ) RECT ( -280 -1040 280 0 ) ;
+ - vga_clock.vga_0.vc\[6\] ( ANTENNA__0840__A1 I ) ( ANTENNA__0861__A1 I ) ( ANTENNA__1047__A1 I ) ( ANTENNA__1079__A1 I ) ( ANTENNA__1080__A1 I ) ( ANTENNA__1083__A1 I ) ( _1437_ Q )
+ ( _1083_ A1 ) ( _1080_ A1 ) ( _1079_ A1 ) ( _1047_ A1 ) ( _0861_ A1 ) ( _0840_ A1 ) + USE SIGNAL
+ + ROUTED Metal2 ( 210000 136080 ) ( * 142800 )
+ NEW Metal2 ( 229040 136080 ) ( * 137200 )
+ NEW Metal3 ( 210000 136080 ) ( 229040 * )
+ NEW Metal2 ( 230160 137200 ) ( * 142800 )
+ NEW Metal2 ( 229040 137200 ) ( 230160 * )
+ NEW Metal2 ( 224560 130480 ) ( * 136080 )
+ NEW Metal2 ( 250320 130480 ) ( * 134960 )
+ NEW Metal3 ( 229040 134960 ) ( 250320 * )
+ NEW Metal3 ( 229040 134960 ) ( * 136080 )
+ NEW Metal2 ( 263760 134960 ) ( * 138320 )
+ NEW Metal3 ( 250320 134960 ) ( 263760 * )
+ NEW Metal3 ( 294000 136080 ) ( 307440 * )
+ NEW Metal3 ( 294000 134960 ) ( * 136080 )
+ NEW Metal3 ( 263760 134960 ) ( 294000 * )
+ NEW Metal2 ( 304080 130480 ) ( 305200 * )
+ NEW Metal2 ( 304080 130480 ) ( * 133840 )
+ NEW Metal2 ( 302960 133840 ) ( 304080 * )
+ NEW Metal2 ( 302960 133840 ) ( * 136080 )
+ NEW Metal2 ( 305200 142800 ) ( 306320 * )
+ NEW Metal2 ( 306320 136080 ) ( * 142800 )
+ NEW Metal2 ( 306320 136080 ) ( 307440 * )
+ NEW Metal2 ( 311920 136080 ) ( * 142800 )
+ NEW Metal3 ( 307440 136080 ) ( 311920 * )
+ NEW Metal3 ( 311920 143920 ) ( 318640 * )
+ NEW Metal2 ( 311920 142800 ) ( * 143920 )
+ NEW Metal2 ( 316400 143920 ) ( * 151760 )
+ NEW Metal3 ( 192080 136080 ) ( 210000 * )
+ NEW Metal1 ( 210000 142800 ) Via1_VV
+ NEW Metal2 ( 210000 136080 ) Via2_VH
+ NEW Metal1 ( 229040 137200 ) Via1_HV
+ NEW Metal2 ( 229040 136080 ) Via2_VH
+ NEW Metal1 ( 230160 142800 ) Via1_VV
+ NEW Metal1 ( 224560 130480 ) Via1_VV
+ NEW Metal2 ( 224560 136080 ) Via2_VH
+ NEW Metal1 ( 250320 130480 ) Via1_VV
+ NEW Metal2 ( 250320 134960 ) Via2_VH
+ NEW Metal1 ( 263760 138320 ) Via1_VV
+ NEW Metal2 ( 263760 134960 ) Via2_VH
+ NEW Metal1 ( 307440 136080 ) Via1_VV
+ NEW Metal2 ( 307440 136080 ) Via2_VH
+ NEW Metal1 ( 305200 130480 ) Via1_VV
+ NEW Metal2 ( 302960 136080 ) Via2_VH
+ NEW Metal1 ( 305200 142800 ) Via1_VV
+ NEW Metal1 ( 311920 142800 ) Via1_VV
+ NEW Metal2 ( 311920 136080 ) Via2_VH
+ NEW Metal1 ( 318640 143920 ) Via1_VV
+ NEW Metal2 ( 318640 143920 ) Via2_VH
+ NEW Metal2 ( 311920 143920 ) Via2_VH
+ NEW Metal1 ( 316400 151760 ) Via1_VV
+ NEW Metal2 ( 316400 143920 ) Via2_VH
+ NEW Metal1 ( 192080 136080 ) Via1_HV
+ NEW Metal2 ( 192080 136080 ) Via2_VH
+ NEW Metal3 ( 224560 136080 ) RECT ( -1040 -280 0 280 )
+ NEW Metal2 ( 307440 136080 ) RECT ( -280 -660 280 0 )
+ NEW Metal3 ( 302960 136080 ) RECT ( -1040 -280 0 280 )
+ NEW Metal2 ( 318640 143920 ) RECT ( -280 -660 280 0 )
+ NEW Metal3 ( 316400 143920 ) RECT ( -1040 -280 0 280 )
+ NEW Metal2 ( 192080 136080 ) RECT ( -280 -660 280 0 ) ;
+ - vga_clock.vga_0.vc\[7\] ( ANTENNA__0841__A1 I ) ( ANTENNA__0860__A2 I ) ( ANTENNA__1049__A1 I ) ( ANTENNA__1082__I I ) ( ANTENNA__1085__A1 I ) ( _1438_ Q ) ( _1085_ A1 )
+ ( _1082_ I ) ( _1049_ A1 ) ( _0860_ A2 ) ( _0841_ A1 ) + USE SIGNAL
+ + ROUTED Metal2 ( 318640 158480 ) ( * 159600 )
+ NEW Metal3 ( 313040 158480 ) ( 318640 * )
+ NEW Metal2 ( 297360 152880 ) ( * 157360 )
+ NEW Metal3 ( 297360 157360 ) ( * 158480 )
+ NEW Metal3 ( 297360 158480 ) ( 313040 * )
+ NEW Metal2 ( 288400 146160 ) ( * 157360 )
+ NEW Metal3 ( 288400 157360 ) ( 297360 * )
+ NEW Metal2 ( 274960 154000 ) ( * 157360 )
+ NEW Metal3 ( 274960 157360 ) ( 288400 * )
+ NEW Metal2 ( 271600 146160 ) ( * 150640 )
+ NEW Metal2 ( 271600 150640 ) ( 274960 * )
+ NEW Metal2 ( 274960 150640 ) ( * 154000 )
+ NEW Metal2 ( 273840 139440 ) ( * 150640 )
+ NEW Metal2 ( 271600 150640 ) ( * 151760 )
+ NEW Metal3 ( 330960 158480 ) ( 341040 * )
+ NEW Metal3 ( 318640 158480 ) ( 330960 * )
+ NEW Metal3 ( 254800 161840 ) ( 262640 * )
+ NEW Metal2 ( 262640 145040 ) ( * 161840 )
+ NEW Metal3 ( 262640 151760 ) ( 271600 * )
+ NEW Metal1 ( 318640 159600 ) Via1_VV
+ NEW Metal2 ( 318640 158480 ) Via2_VH
+ NEW Metal1 ( 313040 158480 ) Via1_VV
+ NEW Metal2 ( 313040 158480 ) Via2_VH
+ NEW Metal1 ( 297360 152880 ) Via1_VV
+ NEW Metal2 ( 297360 157360 ) Via2_VH
+ NEW Metal1 ( 288400 146160 ) Via1_VV
+ NEW Metal2 ( 288400 157360 ) Via2_VH
+ NEW Metal1 ( 274960 154000 ) Via1_VV
+ NEW Metal2 ( 274960 157360 ) Via2_VH
+ NEW Metal1 ( 271600 146160 ) Via1_VV
+ NEW Metal1 ( 273840 139440 ) Via1_VV
+ NEW Metal1 ( 262640 145040 ) Via1_VV
+ NEW Metal2 ( 271600 151760 ) Via2_VH
+ NEW Metal1 ( 330960 158480 ) Via1_VV
+ NEW Metal2 ( 330960 158480 ) Via2_VH
+ NEW Metal1 ( 341040 158480 ) Via1_VV
+ NEW Metal2 ( 341040 158480 ) Via2_VH
+ NEW Metal2 ( 262640 161840 ) Via2_VH
+ NEW Metal1 ( 254800 161840 ) Via1_HV
+ NEW Metal2 ( 254800 161840 ) Via2_VH
+ NEW Metal2 ( 262640 151760 ) Via2_VH
+ NEW Metal2 ( 313040 158480 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 330960 158480 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 341040 158480 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 254800 161840 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 262640 151760 ) RECT ( -280 0 280 1040 ) ;
+ - vga_clock.vga_0.vc\[8\] ( ANTENNA__0842__A1 I ) ( ANTENNA__0860__A1 I ) ( ANTENNA__1051__A1 I ) ( ANTENNA__1088__A1 I ) ( ANTENNA__1089__A1 I ) ( ANTENNA__1091__A1 I ) ( _1439_ Q )
+ ( _1091_ A1 ) ( _1089_ A1 ) ( _1088_ A1 ) ( _1051_ A1 ) ( _0860_ A1 ) ( _0842_ A1 ) + USE SIGNAL
+ + ROUTED Metal2 ( 317520 174160 ) ( * 183120 )
+ NEW Metal3 ( 311920 183120 ) ( 317520 * )
+ NEW Metal2 ( 295120 152880 ) ( * 174160 )
+ NEW Metal3 ( 295120 174160 ) ( 317520 * )
+ NEW Metal2 ( 285040 146160 ) ( * 152880 )
+ NEW Metal3 ( 285040 152880 ) ( 295120 * )
+ NEW Metal2 ( 271600 175280 ) ( * 183120 )
+ NEW Metal3 ( 271600 175280 ) ( 295120 * )
+ NEW Metal3 ( 295120 174160 ) ( * 175280 )
+ NEW Metal2 ( 272720 183120 ) ( * 189840 )
+ NEW Metal2 ( 271600 183120 ) ( 272720 * )
+ NEW Metal3 ( 320880 174160 ) ( 326480 * )
+ NEW Metal3 ( 317520 174160 ) ( 320880 * )
+ NEW Metal3 ( 255920 175280 ) ( 264880 * )
+ NEW Metal2 ( 263760 184240 ) ( 264880 * )
+ NEW Metal2 ( 264880 175280 ) ( * 184240 )
+ NEW Metal2 ( 262640 189840 ) ( 263760 * )
+ NEW Metal2 ( 263760 184240 ) ( * 189840 )
+ NEW Metal2 ( 258160 189840 ) ( * 193200 )
+ NEW Metal2 ( 258160 189840 ) ( 262640 * )
+ NEW Metal3 ( 264880 175280 ) ( 271600 * )
+ NEW Metal1 ( 317520 183120 ) Via1_VV
+ NEW Metal2 ( 317520 174160 ) Via2_VH
+ NEW Metal1 ( 311920 183120 ) Via1_VV
+ NEW Metal2 ( 311920 183120 ) Via2_VH
+ NEW Metal2 ( 317520 183120 ) Via2_VH
+ NEW Metal1 ( 295120 152880 ) Via1_VV
+ NEW Metal2 ( 295120 174160 ) Via2_VH
+ NEW Metal1 ( 285040 146160 ) Via1_VV
+ NEW Metal2 ( 285040 152880 ) Via2_VH
+ NEW Metal2 ( 295120 152880 ) Via2_VH
+ NEW Metal1 ( 271600 183120 ) Via1_VV
+ NEW Metal2 ( 271600 175280 ) Via2_VH
+ NEW Metal1 ( 272720 189840 ) Via1_VV
+ NEW Metal1 ( 320880 174160 ) Via1_VV
+ NEW Metal2 ( 320880 174160 ) Via2_VH
+ NEW Metal1 ( 326480 174160 ) Via1_VV
+ NEW Metal2 ( 326480 174160 ) Via2_VH
+ NEW Metal1 ( 264880 175280 ) Via1_VV
+ NEW Metal2 ( 264880 175280 ) Via2_VH
+ NEW Metal1 ( 255920 175280 ) Via1_VV
+ NEW Metal2 ( 255920 175280 ) Via2_VH
+ NEW Metal1 ( 263760 184240 ) Via1_HV
+ NEW Metal1 ( 262640 189840 ) Via1_VV
+ NEW Metal1 ( 258160 193200 ) Via1_HV
+ NEW Metal2 ( 311920 183120 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 317520 183120 ) RECT ( -280 -1040 280 0 )
+ NEW Metal2 ( 295120 152880 ) RECT ( -280 -1040 280 0 )
+ NEW Metal2 ( 320880 174160 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 326480 174160 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 264880 175280 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 255920 175280 ) RECT ( -280 -660 280 0 ) ;
+ - vga_clock.vga_0.vc\[9\] ( ANTENNA__0843__A1 I ) ( ANTENNA__0863__C I ) ( ANTENNA__1053__A1 I ) ( ANTENNA__1058__A1 I ) ( ANTENNA__1092__I I ) ( _1440_ Q ) ( _1092_ I )
+ ( _1058_ A1 ) ( _1053_ A1 ) ( _0863_ C ) ( _0843_ A1 ) + USE SIGNAL
+ + ROUTED Metal2 ( 318640 201600 ) ( * 205520 )
+ NEW Metal2 ( 310800 115920 ) ( * 121520 )
+ NEW Metal2 ( 307440 140560 ) ( * 151760 )
+ NEW Metal2 ( 307440 140560 ) ( 309680 * )
+ NEW Metal2 ( 309680 124880 ) ( * 140560 )
+ NEW Metal2 ( 309680 124880 ) ( 310800 * )
+ NEW Metal2 ( 310800 121520 ) ( * 124880 )
+ NEW Metal3 ( 297360 143920 ) ( 307440 * )
+ NEW Metal3 ( 301840 189840 ) ( 307440 * )
+ NEW Metal2 ( 307440 151760 ) ( * 189840 )
+ NEW Metal3 ( 307440 189840 ) ( 313040 * )
+ NEW Metal2 ( 297360 189840 ) ( * 190960 )
+ NEW Metal3 ( 297360 189840 ) ( 301840 * )
+ NEW Metal2 ( 315280 189840 ) ( * 198800 )
+ NEW Metal2 ( 315280 201600 ) ( 318640 * )
+ NEW Metal2 ( 315280 198800 ) ( * 201600 )
+ NEW Metal2 ( 322000 189840 ) ( * 192080 )
+ NEW Metal2 ( 323120 192080 ) ( * 199920 )
+ NEW Metal2 ( 322000 192080 ) ( 323120 * )
+ NEW Metal3 ( 310800 121520 ) ( 323120 * )
+ NEW Metal3 ( 313040 189840 ) ( 322000 * )
+ NEW Metal1 ( 318640 205520 ) Via1_VV
+ NEW Metal1 ( 310800 115920 ) Via1_VV
+ NEW Metal2 ( 310800 121520 ) Via2_VH
+ NEW Metal1 ( 307440 151760 ) Via1_VV
+ NEW Metal1 ( 297360 143920 ) Via1_VV
+ NEW Metal2 ( 297360 143920 ) Via2_VH
+ NEW Metal2 ( 307440 143920 ) Via2_VH
+ NEW Metal1 ( 301840 189840 ) Via1_VV
+ NEW Metal2 ( 301840 189840 ) Via2_VH
+ NEW Metal2 ( 307440 189840 ) Via2_VH
+ NEW Metal1 ( 313040 189840 ) Via1_VV
+ NEW Metal2 ( 313040 189840 ) Via2_VH
+ NEW Metal1 ( 297360 190960 ) Via1_VV
+ NEW Metal2 ( 297360 189840 ) Via2_VH
+ NEW Metal1 ( 315280 198800 ) Via1_HV
+ NEW Metal2 ( 315280 189840 ) Via2_VH
+ NEW Metal1 ( 322000 192080 ) Via1_HV
+ NEW Metal2 ( 322000 189840 ) Via2_VH
+ NEW Metal1 ( 323120 199920 ) Via1_VV
+ NEW Metal1 ( 323120 121520 ) Via1_VV
+ NEW Metal2 ( 323120 121520 ) Via2_VH
+ NEW Metal2 ( 297360 143920 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 307440 143920 ) RECT ( -280 -1040 280 0 )
+ NEW Metal2 ( 301840 189840 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 313040 189840 ) RECT ( -280 -660 280 0 )
+ NEW Metal3 ( 315280 189840 ) RECT ( -1040 -280 0 280 )
+ NEW Metal2 ( 323120 121520 ) RECT ( -280 -660 280 0 ) ;
+ - vga_clock.vga_0.x_px\[0\] ( _1411_ Q ) ( _1101_ A3 ) + USE SIGNAL
+ + ROUTED Metal2 ( 357840 231280 ) ( * 240240 )
+ NEW Metal1 ( 357840 231280 ) Via1_VV
+ NEW Metal1 ( 357840 240240 ) Via1_HV ;
+ - vga_clock.vga_0.x_px\[1\] ( _1412_ Q ) ( _1101_ A2 ) + USE SIGNAL
+ + ROUTED Metal2 ( 358960 224560 ) ( * 229040 )
+ NEW Metal2 ( 358960 229040 ) ( 360080 * )
+ NEW Metal1 ( 358960 224560 ) Via1_HV
+ NEW Metal1 ( 360080 229040 ) Via1_VV ;
+ - vga_clock.vga_0.x_px\[2\] ( _1413_ Q ) ( _1100_ A1 ) + USE SIGNAL
+ + ROUTED Metal3 ( 350000 271600 ) ( 358960 * )
+ NEW Metal1 ( 350000 271600 ) Via1_HV
+ NEW Metal2 ( 350000 271600 ) Via2_VH
+ NEW Metal1 ( 358960 271600 ) Via1_VV
+ NEW Metal2 ( 358960 271600 ) Via2_VH
+ NEW Metal2 ( 350000 271600 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 358960 271600 ) RECT ( -280 -660 280 0 ) ;
+ - vga_clock.vga_0.x_px\[3\] ( _1414_ Q ) ( _1101_ A4 ) + USE SIGNAL
+ + ROUTED Metal3 ( 328720 230160 ) ( 356720 * )
+ NEW Metal1 ( 328720 230160 ) Via1_HV
+ NEW Metal2 ( 328720 230160 ) Via2_VH
+ NEW Metal1 ( 356720 230160 ) Via1_VV
+ NEW Metal2 ( 356720 230160 ) Via2_VH
+ NEW Metal2 ( 328720 230160 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 356720 230160 ) RECT ( -280 -660 280 0 ) ;
+ - vga_clock.vga_0.x_px\[6\] ( _1417_ Q ) ( _0772_ A1 ) ( _0685_ A1 ) ( _0677_ I ) ( _0672_ I ) + USE SIGNAL
+ + ROUTED Metal2 ( 298480 286160 ) ( * 294000 )
+ NEW Metal2 ( 290640 301840 ) ( * 308560 )
+ NEW Metal3 ( 290640 301840 ) ( 298480 * )
+ NEW Metal2 ( 298480 294000 ) ( * 301840 )
+ NEW Metal3 ( 279440 301840 ) ( 290640 * )
+ NEW Metal2 ( 268240 300720 ) ( * 302960 )
+ NEW Metal3 ( 268240 300720 ) ( 279440 * )
+ NEW Metal3 ( 279440 300720 ) ( * 301840 )
+ NEW Metal1 ( 298480 294000 ) Via1_VV
+ NEW Metal1 ( 298480 286160 ) Via1_HV
+ NEW Metal1 ( 290640 308560 ) Via1_VV
+ NEW Metal2 ( 290640 301840 ) Via2_VH
+ NEW Metal2 ( 298480 301840 ) Via2_VH
+ NEW Metal1 ( 279440 301840 ) Via1_VV
+ NEW Metal2 ( 279440 301840 ) Via2_VH
+ NEW Metal1 ( 268240 302960 ) Via1_HV
+ NEW Metal2 ( 268240 300720 ) Via2_VH
+ NEW Metal2 ( 279440 301840 ) RECT ( -280 -660 280 0 ) ;
+ - vga_clock.vga_0.x_px\[7\] ( _1418_ Q ) ( _0778_ I ) ( _0772_ A2 ) ( _0685_ A2 ) ( _0673_ A2 ) + USE SIGNAL
+ + ROUTED Metal3 ( 251440 308560 ) ( 274960 * )
+ NEW Metal2 ( 251440 287280 ) ( * 308560 )
+ NEW Metal2 ( 297360 287280 ) ( * 308560 )
+ NEW Metal3 ( 274960 308560 ) ( 297360 * )
+ NEW Metal2 ( 297360 308560 ) ( 298480 * )
+ NEW Metal3 ( 297360 294000 ) ( 301840 * )
+ NEW Metal1 ( 274960 308560 ) Via1_HV
+ NEW Metal2 ( 274960 308560 ) Via2_VH
+ NEW Metal2 ( 251440 308560 ) Via2_VH
+ NEW Metal1 ( 251440 287280 ) Via1_HV
+ NEW Metal1 ( 297360 287280 ) Via1_HV
+ NEW Metal2 ( 297360 308560 ) Via2_VH
+ NEW Metal1 ( 298480 308560 ) Via1_VV
+ NEW Metal1 ( 301840 294000 ) Via1_VV
+ NEW Metal2 ( 301840 294000 ) Via2_VH
+ NEW Metal2 ( 297360 294000 ) Via2_VH
+ NEW Metal2 ( 274960 308560 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 301840 294000 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 297360 294000 ) RECT ( -280 -1040 280 0 ) ;
+ - vga_clock.vga_0.x_px\[8\] ( ANTENNA__0686__A1 I ) ( ANTENNA__0772__A3 I ) ( ANTENNA__0773__A2 I ) ( ANTENNA__0782__A2 I ) ( ANTENNA__0788__A2 I ) ( ANTENNA__0818__A1 I ) ( _1419_ Q )
+ ( _0818_ A1 ) ( _0788_ A2 ) ( _0782_ A2 ) ( _0773_ A2 ) ( _0772_ A3 ) ( _0686_ A1 ) + USE SIGNAL
+ + ROUTED Metal2 ( 290640 270480 ) ( * 292880 )
+ NEW Metal3 ( 290640 268240 ) ( * 270480 )
+ NEW Metal3 ( 290640 291760 ) ( 304080 * )
+ NEW Metal2 ( 304080 280560 ) ( 306320 * )
+ NEW Metal2 ( 304080 280560 ) ( * 291760 )
+ NEW Metal2 ( 309680 288400 ) ( * 291760 )
+ NEW Metal3 ( 304080 291760 ) ( 309680 * )
+ NEW Metal2 ( 268240 373520 ) ( * 378000 )
+ NEW Metal2 ( 263760 378000 ) ( 268240 * )
+ NEW Metal2 ( 268240 334320 ) ( * 351120 )
+ NEW Metal2 ( 267120 351120 ) ( 268240 * )
+ NEW Metal2 ( 267120 351120 ) ( * 364560 )
+ NEW Metal2 ( 267120 364560 ) ( 268240 * )
+ NEW Metal2 ( 268240 364560 ) ( * 373520 )
+ NEW Metal2 ( 281680 333200 ) ( * 335440 )
+ NEW Metal3 ( 268240 335440 ) ( 281680 * )
+ NEW Metal2 ( 283920 335440 ) ( * 346640 )
+ NEW Metal3 ( 281680 335440 ) ( 283920 * )
+ NEW Metal3 ( 283920 341040 ) ( 291760 * )
+ NEW Metal2 ( 291760 355600 ) ( 292880 * )
+ NEW Metal2 ( 291760 341040 ) ( * 355600 )
+ NEW Metal3 ( 291760 348880 ) ( 296240 * )
+ NEW Metal2 ( 267120 319200 ) ( 268240 * )
+ NEW Metal2 ( 268240 319200 ) ( * 334320 )
+ NEW Metal3 ( 248080 264880 ) ( 267120 * )
+ NEW Metal2 ( 267120 264880 ) ( * 319200 )
+ NEW Metal3 ( 267120 268240 ) ( 290640 * )
+ NEW Metal1 ( 290640 292880 ) Via1_VV
+ NEW Metal2 ( 290640 270480 ) Via2_VH
+ NEW Metal1 ( 304080 291760 ) Via1_VV
+ NEW Metal2 ( 304080 291760 ) Via2_VH
+ NEW Metal2 ( 290640 291760 ) Via2_VH
+ NEW Metal1 ( 306320 280560 ) Via1_VV
+ NEW Metal1 ( 309680 288400 ) Via1_VV
+ NEW Metal2 ( 309680 291760 ) Via2_VH
+ NEW Metal1 ( 268240 373520 ) Via1_VV
+ NEW Metal1 ( 263760 378000 ) Via1_VV
+ NEW Metal1 ( 268240 334320 ) Via1_VV
+ NEW Metal1 ( 281680 333200 ) Via1_HV
+ NEW Metal2 ( 281680 335440 ) Via2_VH
+ NEW Metal2 ( 268240 335440 ) Via2_VH
+ NEW Metal1 ( 283920 346640 ) Via1_VV
+ NEW Metal2 ( 283920 335440 ) Via2_VH
+ NEW Metal1 ( 291760 341040 ) Via1_HV
+ NEW Metal2 ( 291760 341040 ) Via2_VH
+ NEW Metal2 ( 283920 341040 ) Via2_VH
+ NEW Metal1 ( 292880 355600 ) Via1_VV
+ NEW Metal1 ( 296240 348880 ) Via1_HV
+ NEW Metal2 ( 296240 348880 ) Via2_VH
+ NEW Metal2 ( 291760 348880 ) Via2_VH
+ NEW Metal2 ( 267120 264880 ) Via2_VH
+ NEW Metal1 ( 248080 264880 ) Via1_HV
+ NEW Metal2 ( 248080 264880 ) Via2_VH
+ NEW Metal2 ( 267120 268240 ) Via2_VH
+ NEW Metal2 ( 304080 291760 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 290640 291760 ) RECT ( -280 -1040 280 0 )
+ NEW Metal2 ( 268240 335440 ) RECT ( -280 -1040 280 0 )
+ NEW Metal2 ( 291760 341040 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 283920 341040 ) RECT ( -280 -1040 280 0 )
+ NEW Metal2 ( 296240 348880 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 291760 348880 ) RECT ( -280 -1040 280 0 )
+ NEW Metal2 ( 248080 264880 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 267120 268240 ) RECT ( -280 -1040 280 0 ) ;
+ - vga_clock.vga_0.x_px\[9\] ( _1420_ Q ) ( _0788_ A1 ) ( _0777_ A1 ) ( _0773_ A1 ) ( _0772_ B ) + USE SIGNAL
+ + ROUTED Metal2 ( 310800 285040 ) ( 311920 * )
+ NEW Metal3 ( 296240 295120 ) ( 310800 * )
+ NEW Metal2 ( 287280 287280 ) ( * 295120 )
+ NEW Metal3 ( 287280 295120 ) ( 296240 * )
+ NEW Metal2 ( 309680 339920 ) ( 310800 * )
+ NEW Metal2 ( 310800 333200 ) ( * 339920 )
+ NEW Metal2 ( 310800 285040 ) ( * 333200 )
+ NEW Metal1 ( 311920 285040 ) Via1_VV
+ NEW Metal1 ( 296240 295120 ) Via1_VV
+ NEW Metal2 ( 296240 295120 ) Via2_VH
+ NEW Metal2 ( 310800 295120 ) Via2_VH
+ NEW Metal1 ( 287280 287280 ) Via1_HV
+ NEW Metal2 ( 287280 295120 ) Via2_VH
+ NEW Metal1 ( 310800 333200 ) Via1_HV
+ NEW Metal1 ( 309680 339920 ) Via1_VV
+ NEW Metal2 ( 296240 295120 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 310800 295120 ) RECT ( -280 -1040 280 0 ) ;
+ - vga_clock.vga_0.y_px\[0\] ( _1421_ Q ) ( _1103_ A2 ) + USE SIGNAL
+ + ROUTED Metal3 ( 365680 89040 ) ( 371280 * )
+ NEW Metal1 ( 365680 89040 ) Via1_HV
+ NEW Metal2 ( 365680 89040 ) Via2_VH
+ NEW Metal1 ( 371280 89040 ) Via1_VV
+ NEW Metal2 ( 371280 89040 ) Via2_VH
+ NEW Metal2 ( 365680 89040 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 371280 89040 ) RECT ( -280 -660 280 0 ) ;
+ - vga_clock.vga_0.y_px\[1\] ( _1422_ Q ) ( _1103_ A1 ) + USE SIGNAL
+ + ROUTED Metal3 ( 367920 90160 ) ( 374640 * )
+ NEW Metal2 ( 367920 83440 ) ( * 90160 )
+ NEW Metal1 ( 367920 83440 ) Via1_HV
+ NEW Metal2 ( 367920 90160 ) Via2_VH
+ NEW Metal1 ( 374640 90160 ) Via1_HV
+ NEW Metal2 ( 374640 90160 ) Via2_VH
+ NEW Metal2 ( 374640 90160 ) RECT ( -280 0 280 660 ) ;
+ - vga_clock.vga_0.y_px\[2\] ( _1423_ Q ) ( _1104_ A1 ) + USE SIGNAL
+ + ROUTED Metal3 ( 367920 114800 ) ( 375760 * )
+ NEW Metal2 ( 375760 114800 ) ( * 166320 )
+ NEW Metal1 ( 367920 114800 ) Via1_HV
+ NEW Metal2 ( 367920 114800 ) Via2_VH
+ NEW Metal2 ( 375760 114800 ) Via2_VH
+ NEW Metal1 ( 375760 166320 ) Via1_VV
+ NEW Metal2 ( 367920 114800 ) RECT ( -280 -660 280 0 ) ;
+ - vga_clock.vga_0.y_px\[3\] ( _1424_ Q ) ( _0710_ A1 ) ( _0706_ A1 ) ( _0703_ A1 ) ( _0701_ A1 ) ( _0693_ A1 ) + USE SIGNAL
+ + ROUTED Metal3 ( 402640 113680 ) ( 410480 * )
+ NEW Metal2 ( 402640 104720 ) ( * 113680 )
+ NEW Metal2 ( 404880 113680 ) ( * 129360 )
+ NEW Metal2 ( 407120 129360 ) ( * 138320 )
+ NEW Metal2 ( 404880 129360 ) ( 407120 * )
+ NEW Metal3 ( 397040 137200 ) ( 407120 * )
+ NEW Metal3 ( 407120 137200 ) ( 418320 * )
+ NEW Metal1 ( 410480 113680 ) Via1_HV
+ NEW Metal2 ( 410480 113680 ) Via2_VH
+ NEW Metal2 ( 402640 113680 ) Via2_VH
+ NEW Metal1 ( 402640 104720 ) Via1_HV
+ NEW Metal1 ( 404880 129360 ) Via1_VV
+ NEW Metal2 ( 404880 113680 ) Via2_VH
+ NEW Metal1 ( 407120 138320 ) Via1_VV
+ NEW Metal1 ( 397040 137200 ) Via1_VV
+ NEW Metal2 ( 397040 137200 ) Via2_VH
+ NEW Metal2 ( 407120 137200 ) Via2_VH
+ NEW Metal1 ( 418320 137200 ) Via1_VV
+ NEW Metal2 ( 418320 137200 ) Via2_VH
+ NEW Metal2 ( 410480 113680 ) RECT ( -280 -660 280 0 )
+ NEW Metal3 ( 404880 113680 ) RECT ( -1040 -280 0 280 )
+ NEW Metal2 ( 397040 137200 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 407120 137200 ) RECT ( -280 -1040 280 0 )
+ NEW Metal2 ( 418320 137200 ) RECT ( -280 -660 280 0 ) ;
+ - vga_clock.vga_0.y_px\[4\] ( _1425_ Q ) ( _0710_ A2 ) ( _0706_ A2 ) ( _0703_ A2 ) ( _0701_ A2 ) ( _0693_ A2 ) + USE SIGNAL
+ + ROUTED Metal3 ( 403760 129360 ) ( 411600 * )
+ NEW Metal2 ( 411600 114800 ) ( * 129360 )
+ NEW Metal2 ( 403760 134960 ) ( 404880 * )
+ NEW Metal2 ( 403760 129360 ) ( * 134960 )
+ NEW Metal2 ( 414960 137200 ) ( 416080 * )
+ NEW Metal2 ( 414960 129360 ) ( * 137200 )
+ NEW Metal3 ( 411600 129360 ) ( 414960 * )
+ NEW Metal2 ( 392560 120400 ) ( * 129360 )
+ NEW Metal3 ( 392560 129360 ) ( 403760 * )
+ NEW Metal2 ( 392560 129360 ) ( * 134960 )
+ NEW Metal1 ( 403760 129360 ) Via1_VV
+ NEW Metal2 ( 403760 129360 ) Via2_VH
+ NEW Metal2 ( 411600 129360 ) Via2_VH
+ NEW Metal1 ( 411600 114800 ) Via1_HV
+ NEW Metal1 ( 404880 134960 ) Via1_VV
+ NEW Metal1 ( 416080 137200 ) Via1_VV
+ NEW Metal2 ( 414960 129360 ) Via2_VH
+ NEW Metal1 ( 392560 120400 ) Via1_HV
+ NEW Metal2 ( 392560 129360 ) Via2_VH
+ NEW Metal1 ( 392560 134960 ) Via1_VV
+ NEW Metal2 ( 403760 129360 ) RECT ( -280 -660 280 0 ) ;
+ - vga_clock.vga_0.y_px\[5\] ( _1426_ Q ) ( _0710_ A3 ) ( _0706_ B ) ( _0702_ A1 ) ( _0693_ A3 ) + USE SIGNAL
+ + ROUTED Metal3 ( 407120 143920 ) ( 420560 * )
+ NEW Metal2 ( 420560 139440 ) ( * 143920 )
+ NEW Metal2 ( 401520 131600 ) ( * 143920 )
+ NEW Metal3 ( 401520 143920 ) ( 407120 * )
+ NEW Metal3 ( 390320 136080 ) ( 401520 * )
+ NEW Metal3 ( 381360 136080 ) ( 390320 * )
+ NEW Metal1 ( 407120 143920 ) Via1_HV
+ NEW Metal2 ( 407120 143920 ) Via2_VH
+ NEW Metal2 ( 420560 143920 ) Via2_VH
+ NEW Metal1 ( 420560 139440 ) Via1_VV
+ NEW Metal1 ( 401520 131600 ) Via1_VV
+ NEW Metal2 ( 401520 143920 ) Via2_VH
+ NEW Metal1 ( 390320 136080 ) Via1_VV
+ NEW Metal2 ( 390320 136080 ) Via2_VH
+ NEW Metal2 ( 401520 136080 ) Via2_VH
+ NEW Metal1 ( 381360 136080 ) Via1_HV
+ NEW Metal2 ( 381360 136080 ) Via2_VH
+ NEW Metal2 ( 407120 143920 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 390320 136080 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 401520 136080 ) RECT ( -280 -1040 280 0 )
+ NEW Metal2 ( 381360 136080 ) RECT ( -280 -660 280 0 ) ;
+ - vga_clock.vga_0.y_px\[6\] ( _1427_ Q ) ( _1104_ A3 ) ( _0710_ B ) ( _0698_ A1 ) ( _0694_ A2 ) + USE SIGNAL
+ + ROUTED Metal3 ( 393680 138320 ) ( 398160 * )
+ NEW Metal2 ( 380240 150640 ) ( * 166320 )
+ NEW Metal3 ( 380240 150640 ) ( 393680 * )
+ NEW Metal2 ( 385840 166320 ) ( * 174160 )
+ NEW Metal2 ( 380240 166320 ) ( 385840 * )
+ NEW Metal2 ( 365680 146160 ) ( * 150640 )
+ NEW Metal3 ( 365680 150640 ) ( 380240 * )
+ NEW Metal2 ( 393680 138320 ) ( * 160720 )
+ NEW Metal2 ( 393680 138320 ) Via2_VH
+ NEW Metal1 ( 398160 138320 ) Via1_VV
+ NEW Metal2 ( 398160 138320 ) Via2_VH
+ NEW Metal1 ( 380240 166320 ) Via1_VV
+ NEW Metal2 ( 380240 150640 ) Via2_VH
+ NEW Metal2 ( 393680 150640 ) Via2_VH
+ NEW Metal1 ( 385840 174160 ) Via1_VV
+ NEW Metal1 ( 365680 146160 ) Via1_HV
+ NEW Metal2 ( 365680 150640 ) Via2_VH
+ NEW Metal1 ( 393680 160720 ) Via1_HV
+ NEW Metal2 ( 398160 138320 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 393680 150640 ) RECT ( -280 -1040 280 0 ) ;
+ - vga_clock.vga_0.y_px\[7\] ( _1428_ Q ) ( _1104_ A2 ) ( _0711_ A1 ) ( _0694_ A1 ) + USE SIGNAL
+ + ROUTED Metal2 ( 383600 168560 ) ( * 174160 )
+ NEW Metal2 ( 369040 167440 ) ( * 168560 )
+ NEW Metal3 ( 369040 168560 ) ( 378000 * )
+ NEW Metal3 ( 378000 168560 ) ( 390320 * )
+ NEW Metal1 ( 378000 168560 ) Via1_VV
+ NEW Metal2 ( 378000 168560 ) Via2_VH
+ NEW Metal1 ( 383600 174160 ) Via1_VV
+ NEW Metal2 ( 383600 168560 ) Via2_VH
+ NEW Metal1 ( 369040 167440 ) Via1_HV
+ NEW Metal2 ( 369040 168560 ) Via2_VH
+ NEW Metal1 ( 390320 168560 ) Via1_HV
+ NEW Metal2 ( 390320 168560 ) Via2_VH
+ NEW Metal2 ( 378000 168560 ) RECT ( -280 -660 280 0 )
+ NEW Metal3 ( 383600 168560 ) RECT ( -1040 -280 0 280 )
+ NEW Metal2 ( 390320 168560 ) RECT ( -280 -660 280 0 ) ;
+ - vga_clock.vga_0.y_px\[8\] ( _1429_ Q ) ( _1101_ A1 ) ( _0719_ I ) ( _0695_ A1 ) + USE SIGNAL
+ + ROUTED Metal2 ( 362320 203280 ) ( * 229040 )
+ NEW Metal3 ( 362320 203280 ) ( 365680 * )
+ NEW Metal2 ( 365680 198800 ) ( * 203280 )
+ NEW Metal3 ( 402640 198800 ) ( * 203280 )
+ NEW Metal3 ( 401520 198800 ) ( 402640 * )
+ NEW Metal2 ( 389200 208880 ) ( * 223440 )
+ NEW Metal2 ( 388080 208880 ) ( 389200 * )
+ NEW Metal2 ( 388080 203280 ) ( * 208880 )
+ NEW Metal3 ( 365680 203280 ) ( 402640 * )
+ NEW Metal2 ( 365680 203280 ) Via2_VH
+ NEW Metal1 ( 362320 229040 ) Via1_VV
+ NEW Metal2 ( 362320 203280 ) Via2_VH
+ NEW Metal1 ( 365680 198800 ) Via1_HV
+ NEW Metal1 ( 401520 198800 ) Via1_VV
+ NEW Metal2 ( 401520 198800 ) Via2_VH
+ NEW Metal1 ( 389200 223440 ) Via1_HV
+ NEW Metal2 ( 388080 203280 ) Via2_VH
+ NEW Metal2 ( 401520 198800 ) RECT ( -280 -660 280 0 )
+ NEW Metal3 ( 388080 203280 ) RECT ( -1040 -280 0 280 ) ;
+ - vga_clock.vga_0.y_px\[9\] ( _1430_ Q ) ( _1104_ A4 ) ( _0721_ A1 ) + USE SIGNAL
+ + ROUTED Metal2 ( 372400 183120 ) ( * 194320 )
+ NEW Metal3 ( 372400 194320 ) ( 385840 * )
+ NEW Metal2 ( 385840 194320 ) ( * 199920 )
+ NEW Metal2 ( 381360 168560 ) ( * 194320 )
+ NEW Metal1 ( 372400 183120 ) Via1_HV
+ NEW Metal2 ( 372400 194320 ) Via2_VH
+ NEW Metal2 ( 385840 194320 ) Via2_VH
+ NEW Metal1 ( 385840 199920 ) Via1_HV
+ NEW Metal1 ( 381360 168560 ) Via1_VV
+ NEW Metal2 ( 381360 194320 ) Via2_VH
+ NEW Metal3 ( 381360 194320 ) RECT ( -1040 -280 0 280 ) ;
+ - vga_clock.x_block_q\[0\] ( _1506_ Q ) + USE SIGNAL ;
+ - vga_clock.x_block_q\[1\] ( _1507_ Q ) + USE SIGNAL ;
+ - vga_clock.x_block_q\[2\] ( _1508_ Q ) + USE SIGNAL ;
+ - vga_clock.x_block_q\[3\] ( _1509_ Q ) + USE SIGNAL ;
+ - vga_clock.x_block_q\[4\] ( _1510_ Q ) + USE SIGNAL ;
+ - vga_clock.x_block_q\[5\] ( _1511_ Q ) ( _1355_ A1 ) + USE SIGNAL
+ + ROUTED Metal2 ( 475440 225680 ) ( * 255920 )
+ NEW Metal2 ( 475440 255920 ) ( 484400 * )
+ NEW Metal1 ( 475440 225680 ) Via1_VV
+ NEW Metal1 ( 484400 255920 ) Via1_HV ;
+ - vga_clock.y_block\[0\] ( _1500_ D ) ( _0728_ A2 ) ( _0705_ A2 ) ( _0704_ Z ) + USE SIGNAL
+ + ROUTED Metal2 ( 457520 112560 ) ( * 145040 )
+ NEW Metal3 ( 431760 112560 ) ( 463120 * )
+ NEW Metal2 ( 457520 145040 ) ( * 152880 )
+ NEW Metal1 ( 463120 112560 ) Via1_HV
+ NEW Metal2 ( 463120 112560 ) Via2_VH
+ NEW Metal1 ( 457520 145040 ) Via1_VV
+ NEW Metal2 ( 457520 112560 ) Via2_VH
+ NEW Metal1 ( 431760 112560 ) Via1_VV
+ NEW Metal2 ( 431760 112560 ) Via2_VH
+ NEW Metal1 ( 457520 152880 ) Via1_HV
+ NEW Metal2 ( 463120 112560 ) RECT ( -280 -660 280 0 )
+ NEW Metal3 ( 457520 112560 ) RECT ( -1040 -280 0 280 )
+ NEW Metal2 ( 431760 112560 ) RECT ( -280 -660 280 0 ) ;
+ - vga_clock.y_block\[1\] ( _1501_ D ) ( _0865_ ZN ) + USE SIGNAL
+ + ROUTED Metal2 ( 427280 122640 ) ( * 127120 )
+ NEW Metal3 ( 419440 127120 ) ( 427280 * )
+ NEW Metal1 ( 427280 122640 ) Via1_HV
+ NEW Metal2 ( 427280 127120 ) Via2_VH
+ NEW Metal1 ( 419440 127120 ) Via1_VV
+ NEW Metal2 ( 419440 127120 ) Via2_VH
+ NEW Metal2 ( 419440 127120 ) RECT ( -280 -660 280 0 ) ;
+ - vga_clock.y_block\[2\] ( _1502_ D ) ( _0730_ A2 ) ( _0709_ A2 ) ( _0700_ A2 ) ( _0699_ Z ) + USE SIGNAL
+ + ROUTED Metal2 ( 432880 152880 ) ( * 154000 )
+ NEW Metal3 ( 432880 152880 ) ( 450800 * )
+ NEW Metal2 ( 442960 152880 ) ( * 168560 )
+ NEW Metal2 ( 427280 167440 ) ( * 168560 )
+ NEW Metal3 ( 427280 168560 ) ( 442960 * )
+ NEW Metal2 ( 419440 168560 ) ( * 169680 )
+ NEW Metal3 ( 419440 168560 ) ( 427280 * )
+ NEW Metal2 ( 450800 138320 ) ( * 152880 )
+ NEW Metal1 ( 450800 138320 ) Via1_HV
+ NEW Metal1 ( 432880 154000 ) Via1_HV
+ NEW Metal2 ( 432880 152880 ) Via2_VH
+ NEW Metal2 ( 450800 152880 ) Via2_VH
+ NEW Metal1 ( 442960 168560 ) Via1_HV
+ NEW Metal2 ( 442960 152880 ) Via2_VH
+ NEW Metal1 ( 427280 167440 ) Via1_VV
+ NEW Metal2 ( 427280 168560 ) Via2_VH
+ NEW Metal2 ( 442960 168560 ) Via2_VH
+ NEW Metal1 ( 419440 169680 ) Via1_VV
+ NEW Metal2 ( 419440 168560 ) Via2_VH
+ NEW Metal3 ( 442960 152880 ) RECT ( -1040 -280 0 280 )
+ NEW Metal2 ( 442960 168560 ) RECT ( -280 -1040 280 0 ) ;
+ - vga_clock.y_block\[3\] ( _1503_ D ) ( _0726_ A2 ) ( _0714_ A2 ) ( _0713_ A2 ) ( _0712_ Z ) + USE SIGNAL
+ + ROUTED Metal2 ( 437360 184240 ) ( * 186480 )
+ NEW Metal3 ( 437360 186480 ) ( 446320 * )
+ NEW Metal2 ( 446320 186480 ) ( * 198800 )
+ NEW Metal2 ( 422800 187600 ) ( * 190960 )
+ NEW Metal3 ( 422800 186480 ) ( * 187600 )
+ NEW Metal3 ( 422800 186480 ) ( 437360 * )
+ NEW Metal2 ( 420560 185360 ) ( * 186480 )
+ NEW Metal3 ( 420560 186480 ) ( 422800 * )
+ NEW Metal3 ( 409360 175280 ) ( 420560 * )
+ NEW Metal2 ( 420560 175280 ) ( * 185360 )
+ NEW Metal1 ( 437360 184240 ) Via1_HV
+ NEW Metal2 ( 437360 186480 ) Via2_VH
+ NEW Metal2 ( 446320 186480 ) Via2_VH
+ NEW Metal1 ( 446320 198800 ) Via1_HV
+ NEW Metal1 ( 422800 190960 ) Via1_VV
+ NEW Metal2 ( 422800 187600 ) Via2_VH
+ NEW Metal1 ( 420560 185360 ) Via1_VV
+ NEW Metal2 ( 420560 186480 ) Via2_VH
+ NEW Metal1 ( 409360 175280 ) Via1_VV
+ NEW Metal2 ( 409360 175280 ) Via2_VH
+ NEW Metal2 ( 420560 175280 ) Via2_VH
+ NEW Metal2 ( 409360 175280 ) RECT ( -280 -660 280 0 ) ;
+ - vga_clock.y_block\[4\] ( _1504_ D ) ( _0717_ A2 ) ( _0697_ A2 ) ( _0696_ Z ) + USE SIGNAL
+ + ROUTED Metal2 ( 422800 224560 ) ( * 245840 )
+ NEW Metal2 ( 422800 245840 ) ( 426160 * )
+ NEW Metal2 ( 419440 216720 ) ( * 224560 )
+ NEW Metal2 ( 419440 224560 ) ( 422800 * )
+ NEW Metal3 ( 403760 222320 ) ( 419440 * )
+ NEW Metal1 ( 422800 224560 ) Via1_HV
+ NEW Metal1 ( 426160 245840 ) Via1_HV
+ NEW Metal1 ( 419440 216720 ) Via1_VV
+ NEW Metal1 ( 403760 222320 ) Via1_VV
+ NEW Metal2 ( 403760 222320 ) Via2_VH
+ NEW Metal2 ( 419440 222320 ) Via2_VH
+ NEW Metal2 ( 403760 222320 ) RECT ( -280 -660 280 0 )
+ NEW Metal2 ( 419440 222320 ) RECT ( -280 -1040 280 0 ) ;
+ - vga_clock.y_block\[5\] ( _1505_ D ) ( _0723_ A3 ) ( _0722_ Z ) + USE SIGNAL
+ + ROUTED Metal2 ( 444080 215600 ) ( * 216720 )
+ NEW Metal3 ( 402640 216720 ) ( 444080 * )
+ NEW Metal2 ( 453040 216720 ) ( * 230160 )
+ NEW Metal3 ( 444080 216720 ) ( 453040 * )
+ NEW Metal1 ( 444080 215600 ) Via1_HV
+ NEW Metal2 ( 444080 216720 ) Via2_VH
+ NEW Metal1 ( 402640 216720 ) Via1_VV
+ NEW Metal2 ( 402640 216720 ) Via2_VH
+ NEW Metal1 ( 453040 230160 ) Via1_HV
+ NEW Metal2 ( 453040 216720 ) Via2_VH
+ NEW Metal2 ( 402640 216720 ) RECT ( -280 -660 280 0 ) ;
+ - vga_clock.y_block_q\[0\] ( _1500_ Q ) ( _1356_ A2 ) + USE SIGNAL
+ + ROUTED Metal2 ( 484400 114800 ) ( * 121520 )
+ NEW Metal2 ( 477680 121520 ) ( 484400 * )
+ NEW Metal1 ( 484400 114800 ) Via1_HV
+ NEW Metal1 ( 477680 121520 ) Via1_VV ;
+ - vga_clock.y_block_q\[1\] ( _1501_ Q ) ( _1356_ A1 ) + USE SIGNAL
+ + ROUTED Metal3 ( 448560 120400 ) ( 475440 * )
+ NEW Metal2 ( 475440 120400 ) ( * 121520 )
+ NEW Metal1 ( 448560 120400 ) Via1_HV
+ NEW Metal2 ( 448560 120400 ) Via2_VH
+ NEW Metal2 ( 475440 120400 ) Via2_VH
+ NEW Metal1 ( 475440 121520 ) Via1_VV
+ NEW Metal2 ( 448560 120400 ) RECT ( -280 -660 280 0 ) ;
+ - vga_clock.y_block_q\[2\] ( _1502_ Q ) ( _1356_ B ) + USE SIGNAL
+ + ROUTED Metal2 ( 472080 121520 ) ( * 136080 )
+ NEW Metal1 ( 472080 121520 ) Via1_HV
+ NEW Metal1 ( 472080 136080 ) Via1_HV ;
+ - vga_clock.y_block_q\[3\] ( _1503_ Q ) ( _1355_ A3 ) + USE SIGNAL
+ + ROUTED Metal2 ( 467600 198800 ) ( * 211120 )
+ NEW Metal2 ( 467600 211120 ) ( 470960 * )
+ NEW Metal2 ( 470960 211120 ) ( * 223440 )
+ NEW Metal1 ( 467600 198800 ) Via1_HV
+ NEW Metal1 ( 470960 223440 ) Via1_VV ;
+ - vga_clock.y_block_q\[4\] ( _1504_ Q ) ( _1355_ A2 ) + USE SIGNAL
+ + ROUTED Metal2 ( 473200 223440 ) ( * 245840 )
+ NEW Metal3 ( 447440 245840 ) ( 473200 * )
+ NEW Metal1 ( 473200 223440 ) Via1_VV
+ NEW Metal2 ( 473200 245840 ) Via2_VH
+ NEW Metal1 ( 447440 245840 ) Via1_HV
+ NEW Metal2 ( 447440 245840 ) Via2_VH
+ NEW Metal2 ( 447440 245840 ) RECT ( -280 -660 280 0 ) ;
+ - vga_clock.y_block_q\[5\] ( _1505_ Q ) ( _1355_ A4 ) + USE SIGNAL
+ + ROUTED Metal3 ( 469840 230160 ) ( 474320 * )
+ NEW Metal2 ( 469840 225680 ) ( * 230160 )
+ NEW Metal1 ( 474320 230160 ) Via1_HV
+ NEW Metal2 ( 474320 230160 ) Via2_VH
+ NEW Metal2 ( 469840 230160 ) Via2_VH
+ NEW Metal1 ( 469840 225680 ) Via1_VV
+ NEW Metal2 ( 474320 230160 ) RECT ( -280 -660 280 0 ) ;
+ - wb_clk_i ( PIN wb_clk_i ) ( ANTENNA_clkbuf_0_wb_clk_i_I I ) ( clkbuf_0_wb_clk_i I ) + USE CLOCK
+ + ROUTED Metal2 ( 47600 309680 ) ( 48720 * )
+ NEW Metal2 ( 48720 299600 ) ( * 309680 )
+ NEW Metal3 ( 7280 516880 0 ) ( 48720 * )
+ NEW Metal2 ( 296240 299600 ) ( * 301840 )
+ NEW Metal3 ( 289520 299600 ) ( 296240 * )
+ NEW Metal2 ( 47600 309680 ) ( * 319200 )
+ NEW Metal2 ( 47600 319200 ) ( 48720 * )
+ NEW Metal2 ( 48720 319200 ) ( * 516880 )
+ NEW Metal3 ( 48720 299600 ) ( 289520 * )
+ NEW Metal2 ( 48720 299600 ) Via2_VH
+ NEW Metal2 ( 48720 516880 ) Via2_VH
+ NEW Metal1 ( 289520 299600 ) Via1_VV
+ NEW Metal2 ( 289520 299600 ) Via2_VH
+ NEW Metal1 ( 296240 301840 ) Via1_HV
+ NEW Metal2 ( 296240 299600 ) Via2_VH
+ NEW Metal2 ( 289520 299600 ) RECT ( -280 -660 280 0 ) ;
+ - wb_rst_i ( PIN wb_rst_i ) ( ANTENNA_input4_I I ) ( input4 I ) + USE SIGNAL
+ + ROUTED Metal2 ( 580720 290640 ) ( * 294000 )
+ NEW Metal3 ( 580720 290640 ) ( 593040 * 0 )
+ NEW Metal2 ( 580720 299600 ) ( 581840 * )
+ NEW Metal2 ( 580720 294000 ) ( * 299600 )
+ NEW Metal1 ( 580720 294000 ) Via1_VV
+ NEW Metal2 ( 580720 290640 ) Via2_VH
+ NEW Metal1 ( 581840 299600 ) Via1_VV ;
+END NETS
+END DESIGN
diff --git a/gds/user_proj_example.gds b/gds/user_proj_example.gds
deleted file mode 100644
index 8dd7f1f..0000000
--- a/gds/user_proj_example.gds
+++ /dev/null
Binary files differ
diff --git a/gds/user_project_wrapper.gds b/gds/user_project_wrapper.gds
deleted file mode 100644
index da1a69d..0000000
--- a/gds/user_project_wrapper.gds
+++ /dev/null
Binary files differ
diff --git a/lef/user_project_wrapper.lef b/lef/user_project_wrapper.lef
index 691aef2..8d44d7b 100644
--- a/lef/user_project_wrapper.lef
+++ b/lef/user_project_wrapper.lef
@@ -2536,11 +2536,19 @@
END
PORT
LAYER Metal4 ;
- RECT 655.290 1.620 658.390 2997.180 ;
+ RECT 655.290 1.620 658.390 941.210 ;
END
PORT
LAYER Metal4 ;
- RECT 745.290 1.620 748.390 2997.180 ;
+ RECT 655.290 1073.030 658.390 2997.180 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 745.290 1.620 748.390 941.210 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 745.290 1073.030 748.390 2997.180 ;
END
PORT
LAYER Metal4 ;
@@ -2548,51 +2556,27 @@
END
PORT
LAYER Metal4 ;
- RECT 925.290 1.620 928.390 849.370 ;
+ RECT 925.290 1.620 928.390 2997.180 ;
END
PORT
LAYER Metal4 ;
- RECT 925.290 1436.470 928.390 2997.180 ;
+ RECT 1015.290 1.620 1018.390 2997.180 ;
END
PORT
LAYER Metal4 ;
- RECT 1015.290 1.620 1018.390 849.370 ;
+ RECT 1105.290 1.620 1108.390 2997.180 ;
END
PORT
LAYER Metal4 ;
- RECT 1015.290 1436.470 1018.390 2997.180 ;
+ RECT 1195.290 1.620 1198.390 2997.180 ;
END
PORT
LAYER Metal4 ;
- RECT 1105.290 1.620 1108.390 849.370 ;
+ RECT 1285.290 1.620 1288.390 2997.180 ;
END
PORT
LAYER Metal4 ;
- RECT 1105.290 1436.470 1108.390 2997.180 ;
- END
- PORT
- LAYER Metal4 ;
- RECT 1195.290 1.620 1198.390 849.370 ;
- END
- PORT
- LAYER Metal4 ;
- RECT 1195.290 1436.470 1198.390 2997.180 ;
- END
- PORT
- LAYER Metal4 ;
- RECT 1285.290 1.620 1288.390 849.370 ;
- END
- PORT
- LAYER Metal4 ;
- RECT 1285.290 1436.470 1288.390 2997.180 ;
- END
- PORT
- LAYER Metal4 ;
- RECT 1375.290 1.620 1378.390 850.100 ;
- END
- PORT
- LAYER Metal4 ;
- RECT 1375.290 1439.660 1378.390 2997.180 ;
+ RECT 1375.290 1.620 1378.390 2997.180 ;
END
PORT
LAYER Metal4 ;
@@ -2844,7 +2828,11 @@
END
PORT
LAYER Metal4 ;
- RECT 673.890 1.620 676.990 2997.180 ;
+ RECT 673.890 1.620 676.990 941.210 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 673.890 1073.030 676.990 2997.180 ;
END
PORT
LAYER Metal4 ;
@@ -2852,7 +2840,7 @@
END
PORT
LAYER Metal4 ;
- RECT 763.890 1439.660 766.990 2997.180 ;
+ RECT 763.890 1137.820 766.990 2997.180 ;
END
PORT
LAYER Metal4 ;
@@ -2860,35 +2848,19 @@
END
PORT
LAYER Metal4 ;
- RECT 943.890 1.620 946.990 849.370 ;
+ RECT 943.890 1.620 946.990 2997.180 ;
END
PORT
LAYER Metal4 ;
- RECT 943.890 1436.470 946.990 2997.180 ;
+ RECT 1033.890 1.620 1036.990 2997.180 ;
END
PORT
LAYER Metal4 ;
- RECT 1033.890 1.620 1036.990 849.370 ;
+ RECT 1123.890 1.620 1126.990 2997.180 ;
END
PORT
LAYER Metal4 ;
- RECT 1033.890 1436.470 1036.990 2997.180 ;
- END
- PORT
- LAYER Metal4 ;
- RECT 1123.890 1.620 1126.990 849.370 ;
- END
- PORT
- LAYER Metal4 ;
- RECT 1123.890 1436.470 1126.990 2997.180 ;
- END
- PORT
- LAYER Metal4 ;
- RECT 1213.890 1.620 1216.990 849.370 ;
- END
- PORT
- LAYER Metal4 ;
- RECT 1213.890 1436.470 1216.990 2997.180 ;
+ RECT 1213.890 1.620 1216.990 2997.180 ;
END
PORT
LAYER Metal4 ;
@@ -3949,7 +3921,7 @@
END wbs_we_i
OBS
LAYER Metal1 ;
- RECT 594.220 768.470 1480.700 1430.610 ;
+ RECT 594.220 860.380 880.380 1145.610 ;
LAYER Metal2 ;
RECT 20.860 2997.300 57.660 2998.100 ;
RECT 59.380 2997.300 168.540 2998.100 ;
@@ -3978,313 +3950,313 @@
RECT 2609.620 2997.300 2718.780 2998.100 ;
RECT 2720.500 2997.300 2829.660 2998.100 ;
RECT 2831.380 2997.300 2940.540 2998.100 ;
- RECT 2942.260 2997.300 2990.820 2998.100 ;
- RECT 20.860 2.700 2990.820 2997.300 ;
- RECT 20.860 0.090 66.060 2.700 ;
- RECT 67.780 0.090 75.580 2.700 ;
- RECT 77.300 0.090 85.100 2.700 ;
- RECT 86.820 0.090 94.620 2.700 ;
- RECT 96.340 0.090 104.140 2.700 ;
- RECT 105.860 0.090 113.660 2.700 ;
- RECT 115.380 0.090 123.180 2.700 ;
- RECT 124.900 0.090 132.700 2.700 ;
- RECT 134.420 0.090 142.220 2.700 ;
- RECT 143.940 0.090 151.740 2.700 ;
- RECT 153.460 0.090 161.260 2.700 ;
- RECT 162.980 0.090 170.780 2.700 ;
- RECT 172.500 0.090 180.300 2.700 ;
- RECT 182.020 0.090 189.820 2.700 ;
- RECT 191.540 0.090 199.340 2.700 ;
- RECT 201.060 0.090 208.860 2.700 ;
- RECT 210.580 0.090 218.380 2.700 ;
- RECT 220.100 0.090 227.900 2.700 ;
- RECT 229.620 0.090 237.420 2.700 ;
- RECT 239.140 0.090 246.940 2.700 ;
- RECT 248.660 0.090 256.460 2.700 ;
- RECT 258.180 0.090 265.980 2.700 ;
- RECT 267.700 0.090 275.500 2.700 ;
- RECT 277.220 0.090 285.020 2.700 ;
- RECT 286.740 0.090 294.540 2.700 ;
- RECT 296.260 0.090 304.060 2.700 ;
- RECT 305.780 0.090 313.580 2.700 ;
- RECT 315.300 0.090 323.100 2.700 ;
- RECT 324.820 0.090 332.620 2.700 ;
- RECT 334.340 0.090 342.140 2.700 ;
- RECT 343.860 0.090 351.660 2.700 ;
- RECT 353.380 0.090 361.180 2.700 ;
- RECT 362.900 0.090 370.700 2.700 ;
- RECT 372.420 0.090 380.220 2.700 ;
- RECT 381.940 0.090 389.740 2.700 ;
- RECT 391.460 0.090 399.260 2.700 ;
- RECT 400.980 0.090 408.780 2.700 ;
- RECT 410.500 0.090 418.300 2.700 ;
- RECT 420.020 0.090 427.820 2.700 ;
- RECT 429.540 0.090 437.340 2.700 ;
- RECT 439.060 0.090 446.860 2.700 ;
- RECT 448.580 0.090 456.380 2.700 ;
- RECT 458.100 0.090 465.900 2.700 ;
- RECT 467.620 0.090 475.420 2.700 ;
- RECT 477.140 0.090 484.940 2.700 ;
- RECT 486.660 0.090 494.460 2.700 ;
- RECT 496.180 0.090 503.980 2.700 ;
- RECT 505.700 0.090 513.500 2.700 ;
- RECT 515.220 0.090 523.020 2.700 ;
- RECT 524.740 0.090 532.540 2.700 ;
- RECT 534.260 0.090 542.060 2.700 ;
- RECT 543.780 0.090 551.580 2.700 ;
- RECT 553.300 0.090 561.100 2.700 ;
- RECT 562.820 0.090 570.620 2.700 ;
- RECT 572.340 0.090 580.140 2.700 ;
- RECT 581.860 0.090 589.660 2.700 ;
- RECT 591.380 0.090 599.180 2.700 ;
- RECT 600.900 0.090 608.700 2.700 ;
- RECT 610.420 0.090 618.220 2.700 ;
- RECT 619.940 0.090 627.740 2.700 ;
- RECT 629.460 0.090 637.260 2.700 ;
- RECT 638.980 0.090 646.780 2.700 ;
- RECT 648.500 0.090 656.300 2.700 ;
- RECT 658.020 0.090 665.820 2.700 ;
- RECT 667.540 0.090 675.340 2.700 ;
- RECT 677.060 0.090 684.860 2.700 ;
- RECT 686.580 0.090 694.380 2.700 ;
- RECT 696.100 0.090 703.900 2.700 ;
- RECT 705.620 0.090 713.420 2.700 ;
- RECT 715.140 0.090 722.940 2.700 ;
- RECT 724.660 0.090 732.460 2.700 ;
- RECT 734.180 0.090 741.980 2.700 ;
- RECT 743.700 0.090 751.500 2.700 ;
- RECT 753.220 0.090 761.020 2.700 ;
- RECT 762.740 0.090 770.540 2.700 ;
- RECT 772.260 0.090 780.060 2.700 ;
- RECT 781.780 0.090 789.580 2.700 ;
- RECT 791.300 0.090 799.100 2.700 ;
- RECT 800.820 0.090 808.620 2.700 ;
- RECT 810.340 0.090 818.140 2.700 ;
- RECT 819.860 0.090 827.660 2.700 ;
- RECT 829.380 0.090 837.180 2.700 ;
- RECT 838.900 0.090 846.700 2.700 ;
- RECT 848.420 0.090 856.220 2.700 ;
- RECT 857.940 0.090 865.740 2.700 ;
- RECT 867.460 0.090 875.260 2.700 ;
- RECT 876.980 0.090 884.780 2.700 ;
- RECT 886.500 0.090 894.300 2.700 ;
- RECT 896.020 0.090 903.820 2.700 ;
- RECT 905.540 0.090 913.340 2.700 ;
- RECT 915.060 0.090 922.860 2.700 ;
- RECT 924.580 0.090 932.380 2.700 ;
- RECT 934.100 0.090 941.900 2.700 ;
- RECT 943.620 0.090 951.420 2.700 ;
- RECT 953.140 0.090 960.940 2.700 ;
- RECT 962.660 0.090 970.460 2.700 ;
- RECT 972.180 0.090 979.980 2.700 ;
- RECT 981.700 0.090 989.500 2.700 ;
- RECT 991.220 0.090 999.020 2.700 ;
- RECT 1000.740 0.090 1008.540 2.700 ;
- RECT 1010.260 0.090 1018.060 2.700 ;
- RECT 1019.780 0.090 1027.580 2.700 ;
- RECT 1029.300 0.090 1037.100 2.700 ;
- RECT 1038.820 0.090 1046.620 2.700 ;
- RECT 1048.340 0.090 1056.140 2.700 ;
- RECT 1057.860 0.090 1065.660 2.700 ;
- RECT 1067.380 0.090 1075.180 2.700 ;
- RECT 1076.900 0.090 1084.700 2.700 ;
- RECT 1086.420 0.090 1094.220 2.700 ;
- RECT 1095.940 0.090 1103.740 2.700 ;
- RECT 1105.460 0.090 1113.260 2.700 ;
- RECT 1114.980 0.090 1122.780 2.700 ;
- RECT 1124.500 0.090 1132.300 2.700 ;
- RECT 1134.020 0.090 1141.820 2.700 ;
- RECT 1143.540 0.090 1151.340 2.700 ;
- RECT 1153.060 0.090 1160.860 2.700 ;
- RECT 1162.580 0.090 1170.380 2.700 ;
- RECT 1172.100 0.090 1179.900 2.700 ;
- RECT 1181.620 0.090 1189.420 2.700 ;
- RECT 1191.140 0.090 1198.940 2.700 ;
- RECT 1200.660 0.090 1208.460 2.700 ;
- RECT 1210.180 0.090 1217.980 2.700 ;
- RECT 1219.700 0.090 1227.500 2.700 ;
- RECT 1229.220 0.090 1237.020 2.700 ;
- RECT 1238.740 0.090 1246.540 2.700 ;
- RECT 1248.260 0.090 1256.060 2.700 ;
- RECT 1257.780 0.090 1265.580 2.700 ;
- RECT 1267.300 0.090 1275.100 2.700 ;
- RECT 1276.820 0.090 1284.620 2.700 ;
- RECT 1286.340 0.090 1294.140 2.700 ;
- RECT 1295.860 0.090 1303.660 2.700 ;
- RECT 1305.380 0.090 1313.180 2.700 ;
- RECT 1314.900 0.090 1322.700 2.700 ;
- RECT 1324.420 0.090 1332.220 2.700 ;
- RECT 1333.940 0.090 1341.740 2.700 ;
- RECT 1343.460 0.090 1351.260 2.700 ;
- RECT 1352.980 0.090 1360.780 2.700 ;
- RECT 1362.500 0.090 1370.300 2.700 ;
- RECT 1372.020 0.090 1379.820 2.700 ;
- RECT 1381.540 0.090 1389.340 2.700 ;
- RECT 1391.060 0.090 1398.860 2.700 ;
- RECT 1400.580 0.090 1408.380 2.700 ;
- RECT 1410.100 0.090 1417.900 2.700 ;
- RECT 1419.620 0.090 1427.420 2.700 ;
- RECT 1429.140 0.090 1436.940 2.700 ;
- RECT 1438.660 0.090 1446.460 2.700 ;
- RECT 1448.180 0.090 1455.980 2.700 ;
- RECT 1457.700 0.090 1465.500 2.700 ;
- RECT 1467.220 0.090 1475.020 2.700 ;
- RECT 1476.740 0.090 1484.540 2.700 ;
- RECT 1486.260 0.090 1494.060 2.700 ;
- RECT 1495.780 0.090 1503.580 2.700 ;
- RECT 1505.300 0.090 1513.100 2.700 ;
- RECT 1514.820 0.090 1522.620 2.700 ;
- RECT 1524.340 0.090 1532.140 2.700 ;
- RECT 1533.860 0.090 1541.660 2.700 ;
- RECT 1543.380 0.090 1551.180 2.700 ;
- RECT 1552.900 0.090 1560.700 2.700 ;
- RECT 1562.420 0.090 1570.220 2.700 ;
- RECT 1571.940 0.090 1579.740 2.700 ;
- RECT 1581.460 0.090 1589.260 2.700 ;
- RECT 1590.980 0.090 1598.780 2.700 ;
- RECT 1600.500 0.090 1608.300 2.700 ;
- RECT 1610.020 0.090 1617.820 2.700 ;
- RECT 1619.540 0.090 1627.340 2.700 ;
- RECT 1629.060 0.090 1636.860 2.700 ;
- RECT 1638.580 0.090 1646.380 2.700 ;
- RECT 1648.100 0.090 1655.900 2.700 ;
- RECT 1657.620 0.090 1665.420 2.700 ;
- RECT 1667.140 0.090 1674.940 2.700 ;
- RECT 1676.660 0.090 1684.460 2.700 ;
- RECT 1686.180 0.090 1693.980 2.700 ;
- RECT 1695.700 0.090 1703.500 2.700 ;
- RECT 1705.220 0.090 1713.020 2.700 ;
- RECT 1714.740 0.090 1722.540 2.700 ;
- RECT 1724.260 0.090 1732.060 2.700 ;
- RECT 1733.780 0.090 1741.580 2.700 ;
- RECT 1743.300 0.090 1751.100 2.700 ;
- RECT 1752.820 0.090 1760.620 2.700 ;
- RECT 1762.340 0.090 1770.140 2.700 ;
- RECT 1771.860 0.090 1779.660 2.700 ;
- RECT 1781.380 0.090 1789.180 2.700 ;
- RECT 1790.900 0.090 1798.700 2.700 ;
- RECT 1800.420 0.090 1808.220 2.700 ;
- RECT 1809.940 0.090 1817.740 2.700 ;
- RECT 1819.460 0.090 1827.260 2.700 ;
- RECT 1828.980 0.090 1836.780 2.700 ;
- RECT 1838.500 0.090 1846.300 2.700 ;
- RECT 1848.020 0.090 1855.820 2.700 ;
- RECT 1857.540 0.090 1865.340 2.700 ;
- RECT 1867.060 0.090 1874.860 2.700 ;
- RECT 1876.580 0.090 1884.380 2.700 ;
- RECT 1886.100 0.090 1893.900 2.700 ;
- RECT 1895.620 0.090 1903.420 2.700 ;
- RECT 1905.140 0.090 1912.940 2.700 ;
- RECT 1914.660 0.090 1922.460 2.700 ;
- RECT 1924.180 0.090 1931.980 2.700 ;
- RECT 1933.700 0.090 1941.500 2.700 ;
- RECT 1943.220 0.090 1951.020 2.700 ;
- RECT 1952.740 0.090 1960.540 2.700 ;
- RECT 1962.260 0.090 1970.060 2.700 ;
- RECT 1971.780 0.090 1979.580 2.700 ;
- RECT 1981.300 0.090 1989.100 2.700 ;
- RECT 1990.820 0.090 1998.620 2.700 ;
- RECT 2000.340 0.090 2008.140 2.700 ;
- RECT 2009.860 0.090 2017.660 2.700 ;
- RECT 2019.380 0.090 2027.180 2.700 ;
- RECT 2028.900 0.090 2036.700 2.700 ;
- RECT 2038.420 0.090 2046.220 2.700 ;
- RECT 2047.940 0.090 2055.740 2.700 ;
- RECT 2057.460 0.090 2065.260 2.700 ;
- RECT 2066.980 0.090 2074.780 2.700 ;
- RECT 2076.500 0.090 2084.300 2.700 ;
- RECT 2086.020 0.090 2093.820 2.700 ;
- RECT 2095.540 0.090 2103.340 2.700 ;
- RECT 2105.060 0.090 2112.860 2.700 ;
- RECT 2114.580 0.090 2122.380 2.700 ;
- RECT 2124.100 0.090 2131.900 2.700 ;
- RECT 2133.620 0.090 2141.420 2.700 ;
- RECT 2143.140 0.090 2150.940 2.700 ;
- RECT 2152.660 0.090 2160.460 2.700 ;
- RECT 2162.180 0.090 2169.980 2.700 ;
- RECT 2171.700 0.090 2179.500 2.700 ;
- RECT 2181.220 0.090 2189.020 2.700 ;
- RECT 2190.740 0.090 2198.540 2.700 ;
- RECT 2200.260 0.090 2208.060 2.700 ;
- RECT 2209.780 0.090 2217.580 2.700 ;
- RECT 2219.300 0.090 2227.100 2.700 ;
- RECT 2228.820 0.090 2236.620 2.700 ;
- RECT 2238.340 0.090 2246.140 2.700 ;
- RECT 2247.860 0.090 2255.660 2.700 ;
- RECT 2257.380 0.090 2265.180 2.700 ;
- RECT 2266.900 0.090 2274.700 2.700 ;
- RECT 2276.420 0.090 2284.220 2.700 ;
- RECT 2285.940 0.090 2293.740 2.700 ;
- RECT 2295.460 0.090 2303.260 2.700 ;
- RECT 2304.980 0.090 2312.780 2.700 ;
- RECT 2314.500 0.090 2322.300 2.700 ;
- RECT 2324.020 0.090 2331.820 2.700 ;
- RECT 2333.540 0.090 2341.340 2.700 ;
- RECT 2343.060 0.090 2350.860 2.700 ;
- RECT 2352.580 0.090 2360.380 2.700 ;
- RECT 2362.100 0.090 2369.900 2.700 ;
- RECT 2371.620 0.090 2379.420 2.700 ;
- RECT 2381.140 0.090 2388.940 2.700 ;
- RECT 2390.660 0.090 2398.460 2.700 ;
- RECT 2400.180 0.090 2407.980 2.700 ;
- RECT 2409.700 0.090 2417.500 2.700 ;
- RECT 2419.220 0.090 2427.020 2.700 ;
- RECT 2428.740 0.090 2436.540 2.700 ;
- RECT 2438.260 0.090 2446.060 2.700 ;
- RECT 2447.780 0.090 2455.580 2.700 ;
- RECT 2457.300 0.090 2465.100 2.700 ;
- RECT 2466.820 0.090 2474.620 2.700 ;
- RECT 2476.340 0.090 2484.140 2.700 ;
- RECT 2485.860 0.090 2493.660 2.700 ;
- RECT 2495.380 0.090 2503.180 2.700 ;
- RECT 2504.900 0.090 2512.700 2.700 ;
- RECT 2514.420 0.090 2522.220 2.700 ;
- RECT 2523.940 0.090 2531.740 2.700 ;
- RECT 2533.460 0.090 2541.260 2.700 ;
- RECT 2542.980 0.090 2550.780 2.700 ;
- RECT 2552.500 0.090 2560.300 2.700 ;
- RECT 2562.020 0.090 2569.820 2.700 ;
- RECT 2571.540 0.090 2579.340 2.700 ;
- RECT 2581.060 0.090 2588.860 2.700 ;
- RECT 2590.580 0.090 2598.380 2.700 ;
- RECT 2600.100 0.090 2607.900 2.700 ;
- RECT 2609.620 0.090 2617.420 2.700 ;
- RECT 2619.140 0.090 2626.940 2.700 ;
- RECT 2628.660 0.090 2636.460 2.700 ;
- RECT 2638.180 0.090 2645.980 2.700 ;
- RECT 2647.700 0.090 2655.500 2.700 ;
- RECT 2657.220 0.090 2665.020 2.700 ;
- RECT 2666.740 0.090 2674.540 2.700 ;
- RECT 2676.260 0.090 2684.060 2.700 ;
- RECT 2685.780 0.090 2693.580 2.700 ;
- RECT 2695.300 0.090 2703.100 2.700 ;
- RECT 2704.820 0.090 2712.620 2.700 ;
- RECT 2714.340 0.090 2722.140 2.700 ;
- RECT 2723.860 0.090 2731.660 2.700 ;
- RECT 2733.380 0.090 2741.180 2.700 ;
- RECT 2742.900 0.090 2750.700 2.700 ;
- RECT 2752.420 0.090 2760.220 2.700 ;
- RECT 2761.940 0.090 2769.740 2.700 ;
- RECT 2771.460 0.090 2779.260 2.700 ;
- RECT 2780.980 0.090 2788.780 2.700 ;
- RECT 2790.500 0.090 2798.300 2.700 ;
- RECT 2800.020 0.090 2807.820 2.700 ;
- RECT 2809.540 0.090 2817.340 2.700 ;
- RECT 2819.060 0.090 2826.860 2.700 ;
- RECT 2828.580 0.090 2836.380 2.700 ;
- RECT 2838.100 0.090 2845.900 2.700 ;
- RECT 2847.620 0.090 2855.420 2.700 ;
- RECT 2857.140 0.090 2864.940 2.700 ;
- RECT 2866.660 0.090 2874.460 2.700 ;
- RECT 2876.180 0.090 2883.980 2.700 ;
- RECT 2885.700 0.090 2893.500 2.700 ;
- RECT 2895.220 0.090 2903.020 2.700 ;
- RECT 2904.740 0.090 2912.540 2.700 ;
- RECT 2914.260 0.090 2922.060 2.700 ;
- RECT 2923.780 0.090 2931.580 2.700 ;
- RECT 2933.300 0.090 2990.820 2.700 ;
+ RECT 2942.260 2997.300 2979.060 2998.100 ;
+ RECT 20.860 2.700 2979.060 2997.300 ;
+ RECT 20.860 1.820 66.060 2.700 ;
+ RECT 67.780 1.820 75.580 2.700 ;
+ RECT 77.300 1.820 85.100 2.700 ;
+ RECT 86.820 1.820 94.620 2.700 ;
+ RECT 96.340 1.820 104.140 2.700 ;
+ RECT 105.860 1.820 113.660 2.700 ;
+ RECT 115.380 1.820 123.180 2.700 ;
+ RECT 124.900 1.820 132.700 2.700 ;
+ RECT 134.420 1.820 142.220 2.700 ;
+ RECT 143.940 1.820 151.740 2.700 ;
+ RECT 153.460 1.820 161.260 2.700 ;
+ RECT 162.980 1.820 170.780 2.700 ;
+ RECT 172.500 1.820 180.300 2.700 ;
+ RECT 182.020 1.820 189.820 2.700 ;
+ RECT 191.540 1.820 199.340 2.700 ;
+ RECT 201.060 1.820 208.860 2.700 ;
+ RECT 210.580 1.820 218.380 2.700 ;
+ RECT 220.100 1.820 227.900 2.700 ;
+ RECT 229.620 1.820 237.420 2.700 ;
+ RECT 239.140 1.820 246.940 2.700 ;
+ RECT 248.660 1.820 256.460 2.700 ;
+ RECT 258.180 1.820 265.980 2.700 ;
+ RECT 267.700 1.820 275.500 2.700 ;
+ RECT 277.220 1.820 285.020 2.700 ;
+ RECT 286.740 1.820 294.540 2.700 ;
+ RECT 296.260 1.820 304.060 2.700 ;
+ RECT 305.780 1.820 313.580 2.700 ;
+ RECT 315.300 1.820 323.100 2.700 ;
+ RECT 324.820 1.820 332.620 2.700 ;
+ RECT 334.340 1.820 342.140 2.700 ;
+ RECT 343.860 1.820 351.660 2.700 ;
+ RECT 353.380 1.820 361.180 2.700 ;
+ RECT 362.900 1.820 370.700 2.700 ;
+ RECT 372.420 1.820 380.220 2.700 ;
+ RECT 381.940 1.820 389.740 2.700 ;
+ RECT 391.460 1.820 399.260 2.700 ;
+ RECT 400.980 1.820 408.780 2.700 ;
+ RECT 410.500 1.820 418.300 2.700 ;
+ RECT 420.020 1.820 427.820 2.700 ;
+ RECT 429.540 1.820 437.340 2.700 ;
+ RECT 439.060 1.820 446.860 2.700 ;
+ RECT 448.580 1.820 456.380 2.700 ;
+ RECT 458.100 1.820 465.900 2.700 ;
+ RECT 467.620 1.820 475.420 2.700 ;
+ RECT 477.140 1.820 484.940 2.700 ;
+ RECT 486.660 1.820 494.460 2.700 ;
+ RECT 496.180 1.820 503.980 2.700 ;
+ RECT 505.700 1.820 513.500 2.700 ;
+ RECT 515.220 1.820 523.020 2.700 ;
+ RECT 524.740 1.820 532.540 2.700 ;
+ RECT 534.260 1.820 542.060 2.700 ;
+ RECT 543.780 1.820 551.580 2.700 ;
+ RECT 553.300 1.820 561.100 2.700 ;
+ RECT 562.820 1.820 570.620 2.700 ;
+ RECT 572.340 1.820 580.140 2.700 ;
+ RECT 581.860 1.820 589.660 2.700 ;
+ RECT 591.380 1.820 599.180 2.700 ;
+ RECT 600.900 1.820 608.700 2.700 ;
+ RECT 610.420 1.820 618.220 2.700 ;
+ RECT 619.940 1.820 627.740 2.700 ;
+ RECT 629.460 1.820 637.260 2.700 ;
+ RECT 638.980 1.820 646.780 2.700 ;
+ RECT 648.500 1.820 656.300 2.700 ;
+ RECT 658.020 1.820 665.820 2.700 ;
+ RECT 667.540 1.820 675.340 2.700 ;
+ RECT 677.060 1.820 684.860 2.700 ;
+ RECT 686.580 1.820 694.380 2.700 ;
+ RECT 696.100 1.820 703.900 2.700 ;
+ RECT 705.620 1.820 713.420 2.700 ;
+ RECT 715.140 1.820 722.940 2.700 ;
+ RECT 724.660 1.820 732.460 2.700 ;
+ RECT 734.180 1.820 741.980 2.700 ;
+ RECT 743.700 1.820 751.500 2.700 ;
+ RECT 753.220 1.820 761.020 2.700 ;
+ RECT 762.740 1.820 770.540 2.700 ;
+ RECT 772.260 1.820 780.060 2.700 ;
+ RECT 781.780 1.820 789.580 2.700 ;
+ RECT 791.300 1.820 799.100 2.700 ;
+ RECT 800.820 1.820 808.620 2.700 ;
+ RECT 810.340 1.820 818.140 2.700 ;
+ RECT 819.860 1.820 827.660 2.700 ;
+ RECT 829.380 1.820 837.180 2.700 ;
+ RECT 838.900 1.820 846.700 2.700 ;
+ RECT 848.420 1.820 856.220 2.700 ;
+ RECT 857.940 1.820 865.740 2.700 ;
+ RECT 867.460 1.820 875.260 2.700 ;
+ RECT 876.980 1.820 884.780 2.700 ;
+ RECT 886.500 1.820 894.300 2.700 ;
+ RECT 896.020 1.820 903.820 2.700 ;
+ RECT 905.540 1.820 913.340 2.700 ;
+ RECT 915.060 1.820 922.860 2.700 ;
+ RECT 924.580 1.820 932.380 2.700 ;
+ RECT 934.100 1.820 941.900 2.700 ;
+ RECT 943.620 1.820 951.420 2.700 ;
+ RECT 953.140 1.820 960.940 2.700 ;
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+ RECT 1048.340 1.820 1056.140 2.700 ;
+ RECT 1057.860 1.820 1065.660 2.700 ;
+ RECT 1067.380 1.820 1075.180 2.700 ;
+ RECT 1076.900 1.820 1084.700 2.700 ;
+ RECT 1086.420 1.820 1094.220 2.700 ;
+ RECT 1095.940 1.820 1103.740 2.700 ;
+ RECT 1105.460 1.820 1113.260 2.700 ;
+ RECT 1114.980 1.820 1122.780 2.700 ;
+ RECT 1124.500 1.820 1132.300 2.700 ;
+ RECT 1134.020 1.820 1141.820 2.700 ;
+ RECT 1143.540 1.820 1151.340 2.700 ;
+ RECT 1153.060 1.820 1160.860 2.700 ;
+ RECT 1162.580 1.820 1170.380 2.700 ;
+ RECT 1172.100 1.820 1179.900 2.700 ;
+ RECT 1181.620 1.820 1189.420 2.700 ;
+ RECT 1191.140 1.820 1198.940 2.700 ;
+ RECT 1200.660 1.820 1208.460 2.700 ;
+ RECT 1210.180 1.820 1217.980 2.700 ;
+ RECT 1219.700 1.820 1227.500 2.700 ;
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+ RECT 1238.740 1.820 1246.540 2.700 ;
+ RECT 1248.260 1.820 1256.060 2.700 ;
+ RECT 1257.780 1.820 1265.580 2.700 ;
+ RECT 1267.300 1.820 1275.100 2.700 ;
+ RECT 1276.820 1.820 1284.620 2.700 ;
+ RECT 1286.340 1.820 1294.140 2.700 ;
+ RECT 1295.860 1.820 1303.660 2.700 ;
+ RECT 1305.380 1.820 1313.180 2.700 ;
+ RECT 1314.900 1.820 1322.700 2.700 ;
+ RECT 1324.420 1.820 1332.220 2.700 ;
+ RECT 1333.940 1.820 1341.740 2.700 ;
+ RECT 1343.460 1.820 1351.260 2.700 ;
+ RECT 1352.980 1.820 1360.780 2.700 ;
+ RECT 1362.500 1.820 1370.300 2.700 ;
+ RECT 1372.020 1.820 1379.820 2.700 ;
+ RECT 1381.540 1.820 1389.340 2.700 ;
+ RECT 1391.060 1.820 1398.860 2.700 ;
+ RECT 1400.580 1.820 1408.380 2.700 ;
+ RECT 1410.100 1.820 1417.900 2.700 ;
+ RECT 1419.620 1.820 1427.420 2.700 ;
+ RECT 1429.140 1.820 1436.940 2.700 ;
+ RECT 1438.660 1.820 1446.460 2.700 ;
+ RECT 1448.180 1.820 1455.980 2.700 ;
+ RECT 1457.700 1.820 1465.500 2.700 ;
+ RECT 1467.220 1.820 1475.020 2.700 ;
+ RECT 1476.740 1.820 1484.540 2.700 ;
+ RECT 1486.260 1.820 1494.060 2.700 ;
+ RECT 1495.780 1.820 1503.580 2.700 ;
+ RECT 1505.300 1.820 1513.100 2.700 ;
+ RECT 1514.820 1.820 1522.620 2.700 ;
+ RECT 1524.340 1.820 1532.140 2.700 ;
+ RECT 1533.860 1.820 1541.660 2.700 ;
+ RECT 1543.380 1.820 1551.180 2.700 ;
+ RECT 1552.900 1.820 1560.700 2.700 ;
+ RECT 1562.420 1.820 1570.220 2.700 ;
+ RECT 1571.940 1.820 1579.740 2.700 ;
+ RECT 1581.460 1.820 1589.260 2.700 ;
+ RECT 1590.980 1.820 1598.780 2.700 ;
+ RECT 1600.500 1.820 1608.300 2.700 ;
+ RECT 1610.020 1.820 1617.820 2.700 ;
+ RECT 1619.540 1.820 1627.340 2.700 ;
+ RECT 1629.060 1.820 1636.860 2.700 ;
+ RECT 1638.580 1.820 1646.380 2.700 ;
+ RECT 1648.100 1.820 1655.900 2.700 ;
+ RECT 1657.620 1.820 1665.420 2.700 ;
+ RECT 1667.140 1.820 1674.940 2.700 ;
+ RECT 1676.660 1.820 1684.460 2.700 ;
+ RECT 1686.180 1.820 1693.980 2.700 ;
+ RECT 1695.700 1.820 1703.500 2.700 ;
+ RECT 1705.220 1.820 1713.020 2.700 ;
+ RECT 1714.740 1.820 1722.540 2.700 ;
+ RECT 1724.260 1.820 1732.060 2.700 ;
+ RECT 1733.780 1.820 1741.580 2.700 ;
+ RECT 1743.300 1.820 1751.100 2.700 ;
+ RECT 1752.820 1.820 1760.620 2.700 ;
+ RECT 1762.340 1.820 1770.140 2.700 ;
+ RECT 1771.860 1.820 1779.660 2.700 ;
+ RECT 1781.380 1.820 1789.180 2.700 ;
+ RECT 1790.900 1.820 1798.700 2.700 ;
+ RECT 1800.420 1.820 1808.220 2.700 ;
+ RECT 1809.940 1.820 1817.740 2.700 ;
+ RECT 1819.460 1.820 1827.260 2.700 ;
+ RECT 1828.980 1.820 1836.780 2.700 ;
+ RECT 1838.500 1.820 1846.300 2.700 ;
+ RECT 1848.020 1.820 1855.820 2.700 ;
+ RECT 1857.540 1.820 1865.340 2.700 ;
+ RECT 1867.060 1.820 1874.860 2.700 ;
+ RECT 1876.580 1.820 1884.380 2.700 ;
+ RECT 1886.100 1.820 1893.900 2.700 ;
+ RECT 1895.620 1.820 1903.420 2.700 ;
+ RECT 1905.140 1.820 1912.940 2.700 ;
+ RECT 1914.660 1.820 1922.460 2.700 ;
+ RECT 1924.180 1.820 1931.980 2.700 ;
+ RECT 1933.700 1.820 1941.500 2.700 ;
+ RECT 1943.220 1.820 1951.020 2.700 ;
+ RECT 1952.740 1.820 1960.540 2.700 ;
+ RECT 1962.260 1.820 1970.060 2.700 ;
+ RECT 1971.780 1.820 1979.580 2.700 ;
+ RECT 1981.300 1.820 1989.100 2.700 ;
+ RECT 1990.820 1.820 1998.620 2.700 ;
+ RECT 2000.340 1.820 2008.140 2.700 ;
+ RECT 2009.860 1.820 2017.660 2.700 ;
+ RECT 2019.380 1.820 2027.180 2.700 ;
+ RECT 2028.900 1.820 2036.700 2.700 ;
+ RECT 2038.420 1.820 2046.220 2.700 ;
+ RECT 2047.940 1.820 2055.740 2.700 ;
+ RECT 2057.460 1.820 2065.260 2.700 ;
+ RECT 2066.980 1.820 2074.780 2.700 ;
+ RECT 2076.500 1.820 2084.300 2.700 ;
+ RECT 2086.020 1.820 2093.820 2.700 ;
+ RECT 2095.540 1.820 2103.340 2.700 ;
+ RECT 2105.060 1.820 2112.860 2.700 ;
+ RECT 2114.580 1.820 2122.380 2.700 ;
+ RECT 2124.100 1.820 2131.900 2.700 ;
+ RECT 2133.620 1.820 2141.420 2.700 ;
+ RECT 2143.140 1.820 2150.940 2.700 ;
+ RECT 2152.660 1.820 2160.460 2.700 ;
+ RECT 2162.180 1.820 2169.980 2.700 ;
+ RECT 2171.700 1.820 2179.500 2.700 ;
+ RECT 2181.220 1.820 2189.020 2.700 ;
+ RECT 2190.740 1.820 2198.540 2.700 ;
+ RECT 2200.260 1.820 2208.060 2.700 ;
+ RECT 2209.780 1.820 2217.580 2.700 ;
+ RECT 2219.300 1.820 2227.100 2.700 ;
+ RECT 2228.820 1.820 2236.620 2.700 ;
+ RECT 2238.340 1.820 2246.140 2.700 ;
+ RECT 2247.860 1.820 2255.660 2.700 ;
+ RECT 2257.380 1.820 2265.180 2.700 ;
+ RECT 2266.900 1.820 2274.700 2.700 ;
+ RECT 2276.420 1.820 2284.220 2.700 ;
+ RECT 2285.940 1.820 2293.740 2.700 ;
+ RECT 2295.460 1.820 2303.260 2.700 ;
+ RECT 2304.980 1.820 2312.780 2.700 ;
+ RECT 2314.500 1.820 2322.300 2.700 ;
+ RECT 2324.020 1.820 2331.820 2.700 ;
+ RECT 2333.540 1.820 2341.340 2.700 ;
+ RECT 2343.060 1.820 2350.860 2.700 ;
+ RECT 2352.580 1.820 2360.380 2.700 ;
+ RECT 2362.100 1.820 2369.900 2.700 ;
+ RECT 2371.620 1.820 2379.420 2.700 ;
+ RECT 2381.140 1.820 2388.940 2.700 ;
+ RECT 2390.660 1.820 2398.460 2.700 ;
+ RECT 2400.180 1.820 2407.980 2.700 ;
+ RECT 2409.700 1.820 2417.500 2.700 ;
+ RECT 2419.220 1.820 2427.020 2.700 ;
+ RECT 2428.740 1.820 2436.540 2.700 ;
+ RECT 2438.260 1.820 2446.060 2.700 ;
+ RECT 2447.780 1.820 2455.580 2.700 ;
+ RECT 2457.300 1.820 2465.100 2.700 ;
+ RECT 2466.820 1.820 2474.620 2.700 ;
+ RECT 2476.340 1.820 2484.140 2.700 ;
+ RECT 2485.860 1.820 2493.660 2.700 ;
+ RECT 2495.380 1.820 2503.180 2.700 ;
+ RECT 2504.900 1.820 2512.700 2.700 ;
+ RECT 2514.420 1.820 2522.220 2.700 ;
+ RECT 2523.940 1.820 2531.740 2.700 ;
+ RECT 2533.460 1.820 2541.260 2.700 ;
+ RECT 2542.980 1.820 2550.780 2.700 ;
+ RECT 2552.500 1.820 2560.300 2.700 ;
+ RECT 2562.020 1.820 2569.820 2.700 ;
+ RECT 2571.540 1.820 2579.340 2.700 ;
+ RECT 2581.060 1.820 2588.860 2.700 ;
+ RECT 2590.580 1.820 2598.380 2.700 ;
+ RECT 2600.100 1.820 2607.900 2.700 ;
+ RECT 2609.620 1.820 2617.420 2.700 ;
+ RECT 2619.140 1.820 2626.940 2.700 ;
+ RECT 2628.660 1.820 2636.460 2.700 ;
+ RECT 2638.180 1.820 2645.980 2.700 ;
+ RECT 2647.700 1.820 2655.500 2.700 ;
+ RECT 2657.220 1.820 2665.020 2.700 ;
+ RECT 2666.740 1.820 2674.540 2.700 ;
+ RECT 2676.260 1.820 2684.060 2.700 ;
+ RECT 2685.780 1.820 2693.580 2.700 ;
+ RECT 2695.300 1.820 2703.100 2.700 ;
+ RECT 2704.820 1.820 2712.620 2.700 ;
+ RECT 2714.340 1.820 2722.140 2.700 ;
+ RECT 2723.860 1.820 2731.660 2.700 ;
+ RECT 2733.380 1.820 2741.180 2.700 ;
+ RECT 2742.900 1.820 2750.700 2.700 ;
+ RECT 2752.420 1.820 2760.220 2.700 ;
+ RECT 2761.940 1.820 2769.740 2.700 ;
+ RECT 2771.460 1.820 2779.260 2.700 ;
+ RECT 2780.980 1.820 2788.780 2.700 ;
+ RECT 2790.500 1.820 2798.300 2.700 ;
+ RECT 2800.020 1.820 2807.820 2.700 ;
+ RECT 2809.540 1.820 2817.340 2.700 ;
+ RECT 2819.060 1.820 2826.860 2.700 ;
+ RECT 2828.580 1.820 2836.380 2.700 ;
+ RECT 2838.100 1.820 2845.900 2.700 ;
+ RECT 2847.620 1.820 2855.420 2.700 ;
+ RECT 2857.140 1.820 2864.940 2.700 ;
+ RECT 2866.660 1.820 2874.460 2.700 ;
+ RECT 2876.180 1.820 2883.980 2.700 ;
+ RECT 2885.700 1.820 2893.500 2.700 ;
+ RECT 2895.220 1.820 2903.020 2.700 ;
+ RECT 2904.740 1.820 2912.540 2.700 ;
+ RECT 2914.260 1.820 2922.060 2.700 ;
+ RECT 2923.780 1.820 2931.580 2.700 ;
+ RECT 2933.300 1.820 2979.060 2.700 ;
LAYER Metal3 ;
- RECT 1.820 2966.900 2998.100 2990.820 ;
+ RECT 1.820 2966.900 2998.100 2979.060 ;
RECT 1.820 2965.180 2997.300 2966.900 ;
RECT 1.820 2958.500 2998.100 2965.180 ;
RECT 2.700 2956.780 2998.100 2958.500 ;
@@ -4455,45 +4427,21 @@
RECT 1.820 42.580 2998.100 99.660 ;
RECT 2.700 40.860 2998.100 42.580 ;
RECT 1.820 34.740 2998.100 40.860 ;
- RECT 1.820 33.020 2997.300 34.740 ;
- RECT 1.820 0.140 2998.100 33.020 ;
+ RECT 1.820 33.740 2997.300 34.740 ;
LAYER Metal4 ;
- RECT 609.740 21.930 654.990 1441.910 ;
- RECT 658.690 21.930 673.590 1441.910 ;
- RECT 677.290 21.930 744.990 1441.910 ;
- RECT 748.690 1439.360 763.590 1441.910 ;
- RECT 767.290 1439.360 834.990 1441.910 ;
- RECT 748.690 850.400 834.990 1439.360 ;
- RECT 748.690 21.930 763.590 850.400 ;
- RECT 767.290 21.930 834.990 850.400 ;
- RECT 838.690 21.930 853.590 1441.910 ;
- RECT 857.290 1436.170 924.990 1441.910 ;
- RECT 928.690 1436.170 943.590 1441.910 ;
- RECT 947.290 1436.170 1014.990 1441.910 ;
- RECT 1018.690 1436.170 1033.590 1441.910 ;
- RECT 1037.290 1436.170 1104.990 1441.910 ;
- RECT 1108.690 1436.170 1123.590 1441.910 ;
- RECT 1127.290 1436.170 1194.990 1441.910 ;
- RECT 1198.690 1436.170 1213.590 1441.910 ;
- RECT 1217.290 1436.170 1284.990 1441.910 ;
- RECT 1288.690 1436.170 1303.590 1441.910 ;
- RECT 857.290 849.670 1303.590 1436.170 ;
- RECT 857.290 21.930 924.990 849.670 ;
- RECT 928.690 21.930 943.590 849.670 ;
- RECT 947.290 21.930 1014.990 849.670 ;
- RECT 1018.690 21.930 1033.590 849.670 ;
- RECT 1037.290 21.930 1104.990 849.670 ;
- RECT 1108.690 21.930 1123.590 849.670 ;
- RECT 1127.290 21.930 1194.990 849.670 ;
- RECT 1198.690 21.930 1213.590 849.670 ;
- RECT 1217.290 21.930 1284.990 849.670 ;
- RECT 1288.690 21.930 1303.590 849.670 ;
- RECT 1307.290 1439.360 1374.990 1441.910 ;
- RECT 1378.690 1439.360 1393.590 1441.910 ;
- RECT 1307.290 850.400 1393.590 1439.360 ;
- RECT 1307.290 21.930 1374.990 850.400 ;
- RECT 1378.690 21.930 1393.590 850.400 ;
- RECT 1397.290 21.930 1456.140 1441.910 ;
+ RECT 590.380 1072.730 654.990 1127.540 ;
+ RECT 658.690 1072.730 673.590 1127.540 ;
+ RECT 677.290 1072.730 744.990 1127.540 ;
+ RECT 748.690 1072.730 834.990 1127.540 ;
+ RECT 590.380 941.510 834.990 1072.730 ;
+ RECT 590.380 830.570 654.990 941.510 ;
+ RECT 658.690 830.570 673.590 941.510 ;
+ RECT 677.290 830.570 744.990 941.510 ;
+ RECT 748.690 850.400 834.990 941.510 ;
+ RECT 748.690 830.570 763.590 850.400 ;
+ RECT 767.290 830.570 834.990 850.400 ;
+ RECT 838.690 830.570 853.590 1127.540 ;
+ RECT 857.290 830.570 890.260 1127.540 ;
END
END user_project_wrapper
END LIBRARY
diff --git a/lef/wrapped_vga_clock.lef b/lef/wrapped_vga_clock.lef
new file mode 100644
index 0000000..fc21185
--- /dev/null
+++ b/lef/wrapped_vga_clock.lef
@@ -0,0 +1,1093 @@
+VERSION 5.7 ;
+ NOWIREEXTENSIONATPIN ON ;
+ DIVIDERCHAR "/" ;
+ BUSBITCHARS "[]" ;
+MACRO wrapped_vga_clock
+ CLASS BLOCK ;
+ FOREIGN wrapped_vga_clock ;
+ ORIGIN 0.000 0.000 ;
+ SIZE 300.000 BY 300.000 ;
+ PIN io_in[0]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal3 ;
+ RECT 296.000 288.680 299.000 289.800 ;
+ END
+ END io_in[0]
+ PIN io_in[10]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal3 ;
+ RECT 296.000 70.280 299.000 71.400 ;
+ END
+ END io_in[10]
+ PIN io_in[11]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 29.960 296.000 31.080 299.000 ;
+ END
+ END io_in[11]
+ PIN io_in[12]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal3 ;
+ RECT 1.000 164.360 4.000 165.480 ;
+ END
+ END io_in[12]
+ PIN io_in[13]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 268.520 296.000 269.640 299.000 ;
+ END
+ END io_in[13]
+ PIN io_in[14]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 218.120 296.000 219.240 299.000 ;
+ END
+ END io_in[14]
+ PIN io_in[15]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal3 ;
+ RECT 1.000 184.520 4.000 185.640 ;
+ END
+ END io_in[15]
+ PIN io_in[16]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal3 ;
+ RECT 1.000 50.120 4.000 51.240 ;
+ END
+ END io_in[16]
+ PIN io_in[17]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 103.880 296.000 105.000 299.000 ;
+ END
+ END io_in[17]
+ PIN io_in[18]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 80.360 1.000 81.480 4.000 ;
+ END
+ END io_in[18]
+ PIN io_in[19]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal3 ;
+ RECT 1.000 40.040 4.000 41.160 ;
+ END
+ END io_in[19]
+ PIN io_in[1]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal3 ;
+ RECT 296.000 268.520 299.000 269.640 ;
+ END
+ END io_in[1]
+ PIN io_in[20]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal3 ;
+ RECT 296.000 9.800 299.000 10.920 ;
+ END
+ END io_in[20]
+ PIN io_in[21]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 258.440 296.000 259.560 299.000 ;
+ END
+ END io_in[21]
+ PIN io_in[22]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal3 ;
+ RECT 1.000 208.040 4.000 209.160 ;
+ END
+ END io_in[22]
+ PIN io_in[23]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal3 ;
+ RECT 1.000 268.520 4.000 269.640 ;
+ END
+ END io_in[23]
+ PIN io_in[24]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal3 ;
+ RECT 296.000 134.120 299.000 135.240 ;
+ END
+ END io_in[24]
+ PIN io_in[25]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal3 ;
+ RECT 1.000 29.960 4.000 31.080 ;
+ END
+ END io_in[25]
+ PIN io_in[26]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal3 ;
+ RECT 1.000 278.600 4.000 279.720 ;
+ END
+ END io_in[26]
+ PIN io_in[27]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 144.200 296.000 145.320 299.000 ;
+ END
+ END io_in[27]
+ PIN io_in[28]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal3 ;
+ RECT 296.000 278.600 299.000 279.720 ;
+ END
+ END io_in[28]
+ PIN io_in[29]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 288.680 1.000 289.800 4.000 ;
+ END
+ END io_in[29]
+ PIN io_in[2]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal3 ;
+ RECT 296.000 90.440 299.000 91.560 ;
+ END
+ END io_in[2]
+ PIN io_in[30]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 134.120 296.000 135.240 299.000 ;
+ END
+ END io_in[30]
+ PIN io_in[31]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 184.520 1.000 185.640 4.000 ;
+ END
+ END io_in[31]
+ PIN io_in[32]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal3 ;
+ RECT 296.000 154.280 299.000 155.400 ;
+ END
+ END io_in[32]
+ PIN io_in[33]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal3 ;
+ RECT 1.000 174.440 4.000 175.560 ;
+ END
+ END io_in[33]
+ PIN io_in[34]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 70.280 1.000 71.400 4.000 ;
+ END
+ END io_in[34]
+ PIN io_in[35]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 113.960 1.000 115.080 4.000 ;
+ END
+ END io_in[35]
+ PIN io_in[36]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal3 ;
+ RECT 296.000 29.960 299.000 31.080 ;
+ END
+ END io_in[36]
+ PIN io_in[37]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal3 ;
+ RECT 1.000 228.200 4.000 229.320 ;
+ END
+ END io_in[37]
+ PIN io_in[3]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 90.440 296.000 91.560 299.000 ;
+ END
+ END io_in[3]
+ PIN io_in[4]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal3 ;
+ RECT 296.000 103.880 299.000 105.000 ;
+ END
+ END io_in[4]
+ PIN io_in[5]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal3 ;
+ RECT 296.000 164.360 299.000 165.480 ;
+ END
+ END io_in[5]
+ PIN io_in[6]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 164.360 296.000 165.480 299.000 ;
+ END
+ END io_in[6]
+ PIN io_in[7]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal3 ;
+ RECT 296.000 124.040 299.000 125.160 ;
+ END
+ END io_in[7]
+ PIN io_in[8]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 174.440 296.000 175.560 299.000 ;
+ END
+ END io_in[8]
+ PIN io_in[9]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 194.600 296.000 195.720 299.000 ;
+ END
+ END io_in[9]
+ PIN io_oeb[0]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 238.280 296.000 239.400 299.000 ;
+ END
+ END io_oeb[0]
+ PIN io_oeb[10]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 298.760 296.000 299.880 299.000 ;
+ END
+ END io_oeb[10]
+ PIN io_oeb[11]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal3 ;
+ RECT 296.000 248.360 299.000 249.480 ;
+ END
+ END io_oeb[11]
+ PIN io_oeb[12]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 40.040 1.000 41.160 4.000 ;
+ END
+ END io_oeb[12]
+ PIN io_oeb[13]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 50.120 296.000 51.240 299.000 ;
+ END
+ END io_oeb[13]
+ PIN io_oeb[14]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 134.120 1.000 135.240 4.000 ;
+ END
+ END io_oeb[14]
+ PIN io_oeb[15]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 174.440 1.000 175.560 4.000 ;
+ END
+ END io_oeb[15]
+ PIN io_oeb[16]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal3 ;
+ RECT 296.000 258.440 299.000 259.560 ;
+ END
+ END io_oeb[16]
+ PIN io_oeb[17]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 268.520 1.000 269.640 4.000 ;
+ END
+ END io_oeb[17]
+ PIN io_oeb[18]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal3 ;
+ RECT 296.000 194.600 299.000 195.720 ;
+ END
+ END io_oeb[18]
+ PIN io_oeb[19]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 124.040 296.000 125.160 299.000 ;
+ END
+ END io_oeb[19]
+ PIN io_oeb[1]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal3 ;
+ RECT 1.000 144.200 4.000 145.320 ;
+ END
+ END io_oeb[1]
+ PIN io_oeb[20]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 70.280 296.000 71.400 299.000 ;
+ END
+ END io_oeb[20]
+ PIN io_oeb[21]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 154.280 296.000 155.400 299.000 ;
+ END
+ END io_oeb[21]
+ PIN io_oeb[22]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 238.280 1.000 239.400 4.000 ;
+ END
+ END io_oeb[22]
+ PIN io_oeb[23]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 90.440 1.000 91.560 4.000 ;
+ END
+ END io_oeb[23]
+ PIN io_oeb[24]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal3 ;
+ RECT 296.000 80.360 299.000 81.480 ;
+ END
+ END io_oeb[24]
+ PIN io_oeb[25]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 80.360 296.000 81.480 299.000 ;
+ END
+ END io_oeb[25]
+ PIN io_oeb[26]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal3 ;
+ RECT 296.000 208.040 299.000 209.160 ;
+ END
+ END io_oeb[26]
+ PIN io_oeb[27]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 19.880 1.000 21.000 4.000 ;
+ END
+ END io_oeb[27]
+ PIN io_oeb[28]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 278.600 1.000 279.720 4.000 ;
+ END
+ END io_oeb[28]
+ PIN io_oeb[29]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal3 ;
+ RECT 296.000 60.200 299.000 61.320 ;
+ END
+ END io_oeb[29]
+ PIN io_oeb[2]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 288.680 296.000 289.800 299.000 ;
+ END
+ END io_oeb[2]
+ PIN io_oeb[30]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal3 ;
+ RECT 1.000 248.360 4.000 249.480 ;
+ END
+ END io_oeb[30]
+ PIN io_oeb[31]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 248.360 1.000 249.480 4.000 ;
+ END
+ END io_oeb[31]
+ PIN io_oeb[32]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 124.040 1.000 125.160 4.000 ;
+ END
+ END io_oeb[32]
+ PIN io_oeb[33]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal3 ;
+ RECT 1.000 238.280 4.000 239.400 ;
+ END
+ END io_oeb[33]
+ PIN io_oeb[34]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal3 ;
+ RECT 296.000 228.200 299.000 229.320 ;
+ END
+ END io_oeb[34]
+ PIN io_oeb[35]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal3 ;
+ RECT 1.000 134.120 4.000 135.240 ;
+ END
+ END io_oeb[35]
+ PIN io_oeb[36]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal3 ;
+ RECT 296.000 19.880 299.000 21.000 ;
+ END
+ END io_oeb[36]
+ PIN io_oeb[37]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal3 ;
+ RECT 1.000 298.760 4.000 299.880 ;
+ END
+ END io_oeb[37]
+ PIN io_oeb[3]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 40.040 296.000 41.160 299.000 ;
+ END
+ END io_oeb[3]
+ PIN io_oeb[4]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal3 ;
+ RECT 1.000 194.600 4.000 195.720 ;
+ END
+ END io_oeb[4]
+ PIN io_oeb[5]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 218.120 1.000 219.240 4.000 ;
+ END
+ END io_oeb[5]
+ PIN io_oeb[6]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 29.960 1.000 31.080 4.000 ;
+ END
+ END io_oeb[6]
+ PIN io_oeb[7]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal3 ;
+ RECT 1.000 124.040 4.000 125.160 ;
+ END
+ END io_oeb[7]
+ PIN io_oeb[8]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal3 ;
+ RECT 296.000 -0.280 299.000 0.840 ;
+ END
+ END io_oeb[8]
+ PIN io_oeb[9]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal3 ;
+ RECT 296.000 174.440 299.000 175.560 ;
+ END
+ END io_oeb[9]
+ PIN io_out[0]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal3 ;
+ RECT 296.000 113.960 299.000 115.080 ;
+ END
+ END io_out[0]
+ PIN io_out[10]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 228.200 1.000 229.320 4.000 ;
+ END
+ END io_out[10]
+ PIN io_out[11]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal3 ;
+ RECT 1.000 218.120 4.000 219.240 ;
+ END
+ END io_out[11]
+ PIN io_out[12]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal3 ;
+ RECT 296.000 50.120 299.000 51.240 ;
+ END
+ END io_out[12]
+ PIN io_out[13]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal3 ;
+ RECT 1.000 154.280 4.000 155.400 ;
+ END
+ END io_out[13]
+ PIN io_out[14]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal3 ;
+ RECT 1.000 9.800 4.000 10.920 ;
+ END
+ END io_out[14]
+ PIN io_out[15]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal3 ;
+ RECT 296.000 218.120 299.000 219.240 ;
+ END
+ END io_out[15]
+ PIN io_out[16]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 258.440 1.000 259.560 4.000 ;
+ END
+ END io_out[16]
+ PIN io_out[17]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal3 ;
+ RECT 296.000 238.280 299.000 239.400 ;
+ END
+ END io_out[17]
+ PIN io_out[18]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 154.280 1.000 155.400 4.000 ;
+ END
+ END io_out[18]
+ PIN io_out[19]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal3 ;
+ RECT 1.000 60.200 4.000 61.320 ;
+ END
+ END io_out[19]
+ PIN io_out[1]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal3 ;
+ RECT 1.000 113.960 4.000 115.080 ;
+ END
+ END io_out[1]
+ PIN io_out[20]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT -0.280 1.000 0.840 4.000 ;
+ END
+ END io_out[20]
+ PIN io_out[21]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 194.600 1.000 195.720 4.000 ;
+ END
+ END io_out[21]
+ PIN io_out[22]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 19.880 296.000 21.000 299.000 ;
+ END
+ END io_out[22]
+ PIN io_out[23]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 113.960 296.000 115.080 299.000 ;
+ END
+ END io_out[23]
+ PIN io_out[24]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 208.040 296.000 209.160 299.000 ;
+ END
+ END io_out[24]
+ PIN io_out[25]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal3 ;
+ RECT 1.000 19.880 4.000 21.000 ;
+ END
+ END io_out[25]
+ PIN io_out[26]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 50.120 1.000 51.240 4.000 ;
+ END
+ END io_out[26]
+ PIN io_out[27]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 9.800 1.000 10.920 4.000 ;
+ END
+ END io_out[27]
+ PIN io_out[28]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 248.360 296.000 249.480 299.000 ;
+ END
+ END io_out[28]
+ PIN io_out[29]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 184.520 296.000 185.640 299.000 ;
+ END
+ END io_out[29]
+ PIN io_out[2]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 144.200 1.000 145.320 4.000 ;
+ END
+ END io_out[2]
+ PIN io_out[30]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 278.600 296.000 279.720 299.000 ;
+ END
+ END io_out[30]
+ PIN io_out[31]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal3 ;
+ RECT 296.000 40.040 299.000 41.160 ;
+ END
+ END io_out[31]
+ PIN io_out[32]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal3 ;
+ RECT 1.000 288.680 4.000 289.800 ;
+ END
+ END io_out[32]
+ PIN io_out[33]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal3 ;
+ RECT 1.000 103.880 4.000 105.000 ;
+ END
+ END io_out[33]
+ PIN io_out[34]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 60.200 1.000 61.320 4.000 ;
+ END
+ END io_out[34]
+ PIN io_out[35]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 103.880 1.000 105.000 4.000 ;
+ END
+ END io_out[35]
+ PIN io_out[36]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal3 ;
+ RECT 1.000 90.440 4.000 91.560 ;
+ END
+ END io_out[36]
+ PIN io_out[37]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal3 ;
+ RECT 296.000 184.520 299.000 185.640 ;
+ END
+ END io_out[37]
+ PIN io_out[3]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 164.360 1.000 165.480 4.000 ;
+ END
+ END io_out[3]
+ PIN io_out[4]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal3 ;
+ RECT 1.000 70.280 4.000 71.400 ;
+ END
+ END io_out[4]
+ PIN io_out[5]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 228.200 296.000 229.320 299.000 ;
+ END
+ END io_out[5]
+ PIN io_out[6]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 9.800 296.000 10.920 299.000 ;
+ END
+ END io_out[6]
+ PIN io_out[7]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 60.200 296.000 61.320 299.000 ;
+ END
+ END io_out[7]
+ PIN io_out[8]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal2 ;
+ RECT 208.040 1.000 209.160 4.000 ;
+ END
+ END io_out[8]
+ PIN io_out[9]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal3 ;
+ RECT 1.000 80.360 4.000 81.480 ;
+ END
+ END io_out[9]
+ PIN vdd
+ DIRECTION INOUT ;
+ USE POWER ;
+ PORT
+ LAYER Metal4 ;
+ RECT 22.240 15.380 23.840 282.540 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 175.840 15.380 177.440 282.540 ;
+ END
+ END vdd
+ PIN vss
+ DIRECTION INOUT ;
+ USE GROUND ;
+ PORT
+ LAYER Metal4 ;
+ RECT 99.040 15.380 100.640 282.540 ;
+ END
+ PORT
+ LAYER Metal4 ;
+ RECT 252.640 15.380 254.240 282.540 ;
+ END
+ END vss
+ PIN wb_clk_i
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal3 ;
+ RECT 1.000 258.440 4.000 259.560 ;
+ END
+ END wb_clk_i
+ PIN wb_rst_i
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER Metal3 ;
+ RECT 296.000 144.200 299.000 145.320 ;
+ END
+ END wb_rst_i
+ OBS
+ LAYER Metal1 ;
+ RECT 6.720 15.380 292.880 282.540 ;
+ LAYER Metal2 ;
+ RECT 0.700 299.300 298.900 299.510 ;
+ RECT 0.700 295.700 9.500 299.300 ;
+ RECT 11.220 295.700 19.580 299.300 ;
+ RECT 21.300 295.700 29.660 299.300 ;
+ RECT 31.380 295.700 39.740 299.300 ;
+ RECT 41.460 295.700 49.820 299.300 ;
+ RECT 51.540 295.700 59.900 299.300 ;
+ RECT 61.620 295.700 69.980 299.300 ;
+ RECT 71.700 295.700 80.060 299.300 ;
+ RECT 81.780 295.700 90.140 299.300 ;
+ RECT 91.860 295.700 103.580 299.300 ;
+ RECT 105.300 295.700 113.660 299.300 ;
+ RECT 115.380 295.700 123.740 299.300 ;
+ RECT 125.460 295.700 133.820 299.300 ;
+ RECT 135.540 295.700 143.900 299.300 ;
+ RECT 145.620 295.700 153.980 299.300 ;
+ RECT 155.700 295.700 164.060 299.300 ;
+ RECT 165.780 295.700 174.140 299.300 ;
+ RECT 175.860 295.700 184.220 299.300 ;
+ RECT 185.940 295.700 194.300 299.300 ;
+ RECT 196.020 295.700 207.740 299.300 ;
+ RECT 209.460 295.700 217.820 299.300 ;
+ RECT 219.540 295.700 227.900 299.300 ;
+ RECT 229.620 295.700 237.980 299.300 ;
+ RECT 239.700 295.700 248.060 299.300 ;
+ RECT 249.780 295.700 258.140 299.300 ;
+ RECT 259.860 295.700 268.220 299.300 ;
+ RECT 269.940 295.700 278.300 299.300 ;
+ RECT 280.020 295.700 288.380 299.300 ;
+ RECT 290.100 295.700 298.460 299.300 ;
+ RECT 0.700 4.300 298.900 295.700 ;
+ RECT 1.140 3.500 9.500 4.300 ;
+ RECT 11.220 3.500 19.580 4.300 ;
+ RECT 21.300 3.500 29.660 4.300 ;
+ RECT 31.380 3.500 39.740 4.300 ;
+ RECT 41.460 3.500 49.820 4.300 ;
+ RECT 51.540 3.500 59.900 4.300 ;
+ RECT 61.620 3.500 69.980 4.300 ;
+ RECT 71.700 3.500 80.060 4.300 ;
+ RECT 81.780 3.500 90.140 4.300 ;
+ RECT 91.860 3.500 103.580 4.300 ;
+ RECT 105.300 3.500 113.660 4.300 ;
+ RECT 115.380 3.500 123.740 4.300 ;
+ RECT 125.460 3.500 133.820 4.300 ;
+ RECT 135.540 3.500 143.900 4.300 ;
+ RECT 145.620 3.500 153.980 4.300 ;
+ RECT 155.700 3.500 164.060 4.300 ;
+ RECT 165.780 3.500 174.140 4.300 ;
+ RECT 175.860 3.500 184.220 4.300 ;
+ RECT 185.940 3.500 194.300 4.300 ;
+ RECT 196.020 3.500 207.740 4.300 ;
+ RECT 209.460 3.500 217.820 4.300 ;
+ RECT 219.540 3.500 227.900 4.300 ;
+ RECT 229.620 3.500 237.980 4.300 ;
+ RECT 239.700 3.500 248.060 4.300 ;
+ RECT 249.780 3.500 258.140 4.300 ;
+ RECT 259.860 3.500 268.220 4.300 ;
+ RECT 269.940 3.500 278.300 4.300 ;
+ RECT 280.020 3.500 288.380 4.300 ;
+ RECT 290.100 3.500 298.900 4.300 ;
+ LAYER Metal3 ;
+ RECT 4.300 298.460 298.950 299.460 ;
+ RECT 3.500 290.100 298.950 298.460 ;
+ RECT 4.300 288.380 295.700 290.100 ;
+ RECT 3.500 280.020 298.950 288.380 ;
+ RECT 4.300 278.300 295.700 280.020 ;
+ RECT 3.500 269.940 298.950 278.300 ;
+ RECT 4.300 268.220 295.700 269.940 ;
+ RECT 3.500 259.860 298.950 268.220 ;
+ RECT 4.300 258.140 295.700 259.860 ;
+ RECT 3.500 249.780 298.950 258.140 ;
+ RECT 4.300 248.060 295.700 249.780 ;
+ RECT 3.500 239.700 298.950 248.060 ;
+ RECT 4.300 237.980 295.700 239.700 ;
+ RECT 3.500 229.620 298.950 237.980 ;
+ RECT 4.300 227.900 295.700 229.620 ;
+ RECT 3.500 219.540 298.950 227.900 ;
+ RECT 4.300 217.820 295.700 219.540 ;
+ RECT 3.500 209.460 298.950 217.820 ;
+ RECT 4.300 207.740 295.700 209.460 ;
+ RECT 3.500 196.020 298.950 207.740 ;
+ RECT 4.300 194.300 295.700 196.020 ;
+ RECT 3.500 185.940 298.950 194.300 ;
+ RECT 4.300 184.220 295.700 185.940 ;
+ RECT 3.500 175.860 298.950 184.220 ;
+ RECT 4.300 174.140 295.700 175.860 ;
+ RECT 3.500 165.780 298.950 174.140 ;
+ RECT 4.300 164.060 295.700 165.780 ;
+ RECT 3.500 155.700 298.950 164.060 ;
+ RECT 4.300 153.980 295.700 155.700 ;
+ RECT 3.500 145.620 298.950 153.980 ;
+ RECT 4.300 143.900 295.700 145.620 ;
+ RECT 3.500 135.540 298.950 143.900 ;
+ RECT 4.300 133.820 295.700 135.540 ;
+ RECT 3.500 125.460 298.950 133.820 ;
+ RECT 4.300 123.740 295.700 125.460 ;
+ RECT 3.500 115.380 298.950 123.740 ;
+ RECT 4.300 113.660 295.700 115.380 ;
+ RECT 3.500 105.300 298.950 113.660 ;
+ RECT 4.300 103.580 295.700 105.300 ;
+ RECT 3.500 91.860 298.950 103.580 ;
+ RECT 4.300 90.140 295.700 91.860 ;
+ RECT 3.500 81.780 298.950 90.140 ;
+ RECT 4.300 80.060 295.700 81.780 ;
+ RECT 3.500 71.700 298.950 80.060 ;
+ RECT 4.300 69.980 295.700 71.700 ;
+ RECT 3.500 61.620 298.950 69.980 ;
+ RECT 4.300 59.900 295.700 61.620 ;
+ RECT 3.500 51.540 298.950 59.900 ;
+ RECT 4.300 49.820 295.700 51.540 ;
+ RECT 3.500 41.460 298.950 49.820 ;
+ RECT 4.300 39.740 295.700 41.460 ;
+ RECT 3.500 31.380 298.950 39.740 ;
+ RECT 4.300 29.660 295.700 31.380 ;
+ RECT 3.500 21.300 298.950 29.660 ;
+ RECT 4.300 19.580 295.700 21.300 ;
+ RECT 3.500 11.220 298.950 19.580 ;
+ RECT 4.300 9.500 295.700 11.220 ;
+ RECT 3.500 1.140 298.950 9.500 ;
+ RECT 3.500 0.700 295.700 1.140 ;
+ LAYER Metal4 ;
+ RECT 59.500 106.490 98.740 217.750 ;
+ RECT 100.940 106.490 175.540 217.750 ;
+ RECT 177.740 106.490 218.820 217.750 ;
+ END
+END wrapped_vga_clock
+END LIBRARY
+
diff --git a/lib/user_project_wrapper.lib b/lib/user_project_wrapper.lib
index 3c00910..2c39335 100644
--- a/lib/user_project_wrapper.lib
+++ b/lib/user_project_wrapper.lib
@@ -110,11 +110,11 @@
}
pin("wb_clk_i") {
direction : input;
- capacitance : 0.1273;
+ capacitance : 0.1039;
}
pin("wb_rst_i") {
direction : input;
- capacitance : 0.2509;
+ capacitance : 0.1357;
}
pin("wbs_ack_o") {
direction : output;
@@ -122,15 +122,15 @@
}
pin("wbs_cyc_i") {
direction : input;
- capacitance : 0.1867;
+ capacitance : 0.0000;
}
pin("wbs_stb_i") {
direction : input;
- capacitance : 0.1512;
+ capacitance : 0.0000;
}
pin("wbs_we_i") {
direction : input;
- capacitance : 0.1561;
+ capacitance : 0.0000;
}
pin("vss") {
direction : input;
@@ -146,155 +146,155 @@
capacitance : 0.0000;
pin("io_in[37]") {
direction : input;
- capacitance : 0.1843;
+ capacitance : 0.0938;
}
pin("io_in[36]") {
direction : input;
- capacitance : 0.2294;
+ capacitance : 0.1249;
}
pin("io_in[35]") {
direction : input;
- capacitance : 0.1507;
+ capacitance : 0.0577;
}
pin("io_in[34]") {
direction : input;
- capacitance : 0.4871;
+ capacitance : 0.0406;
}
pin("io_in[33]") {
direction : input;
- capacitance : 0.2661;
+ capacitance : 0.0401;
}
pin("io_in[32]") {
direction : input;
- capacitance : 0.4696;
+ capacitance : 0.1190;
}
pin("io_in[31]") {
direction : input;
- capacitance : 0.3086;
+ capacitance : 0.1653;
}
pin("io_in[30]") {
direction : input;
- capacitance : 0.0933;
+ capacitance : 0.0777;
}
pin("io_in[29]") {
direction : input;
- capacitance : 0.1237;
+ capacitance : 0.2422;
}
pin("io_in[28]") {
direction : input;
- capacitance : 0.1259;
+ capacitance : 0.3132;
}
pin("io_in[27]") {
direction : input;
- capacitance : 0.4135;
+ capacitance : 0.1241;
}
pin("io_in[26]") {
direction : input;
- capacitance : 0.1421;
+ capacitance : 0.1257;
}
pin("io_in[25]") {
direction : input;
- capacitance : 0.1674;
+ capacitance : 0.1555;
}
pin("io_in[24]") {
direction : input;
- capacitance : 0.2100;
+ capacitance : 0.3881;
}
pin("io_in[23]") {
direction : input;
- capacitance : 0.1522;
+ capacitance : 0.1404;
}
pin("io_in[22]") {
direction : input;
- capacitance : 0.1597;
+ capacitance : 0.1521;
}
pin("io_in[21]") {
direction : input;
- capacitance : 0.1096;
+ capacitance : 0.1434;
}
pin("io_in[20]") {
direction : input;
- capacitance : 0.1144;
+ capacitance : 0.1627;
}
pin("io_in[19]") {
direction : input;
- capacitance : 0.3139;
+ capacitance : 0.2440;
}
pin("io_in[18]") {
direction : input;
- capacitance : 0.3541;
+ capacitance : 0.3124;
}
pin("io_in[17]") {
direction : input;
- capacitance : 0.1857;
+ capacitance : 0.4304;
}
pin("io_in[16]") {
direction : input;
- capacitance : 0.2570;
+ capacitance : 0.7854;
}
pin("io_in[15]") {
direction : input;
- capacitance : 0.2323;
+ capacitance : 0.3058;
}
pin("io_in[14]") {
direction : input;
- capacitance : 0.2182;
+ capacitance : 0.2391;
}
pin("io_in[13]") {
direction : input;
- capacitance : 0.2138;
+ capacitance : 0.2223;
}
pin("io_in[12]") {
direction : input;
- capacitance : 0.1898;
+ capacitance : 0.2638;
}
pin("io_in[11]") {
direction : input;
- capacitance : 0.1787;
+ capacitance : 0.2113;
}
pin("io_in[10]") {
direction : input;
- capacitance : 0.1824;
+ capacitance : 0.1966;
}
pin("io_in[9]") {
direction : input;
- capacitance : 0.2989;
+ capacitance : 0.1754;
}
pin("io_in[8]") {
direction : input;
- capacitance : 0.1441;
+ capacitance : 0.1882;
}
pin("io_in[7]") {
direction : input;
- capacitance : 0.4710;
+ capacitance : 0.1549;
}
pin("io_in[6]") {
direction : input;
- capacitance : 0.3850;
+ capacitance : 0.1989;
}
pin("io_in[5]") {
direction : input;
- capacitance : 0.4559;
+ capacitance : 0.1263;
}
pin("io_in[4]") {
direction : input;
- capacitance : 0.3686;
+ capacitance : 0.1330;
}
pin("io_in[3]") {
direction : input;
- capacitance : 0.3645;
+ capacitance : 0.3405;
}
pin("io_in[2]") {
direction : input;
- capacitance : 0.5106;
+ capacitance : 0.1577;
}
pin("io_in[1]") {
direction : input;
- capacitance : 0.3712;
+ capacitance : 0.1824;
}
pin("io_in[0]") {
direction : input;
- capacitance : 0.2560;
+ capacitance : 0.1954;
}
}
bus("io_oeb") {
@@ -617,259 +617,259 @@
capacitance : 0.0000;
pin("la_data_in[63]") {
direction : input;
- capacitance : 0.3257;
+ capacitance : 0.0000;
}
pin("la_data_in[62]") {
direction : input;
- capacitance : 0.3814;
+ capacitance : 0.0000;
}
pin("la_data_in[61]") {
direction : input;
- capacitance : 0.4484;
+ capacitance : 0.0000;
}
pin("la_data_in[60]") {
direction : input;
- capacitance : 0.3756;
+ capacitance : 0.0000;
}
pin("la_data_in[59]") {
direction : input;
- capacitance : 0.3413;
+ capacitance : 0.0000;
}
pin("la_data_in[58]") {
direction : input;
- capacitance : 0.3226;
+ capacitance : 0.0000;
}
pin("la_data_in[57]") {
direction : input;
- capacitance : 0.3711;
+ capacitance : 0.0000;
}
pin("la_data_in[56]") {
direction : input;
- capacitance : 0.5478;
+ capacitance : 0.0000;
}
pin("la_data_in[55]") {
direction : input;
- capacitance : 0.2685;
+ capacitance : 0.0000;
}
pin("la_data_in[54]") {
direction : input;
- capacitance : 0.2668;
+ capacitance : 0.0000;
}
pin("la_data_in[53]") {
direction : input;
- capacitance : 0.5277;
+ capacitance : 0.0000;
}
pin("la_data_in[52]") {
direction : input;
- capacitance : 0.5632;
+ capacitance : 0.0000;
}
pin("la_data_in[51]") {
direction : input;
- capacitance : 0.5891;
+ capacitance : 0.0000;
}
pin("la_data_in[50]") {
direction : input;
- capacitance : 0.5788;
+ capacitance : 0.0000;
}
pin("la_data_in[49]") {
direction : input;
- capacitance : 0.4229;
+ capacitance : 0.0000;
}
pin("la_data_in[48]") {
direction : input;
- capacitance : 0.4712;
+ capacitance : 0.0000;
}
pin("la_data_in[47]") {
direction : input;
- capacitance : 0.5167;
+ capacitance : 0.0000;
}
pin("la_data_in[46]") {
direction : input;
- capacitance : 0.3883;
+ capacitance : 0.0000;
}
pin("la_data_in[45]") {
direction : input;
- capacitance : 0.4514;
+ capacitance : 0.0000;
}
pin("la_data_in[44]") {
direction : input;
- capacitance : 0.2603;
+ capacitance : 0.0000;
}
pin("la_data_in[43]") {
direction : input;
- capacitance : 0.5088;
+ capacitance : 0.0000;
}
pin("la_data_in[42]") {
direction : input;
- capacitance : 0.3691;
+ capacitance : 0.0000;
}
pin("la_data_in[41]") {
direction : input;
- capacitance : 0.2908;
+ capacitance : 0.0000;
}
pin("la_data_in[40]") {
direction : input;
- capacitance : 0.4555;
+ capacitance : 0.0000;
}
pin("la_data_in[39]") {
direction : input;
- capacitance : 0.3180;
+ capacitance : 0.0000;
}
pin("la_data_in[38]") {
direction : input;
- capacitance : 0.3758;
+ capacitance : 0.0000;
}
pin("la_data_in[37]") {
direction : input;
- capacitance : 0.2842;
+ capacitance : 0.0000;
}
pin("la_data_in[36]") {
direction : input;
- capacitance : 0.2897;
+ capacitance : 0.0000;
}
pin("la_data_in[35]") {
direction : input;
- capacitance : 0.3235;
+ capacitance : 0.0000;
}
pin("la_data_in[34]") {
direction : input;
- capacitance : 0.2833;
+ capacitance : 0.0000;
}
pin("la_data_in[33]") {
direction : input;
- capacitance : 0.2708;
+ capacitance : 0.0000;
}
pin("la_data_in[32]") {
direction : input;
- capacitance : 0.3616;
+ capacitance : 0.0000;
}
pin("la_data_in[31]") {
direction : input;
- capacitance : 0.3487;
+ capacitance : 0.0000;
}
pin("la_data_in[30]") {
direction : input;
- capacitance : 0.3554;
+ capacitance : 0.0000;
}
pin("la_data_in[29]") {
direction : input;
- capacitance : 0.2439;
+ capacitance : 0.0000;
}
pin("la_data_in[28]") {
direction : input;
- capacitance : 0.2320;
+ capacitance : 0.0000;
}
pin("la_data_in[27]") {
direction : input;
- capacitance : 0.3301;
+ capacitance : 0.0000;
}
pin("la_data_in[26]") {
direction : input;
- capacitance : 0.2137;
+ capacitance : 0.0000;
}
pin("la_data_in[25]") {
direction : input;
- capacitance : 0.2003;
+ capacitance : 0.0000;
}
pin("la_data_in[24]") {
direction : input;
- capacitance : 0.4306;
+ capacitance : 0.0000;
}
pin("la_data_in[23]") {
direction : input;
- capacitance : 0.2660;
+ capacitance : 0.0000;
}
pin("la_data_in[22]") {
direction : input;
- capacitance : 0.2372;
+ capacitance : 0.0000;
}
pin("la_data_in[21]") {
direction : input;
- capacitance : 0.3066;
+ capacitance : 0.0000;
}
pin("la_data_in[20]") {
direction : input;
- capacitance : 0.1891;
+ capacitance : 0.0000;
}
pin("la_data_in[19]") {
direction : input;
- capacitance : 0.2204;
+ capacitance : 0.0000;
}
pin("la_data_in[18]") {
direction : input;
- capacitance : 0.3278;
+ capacitance : 0.0000;
}
pin("la_data_in[17]") {
direction : input;
- capacitance : 0.3488;
+ capacitance : 0.0000;
}
pin("la_data_in[16]") {
direction : input;
- capacitance : 0.3207;
+ capacitance : 0.0000;
}
pin("la_data_in[15]") {
direction : input;
- capacitance : 0.1235;
+ capacitance : 0.0000;
}
pin("la_data_in[14]") {
direction : input;
- capacitance : 0.4511;
+ capacitance : 0.0000;
}
pin("la_data_in[13]") {
direction : input;
- capacitance : 0.1549;
+ capacitance : 0.0000;
}
pin("la_data_in[12]") {
direction : input;
- capacitance : 0.1364;
+ capacitance : 0.0000;
}
pin("la_data_in[11]") {
direction : input;
- capacitance : 0.3292;
+ capacitance : 0.0000;
}
pin("la_data_in[10]") {
direction : input;
- capacitance : 0.1327;
+ capacitance : 0.0000;
}
pin("la_data_in[9]") {
direction : input;
- capacitance : 0.1062;
+ capacitance : 0.0000;
}
pin("la_data_in[8]") {
direction : input;
- capacitance : 0.4163;
+ capacitance : 0.0000;
}
pin("la_data_in[7]") {
direction : input;
- capacitance : 0.3849;
+ capacitance : 0.0000;
}
pin("la_data_in[6]") {
direction : input;
- capacitance : 0.2139;
+ capacitance : 0.0000;
}
pin("la_data_in[5]") {
direction : input;
- capacitance : 0.2451;
+ capacitance : 0.0000;
}
pin("la_data_in[4]") {
direction : input;
- capacitance : 0.2458;
+ capacitance : 0.0000;
}
pin("la_data_in[3]") {
direction : input;
- capacitance : 0.0861;
+ capacitance : 0.0000;
}
pin("la_data_in[2]") {
direction : input;
- capacitance : 0.2021;
+ capacitance : 0.0000;
}
pin("la_data_in[1]") {
direction : input;
- capacitance : 0.2468;
+ capacitance : 0.0000;
}
pin("la_data_in[0]") {
direction : input;
- capacitance : 0.2522;
+ capacitance : 0.0000;
}
}
bus("la_data_out") {
@@ -1139,259 +1139,259 @@
capacitance : 0.0000;
pin("la_oenb[63]") {
direction : input;
- capacitance : 0.1666;
+ capacitance : 0.0000;
}
pin("la_oenb[62]") {
direction : input;
- capacitance : 0.6410;
+ capacitance : 0.0000;
}
pin("la_oenb[61]") {
direction : input;
- capacitance : 0.3915;
+ capacitance : 0.0000;
}
pin("la_oenb[60]") {
direction : input;
- capacitance : 0.1472;
+ capacitance : 0.0000;
}
pin("la_oenb[59]") {
direction : input;
- capacitance : 0.2868;
+ capacitance : 0.0000;
}
pin("la_oenb[58]") {
direction : input;
- capacitance : 0.6457;
+ capacitance : 0.0000;
}
pin("la_oenb[57]") {
direction : input;
- capacitance : 0.4769;
+ capacitance : 0.0000;
}
pin("la_oenb[56]") {
direction : input;
- capacitance : 0.4703;
+ capacitance : 0.0000;
}
pin("la_oenb[55]") {
direction : input;
- capacitance : 0.6107;
+ capacitance : 0.0000;
}
pin("la_oenb[54]") {
direction : input;
- capacitance : 0.7370;
+ capacitance : 0.0000;
}
pin("la_oenb[53]") {
direction : input;
- capacitance : 0.4053;
+ capacitance : 0.0000;
}
pin("la_oenb[52]") {
direction : input;
- capacitance : 0.3562;
+ capacitance : 0.0000;
}
pin("la_oenb[51]") {
direction : input;
- capacitance : 0.5767;
+ capacitance : 0.0000;
}
pin("la_oenb[50]") {
direction : input;
- capacitance : 0.5416;
+ capacitance : 0.0000;
}
pin("la_oenb[49]") {
direction : input;
- capacitance : 0.2924;
+ capacitance : 0.0000;
}
pin("la_oenb[48]") {
direction : input;
- capacitance : 0.1905;
+ capacitance : 0.0000;
}
pin("la_oenb[47]") {
direction : input;
- capacitance : 0.3684;
+ capacitance : 0.0000;
}
pin("la_oenb[46]") {
direction : input;
- capacitance : 0.5052;
+ capacitance : 0.0000;
}
pin("la_oenb[45]") {
direction : input;
- capacitance : 0.3567;
+ capacitance : 0.0000;
}
pin("la_oenb[44]") {
direction : input;
- capacitance : 0.4817;
+ capacitance : 0.0000;
}
pin("la_oenb[43]") {
direction : input;
- capacitance : 0.1341;
+ capacitance : 0.0000;
}
pin("la_oenb[42]") {
direction : input;
- capacitance : 0.1900;
+ capacitance : 0.0000;
}
pin("la_oenb[41]") {
direction : input;
- capacitance : 0.2615;
+ capacitance : 0.0000;
}
pin("la_oenb[40]") {
direction : input;
- capacitance : 0.1385;
+ capacitance : 0.0000;
}
pin("la_oenb[39]") {
direction : input;
- capacitance : 0.5256;
+ capacitance : 0.0000;
}
pin("la_oenb[38]") {
direction : input;
- capacitance : 0.5893;
+ capacitance : 0.0000;
}
pin("la_oenb[37]") {
direction : input;
- capacitance : 0.2003;
+ capacitance : 0.0000;
}
pin("la_oenb[36]") {
direction : input;
- capacitance : 0.4016;
+ capacitance : 0.0000;
}
pin("la_oenb[35]") {
direction : input;
- capacitance : 0.3954;
+ capacitance : 0.0000;
}
pin("la_oenb[34]") {
direction : input;
- capacitance : 0.2912;
+ capacitance : 0.0000;
}
pin("la_oenb[33]") {
direction : input;
- capacitance : 0.4027;
+ capacitance : 0.0000;
}
pin("la_oenb[32]") {
direction : input;
- capacitance : 0.3969;
+ capacitance : 0.0000;
}
pin("la_oenb[31]") {
direction : input;
- capacitance : 0.1244;
+ capacitance : 0.0000;
}
pin("la_oenb[30]") {
direction : input;
- capacitance : 0.3872;
+ capacitance : 0.0000;
}
pin("la_oenb[29]") {
direction : input;
- capacitance : 0.3392;
+ capacitance : 0.0000;
}
pin("la_oenb[28]") {
direction : input;
- capacitance : 0.2694;
+ capacitance : 0.0000;
}
pin("la_oenb[27]") {
direction : input;
- capacitance : 0.2698;
+ capacitance : 0.0000;
}
pin("la_oenb[26]") {
direction : input;
- capacitance : 0.4200;
+ capacitance : 0.0000;
}
pin("la_oenb[25]") {
direction : input;
- capacitance : 0.4796;
+ capacitance : 0.0000;
}
pin("la_oenb[24]") {
direction : input;
- capacitance : 0.2912;
+ capacitance : 0.0000;
}
pin("la_oenb[23]") {
direction : input;
- capacitance : 0.3527;
+ capacitance : 0.0000;
}
pin("la_oenb[22]") {
direction : input;
- capacitance : 0.1049;
+ capacitance : 0.0000;
}
pin("la_oenb[21]") {
direction : input;
- capacitance : 0.1567;
+ capacitance : 0.0000;
}
pin("la_oenb[20]") {
direction : input;
- capacitance : 0.3421;
+ capacitance : 0.0000;
}
pin("la_oenb[19]") {
direction : input;
- capacitance : 0.1915;
+ capacitance : 0.0000;
}
pin("la_oenb[18]") {
direction : input;
- capacitance : 0.1870;
+ capacitance : 0.0000;
}
pin("la_oenb[17]") {
direction : input;
- capacitance : 0.3927;
+ capacitance : 0.0000;
}
pin("la_oenb[16]") {
direction : input;
- capacitance : 0.0932;
+ capacitance : 0.0000;
}
pin("la_oenb[15]") {
direction : input;
- capacitance : 0.1430;
+ capacitance : 0.0000;
}
pin("la_oenb[14]") {
direction : input;
- capacitance : 0.1556;
+ capacitance : 0.0000;
}
pin("la_oenb[13]") {
direction : input;
- capacitance : 0.2846;
+ capacitance : 0.0000;
}
pin("la_oenb[12]") {
direction : input;
- capacitance : 0.1813;
+ capacitance : 0.0000;
}
pin("la_oenb[11]") {
direction : input;
- capacitance : 0.2593;
+ capacitance : 0.0000;
}
pin("la_oenb[10]") {
direction : input;
- capacitance : 0.2618;
+ capacitance : 0.0000;
}
pin("la_oenb[9]") {
direction : input;
- capacitance : 0.3199;
+ capacitance : 0.0000;
}
pin("la_oenb[8]") {
direction : input;
- capacitance : 0.2600;
+ capacitance : 0.0000;
}
pin("la_oenb[7]") {
direction : input;
- capacitance : 0.1562;
+ capacitance : 0.0000;
}
pin("la_oenb[6]") {
direction : input;
- capacitance : 0.3305;
+ capacitance : 0.0000;
}
pin("la_oenb[5]") {
direction : input;
- capacitance : 0.2892;
+ capacitance : 0.0000;
}
pin("la_oenb[4]") {
direction : input;
- capacitance : 0.3777;
+ capacitance : 0.0000;
}
pin("la_oenb[3]") {
direction : input;
- capacitance : 0.1086;
+ capacitance : 0.0000;
}
pin("la_oenb[2]") {
direction : input;
- capacitance : 0.1170;
+ capacitance : 0.0000;
}
pin("la_oenb[1]") {
direction : input;
- capacitance : 0.1973;
+ capacitance : 0.0000;
}
pin("la_oenb[0]") {
direction : input;
- capacitance : 0.3148;
+ capacitance : 0.0000;
}
}
bus("user_irq") {
@@ -1417,131 +1417,131 @@
capacitance : 0.0000;
pin("wbs_adr_i[31]") {
direction : input;
- capacitance : 0.1536;
+ capacitance : 0.0000;
}
pin("wbs_adr_i[30]") {
direction : input;
- capacitance : 0.2071;
+ capacitance : 0.0000;
}
pin("wbs_adr_i[29]") {
direction : input;
- capacitance : 0.2806;
+ capacitance : 0.0000;
}
pin("wbs_adr_i[28]") {
direction : input;
- capacitance : 0.1122;
+ capacitance : 0.0000;
}
pin("wbs_adr_i[27]") {
direction : input;
- capacitance : 0.0787;
+ capacitance : 0.0000;
}
pin("wbs_adr_i[26]") {
direction : input;
- capacitance : 0.0684;
+ capacitance : 0.0000;
}
pin("wbs_adr_i[25]") {
direction : input;
- capacitance : 0.0618;
+ capacitance : 0.0000;
}
pin("wbs_adr_i[24]") {
direction : input;
- capacitance : 0.2021;
+ capacitance : 0.0000;
}
pin("wbs_adr_i[23]") {
direction : input;
- capacitance : 0.0988;
+ capacitance : 0.0000;
}
pin("wbs_adr_i[22]") {
direction : input;
- capacitance : 0.0903;
+ capacitance : 0.0000;
}
pin("wbs_adr_i[21]") {
direction : input;
- capacitance : 0.1019;
+ capacitance : 0.0000;
}
pin("wbs_adr_i[20]") {
direction : input;
- capacitance : 0.1998;
+ capacitance : 0.0000;
}
pin("wbs_adr_i[19]") {
direction : input;
- capacitance : 0.0847;
+ capacitance : 0.0000;
}
pin("wbs_adr_i[18]") {
direction : input;
- capacitance : 0.1924;
+ capacitance : 0.0000;
}
pin("wbs_adr_i[17]") {
direction : input;
- capacitance : 0.2232;
+ capacitance : 0.0000;
}
pin("wbs_adr_i[16]") {
direction : input;
- capacitance : 0.2400;
+ capacitance : 0.0000;
}
pin("wbs_adr_i[15]") {
direction : input;
- capacitance : 0.1287;
+ capacitance : 0.0000;
}
pin("wbs_adr_i[14]") {
direction : input;
- capacitance : 0.1321;
+ capacitance : 0.0000;
}
pin("wbs_adr_i[13]") {
direction : input;
- capacitance : 0.1304;
+ capacitance : 0.0000;
}
pin("wbs_adr_i[12]") {
direction : input;
- capacitance : 0.1442;
+ capacitance : 0.0000;
}
pin("wbs_adr_i[11]") {
direction : input;
- capacitance : 0.1493;
+ capacitance : 0.0000;
}
pin("wbs_adr_i[10]") {
direction : input;
- capacitance : 0.0927;
+ capacitance : 0.0000;
}
pin("wbs_adr_i[9]") {
direction : input;
- capacitance : 0.1537;
+ capacitance : 0.0000;
}
pin("wbs_adr_i[8]") {
direction : input;
- capacitance : 0.1794;
+ capacitance : 0.0000;
}
pin("wbs_adr_i[7]") {
direction : input;
- capacitance : 0.2008;
+ capacitance : 0.0000;
}
pin("wbs_adr_i[6]") {
direction : input;
- capacitance : 0.2136;
+ capacitance : 0.0000;
}
pin("wbs_adr_i[5]") {
direction : input;
- capacitance : 0.1495;
+ capacitance : 0.0000;
}
pin("wbs_adr_i[4]") {
direction : input;
- capacitance : 0.1905;
+ capacitance : 0.0000;
}
pin("wbs_adr_i[3]") {
direction : input;
- capacitance : 0.2482;
+ capacitance : 0.0000;
}
pin("wbs_adr_i[2]") {
direction : input;
- capacitance : 0.2011;
+ capacitance : 0.0000;
}
pin("wbs_adr_i[1]") {
direction : input;
- capacitance : 0.1299;
+ capacitance : 0.0000;
}
pin("wbs_adr_i[0]") {
direction : input;
- capacitance : 0.1718;
+ capacitance : 0.0000;
}
}
bus("wbs_dat_i") {
@@ -1550,131 +1550,131 @@
capacitance : 0.0000;
pin("wbs_dat_i[31]") {
direction : input;
- capacitance : 0.2013;
+ capacitance : 0.0000;
}
pin("wbs_dat_i[30]") {
direction : input;
- capacitance : 0.2090;
+ capacitance : 0.0000;
}
pin("wbs_dat_i[29]") {
direction : input;
- capacitance : 0.1136;
+ capacitance : 0.0000;
}
pin("wbs_dat_i[28]") {
direction : input;
- capacitance : 0.1109;
+ capacitance : 0.0000;
}
pin("wbs_dat_i[27]") {
direction : input;
- capacitance : 0.1227;
+ capacitance : 0.0000;
}
pin("wbs_dat_i[26]") {
direction : input;
- capacitance : 0.1034;
+ capacitance : 0.0000;
}
pin("wbs_dat_i[25]") {
direction : input;
- capacitance : 0.2105;
+ capacitance : 0.0000;
}
pin("wbs_dat_i[24]") {
direction : input;
- capacitance : 0.0615;
+ capacitance : 0.0000;
}
pin("wbs_dat_i[23]") {
direction : input;
- capacitance : 0.0903;
+ capacitance : 0.0000;
}
pin("wbs_dat_i[22]") {
direction : input;
- capacitance : 0.0951;
+ capacitance : 0.0000;
}
pin("wbs_dat_i[21]") {
direction : input;
- capacitance : 0.0991;
+ capacitance : 0.0000;
}
pin("wbs_dat_i[20]") {
direction : input;
- capacitance : 0.1147;
+ capacitance : 0.0000;
}
pin("wbs_dat_i[19]") {
direction : input;
- capacitance : 0.0790;
+ capacitance : 0.0000;
}
pin("wbs_dat_i[18]") {
direction : input;
- capacitance : 0.0952;
+ capacitance : 0.0000;
}
pin("wbs_dat_i[17]") {
direction : input;
- capacitance : 0.1844;
+ capacitance : 0.0000;
}
pin("wbs_dat_i[16]") {
direction : input;
- capacitance : 0.0958;
+ capacitance : 0.0000;
}
pin("wbs_dat_i[15]") {
direction : input;
- capacitance : 0.1624;
+ capacitance : 0.0000;
}
pin("wbs_dat_i[14]") {
direction : input;
- capacitance : 0.1175;
+ capacitance : 0.0000;
}
pin("wbs_dat_i[13]") {
direction : input;
- capacitance : 0.1146;
+ capacitance : 0.0000;
}
pin("wbs_dat_i[12]") {
direction : input;
- capacitance : 0.1433;
+ capacitance : 0.0000;
}
pin("wbs_dat_i[11]") {
direction : input;
- capacitance : 0.1603;
+ capacitance : 0.0000;
}
pin("wbs_dat_i[10]") {
direction : input;
- capacitance : 0.1450;
+ capacitance : 0.0000;
}
pin("wbs_dat_i[9]") {
direction : input;
- capacitance : 0.1311;
+ capacitance : 0.0000;
}
pin("wbs_dat_i[8]") {
direction : input;
- capacitance : 0.1314;
+ capacitance : 0.0000;
}
pin("wbs_dat_i[7]") {
direction : input;
- capacitance : 0.1861;
+ capacitance : 0.0000;
}
pin("wbs_dat_i[6]") {
direction : input;
- capacitance : 0.1501;
+ capacitance : 0.0000;
}
pin("wbs_dat_i[5]") {
direction : input;
- capacitance : 0.1964;
+ capacitance : 0.0000;
}
pin("wbs_dat_i[4]") {
direction : input;
- capacitance : 0.2157;
+ capacitance : 0.0000;
}
pin("wbs_dat_i[3]") {
direction : input;
- capacitance : 0.2350;
+ capacitance : 0.0000;
}
pin("wbs_dat_i[2]") {
direction : input;
- capacitance : 0.0828;
+ capacitance : 0.0000;
}
pin("wbs_dat_i[1]") {
direction : input;
- capacitance : 0.1650;
+ capacitance : 0.0000;
}
pin("wbs_dat_i[0]") {
direction : input;
- capacitance : 0.2677;
+ capacitance : 0.0000;
}
}
bus("wbs_dat_o") {
@@ -1816,19 +1816,19 @@
capacitance : 0.0000;
pin("wbs_sel_i[3]") {
direction : input;
- capacitance : 0.2178;
+ capacitance : 0.0000;
}
pin("wbs_sel_i[2]") {
direction : input;
- capacitance : 0.1412;
+ capacitance : 0.0000;
}
pin("wbs_sel_i[1]") {
direction : input;
- capacitance : 0.1819;
+ capacitance : 0.0000;
}
pin("wbs_sel_i[0]") {
direction : input;
- capacitance : 0.0939;
+ capacitance : 0.0000;
}
}
}
diff --git a/mag/user_proj_example.mag b/mag/user_proj_example.mag
index f55c43d..cbc4133 100644
--- a/mag/user_proj_example.mag
+++ b/mag/user_proj_example.mag
@@ -1,7 +1,7 @@
magic
tech gf180mcuC
magscale 1 10
-timestamp 1669047491
+timestamp 1669194844
<< metal1 >>
rect 158162 117070 158174 117122
rect 158226 117119 158238 117122
@@ -68143,7 +68143,7 @@
rect 173700 3108 173728 3164
rect 173408 3076 173728 3108
rect 117292 2930 117348 2940
-use gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__346__I deps/pdks/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag
+use gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__346__I pdk_gf180/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag
timestamp 1666464484
transform 1 0 92064 0 -1 7840
box -86 -86 310 870
@@ -71227,15 +71227,15 @@
timestamp 1666464484
transform -1 0 21952 0 1 4704
box -86 -86 310 870
-use gf180mcu_fd_sc_mcu7t5v0__fillcap_32 FILLER_0_2 deps/pdks/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag
+use gf180mcu_fd_sc_mcu7t5v0__fillcap_32 FILLER_0_2 pdk_gf180/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag
timestamp 1666464484
transform 1 0 1568 0 1 3136
box -86 -86 3670 870
-use gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_0_34 deps/pdks/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag
+use gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_0_34 pdk_gf180/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag
timestamp 1666464484
transform 1 0 5152 0 1 3136
box 0 -60 112 844
-use gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_0_37 deps/pdks/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag
+use gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_0_37 pdk_gf180/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag
timestamp 1666464484
transform 1 0 5488 0 1 3136
box 0 -60 224 844
@@ -71275,7 +71275,7 @@
timestamp 1666464484
transform 1 0 14784 0 1 3136
box 0 -60 224 844
-use gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_0_136 deps/pdks/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag
+use gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_0_136 pdk_gf180/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag
timestamp 1666464484
transform 1 0 16576 0 1 3136
box -86 -86 534 870
@@ -71947,7 +71947,7 @@
timestamp 1666464484
transform 1 0 174608 0 1 3136
box 0 -60 224 844
-use gf180mcu_fd_sc_mcu7t5v0__fillcap_16 FILLER_0_1553 deps/pdks/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag
+use gf180mcu_fd_sc_mcu7t5v0__fillcap_16 FILLER_0_1553 pdk_gf180/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag
timestamp 1666464484
transform 1 0 175280 0 1 3136
box -86 -86 1878 870
@@ -71967,7 +71967,7 @@
timestamp 1666464484
transform 1 0 1568 0 -1 4704
box -86 -86 3670 870
-use gf180mcu_fd_sc_mcu7t5v0__fillcap_8 FILLER_1_34 deps/pdks/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag
+use gf180mcu_fd_sc_mcu7t5v0__fillcap_8 FILLER_1_34 pdk_gf180/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag
timestamp 1666464484
transform 1 0 5152 0 -1 4704
box -86 -86 982 870
@@ -74187,7 +74187,7 @@
timestamp 1666464484
transform 1 0 151984 0 -1 6272
box -86 -86 534 870
-use gf180mcu_fd_sc_mcu7t5v0__fillcap_64 FILLER_3_1351 deps/pdks/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag
+use gf180mcu_fd_sc_mcu7t5v0__fillcap_64 FILLER_3_1351 pdk_gf180/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag
timestamp 1666464484
transform 1 0 152656 0 -1 6272
box -86 -86 7254 870
@@ -117367,7 +117367,7 @@
timestamp 1666464484
transform 1 0 177968 0 1 116032
box -86 -86 534 870
-use gf180mcu_fd_sc_mcu7t5v0__endcap PHY_0 deps/pdks/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag
+use gf180mcu_fd_sc_mcu7t5v0__endcap PHY_0 pdk_gf180/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag
timestamp 1666464484
transform 1 0 1344 0 1 3136
box -86 -86 310 870
@@ -118527,7 +118527,7 @@
timestamp 1666464484
transform -1 0 178640 0 1 116032
box -86 -86 310 870
-use gf180mcu_fd_sc_mcu7t5v0__filltie TAP_290 deps/pdks/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag
+use gf180mcu_fd_sc_mcu7t5v0__filltie TAP_290 pdk_gf180/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag
timestamp 1666464484
transform 1 0 5264 0 1 3136
box -86 -86 310 870
@@ -131471,15 +131471,15 @@
timestamp 1666464484
transform 1 0 177744 0 1 116032
box -86 -86 310 870
-use gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _346_ deps/pdks/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag
+use gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _346_ pdk_gf180/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag
timestamp 1666464484
transform 1 0 89152 0 -1 4704
box -86 -86 534 870
-use gf180mcu_fd_sc_mcu7t5v0__and2_1 _347_ deps/pdks/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag
+use gf180mcu_fd_sc_mcu7t5v0__and2_1 _347_ pdk_gf180/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag
timestamp 1666464484
transform 1 0 8288 0 1 4704
box -86 -86 982 870
-use gf180mcu_fd_sc_mcu7t5v0__clkbuf_1 _348_ deps/pdks/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag
+use gf180mcu_fd_sc_mcu7t5v0__clkbuf_1 _348_ pdk_gf180/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag
timestamp 1666464484
transform -1 0 135856 0 -1 4704
box -86 -86 758 870
@@ -131491,11 +131491,11 @@
timestamp 1666464484
transform 1 0 132496 0 -1 6272
box -86 -86 758 870
-use gf180mcu_fd_sc_mcu7t5v0__nand2_1 _351_ deps/pdks/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag
+use gf180mcu_fd_sc_mcu7t5v0__nand2_1 _351_ pdk_gf180/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag
timestamp 1666464484
transform -1 0 92848 0 -1 6272
box -86 -86 646 870
-use gf180mcu_fd_sc_mcu7t5v0__nor2_1 _352_ deps/pdks/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag
+use gf180mcu_fd_sc_mcu7t5v0__nor2_1 _352_ pdk_gf180/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag
timestamp 1666464484
transform -1 0 64624 0 -1 4704
box -86 -86 758 870
@@ -131543,7 +131543,7 @@
timestamp 1666464484
transform 1 0 123648 0 -1 6272
box -86 -86 758 870
-use gf180mcu_fd_sc_mcu7t5v0__oai21_1 _364_ deps/pdks/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag
+use gf180mcu_fd_sc_mcu7t5v0__oai21_1 _364_ pdk_gf180/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag
timestamp 1666464484
transform 1 0 123312 0 -1 4704
box -86 -86 982 870
@@ -131563,7 +131563,7 @@
timestamp 1666464484
transform 1 0 121856 0 -1 6272
box -86 -86 758 870
-use gf180mcu_fd_sc_mcu7t5v0__or3_1 _369_ deps/pdks/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag
+use gf180mcu_fd_sc_mcu7t5v0__or3_1 _369_ pdk_gf180/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag
timestamp 1666464484
transform 1 0 113008 0 -1 6272
box -86 -86 1206 870
@@ -131591,11 +131591,11 @@
timestamp 1666464484
transform 1 0 129808 0 1 3136
box -86 -86 758 870
-use gf180mcu_fd_sc_mcu7t5v0__aoi21_1 _376_ deps/pdks/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag
+use gf180mcu_fd_sc_mcu7t5v0__aoi21_1 _376_ pdk_gf180/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag
timestamp 1666464484
transform 1 0 130368 0 1 4704
box -86 -86 982 870
-use gf180mcu_fd_sc_mcu7t5v0__or4_1 _377_ deps/pdks/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag
+use gf180mcu_fd_sc_mcu7t5v0__or4_1 _377_ pdk_gf180/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag
timestamp 1666464484
transform -1 0 128576 0 1 4704
box -86 -86 1430 870
@@ -131623,7 +131623,7 @@
timestamp 1666464484
transform 1 0 139664 0 -1 6272
box -86 -86 758 870
-use gf180mcu_fd_sc_mcu7t5v0__nor4_1 _384_ deps/pdks/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag
+use gf180mcu_fd_sc_mcu7t5v0__nor4_1 _384_ pdk_gf180/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag
timestamp 1666464484
transform 1 0 136416 0 1 4704
box -86 -86 1206 870
@@ -131695,7 +131695,7 @@
timestamp 1666464484
transform 1 0 141456 0 -1 4704
box -86 -86 1206 870
-use gf180mcu_fd_sc_mcu7t5v0__nand4_1 _402_ deps/pdks/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag
+use gf180mcu_fd_sc_mcu7t5v0__nand4_1 _402_ pdk_gf180/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag
timestamp 1666464484
transform -1 0 138768 0 1 4704
box -86 -86 1094 870
@@ -131735,7 +131735,7 @@
timestamp 1666464484
transform 1 0 65296 0 -1 6272
box -86 -86 534 870
-use gf180mcu_fd_sc_mcu7t5v0__aoi22_1 _412_ deps/pdks/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag
+use gf180mcu_fd_sc_mcu7t5v0__aoi22_1 _412_ pdk_gf180/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag
timestamp 1666464484
transform 1 0 67088 0 -1 6272
box -86 -86 1094 870
@@ -131767,7 +131767,7 @@
timestamp 1666464484
transform 1 0 62160 0 -1 4704
box -86 -86 758 870
-use gf180mcu_fd_sc_mcu7t5v0__xor2_1 _420_ deps/pdks/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag
+use gf180mcu_fd_sc_mcu7t5v0__xor2_1 _420_ pdk_gf180/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag
timestamp 1666464484
transform 1 0 65744 0 1 4704
box -86 -86 1430 870
@@ -131775,11 +131775,11 @@
timestamp 1666464484
transform 1 0 78288 0 1 6272
box -86 -86 758 870
-use gf180mcu_fd_sc_mcu7t5v0__and4_1 _422_ deps/pdks/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag
+use gf180mcu_fd_sc_mcu7t5v0__and4_1 _422_ pdk_gf180/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag
timestamp 1666464484
transform 1 0 42112 0 -1 4704
box -86 -86 1318 870
-use gf180mcu_fd_sc_mcu7t5v0__aoi221_1 _423_ deps/pdks/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag
+use gf180mcu_fd_sc_mcu7t5v0__aoi221_1 _423_ pdk_gf180/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag
timestamp 1666464484
transform 1 0 67312 0 -1 4704
box -86 -86 1318 870
@@ -131787,7 +131787,7 @@
timestamp 1666464484
transform -1 0 67312 0 -1 9408
box -86 -86 758 870
-use gf180mcu_fd_sc_mcu7t5v0__nand3_1 _425_ deps/pdks/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag
+use gf180mcu_fd_sc_mcu7t5v0__nand3_1 _425_ pdk_gf180/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag
timestamp 1666464484
transform 1 0 67536 0 1 6272
box -86 -86 870 870
@@ -131815,7 +131815,7 @@
timestamp 1666464484
transform -1 0 69104 0 -1 9408
box -86 -86 758 870
-use gf180mcu_fd_sc_mcu7t5v0__xnor2_1 _432_ deps/pdks/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag
+use gf180mcu_fd_sc_mcu7t5v0__xnor2_1 _432_ pdk_gf180/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag
timestamp 1666464484
transform 1 0 67312 0 1 4704
box -86 -86 1542 870
@@ -131839,11 +131839,11 @@
timestamp 1666464484
transform -1 0 128240 0 -1 4704
box -86 -86 758 870
-use gf180mcu_fd_sc_mcu7t5v0__buf_1 _438_ deps/pdks/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag
+use gf180mcu_fd_sc_mcu7t5v0__buf_1 _438_ pdk_gf180/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag
timestamp 1666464484
transform 1 0 23856 0 1 6272
box -86 -86 758 870
-use gf180mcu_fd_sc_mcu7t5v0__and4_2 _439_ deps/pdks/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag
+use gf180mcu_fd_sc_mcu7t5v0__and4_2 _439_ pdk_gf180/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag
timestamp 1666464484
transform 1 0 65856 0 1 6272
box -86 -86 1542 870
@@ -131859,7 +131859,7 @@
timestamp 1666464484
transform 1 0 76832 0 1 3136
box -86 -86 758 870
-use gf180mcu_fd_sc_mcu7t5v0__aoi222_1 _443_ deps/pdks/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag
+use gf180mcu_fd_sc_mcu7t5v0__aoi222_1 _443_ pdk_gf180/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag
timestamp 1666464484
transform 1 0 71008 0 -1 4704
box -86 -86 1654 870
@@ -131919,7 +131919,7 @@
timestamp 1666464484
transform -1 0 76720 0 1 7840
box -86 -86 758 870
-use gf180mcu_fd_sc_mcu7t5v0__nand4_4 _458_ deps/pdks/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag
+use gf180mcu_fd_sc_mcu7t5v0__nand4_4 _458_ pdk_gf180/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag
timestamp 1666464484
transform 1 0 71792 0 1 4704
box -86 -86 3670 870
@@ -131983,7 +131983,7 @@
timestamp 1666464484
transform 1 0 75264 0 1 7840
box -86 -86 646 870
-use gf180mcu_fd_sc_mcu7t5v0__nor3_1 _474_ deps/pdks/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag
+use gf180mcu_fd_sc_mcu7t5v0__nor3_1 _474_ pdk_gf180/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag
timestamp 1666464484
transform 1 0 77168 0 1 6272
box -86 -86 982 870
@@ -132023,11 +132023,11 @@
timestamp 1666464484
transform -1 0 84112 0 1 9408
box -86 -86 758 870
-use gf180mcu_fd_sc_mcu7t5v0__inv_1 _484_ deps/pdks/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag
+use gf180mcu_fd_sc_mcu7t5v0__inv_1 _484_ pdk_gf180/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag
timestamp 1666464484
transform -1 0 51968 0 -1 10976
box -86 -86 534 870
-use gf180mcu_fd_sc_mcu7t5v0__nor4_4 _485_ deps/pdks/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag
+use gf180mcu_fd_sc_mcu7t5v0__nor4_4 _485_ pdk_gf180/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag
timestamp 1666464484
transform 1 0 76272 0 -1 7840
box -86 -86 4230 870
@@ -132083,7 +132083,7 @@
timestamp 1666464484
transform 1 0 81648 0 -1 10976
box -86 -86 758 870
-use gf180mcu_fd_sc_mcu7t5v0__clkinv_2 _499_ deps/pdks/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag
+use gf180mcu_fd_sc_mcu7t5v0__clkinv_2 _499_ pdk_gf180/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag
timestamp 1666464484
transform 1 0 68096 0 1 7840
box -86 -86 758 870
@@ -132091,7 +132091,7 @@
timestamp 1666464484
transform -1 0 85792 0 -1 7840
box -86 -86 3670 870
-use gf180mcu_fd_sc_mcu7t5v0__or2_1 _501_ deps/pdks/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag
+use gf180mcu_fd_sc_mcu7t5v0__or2_1 _501_ pdk_gf180/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag
timestamp 1666464484
transform 1 0 82768 0 1 6272
box -86 -86 982 870
@@ -132231,7 +132231,7 @@
timestamp 1666464484
transform -1 0 119616 0 1 9408
box -86 -86 758 870
-use gf180mcu_fd_sc_mcu7t5v0__and3_1 _536_ deps/pdks/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag
+use gf180mcu_fd_sc_mcu7t5v0__and3_1 _536_ pdk_gf180/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag
timestamp 1666464484
transform 1 0 119280 0 1 7840
box -86 -86 1206 870
@@ -132275,7 +132275,7 @@
timestamp 1666464484
transform 1 0 104944 0 1 6272
box -86 -86 3670 870
-use gf180mcu_fd_sc_mcu7t5v0__oai211_1 _547_ deps/pdks/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag
+use gf180mcu_fd_sc_mcu7t5v0__oai211_1 _547_ pdk_gf180/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag
timestamp 1666464484
transform -1 0 116480 0 1 6272
box -86 -86 1206 870
@@ -132395,7 +132395,7 @@
timestamp 1666464484
transform 1 0 102816 0 -1 6272
box -86 -86 646 870
-use gf180mcu_fd_sc_mcu7t5v0__nor4_2 _577_ deps/pdks/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag
+use gf180mcu_fd_sc_mcu7t5v0__nor4_2 _577_ pdk_gf180/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag
timestamp 1666464484
transform 1 0 102928 0 1 4704
box -86 -86 2102 870
@@ -132403,7 +132403,7 @@
timestamp 1666464484
transform -1 0 102928 0 -1 7840
box -86 -86 758 870
-use gf180mcu_fd_sc_mcu7t5v0__aoi211_1 _579_ deps/pdks/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag
+use gf180mcu_fd_sc_mcu7t5v0__aoi211_1 _579_ pdk_gf180/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag
timestamp 1666464484
transform -1 0 102256 0 -1 6272
box -86 -86 1206 870
@@ -132535,7 +132535,7 @@
timestamp 1666464484
transform 1 0 94976 0 -1 9408
box -86 -86 534 870
-use gf180mcu_fd_sc_mcu7t5v0__oai31_1 _612_ deps/pdks/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag
+use gf180mcu_fd_sc_mcu7t5v0__oai31_1 _612_ pdk_gf180/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag
timestamp 1666464484
transform 1 0 94640 0 1 7840
box -86 -86 1318 870
@@ -132571,7 +132571,7 @@
timestamp 1666464484
transform 1 0 62384 0 -1 6272
box -86 -86 758 870
-use gf180mcu_fd_sc_mcu7t5v0__mux2_2 _621_ deps/pdks/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag
+use gf180mcu_fd_sc_mcu7t5v0__mux2_2 _621_ pdk_gf180/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag
timestamp 1666464484
transform -1 0 62944 0 1 4704
box -86 -86 1766 870
@@ -132583,7 +132583,7 @@
timestamp 1666464484
transform -1 0 49168 0 1 6272
box -86 -86 758 870
-use gf180mcu_fd_sc_mcu7t5v0__buf_2 _624_ deps/pdks/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag
+use gf180mcu_fd_sc_mcu7t5v0__buf_2 _624_ pdk_gf180/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag
timestamp 1666464484
transform -1 0 23408 0 1 6272
box -86 -86 982 870
@@ -132855,7 +132855,7 @@
timestamp 1666464484
transform 1 0 63280 0 -1 7840
box -86 -86 982 870
-use gf180mcu_fd_sc_mcu7t5v0__dffq_1 _692_ deps/pdks/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag
+use gf180mcu_fd_sc_mcu7t5v0__dffq_1 _692_ pdk_gf180/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag
timestamp 1666464484
transform -1 0 38976 0 -1 4704
box -86 -86 3334 870
@@ -132867,7 +132867,7 @@
timestamp 1666464484
transform -1 0 66864 0 1 10976
box -86 -86 3334 870
-use gf180mcu_fd_sc_mcu7t5v0__dffq_2 _695_ deps/pdks/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag
+use gf180mcu_fd_sc_mcu7t5v0__dffq_2 _695_ pdk_gf180/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag
timestamp 1666464484
transform -1 0 68656 0 1 9408
box -86 -86 3558 870
@@ -133391,7 +133391,7 @@
timestamp 1666464484
transform 1 0 117040 0 -1 9408
box -86 -86 758 870
-use gf180mcu_fd_sc_mcu7t5v0__clkbuf_16 clkbuf_0_wb_clk_i deps/pdks/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag
+use gf180mcu_fd_sc_mcu7t5v0__clkbuf_16 clkbuf_0_wb_clk_i pdk_gf180/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag
timestamp 1666464484
transform 1 0 61264 0 1 7840
box -86 -86 5686 870
@@ -133683,7 +133683,7 @@
timestamp 1666464484
transform -1 0 173600 0 1 3136
box -86 -86 758 870
-use gf180mcu_fd_sc_mcu7t5v0__clkbuf_8 input65 deps/pdks/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag
+use gf180mcu_fd_sc_mcu7t5v0__clkbuf_8 input65 pdk_gf180/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag
timestamp 1666464484
transform 1 0 6160 0 1 3136
box -86 -86 2998 870
@@ -133843,7 +133843,7 @@
timestamp 1666464484
transform 1 0 9408 0 1 4704
box -86 -86 758 870
-use gf180mcu_fd_sc_mcu7t5v0__clkbuf_4 output105 deps/pdks/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag
+use gf180mcu_fd_sc_mcu7t5v0__clkbuf_4 output105 pdk_gf180/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag
timestamp 1666464484
transform -1 0 4592 0 1 116032
box -86 -86 1654 870
@@ -134379,7 +134379,7 @@
timestamp 1666464484
transform -1 0 29008 0 1 4704
box -86 -86 1654 870
-use gf180mcu_fd_sc_mcu7t5v0__tiel user_proj_example_239 deps/pdks/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag
+use gf180mcu_fd_sc_mcu7t5v0__tiel user_proj_example_239 pdk_gf180/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/mag
timestamp 1666464484
transform -1 0 177520 0 1 116032
box -86 -86 534 870
diff --git a/mag/user_project_wrapper.mag b/mag/user_project_wrapper.mag
index 3be37e9..5ef8c55 100644
--- a/mag/user_project_wrapper.mag
+++ b/mag/user_project_wrapper.mag
@@ -1,320 +1,267 @@
magic
tech gf180mcuC
magscale 1 10
-timestamp 1669047626
+timestamp 1669196085
<< metal1 >>
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-rect 262946 165118 262958 165170
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<< via1 >>
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<< metal2 >>
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@@ -323,7515 +270,2398 @@
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<< via2 >>
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<< metal3 >>
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<< via3 >>
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<< metal4 >>
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-rect 203058 598380 203678 599436
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-rect 203058 383918 203678 401490
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-rect 203058 365546 203678 365614
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-rect 203058 329918 203678 347490
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-rect 203058 293918 203678 311490
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-rect 206778 599340 207398 599436
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-rect 206778 551918 207398 569490
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rect 149058 185862 149154 185918
rect 149210 185862 149278 185918
rect 149334 185862 149402 185918
@@ -31873,214 +20110,6 @@
rect 168278 191490 168348 191546
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@@ -32906,217 +20727,6 @@
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rect 167058 149862 167154 149918
rect 167210 149862 167278 149918
rect 167334 149862 167402 149918
@@ -33357,6 +20967,633 @@
rect 167458 1380 167526 1436
rect 167582 1380 167678 1436
rect 167058 324 167678 1380
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-rect 170874 281862 170930 281918
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rect 168222 173614 168278 173670
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rect 170874 173862 170930 173918
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@@ -82821,126 +73564,6 @@
rect 167278 167490 167334 167546
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rect 167526 167490 167582 167546
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@@ -126384,9 +122135,7 @@
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@@ -126649,21 +122424,31 @@
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@@ -127572,9 +123415,7 @@
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@@ -127582,21 +123423,35 @@
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@@ -127707,21 +123562,31 @@
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@@ -128640,21 +124561,35 @@
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@@ -128728,7 +124663,13 @@
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-rect 291034 227862 291102 227918
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@@ -128899,21 +124851,33 @@
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-rect 198874 227738 198942 227794
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-rect 260314 227738 260382 227794
-rect 260438 227738 260874 227794
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@@ -128921,9 +124885,7 @@
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-rect 279302 173862 290978 173918
-rect 291034 173862 291102 173918
-rect 291158 173862 296874 173918
+rect 279302 173862 296874 173918
rect 296930 173862 296998 173918
rect 297054 173862 297122 173918
rect 297178 173862 297246 173918
@@ -132081,13 +128259,23 @@
rect 170930 173738 170998 173794
rect 171054 173738 171122 173794
rect 171178 173738 171246 173794
-rect 171302 173738 198818 173794
-rect 198874 173738 198942 173794
-rect 198998 173738 229538 173794
-rect 229594 173738 229662 173794
-rect 229718 173738 260258 173794
-rect 260314 173738 260382 173794
-rect 260438 173738 260874 173794
+rect 171302 173738 188874 173794
+rect 188930 173738 188998 173794
+rect 189054 173738 189122 173794
+rect 189178 173738 189246 173794
+rect 189302 173738 206874 173794
+rect 206930 173738 206998 173794
+rect 207054 173738 207122 173794
+rect 207178 173738 207246 173794
+rect 207302 173738 224874 173794
+rect 224930 173738 224998 173794
+rect 225054 173738 225122 173794
+rect 225178 173738 225246 173794
+rect 225302 173738 242874 173794
+rect 242930 173738 242998 173794
+rect 243054 173738 243122 173794
+rect 243178 173738 243246 173794
+rect 243302 173738 260874 173794
rect 260930 173738 260998 173794
rect 261054 173738 261122 173794
rect 261178 173738 261246 173794
@@ -132095,9 +128283,7 @@
rect 278930 173738 278998 173794
rect 279054 173738 279122 173794
rect 279178 173738 279246 173794
-rect 279302 173738 290978 173794
-rect 291034 173738 291102 173794
-rect 291158 173738 296874 173794
+rect 279302 173738 296874 173794
rect 296930 173738 296998 173794
rect 297054 173738 297122 173794
rect 297178 173738 297246 173794
@@ -132215,13 +128401,23 @@
rect 170930 173614 170998 173670
rect 171054 173614 171122 173670
rect 171178 173614 171246 173670
-rect 171302 173614 198818 173670
-rect 198874 173614 198942 173670
-rect 198998 173614 229538 173670
-rect 229594 173614 229662 173670
-rect 229718 173614 260258 173670
-rect 260314 173614 260382 173670
-rect 260438 173614 260874 173670
+rect 171302 173614 188874 173670
+rect 188930 173614 188998 173670
+rect 189054 173614 189122 173670
+rect 189178 173614 189246 173670
+rect 189302 173614 206874 173670
+rect 206930 173614 206998 173670
+rect 207054 173614 207122 173670
+rect 207178 173614 207246 173670
+rect 207302 173614 224874 173670
+rect 224930 173614 224998 173670
+rect 225054 173614 225122 173670
+rect 225178 173614 225246 173670
+rect 225302 173614 242874 173670
+rect 242930 173614 242998 173670
+rect 243054 173614 243122 173670
+rect 243178 173614 243246 173670
+rect 243302 173614 260874 173670
rect 260930 173614 260998 173670
rect 261054 173614 261122 173670
rect 261178 173614 261246 173670
@@ -132229,9 +128425,7 @@
rect 278930 173614 278998 173670
rect 279054 173614 279122 173670
rect 279178 173614 279246 173670
-rect 279302 173614 290978 173670
-rect 291034 173614 291102 173670
-rect 291158 173614 296874 173670
+rect 279302 173614 296874 173670
rect 296930 173614 296998 173670
rect 297054 173614 297122 173670
rect 297178 173614 297246 173670
@@ -132349,13 +128543,23 @@
rect 170930 173490 170998 173546
rect 171054 173490 171122 173546
rect 171178 173490 171246 173546
-rect 171302 173490 198818 173546
-rect 198874 173490 198942 173546
-rect 198998 173490 229538 173546
-rect 229594 173490 229662 173546
-rect 229718 173490 260258 173546
-rect 260314 173490 260382 173546
-rect 260438 173490 260874 173546
+rect 171302 173490 188874 173546
+rect 188930 173490 188998 173546
+rect 189054 173490 189122 173546
+rect 189178 173490 189246 173546
+rect 189302 173490 206874 173546
+rect 206930 173490 206998 173546
+rect 207054 173490 207122 173546
+rect 207178 173490 207246 173546
+rect 207302 173490 224874 173546
+rect 224930 173490 224998 173546
+rect 225054 173490 225122 173546
+rect 225178 173490 225246 173546
+rect 225302 173490 242874 173546
+rect 242930 173490 242998 173546
+rect 243054 173490 243122 173546
+rect 243178 173490 243246 173546
+rect 243302 173490 260874 173546
rect 260930 173490 260998 173546
rect 261054 173490 261122 173546
rect 261178 173490 261246 173546
@@ -132363,9 +128567,7 @@
rect 278930 173490 278998 173546
rect 279054 173490 279122 173546
rect 279178 173490 279246 173546
-rect 279302 173490 290978 173546
-rect 291034 173490 291102 173546
-rect 291158 173490 296874 173546
+rect 279302 173490 296874 173546
rect 296930 173490 296998 173546
rect 297054 173490 297122 173546
rect 297178 173490 297246 173546
@@ -144388,10 +140590,10 @@
rect 599776 420 599844 476
rect 599900 420 599996 476
rect -12 324 599996 420
-use user_proj_example mprj
+use wrapped_vga_clock wrapped_vga_clock
timestamp 0
transform 1 0 117500 0 1 169000
-box 1344 0 178640 120000
+box -56 -56 59976 59976
<< labels >>
flabel metal3 s 599520 6664 600960 6888 0 FreeSans 896 0 0 0 io_in[0]
port 0 nsew signal input
@@ -145035,35 +141237,27 @@
port 310 nsew power bidirectional
flabel metal4 s 113058 324 113678 599436 0 FreeSans 2560 90 0 0 vdd
port 310 nsew power bidirectional
-flabel metal4 s 131058 324 131678 599436 0 FreeSans 2560 90 0 0 vdd
+flabel metal4 s 131058 324 131678 188242 0 FreeSans 2560 90 0 0 vdd
port 310 nsew power bidirectional
-flabel metal4 s 149058 324 149678 599436 0 FreeSans 2560 90 0 0 vdd
+flabel metal4 s 131058 214606 131678 599436 0 FreeSans 2560 90 0 0 vdd
+port 310 nsew power bidirectional
+flabel metal4 s 149058 324 149678 188242 0 FreeSans 2560 90 0 0 vdd
+port 310 nsew power bidirectional
+flabel metal4 s 149058 214606 149678 599436 0 FreeSans 2560 90 0 0 vdd
port 310 nsew power bidirectional
flabel metal4 s 167058 324 167678 599436 0 FreeSans 2560 90 0 0 vdd
port 310 nsew power bidirectional
-flabel metal4 s 185058 324 185678 169874 0 FreeSans 2560 90 0 0 vdd
+flabel metal4 s 185058 324 185678 599436 0 FreeSans 2560 90 0 0 vdd
port 310 nsew power bidirectional
-flabel metal4 s 185058 287294 185678 599436 0 FreeSans 2560 90 0 0 vdd
+flabel metal4 s 203058 324 203678 599436 0 FreeSans 2560 90 0 0 vdd
port 310 nsew power bidirectional
-flabel metal4 s 203058 324 203678 169874 0 FreeSans 2560 90 0 0 vdd
+flabel metal4 s 221058 324 221678 599436 0 FreeSans 2560 90 0 0 vdd
port 310 nsew power bidirectional
-flabel metal4 s 203058 287294 203678 599436 0 FreeSans 2560 90 0 0 vdd
+flabel metal4 s 239058 324 239678 599436 0 FreeSans 2560 90 0 0 vdd
port 310 nsew power bidirectional
-flabel metal4 s 221058 324 221678 169874 0 FreeSans 2560 90 0 0 vdd
+flabel metal4 s 257058 324 257678 599436 0 FreeSans 2560 90 0 0 vdd
port 310 nsew power bidirectional
-flabel metal4 s 221058 287294 221678 599436 0 FreeSans 2560 90 0 0 vdd
-port 310 nsew power bidirectional
-flabel metal4 s 239058 324 239678 169874 0 FreeSans 2560 90 0 0 vdd
-port 310 nsew power bidirectional
-flabel metal4 s 239058 287294 239678 599436 0 FreeSans 2560 90 0 0 vdd
-port 310 nsew power bidirectional
-flabel metal4 s 257058 324 257678 169874 0 FreeSans 2560 90 0 0 vdd
-port 310 nsew power bidirectional
-flabel metal4 s 257058 287294 257678 599436 0 FreeSans 2560 90 0 0 vdd
-port 310 nsew power bidirectional
-flabel metal4 s 275058 324 275678 170020 0 FreeSans 2560 90 0 0 vdd
-port 310 nsew power bidirectional
-flabel metal4 s 275058 287932 275678 599436 0 FreeSans 2560 90 0 0 vdd
+flabel metal4 s 275058 324 275678 599436 0 FreeSans 2560 90 0 0 vdd
port 310 nsew power bidirectional
flabel metal4 s 293058 324 293678 599436 0 FreeSans 2560 90 0 0 vdd
port 310 nsew power bidirectional
@@ -145187,29 +141381,23 @@
port 311 nsew ground bidirectional
flabel metal4 s 116778 324 117398 599436 0 FreeSans 2560 90 0 0 vss
port 311 nsew ground bidirectional
-flabel metal4 s 134778 324 135398 599436 0 FreeSans 2560 90 0 0 vss
+flabel metal4 s 134778 324 135398 188242 0 FreeSans 2560 90 0 0 vss
+port 311 nsew ground bidirectional
+flabel metal4 s 134778 214606 135398 599436 0 FreeSans 2560 90 0 0 vss
port 311 nsew ground bidirectional
flabel metal4 s 152778 324 153398 170020 0 FreeSans 2560 90 0 0 vss
port 311 nsew ground bidirectional
-flabel metal4 s 152778 287932 153398 599436 0 FreeSans 2560 90 0 0 vss
+flabel metal4 s 152778 227564 153398 599436 0 FreeSans 2560 90 0 0 vss
port 311 nsew ground bidirectional
flabel metal4 s 170778 324 171398 599436 0 FreeSans 2560 90 0 0 vss
port 311 nsew ground bidirectional
-flabel metal4 s 188778 324 189398 169874 0 FreeSans 2560 90 0 0 vss
+flabel metal4 s 188778 324 189398 599436 0 FreeSans 2560 90 0 0 vss
port 311 nsew ground bidirectional
-flabel metal4 s 188778 287294 189398 599436 0 FreeSans 2560 90 0 0 vss
+flabel metal4 s 206778 324 207398 599436 0 FreeSans 2560 90 0 0 vss
port 311 nsew ground bidirectional
-flabel metal4 s 206778 324 207398 169874 0 FreeSans 2560 90 0 0 vss
+flabel metal4 s 224778 324 225398 599436 0 FreeSans 2560 90 0 0 vss
port 311 nsew ground bidirectional
-flabel metal4 s 206778 287294 207398 599436 0 FreeSans 2560 90 0 0 vss
-port 311 nsew ground bidirectional
-flabel metal4 s 224778 324 225398 169874 0 FreeSans 2560 90 0 0 vss
-port 311 nsew ground bidirectional
-flabel metal4 s 224778 287294 225398 599436 0 FreeSans 2560 90 0 0 vss
-port 311 nsew ground bidirectional
-flabel metal4 s 242778 324 243398 169874 0 FreeSans 2560 90 0 0 vss
-port 311 nsew ground bidirectional
-flabel metal4 s 242778 287294 243398 599436 0 FreeSans 2560 90 0 0 vss
+flabel metal4 s 242778 324 243398 599436 0 FreeSans 2560 90 0 0 vss
port 311 nsew ground bidirectional
flabel metal4 s 260778 324 261398 599436 0 FreeSans 2560 90 0 0 vss
port 311 nsew ground bidirectional
@@ -145527,423 +141715,124 @@
port 416 nsew signal input
flabel metal2 s 22792 -960 23016 480 0 FreeSans 896 90 0 0 wbs_we_i
port 417 nsew signal input
-rlabel via4 293554 275890 293554 275890 0 vdd
-rlabel via4 297274 281890 297274 281890 0 vss
-rlabel metal3 118272 288232 118272 288232 0 io_in[0]
-rlabel metal2 165522 288904 165522 288904 0 io_in[10]
-rlabel metal2 170226 288904 170226 288904 0 io_in[11]
-rlabel metal2 175042 288904 175042 288904 0 io_in[12]
-rlabel metal2 192360 412944 192360 412944 0 io_in[13]
-rlabel metal2 194040 431536 194040 431536 0 io_in[14]
-rlabel metal2 189042 288904 189042 288904 0 io_in[15]
-rlabel metal2 193746 288904 193746 288904 0 io_in[16]
-rlabel metal2 454328 599592 454328 599592 0 io_in[17]
-rlabel metal2 203560 290486 203560 290486 0 io_in[18]
-rlabel metal2 208264 290598 208264 290598 0 io_in[19]
-rlabel metal3 121408 288008 121408 288008 0 io_in[1]
-rlabel metal2 212562 288904 212562 288904 0 io_in[20]
-rlabel metal3 189952 594776 189952 594776 0 io_in[21]
-rlabel metal2 121688 599592 121688 599592 0 io_in[22]
-rlabel metal2 226954 288904 226954 288904 0 io_in[23]
-rlabel metal3 3990 591416 3990 591416 0 io_in[24]
+rlabel via4 167554 221890 167554 221890 0 vdd
+rlabel via4 171274 227890 171274 227890 0 vss
+rlabel metal2 378840 116816 378840 116816 0 io_in[0]
+rlabel metal2 593880 294896 593880 294896 0 io_in[10]
+rlabel metal1 123592 228928 123592 228928 0 io_in[11]
+rlabel metal3 115122 201992 115122 201992 0 io_in[12]
+rlabel metal3 171752 233464 171752 233464 0 io_in[13]
+rlabel metal3 366268 566216 366268 566216 0 io_in[14]
+rlabel metal2 588056 401940 588056 401940 0 io_in[15]
+rlabel metal2 521192 599592 521192 599592 0 io_in[16]
+rlabel metal1 138376 228928 138376 228928 0 io_in[17]
+rlabel metal2 133784 167314 133784 167314 0 io_in[18]
+rlabel metal3 216440 593880 216440 593880 0 io_in[19]
+rlabel metal3 599592 45976 599592 45976 0 io_in[1]
+rlabel metal2 255528 597170 255528 597170 0 io_in[20]
+rlabel metal3 188160 594776 188160 594776 0 io_in[21]
+rlabel metal3 116634 210728 116634 210728 0 io_in[22]
+rlabel metal2 55664 599592 55664 599592 0 io_in[23]
+rlabel metal3 177702 195944 177702 195944 0 io_in[24]
rlabel metal3 392 548184 392 548184 0 io_in[25]
-rlabel metal2 240786 288904 240786 288904 0 io_in[26]
-rlabel metal3 392 462672 392 462672 0 io_in[27]
+rlabel metal3 392 505848 392 505848 0 io_in[26]
+rlabel metal3 145880 233464 145880 233464 0 io_in[27]
rlabel metal3 392 420336 392 420336 0 io_in[28]
-rlabel metal2 236040 339864 236040 339864 0 io_in[29]
-rlabel metal2 128296 290710 128296 290710 0 io_in[2]
+rlabel metal3 52710 378056 52710 378056 0 io_in[29]
+rlabel metal3 344414 187208 344414 187208 0 io_in[2]
rlabel metal3 392 334824 392 334824 0 io_in[30]
rlabel metal3 392 292488 392 292488 0 io_in[31]
rlabel metal3 392 249312 392 249312 0 io_in[32]
-rlabel metal3 392 206976 392 206976 0 io_in[33]
-rlabel metal3 29190 164696 29190 164696 0 io_in[34]
+rlabel metal2 6776 205688 6776 205688 0 io_in[33]
+rlabel metal2 131656 166978 131656 166978 0 io_in[34]
rlabel metal3 392 121464 392 121464 0 io_in[35]
-rlabel metal2 287826 288904 287826 288904 0 io_in[36]
+rlabel metal3 392 79128 392 79128 0 io_in[36]
rlabel metal3 392 35952 392 35952 0 io_in[37]
-rlabel metal2 595560 217168 595560 217168 0 io_in[3]
-rlabel metal2 420840 226856 420840 226856 0 io_in[4]
-rlabel metal3 142408 288008 142408 288008 0 io_in[5]
-rlabel metal4 155456 288232 155456 288232 0 io_in[6]
-rlabel metal4 151816 287336 151816 287336 0 io_in[7]
-rlabel metal2 156394 288904 156394 288904 0 io_in[8]
-rlabel metal2 264600 331464 264600 331464 0 io_in[9]
-rlabel metal2 119770 288232 119770 288232 0 io_oeb[0]
-rlabel metal2 167496 291046 167496 291046 0 io_oeb[10]
-rlabel metal2 171794 288904 171794 288904 0 io_oeb[11]
-rlabel metal2 176666 288904 176666 288904 0 io_oeb[12]
-rlabel metal2 181552 302400 181552 302400 0 io_oeb[13]
-rlabel metal2 186312 291046 186312 291046 0 io_oeb[14]
-rlabel metal2 190610 288904 190610 288904 0 io_oeb[15]
-rlabel metal2 195314 288904 195314 288904 0 io_oeb[16]
-rlabel metal2 200186 288904 200186 288904 0 io_oeb[17]
-rlabel metal2 205072 302400 205072 302400 0 io_oeb[18]
-rlabel metal2 209426 288904 209426 288904 0 io_oeb[19]
-rlabel metal2 124754 288904 124754 288904 0 io_oeb[1]
-rlabel metal2 214130 288904 214130 288904 0 io_oeb[20]
-rlabel metal2 218834 288904 218834 288904 0 io_oeb[21]
-rlabel metal2 78344 597562 78344 597562 0 io_oeb[22]
-rlabel metal2 10808 599592 10808 599592 0 io_oeb[23]
-rlabel metal2 232946 288904 232946 288904 0 io_oeb[24]
+rlabel metal3 230384 232008 230384 232008 0 io_in[3]
+rlabel metal3 273854 189896 273854 189896 0 io_in[4]
+rlabel metal2 190456 204344 190456 204344 0 io_in[5]
+rlabel metal3 248696 236040 248696 236040 0 io_in[6]
+rlabel metal2 380520 239792 380520 239792 0 io_in[7]
+rlabel metal2 353640 280168 353640 280168 0 io_in[8]
+rlabel metal3 157640 235144 157640 235144 0 io_in[9]
+rlabel metal3 168168 231896 168168 231896 0 io_oeb[0]
+rlabel metal2 190680 330960 190680 330960 0 io_oeb[10]
+rlabel metal2 592200 345968 592200 345968 0 io_oeb[11]
+rlabel metal2 125720 168434 125720 168434 0 io_oeb[12]
+rlabel metal1 127624 228928 127624 228928 0 io_oeb[13]
+rlabel metal2 144424 168378 144424 168378 0 io_oeb[14]
+rlabel metal2 168056 167552 168056 167552 0 io_oeb[15]
+rlabel metal2 477288 597618 477288 597618 0 io_oeb[16]
+rlabel metal2 171304 167762 171304 167762 0 io_oeb[17]
+rlabel metal3 307776 595784 307776 595784 0 io_oeb[18]
+rlabel metal1 142408 228928 142408 228928 0 io_oeb[19]
+rlabel metal3 599592 72744 599592 72744 0 io_oeb[1]
+rlabel metal2 210560 599592 210560 599592 0 io_oeb[20]
+rlabel metal3 147728 233464 147728 233464 0 io_oeb[21]
+rlabel metal2 165256 168322 165256 168322 0 io_oeb[22]
+rlabel metal2 96600 361424 96600 361424 0 io_oeb[23]
+rlabel metal3 4410 562968 4410 562968 0 io_oeb[24]
rlabel metal3 392 519680 392 519680 0 io_oeb[25]
-rlabel metal3 2422 477624 2422 477624 0 io_oeb[26]
-rlabel metal3 2366 434952 2366 434952 0 io_oeb[27]
+rlabel metal3 392 477344 392 477344 0 io_oeb[26]
+rlabel metal2 121576 168602 121576 168602 0 io_oeb[27]
rlabel metal3 392 391832 392 391832 0 io_oeb[28]
-rlabel metal2 256466 288904 256466 288904 0 io_oeb[29]
-rlabel metal2 447720 203392 447720 203392 0 io_oeb[2]
-rlabel metal3 2646 306936 2646 306936 0 io_oeb[30]
+rlabel metal3 4410 349608 4410 349608 0 io_oeb[29]
+rlabel metal1 175336 228928 175336 228928 0 io_oeb[2]
+rlabel metal3 3990 306936 3990 306936 0 io_oeb[30]
rlabel metal3 392 263984 392 263984 0 io_oeb[31]
-rlabel metal3 3990 221704 3990 221704 0 io_oeb[32]
+rlabel metal2 142408 168378 142408 168378 0 io_oeb[32]
rlabel metal3 392 178472 392 178472 0 io_oeb[33]
-rlabel metal2 279986 288904 279986 288904 0 io_oeb[34]
+rlabel metal3 177758 214760 177758 214760 0 io_oeb[34]
rlabel metal3 392 92960 392 92960 0 io_oeb[35]
rlabel metal3 392 50624 392 50624 0 io_oeb[36]
-rlabel metal3 5670 8344 5670 8344 0 io_oeb[37]
-rlabel metal2 595672 233016 595672 233016 0 io_oeb[3]
-rlabel metal4 139272 287952 139272 287952 0 io_oeb[4]
-rlabel metal2 143976 289254 143976 289254 0 io_oeb[5]
-rlabel metal2 148918 288904 148918 288904 0 io_oeb[6]
-rlabel metal2 596120 302344 596120 302344 0 io_oeb[7]
-rlabel metal3 599592 352968 599592 352968 0 io_oeb[8]
-rlabel metal2 162386 288904 162386 288904 0 io_oeb[9]
-rlabel metal4 122024 287336 122024 287336 0 io_out[0]
-rlabel metal2 168658 288904 168658 288904 0 io_out[10]
-rlabel metal2 173418 288904 173418 288904 0 io_out[11]
-rlabel metal2 178290 288904 178290 288904 0 io_out[12]
-rlabel metal3 599592 539504 599592 539504 0 io_out[13]
-rlabel metal2 187474 288904 187474 288904 0 io_out[14]
-rlabel metal2 192178 288904 192178 288904 0 io_out[15]
-rlabel metal2 499184 599592 499184 599592 0 io_out[16]
-rlabel metal2 201810 288904 201810 288904 0 io_out[17]
-rlabel metal2 206696 290542 206696 290542 0 io_out[18]
-rlabel metal2 210994 288904 210994 288904 0 io_out[19]
-rlabel metal4 126728 287392 126728 287392 0 io_out[1]
-rlabel metal2 215698 288904 215698 288904 0 io_out[20]
-rlabel metal2 166544 599592 166544 599592 0 io_out[21]
+rlabel metal3 392 7448 392 7448 0 io_oeb[37]
+rlabel metal1 125608 228928 125608 228928 0 io_oeb[3]
+rlabel metal2 595784 211288 595784 211288 0 io_oeb[4]
+rlabel metal2 195720 198856 195720 198856 0 io_oeb[5]
+rlabel metal2 123704 168546 123704 168546 0 io_oeb[6]
+rlabel metal2 595672 276304 595672 276304 0 io_oeb[7]
+rlabel metal2 373800 259504 373800 259504 0 io_oeb[8]
+rlabel metal3 284774 204008 284774 204008 0 io_oeb[9]
+rlabel metal3 308294 191912 308294 191912 0 io_out[0]
+rlabel metal2 163352 168602 163352 168602 0 io_out[10]
+rlabel metal3 117642 212744 117642 212744 0 io_out[11]
+rlabel metal2 467880 339080 467880 339080 0 io_out[12]
+rlabel metal3 116746 199976 116746 199976 0 io_out[13]
+rlabel metal4 118104 169512 118104 169512 0 io_out[14]
+rlabel metal2 565208 599592 565208 599592 0 io_out[15]
+rlabel metal2 169400 167650 169400 167650 0 io_out[16]
+rlabel metal2 382200 406224 382200 406224 0 io_out[17]
+rlabel metal2 148568 167538 148568 167538 0 io_out[18]
+rlabel metal3 116690 181160 116690 181160 0 io_out[19]
+rlabel metal3 116746 191800 116746 191800 0 io_out[1]
+rlabel metal2 117544 168714 117544 168714 0 io_out[20]
+rlabel metal2 167048 597562 167048 597562 0 io_out[21]
rlabel metal3 101080 594776 101080 594776 0 io_out[22]
-rlabel metal2 230342 288792 230342 288792 0 io_out[23]
-rlabel metal2 234514 288904 234514 288904 0 io_out[24]
-rlabel metal3 2310 534520 2310 534520 0 io_out[25]
+rlabel metal2 71400 414120 71400 414120 0 io_out[23]
+rlabel metal3 392 576688 392 576688 0 io_out[24]
+rlabel metal3 5670 534520 5670 534520 0 io_out[25]
rlabel metal3 392 491176 392 491176 0 io_out[26]
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+rlabel metal3 2310 22680 2310 22680 0 io_out[37]
+rlabel metal2 150010 169288 150010 169288 0 io_out[3]
+rlabel metal3 116634 183176 116634 183176 0 io_out[4]
+rlabel metal1 163240 228928 163240 228928 0 io_out[5]
+rlabel metal1 119560 228928 119560 228928 0 io_out[6]
+rlabel metal2 192360 269304 192360 269304 0 io_out[7]
+rlabel metal2 355320 252560 355320 252560 0 io_out[8]
+rlabel metal3 116802 185192 116802 185192 0 io_out[9]
+rlabel metal2 12488 392 12488 392 0 wb_clk_i
+rlabel metal3 96824 163800 96824 163800 0 wb_rst_i
<< properties >>
string FIXED_BBOX 0 0 600000 600000
<< end >>
diff --git a/maglef/user_proj_example.mag b/maglef/user_proj_example.mag
index 21e4044..039dbfe 100644
--- a/maglef/user_proj_example.mag
+++ b/maglef/user_proj_example.mag
@@ -1,7 +1,7 @@
magic
tech gf180mcuC
magscale 1 5
-timestamp 1669047494
+timestamp 1669194846
<< obsm1 >>
rect 672 855 89320 58561
<< metal2 >>
@@ -1719,7 +1719,7 @@
string LEFclass BLOCK
string LEFview TRUE
string GDS_END 3433480
-string GDS_FILE /home/marwan/caravel_user_project-gf180mcu/openlane/user_proj_example/runs/22_11_21_08_16/results/signoff/user_proj_example.magic.gds
+string GDS_FILE /home/matt/work/asic-workshop/shuttle8/gf180-vga-clock/openlane/user_proj_example/runs/22_11_23_10_12/results/signoff/user_proj_example.magic.gds
string GDS_START 200846
<< end >>
diff --git a/maglef/user_project_wrapper.mag b/maglef/user_project_wrapper.mag
index 7a3ef62..7229408 100644
--- a/maglef/user_project_wrapper.mag
+++ b/maglef/user_project_wrapper.mag
@@ -1,9 +1,9 @@
magic
tech gf180mcuC
magscale 1 5
-timestamp 1669047632
+timestamp 1669196087
<< obsm1 >>
-rect 59422 76847 148070 143061
+rect 59422 86038 88038 114561
<< metal2 >>
rect 5796 299760 5908 300480
rect 16884 299760 16996 300480
@@ -362,311 +362,311 @@
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rect 272050 299730 282966 299810
rect 283138 299730 294054 299810
-rect 294226 299730 299082 299810
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+rect 169570 182 170350 270
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+rect 174330 182 175110 270
+rect 175282 182 176062 270
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+rect 179090 182 179870 270
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+rect 183850 182 184630 270
+rect 184802 182 185582 270
+rect 185754 182 186534 270
+rect 186706 182 187486 270
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+rect 188610 182 189390 270
+rect 189562 182 190342 270
+rect 190514 182 191294 270
+rect 191466 182 192246 270
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+rect 193370 182 194150 270
+rect 194322 182 195102 270
+rect 195274 182 196054 270
+rect 196226 182 197006 270
+rect 197178 182 197958 270
+rect 198130 182 198910 270
+rect 199082 182 199862 270
+rect 200034 182 200814 270
+rect 200986 182 201766 270
+rect 201938 182 202718 270
+rect 202890 182 203670 270
+rect 203842 182 204622 270
+rect 204794 182 205574 270
+rect 205746 182 206526 270
+rect 206698 182 207478 270
+rect 207650 182 208430 270
+rect 208602 182 209382 270
+rect 209554 182 210334 270
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+rect 211458 182 212238 270
+rect 212410 182 213190 270
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+rect 214314 182 215094 270
+rect 215266 182 216046 270
+rect 216218 182 216998 270
+rect 217170 182 217950 270
+rect 218122 182 218902 270
+rect 219074 182 219854 270
+rect 220026 182 220806 270
+rect 220978 182 221758 270
+rect 221930 182 222710 270
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+rect 223834 182 224614 270
+rect 224786 182 225566 270
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+rect 226690 182 227470 270
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+rect 229546 182 230326 270
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+rect 231450 182 232230 270
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+rect 246682 182 247462 270
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+rect 267626 182 268406 270
+rect 268578 182 269358 270
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+rect 271434 182 272214 270
+rect 272386 182 273166 270
+rect 273338 182 274118 270
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+rect 277146 182 277926 270
+rect 278098 182 278878 270
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+rect 280002 182 280782 270
+rect 280954 182 281734 270
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+rect 289522 182 290302 270
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+rect 292378 182 293158 270
+rect 293330 182 297906 270
<< metal3 >>
rect 299760 296548 300480 296660
rect -480 295708 240 295820
@@ -756,7 +756,7 @@
rect -480 4116 240 4228
rect 299760 3332 300480 3444
<< obsm3 >>
-rect 182 296690 299810 299082
+rect 182 296690 299810 297906
rect 182 296518 299730 296690
rect 182 295850 299810 296518
rect 270 295678 299810 295850
@@ -927,8 +927,7 @@
rect 182 4258 299810 9966
rect 270 4086 299810 4258
rect 182 3474 299810 4086
-rect 182 3302 299730 3474
-rect 182 14 299810 3302
+rect 182 3374 299730 3474
<< metal4 >>
rect -6 162 304 299718
rect 474 642 784 299238
@@ -946,34 +945,27 @@
rect 49389 162 49699 299718
rect 56529 162 56839 299718
rect 58389 162 58699 299718
-rect 65529 162 65839 299718
-rect 67389 162 67699 299718
-rect 74529 162 74839 299718
-rect 76389 143966 76699 299718
+rect 65529 107303 65839 299718
+rect 67389 107303 67699 299718
+rect 74529 107303 74839 299718
+rect 76389 113782 76699 299718
+rect 65529 162 65839 94121
+rect 67389 162 67699 94121
+rect 74529 162 74839 94121
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-rect 92529 143647 92839 299718
-rect 94389 143647 94699 299718
-rect 101529 143647 101839 299718
-rect 103389 143647 103699 299718
-rect 110529 143647 110839 299718
-rect 112389 143647 112699 299718
-rect 119529 143647 119839 299718
-rect 121389 143647 121699 299718
-rect 128529 143647 128839 299718
-rect 92529 162 92839 84937
-rect 94389 162 94699 84937
-rect 101529 162 101839 84937
-rect 103389 162 103699 84937
-rect 110529 162 110839 84937
-rect 112389 162 112699 84937
-rect 119529 162 119839 84937
-rect 121389 162 121699 84937
-rect 128529 162 128839 84937
+rect 92529 162 92839 299718
+rect 94389 162 94699 299718
+rect 101529 162 101839 299718
+rect 103389 162 103699 299718
+rect 110529 162 110839 299718
+rect 112389 162 112699 299718
+rect 119529 162 119839 299718
+rect 121389 162 121699 299718
+rect 128529 162 128839 299718
rect 130389 162 130699 299718
-rect 137529 143966 137839 299718
-rect 137529 162 137839 85010
+rect 137529 162 137839 299718
rect 139389 162 139699 299718
rect 146529 162 146839 299718
rect 148389 162 148699 299718
@@ -1012,42 +1004,19 @@
rect 299208 642 299518 299238
rect 299688 162 299998 299718
<< obsm4 >>
-rect 60974 2193 65499 144191
-rect 65869 2193 67359 144191
-rect 67729 2193 74499 144191
-rect 74869 143936 76359 144191
-rect 76729 143936 83499 144191
-rect 74869 85040 83499 143936
-rect 74869 2193 76359 85040
-rect 76729 2193 83499 85040
-rect 83869 2193 85359 144191
-rect 85729 143617 92499 144191
-rect 92869 143617 94359 144191
-rect 94729 143617 101499 144191
-rect 101869 143617 103359 144191
-rect 103729 143617 110499 144191
-rect 110869 143617 112359 144191
-rect 112729 143617 119499 144191
-rect 119869 143617 121359 144191
-rect 121729 143617 128499 144191
-rect 128869 143617 130359 144191
-rect 85729 84967 130359 143617
-rect 85729 2193 92499 84967
-rect 92869 2193 94359 84967
-rect 94729 2193 101499 84967
-rect 101869 2193 103359 84967
-rect 103729 2193 110499 84967
-rect 110869 2193 112359 84967
-rect 112729 2193 119499 84967
-rect 119869 2193 121359 84967
-rect 121729 2193 128499 84967
-rect 128869 2193 130359 84967
-rect 130729 143936 137499 144191
-rect 137869 143936 139359 144191
-rect 130729 85040 139359 143936
-rect 130729 2193 137499 85040
-rect 137869 2193 139359 85040
-rect 139729 2193 145614 144191
+rect 59038 107273 65499 112754
+rect 65869 107273 67359 112754
+rect 67729 107273 74499 112754
+rect 74869 107273 83499 112754
+rect 59038 94151 83499 107273
+rect 59038 83057 65499 94151
+rect 65869 83057 67359 94151
+rect 67729 83057 74499 94151
+rect 74869 85040 83499 94151
+rect 74869 83057 76359 85040
+rect 76729 83057 83499 85040
+rect 83869 83057 85359 112754
+rect 85729 83057 89026 112754
<< metal5 >>
rect -6 299408 299998 299718
rect 474 298928 299518 299238
@@ -1762,35 +1731,27 @@
port 311 nsew power bidirectional
rlabel metal4 s 56529 162 56839 299718 6 vdd
port 311 nsew power bidirectional
-rlabel metal4 s 65529 162 65839 299718 6 vdd
+rlabel metal4 s 65529 162 65839 94121 6 vdd
port 311 nsew power bidirectional
-rlabel metal4 s 74529 162 74839 299718 6 vdd
+rlabel metal4 s 65529 107303 65839 299718 6 vdd
+port 311 nsew power bidirectional
+rlabel metal4 s 74529 162 74839 94121 6 vdd
+port 311 nsew power bidirectional
+rlabel metal4 s 74529 107303 74839 299718 6 vdd
port 311 nsew power bidirectional
rlabel metal4 s 83529 162 83839 299718 6 vdd
port 311 nsew power bidirectional
-rlabel metal4 s 92529 162 92839 84937 6 vdd
+rlabel metal4 s 92529 162 92839 299718 6 vdd
port 311 nsew power bidirectional
-rlabel metal4 s 92529 143647 92839 299718 6 vdd
+rlabel metal4 s 101529 162 101839 299718 6 vdd
port 311 nsew power bidirectional
-rlabel metal4 s 101529 162 101839 84937 6 vdd
+rlabel metal4 s 110529 162 110839 299718 6 vdd
port 311 nsew power bidirectional
-rlabel metal4 s 101529 143647 101839 299718 6 vdd
+rlabel metal4 s 119529 162 119839 299718 6 vdd
port 311 nsew power bidirectional
-rlabel metal4 s 110529 162 110839 84937 6 vdd
+rlabel metal4 s 128529 162 128839 299718 6 vdd
port 311 nsew power bidirectional
-rlabel metal4 s 110529 143647 110839 299718 6 vdd
-port 311 nsew power bidirectional
-rlabel metal4 s 119529 162 119839 84937 6 vdd
-port 311 nsew power bidirectional
-rlabel metal4 s 119529 143647 119839 299718 6 vdd
-port 311 nsew power bidirectional
-rlabel metal4 s 128529 162 128839 84937 6 vdd
-port 311 nsew power bidirectional
-rlabel metal4 s 128529 143647 128839 299718 6 vdd
-port 311 nsew power bidirectional
-rlabel metal4 s 137529 162 137839 85010 6 vdd
-port 311 nsew power bidirectional
-rlabel metal4 s 137529 143966 137839 299718 6 vdd
+rlabel metal4 s 137529 162 137839 299718 6 vdd
port 311 nsew power bidirectional
rlabel metal4 s 146529 162 146839 299718 6 vdd
port 311 nsew power bidirectional
@@ -1914,29 +1875,23 @@
port 312 nsew ground bidirectional
rlabel metal4 s 58389 162 58699 299718 6 vss
port 312 nsew ground bidirectional
-rlabel metal4 s 67389 162 67699 299718 6 vss
+rlabel metal4 s 67389 162 67699 94121 6 vss
+port 312 nsew ground bidirectional
+rlabel metal4 s 67389 107303 67699 299718 6 vss
port 312 nsew ground bidirectional
rlabel metal4 s 76389 162 76699 85010 6 vss
port 312 nsew ground bidirectional
-rlabel metal4 s 76389 143966 76699 299718 6 vss
+rlabel metal4 s 76389 113782 76699 299718 6 vss
port 312 nsew ground bidirectional
rlabel metal4 s 85389 162 85699 299718 6 vss
port 312 nsew ground bidirectional
-rlabel metal4 s 94389 162 94699 84937 6 vss
+rlabel metal4 s 94389 162 94699 299718 6 vss
port 312 nsew ground bidirectional
-rlabel metal4 s 94389 143647 94699 299718 6 vss
+rlabel metal4 s 103389 162 103699 299718 6 vss
port 312 nsew ground bidirectional
-rlabel metal4 s 103389 162 103699 84937 6 vss
+rlabel metal4 s 112389 162 112699 299718 6 vss
port 312 nsew ground bidirectional
-rlabel metal4 s 103389 143647 103699 299718 6 vss
-port 312 nsew ground bidirectional
-rlabel metal4 s 112389 162 112699 84937 6 vss
-port 312 nsew ground bidirectional
-rlabel metal4 s 112389 143647 112699 299718 6 vss
-port 312 nsew ground bidirectional
-rlabel metal4 s 121389 162 121699 84937 6 vss
-port 312 nsew ground bidirectional
-rlabel metal4 s 121389 143647 121699 299718 6 vss
+rlabel metal4 s 121389 162 121699 299718 6 vss
port 312 nsew ground bidirectional
rlabel metal4 s 130389 162 130699 299718 6 vss
port 312 nsew ground bidirectional
@@ -2258,8 +2213,8 @@
string FIXED_BBOX 0 0 300000 300000
string LEFclass BLOCK
string LEFview TRUE
-string GDS_END 6363900
-string GDS_FILE /home/marwan/caravel_user_project-gf180mcu/openlane/user_project_wrapper/runs/22_11_21_08_19/results/signoff/user_project_wrapper.magic.gds
-string GDS_START 3433534
+string GDS_END 4813198
+string GDS_FILE /home/matt/work/asic-workshop/shuttle8/gf180-vga-clock/openlane/user_project_wrapper/runs/22_11_23_10_34/results/signoff/user_project_wrapper.magic.gds
+string GDS_START 2095288
<< end >>
diff --git a/openlane/user_project_wrapper/config.tcl b/openlane/user_project_wrapper/config.tcl
index df19160..e83f17c 100644
--- a/openlane/user_project_wrapper/config.tcl
+++ b/openlane/user_project_wrapper/config.tcl
@@ -34,14 +34,14 @@
## Clock configurations
set ::env(CLOCK_PORT) "user_clock2"
-set ::env(CLOCK_NET) "mprj.clk"
+set ::env(CLOCK_NET) "wrapped_vga_clock.wb_clk_i"
set ::env(CLOCK_PERIOD) "10"
## Internal Macros
### Macro PDN Connections
set ::env(FP_PDN_MACRO_HOOKS) "\
- mprj vdd vss vdd vss"
+ wrapped_vga_clock vdd vss vdd vss"
### Macro Placement
set ::env(MACRO_PLACEMENT_CFG) $::env(DESIGN_DIR)/macro.cfg
@@ -49,13 +49,13 @@
### Black-box verilog and views
set ::env(VERILOG_FILES_BLACKBOX) "\
$::env(CARAVEL_ROOT)/verilog/rtl/defines.v \
- $::env(DESIGN_DIR)/../../verilog/rtl/user_proj_example.v"
+ $::env(DESIGN_DIR)/../../verilog/rtl/wrapped_vga_clock.v"
set ::env(EXTRA_LEFS) "\
- $::env(DESIGN_DIR)/../../lef/user_proj_example.lef"
+ $::env(DESIGN_DIR)/../../lef/wrapped_vga_clock.lef"
set ::env(EXTRA_GDS_FILES) "\
- $::env(DESIGN_DIR)/../../gds/user_proj_example.gds"
+ $::env(DESIGN_DIR)/../../gds/wrapped_vga_clock.gds"
set ::env(RT_MAX_LAYER) {Metal4}
@@ -80,4 +80,4 @@
set ::env(CLOCK_TREE_SYNTH) 0
# YOU ARE NOT ALLOWED TO CHANGE ANY VARIABLES DEFINED IN THE FIXED WRAPPER CFGS
-source $::env(DESIGN_DIR)/fixed_dont_change/fixed_wrapper_cfgs.tcl
\ No newline at end of file
+source $::env(DESIGN_DIR)/fixed_dont_change/fixed_wrapper_cfgs.tcl
diff --git a/openlane/user_project_wrapper/macro.cfg b/openlane/user_project_wrapper/macro.cfg
index a7365ab..7ec5814 100644
--- a/openlane/user_project_wrapper/macro.cfg
+++ b/openlane/user_project_wrapper/macro.cfg
@@ -1 +1 @@
-mprj 1175 1690 N
+wrapped_vga_clock 1175 1690 N
diff --git a/openlane/wrapped_vga_clock/config.tcl b/openlane/wrapped_vga_clock/config.tcl
new file mode 100644
index 0000000..62e868f
--- /dev/null
+++ b/openlane/wrapped_vga_clock/config.tcl
@@ -0,0 +1,46 @@
+# User config
+set script_dir [file dirname [file normalize [info script]]]
+
+# name of your project, should also match the name of the top module
+set ::env(DESIGN_NAME) wrapped_vga_clock
+
+set ::env(STD_CELL_LIBRARY) "gf180mcu_fd_sc_mcu7t5v0"
+
+# add your source files here
+set ::env(VERILOG_FILES) "$::env(DESIGN_DIR)/../../verilog/rtl/wrapped_vga_clock.v \
+ $::env(DESIGN_DIR)/../../verilog/rtl/vga-clock/rtl/button_pulse.v \
+ $::env(DESIGN_DIR)/../../verilog/rtl/vga-clock/rtl/digit.v \
+ $::env(DESIGN_DIR)/../../verilog/rtl/vga-clock/rtl/fontROM.v \
+ $::env(DESIGN_DIR)/../../verilog/rtl/vga-clock/rtl/top.v \
+ $::env(DESIGN_DIR)/../../verilog/rtl/vga-clock/rtl/vga_clock.v \
+ $::env(DESIGN_DIR)/../../verilog/rtl/vga-clock/rtl/VgaSyncGen.v"
+
+
+# set absolute size of the die to 300 x 300 um
+set ::env(DIE_AREA) "0 0 300 300"
+set ::env(FP_SIZING) absolute
+
+set ::env(FP_CORE_UTIL) 40
+set ::env(PL_TARGET_DENSITY) [ expr ($::env(FP_CORE_UTIL)+5) / 100.0 ]
+
+# define number of IO pads
+set ::env(SYNTH_DEFINES) "MPRJ_IO_PADS=38"
+
+# clock period is ns
+# need 40MHz for VGA out = 25ns
+set ::env(CLOCK_PERIOD) "30"
+set ::env(CLOCK_PORT) "wb_clk_i"
+
+# macro needs to work inside Caravel, so can't be core and can't use metal 5
+set ::env(DESIGN_IS_CORE) 0
+set ::env(RT_MAX_LAYER) {Metal4}
+
+# define power straps so the macro works inside Caravel's PDN
+set ::env(VDD_NETS) [list {vdd}]
+set ::env(GND_NETS) [list {vss}]
+
+# regular pin order seems to help with aggregating all the macros for the group project
+#set ::env(FP_PIN_ORDER_CFG) $script_dir/pin_order.cfg
+
+set ::env(FP_IO_VTHICKNESS_MULT) 4
+set ::env(FP_IO_HTHICKNESS_MULT) 4
diff --git a/sdc/user_proj_example.sdc b/sdc/user_proj_example.sdc
index ec042e2..d2691a6 100644
--- a/sdc/user_proj_example.sdc
+++ b/sdc/user_proj_example.sdc
@@ -1,6 +1,6 @@
###############################################################################
# Created by write_sdc
-# Mon Nov 21 16:17:28 2022
+# Wed Nov 23 09:13:32 2022
###############################################################################
current_design user_proj_example
###############################################################################
diff --git a/sdc/user_project_wrapper.sdc b/sdc/user_project_wrapper.sdc
index 18a72bd..c746f67 100644
--- a/sdc/user_project_wrapper.sdc
+++ b/sdc/user_project_wrapper.sdc
@@ -1,6 +1,6 @@
###############################################################################
# Created by write_sdc
-# Mon Nov 21 16:19:52 2022
+# Wed Nov 23 09:34:23 2022
###############################################################################
current_design user_project_wrapper
###############################################################################
diff --git a/sdf/multicorner/nom/user_project_wrapper.ff.sdf b/sdf/multicorner/nom/user_project_wrapper.ff.sdf
index 27fbd8f..388c30e 100644
--- a/sdf/multicorner/nom/user_project_wrapper.ff.sdf
+++ b/sdf/multicorner/nom/user_project_wrapper.ff.sdf
@@ -1,7 +1,7 @@
(DELAYFILE
(SDFVERSION "3.0")
(DESIGN "user_project_wrapper")
- (DATE "Mon Nov 21 16:20:23 2022")
+ (DATE "Wed Nov 23 09:34:43 2022")
(VENDOR "Parallax")
(PROGRAM "STA")
(VERSION "2.3.2")
@@ -12,421 +12,122 @@
(INSTANCE)
(DELAY
(ABSOLUTE
- (INTERCONNECT io_in[0] mprj.io_in[0] (1.697:1.697:1.697) (1.092:1.092:1.092))
- (INTERCONNECT io_in[10] mprj.io_in[10] (1.200:1.200:1.200) (0.770:0.770:0.770))
- (INTERCONNECT io_in[11] mprj.io_in[11] (1.179:1.179:1.179) (0.757:0.757:0.757))
- (INTERCONNECT io_in[12] mprj.io_in[12] (1.253:1.253:1.253) (0.804:0.804:0.804))
- (INTERCONNECT io_in[13] mprj.io_in[13] (1.413:1.413:1.413) (0.907:0.907:0.907))
- (INTERCONNECT io_in[14] mprj.io_in[14] (1.443:1.443:1.443) (0.926:0.926:0.926))
- (INTERCONNECT io_in[15] mprj.io_in[15] (1.536:1.536:1.536) (0.987:0.987:0.987))
- (INTERCONNECT io_in[16] mprj.io_in[16] (1.697:1.697:1.697) (1.089:1.089:1.089))
- (INTERCONNECT io_in[17] mprj.io_in[17] (1.220:1.220:1.220) (0.782:0.782:0.782))
- (INTERCONNECT io_in[18] mprj.io_in[18] (2.305:2.305:2.305) (1.468:1.468:1.468))
- (INTERCONNECT io_in[19] mprj.io_in[19] (2.040:2.040:2.040) (1.300:1.300:1.300))
- (INTERCONNECT io_in[1] mprj.io_in[1] (2.454:2.454:2.454) (1.572:1.572:1.572))
- (INTERCONNECT io_in[20] mprj.io_in[20] (0.745:0.745:0.745) (0.475:0.475:0.475))
- (INTERCONNECT io_in[21] mprj.io_in[21] (0.714:0.714:0.714) (0.456:0.456:0.456))
- (INTERCONNECT io_in[22] mprj.io_in[22] (1.044:1.044:1.044) (0.668:0.668:0.668))
- (INTERCONNECT io_in[23] mprj.io_in[23] (0.996:0.996:0.996) (0.638:0.638:0.638))
- (INTERCONNECT io_in[24] mprj.io_in[24] (1.380:1.380:1.380) (0.883:0.883:0.883))
- (INTERCONNECT io_in[25] mprj.io_in[25] (1.097:1.097:1.097) (0.702:0.702:0.702))
- (INTERCONNECT io_in[26] mprj.io_in[26] (0.929:0.929:0.929) (0.594:0.594:0.594))
- (INTERCONNECT io_in[27] mprj.io_in[27] (2.668:2.668:2.668) (1.693:1.693:1.693))
- (INTERCONNECT io_in[28] mprj.io_in[28] (0.821:0.821:0.821) (0.524:0.524:0.524))
- (INTERCONNECT io_in[29] mprj.io_in[29] (0.805:0.805:0.805) (0.514:0.514:0.514))
- (INTERCONNECT io_in[2] mprj.io_in[2] (3.342:3.342:3.342) (2.123:2.123:2.123))
- (INTERCONNECT io_in[30] mprj.io_in[30] (0.608:0.608:0.608) (0.387:0.387:0.387))
- (INTERCONNECT io_in[31] mprj.io_in[31] (1.976:1.976:1.976) (1.249:1.249:1.249))
- (INTERCONNECT io_in[32] mprj.io_in[32] (3.009:3.009:3.009) (1.905:1.905:1.905))
- (INTERCONNECT io_in[33] mprj.io_in[33] (1.724:1.724:1.724) (1.096:1.096:1.096))
- (INTERCONNECT io_in[34] mprj.io_in[34] (3.135:3.135:3.135) (1.986:1.986:1.986))
- (INTERCONNECT io_in[35] mprj.io_in[35] (0.985:0.985:0.985) (0.630:0.630:0.630))
- (INTERCONNECT io_in[36] mprj.io_in[36] (1.493:1.493:1.493) (0.954:0.954:0.954))
- (INTERCONNECT io_in[37] mprj.io_in[37] (1.212:1.212:1.212) (0.777:0.777:0.777))
- (INTERCONNECT io_in[3] mprj.io_in[3] (2.373:2.373:2.373) (1.519:1.519:1.519))
- (INTERCONNECT io_in[4] mprj.io_in[4] (2.419:2.419:2.419) (1.549:1.549:1.549))
- (INTERCONNECT io_in[5] mprj.io_in[5] (2.964:2.964:2.964) (1.882:1.882:1.882))
- (INTERCONNECT io_in[6] mprj.io_in[6] (2.501:2.501:2.501) (1.591:1.591:1.591))
- (INTERCONNECT io_in[7] mprj.io_in[7] (3.035:3.035:3.035) (1.920:1.920:1.920))
- (INTERCONNECT io_in[8] mprj.io_in[8] (0.948:0.948:0.948) (0.609:0.609:0.609))
- (INTERCONNECT io_in[9] mprj.io_in[9] (1.955:1.955:1.955) (1.248:1.248:1.248))
- (INTERCONNECT la_data_in[0] mprj.la_data_in[0] (1.618:1.618:1.618) (1.028:1.028:1.028))
- (INTERCONNECT la_data_in[10] mprj.la_data_in[10] (0.856:0.856:0.856) (0.544:0.544:0.544))
- (INTERCONNECT la_data_in[11] mprj.la_data_in[11] (2.118:2.118:2.118) (1.351:1.351:1.351))
- (INTERCONNECT la_data_in[12] mprj.la_data_in[12] (0.881:0.881:0.881) (0.560:0.560:0.560))
- (INTERCONNECT la_data_in[13] mprj.la_data_in[13] (0.998:0.998:0.998) (0.633:0.633:0.633))
- (INTERCONNECT la_data_in[14] mprj.la_data_in[14] (2.896:2.896:2.896) (1.845:1.845:1.845))
- (INTERCONNECT la_data_in[15] mprj.la_data_in[15] (0.800:0.800:0.800) (0.510:0.510:0.510))
- (INTERCONNECT la_data_in[16] mprj.la_data_in[16] (2.065:2.065:2.065) (1.317:1.317:1.317))
- (INTERCONNECT la_data_in[17] mprj.la_data_in[17] (2.241:2.241:2.241) (1.429:1.429:1.429))
- (INTERCONNECT la_data_in[18] mprj.la_data_in[18] (2.109:2.109:2.109) (1.344:1.344:1.344))
- (INTERCONNECT la_data_in[19] mprj.la_data_in[19] (1.422:1.422:1.422) (0.906:0.906:0.906))
- (INTERCONNECT la_data_in[1] mprj.la_data_in[1] (1.586:1.586:1.586) (1.009:1.009:1.009))
- (INTERCONNECT la_data_in[20] mprj.la_data_in[20] (1.224:1.224:1.224) (0.778:0.778:0.778))
- (INTERCONNECT la_data_in[21] mprj.la_data_in[21] (1.974:1.974:1.974) (1.258:1.258:1.258))
- (INTERCONNECT la_data_in[22] mprj.la_data_in[22] (1.531:1.531:1.531) (0.975:0.975:0.975))
- (INTERCONNECT la_data_in[23] mprj.la_data_in[23] (1.705:1.705:1.705) (1.083:1.083:1.083))
- (INTERCONNECT la_data_in[24] mprj.la_data_in[24] (2.769:2.769:2.769) (1.766:1.766:1.766))
- (INTERCONNECT la_data_in[25] mprj.la_data_in[25] (1.297:1.297:1.297) (0.826:0.826:0.826))
- (INTERCONNECT la_data_in[26] mprj.la_data_in[26] (1.382:1.382:1.382) (0.880:0.880:0.880))
- (INTERCONNECT la_data_in[27] mprj.la_data_in[27] (2.130:2.130:2.130) (1.358:1.358:1.358))
- (INTERCONNECT la_data_in[28] mprj.la_data_in[28] (1.498:1.498:1.498) (0.954:0.954:0.954))
- (INTERCONNECT la_data_in[29] mprj.la_data_in[29] (1.571:1.571:1.571) (1.000:1.000:1.000))
- (INTERCONNECT la_data_in[2] mprj.la_data_in[2] (1.295:1.295:1.295) (0.821:0.821:0.821))
- (INTERCONNECT la_data_in[30] mprj.la_data_in[30] (2.290:2.290:2.290) (1.458:1.458:1.458))
- (INTERCONNECT la_data_in[31] mprj.la_data_in[31] (2.246:2.246:2.246) (1.425:1.425:1.425))
- (INTERCONNECT la_data_in[32] mprj.la_data_in[32] (2.328:2.328:2.328) (1.478:1.478:1.478))
- (INTERCONNECT la_data_in[33] mprj.la_data_in[33] (1.752:1.752:1.752) (1.114:1.114:1.114))
- (INTERCONNECT la_data_in[34] mprj.la_data_in[34] (1.830:1.830:1.830) (1.164:1.164:1.164))
- (INTERCONNECT la_data_in[35] mprj.la_data_in[35] (2.090:2.090:2.090) (1.331:1.331:1.331))
- (INTERCONNECT la_data_in[36] mprj.la_data_in[36] (1.872:1.872:1.872) (1.189:1.189:1.189))
- (INTERCONNECT la_data_in[37] mprj.la_data_in[37] (1.838:1.838:1.838) (1.168:1.168:1.168))
- (INTERCONNECT la_data_in[38] mprj.la_data_in[38] (2.421:2.421:2.421) (1.537:1.537:1.537))
- (INTERCONNECT la_data_in[39] mprj.la_data_in[39] (2.057:2.057:2.057) (1.309:1.309:1.309))
- (INTERCONNECT la_data_in[3] mprj.la_data_in[3] (0.558:0.558:0.558) (0.354:0.354:0.354))
- (INTERCONNECT la_data_in[40] mprj.la_data_in[40] (2.930:2.930:2.930) (1.859:1.859:1.859))
- (INTERCONNECT la_data_in[41] mprj.la_data_in[41] (1.882:1.882:1.882) (1.196:1.196:1.196))
- (INTERCONNECT la_data_in[42] mprj.la_data_in[42] (2.382:2.382:2.382) (1.513:1.513:1.513))
- (INTERCONNECT la_data_in[43] mprj.la_data_in[43] (3.270:3.270:3.270) (2.075:2.075:2.075))
- (INTERCONNECT la_data_in[44] mprj.la_data_in[44] (1.688:1.688:1.688) (1.074:1.074:1.074))
- (INTERCONNECT la_data_in[45] mprj.la_data_in[45] (2.906:2.906:2.906) (1.843:1.843:1.843))
- (INTERCONNECT la_data_in[46] mprj.la_data_in[46] (2.510:2.510:2.510) (1.597:1.597:1.597))
- (INTERCONNECT la_data_in[47] mprj.la_data_in[47] (3.319:3.319:3.319) (2.103:2.103:2.103))
- (INTERCONNECT la_data_in[48] mprj.la_data_in[48] (3.030:3.030:3.030) (1.921:1.921:1.921))
- (INTERCONNECT la_data_in[49] mprj.la_data_in[49] (2.735:2.735:2.735) (1.740:1.740:1.740))
- (INTERCONNECT la_data_in[4] mprj.la_data_in[4] (1.581:1.581:1.581) (1.006:1.006:1.006))
- (INTERCONNECT la_data_in[50] mprj.la_data_in[50] (3.715:3.715:3.715) (2.351:2.351:2.351))
- (INTERCONNECT la_data_in[51] mprj.la_data_in[51] (3.781:3.781:3.781) (2.393:2.393:2.393))
- (INTERCONNECT la_data_in[52] mprj.la_data_in[52] (3.617:3.617:3.617) (2.289:2.289:2.289))
- (INTERCONNECT la_data_in[53] mprj.la_data_in[53] (3.393:3.393:3.393) (2.148:2.148:2.148))
- (INTERCONNECT la_data_in[54] mprj.la_data_in[54] (1.735:1.735:1.735) (1.105:1.105:1.105))
- (INTERCONNECT la_data_in[55] mprj.la_data_in[55] (1.748:1.748:1.748) (1.114:1.114:1.114))
- (INTERCONNECT la_data_in[56] mprj.la_data_in[56] (3.524:3.524:3.524) (2.230:2.230:2.230))
- (INTERCONNECT la_data_in[57] mprj.la_data_in[57] (2.403:2.403:2.403) (1.528:1.528:1.528))
- (INTERCONNECT la_data_in[58] mprj.la_data_in[58] (2.095:2.095:2.095) (1.333:1.333:1.333))
- (INTERCONNECT la_data_in[59] mprj.la_data_in[59] (2.215:2.215:2.215) (1.410:1.410:1.410))
- (INTERCONNECT la_data_in[5] mprj.la_data_in[5] (1.577:1.577:1.577) (1.003:1.003:1.003))
- (INTERCONNECT la_data_in[60] mprj.la_data_in[60] (2.431:2.431:2.431) (1.544:1.544:1.544))
- (INTERCONNECT la_data_in[61] mprj.la_data_in[61] (2.902:2.902:2.902) (1.846:1.846:1.846))
- (INTERCONNECT la_data_in[62] mprj.la_data_in[62] (2.470:2.470:2.470) (1.569:1.569:1.569))
- (INTERCONNECT la_data_in[63] mprj.la_data_in[63] (2.117:2.117:2.117) (1.348:1.348:1.348))
- (INTERCONNECT la_data_in[6] mprj.la_data_in[6] (1.378:1.378:1.378) (0.877:0.877:0.877))
- (INTERCONNECT la_data_in[7] mprj.la_data_in[7] (2.468:2.468:2.468) (1.571:1.571:1.571))
- (INTERCONNECT la_data_in[8] mprj.la_data_in[8] (2.668:2.668:2.668) (1.698:1.698:1.698))
- (INTERCONNECT la_data_in[9] mprj.la_data_in[9] (0.687:0.687:0.687) (0.437:0.437:0.437))
- (INTERCONNECT la_oenb[0] mprj.la_oenb[0] (2.014:2.014:2.014) (1.279:1.279:1.279))
- (INTERCONNECT la_oenb[10] mprj.la_oenb[10] (1.684:1.684:1.684) (1.073:1.073:1.073))
- (INTERCONNECT la_oenb[11] mprj.la_oenb[11] (1.668:1.668:1.668) (1.062:1.062:1.062))
- (INTERCONNECT la_oenb[12] mprj.la_oenb[12] (1.172:1.172:1.172) (0.746:0.746:0.746))
- (INTERCONNECT la_oenb[13] mprj.la_oenb[13] (1.831:1.831:1.831) (1.166:1.166:1.166))
- (INTERCONNECT la_oenb[14] mprj.la_oenb[14] (1.006:1.006:1.006) (0.640:0.640:0.640))
- (INTERCONNECT la_oenb[15] mprj.la_oenb[15] (0.926:0.926:0.926) (0.589:0.589:0.589))
- (INTERCONNECT la_oenb[16] mprj.la_oenb[16] (0.605:0.605:0.605) (0.385:0.385:0.385))
- (INTERCONNECT la_oenb[17] mprj.la_oenb[17] (2.526:2.526:2.526) (1.613:1.613:1.613))
- (INTERCONNECT la_oenb[18] mprj.la_oenb[18] (1.209:1.209:1.209) (0.769:0.769:0.769))
- (INTERCONNECT la_oenb[19] mprj.la_oenb[19] (1.239:1.239:1.239) (0.788:0.788:0.788))
- (INTERCONNECT la_oenb[1] mprj.la_oenb[1] (1.268:1.268:1.268) (0.805:0.805:0.805))
- (INTERCONNECT la_oenb[20] mprj.la_oenb[20] (2.204:2.204:2.204) (1.406:1.406:1.406))
- (INTERCONNECT la_oenb[21] mprj.la_oenb[21] (1.015:1.015:1.015) (0.646:0.646:0.646))
- (INTERCONNECT la_oenb[22] mprj.la_oenb[22] (0.681:0.681:0.681) (0.434:0.434:0.434))
- (INTERCONNECT la_oenb[23] mprj.la_oenb[23] (2.272:2.272:2.272) (1.450:1.450:1.450))
- (INTERCONNECT la_oenb[24] mprj.la_oenb[24] (1.876:1.876:1.876) (1.191:1.191:1.191))
- (INTERCONNECT la_oenb[25] mprj.la_oenb[25] (3.081:3.081:3.081) (1.966:1.966:1.966))
- (INTERCONNECT la_oenb[26] mprj.la_oenb[26] (2.703:2.703:2.703) (1.724:1.724:1.724))
- (INTERCONNECT la_oenb[27] mprj.la_oenb[27] (1.740:1.740:1.740) (1.105:1.105:1.105))
- (INTERCONNECT la_oenb[28] mprj.la_oenb[28] (1.738:1.738:1.738) (1.103:1.103:1.103))
- (INTERCONNECT la_oenb[29] mprj.la_oenb[29] (2.188:2.188:2.188) (1.396:1.396:1.396))
- (INTERCONNECT la_oenb[2] mprj.la_oenb[2] (0.756:0.756:0.756) (0.481:0.481:0.481))
- (INTERCONNECT la_oenb[30] mprj.la_oenb[30] (2.487:2.487:2.487) (1.578:1.578:1.578))
- (INTERCONNECT la_oenb[31] mprj.la_oenb[31] (0.809:0.809:0.809) (0.516:0.516:0.516))
- (INTERCONNECT la_oenb[32] mprj.la_oenb[32] (2.558:2.558:2.558) (1.629:1.629:1.629))
- (INTERCONNECT la_oenb[33] mprj.la_oenb[33] (2.588:2.588:2.588) (1.642:1.642:1.642))
- (INTERCONNECT la_oenb[34] mprj.la_oenb[34] (1.884:1.884:1.884) (1.199:1.199:1.199))
- (INTERCONNECT la_oenb[35] mprj.la_oenb[35] (2.528:2.528:2.528) (1.606:1.606:1.606))
- (INTERCONNECT la_oenb[36] mprj.la_oenb[36] (2.587:2.587:2.587) (1.646:1.646:1.646))
- (INTERCONNECT la_oenb[37] mprj.la_oenb[37] (1.294:1.294:1.294) (0.823:0.823:0.823))
- (INTERCONNECT la_oenb[38] mprj.la_oenb[38] (3.782:3.782:3.782) (2.406:2.406:2.406))
- (INTERCONNECT la_oenb[39] mprj.la_oenb[39] (3.366:3.366:3.366) (2.139:2.139:2.139))
- (INTERCONNECT la_oenb[3] mprj.la_oenb[3] (0.702:0.702:0.702) (0.447:0.447:0.447))
- (INTERCONNECT la_oenb[40] mprj.la_oenb[40] (0.902:0.902:0.902) (0.576:0.576:0.576))
- (INTERCONNECT la_oenb[41] mprj.la_oenb[41] (1.693:1.693:1.693) (1.076:1.076:1.076))
- (INTERCONNECT la_oenb[42] mprj.la_oenb[42] (1.232:1.232:1.232) (0.785:0.785:0.785))
- (INTERCONNECT la_oenb[43] mprj.la_oenb[43] (0.874:0.874:0.874) (0.559:0.559:0.559))
- (INTERCONNECT la_oenb[44] mprj.la_oenb[44] (3.096:3.096:3.096) (1.964:1.964:1.964))
- (INTERCONNECT la_oenb[45] mprj.la_oenb[45] (2.308:2.308:2.308) (1.470:1.470:1.470))
- (INTERCONNECT la_oenb[46] mprj.la_oenb[46] (3.247:3.247:3.247) (2.055:2.055:2.055))
- (INTERCONNECT la_oenb[47] mprj.la_oenb[47] (2.374:2.374:2.374) (1.509:1.509:1.509))
- (INTERCONNECT la_oenb[48] mprj.la_oenb[48] (1.238:1.238:1.238) (0.789:0.789:0.789))
- (INTERCONNECT la_oenb[49] mprj.la_oenb[49] (1.889:1.889:1.889) (1.202:1.202:1.202))
- (INTERCONNECT la_oenb[4] mprj.la_oenb[4] (2.419:2.419:2.419) (1.538:1.538:1.538))
- (INTERCONNECT la_oenb[50] mprj.la_oenb[50] (3.477:3.477:3.477) (2.202:2.202:2.202))
- (INTERCONNECT la_oenb[51] mprj.la_oenb[51] (3.691:3.691:3.691) (2.340:2.340:2.340))
- (INTERCONNECT la_oenb[52] mprj.la_oenb[52] (2.298:2.298:2.298) (1.462:1.462:1.462))
- (INTERCONNECT la_oenb[53] mprj.la_oenb[53] (2.615:2.615:2.615) (1.660:1.660:1.660))
- (INTERCONNECT la_oenb[54] mprj.la_oenb[54] (4.730:4.730:4.730) (3.005:3.005:3.005))
- (INTERCONNECT la_oenb[55] mprj.la_oenb[55] (3.917:3.917:3.917) (2.478:2.478:2.478))
- (INTERCONNECT la_oenb[56] mprj.la_oenb[56] (3.031:3.031:3.031) (1.920:1.920:1.920))
- (INTERCONNECT la_oenb[57] mprj.la_oenb[57] (3.063:3.063:3.063) (1.944:1.944:1.944))
- (INTERCONNECT la_oenb[58] mprj.la_oenb[58] (4.150:4.150:4.150) (2.625:2.625:2.625))
- (INTERCONNECT la_oenb[59] mprj.la_oenb[59] (1.866:1.866:1.866) (1.189:1.189:1.189))
- (INTERCONNECT la_oenb[5] mprj.la_oenb[5] (1.860:1.860:1.860) (1.185:1.185:1.185))
- (INTERCONNECT la_oenb[60] mprj.la_oenb[60] (0.963:0.963:0.963) (0.616:0.616:0.616))
- (INTERCONNECT la_oenb[61] mprj.la_oenb[61] (2.540:2.540:2.540) (1.619:1.619:1.619))
- (INTERCONNECT la_oenb[62] mprj.la_oenb[62] (4.118:4.118:4.118) (2.604:2.604:2.604))
- (INTERCONNECT la_oenb[63] mprj.la_oenb[63] (1.088:1.088:1.088) (0.695:0.695:0.695))
- (INTERCONNECT la_oenb[6] mprj.la_oenb[6] (2.124:2.124:2.124) (1.355:1.355:1.355))
- (INTERCONNECT la_oenb[7] mprj.la_oenb[7] (1.009:1.009:1.009) (0.642:0.642:0.642))
- (INTERCONNECT la_oenb[8] mprj.la_oenb[8] (1.674:1.674:1.674) (1.067:1.067:1.067))
- (INTERCONNECT la_oenb[9] mprj.la_oenb[9] (2.057:2.057:2.057) (1.312:1.312:1.312))
- (INTERCONNECT wb_clk_i mprj.wb_clk_i (0.826:0.826:0.826) (0.526:0.526:0.526))
- (INTERCONNECT wb_rst_i mprj.wb_rst_i (1.618:1.618:1.618) (1.026:1.026:1.026))
- (INTERCONNECT wbs_adr_i[0] mprj.wbs_adr_i[0] (1.113:1.113:1.113) (0.708:0.708:0.708))
- (INTERCONNECT wbs_adr_i[10] mprj.wbs_adr_i[10] (0.601:0.601:0.601) (0.382:0.382:0.382))
- (INTERCONNECT wbs_adr_i[11] mprj.wbs_adr_i[11] (0.964:0.964:0.964) (0.613:0.613:0.613))
- (INTERCONNECT wbs_adr_i[12] mprj.wbs_adr_i[12] (0.932:0.932:0.932) (0.593:0.593:0.593))
- (INTERCONNECT wbs_adr_i[13] mprj.wbs_adr_i[13] (0.841:0.841:0.841) (0.534:0.534:0.534))
- (INTERCONNECT wbs_adr_i[14] mprj.wbs_adr_i[14] (0.853:0.853:0.853) (0.542:0.542:0.542))
- (INTERCONNECT wbs_adr_i[15] mprj.wbs_adr_i[15] (0.831:0.831:0.831) (0.528:0.528:0.528))
- (INTERCONNECT wbs_adr_i[16] mprj.wbs_adr_i[16] (1.537:1.537:1.537) (0.976:0.976:0.976))
- (INTERCONNECT wbs_adr_i[17] mprj.wbs_adr_i[17] (1.430:1.430:1.430) (0.907:0.907:0.907))
- (INTERCONNECT wbs_adr_i[18] mprj.wbs_adr_i[18] (1.238:1.238:1.238) (0.786:0.786:0.786))
- (INTERCONNECT wbs_adr_i[19] mprj.wbs_adr_i[19] (0.549:0.549:0.549) (0.349:0.349:0.349))
- (INTERCONNECT wbs_adr_i[1] mprj.wbs_adr_i[1] (0.842:0.842:0.842) (0.536:0.536:0.536))
- (INTERCONNECT wbs_adr_i[20] mprj.wbs_adr_i[20] (1.282:1.282:1.282) (0.813:0.813:0.813))
- (INTERCONNECT wbs_adr_i[21] mprj.wbs_adr_i[21] (0.658:0.658:0.658) (0.417:0.417:0.417))
- (INTERCONNECT wbs_adr_i[22] mprj.wbs_adr_i[22] (0.583:0.583:0.583) (0.369:0.369:0.369))
- (INTERCONNECT wbs_adr_i[23] mprj.wbs_adr_i[23] (0.637:0.637:0.637) (0.404:0.404:0.404))
- (INTERCONNECT wbs_adr_i[24] mprj.wbs_adr_i[24] (1.295:1.295:1.295) (0.820:0.820:0.820))
- (INTERCONNECT wbs_adr_i[25] mprj.wbs_adr_i[25] (0.401:0.401:0.401) (0.254:0.254:0.254))
- (INTERCONNECT wbs_adr_i[26] mprj.wbs_adr_i[26] (0.444:0.444:0.444) (0.281:0.281:0.281))
- (INTERCONNECT wbs_adr_i[27] mprj.wbs_adr_i[27] (0.510:0.510:0.510) (0.324:0.324:0.324))
- (INTERCONNECT wbs_adr_i[28] mprj.wbs_adr_i[28] (0.724:0.724:0.724) (0.460:0.460:0.460))
- (INTERCONNECT wbs_adr_i[29] mprj.wbs_adr_i[29] (1.799:1.799:1.799) (1.143:1.143:1.143))
- (INTERCONNECT wbs_adr_i[2] mprj.wbs_adr_i[2] (1.291:1.291:1.291) (0.820:0.820:0.820))
- (INTERCONNECT wbs_adr_i[30] mprj.wbs_adr_i[30] (1.333:1.333:1.333) (0.848:0.848:0.848))
- (INTERCONNECT wbs_adr_i[31] mprj.wbs_adr_i[31] (0.991:0.991:0.991) (0.630:0.630:0.630))
- (INTERCONNECT wbs_adr_i[3] mprj.wbs_adr_i[3] (1.593:1.593:1.593) (1.014:1.014:1.014))
- (INTERCONNECT wbs_adr_i[4] mprj.wbs_adr_i[4] (1.230:1.230:1.230) (0.782:0.782:0.782))
- (INTERCONNECT wbs_adr_i[5] mprj.wbs_adr_i[5] (0.967:0.967:0.967) (0.615:0.615:0.615))
- (INTERCONNECT wbs_adr_i[6] mprj.wbs_adr_i[6] (1.376:1.376:1.376) (0.874:0.874:0.874))
- (INTERCONNECT wbs_adr_i[7] mprj.wbs_adr_i[7] (1.294:1.294:1.294) (0.822:0.822:0.822))
- (INTERCONNECT wbs_adr_i[8] mprj.wbs_adr_i[8] (1.158:1.158:1.158) (0.735:0.735:0.735))
- (INTERCONNECT wbs_adr_i[9] mprj.wbs_adr_i[9] (0.992:0.992:0.992) (0.631:0.631:0.631))
- (INTERCONNECT wbs_cyc_i mprj.wbs_cyc_i (1.208:1.208:1.208) (0.768:0.768:0.768))
- (INTERCONNECT wbs_dat_i[0] mprj.wbs_dat_i[0] (1.723:1.723:1.723) (1.093:1.093:1.093))
- (INTERCONNECT wbs_dat_i[10] mprj.wbs_dat_i[10] (0.936:0.936:0.936) (0.595:0.595:0.595))
- (INTERCONNECT wbs_dat_i[11] mprj.wbs_dat_i[11] (1.034:1.034:1.034) (0.657:0.657:0.657))
- (INTERCONNECT wbs_dat_i[12] mprj.wbs_dat_i[12] (0.925:0.925:0.925) (0.588:0.588:0.588))
- (INTERCONNECT wbs_dat_i[13] mprj.wbs_dat_i[13] (0.740:0.740:0.740) (0.471:0.471:0.471))
- (INTERCONNECT wbs_dat_i[14] mprj.wbs_dat_i[14] (0.759:0.759:0.759) (0.482:0.482:0.482))
- (INTERCONNECT wbs_dat_i[15] mprj.wbs_dat_i[15] (1.048:1.048:1.048) (0.666:0.666:0.666))
- (INTERCONNECT wbs_dat_i[16] mprj.wbs_dat_i[16] (0.620:0.620:0.620) (0.394:0.394:0.394))
- (INTERCONNECT wbs_dat_i[17] mprj.wbs_dat_i[17] (1.188:1.188:1.188) (0.754:0.754:0.754))
- (INTERCONNECT wbs_dat_i[18] mprj.wbs_dat_i[18] (0.616:0.616:0.616) (0.391:0.391:0.391))
- (INTERCONNECT wbs_dat_i[19] mprj.wbs_dat_i[19] (0.512:0.512:0.512) (0.325:0.325:0.325))
- (INTERCONNECT wbs_dat_i[1] mprj.wbs_dat_i[1] (1.067:1.067:1.067) (0.679:0.679:0.679))
- (INTERCONNECT wbs_dat_i[20] mprj.wbs_dat_i[20] (0.740:0.740:0.740) (0.470:0.470:0.470))
- (INTERCONNECT wbs_dat_i[21] mprj.wbs_dat_i[21] (0.639:0.639:0.639) (0.405:0.405:0.405))
- (INTERCONNECT wbs_dat_i[22] mprj.wbs_dat_i[22] (0.613:0.613:0.613) (0.388:0.388:0.388))
- (INTERCONNECT wbs_dat_i[23] mprj.wbs_dat_i[23] (0.582:0.582:0.582) (0.369:0.369:0.369))
- (INTERCONNECT wbs_dat_i[24] mprj.wbs_dat_i[24] (0.399:0.399:0.399) (0.253:0.253:0.253))
- (INTERCONNECT wbs_dat_i[25] mprj.wbs_dat_i[25] (1.348:1.348:1.348) (0.854:0.854:0.854))
- (INTERCONNECT wbs_dat_i[26] mprj.wbs_dat_i[26] (0.666:0.666:0.666) (0.422:0.422:0.422))
- (INTERCONNECT wbs_dat_i[27] mprj.wbs_dat_i[27] (0.792:0.792:0.792) (0.503:0.503:0.503))
- (INTERCONNECT wbs_dat_i[28] mprj.wbs_dat_i[28] (0.716:0.716:0.716) (0.455:0.455:0.455))
- (INTERCONNECT wbs_dat_i[29] mprj.wbs_dat_i[29] (0.734:0.734:0.734) (0.466:0.466:0.466))
- (INTERCONNECT wbs_dat_i[2] mprj.wbs_dat_i[2] (0.538:0.538:0.538) (0.342:0.342:0.342))
- (INTERCONNECT wbs_dat_i[30] mprj.wbs_dat_i[30] (1.339:1.339:1.339) (0.849:0.849:0.849))
- (INTERCONNECT wbs_dat_i[31] mprj.wbs_dat_i[31] (1.292:1.292:1.292) (0.820:0.820:0.820))
- (INTERCONNECT wbs_dat_i[3] mprj.wbs_dat_i[3] (1.513:1.513:1.513) (0.962:0.962:0.962))
- (INTERCONNECT wbs_dat_i[4] mprj.wbs_dat_i[4] (1.390:1.390:1.390) (0.883:0.883:0.883))
- (INTERCONNECT wbs_dat_i[5] mprj.wbs_dat_i[5] (1.266:1.266:1.266) (0.804:0.804:0.804))
- (INTERCONNECT wbs_dat_i[6] mprj.wbs_dat_i[6] (0.970:0.970:0.970) (0.616:0.616:0.616))
- (INTERCONNECT wbs_dat_i[7] mprj.wbs_dat_i[7] (1.200:1.200:1.200) (0.762:0.762:0.762))
- (INTERCONNECT wbs_dat_i[8] mprj.wbs_dat_i[8] (0.850:0.850:0.850) (0.541:0.541:0.541))
- (INTERCONNECT wbs_dat_i[9] mprj.wbs_dat_i[9] (0.847:0.847:0.847) (0.539:0.539:0.539))
- (INTERCONNECT wbs_sel_i[0] mprj.wbs_sel_i[0] (0.610:0.610:0.610) (0.388:0.388:0.388))
- (INTERCONNECT wbs_sel_i[1] mprj.wbs_sel_i[1] (1.176:1.176:1.176) (0.747:0.747:0.747))
- (INTERCONNECT wbs_sel_i[2] mprj.wbs_sel_i[2] (0.914:0.914:0.914) (0.582:0.582:0.582))
- (INTERCONNECT wbs_sel_i[3] mprj.wbs_sel_i[3] (1.405:1.405:1.405) (0.893:0.893:0.893))
- (INTERCONNECT wbs_stb_i mprj.wbs_stb_i (0.980:0.980:0.980) (0.624:0.624:0.624))
- (INTERCONNECT wbs_we_i mprj.wbs_we_i (1.011:1.011:1.011) (0.644:0.644:0.644))
- (INTERCONNECT mprj.io_oeb[0] io_oeb[0] (0.399:0.399:0.399))
- (INTERCONNECT mprj.io_oeb[10] io_oeb[10] (0.104:0.104:0.104))
- (INTERCONNECT mprj.io_oeb[11] io_oeb[11] (0.114:0.114:0.114))
- (INTERCONNECT mprj.io_oeb[12] io_oeb[12] (0.135:0.135:0.135))
- (INTERCONNECT mprj.io_oeb[13] io_oeb[13] (0.134:0.134:0.134))
- (INTERCONNECT mprj.io_oeb[14] io_oeb[14] (0.147:0.147:0.147))
- (INTERCONNECT mprj.io_oeb[15] io_oeb[15] (0.288:0.288:0.288))
- (INTERCONNECT mprj.io_oeb[16] io_oeb[16] (0.232:0.232:0.232))
- (INTERCONNECT mprj.io_oeb[17] io_oeb[17] (0.092:0.092:0.092))
- (INTERCONNECT mprj.io_oeb[18] io_oeb[18] (0.074:0.074:0.074))
- (INTERCONNECT mprj.io_oeb[19] io_oeb[19] (0.060:0.060:0.060))
- (INTERCONNECT mprj.io_oeb[1] io_oeb[1] (0.266:0.266:0.266))
- (INTERCONNECT mprj.io_oeb[20] io_oeb[20] (0.044:0.044:0.044))
- (INTERCONNECT mprj.io_oeb[21] io_oeb[21] (0.067:0.067:0.067))
- (INTERCONNECT mprj.io_oeb[22] io_oeb[22] (0.076:0.076:0.076))
- (INTERCONNECT mprj.io_oeb[23] io_oeb[23] (0.094:0.094:0.094))
- (INTERCONNECT mprj.io_oeb[24] io_oeb[24] (0.085:0.085:0.085))
- (INTERCONNECT mprj.io_oeb[25] io_oeb[25] (0.076:0.076:0.076))
- (INTERCONNECT mprj.io_oeb[26] io_oeb[26] (0.284:0.284:0.284))
- (INTERCONNECT mprj.io_oeb[27] io_oeb[27] (0.242:0.242:0.242))
- (INTERCONNECT mprj.io_oeb[28] io_oeb[28] (0.051:0.051:0.051))
- (INTERCONNECT mprj.io_oeb[29] io_oeb[29] (0.043:0.043:0.043))
- (INTERCONNECT mprj.io_oeb[2] io_oeb[2] (0.306:0.306:0.306))
- (INTERCONNECT mprj.io_oeb[30] io_oeb[30] (0.148:0.148:0.148))
- (INTERCONNECT mprj.io_oeb[31] io_oeb[31] (0.055:0.055:0.055))
- (INTERCONNECT mprj.io_oeb[32] io_oeb[32] (0.176:0.176:0.176))
- (INTERCONNECT mprj.io_oeb[33] io_oeb[33] (0.183:0.183:0.183))
- (INTERCONNECT mprj.io_oeb[34] io_oeb[34] (0.161:0.161:0.161))
- (INTERCONNECT mprj.io_oeb[35] io_oeb[35] (0.147:0.147:0.147))
- (INTERCONNECT mprj.io_oeb[36] io_oeb[36] (0.234:0.234:0.234))
- (INTERCONNECT mprj.io_oeb[37] io_oeb[37] (0.246:0.246:0.246))
- (INTERCONNECT mprj.io_oeb[3] io_oeb[3] (0.255:0.255:0.255))
- (INTERCONNECT mprj.io_oeb[4] io_oeb[4] (0.161:0.161:0.161))
- (INTERCONNECT mprj.io_oeb[5] io_oeb[5] (0.116:0.116:0.116))
- (INTERCONNECT mprj.io_oeb[6] io_oeb[6] (0.151:0.151:0.151))
- (INTERCONNECT mprj.io_oeb[7] io_oeb[7] (0.177:0.177:0.177))
- (INTERCONNECT mprj.io_oeb[8] io_oeb[8] (0.084:0.084:0.084))
- (INTERCONNECT mprj.io_oeb[9] io_oeb[9] (0.094:0.094:0.094))
- (INTERCONNECT mprj.io_out[0] io_out[0] (0.406:0.406:0.406))
- (INTERCONNECT mprj.io_out[10] io_out[10] (0.099:0.099:0.099))
- (INTERCONNECT mprj.io_out[11] io_out[11] (0.110:0.110:0.110))
- (INTERCONNECT mprj.io_out[12] io_out[12] (0.119:0.119:0.119))
- (INTERCONNECT mprj.io_out[13] io_out[13] (0.129:0.129:0.129))
- (INTERCONNECT mprj.io_out[14] io_out[14] (0.167:0.167:0.167))
- (INTERCONNECT mprj.io_out[15] io_out[15] (0.244:0.244:0.244))
- (INTERCONNECT mprj.io_out[16] io_out[16] (0.117:0.117:0.117))
- (INTERCONNECT mprj.io_out[17] io_out[17] (0.171:0.171:0.171))
- (INTERCONNECT mprj.io_out[18] io_out[18] (0.133:0.133:0.133))
- (INTERCONNECT mprj.io_out[19] io_out[19] (0.078:0.078:0.078))
- (INTERCONNECT mprj.io_out[1] io_out[1] (0.194:0.194:0.194))
- (INTERCONNECT mprj.io_out[20] io_out[20] (0.048:0.048:0.048))
- (INTERCONNECT mprj.io_out[21] io_out[21] (0.059:0.059:0.059))
- (INTERCONNECT mprj.io_out[22] io_out[22] (0.092:0.092:0.092))
- (INTERCONNECT mprj.io_out[23] io_out[23] (0.105:0.105:0.105))
- (INTERCONNECT mprj.io_out[24] io_out[24] (0.095:0.095:0.095))
- (INTERCONNECT mprj.io_out[25] io_out[25] (0.245:0.245:0.245))
- (INTERCONNECT mprj.io_out[26] io_out[26] (0.077:0.077:0.077))
- (INTERCONNECT mprj.io_out[27] io_out[27] (0.063:0.063:0.063))
- (INTERCONNECT mprj.io_out[28] io_out[28] (0.055:0.055:0.055))
- (INTERCONNECT mprj.io_out[29] io_out[29] (0.204:0.204:0.204))
- (INTERCONNECT mprj.io_out[2] io_out[2] (0.210:0.210:0.210))
- (INTERCONNECT mprj.io_out[30] io_out[30] (0.039:0.039:0.039))
- (INTERCONNECT mprj.io_out[31] io_out[31] (0.049:0.049:0.049))
- (INTERCONNECT mprj.io_out[32] io_out[32] (0.085:0.085:0.085))
- (INTERCONNECT mprj.io_out[33] io_out[33] (0.118:0.118:0.118))
- (INTERCONNECT mprj.io_out[34] io_out[34] (0.147:0.147:0.147))
- (INTERCONNECT mprj.io_out[35] io_out[35] (0.160:0.160:0.160))
- (INTERCONNECT mprj.io_out[36] io_out[36] (0.125:0.125:0.125))
- (INTERCONNECT mprj.io_out[37] io_out[37] (0.103:0.103:0.103))
- (INTERCONNECT mprj.io_out[3] io_out[3] (0.191:0.191:0.191))
- (INTERCONNECT mprj.io_out[4] io_out[4] (0.136:0.136:0.136))
- (INTERCONNECT mprj.io_out[5] io_out[5] (0.159:0.159:0.159))
- (INTERCONNECT mprj.io_out[6] io_out[6] (0.135:0.135:0.135))
- (INTERCONNECT mprj.io_out[7] io_out[7] (0.126:0.126:0.126))
- (INTERCONNECT mprj.io_out[8] io_out[8] (0.080:0.080:0.080))
- (INTERCONNECT mprj.io_out[9] io_out[9] (0.091:0.091:0.091))
- (INTERCONNECT mprj.irq[0] user_irq[0] (0.160:0.160:0.160))
- (INTERCONNECT mprj.irq[1] user_irq[1] (0.164:0.164:0.164))
- (INTERCONNECT mprj.irq[2] user_irq[2] (0.096:0.096:0.096))
- (INTERCONNECT mprj.la_data_out[0] la_data_out[0] (0.047:0.047:0.047))
- (INTERCONNECT mprj.la_data_out[10] la_data_out[10] (0.100:0.100:0.100))
- (INTERCONNECT mprj.la_data_out[11] la_data_out[11] (0.080:0.080:0.080))
- (INTERCONNECT mprj.la_data_out[12] la_data_out[12] (0.080:0.080:0.080))
- (INTERCONNECT mprj.la_data_out[13] la_data_out[13] (0.100:0.100:0.100))
- (INTERCONNECT mprj.la_data_out[14] la_data_out[14] (0.064:0.064:0.064))
- (INTERCONNECT mprj.la_data_out[15] la_data_out[15] (0.080:0.080:0.080))
- (INTERCONNECT mprj.la_data_out[16] la_data_out[16] (0.045:0.045:0.045))
- (INTERCONNECT mprj.la_data_out[17] la_data_out[17] (0.129:0.129:0.129))
- (INTERCONNECT mprj.la_data_out[18] la_data_out[18] (0.073:0.073:0.073))
- (INTERCONNECT mprj.la_data_out[19] la_data_out[19] (0.051:0.051:0.051))
- (INTERCONNECT mprj.la_data_out[1] la_data_out[1] (0.061:0.061:0.061))
- (INTERCONNECT mprj.la_data_out[20] la_data_out[20] (0.131:0.131:0.131))
- (INTERCONNECT mprj.la_data_out[21] la_data_out[21] (0.045:0.045:0.045))
- (INTERCONNECT mprj.la_data_out[22] la_data_out[22] (0.054:0.054:0.054))
- (INTERCONNECT mprj.la_data_out[23] la_data_out[23] (0.062:0.062:0.062))
- (INTERCONNECT mprj.la_data_out[24] la_data_out[24] (0.076:0.076:0.076))
- (INTERCONNECT mprj.la_data_out[25] la_data_out[25] (0.075:0.075:0.075))
- (INTERCONNECT mprj.la_data_out[26] la_data_out[26] (0.095:0.095:0.095))
- (INTERCONNECT mprj.la_data_out[27] la_data_out[27] (0.071:0.071:0.071))
- (INTERCONNECT mprj.la_data_out[28] la_data_out[28] (0.102:0.102:0.102))
- (INTERCONNECT mprj.la_data_out[29] la_data_out[29] (0.072:0.072:0.072))
- (INTERCONNECT mprj.la_data_out[2] la_data_out[2] (0.038:0.038:0.038))
- (INTERCONNECT mprj.la_data_out[30] la_data_out[30] (0.102:0.102:0.102))
- (INTERCONNECT mprj.la_data_out[31] la_data_out[31] (0.080:0.080:0.080))
- (INTERCONNECT mprj.la_data_out[32] la_data_out[32] (0.101:0.101:0.101))
- (INTERCONNECT mprj.la_data_out[33] la_data_out[33] (0.107:0.107:0.107))
- (INTERCONNECT mprj.la_data_out[34] la_data_out[34] (0.119:0.119:0.119))
- (INTERCONNECT mprj.la_data_out[35] la_data_out[35] (0.119:0.119:0.119))
- (INTERCONNECT mprj.la_data_out[36] la_data_out[36] (0.072:0.072:0.072))
- (INTERCONNECT mprj.la_data_out[37] la_data_out[37] (0.095:0.095:0.095))
- (INTERCONNECT mprj.la_data_out[38] la_data_out[38] (0.142:0.142:0.142))
- (INTERCONNECT mprj.la_data_out[39] la_data_out[39] (0.137:0.137:0.137))
- (INTERCONNECT mprj.la_data_out[3] la_data_out[3] (0.055:0.055:0.055))
- (INTERCONNECT mprj.la_data_out[40] la_data_out[40] (0.104:0.104:0.104))
- (INTERCONNECT mprj.la_data_out[41] la_data_out[41] (0.141:0.141:0.141))
- (INTERCONNECT mprj.la_data_out[42] la_data_out[42] (0.156:0.156:0.156))
- (INTERCONNECT mprj.la_data_out[43] la_data_out[43] (0.160:0.160:0.160))
- (INTERCONNECT mprj.la_data_out[44] la_data_out[44] (0.135:0.135:0.135))
- (INTERCONNECT mprj.la_data_out[45] la_data_out[45] (0.072:0.072:0.072))
- (INTERCONNECT mprj.la_data_out[46] la_data_out[46] (0.155:0.155:0.155))
- (INTERCONNECT mprj.la_data_out[47] la_data_out[47] (0.142:0.142:0.142))
- (INTERCONNECT mprj.la_data_out[48] la_data_out[48] (0.184:0.184:0.184))
- (INTERCONNECT mprj.la_data_out[49] la_data_out[49] (0.126:0.126:0.126))
- (INTERCONNECT mprj.la_data_out[4] la_data_out[4] (0.087:0.087:0.087))
- (INTERCONNECT mprj.la_data_out[50] la_data_out[50] (0.198:0.198:0.198))
- (INTERCONNECT mprj.la_data_out[51] la_data_out[51] (0.205:0.205:0.205))
- (INTERCONNECT mprj.la_data_out[52] la_data_out[52] (0.141:0.141:0.141))
- (INTERCONNECT mprj.la_data_out[53] la_data_out[53] (0.144:0.144:0.144))
- (INTERCONNECT mprj.la_data_out[54] la_data_out[54] (0.126:0.126:0.126))
- (INTERCONNECT mprj.la_data_out[55] la_data_out[55] (0.220:0.220:0.220))
- (INTERCONNECT mprj.la_data_out[56] la_data_out[56] (0.238:0.238:0.238))
- (INTERCONNECT mprj.la_data_out[57] la_data_out[57] (0.126:0.126:0.126))
- (INTERCONNECT mprj.la_data_out[58] la_data_out[58] (0.158:0.158:0.158))
- (INTERCONNECT mprj.la_data_out[59] la_data_out[59] (0.151:0.151:0.151))
- (INTERCONNECT mprj.la_data_out[5] la_data_out[5] (0.083:0.083:0.083))
- (INTERCONNECT mprj.la_data_out[60] la_data_out[60] (0.247:0.247:0.247))
- (INTERCONNECT mprj.la_data_out[61] la_data_out[61] (0.105:0.105:0.105))
- (INTERCONNECT mprj.la_data_out[62] la_data_out[62] (0.165:0.165:0.165))
- (INTERCONNECT mprj.la_data_out[63] la_data_out[63] (0.172:0.172:0.172))
- (INTERCONNECT mprj.la_data_out[6] la_data_out[6] (0.047:0.047:0.047))
- (INTERCONNECT mprj.la_data_out[7] la_data_out[7] (0.066:0.066:0.066))
- (INTERCONNECT mprj.la_data_out[8] la_data_out[8] (0.059:0.059:0.059))
- (INTERCONNECT mprj.la_data_out[9] la_data_out[9] (0.065:0.065:0.065))
- (INTERCONNECT mprj.wbs_ack_o wbs_ack_o (0.037:0.037:0.037))
- (INTERCONNECT mprj.wbs_dat_o[0] wbs_dat_o[0] (0.035:0.035:0.035))
- (INTERCONNECT mprj.wbs_dat_o[10] wbs_dat_o[10] (0.031:0.031:0.031))
- (INTERCONNECT mprj.wbs_dat_o[11] wbs_dat_o[11] (0.047:0.047:0.047))
- (INTERCONNECT mprj.wbs_dat_o[12] wbs_dat_o[12] (0.031:0.031:0.031))
- (INTERCONNECT mprj.wbs_dat_o[13] wbs_dat_o[13] (0.026:0.026:0.026))
- (INTERCONNECT mprj.wbs_dat_o[14] wbs_dat_o[14] (0.040:0.040:0.040))
- (INTERCONNECT mprj.wbs_dat_o[15] wbs_dat_o[15] (0.027:0.027:0.027))
- (INTERCONNECT mprj.wbs_dat_o[16] wbs_dat_o[16] (0.033:0.033:0.033))
- (INTERCONNECT mprj.wbs_dat_o[17] wbs_dat_o[17] (0.030:0.030:0.030))
- (INTERCONNECT mprj.wbs_dat_o[18] wbs_dat_o[18] (0.038:0.038:0.038))
- (INTERCONNECT mprj.wbs_dat_o[19] wbs_dat_o[19] (0.027:0.027:0.027))
- (INTERCONNECT mprj.wbs_dat_o[1] wbs_dat_o[1] (0.059:0.059:0.059))
- (INTERCONNECT mprj.wbs_dat_o[20] wbs_dat_o[20] (0.038:0.038:0.038))
- (INTERCONNECT mprj.wbs_dat_o[21] wbs_dat_o[21] (0.031:0.031:0.031))
- (INTERCONNECT mprj.wbs_dat_o[22] wbs_dat_o[22] (0.050:0.050:0.050))
- (INTERCONNECT mprj.wbs_dat_o[23] wbs_dat_o[23] (0.048:0.048:0.048))
- (INTERCONNECT mprj.wbs_dat_o[24] wbs_dat_o[24] (0.049:0.049:0.049))
- (INTERCONNECT mprj.wbs_dat_o[25] wbs_dat_o[25] (0.059:0.059:0.059))
- (INTERCONNECT mprj.wbs_dat_o[26] wbs_dat_o[26] (0.047:0.047:0.047))
- (INTERCONNECT mprj.wbs_dat_o[27] wbs_dat_o[27] (0.038:0.038:0.038))
- (INTERCONNECT mprj.wbs_dat_o[28] wbs_dat_o[28] (0.056:0.056:0.056))
- (INTERCONNECT mprj.wbs_dat_o[29] wbs_dat_o[29] (0.050:0.050:0.050))
- (INTERCONNECT mprj.wbs_dat_o[2] wbs_dat_o[2] (0.052:0.052:0.052))
- (INTERCONNECT mprj.wbs_dat_o[30] wbs_dat_o[30] (0.044:0.044:0.044))
- (INTERCONNECT mprj.wbs_dat_o[31] wbs_dat_o[31] (0.059:0.059:0.059))
- (INTERCONNECT mprj.wbs_dat_o[3] wbs_dat_o[3] (0.052:0.052:0.052))
- (INTERCONNECT mprj.wbs_dat_o[4] wbs_dat_o[4] (0.047:0.047:0.047))
- (INTERCONNECT mprj.wbs_dat_o[5] wbs_dat_o[5] (0.034:0.034:0.034))
- (INTERCONNECT mprj.wbs_dat_o[6] wbs_dat_o[6] (0.042:0.042:0.042))
- (INTERCONNECT mprj.wbs_dat_o[7] wbs_dat_o[7] (0.059:0.059:0.059))
- (INTERCONNECT mprj.wbs_dat_o[8] wbs_dat_o[8] (0.037:0.037:0.037))
- (INTERCONNECT mprj.wbs_dat_o[9] wbs_dat_o[9] (0.061:0.061:0.061))
+ (INTERCONNECT io_in[0] wrapped_vga_clock.io_in[0] (1.287:1.287:1.287) (0.824:0.824:0.824))
+ (INTERCONNECT io_in[10] wrapped_vga_clock.io_in[10] (1.298:1.298:1.298) (0.833:0.833:0.833))
+ (INTERCONNECT io_in[11] wrapped_vga_clock.io_in[11] (1.399:1.399:1.399) (0.899:0.899:0.899))
+ (INTERCONNECT io_in[12] wrapped_vga_clock.io_in[12] (1.754:1.754:1.754) (1.130:1.130:1.130))
+ (INTERCONNECT io_in[13] wrapped_vga_clock.io_in[13] (1.472:1.472:1.472) (0.946:0.946:0.946))
+ (INTERCONNECT io_in[14] wrapped_vga_clock.io_in[14] (1.587:1.587:1.587) (1.020:1.020:1.020))
+ (INTERCONNECT io_in[15] wrapped_vga_clock.io_in[15] (2.041:2.041:2.041) (1.317:1.317:1.317))
+ (INTERCONNECT io_in[16] wrapped_vga_clock.io_in[16] (5.122:5.122:5.122) (3.241:3.241:3.241))
+ (INTERCONNECT io_in[17] wrapped_vga_clock.io_in[17] (2.810:2.810:2.810) (1.798:1.798:1.798))
+ (INTERCONNECT io_in[18] wrapped_vga_clock.io_in[18] (2.064:2.064:2.064) (1.328:1.328:1.328))
+ (INTERCONNECT io_in[19] wrapped_vga_clock.io_in[19] (1.612:1.612:1.612) (1.035:1.035:1.035))
+ (INTERCONNECT io_in[1] wrapped_vga_clock.io_in[1] (1.199:1.199:1.199) (0.767:0.767:0.767))
+ (INTERCONNECT io_in[20] wrapped_vga_clock.io_in[20] (1.070:1.070:1.070) (0.687:0.687:0.687))
+ (INTERCONNECT io_in[21] wrapped_vga_clock.io_in[21] (0.938:0.938:0.938) (0.601:0.601:0.601))
+ (INTERCONNECT io_in[22] wrapped_vga_clock.io_in[22] (0.995:0.995:0.995) (0.638:0.638:0.638))
+ (INTERCONNECT io_in[23] wrapped_vga_clock.io_in[23] (0.919:0.919:0.919) (0.589:0.589:0.589))
+ (INTERCONNECT io_in[24] wrapped_vga_clock.io_in[24] (2.534:2.534:2.534) (1.613:1.613:1.613))
+ (INTERCONNECT io_in[25] wrapped_vga_clock.io_in[25] (1.020:1.020:1.020) (0.654:0.654:0.654))
+ (INTERCONNECT io_in[26] wrapped_vga_clock.io_in[26] (0.820:0.820:0.820) (0.525:0.525:0.525))
+ (INTERCONNECT io_in[27] wrapped_vga_clock.io_in[27] (0.808:0.808:0.808) (0.516:0.516:0.516))
+ (INTERCONNECT io_in[28] wrapped_vga_clock.io_in[28] (2.028:2.028:2.028) (1.289:1.289:1.289))
+ (INTERCONNECT io_in[29] wrapped_vga_clock.io_in[29] (1.575:1.575:1.575) (1.003:1.003:1.003))
+ (INTERCONNECT io_in[2] wrapped_vga_clock.io_in[2] (1.035:1.035:1.035) (0.663:0.663:0.663))
+ (INTERCONNECT io_in[30] wrapped_vga_clock.io_in[30] (0.505:0.505:0.505) (0.321:0.321:0.321))
+ (INTERCONNECT io_in[31] wrapped_vga_clock.io_in[31] (1.071:1.071:1.071) (0.682:0.682:0.682))
+ (INTERCONNECT io_in[32] wrapped_vga_clock.io_in[32] (0.771:0.771:0.771) (0.490:0.490:0.490))
+ (INTERCONNECT io_in[33] wrapped_vga_clock.io_in[33] (0.260:0.260:0.260) (0.165:0.165:0.165))
+ (INTERCONNECT io_in[34] wrapped_vga_clock.io_in[34] (0.264:0.264:0.264) (0.167:0.167:0.167))
+ (INTERCONNECT io_in[35] wrapped_vga_clock.io_in[35] (0.374:0.374:0.374) (0.237:0.237:0.237))
+ (INTERCONNECT io_in[36] wrapped_vga_clock.io_in[36] (0.810:0.810:0.810) (0.516:0.516:0.516))
+ (INTERCONNECT io_in[37] wrapped_vga_clock.io_in[37] (0.609:0.609:0.609) (0.388:0.388:0.388))
+ (INTERCONNECT io_in[3] wrapped_vga_clock.io_in[3] (2.228:2.228:2.228) (1.422:1.422:1.422))
+ (INTERCONNECT io_in[4] wrapped_vga_clock.io_in[4] (0.869:0.869:0.869) (0.556:0.556:0.556))
+ (INTERCONNECT io_in[5] wrapped_vga_clock.io_in[5] (0.828:0.828:0.828) (0.531:0.531:0.531))
+ (INTERCONNECT io_in[6] wrapped_vga_clock.io_in[6] (1.303:1.303:1.303) (0.832:0.832:0.832))
+ (INTERCONNECT io_in[7] wrapped_vga_clock.io_in[7] (1.015:1.015:1.015) (0.650:0.650:0.650))
+ (INTERCONNECT io_in[8] wrapped_vga_clock.io_in[8] (1.237:1.237:1.237) (0.791:0.791:0.791))
+ (INTERCONNECT io_in[9] wrapped_vga_clock.io_in[9] (1.156:1.156:1.156) (0.742:0.742:0.742))
+ (INTERCONNECT wb_clk_i wrapped_vga_clock.wb_clk_i (0.676:0.676:0.676) (0.431:0.431:0.431))
+ (INTERCONNECT wb_rst_i wrapped_vga_clock.wb_rst_i (0.884:0.884:0.884) (0.565:0.565:0.565))
+ (INTERCONNECT wrapped_vga_clock.io_oeb[0] io_oeb[0] (0.124:0.124:0.124))
+ (INTERCONNECT wrapped_vga_clock.io_oeb[10] io_oeb[10] (0.119:0.119:0.119))
+ (INTERCONNECT wrapped_vga_clock.io_oeb[11] io_oeb[11] (0.166:0.166:0.166))
+ (INTERCONNECT wrapped_vga_clock.io_oeb[12] io_oeb[12] (0.193:0.193:0.193))
+ (INTERCONNECT wrapped_vga_clock.io_oeb[13] io_oeb[13] (0.174:0.174:0.174))
+ (INTERCONNECT wrapped_vga_clock.io_oeb[14] io_oeb[14] (0.213:0.213:0.213))
+ (INTERCONNECT wrapped_vga_clock.io_oeb[15] io_oeb[15] (0.260:0.260:0.260))
+ (INTERCONNECT wrapped_vga_clock.io_oeb[16] io_oeb[16] (0.148:0.148:0.148))
+ (INTERCONNECT wrapped_vga_clock.io_oeb[17] io_oeb[17] (0.140:0.140:0.140))
+ (INTERCONNECT wrapped_vga_clock.io_oeb[18] io_oeb[18] (0.126:0.126:0.126))
+ (INTERCONNECT wrapped_vga_clock.io_oeb[19] io_oeb[19] (0.099:0.099:0.099))
+ (INTERCONNECT wrapped_vga_clock.io_oeb[1] io_oeb[1] (0.118:0.118:0.118))
+ (INTERCONNECT wrapped_vga_clock.io_oeb[20] io_oeb[20] (0.084:0.084:0.084))
+ (INTERCONNECT wrapped_vga_clock.io_oeb[21] io_oeb[21] (0.058:0.058:0.058))
+ (INTERCONNECT wrapped_vga_clock.io_oeb[22] io_oeb[22] (0.099:0.099:0.099))
+ (INTERCONNECT wrapped_vga_clock.io_oeb[23] io_oeb[23] (0.106:0.106:0.106))
+ (INTERCONNECT wrapped_vga_clock.io_oeb[24] io_oeb[24] (0.106:0.106:0.106))
+ (INTERCONNECT wrapped_vga_clock.io_oeb[25] io_oeb[25] (0.077:0.077:0.077))
+ (INTERCONNECT wrapped_vga_clock.io_oeb[26] io_oeb[26] (0.116:0.116:0.116))
+ (INTERCONNECT wrapped_vga_clock.io_oeb[27] io_oeb[27] (0.060:0.060:0.060))
+ (INTERCONNECT wrapped_vga_clock.io_oeb[28] io_oeb[28] (0.069:0.069:0.069))
+ (INTERCONNECT wrapped_vga_clock.io_oeb[29] io_oeb[29] (0.089:0.089:0.089))
+ (INTERCONNECT wrapped_vga_clock.io_oeb[2] io_oeb[2] (0.104:0.104:0.104))
+ (INTERCONNECT wrapped_vga_clock.io_oeb[30] io_oeb[30] (0.025:0.025:0.025))
+ (INTERCONNECT wrapped_vga_clock.io_oeb[31] io_oeb[31] (0.047:0.047:0.047))
+ (INTERCONNECT wrapped_vga_clock.io_oeb[32] io_oeb[32] (0.027:0.027:0.027))
+ (INTERCONNECT wrapped_vga_clock.io_oeb[33] io_oeb[33] (0.018:0.018:0.018))
+ (INTERCONNECT wrapped_vga_clock.io_oeb[34] io_oeb[34] (0.042:0.042:0.042))
+ (INTERCONNECT wrapped_vga_clock.io_oeb[35] io_oeb[35] (0.027:0.027:0.027))
+ (INTERCONNECT wrapped_vga_clock.io_oeb[36] io_oeb[36] (0.040:0.040:0.040))
+ (INTERCONNECT wrapped_vga_clock.io_oeb[37] io_oeb[37] (0.050:0.050:0.050))
+ (INTERCONNECT wrapped_vga_clock.io_oeb[3] io_oeb[3] (0.101:0.101:0.101))
+ (INTERCONNECT wrapped_vga_clock.io_oeb[4] io_oeb[4] (0.190:0.190:0.190))
+ (INTERCONNECT wrapped_vga_clock.io_oeb[5] io_oeb[5] (0.165:0.165:0.165))
+ (INTERCONNECT wrapped_vga_clock.io_oeb[6] io_oeb[6] (0.115:0.115:0.115))
+ (INTERCONNECT wrapped_vga_clock.io_oeb[7] io_oeb[7] (0.214:0.214:0.214))
+ (INTERCONNECT wrapped_vga_clock.io_oeb[8] io_oeb[8] (0.124:0.124:0.124))
+ (INTERCONNECT wrapped_vga_clock.io_oeb[9] io_oeb[9] (0.115:0.115:0.115))
+ (INTERCONNECT wrapped_vga_clock.io_out[0] io_out[0] (0.111:0.111:0.111))
+ (INTERCONNECT wrapped_vga_clock.io_out[10] io_out[10] (0.175:0.175:0.175))
+ (INTERCONNECT wrapped_vga_clock.io_out[11] io_out[11] (0.530:0.530:0.530))
+ (INTERCONNECT wrapped_vga_clock.io_out[12] io_out[12] (0.157:0.157:0.157))
+ (INTERCONNECT wrapped_vga_clock.io_out[13] io_out[13] (0.187:0.187:0.187))
+ (INTERCONNECT wrapped_vga_clock.io_out[14] io_out[14] (0.217:0.217:0.217))
+ (INTERCONNECT wrapped_vga_clock.io_out[15] io_out[15] (0.169:0.169:0.169))
+ (INTERCONNECT wrapped_vga_clock.io_out[16] io_out[16] (0.173:0.173:0.173))
+ (INTERCONNECT wrapped_vga_clock.io_out[17] io_out[17] (0.161:0.161:0.161))
+ (INTERCONNECT wrapped_vga_clock.io_out[18] io_out[18] (0.136:0.136:0.136))
+ (INTERCONNECT wrapped_vga_clock.io_out[19] io_out[19] (0.219:0.219:0.219))
+ (INTERCONNECT wrapped_vga_clock.io_out[1] io_out[1] (0.118:0.118:0.118))
+ (INTERCONNECT wrapped_vga_clock.io_out[20] io_out[20] (0.104:0.104:0.104))
+ (INTERCONNECT wrapped_vga_clock.io_out[21] io_out[21] (0.115:0.115:0.115))
+ (INTERCONNECT wrapped_vga_clock.io_out[22] io_out[22] (0.063:0.063:0.063))
+ (INTERCONNECT wrapped_vga_clock.io_out[23] io_out[23] (0.085:0.085:0.085))
+ (INTERCONNECT wrapped_vga_clock.io_out[24] io_out[24] (0.100:0.100:0.100))
+ (INTERCONNECT wrapped_vga_clock.io_out[25] io_out[25] (0.081:0.081:0.081))
+ (INTERCONNECT wrapped_vga_clock.io_out[26] io_out[26] (0.077:0.077:0.077))
+ (INTERCONNECT wrapped_vga_clock.io_out[27] io_out[27] (0.065:0.065:0.065))
+ (INTERCONNECT wrapped_vga_clock.io_out[28] io_out[28] (0.051:0.051:0.051))
+ (INTERCONNECT wrapped_vga_clock.io_out[29] io_out[29] (0.041:0.041:0.041))
+ (INTERCONNECT wrapped_vga_clock.io_out[2] io_out[2] (0.093:0.093:0.093))
+ (INTERCONNECT wrapped_vga_clock.io_out[30] io_out[30] (0.047:0.047:0.047))
+ (INTERCONNECT wrapped_vga_clock.io_out[31] io_out[31] (0.062:0.062:0.062))
+ (INTERCONNECT wrapped_vga_clock.io_out[32] io_out[32] (0.014:0.014:0.014))
+ (INTERCONNECT wrapped_vga_clock.io_out[33] io_out[33] (0.013:0.013:0.013))
+ (INTERCONNECT wrapped_vga_clock.io_out[34] io_out[34] (0.017:0.017:0.017))
+ (INTERCONNECT wrapped_vga_clock.io_out[35] io_out[35] (0.024:0.024:0.024))
+ (INTERCONNECT wrapped_vga_clock.io_out[36] io_out[36] (0.031:0.031:0.031))
+ (INTERCONNECT wrapped_vga_clock.io_out[37] io_out[37] (0.059:0.059:0.059))
+ (INTERCONNECT wrapped_vga_clock.io_out[3] io_out[3] (0.078:0.078:0.078))
+ (INTERCONNECT wrapped_vga_clock.io_out[4] io_out[4] (0.155:0.155:0.155))
+ (INTERCONNECT wrapped_vga_clock.io_out[5] io_out[5] (0.109:0.109:0.109))
+ (INTERCONNECT wrapped_vga_clock.io_out[6] io_out[6] (0.093:0.093:0.093))
+ (INTERCONNECT wrapped_vga_clock.io_out[7] io_out[7] (0.102:0.102:0.102))
+ (INTERCONNECT wrapped_vga_clock.io_out[8] io_out[8] (0.133:0.133:0.133))
+ (INTERCONNECT wrapped_vga_clock.io_out[9] io_out[9] (0.142:0.142:0.142))
)
)
)
diff --git a/sdf/multicorner/nom/user_project_wrapper.ss.sdf b/sdf/multicorner/nom/user_project_wrapper.ss.sdf
index de6c4aa..4aaeaf5 100644
--- a/sdf/multicorner/nom/user_project_wrapper.ss.sdf
+++ b/sdf/multicorner/nom/user_project_wrapper.ss.sdf
@@ -1,7 +1,7 @@
(DELAYFILE
(SDFVERSION "3.0")
(DESIGN "user_project_wrapper")
- (DATE "Mon Nov 21 16:20:23 2022")
+ (DATE "Wed Nov 23 09:34:43 2022")
(VENDOR "Parallax")
(PROGRAM "STA")
(VERSION "2.3.2")
@@ -12,421 +12,122 @@
(INSTANCE)
(DELAY
(ABSOLUTE
- (INTERCONNECT io_in[0] mprj.io_in[0] (19.413:19.413:19.413) (7.461:7.461:7.461))
- (INTERCONNECT io_in[10] mprj.io_in[10] (13.839:13.839:13.839) (5.305:5.305:5.305))
- (INTERCONNECT io_in[11] mprj.io_in[11] (13.564:13.564:13.564) (5.201:5.201:5.201))
- (INTERCONNECT io_in[12] mprj.io_in[12] (14.404:14.404:14.404) (5.525:5.525:5.525))
- (INTERCONNECT io_in[13] mprj.io_in[13] (16.218:16.218:16.218) (6.226:6.226:6.226))
- (INTERCONNECT io_in[14] mprj.io_in[14] (16.547:16.547:16.547) (6.353:6.353:6.353))
- (INTERCONNECT io_in[15] mprj.io_in[15] (17.613:17.613:17.613) (6.764:6.764:6.764))
- (INTERCONNECT io_in[16] mprj.io_in[16] (19.482:19.482:19.482) (7.489:7.489:7.489))
- (INTERCONNECT io_in[17] mprj.io_in[17] (14.086:14.086:14.086) (5.399:5.399:5.399))
- (INTERCONNECT io_in[18] mprj.io_in[18] (26.792:26.792:26.792) (10.290:10.290:10.290))
- (INTERCONNECT io_in[19] mprj.io_in[19] (23.751:23.751:23.751) (9.115:9.115:9.115))
- (INTERCONNECT io_in[1] mprj.io_in[1] (28.121:28.121:28.121) (10.826:10.826:10.826))
- (INTERCONNECT io_in[20] mprj.io_in[20] (8.679:8.679:8.679) (3.319:3.319:3.319))
- (INTERCONNECT io_in[21] mprj.io_in[21] (8.315:8.315:8.315) (3.180:3.180:3.180))
- (INTERCONNECT io_in[22] mprj.io_in[22] (12.119:12.119:12.119) (4.639:4.639:4.639))
- (INTERCONNECT io_in[23] mprj.io_in[23] (11.549:11.549:11.549) (4.421:4.421:4.421))
- (INTERCONNECT io_in[24] mprj.io_in[24] (15.923:15.923:15.923) (6.107:6.107:6.107))
- (INTERCONNECT io_in[25] mprj.io_in[25] (12.698:12.698:12.698) (4.864:4.864:4.864))
- (INTERCONNECT io_in[26] mprj.io_in[26] (10.785:10.785:10.785) (4.127:4.127:4.127))
- (INTERCONNECT io_in[27] mprj.io_in[27] (31.247:31.247:31.247) (11.991:11.991:11.991))
- (INTERCONNECT io_in[28] mprj.io_in[28] (9.556:9.556:9.556) (3.655:3.655:3.655))
- (INTERCONNECT io_in[29] mprj.io_in[29] (9.382:9.382:9.382) (3.588:3.588:3.588))
- (INTERCONNECT io_in[2] mprj.io_in[2] (38.630:38.630:38.630) (14.859:14.859:14.859))
- (INTERCONNECT io_in[30] mprj.io_in[30] (7.074:7.074:7.074) (2.704:2.704:2.704))
- (INTERCONNECT io_in[31] mprj.io_in[31] (23.320:23.320:23.320) (8.925:8.925:8.925))
- (INTERCONNECT io_in[32] mprj.io_in[32] (35.456:35.456:35.456) (13.595:13.595:13.595))
- (INTERCONNECT io_in[33] mprj.io_in[33] (20.134:20.134:20.134) (7.714:7.714:7.714))
- (INTERCONNECT io_in[34] mprj.io_in[34] (36.795:36.795:36.795) (14.121:14.121:14.121))
- (INTERCONNECT io_in[35] mprj.io_in[35] (11.439:11.439:11.439) (4.378:4.378:4.378))
- (INTERCONNECT io_in[36] mprj.io_in[36] (17.370:17.370:17.370) (6.656:6.656:6.656))
- (INTERCONNECT io_in[37] mprj.io_in[37] (13.982:13.982:13.982) (5.360:5.360:5.360))
- (INTERCONNECT io_in[3] mprj.io_in[3] (27.576:27.576:27.576) (10.582:10.582:10.582))
- (INTERCONNECT io_in[4] mprj.io_in[4] (27.902:27.902:27.902) (10.728:10.728:10.728))
- (INTERCONNECT io_in[5] mprj.io_in[5] (34.476:34.476:34.476) (13.247:13.247:13.247))
- (INTERCONNECT io_in[6] mprj.io_in[6] (29.121:29.121:29.121) (11.184:11.184:11.184))
- (INTERCONNECT io_in[7] mprj.io_in[7] (35.583:35.583:35.583) (13.657:13.657:13.657))
- (INTERCONNECT io_in[8] mprj.io_in[8] (10.945:10.945:10.945) (4.191:4.191:4.191))
- (INTERCONNECT io_in[9] mprj.io_in[9] (22.628:22.628:22.628) (8.691:8.691:8.691))
- (INTERCONNECT la_data_in[0] mprj.la_data_in[0] (19.067:19.067:19.067) (7.294:7.294:7.294))
- (INTERCONNECT la_data_in[10] mprj.la_data_in[10] (10.058:10.058:10.058) (3.842:3.842:3.842))
- (INTERCONNECT la_data_in[11] mprj.la_data_in[11] (24.882:24.882:24.882) (9.530:9.530:9.530))
- (INTERCONNECT la_data_in[12] mprj.la_data_in[12] (10.340:10.340:10.340) (3.950:3.950:3.950))
- (INTERCONNECT la_data_in[13] mprj.la_data_in[13] (11.743:11.743:11.743) (4.485:4.485:4.485))
- (INTERCONNECT la_data_in[14] mprj.la_data_in[14] (34.065:34.065:34.065) (13.053:13.053:13.053))
- (INTERCONNECT la_data_in[15] mprj.la_data_in[15] (9.362:9.362:9.362) (3.578:3.578:3.578))
- (INTERCONNECT la_data_in[16] mprj.la_data_in[16] (24.242:24.242:24.242) (9.285:9.285:9.285))
- (INTERCONNECT la_data_in[17] mprj.la_data_in[17] (26.355:26.355:26.355) (10.094:10.094:10.094))
- (INTERCONNECT la_data_in[18] mprj.la_data_in[18] (24.779:24.779:24.779) (9.490:9.490:9.490))
- (INTERCONNECT la_data_in[19] mprj.la_data_in[19] (16.682:16.682:16.682) (6.383:6.383:6.383))
- (INTERCONNECT la_data_in[1] mprj.la_data_in[1] (18.664:18.664:18.664) (7.141:7.141:7.141))
- (INTERCONNECT la_data_in[20] mprj.la_data_in[20] (14.325:14.325:14.325) (5.480:5.480:5.480))
- (INTERCONNECT la_data_in[21] mprj.la_data_in[21] (23.176:23.176:23.176) (8.876:8.876:8.876))
- (INTERCONNECT la_data_in[22] mprj.la_data_in[22] (17.947:17.947:17.947) (6.869:6.869:6.869))
- (INTERCONNECT la_data_in[23] mprj.la_data_in[23] (20.112:20.112:20.112) (7.694:7.694:7.694))
- (INTERCONNECT la_data_in[24] mprj.la_data_in[24] (32.529:32.529:32.529) (12.466:12.466:12.466))
- (INTERCONNECT la_data_in[25] mprj.la_data_in[25] (15.170:15.170:15.170) (5.805:5.805:5.805))
- (INTERCONNECT la_data_in[26] mprj.la_data_in[26] (16.179:16.179:16.179) (6.192:6.192:6.192))
- (INTERCONNECT la_data_in[27] mprj.la_data_in[27] (24.958:24.958:24.958) (9.563:9.563:9.563))
- (INTERCONNECT la_data_in[28] mprj.la_data_in[28] (17.558:17.558:17.558) (6.720:6.720:6.720))
- (INTERCONNECT la_data_in[29] mprj.la_data_in[29] (18.454:18.454:18.454) (7.062:7.062:7.062))
- (INTERCONNECT la_data_in[2] mprj.la_data_in[2] (15.293:15.293:15.293) (5.844:5.844:5.844))
- (INTERCONNECT la_data_in[30] mprj.la_data_in[30] (26.859:26.859:26.859) (10.292:10.292:10.292))
- (INTERCONNECT la_data_in[31] mprj.la_data_in[31] (26.352:26.352:26.352) (10.097:10.097:10.097))
- (INTERCONNECT la_data_in[32] mprj.la_data_in[32] (27.323:27.323:27.323) (10.469:10.469:10.469))
- (INTERCONNECT la_data_in[33] mprj.la_data_in[33] (20.489:20.489:20.489) (7.849:7.849:7.849))
- (INTERCONNECT la_data_in[34] mprj.la_data_in[34] (21.427:21.427:21.427) (8.208:8.208:8.208))
- (INTERCONNECT la_data_in[35] mprj.la_data_in[35] (24.459:24.459:24.459) (9.373:9.373:9.373))
- (INTERCONNECT la_data_in[36] mprj.la_data_in[36] (21.909:21.909:21.909) (8.394:8.394:8.394))
- (INTERCONNECT la_data_in[37] mprj.la_data_in[37] (21.495:21.495:21.495) (8.235:8.235:8.235))
- (INTERCONNECT la_data_in[38] mprj.la_data_in[38] (28.398:28.398:28.398) (10.891:10.891:10.891))
- (INTERCONNECT la_data_in[39] mprj.la_data_in[39] (24.050:24.050:24.050) (9.217:9.217:9.217))
- (INTERCONNECT la_data_in[3] mprj.la_data_in[3] (6.529:6.529:6.529) (2.494:2.494:2.494))
- (INTERCONNECT la_data_in[40] mprj.la_data_in[40] (34.405:34.405:34.405) (13.198:13.198:13.198))
- (INTERCONNECT la_data_in[41] mprj.la_data_in[41] (21.996:21.996:21.996) (8.429:8.429:8.429))
- (INTERCONNECT la_data_in[42] mprj.la_data_in[42] (27.898:27.898:27.898) (10.701:10.701:10.701))
- (INTERCONNECT la_data_in[43] mprj.la_data_in[43] (38.420:38.420:38.420) (14.740:14.740:14.740))
- (INTERCONNECT la_data_in[44] mprj.la_data_in[44] (19.697:19.697:19.697) (7.548:7.548:7.548))
- (INTERCONNECT la_data_in[45] mprj.la_data_in[45] (34.106:34.106:34.106) (13.087:13.087:13.087))
- (INTERCONNECT la_data_in[46] mprj.la_data_in[46] (29.348:29.348:29.348) (11.262:11.262:11.262))
- (INTERCONNECT la_data_in[47] mprj.la_data_in[47] (39.023:39.023:39.023) (14.973:14.973:14.973))
- (INTERCONNECT la_data_in[48] mprj.la_data_in[48] (35.592:35.592:35.592) (13.656:13.656:13.656))
- (INTERCONNECT la_data_in[49] mprj.la_data_in[49] (31.960:31.960:31.960) (12.267:12.267:12.267))
- (INTERCONNECT la_data_in[4] mprj.la_data_in[4] (18.589:18.589:18.589) (7.113:7.113:7.113))
- (INTERCONNECT la_data_in[50] mprj.la_data_in[50] (43.701:43.701:43.701) (16.770:16.770:16.770))
- (INTERCONNECT la_data_in[51] mprj.la_data_in[51] (44.480:44.480:44.480) (17.069:17.069:17.069))
- (INTERCONNECT la_data_in[52] mprj.la_data_in[52] (42.530:42.530:42.530) (16.321:16.321:16.321))
- (INTERCONNECT la_data_in[53] mprj.la_data_in[53] (39.854:39.854:39.854) (15.295:15.295:15.295))
- (INTERCONNECT la_data_in[54] mprj.la_data_in[54] (20.197:20.197:20.197) (7.742:7.742:7.742))
- (INTERCONNECT la_data_in[55] mprj.la_data_in[55] (20.326:20.326:20.326) (7.793:7.793:7.793))
- (INTERCONNECT la_data_in[56] mprj.la_data_in[56] (41.371:41.371:41.371) (15.879:15.879:15.879))
- (INTERCONNECT la_data_in[57] mprj.la_data_in[57] (28.061:28.061:28.061) (10.769:10.769:10.769))
- (INTERCONNECT la_data_in[58] mprj.la_data_in[58] (24.406:24.406:24.406) (9.367:9.367:9.367))
- (INTERCONNECT la_data_in[59] mprj.la_data_in[59] (25.816:25.816:25.816) (9.908:9.908:9.908))
- (INTERCONNECT la_data_in[5] mprj.la_data_in[5] (18.541:18.541:18.541) (7.095:7.095:7.095))
- (INTERCONNECT la_data_in[60] mprj.la_data_in[60] (28.396:28.396:28.396) (10.900:10.900:10.900))
- (INTERCONNECT la_data_in[61] mprj.la_data_in[61] (33.890:33.890:33.890) (13.013:13.013:13.013))
- (INTERCONNECT la_data_in[62] mprj.la_data_in[62] (28.840:28.840:28.840) (11.071:11.071:11.071))
- (INTERCONNECT la_data_in[63] mprj.la_data_in[63] (24.639:24.639:24.639) (9.458:9.458:9.458))
- (INTERCONNECT la_data_in[6] mprj.la_data_in[6] (16.186:16.186:16.186) (6.191:6.191:6.191))
- (INTERCONNECT la_data_in[7] mprj.la_data_in[7] (29.075:29.075:29.075) (11.135:11.135:11.135))
- (INTERCONNECT la_data_in[8] mprj.la_data_in[8] (31.437:31.437:31.437) (12.041:12.041:12.041))
- (INTERCONNECT la_data_in[9] mprj.la_data_in[9] (8.050:8.050:8.050) (3.076:3.076:3.076))
- (INTERCONNECT la_oenb[0] mprj.la_oenb[0] (23.786:23.786:23.786) (9.102:9.102:9.102))
- (INTERCONNECT la_oenb[10] mprj.la_oenb[10] (19.799:19.799:19.799) (7.578:7.578:7.578))
- (INTERCONNECT la_oenb[11] mprj.la_oenb[11] (19.608:19.608:19.608) (7.505:7.505:7.505))
- (INTERCONNECT la_oenb[12] mprj.la_oenb[12] (13.738:13.738:13.738) (5.253:5.253:5.253))
- (INTERCONNECT la_oenb[13] mprj.la_oenb[13] (21.519:21.519:21.519) (8.238:8.238:8.238))
- (INTERCONNECT la_oenb[14] mprj.la_oenb[14] (11.794:11.794:11.794) (4.507:4.507:4.507))
- (INTERCONNECT la_oenb[15] mprj.la_oenb[15] (10.844:10.844:10.844) (4.144:4.144:4.144))
- (INTERCONNECT la_oenb[16] mprj.la_oenb[16] (7.068:7.068:7.068) (2.701:2.701:2.701))
- (INTERCONNECT la_oenb[17] mprj.la_oenb[17] (29.673:29.673:29.673) (11.370:11.370:11.370))
- (INTERCONNECT la_oenb[18] mprj.la_oenb[18] (14.162:14.162:14.162) (5.417:5.417:5.417))
- (INTERCONNECT la_oenb[19] mprj.la_oenb[19] (14.507:14.507:14.507) (5.549:5.549:5.549))
- (INTERCONNECT la_oenb[1] mprj.la_oenb[1] (14.934:14.934:14.934) (5.708:5.708:5.708))
- (INTERCONNECT la_oenb[20] mprj.la_oenb[20] (25.858:25.858:25.858) (9.907:9.907:9.907))
- (INTERCONNECT la_oenb[21] mprj.la_oenb[21] (11.884:11.884:11.884) (4.543:4.543:4.543))
- (INTERCONNECT la_oenb[22] mprj.la_oenb[22] (7.951:7.951:7.951) (3.039:3.039:3.039))
- (INTERCONNECT la_oenb[23] mprj.la_oenb[23] (26.659:26.659:26.659) (10.214:10.214:10.214))
- (INTERCONNECT la_oenb[24] mprj.la_oenb[24] (22.016:22.016:22.016) (8.431:8.431:8.431))
- (INTERCONNECT la_oenb[25] mprj.la_oenb[25] (36.216:36.216:36.216) (13.880:13.880:13.880))
- (INTERCONNECT la_oenb[26] mprj.la_oenb[26] (31.730:31.730:31.730) (12.160:12.160:12.160))
- (INTERCONNECT la_oenb[27] mprj.la_oenb[27] (20.403:20.403:20.403) (7.812:7.812:7.812))
- (INTERCONNECT la_oenb[28] mprj.la_oenb[28] (20.374:20.374:20.374) (7.801:7.801:7.801))
- (INTERCONNECT la_oenb[29] mprj.la_oenb[29] (25.639:25.639:25.639) (9.825:9.825:9.825))
- (INTERCONNECT la_oenb[2] mprj.la_oenb[2] (8.868:8.868:8.868) (3.388:3.388:3.388))
- (INTERCONNECT la_oenb[30] mprj.la_oenb[30] (29.253:29.253:29.253) (11.207:11.207:11.207))
- (INTERCONNECT la_oenb[31] mprj.la_oenb[31] (9.436:9.436:9.436) (3.608:3.608:3.608))
- (INTERCONNECT la_oenb[32] mprj.la_oenb[32] (29.992:29.992:29.992) (11.495:11.495:11.495))
- (INTERCONNECT la_oenb[33] mprj.la_oenb[33] (30.419:30.419:30.419) (11.656:11.656:11.656))
- (INTERCONNECT la_oenb[34] mprj.la_oenb[34] (22.026:22.026:22.026) (8.440:8.440:8.440))
- (INTERCONNECT la_oenb[35] mprj.la_oenb[35] (29.858:29.858:29.858) (11.431:11.431:11.431))
- (INTERCONNECT la_oenb[36] mprj.la_oenb[36] (30.343:30.343:30.343) (11.629:11.629:11.629))
- (INTERCONNECT la_oenb[37] mprj.la_oenb[37] (15.170:15.170:15.170) (5.804:5.804:5.804))
- (INTERCONNECT la_oenb[38] mprj.la_oenb[38] (44.488:44.488:44.488) (17.055:17.055:17.055))
- (INTERCONNECT la_oenb[39] mprj.la_oenb[39] (39.680:39.680:39.680) (15.204:15.204:15.204))
- (INTERCONNECT la_oenb[3] mprj.la_oenb[3] (8.233:8.233:8.233) (3.145:3.145:3.145))
- (INTERCONNECT la_oenb[40] mprj.la_oenb[40] (10.508:10.508:10.508) (4.019:4.019:4.019))
- (INTERCONNECT la_oenb[41] mprj.la_oenb[41] (19.784:19.784:19.784) (7.579:7.579:7.579))
- (INTERCONNECT la_oenb[42] mprj.la_oenb[42] (14.396:14.396:14.396) (5.509:5.509:5.509))
- (INTERCONNECT la_oenb[43] mprj.la_oenb[43] (10.177:10.177:10.177) (3.893:3.893:3.893))
- (INTERCONNECT la_oenb[44] mprj.la_oenb[44] (36.380:36.380:36.380) (13.956:13.956:13.956))
- (INTERCONNECT la_oenb[45] mprj.la_oenb[45] (26.969:26.969:26.969) (10.340:10.340:10.340))
- (INTERCONNECT la_oenb[46] mprj.la_oenb[46] (38.149:38.149:38.149) (14.636:14.636:14.636))
- (INTERCONNECT la_oenb[47] mprj.la_oenb[47] (27.844:27.844:27.844) (10.670:10.670:10.670))
- (INTERCONNECT la_oenb[48] mprj.la_oenb[48] (14.436:14.436:14.436) (5.526:5.526:5.526))
- (INTERCONNECT la_oenb[49] mprj.la_oenb[49] (22.110:22.110:22.110) (8.470:8.470:8.470))
- (INTERCONNECT la_oenb[4] mprj.la_oenb[4] (28.528:28.528:28.528) (10.923:10.923:10.923))
- (INTERCONNECT la_oenb[50] mprj.la_oenb[50] (40.898:40.898:40.898) (15.692:15.692:15.692))
- (INTERCONNECT la_oenb[51] mprj.la_oenb[51] (43.528:43.528:43.528) (16.680:16.680:16.680))
- (INTERCONNECT la_oenb[52] mprj.la_oenb[52] (26.922:26.922:26.922) (10.318:10.318:10.318))
- (INTERCONNECT la_oenb[53] mprj.la_oenb[53] (30.630:30.630:30.630) (11.752:11.752:11.752))
- (INTERCONNECT la_oenb[54] mprj.la_oenb[54] (55.622:55.622:55.622) (21.347:21.347:21.347))
- (INTERCONNECT la_oenb[55] mprj.la_oenb[55] (46.103:46.103:46.103) (17.692:17.692:17.692))
- (INTERCONNECT la_oenb[56] mprj.la_oenb[56] (35.531:35.531:35.531) (13.637:13.637:13.637))
- (INTERCONNECT la_oenb[57] mprj.la_oenb[57] (36.013:36.013:36.013) (13.803:13.803:13.803))
- (INTERCONNECT la_oenb[58] mprj.la_oenb[58] (48.756:48.756:48.756) (18.716:18.716:18.716))
- (INTERCONNECT la_oenb[59] mprj.la_oenb[59] (21.703:21.703:21.703) (8.329:8.329:8.329))
- (INTERCONNECT la_oenb[5] mprj.la_oenb[5] (21.865:21.865:21.865) (8.371:8.371:8.371))
- (INTERCONNECT la_oenb[60] mprj.la_oenb[60] (11.173:11.173:11.173) (4.276:4.276:4.276))
- (INTERCONNECT la_oenb[61] mprj.la_oenb[61] (29.603:29.603:29.603) (11.366:11.366:11.366))
- (INTERCONNECT la_oenb[62] mprj.la_oenb[62] (48.400:48.400:48.400) (18.578:18.578:18.578))
- (INTERCONNECT la_oenb[63] mprj.la_oenb[63] (12.639:12.639:12.639) (4.838:4.838:4.838))
- (INTERCONNECT la_oenb[6] mprj.la_oenb[6] (24.978:24.978:24.978) (9.565:9.565:9.565))
- (INTERCONNECT la_oenb[7] mprj.la_oenb[7] (11.842:11.842:11.842) (4.525:4.525:4.525))
- (INTERCONNECT la_oenb[8] mprj.la_oenb[8] (19.664:19.664:19.664) (7.527:7.527:7.527))
- (INTERCONNECT la_oenb[9] mprj.la_oenb[9] (24.183:24.183:24.183) (9.261:9.261:9.261))
- (INTERCONNECT wb_clk_i mprj.wb_clk_i (9.655:9.655:9.655) (3.690:3.690:3.690))
- (INTERCONNECT wb_rst_i mprj.wb_rst_i (18.983:18.983:18.983) (7.266:7.266:7.266))
- (INTERCONNECT wbs_adr_i[0] mprj.wbs_adr_i[0] (13.023:13.023:13.023) (4.980:4.980:4.980))
- (INTERCONNECT wbs_adr_i[10] mprj.wbs_adr_i[10] (7.024:7.024:7.024) (2.684:2.684:2.684))
- (INTERCONNECT wbs_adr_i[11] mprj.wbs_adr_i[11] (11.320:11.320:11.320) (4.325:4.325:4.325))
- (INTERCONNECT wbs_adr_i[12] mprj.wbs_adr_i[12] (10.937:10.937:10.937) (4.178:4.178:4.178))
- (INTERCONNECT wbs_adr_i[13] mprj.wbs_adr_i[13] (9.887:9.887:9.887) (3.776:3.776:3.776))
- (INTERCONNECT wbs_adr_i[14] mprj.wbs_adr_i[14] (10.018:10.018:10.018) (3.826:3.826:3.826))
- (INTERCONNECT wbs_adr_i[15] mprj.wbs_adr_i[15] (9.755:9.755:9.755) (3.726:3.726:3.726))
- (INTERCONNECT wbs_adr_i[16] mprj.wbs_adr_i[16] (18.146:18.146:18.146) (6.939:6.939:6.939))
- (INTERCONNECT wbs_adr_i[17] mprj.wbs_adr_i[17] (16.884:16.884:16.884) (6.455:6.455:6.455))
- (INTERCONNECT wbs_adr_i[18] mprj.wbs_adr_i[18] (14.568:14.568:14.568) (5.569:5.569:5.569))
- (INTERCONNECT wbs_adr_i[19] mprj.wbs_adr_i[19] (6.423:6.423:6.423) (2.453:2.453:2.453))
- (INTERCONNECT wbs_adr_i[1] mprj.wbs_adr_i[1] (9.853:9.853:9.853) (3.766:3.766:3.766))
- (INTERCONNECT wbs_adr_i[20] mprj.wbs_adr_i[20] (15.120:15.120:15.120) (5.779:5.779:5.779))
- (INTERCONNECT wbs_adr_i[21] mprj.wbs_adr_i[21] (7.724:7.724:7.724) (2.950:2.950:2.950))
- (INTERCONNECT wbs_adr_i[22] mprj.wbs_adr_i[22] (6.841:6.841:6.841) (2.612:2.612:2.612))
- (INTERCONNECT wbs_adr_i[23] mprj.wbs_adr_i[23] (7.484:7.484:7.484) (2.858:2.858:2.858))
- (INTERCONNECT wbs_adr_i[24] mprj.wbs_adr_i[24] (15.292:15.292:15.292) (5.843:5.843:5.843))
- (INTERCONNECT wbs_adr_i[25] mprj.wbs_adr_i[25] (4.686:4.686:4.686) (1.790:1.790:1.790))
- (INTERCONNECT wbs_adr_i[26] mprj.wbs_adr_i[26] (5.188:5.188:5.188) (1.981:1.981:1.981))
- (INTERCONNECT wbs_adr_i[27] mprj.wbs_adr_i[27] (5.971:5.971:5.971) (2.280:2.280:2.280))
- (INTERCONNECT wbs_adr_i[28] mprj.wbs_adr_i[28] (8.501:8.501:8.501) (3.247:3.247:3.247))
- (INTERCONNECT wbs_adr_i[29] mprj.wbs_adr_i[29] (21.211:21.211:21.211) (8.116:8.116:8.116))
- (INTERCONNECT wbs_adr_i[2] mprj.wbs_adr_i[2] (15.220:15.220:15.220) (5.817:5.817:5.817))
- (INTERCONNECT wbs_adr_i[30] mprj.wbs_adr_i[30] (15.673:15.673:15.673) (5.994:5.994:5.994))
- (INTERCONNECT wbs_adr_i[31] mprj.wbs_adr_i[31] (11.646:11.646:11.646) (4.449:4.449:4.449))
- (INTERCONNECT wbs_adr_i[3] mprj.wbs_adr_i[3] (18.768:18.768:18.768) (7.180:7.180:7.180))
- (INTERCONNECT wbs_adr_i[4] mprj.wbs_adr_i[4] (14.424:14.424:14.424) (5.516:5.516:5.516))
- (INTERCONNECT wbs_adr_i[5] mprj.wbs_adr_i[5] (11.340:11.340:11.340) (4.333:4.333:4.333))
- (INTERCONNECT wbs_adr_i[6] mprj.wbs_adr_i[6] (16.166:16.166:16.166) (6.184:6.184:6.184))
- (INTERCONNECT wbs_adr_i[7] mprj.wbs_adr_i[7] (15.202:15.202:15.202) (5.814:5.814:5.814))
- (INTERCONNECT wbs_adr_i[8] mprj.wbs_adr_i[8] (13.588:13.588:13.588) (5.195:5.195:5.195))
- (INTERCONNECT wbs_adr_i[9] mprj.wbs_adr_i[9] (11.650:11.650:11.650) (4.451:4.451:4.451))
- (INTERCONNECT wbs_cyc_i mprj.wbs_cyc_i (14.144:14.144:14.144) (5.410:5.410:5.410))
- (INTERCONNECT wbs_dat_i[0] mprj.wbs_dat_i[0] (20.242:20.242:20.242) (7.749:7.749:7.749))
- (INTERCONNECT wbs_dat_i[10] mprj.wbs_dat_i[10] (10.993:10.993:10.993) (4.199:4.199:4.199))
- (INTERCONNECT wbs_dat_i[11] mprj.wbs_dat_i[11] (12.150:12.150:12.150) (4.642:4.642:4.642))
- (INTERCONNECT wbs_dat_i[12] mprj.wbs_dat_i[12] (10.867:10.867:10.867) (4.151:4.151:4.151))
- (INTERCONNECT wbs_dat_i[13] mprj.wbs_dat_i[13] (8.690:8.690:8.690) (3.320:3.320:3.320))
- (INTERCONNECT wbs_dat_i[14] mprj.wbs_dat_i[14] (8.907:8.907:8.907) (3.403:3.403:3.403))
- (INTERCONNECT wbs_dat_i[15] mprj.wbs_dat_i[15] (12.304:12.304:12.304) (4.701:4.701:4.701))
- (INTERCONNECT wbs_dat_i[16] mprj.wbs_dat_i[16] (7.263:7.263:7.263) (2.774:2.774:2.774))
- (INTERCONNECT wbs_dat_i[17] mprj.wbs_dat_i[17] (13.964:13.964:13.964) (5.337:5.337:5.337))
- (INTERCONNECT wbs_dat_i[18] mprj.wbs_dat_i[18] (7.217:7.217:7.217) (2.757:2.757:2.757))
- (INTERCONNECT wbs_dat_i[19] mprj.wbs_dat_i[19] (5.991:5.991:5.991) (2.288:2.288:2.288))
- (INTERCONNECT wbs_dat_i[1] mprj.wbs_dat_i[1] (12.504:12.504:12.504) (4.780:4.780:4.780))
- (INTERCONNECT wbs_dat_i[20] mprj.wbs_dat_i[20] (8.694:8.694:8.694) (3.320:3.320:3.320))
- (INTERCONNECT wbs_dat_i[21] mprj.wbs_dat_i[21] (7.508:7.508:7.508) (2.867:2.867:2.867))
- (INTERCONNECT wbs_dat_i[22] mprj.wbs_dat_i[22] (7.206:7.206:7.206) (2.751:2.751:2.751))
- (INTERCONNECT wbs_dat_i[23] mprj.wbs_dat_i[23] (6.841:6.841:6.841) (2.612:2.612:2.612))
- (INTERCONNECT wbs_dat_i[24] mprj.wbs_dat_i[24] (4.661:4.661:4.661) (1.780:1.780:1.780))
- (INTERCONNECT wbs_dat_i[25] mprj.wbs_dat_i[25] (15.921:15.921:15.921) (6.085:6.085:6.085))
- (INTERCONNECT wbs_dat_i[26] mprj.wbs_dat_i[26] (7.832:7.832:7.832) (2.990:2.990:2.990))
- (INTERCONNECT wbs_dat_i[27] mprj.wbs_dat_i[27] (9.302:9.302:9.302) (3.553:3.553:3.553))
- (INTERCONNECT wbs_dat_i[28] mprj.wbs_dat_i[28] (8.405:8.405:8.405) (3.211:3.211:3.211))
- (INTERCONNECT wbs_dat_i[29] mprj.wbs_dat_i[29] (8.612:8.612:8.612) (3.290:3.290:3.290))
- (INTERCONNECT wbs_dat_i[2] mprj.wbs_dat_i[2] (6.277:6.277:6.277) (2.398:2.398:2.398))
- (INTERCONNECT wbs_dat_i[30] mprj.wbs_dat_i[30] (15.815:15.815:15.815) (6.044:6.044:6.044))
- (INTERCONNECT wbs_dat_i[31] mprj.wbs_dat_i[31] (15.231:15.231:15.231) (5.822:5.822:5.822))
- (INTERCONNECT wbs_dat_i[3] mprj.wbs_dat_i[3] (17.782:17.782:17.782) (6.804:6.804:6.804))
- (INTERCONNECT wbs_dat_i[4] mprj.wbs_dat_i[4] (16.324:16.324:16.324) (6.244:6.244:6.244))
- (INTERCONNECT wbs_dat_i[5] mprj.wbs_dat_i[5] (14.868:14.868:14.868) (5.686:5.686:5.686))
- (INTERCONNECT wbs_dat_i[6] mprj.wbs_dat_i[6] (11.378:11.378:11.378) (4.347:4.347:4.347))
- (INTERCONNECT wbs_dat_i[7] mprj.wbs_dat_i[7] (14.090:14.090:14.090) (5.387:5.387:5.387))
- (INTERCONNECT wbs_dat_i[8] mprj.wbs_dat_i[8] (9.967:9.967:9.967) (3.808:3.808:3.808))
- (INTERCONNECT wbs_dat_i[9] mprj.wbs_dat_i[9] (9.939:9.939:9.939) (3.797:3.797:3.797))
- (INTERCONNECT wbs_sel_i[0] mprj.wbs_sel_i[0] (7.118:7.118:7.118) (2.720:2.720:2.720))
- (INTERCONNECT wbs_sel_i[1] mprj.wbs_sel_i[1] (13.782:13.782:13.782) (5.270:5.270:5.270))
- (INTERCONNECT wbs_sel_i[2] mprj.wbs_sel_i[2] (10.712:10.712:10.712) (4.093:4.093:4.093))
- (INTERCONNECT wbs_sel_i[3] mprj.wbs_sel_i[3] (16.486:16.486:16.486) (6.307:6.307:6.307))
- (INTERCONNECT wbs_stb_i mprj.wbs_stb_i (11.469:11.469:11.469) (4.384:4.384:4.384))
- (INTERCONNECT wbs_we_i mprj.wbs_we_i (11.837:11.837:11.837) (4.525:4.525:4.525))
- (INTERCONNECT mprj.io_oeb[0] io_oeb[0] (0.399:0.399:0.399))
- (INTERCONNECT mprj.io_oeb[10] io_oeb[10] (0.104:0.104:0.104))
- (INTERCONNECT mprj.io_oeb[11] io_oeb[11] (0.114:0.114:0.114))
- (INTERCONNECT mprj.io_oeb[12] io_oeb[12] (0.135:0.135:0.135))
- (INTERCONNECT mprj.io_oeb[13] io_oeb[13] (0.134:0.134:0.134))
- (INTERCONNECT mprj.io_oeb[14] io_oeb[14] (0.147:0.147:0.147))
- (INTERCONNECT mprj.io_oeb[15] io_oeb[15] (0.288:0.288:0.288))
- (INTERCONNECT mprj.io_oeb[16] io_oeb[16] (0.232:0.232:0.232))
- (INTERCONNECT mprj.io_oeb[17] io_oeb[17] (0.092:0.092:0.092))
- (INTERCONNECT mprj.io_oeb[18] io_oeb[18] (0.074:0.074:0.074))
- (INTERCONNECT mprj.io_oeb[19] io_oeb[19] (0.060:0.060:0.060))
- (INTERCONNECT mprj.io_oeb[1] io_oeb[1] (0.266:0.266:0.266))
- (INTERCONNECT mprj.io_oeb[20] io_oeb[20] (0.044:0.044:0.044))
- (INTERCONNECT mprj.io_oeb[21] io_oeb[21] (0.067:0.067:0.067))
- (INTERCONNECT mprj.io_oeb[22] io_oeb[22] (0.076:0.076:0.076))
- (INTERCONNECT mprj.io_oeb[23] io_oeb[23] (0.094:0.094:0.094))
- (INTERCONNECT mprj.io_oeb[24] io_oeb[24] (0.085:0.085:0.085))
- (INTERCONNECT mprj.io_oeb[25] io_oeb[25] (0.076:0.076:0.076))
- (INTERCONNECT mprj.io_oeb[26] io_oeb[26] (0.284:0.284:0.284))
- (INTERCONNECT mprj.io_oeb[27] io_oeb[27] (0.242:0.242:0.242))
- (INTERCONNECT mprj.io_oeb[28] io_oeb[28] (0.051:0.051:0.051))
- (INTERCONNECT mprj.io_oeb[29] io_oeb[29] (0.043:0.043:0.043))
- (INTERCONNECT mprj.io_oeb[2] io_oeb[2] (0.306:0.306:0.306))
- (INTERCONNECT mprj.io_oeb[30] io_oeb[30] (0.148:0.148:0.148))
- (INTERCONNECT mprj.io_oeb[31] io_oeb[31] (0.055:0.055:0.055))
- (INTERCONNECT mprj.io_oeb[32] io_oeb[32] (0.176:0.176:0.176))
- (INTERCONNECT mprj.io_oeb[33] io_oeb[33] (0.183:0.183:0.183))
- (INTERCONNECT mprj.io_oeb[34] io_oeb[34] (0.161:0.161:0.161))
- (INTERCONNECT mprj.io_oeb[35] io_oeb[35] (0.147:0.147:0.147))
- (INTERCONNECT mprj.io_oeb[36] io_oeb[36] (0.234:0.234:0.234))
- (INTERCONNECT mprj.io_oeb[37] io_oeb[37] (0.246:0.246:0.246))
- (INTERCONNECT mprj.io_oeb[3] io_oeb[3] (0.255:0.255:0.255))
- (INTERCONNECT mprj.io_oeb[4] io_oeb[4] (0.161:0.161:0.161))
- (INTERCONNECT mprj.io_oeb[5] io_oeb[5] (0.116:0.116:0.116))
- (INTERCONNECT mprj.io_oeb[6] io_oeb[6] (0.151:0.151:0.151))
- (INTERCONNECT mprj.io_oeb[7] io_oeb[7] (0.177:0.177:0.177))
- (INTERCONNECT mprj.io_oeb[8] io_oeb[8] (0.084:0.084:0.084))
- (INTERCONNECT mprj.io_oeb[9] io_oeb[9] (0.094:0.094:0.094))
- (INTERCONNECT mprj.io_out[0] io_out[0] (0.406:0.406:0.406))
- (INTERCONNECT mprj.io_out[10] io_out[10] (0.099:0.099:0.099))
- (INTERCONNECT mprj.io_out[11] io_out[11] (0.110:0.110:0.110))
- (INTERCONNECT mprj.io_out[12] io_out[12] (0.119:0.119:0.119))
- (INTERCONNECT mprj.io_out[13] io_out[13] (0.129:0.129:0.129))
- (INTERCONNECT mprj.io_out[14] io_out[14] (0.167:0.167:0.167))
- (INTERCONNECT mprj.io_out[15] io_out[15] (0.244:0.244:0.244))
- (INTERCONNECT mprj.io_out[16] io_out[16] (0.117:0.117:0.117))
- (INTERCONNECT mprj.io_out[17] io_out[17] (0.171:0.171:0.171))
- (INTERCONNECT mprj.io_out[18] io_out[18] (0.133:0.133:0.133))
- (INTERCONNECT mprj.io_out[19] io_out[19] (0.078:0.078:0.078))
- (INTERCONNECT mprj.io_out[1] io_out[1] (0.194:0.194:0.194))
- (INTERCONNECT mprj.io_out[20] io_out[20] (0.048:0.048:0.048))
- (INTERCONNECT mprj.io_out[21] io_out[21] (0.059:0.059:0.059))
- (INTERCONNECT mprj.io_out[22] io_out[22] (0.092:0.092:0.092))
- (INTERCONNECT mprj.io_out[23] io_out[23] (0.105:0.105:0.105))
- (INTERCONNECT mprj.io_out[24] io_out[24] (0.095:0.095:0.095))
- (INTERCONNECT mprj.io_out[25] io_out[25] (0.245:0.245:0.245))
- (INTERCONNECT mprj.io_out[26] io_out[26] (0.077:0.077:0.077))
- (INTERCONNECT mprj.io_out[27] io_out[27] (0.063:0.063:0.063))
- (INTERCONNECT mprj.io_out[28] io_out[28] (0.055:0.055:0.055))
- (INTERCONNECT mprj.io_out[29] io_out[29] (0.204:0.204:0.204))
- (INTERCONNECT mprj.io_out[2] io_out[2] (0.210:0.210:0.210))
- (INTERCONNECT mprj.io_out[30] io_out[30] (0.039:0.039:0.039))
- (INTERCONNECT mprj.io_out[31] io_out[31] (0.049:0.049:0.049))
- (INTERCONNECT mprj.io_out[32] io_out[32] (0.085:0.085:0.085))
- (INTERCONNECT mprj.io_out[33] io_out[33] (0.118:0.118:0.118))
- (INTERCONNECT mprj.io_out[34] io_out[34] (0.147:0.147:0.147))
- (INTERCONNECT mprj.io_out[35] io_out[35] (0.160:0.160:0.160))
- (INTERCONNECT mprj.io_out[36] io_out[36] (0.125:0.125:0.125))
- (INTERCONNECT mprj.io_out[37] io_out[37] (0.103:0.103:0.103))
- (INTERCONNECT mprj.io_out[3] io_out[3] (0.191:0.191:0.191))
- (INTERCONNECT mprj.io_out[4] io_out[4] (0.136:0.136:0.136))
- (INTERCONNECT mprj.io_out[5] io_out[5] (0.159:0.159:0.159))
- (INTERCONNECT mprj.io_out[6] io_out[6] (0.135:0.135:0.135))
- (INTERCONNECT mprj.io_out[7] io_out[7] (0.126:0.126:0.126))
- (INTERCONNECT mprj.io_out[8] io_out[8] (0.080:0.080:0.080))
- (INTERCONNECT mprj.io_out[9] io_out[9] (0.091:0.091:0.091))
- (INTERCONNECT mprj.irq[0] user_irq[0] (0.160:0.160:0.160))
- (INTERCONNECT mprj.irq[1] user_irq[1] (0.164:0.164:0.164))
- (INTERCONNECT mprj.irq[2] user_irq[2] (0.096:0.096:0.096))
- (INTERCONNECT mprj.la_data_out[0] la_data_out[0] (0.047:0.047:0.047))
- (INTERCONNECT mprj.la_data_out[10] la_data_out[10] (0.100:0.100:0.100))
- (INTERCONNECT mprj.la_data_out[11] la_data_out[11] (0.080:0.080:0.080))
- (INTERCONNECT mprj.la_data_out[12] la_data_out[12] (0.080:0.080:0.080))
- (INTERCONNECT mprj.la_data_out[13] la_data_out[13] (0.100:0.100:0.100))
- (INTERCONNECT mprj.la_data_out[14] la_data_out[14] (0.064:0.064:0.064))
- (INTERCONNECT mprj.la_data_out[15] la_data_out[15] (0.080:0.080:0.080))
- (INTERCONNECT mprj.la_data_out[16] la_data_out[16] (0.045:0.045:0.045))
- (INTERCONNECT mprj.la_data_out[17] la_data_out[17] (0.129:0.129:0.129))
- (INTERCONNECT mprj.la_data_out[18] la_data_out[18] (0.073:0.073:0.073))
- (INTERCONNECT mprj.la_data_out[19] la_data_out[19] (0.051:0.051:0.051))
- (INTERCONNECT mprj.la_data_out[1] la_data_out[1] (0.061:0.061:0.061))
- (INTERCONNECT mprj.la_data_out[20] la_data_out[20] (0.131:0.131:0.131))
- (INTERCONNECT mprj.la_data_out[21] la_data_out[21] (0.045:0.045:0.045))
- (INTERCONNECT mprj.la_data_out[22] la_data_out[22] (0.054:0.054:0.054))
- (INTERCONNECT mprj.la_data_out[23] la_data_out[23] (0.062:0.062:0.062))
- (INTERCONNECT mprj.la_data_out[24] la_data_out[24] (0.076:0.076:0.076))
- (INTERCONNECT mprj.la_data_out[25] la_data_out[25] (0.075:0.075:0.075))
- (INTERCONNECT mprj.la_data_out[26] la_data_out[26] (0.095:0.095:0.095))
- (INTERCONNECT mprj.la_data_out[27] la_data_out[27] (0.071:0.071:0.071))
- (INTERCONNECT mprj.la_data_out[28] la_data_out[28] (0.102:0.102:0.102))
- (INTERCONNECT mprj.la_data_out[29] la_data_out[29] (0.072:0.072:0.072))
- (INTERCONNECT mprj.la_data_out[2] la_data_out[2] (0.038:0.038:0.038))
- (INTERCONNECT mprj.la_data_out[30] la_data_out[30] (0.102:0.102:0.102))
- (INTERCONNECT mprj.la_data_out[31] la_data_out[31] (0.080:0.080:0.080))
- (INTERCONNECT mprj.la_data_out[32] la_data_out[32] (0.101:0.101:0.101))
- (INTERCONNECT mprj.la_data_out[33] la_data_out[33] (0.107:0.107:0.107))
- (INTERCONNECT mprj.la_data_out[34] la_data_out[34] (0.119:0.119:0.119))
- (INTERCONNECT mprj.la_data_out[35] la_data_out[35] (0.119:0.119:0.119))
- (INTERCONNECT mprj.la_data_out[36] la_data_out[36] (0.072:0.072:0.072))
- (INTERCONNECT mprj.la_data_out[37] la_data_out[37] (0.095:0.095:0.095))
- (INTERCONNECT mprj.la_data_out[38] la_data_out[38] (0.142:0.142:0.142))
- (INTERCONNECT mprj.la_data_out[39] la_data_out[39] (0.137:0.137:0.137))
- (INTERCONNECT mprj.la_data_out[3] la_data_out[3] (0.055:0.055:0.055))
- (INTERCONNECT mprj.la_data_out[40] la_data_out[40] (0.104:0.104:0.104))
- (INTERCONNECT mprj.la_data_out[41] la_data_out[41] (0.141:0.141:0.141))
- (INTERCONNECT mprj.la_data_out[42] la_data_out[42] (0.156:0.156:0.156))
- (INTERCONNECT mprj.la_data_out[43] la_data_out[43] (0.160:0.160:0.160))
- (INTERCONNECT mprj.la_data_out[44] la_data_out[44] (0.135:0.135:0.135))
- (INTERCONNECT mprj.la_data_out[45] la_data_out[45] (0.072:0.072:0.072))
- (INTERCONNECT mprj.la_data_out[46] la_data_out[46] (0.155:0.155:0.155))
- (INTERCONNECT mprj.la_data_out[47] la_data_out[47] (0.142:0.142:0.142))
- (INTERCONNECT mprj.la_data_out[48] la_data_out[48] (0.184:0.184:0.184))
- (INTERCONNECT mprj.la_data_out[49] la_data_out[49] (0.126:0.126:0.126))
- (INTERCONNECT mprj.la_data_out[4] la_data_out[4] (0.087:0.087:0.087))
- (INTERCONNECT mprj.la_data_out[50] la_data_out[50] (0.198:0.198:0.198))
- (INTERCONNECT mprj.la_data_out[51] la_data_out[51] (0.205:0.205:0.205))
- (INTERCONNECT mprj.la_data_out[52] la_data_out[52] (0.141:0.141:0.141))
- (INTERCONNECT mprj.la_data_out[53] la_data_out[53] (0.144:0.144:0.144))
- (INTERCONNECT mprj.la_data_out[54] la_data_out[54] (0.126:0.126:0.126))
- (INTERCONNECT mprj.la_data_out[55] la_data_out[55] (0.220:0.220:0.220))
- (INTERCONNECT mprj.la_data_out[56] la_data_out[56] (0.238:0.238:0.238))
- (INTERCONNECT mprj.la_data_out[57] la_data_out[57] (0.126:0.126:0.126))
- (INTERCONNECT mprj.la_data_out[58] la_data_out[58] (0.158:0.158:0.158))
- (INTERCONNECT mprj.la_data_out[59] la_data_out[59] (0.151:0.151:0.151))
- (INTERCONNECT mprj.la_data_out[5] la_data_out[5] (0.083:0.083:0.083))
- (INTERCONNECT mprj.la_data_out[60] la_data_out[60] (0.247:0.247:0.247))
- (INTERCONNECT mprj.la_data_out[61] la_data_out[61] (0.105:0.105:0.105))
- (INTERCONNECT mprj.la_data_out[62] la_data_out[62] (0.165:0.165:0.165))
- (INTERCONNECT mprj.la_data_out[63] la_data_out[63] (0.172:0.172:0.172))
- (INTERCONNECT mprj.la_data_out[6] la_data_out[6] (0.047:0.047:0.047))
- (INTERCONNECT mprj.la_data_out[7] la_data_out[7] (0.066:0.066:0.066))
- (INTERCONNECT mprj.la_data_out[8] la_data_out[8] (0.059:0.059:0.059))
- (INTERCONNECT mprj.la_data_out[9] la_data_out[9] (0.065:0.065:0.065))
- (INTERCONNECT mprj.wbs_ack_o wbs_ack_o (0.037:0.037:0.037))
- (INTERCONNECT mprj.wbs_dat_o[0] wbs_dat_o[0] (0.035:0.035:0.035))
- (INTERCONNECT mprj.wbs_dat_o[10] wbs_dat_o[10] (0.031:0.031:0.031))
- (INTERCONNECT mprj.wbs_dat_o[11] wbs_dat_o[11] (0.047:0.047:0.047))
- (INTERCONNECT mprj.wbs_dat_o[12] wbs_dat_o[12] (0.031:0.031:0.031))
- (INTERCONNECT mprj.wbs_dat_o[13] wbs_dat_o[13] (0.026:0.026:0.026))
- (INTERCONNECT mprj.wbs_dat_o[14] wbs_dat_o[14] (0.040:0.040:0.040))
- (INTERCONNECT mprj.wbs_dat_o[15] wbs_dat_o[15] (0.027:0.027:0.027))
- (INTERCONNECT mprj.wbs_dat_o[16] wbs_dat_o[16] (0.033:0.033:0.033))
- (INTERCONNECT mprj.wbs_dat_o[17] wbs_dat_o[17] (0.030:0.030:0.030))
- (INTERCONNECT mprj.wbs_dat_o[18] wbs_dat_o[18] (0.038:0.038:0.038))
- (INTERCONNECT mprj.wbs_dat_o[19] wbs_dat_o[19] (0.027:0.027:0.027))
- (INTERCONNECT mprj.wbs_dat_o[1] wbs_dat_o[1] (0.059:0.059:0.059))
- (INTERCONNECT mprj.wbs_dat_o[20] wbs_dat_o[20] (0.038:0.038:0.038))
- (INTERCONNECT mprj.wbs_dat_o[21] wbs_dat_o[21] (0.031:0.031:0.031))
- (INTERCONNECT mprj.wbs_dat_o[22] wbs_dat_o[22] (0.050:0.050:0.050))
- (INTERCONNECT mprj.wbs_dat_o[23] wbs_dat_o[23] (0.048:0.048:0.048))
- (INTERCONNECT mprj.wbs_dat_o[24] wbs_dat_o[24] (0.049:0.049:0.049))
- (INTERCONNECT mprj.wbs_dat_o[25] wbs_dat_o[25] (0.059:0.059:0.059))
- (INTERCONNECT mprj.wbs_dat_o[26] wbs_dat_o[26] (0.047:0.047:0.047))
- (INTERCONNECT mprj.wbs_dat_o[27] wbs_dat_o[27] (0.038:0.038:0.038))
- (INTERCONNECT mprj.wbs_dat_o[28] wbs_dat_o[28] (0.056:0.056:0.056))
- (INTERCONNECT mprj.wbs_dat_o[29] wbs_dat_o[29] (0.050:0.050:0.050))
- (INTERCONNECT mprj.wbs_dat_o[2] wbs_dat_o[2] (0.052:0.052:0.052))
- (INTERCONNECT mprj.wbs_dat_o[30] wbs_dat_o[30] (0.044:0.044:0.044))
- (INTERCONNECT mprj.wbs_dat_o[31] wbs_dat_o[31] (0.059:0.059:0.059))
- (INTERCONNECT mprj.wbs_dat_o[3] wbs_dat_o[3] (0.052:0.052:0.052))
- (INTERCONNECT mprj.wbs_dat_o[4] wbs_dat_o[4] (0.047:0.047:0.047))
- (INTERCONNECT mprj.wbs_dat_o[5] wbs_dat_o[5] (0.034:0.034:0.034))
- (INTERCONNECT mprj.wbs_dat_o[6] wbs_dat_o[6] (0.042:0.042:0.042))
- (INTERCONNECT mprj.wbs_dat_o[7] wbs_dat_o[7] (0.059:0.059:0.059))
- (INTERCONNECT mprj.wbs_dat_o[8] wbs_dat_o[8] (0.037:0.037:0.037))
- (INTERCONNECT mprj.wbs_dat_o[9] wbs_dat_o[9] (0.061:0.061:0.061))
+ (INTERCONNECT io_in[0] wrapped_vga_clock.io_in[0] (14.821:14.821:14.821) (5.685:5.685:5.685))
+ (INTERCONNECT io_in[10] wrapped_vga_clock.io_in[10] (14.915:14.915:14.915) (5.723:5.723:5.723))
+ (INTERCONNECT io_in[11] wrapped_vga_clock.io_in[11] (16.031:16.031:16.031) (6.155:6.155:6.155))
+ (INTERCONNECT io_in[12] wrapped_vga_clock.io_in[12] (20.004:20.004:20.004) (7.698:7.698:7.698))
+ (INTERCONNECT io_in[13] wrapped_vga_clock.io_in[13] (16.860:16.860:16.860) (6.475:6.475:6.475))
+ (INTERCONNECT io_in[14] wrapped_vga_clock.io_in[14] (18.137:18.137:18.137) (6.970:6.970:6.970))
+ (INTERCONNECT io_in[15] wrapped_vga_clock.io_in[15] (23.191:23.191:23.191) (8.934:8.934:8.934))
+ (INTERCONNECT io_in[16] wrapped_vga_clock.io_in[16] (59.394:59.394:59.394) (22.862:22.862:22.862))
+ (INTERCONNECT io_in[17] wrapped_vga_clock.io_in[17] (32.558:32.558:32.558) (12.514:12.514:12.514))
+ (INTERCONNECT io_in[18] wrapped_vga_clock.io_in[18] (23.671:23.671:23.671) (9.108:9.108:9.108))
+ (INTERCONNECT io_in[19] wrapped_vga_clock.io_in[19] (18.497:18.497:18.497) (7.110:7.110:7.110))
+ (INTERCONNECT io_in[1] wrapped_vga_clock.io_in[1] (13.836:13.836:13.836) (5.304:5.304:5.304))
+ (INTERCONNECT io_in[20] wrapped_vga_clock.io_in[20] (12.347:12.347:12.347) (4.731:4.731:4.731))
+ (INTERCONNECT io_in[21] wrapped_vga_clock.io_in[21] (10.886:10.886:10.886) (4.166:4.166:4.166))
+ (INTERCONNECT io_in[22] wrapped_vga_clock.io_in[22] (11.542:11.542:11.542) (4.418:4.418:4.418))
+ (INTERCONNECT io_in[23] wrapped_vga_clock.io_in[23] (10.657:10.657:10.657) (4.079:4.079:4.079))
+ (INTERCONNECT io_in[24] wrapped_vga_clock.io_in[24] (29.363:29.363:29.363) (11.285:11.285:11.285))
+ (INTERCONNECT io_in[25] wrapped_vga_clock.io_in[25] (11.801:11.801:11.801) (4.519:4.519:4.519))
+ (INTERCONNECT io_in[26] wrapped_vga_clock.io_in[26] (9.542:9.542:9.542) (3.650:3.650:3.650))
+ (INTERCONNECT io_in[27] wrapped_vga_clock.io_in[27] (9.415:9.415:9.415) (3.601:3.601:3.601))
+ (INTERCONNECT io_in[28] wrapped_vga_clock.io_in[28] (23.689:23.689:23.689) (9.087:9.087:9.087))
+ (INTERCONNECT io_in[29] wrapped_vga_clock.io_in[29] (18.336:18.336:18.336) (7.027:7.027:7.027))
+ (INTERCONNECT io_in[2] wrapped_vga_clock.io_in[2] (11.970:11.970:11.970) (4.584:4.584:4.584))
+ (INTERCONNECT io_in[30] wrapped_vga_clock.io_in[30] (5.893:5.893:5.893) (2.251:2.251:2.251))
+ (INTERCONNECT io_in[31] wrapped_vga_clock.io_in[31] (12.531:12.531:12.531) (4.792:4.792:4.792))
+ (INTERCONNECT io_in[32] wrapped_vga_clock.io_in[32] (9.026:9.026:9.026) (3.449:3.449:3.449))
+ (INTERCONNECT io_in[33] wrapped_vga_clock.io_in[33] (3.037:3.037:3.037) (1.160:1.160:1.160))
+ (INTERCONNECT io_in[34] wrapped_vga_clock.io_in[34] (3.075:3.075:3.075) (1.175:1.175:1.175))
+ (INTERCONNECT io_in[35] wrapped_vga_clock.io_in[35] (4.375:4.375:4.375) (1.671:1.671:1.671))
+ (INTERCONNECT io_in[36] wrapped_vga_clock.io_in[36] (9.474:9.474:9.474) (3.621:3.621:3.621))
+ (INTERCONNECT io_in[37] wrapped_vga_clock.io_in[37] (7.111:7.111:7.111) (2.718:2.718:2.718))
+ (INTERCONNECT io_in[3] wrapped_vga_clock.io_in[3] (25.776:25.776:25.776) (9.907:9.907:9.907))
+ (INTERCONNECT io_in[4] wrapped_vga_clock.io_in[4] (10.097:10.097:10.097) (3.863:3.863:3.863))
+ (INTERCONNECT io_in[5] wrapped_vga_clock.io_in[5] (9.586:9.586:9.586) (3.670:3.670:3.670))
+ (INTERCONNECT io_in[6] wrapped_vga_clock.io_in[6] (15.075:15.075:15.075) (5.778:5.778:5.778))
+ (INTERCONNECT io_in[7] wrapped_vga_clock.io_in[7] (11.757:11.757:11.757) (4.501:4.501:4.501))
+ (INTERCONNECT io_in[8] wrapped_vga_clock.io_in[8] (14.274:14.274:14.274) (5.472:5.472:5.472))
+ (INTERCONNECT io_in[9] wrapped_vga_clock.io_in[9] (13.308:13.308:13.308) (5.102:5.102:5.102))
+ (INTERCONNECT wb_clk_i wrapped_vga_clock.wb_clk_i (7.879:7.879:7.879) (3.013:3.013:3.013))
+ (INTERCONNECT wb_rst_i wrapped_vga_clock.wb_rst_i (10.294:10.294:10.294) (3.937:3.937:3.937))
+ (INTERCONNECT wrapped_vga_clock.io_oeb[0] io_oeb[0] (0.124:0.124:0.124))
+ (INTERCONNECT wrapped_vga_clock.io_oeb[10] io_oeb[10] (0.119:0.119:0.119))
+ (INTERCONNECT wrapped_vga_clock.io_oeb[11] io_oeb[11] (0.166:0.166:0.166))
+ (INTERCONNECT wrapped_vga_clock.io_oeb[12] io_oeb[12] (0.193:0.193:0.193))
+ (INTERCONNECT wrapped_vga_clock.io_oeb[13] io_oeb[13] (0.174:0.174:0.174))
+ (INTERCONNECT wrapped_vga_clock.io_oeb[14] io_oeb[14] (0.213:0.213:0.213))
+ (INTERCONNECT wrapped_vga_clock.io_oeb[15] io_oeb[15] (0.260:0.260:0.260))
+ (INTERCONNECT wrapped_vga_clock.io_oeb[16] io_oeb[16] (0.148:0.148:0.148))
+ (INTERCONNECT wrapped_vga_clock.io_oeb[17] io_oeb[17] (0.140:0.140:0.140))
+ (INTERCONNECT wrapped_vga_clock.io_oeb[18] io_oeb[18] (0.126:0.126:0.126))
+ (INTERCONNECT wrapped_vga_clock.io_oeb[19] io_oeb[19] (0.099:0.099:0.099))
+ (INTERCONNECT wrapped_vga_clock.io_oeb[1] io_oeb[1] (0.118:0.118:0.118))
+ (INTERCONNECT wrapped_vga_clock.io_oeb[20] io_oeb[20] (0.084:0.084:0.084))
+ (INTERCONNECT wrapped_vga_clock.io_oeb[21] io_oeb[21] (0.058:0.058:0.058))
+ (INTERCONNECT wrapped_vga_clock.io_oeb[22] io_oeb[22] (0.099:0.099:0.099))
+ (INTERCONNECT wrapped_vga_clock.io_oeb[23] io_oeb[23] (0.106:0.106:0.106))
+ (INTERCONNECT wrapped_vga_clock.io_oeb[24] io_oeb[24] (0.106:0.106:0.106))
+ (INTERCONNECT wrapped_vga_clock.io_oeb[25] io_oeb[25] (0.077:0.077:0.077))
+ (INTERCONNECT wrapped_vga_clock.io_oeb[26] io_oeb[26] (0.116:0.116:0.116))
+ (INTERCONNECT wrapped_vga_clock.io_oeb[27] io_oeb[27] (0.060:0.060:0.060))
+ (INTERCONNECT wrapped_vga_clock.io_oeb[28] io_oeb[28] (0.069:0.069:0.069))
+ (INTERCONNECT wrapped_vga_clock.io_oeb[29] io_oeb[29] (0.089:0.089:0.089))
+ (INTERCONNECT wrapped_vga_clock.io_oeb[2] io_oeb[2] (0.104:0.104:0.104))
+ (INTERCONNECT wrapped_vga_clock.io_oeb[30] io_oeb[30] (0.025:0.025:0.025))
+ (INTERCONNECT wrapped_vga_clock.io_oeb[31] io_oeb[31] (0.047:0.047:0.047))
+ (INTERCONNECT wrapped_vga_clock.io_oeb[32] io_oeb[32] (0.027:0.027:0.027))
+ (INTERCONNECT wrapped_vga_clock.io_oeb[33] io_oeb[33] (0.018:0.018:0.018))
+ (INTERCONNECT wrapped_vga_clock.io_oeb[34] io_oeb[34] (0.042:0.042:0.042))
+ (INTERCONNECT wrapped_vga_clock.io_oeb[35] io_oeb[35] (0.027:0.027:0.027))
+ (INTERCONNECT wrapped_vga_clock.io_oeb[36] io_oeb[36] (0.040:0.040:0.040))
+ (INTERCONNECT wrapped_vga_clock.io_oeb[37] io_oeb[37] (0.050:0.050:0.050))
+ (INTERCONNECT wrapped_vga_clock.io_oeb[3] io_oeb[3] (0.101:0.101:0.101))
+ (INTERCONNECT wrapped_vga_clock.io_oeb[4] io_oeb[4] (0.190:0.190:0.190))
+ (INTERCONNECT wrapped_vga_clock.io_oeb[5] io_oeb[5] (0.165:0.165:0.165))
+ (INTERCONNECT wrapped_vga_clock.io_oeb[6] io_oeb[6] (0.115:0.115:0.115))
+ (INTERCONNECT wrapped_vga_clock.io_oeb[7] io_oeb[7] (0.214:0.214:0.214))
+ (INTERCONNECT wrapped_vga_clock.io_oeb[8] io_oeb[8] (0.124:0.124:0.124))
+ (INTERCONNECT wrapped_vga_clock.io_oeb[9] io_oeb[9] (0.115:0.115:0.115))
+ (INTERCONNECT wrapped_vga_clock.io_out[0] io_out[0] (0.111:0.111:0.111))
+ (INTERCONNECT wrapped_vga_clock.io_out[10] io_out[10] (0.175:0.175:0.175))
+ (INTERCONNECT wrapped_vga_clock.io_out[11] io_out[11] (0.530:0.530:0.530))
+ (INTERCONNECT wrapped_vga_clock.io_out[12] io_out[12] (0.157:0.157:0.157))
+ (INTERCONNECT wrapped_vga_clock.io_out[13] io_out[13] (0.187:0.187:0.187))
+ (INTERCONNECT wrapped_vga_clock.io_out[14] io_out[14] (0.217:0.217:0.217))
+ (INTERCONNECT wrapped_vga_clock.io_out[15] io_out[15] (0.169:0.169:0.169))
+ (INTERCONNECT wrapped_vga_clock.io_out[16] io_out[16] (0.173:0.173:0.173))
+ (INTERCONNECT wrapped_vga_clock.io_out[17] io_out[17] (0.161:0.161:0.161))
+ (INTERCONNECT wrapped_vga_clock.io_out[18] io_out[18] (0.136:0.136:0.136))
+ (INTERCONNECT wrapped_vga_clock.io_out[19] io_out[19] (0.219:0.219:0.219))
+ (INTERCONNECT wrapped_vga_clock.io_out[1] io_out[1] (0.118:0.118:0.118))
+ (INTERCONNECT wrapped_vga_clock.io_out[20] io_out[20] (0.104:0.104:0.104))
+ (INTERCONNECT wrapped_vga_clock.io_out[21] io_out[21] (0.115:0.115:0.115))
+ (INTERCONNECT wrapped_vga_clock.io_out[22] io_out[22] (0.063:0.063:0.063))
+ (INTERCONNECT wrapped_vga_clock.io_out[23] io_out[23] (0.085:0.085:0.085))
+ (INTERCONNECT wrapped_vga_clock.io_out[24] io_out[24] (0.100:0.100:0.100))
+ (INTERCONNECT wrapped_vga_clock.io_out[25] io_out[25] (0.081:0.081:0.081))
+ (INTERCONNECT wrapped_vga_clock.io_out[26] io_out[26] (0.077:0.077:0.077))
+ (INTERCONNECT wrapped_vga_clock.io_out[27] io_out[27] (0.065:0.065:0.065))
+ (INTERCONNECT wrapped_vga_clock.io_out[28] io_out[28] (0.051:0.051:0.051))
+ (INTERCONNECT wrapped_vga_clock.io_out[29] io_out[29] (0.041:0.041:0.041))
+ (INTERCONNECT wrapped_vga_clock.io_out[2] io_out[2] (0.093:0.093:0.093))
+ (INTERCONNECT wrapped_vga_clock.io_out[30] io_out[30] (0.047:0.047:0.047))
+ (INTERCONNECT wrapped_vga_clock.io_out[31] io_out[31] (0.062:0.062:0.062))
+ (INTERCONNECT wrapped_vga_clock.io_out[32] io_out[32] (0.014:0.014:0.014))
+ (INTERCONNECT wrapped_vga_clock.io_out[33] io_out[33] (0.013:0.013:0.013))
+ (INTERCONNECT wrapped_vga_clock.io_out[34] io_out[34] (0.017:0.017:0.017))
+ (INTERCONNECT wrapped_vga_clock.io_out[35] io_out[35] (0.024:0.024:0.024))
+ (INTERCONNECT wrapped_vga_clock.io_out[36] io_out[36] (0.031:0.031:0.031))
+ (INTERCONNECT wrapped_vga_clock.io_out[37] io_out[37] (0.059:0.059:0.059))
+ (INTERCONNECT wrapped_vga_clock.io_out[3] io_out[3] (0.078:0.078:0.078))
+ (INTERCONNECT wrapped_vga_clock.io_out[4] io_out[4] (0.155:0.155:0.155))
+ (INTERCONNECT wrapped_vga_clock.io_out[5] io_out[5] (0.109:0.109:0.109))
+ (INTERCONNECT wrapped_vga_clock.io_out[6] io_out[6] (0.093:0.093:0.093))
+ (INTERCONNECT wrapped_vga_clock.io_out[7] io_out[7] (0.102:0.102:0.102))
+ (INTERCONNECT wrapped_vga_clock.io_out[8] io_out[8] (0.133:0.133:0.133))
+ (INTERCONNECT wrapped_vga_clock.io_out[9] io_out[9] (0.142:0.142:0.142))
)
)
)
diff --git a/sdf/multicorner/nom/user_project_wrapper.tt.sdf b/sdf/multicorner/nom/user_project_wrapper.tt.sdf
index 8f37699..2c66f24 100644
--- a/sdf/multicorner/nom/user_project_wrapper.tt.sdf
+++ b/sdf/multicorner/nom/user_project_wrapper.tt.sdf
@@ -1,7 +1,7 @@
(DELAYFILE
(SDFVERSION "3.0")
(DESIGN "user_project_wrapper")
- (DATE "Mon Nov 21 16:20:23 2022")
+ (DATE "Wed Nov 23 09:34:43 2022")
(VENDOR "Parallax")
(PROGRAM "STA")
(VERSION "2.3.2")
@@ -12,421 +12,122 @@
(INSTANCE)
(DELAY
(ABSOLUTE
- (INTERCONNECT io_in[0] mprj.io_in[0] (3.522:3.522:3.522) (1.964:1.964:1.964))
- (INTERCONNECT io_in[10] mprj.io_in[10] (2.498:2.498:2.498) (1.388:1.388:1.388))
- (INTERCONNECT io_in[11] mprj.io_in[11] (2.450:2.450:2.450) (1.363:1.363:1.363))
- (INTERCONNECT io_in[12] mprj.io_in[12] (2.604:2.604:2.604) (1.449:1.449:1.449))
- (INTERCONNECT io_in[13] mprj.io_in[13] (2.936:2.936:2.936) (1.635:1.635:1.635))
- (INTERCONNECT io_in[14] mprj.io_in[14] (2.996:2.996:2.996) (1.669:1.669:1.669))
- (INTERCONNECT io_in[15] mprj.io_in[15] (3.191:3.191:3.191) (1.778:1.778:1.778))
- (INTERCONNECT io_in[16] mprj.io_in[16] (3.530:3.530:3.530) (1.966:1.966:1.966))
- (INTERCONNECT io_in[17] mprj.io_in[17] (2.542:2.542:2.542) (1.412:1.412:1.412))
- (INTERCONNECT io_in[18] mprj.io_in[18] (4.839:4.839:4.839) (2.681:2.681:2.681))
- (INTERCONNECT io_in[19] mprj.io_in[19] (4.281:4.281:4.281) (2.371:2.371:2.371))
- (INTERCONNECT io_in[1] mprj.io_in[1] (5.113:5.113:5.113) (2.844:2.844:2.844))
- (INTERCONNECT io_in[20] mprj.io_in[20] (1.559:1.559:1.559) (0.863:0.863:0.863))
- (INTERCONNECT io_in[21] mprj.io_in[21] (1.494:1.494:1.494) (0.828:0.828:0.828))
- (INTERCONNECT io_in[22] mprj.io_in[22] (2.181:2.181:2.181) (1.209:1.209:1.209))
- (INTERCONNECT io_in[23] mprj.io_in[23] (2.079:2.079:2.079) (1.153:1.153:1.153))
- (INTERCONNECT io_in[24] mprj.io_in[24] (2.875:2.875:2.875) (1.598:1.598:1.598))
- (INTERCONNECT io_in[25] mprj.io_in[25] (2.288:2.288:2.288) (1.270:1.270:1.270))
- (INTERCONNECT io_in[26] mprj.io_in[26] (1.940:1.940:1.940) (1.076:1.076:1.076))
- (INTERCONNECT io_in[27] mprj.io_in[27] (5.627:5.627:5.627) (3.109:3.109:3.109))
- (INTERCONNECT io_in[28] mprj.io_in[28] (1.717:1.717:1.717) (0.951:0.951:0.951))
- (INTERCONNECT io_in[29] mprj.io_in[29] (1.686:1.686:1.686) (0.933:0.933:0.933))
- (INTERCONNECT io_in[2] mprj.io_in[2] (7.009:7.009:7.009) (3.880:3.880:3.880))
- (INTERCONNECT io_in[30] mprj.io_in[30] (1.271:1.271:1.271) (0.703:0.703:0.703))
- (INTERCONNECT io_in[31] mprj.io_in[31] (4.178:4.178:4.178) (2.301:2.301:2.301))
- (INTERCONNECT io_in[32] mprj.io_in[32] (6.366:6.366:6.366) (3.508:3.508:3.508))
- (INTERCONNECT io_in[33] mprj.io_in[33] (3.621:3.621:3.621) (2.002:2.002:2.002))
- (INTERCONNECT io_in[34] mprj.io_in[34] (6.625:6.625:6.625) (3.657:3.657:3.657))
- (INTERCONNECT io_in[35] mprj.io_in[35] (2.058:2.058:2.058) (1.141:1.141:1.141))
- (INTERCONNECT io_in[36] mprj.io_in[36] (3.127:3.127:3.127) (1.732:1.732:1.732))
- (INTERCONNECT io_in[37] mprj.io_in[37] (2.524:2.524:2.524) (1.402:1.402:1.402))
- (INTERCONNECT io_in[3] mprj.io_in[3] (4.976:4.976:4.976) (2.760:2.760:2.760))
- (INTERCONNECT io_in[4] mprj.io_in[4] (5.053:5.053:5.053) (2.809:2.809:2.809))
- (INTERCONNECT io_in[5] mprj.io_in[5] (6.232:6.232:6.232) (3.445:3.445:3.445))
- (INTERCONNECT io_in[6] mprj.io_in[6] (5.258:5.258:5.258) (2.911:2.911:2.911))
- (INTERCONNECT io_in[7] mprj.io_in[7] (6.411:6.411:6.411) (3.533:3.533:3.533))
- (INTERCONNECT io_in[8] mprj.io_in[8] (1.973:1.973:1.973) (1.097:1.097:1.097))
- (INTERCONNECT io_in[9] mprj.io_in[9] (4.089:4.089:4.089) (2.268:2.268:2.268))
- (INTERCONNECT la_data_in[0] mprj.la_data_in[0] (3.415:3.415:3.415) (1.882:1.882:1.882))
- (INTERCONNECT la_data_in[10] mprj.la_data_in[10] (1.801:1.801:1.801) (0.994:0.994:0.994))
- (INTERCONNECT la_data_in[11] mprj.la_data_in[11] (4.467:4.467:4.467) (2.467:2.467:2.467))
- (INTERCONNECT la_data_in[12] mprj.la_data_in[12] (1.851:1.851:1.851) (1.022:1.022:1.022))
- (INTERCONNECT la_data_in[13] mprj.la_data_in[13] (2.098:2.098:2.098) (1.159:1.159:1.159))
- (INTERCONNECT la_data_in[14] mprj.la_data_in[14] (6.118:6.118:6.118) (3.377:3.377:3.377))
- (INTERCONNECT la_data_in[15] mprj.la_data_in[15] (1.679:1.679:1.679) (0.928:0.928:0.928))
- (INTERCONNECT la_data_in[16] mprj.la_data_in[16] (4.353:4.353:4.353) (2.404:2.404:2.404))
- (INTERCONNECT la_data_in[17] mprj.la_data_in[17] (4.731:4.731:4.731) (2.612:2.612:2.612))
- (INTERCONNECT la_data_in[18] mprj.la_data_in[18] (4.448:4.448:4.448) (2.456:2.456:2.456))
- (INTERCONNECT la_data_in[19] mprj.la_data_in[19] (2.992:2.992:2.992) (1.652:1.652:1.652))
- (INTERCONNECT la_data_in[1] mprj.la_data_in[1] (3.345:3.345:3.345) (1.845:1.845:1.845))
- (INTERCONNECT la_data_in[20] mprj.la_data_in[20] (2.570:2.570:2.570) (1.419:1.419:1.419))
- (INTERCONNECT la_data_in[21] mprj.la_data_in[21] (4.161:4.161:4.161) (2.298:2.298:2.298))
- (INTERCONNECT la_data_in[22] mprj.la_data_in[22] (3.221:3.221:3.221) (1.779:1.779:1.779))
- (INTERCONNECT la_data_in[23] mprj.la_data_in[23] (3.602:3.602:3.602) (1.985:1.985:1.985))
- (INTERCONNECT la_data_in[24] mprj.la_data_in[24] (5.845:5.845:5.845) (3.228:3.228:3.228))
- (INTERCONNECT la_data_in[25] mprj.la_data_in[25] (2.723:2.723:2.723) (1.504:1.504:1.504))
- (INTERCONNECT la_data_in[26] mprj.la_data_in[26] (2.904:2.904:2.904) (1.604:1.604:1.604))
- (INTERCONNECT la_data_in[27] mprj.la_data_in[27] (4.486:4.486:4.486) (2.479:2.479:2.479))
- (INTERCONNECT la_data_in[28] mprj.la_data_in[28] (3.151:3.151:3.151) (1.740:1.740:1.740))
- (INTERCONNECT la_data_in[29] mprj.la_data_in[29] (3.310:3.310:3.310) (1.827:1.827:1.827))
- (INTERCONNECT la_data_in[2] mprj.la_data_in[2] (2.734:2.734:2.734) (1.505:1.505:1.505))
- (INTERCONNECT la_data_in[30] mprj.la_data_in[30] (4.827:4.827:4.827) (2.667:2.667:2.667))
- (INTERCONNECT la_data_in[31] mprj.la_data_in[31] (4.735:4.735:4.735) (2.614:2.614:2.614))
- (INTERCONNECT la_data_in[32] mprj.la_data_in[32] (4.909:4.909:4.909) (2.710:2.710:2.710))
- (INTERCONNECT la_data_in[33] mprj.la_data_in[33] (3.683:3.683:3.683) (2.036:2.036:2.036))
- (INTERCONNECT la_data_in[34] mprj.la_data_in[34] (3.850:3.850:3.850) (2.128:2.128:2.128))
- (INTERCONNECT la_data_in[35] mprj.la_data_in[35] (4.399:4.399:4.399) (2.432:2.432:2.432))
- (INTERCONNECT la_data_in[36] mprj.la_data_in[36] (3.938:3.938:3.938) (2.177:2.177:2.177))
- (INTERCONNECT la_data_in[37] mprj.la_data_in[37] (3.864:3.864:3.864) (2.136:2.136:2.136))
- (INTERCONNECT la_data_in[38] mprj.la_data_in[38] (5.105:5.105:5.105) (2.819:2.819:2.819))
- (INTERCONNECT la_data_in[39] mprj.la_data_in[39] (4.326:4.326:4.326) (2.392:2.392:2.392))
- (INTERCONNECT la_data_in[3] mprj.la_data_in[3] (1.170:1.170:1.170) (0.646:0.646:0.646))
- (INTERCONNECT la_data_in[40] mprj.la_data_in[40] (6.186:6.186:6.186) (3.414:3.414:3.414))
- (INTERCONNECT la_data_in[41] mprj.la_data_in[41] (3.956:3.956:3.956) (2.187:2.187:2.187))
- (INTERCONNECT la_data_in[42] mprj.la_data_in[42] (5.018:5.018:5.018) (2.772:2.772:2.772))
- (INTERCONNECT la_data_in[43] mprj.la_data_in[43] (6.910:6.910:6.910) (3.813:3.813:3.813))
- (INTERCONNECT la_data_in[44] mprj.la_data_in[44] (3.544:3.544:3.544) (1.961:1.961:1.961))
- (INTERCONNECT la_data_in[45] mprj.la_data_in[45] (6.138:6.138:6.138) (3.389:3.389:3.389))
- (INTERCONNECT la_data_in[46] mprj.la_data_in[46] (5.284:5.284:5.284) (2.922:2.922:2.922))
- (INTERCONNECT la_data_in[47] mprj.la_data_in[47] (7.020:7.020:7.020) (3.874:3.874:3.874))
- (INTERCONNECT la_data_in[48] mprj.la_data_in[48] (6.404:6.404:6.404) (3.535:3.535:3.535))
- (INTERCONNECT la_data_in[49] mprj.la_data_in[49] (5.757:5.757:5.757) (3.184:3.184:3.184))
- (INTERCONNECT la_data_in[4] mprj.la_data_in[4] (3.333:3.333:3.333) (1.838:1.838:1.838))
- (INTERCONNECT la_data_in[50] mprj.la_data_in[50] (7.864:7.864:7.864) (4.337:4.337:4.337))
- (INTERCONNECT la_data_in[51] mprj.la_data_in[51] (8.004:8.004:8.004) (4.414:4.414:4.414))
- (INTERCONNECT la_data_in[52] mprj.la_data_in[52] (7.654:7.654:7.654) (4.222:4.222:4.222))
- (INTERCONNECT la_data_in[53] mprj.la_data_in[53] (7.175:7.175:7.175) (3.959:3.959:3.959))
- (INTERCONNECT la_data_in[54] mprj.la_data_in[54] (3.638:3.638:3.638) (2.014:2.014:2.014))
- (INTERCONNECT la_data_in[55] mprj.la_data_in[55] (3.663:3.663:3.663) (2.029:2.029:2.029))
- (INTERCONNECT la_data_in[56] mprj.la_data_in[56] (7.451:7.451:7.451) (4.105:4.105:4.105))
- (INTERCONNECT la_data_in[57] mprj.la_data_in[57] (5.056:5.056:5.056) (2.796:2.796:2.796))
- (INTERCONNECT la_data_in[58] mprj.la_data_in[58] (4.399:4.399:4.399) (2.434:2.434:2.434))
- (INTERCONNECT la_data_in[59] mprj.la_data_in[59] (4.653:4.653:4.653) (2.575:2.575:2.575))
- (INTERCONNECT la_data_in[5] mprj.la_data_in[5] (3.324:3.324:3.324) (1.834:1.834:1.834))
- (INTERCONNECT la_data_in[60] mprj.la_data_in[60] (5.118:5.118:5.118) (2.831:2.831:2.831))
- (INTERCONNECT la_data_in[61] mprj.la_data_in[61] (6.112:6.112:6.112) (3.381:3.381:3.381))
- (INTERCONNECT la_data_in[62] mprj.la_data_in[62] (5.200:5.200:5.200) (2.876:2.876:2.876))
- (INTERCONNECT la_data_in[63] mprj.la_data_in[63] (4.443:4.443:4.443) (2.460:2.460:2.460))
- (INTERCONNECT la_data_in[6] mprj.la_data_in[6] (2.899:2.899:2.899) (1.601:1.601:1.601))
- (INTERCONNECT la_data_in[7] mprj.la_data_in[7] (5.217:5.217:5.217) (2.877:2.877:2.877))
- (INTERCONNECT la_data_in[8] mprj.la_data_in[8] (5.641:5.641:5.641) (3.112:3.112:3.112))
- (INTERCONNECT la_data_in[9] mprj.la_data_in[9] (1.443:1.443:1.443) (0.797:0.797:0.797))
- (INTERCONNECT la_oenb[0] mprj.la_oenb[0] (4.261:4.261:4.261) (2.347:2.347:2.347))
- (INTERCONNECT la_oenb[10] mprj.la_oenb[10] (3.551:3.551:3.551) (1.960:1.960:1.960))
- (INTERCONNECT la_oenb[11] mprj.la_oenb[11] (3.517:3.517:3.517) (1.941:1.941:1.941))
- (INTERCONNECT la_oenb[12] mprj.la_oenb[12] (2.461:2.461:2.461) (1.360:1.360:1.360))
- (INTERCONNECT la_oenb[13] mprj.la_oenb[13] (3.861:3.861:3.861) (2.131:2.131:2.131))
- (INTERCONNECT la_oenb[14] mprj.la_oenb[14] (2.113:2.113:2.113) (1.168:1.168:1.168))
- (INTERCONNECT la_oenb[15] mprj.la_oenb[15] (1.943:1.943:1.943) (1.074:1.074:1.074))
- (INTERCONNECT la_oenb[16] mprj.la_oenb[16] (1.268:1.268:1.268) (0.701:0.701:0.701))
- (INTERCONNECT la_oenb[17] mprj.la_oenb[17] (5.331:5.331:5.331) (2.945:2.945:2.945))
- (INTERCONNECT la_oenb[18] mprj.la_oenb[18] (2.540:2.540:2.540) (1.403:1.403:1.403))
- (INTERCONNECT la_oenb[19] mprj.la_oenb[19] (2.602:2.602:2.602) (1.437:1.437:1.437))
- (INTERCONNECT la_oenb[1] mprj.la_oenb[1] (2.673:2.673:2.673) (1.472:1.472:1.472))
- (INTERCONNECT la_oenb[20] mprj.la_oenb[20] (4.646:4.646:4.646) (2.567:2.567:2.567))
- (INTERCONNECT la_oenb[21] mprj.la_oenb[21] (2.131:2.131:2.131) (1.177:1.177:1.177))
- (INTERCONNECT la_oenb[22] mprj.la_oenb[22] (1.428:1.428:1.428) (0.789:0.789:0.789))
- (INTERCONNECT la_oenb[23] mprj.la_oenb[23] (4.791:4.791:4.791) (2.647:2.647:2.647))
- (INTERCONNECT la_oenb[24] mprj.la_oenb[24] (3.953:3.953:3.953) (2.183:2.183:2.183))
- (INTERCONNECT la_oenb[25] mprj.la_oenb[25] (6.508:6.508:6.508) (3.594:3.594:3.594))
- (INTERCONNECT la_oenb[26] mprj.la_oenb[26] (5.703:5.703:5.703) (3.150:3.150:3.150))
- (INTERCONNECT la_oenb[27] mprj.la_oenb[27] (3.663:3.663:3.663) (2.023:2.023:2.023))
- (INTERCONNECT la_oenb[28] mprj.la_oenb[28] (3.658:3.658:3.658) (2.020:2.020:2.020))
- (INTERCONNECT la_oenb[29] mprj.la_oenb[29] (4.609:4.609:4.609) (2.547:2.547:2.547))
- (INTERCONNECT la_oenb[2] mprj.la_oenb[2] (1.587:1.587:1.587) (0.876:0.876:0.876))
- (INTERCONNECT la_oenb[30] mprj.la_oenb[30] (5.252:5.252:5.252) (2.898:2.898:2.898))
- (INTERCONNECT la_oenb[31] mprj.la_oenb[31] (1.695:1.695:1.695) (0.938:0.938:0.938))
- (INTERCONNECT la_oenb[32] mprj.la_oenb[32] (5.393:5.393:5.393) (2.980:2.980:2.980))
- (INTERCONNECT la_oenb[33] mprj.la_oenb[33] (5.465:5.465:5.465) (3.016:3.016:3.016))
- (INTERCONNECT la_oenb[34] mprj.la_oenb[34] (3.961:3.961:3.961) (2.190:2.190:2.190))
- (INTERCONNECT la_oenb[35] mprj.la_oenb[35] (5.352:5.352:5.352) (2.949:2.949:2.949))
- (INTERCONNECT la_oenb[36] mprj.la_oenb[36] (5.455:5.455:5.455) (3.014:3.014:3.014))
- (INTERCONNECT la_oenb[37] mprj.la_oenb[37] (2.721:2.721:2.721) (1.502:1.502:1.502))
- (INTERCONNECT la_oenb[38] mprj.la_oenb[38] (7.995:7.995:7.995) (4.414:4.414:4.414))
- (INTERCONNECT la_oenb[39] mprj.la_oenb[39] (7.123:7.123:7.123) (3.929:3.929:3.929))
- (INTERCONNECT la_oenb[3] mprj.la_oenb[3] (1.475:1.475:1.475) (0.815:0.815:0.815))
- (INTERCONNECT la_oenb[40] mprj.la_oenb[40] (1.888:1.888:1.888) (1.046:1.046:1.046))
- (INTERCONNECT la_oenb[41] mprj.la_oenb[41] (3.556:3.556:3.556) (1.966:1.966:1.966))
- (INTERCONNECT la_oenb[42] mprj.la_oenb[42] (2.585:2.585:2.585) (1.429:1.429:1.429))
- (INTERCONNECT la_oenb[43] mprj.la_oenb[43] (1.829:1.829:1.829) (1.013:1.013:1.013))
- (INTERCONNECT la_oenb[44] mprj.la_oenb[44] (6.541:6.541:6.541) (3.609:3.609:3.609))
- (INTERCONNECT la_oenb[45] mprj.la_oenb[45] (4.854:4.854:4.854) (2.686:2.686:2.686))
- (INTERCONNECT la_oenb[46] mprj.la_oenb[46] (6.861:6.861:6.861) (3.785:3.785:3.785))
- (INTERCONNECT la_oenb[47] mprj.la_oenb[47] (5.004:5.004:5.004) (2.765:2.765:2.765))
- (INTERCONNECT la_oenb[48] mprj.la_oenb[48] (2.594:2.594:2.594) (1.435:1.435:1.435))
- (INTERCONNECT la_oenb[49] mprj.la_oenb[49] (3.974:3.974:3.974) (2.196:2.196:2.196))
- (INTERCONNECT la_oenb[4] mprj.la_oenb[4] (5.116:5.116:5.116) (2.820:2.820:2.820))
- (INTERCONNECT la_oenb[50] mprj.la_oenb[50] (7.357:7.357:7.357) (4.058:4.058:4.058))
- (INTERCONNECT la_oenb[51] mprj.la_oenb[51] (7.814:7.814:7.814) (4.308:4.308:4.308))
- (INTERCONNECT la_oenb[52] mprj.la_oenb[52] (4.841:4.841:4.841) (2.675:2.675:2.675))
- (INTERCONNECT la_oenb[53] mprj.la_oenb[53] (5.512:5.512:5.512) (3.045:3.045:3.045))
- (INTERCONNECT la_oenb[54] mprj.la_oenb[54] (10.004:10.004:10.004) (5.522:5.522:5.522))
- (INTERCONNECT la_oenb[55] mprj.la_oenb[55] (8.296:8.296:8.296) (4.567:4.567:4.567))
- (INTERCONNECT la_oenb[56] mprj.la_oenb[56] (6.400:6.400:6.400) (3.534:3.534:3.534))
- (INTERCONNECT la_oenb[57] mprj.la_oenb[57] (6.471:6.471:6.471) (3.571:3.571:3.571))
- (INTERCONNECT la_oenb[58] mprj.la_oenb[58] (8.783:8.783:8.783) (4.837:4.837:4.837))
- (INTERCONNECT la_oenb[59] mprj.la_oenb[59] (3.912:3.912:3.912) (2.167:2.167:2.167))
- (INTERCONNECT la_oenb[5] mprj.la_oenb[5] (3.923:3.923:3.923) (2.166:2.166:2.166))
- (INTERCONNECT la_oenb[60] mprj.la_oenb[60] (2.011:2.011:2.011) (1.115:1.115:1.115))
- (INTERCONNECT la_oenb[61] mprj.la_oenb[61] (5.338:5.338:5.338) (2.955:2.955:2.955))
- (INTERCONNECT la_oenb[62] mprj.la_oenb[62] (8.717:8.717:8.717) (4.800:4.800:4.800))
- (INTERCONNECT la_oenb[63] mprj.la_oenb[63] (2.274:2.274:2.274) (1.260:1.260:1.260))
- (INTERCONNECT la_oenb[6] mprj.la_oenb[6] (4.483:4.483:4.483) (2.476:2.476:2.476))
- (INTERCONNECT la_oenb[7] mprj.la_oenb[7] (2.119:2.119:2.119) (1.171:1.171:1.171))
- (INTERCONNECT la_oenb[8] mprj.la_oenb[8] (3.528:3.528:3.528) (1.948:1.948:1.948))
- (INTERCONNECT la_oenb[9] mprj.la_oenb[9] (4.341:4.341:4.341) (2.397:2.397:2.397))
- (INTERCONNECT wb_clk_i mprj.wb_clk_i (1.732:1.732:1.732) (0.958:0.958:0.958))
- (INTERCONNECT wb_rst_i mprj.wb_rst_i (3.406:3.406:3.406) (1.880:1.880:1.880))
- (INTERCONNECT wbs_adr_i[0] mprj.wbs_adr_i[0] (2.336:2.336:2.336) (1.290:1.290:1.290))
- (INTERCONNECT wbs_adr_i[10] mprj.wbs_adr_i[10] (1.260:1.260:1.260) (0.695:0.695:0.695))
- (INTERCONNECT wbs_adr_i[11] mprj.wbs_adr_i[11] (2.027:2.027:2.027) (1.119:1.119:1.119))
- (INTERCONNECT wbs_adr_i[12] mprj.wbs_adr_i[12] (1.958:1.958:1.958) (1.081:1.081:1.081))
- (INTERCONNECT wbs_adr_i[13] mprj.wbs_adr_i[13] (1.769:1.769:1.769) (0.977:0.977:0.977))
- (INTERCONNECT wbs_adr_i[14] mprj.wbs_adr_i[14] (1.793:1.793:1.793) (0.990:0.990:0.990))
- (INTERCONNECT wbs_adr_i[15] mprj.wbs_adr_i[15] (1.747:1.747:1.747) (0.964:0.964:0.964))
- (INTERCONNECT wbs_adr_i[16] mprj.wbs_adr_i[16] (3.247:3.247:3.247) (1.788:1.788:1.788))
- (INTERCONNECT wbs_adr_i[17] mprj.wbs_adr_i[17] (3.020:3.020:3.020) (1.663:1.663:1.663))
- (INTERCONNECT wbs_adr_i[18] mprj.wbs_adr_i[18] (2.607:2.607:2.607) (1.437:1.437:1.437))
- (INTERCONNECT wbs_adr_i[19] mprj.wbs_adr_i[19] (1.151:1.151:1.151) (0.635:0.635:0.635))
- (INTERCONNECT wbs_adr_i[1] mprj.wbs_adr_i[1] (1.767:1.767:1.767) (0.976:0.976:0.976))
- (INTERCONNECT wbs_adr_i[20] mprj.wbs_adr_i[20] (2.704:2.704:2.704) (1.489:1.489:1.489))
- (INTERCONNECT wbs_adr_i[21] mprj.wbs_adr_i[21] (1.384:1.384:1.384) (0.762:0.762:0.762))
- (INTERCONNECT wbs_adr_i[22] mprj.wbs_adr_i[22] (1.226:1.226:1.226) (0.675:0.675:0.675))
- (INTERCONNECT wbs_adr_i[23] mprj.wbs_adr_i[23] (1.340:1.340:1.340) (0.738:0.738:0.738))
- (INTERCONNECT wbs_adr_i[24] mprj.wbs_adr_i[24] (2.734:2.734:2.734) (1.504:1.504:1.504))
- (INTERCONNECT wbs_adr_i[25] mprj.wbs_adr_i[25] (0.840:0.840:0.840) (0.463:0.463:0.463))
- (INTERCONNECT wbs_adr_i[26] mprj.wbs_adr_i[26] (0.930:0.930:0.930) (0.513:0.513:0.513))
- (INTERCONNECT wbs_adr_i[27] mprj.wbs_adr_i[27] (1.070:1.070:1.070) (0.590:0.590:0.590))
- (INTERCONNECT wbs_adr_i[28] mprj.wbs_adr_i[28] (1.522:1.522:1.522) (0.840:0.840:0.840))
- (INTERCONNECT wbs_adr_i[29] mprj.wbs_adr_i[29] (3.800:3.800:3.800) (2.094:2.094:2.094))
- (INTERCONNECT wbs_adr_i[2] mprj.wbs_adr_i[2] (2.721:2.721:2.721) (1.501:1.501:1.501))
- (INTERCONNECT wbs_adr_i[30] mprj.wbs_adr_i[30] (2.806:2.806:2.806) (1.549:1.549:1.549))
- (INTERCONNECT wbs_adr_i[31] mprj.wbs_adr_i[31] (2.082:2.082:2.082) (1.151:1.151:1.151))
- (INTERCONNECT wbs_adr_i[3] mprj.wbs_adr_i[3] (3.360:3.360:3.360) (1.855:1.855:1.855))
- (INTERCONNECT wbs_adr_i[4] mprj.wbs_adr_i[4] (2.586:2.586:2.586) (1.427:1.427:1.427))
- (INTERCONNECT wbs_adr_i[5] mprj.wbs_adr_i[5] (2.031:2.031:2.031) (1.122:1.122:1.122))
- (INTERCONNECT wbs_adr_i[6] mprj.wbs_adr_i[6] (2.897:2.897:2.897) (1.598:1.598:1.598))
- (INTERCONNECT wbs_adr_i[7] mprj.wbs_adr_i[7] (2.724:2.724:2.724) (1.502:1.502:1.502))
- (INTERCONNECT wbs_adr_i[8] mprj.wbs_adr_i[8] (2.434:2.434:2.434) (1.343:1.343:1.343))
- (INTERCONNECT wbs_adr_i[9] mprj.wbs_adr_i[9] (2.086:2.086:2.086) (1.152:1.152:1.152))
- (INTERCONNECT wbs_cyc_i mprj.wbs_cyc_i (2.537:2.537:2.537) (1.401:1.401:1.401))
- (INTERCONNECT wbs_dat_i[0] mprj.wbs_dat_i[0] (3.631:3.631:3.631) (2.004:2.004:2.004))
- (INTERCONNECT wbs_dat_i[10] mprj.wbs_dat_i[10] (1.968:1.968:1.968) (1.086:1.086:1.086))
- (INTERCONNECT wbs_dat_i[11] mprj.wbs_dat_i[11] (2.175:2.175:2.175) (1.200:1.200:1.200))
- (INTERCONNECT wbs_dat_i[12] mprj.wbs_dat_i[12] (1.945:1.945:1.945) (1.073:1.073:1.073))
- (INTERCONNECT wbs_dat_i[13] mprj.wbs_dat_i[13] (1.557:1.557:1.557) (0.859:0.859:0.859))
- (INTERCONNECT wbs_dat_i[14] mprj.wbs_dat_i[14] (1.595:1.595:1.595) (0.881:0.881:0.881))
- (INTERCONNECT wbs_dat_i[15] mprj.wbs_dat_i[15] (2.201:2.201:2.201) (1.216:1.216:1.216))
- (INTERCONNECT wbs_dat_i[16] mprj.wbs_dat_i[16] (1.302:1.302:1.302) (0.718:0.718:0.718))
- (INTERCONNECT wbs_dat_i[17] mprj.wbs_dat_i[17] (2.500:2.500:2.500) (1.378:1.378:1.378))
- (INTERCONNECT wbs_dat_i[18] mprj.wbs_dat_i[18] (1.293:1.293:1.293) (0.714:0.714:0.714))
- (INTERCONNECT wbs_dat_i[19] mprj.wbs_dat_i[19] (1.074:1.074:1.074) (0.593:0.593:0.593))
- (INTERCONNECT wbs_dat_i[1] mprj.wbs_dat_i[1] (2.241:2.241:2.241) (1.238:1.238:1.238))
- (INTERCONNECT wbs_dat_i[20] mprj.wbs_dat_i[20] (1.556:1.556:1.556) (0.858:0.858:0.858))
- (INTERCONNECT wbs_dat_i[21] mprj.wbs_dat_i[21] (1.344:1.344:1.344) (0.741:0.741:0.741))
- (INTERCONNECT wbs_dat_i[22] mprj.wbs_dat_i[22] (1.290:1.290:1.290) (0.710:0.710:0.710))
- (INTERCONNECT wbs_dat_i[23] mprj.wbs_dat_i[23] (1.225:1.225:1.225) (0.675:0.675:0.675))
- (INTERCONNECT wbs_dat_i[24] mprj.wbs_dat_i[24] (0.836:0.836:0.836) (0.461:0.461:0.461))
- (INTERCONNECT wbs_dat_i[25] mprj.wbs_dat_i[25] (2.847:2.847:2.847) (1.567:1.567:1.567))
- (INTERCONNECT wbs_dat_i[26] mprj.wbs_dat_i[26] (1.402:1.402:1.402) (0.772:0.772:0.772))
- (INTERCONNECT wbs_dat_i[27] mprj.wbs_dat_i[27] (1.665:1.665:1.665) (0.919:0.919:0.919))
- (INTERCONNECT wbs_dat_i[28] mprj.wbs_dat_i[28] (1.505:1.505:1.505) (0.831:0.831:0.831))
- (INTERCONNECT wbs_dat_i[29] mprj.wbs_dat_i[29] (1.542:1.542:1.542) (0.851:0.851:0.851))
- (INTERCONNECT wbs_dat_i[2] mprj.wbs_dat_i[2] (1.126:1.126:1.126) (0.622:0.622:0.622))
- (INTERCONNECT wbs_dat_i[30] mprj.wbs_dat_i[30] (2.828:2.828:2.828) (1.557:1.557:1.557))
- (INTERCONNECT wbs_dat_i[31] mprj.wbs_dat_i[31] (2.725:2.725:2.725) (1.502:1.502:1.502))
- (INTERCONNECT wbs_dat_i[3] mprj.wbs_dat_i[3] (3.188:3.188:3.188) (1.759:1.759:1.759))
- (INTERCONNECT wbs_dat_i[4] mprj.wbs_dat_i[4] (2.926:2.926:2.926) (1.614:1.614:1.614))
- (INTERCONNECT wbs_dat_i[5] mprj.wbs_dat_i[5] (2.664:2.664:2.664) (1.470:1.470:1.470))
- (INTERCONNECT wbs_dat_i[6] mprj.wbs_dat_i[6] (2.037:2.037:2.037) (1.125:1.125:1.125))
- (INTERCONNECT wbs_dat_i[7] mprj.wbs_dat_i[7] (2.524:2.524:2.524) (1.392:1.392:1.392))
- (INTERCONNECT wbs_dat_i[8] mprj.wbs_dat_i[8] (1.785:1.785:1.785) (0.986:0.986:0.986))
- (INTERCONNECT wbs_dat_i[9] mprj.wbs_dat_i[9] (1.780:1.780:1.780) (0.983:0.983:0.983))
- (INTERCONNECT wbs_sel_i[0] mprj.wbs_sel_i[0] (1.277:1.277:1.277) (0.706:0.706:0.706))
- (INTERCONNECT wbs_sel_i[1] mprj.wbs_sel_i[1] (2.470:2.470:2.470) (1.364:1.364:1.364))
- (INTERCONNECT wbs_sel_i[2] mprj.wbs_sel_i[2] (1.919:1.919:1.919) (1.061:1.061:1.061))
- (INTERCONNECT wbs_sel_i[3] mprj.wbs_sel_i[3] (2.956:2.956:2.956) (1.631:1.631:1.631))
- (INTERCONNECT wbs_stb_i mprj.wbs_stb_i (2.056:2.056:2.056) (1.136:1.136:1.136))
- (INTERCONNECT wbs_we_i mprj.wbs_we_i (2.122:2.122:2.122) (1.173:1.173:1.173))
- (INTERCONNECT mprj.io_oeb[0] io_oeb[0] (0.399:0.399:0.399))
- (INTERCONNECT mprj.io_oeb[10] io_oeb[10] (0.104:0.104:0.104))
- (INTERCONNECT mprj.io_oeb[11] io_oeb[11] (0.114:0.114:0.114))
- (INTERCONNECT mprj.io_oeb[12] io_oeb[12] (0.135:0.135:0.135))
- (INTERCONNECT mprj.io_oeb[13] io_oeb[13] (0.134:0.134:0.134))
- (INTERCONNECT mprj.io_oeb[14] io_oeb[14] (0.147:0.147:0.147))
- (INTERCONNECT mprj.io_oeb[15] io_oeb[15] (0.288:0.288:0.288))
- (INTERCONNECT mprj.io_oeb[16] io_oeb[16] (0.232:0.232:0.232))
- (INTERCONNECT mprj.io_oeb[17] io_oeb[17] (0.092:0.092:0.092))
- (INTERCONNECT mprj.io_oeb[18] io_oeb[18] (0.074:0.074:0.074))
- (INTERCONNECT mprj.io_oeb[19] io_oeb[19] (0.060:0.060:0.060))
- (INTERCONNECT mprj.io_oeb[1] io_oeb[1] (0.266:0.266:0.266))
- (INTERCONNECT mprj.io_oeb[20] io_oeb[20] (0.044:0.044:0.044))
- (INTERCONNECT mprj.io_oeb[21] io_oeb[21] (0.067:0.067:0.067))
- (INTERCONNECT mprj.io_oeb[22] io_oeb[22] (0.076:0.076:0.076))
- (INTERCONNECT mprj.io_oeb[23] io_oeb[23] (0.094:0.094:0.094))
- (INTERCONNECT mprj.io_oeb[24] io_oeb[24] (0.085:0.085:0.085))
- (INTERCONNECT mprj.io_oeb[25] io_oeb[25] (0.076:0.076:0.076))
- (INTERCONNECT mprj.io_oeb[26] io_oeb[26] (0.284:0.284:0.284))
- (INTERCONNECT mprj.io_oeb[27] io_oeb[27] (0.242:0.242:0.242))
- (INTERCONNECT mprj.io_oeb[28] io_oeb[28] (0.051:0.051:0.051))
- (INTERCONNECT mprj.io_oeb[29] io_oeb[29] (0.043:0.043:0.043))
- (INTERCONNECT mprj.io_oeb[2] io_oeb[2] (0.306:0.306:0.306))
- (INTERCONNECT mprj.io_oeb[30] io_oeb[30] (0.148:0.148:0.148))
- (INTERCONNECT mprj.io_oeb[31] io_oeb[31] (0.055:0.055:0.055))
- (INTERCONNECT mprj.io_oeb[32] io_oeb[32] (0.176:0.176:0.176))
- (INTERCONNECT mprj.io_oeb[33] io_oeb[33] (0.183:0.183:0.183))
- (INTERCONNECT mprj.io_oeb[34] io_oeb[34] (0.161:0.161:0.161))
- (INTERCONNECT mprj.io_oeb[35] io_oeb[35] (0.147:0.147:0.147))
- (INTERCONNECT mprj.io_oeb[36] io_oeb[36] (0.234:0.234:0.234))
- (INTERCONNECT mprj.io_oeb[37] io_oeb[37] (0.246:0.246:0.246))
- (INTERCONNECT mprj.io_oeb[3] io_oeb[3] (0.255:0.255:0.255))
- (INTERCONNECT mprj.io_oeb[4] io_oeb[4] (0.161:0.161:0.161))
- (INTERCONNECT mprj.io_oeb[5] io_oeb[5] (0.116:0.116:0.116))
- (INTERCONNECT mprj.io_oeb[6] io_oeb[6] (0.151:0.151:0.151))
- (INTERCONNECT mprj.io_oeb[7] io_oeb[7] (0.177:0.177:0.177))
- (INTERCONNECT mprj.io_oeb[8] io_oeb[8] (0.084:0.084:0.084))
- (INTERCONNECT mprj.io_oeb[9] io_oeb[9] (0.094:0.094:0.094))
- (INTERCONNECT mprj.io_out[0] io_out[0] (0.406:0.406:0.406))
- (INTERCONNECT mprj.io_out[10] io_out[10] (0.099:0.099:0.099))
- (INTERCONNECT mprj.io_out[11] io_out[11] (0.110:0.110:0.110))
- (INTERCONNECT mprj.io_out[12] io_out[12] (0.119:0.119:0.119))
- (INTERCONNECT mprj.io_out[13] io_out[13] (0.129:0.129:0.129))
- (INTERCONNECT mprj.io_out[14] io_out[14] (0.167:0.167:0.167))
- (INTERCONNECT mprj.io_out[15] io_out[15] (0.244:0.244:0.244))
- (INTERCONNECT mprj.io_out[16] io_out[16] (0.117:0.117:0.117))
- (INTERCONNECT mprj.io_out[17] io_out[17] (0.171:0.171:0.171))
- (INTERCONNECT mprj.io_out[18] io_out[18] (0.133:0.133:0.133))
- (INTERCONNECT mprj.io_out[19] io_out[19] (0.078:0.078:0.078))
- (INTERCONNECT mprj.io_out[1] io_out[1] (0.194:0.194:0.194))
- (INTERCONNECT mprj.io_out[20] io_out[20] (0.048:0.048:0.048))
- (INTERCONNECT mprj.io_out[21] io_out[21] (0.059:0.059:0.059))
- (INTERCONNECT mprj.io_out[22] io_out[22] (0.092:0.092:0.092))
- (INTERCONNECT mprj.io_out[23] io_out[23] (0.105:0.105:0.105))
- (INTERCONNECT mprj.io_out[24] io_out[24] (0.095:0.095:0.095))
- (INTERCONNECT mprj.io_out[25] io_out[25] (0.245:0.245:0.245))
- (INTERCONNECT mprj.io_out[26] io_out[26] (0.077:0.077:0.077))
- (INTERCONNECT mprj.io_out[27] io_out[27] (0.063:0.063:0.063))
- (INTERCONNECT mprj.io_out[28] io_out[28] (0.055:0.055:0.055))
- (INTERCONNECT mprj.io_out[29] io_out[29] (0.204:0.204:0.204))
- (INTERCONNECT mprj.io_out[2] io_out[2] (0.210:0.210:0.210))
- (INTERCONNECT mprj.io_out[30] io_out[30] (0.039:0.039:0.039))
- (INTERCONNECT mprj.io_out[31] io_out[31] (0.049:0.049:0.049))
- (INTERCONNECT mprj.io_out[32] io_out[32] (0.085:0.085:0.085))
- (INTERCONNECT mprj.io_out[33] io_out[33] (0.118:0.118:0.118))
- (INTERCONNECT mprj.io_out[34] io_out[34] (0.147:0.147:0.147))
- (INTERCONNECT mprj.io_out[35] io_out[35] (0.160:0.160:0.160))
- (INTERCONNECT mprj.io_out[36] io_out[36] (0.125:0.125:0.125))
- (INTERCONNECT mprj.io_out[37] io_out[37] (0.103:0.103:0.103))
- (INTERCONNECT mprj.io_out[3] io_out[3] (0.191:0.191:0.191))
- (INTERCONNECT mprj.io_out[4] io_out[4] (0.136:0.136:0.136))
- (INTERCONNECT mprj.io_out[5] io_out[5] (0.159:0.159:0.159))
- (INTERCONNECT mprj.io_out[6] io_out[6] (0.135:0.135:0.135))
- (INTERCONNECT mprj.io_out[7] io_out[7] (0.126:0.126:0.126))
- (INTERCONNECT mprj.io_out[8] io_out[8] (0.080:0.080:0.080))
- (INTERCONNECT mprj.io_out[9] io_out[9] (0.091:0.091:0.091))
- (INTERCONNECT mprj.irq[0] user_irq[0] (0.160:0.160:0.160))
- (INTERCONNECT mprj.irq[1] user_irq[1] (0.164:0.164:0.164))
- (INTERCONNECT mprj.irq[2] user_irq[2] (0.096:0.096:0.096))
- (INTERCONNECT mprj.la_data_out[0] la_data_out[0] (0.047:0.047:0.047))
- (INTERCONNECT mprj.la_data_out[10] la_data_out[10] (0.100:0.100:0.100))
- (INTERCONNECT mprj.la_data_out[11] la_data_out[11] (0.080:0.080:0.080))
- (INTERCONNECT mprj.la_data_out[12] la_data_out[12] (0.080:0.080:0.080))
- (INTERCONNECT mprj.la_data_out[13] la_data_out[13] (0.100:0.100:0.100))
- (INTERCONNECT mprj.la_data_out[14] la_data_out[14] (0.064:0.064:0.064))
- (INTERCONNECT mprj.la_data_out[15] la_data_out[15] (0.080:0.080:0.080))
- (INTERCONNECT mprj.la_data_out[16] la_data_out[16] (0.045:0.045:0.045))
- (INTERCONNECT mprj.la_data_out[17] la_data_out[17] (0.129:0.129:0.129))
- (INTERCONNECT mprj.la_data_out[18] la_data_out[18] (0.073:0.073:0.073))
- (INTERCONNECT mprj.la_data_out[19] la_data_out[19] (0.051:0.051:0.051))
- (INTERCONNECT mprj.la_data_out[1] la_data_out[1] (0.061:0.061:0.061))
- (INTERCONNECT mprj.la_data_out[20] la_data_out[20] (0.131:0.131:0.131))
- (INTERCONNECT mprj.la_data_out[21] la_data_out[21] (0.045:0.045:0.045))
- (INTERCONNECT mprj.la_data_out[22] la_data_out[22] (0.054:0.054:0.054))
- (INTERCONNECT mprj.la_data_out[23] la_data_out[23] (0.062:0.062:0.062))
- (INTERCONNECT mprj.la_data_out[24] la_data_out[24] (0.076:0.076:0.076))
- (INTERCONNECT mprj.la_data_out[25] la_data_out[25] (0.075:0.075:0.075))
- (INTERCONNECT mprj.la_data_out[26] la_data_out[26] (0.095:0.095:0.095))
- (INTERCONNECT mprj.la_data_out[27] la_data_out[27] (0.071:0.071:0.071))
- (INTERCONNECT mprj.la_data_out[28] la_data_out[28] (0.102:0.102:0.102))
- (INTERCONNECT mprj.la_data_out[29] la_data_out[29] (0.072:0.072:0.072))
- (INTERCONNECT mprj.la_data_out[2] la_data_out[2] (0.038:0.038:0.038))
- (INTERCONNECT mprj.la_data_out[30] la_data_out[30] (0.102:0.102:0.102))
- (INTERCONNECT mprj.la_data_out[31] la_data_out[31] (0.080:0.080:0.080))
- (INTERCONNECT mprj.la_data_out[32] la_data_out[32] (0.101:0.101:0.101))
- (INTERCONNECT mprj.la_data_out[33] la_data_out[33] (0.107:0.107:0.107))
- (INTERCONNECT mprj.la_data_out[34] la_data_out[34] (0.119:0.119:0.119))
- (INTERCONNECT mprj.la_data_out[35] la_data_out[35] (0.119:0.119:0.119))
- (INTERCONNECT mprj.la_data_out[36] la_data_out[36] (0.072:0.072:0.072))
- (INTERCONNECT mprj.la_data_out[37] la_data_out[37] (0.095:0.095:0.095))
- (INTERCONNECT mprj.la_data_out[38] la_data_out[38] (0.142:0.142:0.142))
- (INTERCONNECT mprj.la_data_out[39] la_data_out[39] (0.137:0.137:0.137))
- (INTERCONNECT mprj.la_data_out[3] la_data_out[3] (0.055:0.055:0.055))
- (INTERCONNECT mprj.la_data_out[40] la_data_out[40] (0.104:0.104:0.104))
- (INTERCONNECT mprj.la_data_out[41] la_data_out[41] (0.141:0.141:0.141))
- (INTERCONNECT mprj.la_data_out[42] la_data_out[42] (0.156:0.156:0.156))
- (INTERCONNECT mprj.la_data_out[43] la_data_out[43] (0.160:0.160:0.160))
- (INTERCONNECT mprj.la_data_out[44] la_data_out[44] (0.135:0.135:0.135))
- (INTERCONNECT mprj.la_data_out[45] la_data_out[45] (0.072:0.072:0.072))
- (INTERCONNECT mprj.la_data_out[46] la_data_out[46] (0.155:0.155:0.155))
- (INTERCONNECT mprj.la_data_out[47] la_data_out[47] (0.142:0.142:0.142))
- (INTERCONNECT mprj.la_data_out[48] la_data_out[48] (0.184:0.184:0.184))
- (INTERCONNECT mprj.la_data_out[49] la_data_out[49] (0.126:0.126:0.126))
- (INTERCONNECT mprj.la_data_out[4] la_data_out[4] (0.087:0.087:0.087))
- (INTERCONNECT mprj.la_data_out[50] la_data_out[50] (0.198:0.198:0.198))
- (INTERCONNECT mprj.la_data_out[51] la_data_out[51] (0.205:0.205:0.205))
- (INTERCONNECT mprj.la_data_out[52] la_data_out[52] (0.141:0.141:0.141))
- (INTERCONNECT mprj.la_data_out[53] la_data_out[53] (0.144:0.144:0.144))
- (INTERCONNECT mprj.la_data_out[54] la_data_out[54] (0.126:0.126:0.126))
- (INTERCONNECT mprj.la_data_out[55] la_data_out[55] (0.220:0.220:0.220))
- (INTERCONNECT mprj.la_data_out[56] la_data_out[56] (0.238:0.238:0.238))
- (INTERCONNECT mprj.la_data_out[57] la_data_out[57] (0.126:0.126:0.126))
- (INTERCONNECT mprj.la_data_out[58] la_data_out[58] (0.158:0.158:0.158))
- (INTERCONNECT mprj.la_data_out[59] la_data_out[59] (0.151:0.151:0.151))
- (INTERCONNECT mprj.la_data_out[5] la_data_out[5] (0.083:0.083:0.083))
- (INTERCONNECT mprj.la_data_out[60] la_data_out[60] (0.247:0.247:0.247))
- (INTERCONNECT mprj.la_data_out[61] la_data_out[61] (0.105:0.105:0.105))
- (INTERCONNECT mprj.la_data_out[62] la_data_out[62] (0.165:0.165:0.165))
- (INTERCONNECT mprj.la_data_out[63] la_data_out[63] (0.172:0.172:0.172))
- (INTERCONNECT mprj.la_data_out[6] la_data_out[6] (0.047:0.047:0.047))
- (INTERCONNECT mprj.la_data_out[7] la_data_out[7] (0.066:0.066:0.066))
- (INTERCONNECT mprj.la_data_out[8] la_data_out[8] (0.059:0.059:0.059))
- (INTERCONNECT mprj.la_data_out[9] la_data_out[9] (0.065:0.065:0.065))
- (INTERCONNECT mprj.wbs_ack_o wbs_ack_o (0.037:0.037:0.037))
- (INTERCONNECT mprj.wbs_dat_o[0] wbs_dat_o[0] (0.035:0.035:0.035))
- (INTERCONNECT mprj.wbs_dat_o[10] wbs_dat_o[10] (0.031:0.031:0.031))
- (INTERCONNECT mprj.wbs_dat_o[11] wbs_dat_o[11] (0.047:0.047:0.047))
- (INTERCONNECT mprj.wbs_dat_o[12] wbs_dat_o[12] (0.031:0.031:0.031))
- (INTERCONNECT mprj.wbs_dat_o[13] wbs_dat_o[13] (0.026:0.026:0.026))
- (INTERCONNECT mprj.wbs_dat_o[14] wbs_dat_o[14] (0.040:0.040:0.040))
- (INTERCONNECT mprj.wbs_dat_o[15] wbs_dat_o[15] (0.027:0.027:0.027))
- (INTERCONNECT mprj.wbs_dat_o[16] wbs_dat_o[16] (0.033:0.033:0.033))
- (INTERCONNECT mprj.wbs_dat_o[17] wbs_dat_o[17] (0.030:0.030:0.030))
- (INTERCONNECT mprj.wbs_dat_o[18] wbs_dat_o[18] (0.038:0.038:0.038))
- (INTERCONNECT mprj.wbs_dat_o[19] wbs_dat_o[19] (0.027:0.027:0.027))
- (INTERCONNECT mprj.wbs_dat_o[1] wbs_dat_o[1] (0.059:0.059:0.059))
- (INTERCONNECT mprj.wbs_dat_o[20] wbs_dat_o[20] (0.038:0.038:0.038))
- (INTERCONNECT mprj.wbs_dat_o[21] wbs_dat_o[21] (0.031:0.031:0.031))
- (INTERCONNECT mprj.wbs_dat_o[22] wbs_dat_o[22] (0.050:0.050:0.050))
- (INTERCONNECT mprj.wbs_dat_o[23] wbs_dat_o[23] (0.048:0.048:0.048))
- (INTERCONNECT mprj.wbs_dat_o[24] wbs_dat_o[24] (0.049:0.049:0.049))
- (INTERCONNECT mprj.wbs_dat_o[25] wbs_dat_o[25] (0.059:0.059:0.059))
- (INTERCONNECT mprj.wbs_dat_o[26] wbs_dat_o[26] (0.047:0.047:0.047))
- (INTERCONNECT mprj.wbs_dat_o[27] wbs_dat_o[27] (0.038:0.038:0.038))
- (INTERCONNECT mprj.wbs_dat_o[28] wbs_dat_o[28] (0.056:0.056:0.056))
- (INTERCONNECT mprj.wbs_dat_o[29] wbs_dat_o[29] (0.050:0.050:0.050))
- (INTERCONNECT mprj.wbs_dat_o[2] wbs_dat_o[2] (0.052:0.052:0.052))
- (INTERCONNECT mprj.wbs_dat_o[30] wbs_dat_o[30] (0.044:0.044:0.044))
- (INTERCONNECT mprj.wbs_dat_o[31] wbs_dat_o[31] (0.059:0.059:0.059))
- (INTERCONNECT mprj.wbs_dat_o[3] wbs_dat_o[3] (0.052:0.052:0.052))
- (INTERCONNECT mprj.wbs_dat_o[4] wbs_dat_o[4] (0.047:0.047:0.047))
- (INTERCONNECT mprj.wbs_dat_o[5] wbs_dat_o[5] (0.034:0.034:0.034))
- (INTERCONNECT mprj.wbs_dat_o[6] wbs_dat_o[6] (0.042:0.042:0.042))
- (INTERCONNECT mprj.wbs_dat_o[7] wbs_dat_o[7] (0.059:0.059:0.059))
- (INTERCONNECT mprj.wbs_dat_o[8] wbs_dat_o[8] (0.037:0.037:0.037))
- (INTERCONNECT mprj.wbs_dat_o[9] wbs_dat_o[9] (0.061:0.061:0.061))
+ (INTERCONNECT io_in[0] wrapped_vga_clock.io_in[0] (2.678:2.678:2.678) (1.488:1.488:1.488))
+ (INTERCONNECT io_in[10] wrapped_vga_clock.io_in[10] (2.697:2.697:2.697) (1.501:1.501:1.501))
+ (INTERCONNECT io_in[11] wrapped_vga_clock.io_in[11] (2.904:2.904:2.904) (1.618:1.618:1.618))
+ (INTERCONNECT io_in[12] wrapped_vga_clock.io_in[12] (3.636:3.636:3.636) (2.030:2.030:2.030))
+ (INTERCONNECT io_in[13] wrapped_vga_clock.io_in[13] (3.055:3.055:3.055) (1.703:1.703:1.703))
+ (INTERCONNECT io_in[14] wrapped_vga_clock.io_in[14] (3.291:3.291:3.291) (1.836:1.836:1.836))
+ (INTERCONNECT io_in[15] wrapped_vga_clock.io_in[15] (4.225:4.225:4.225) (2.362:2.362:2.362))
+ (INTERCONNECT io_in[16] wrapped_vga_clock.io_in[16] (10.791:10.791:10.791) (5.953:5.953:5.953))
+ (INTERCONNECT io_in[17] wrapped_vga_clock.io_in[17] (5.887:5.887:5.887) (3.268:3.268:3.268))
+ (INTERCONNECT io_in[18] wrapped_vga_clock.io_in[18] (4.298:4.298:4.298) (2.395:2.395:2.395))
+ (INTERCONNECT io_in[19] wrapped_vga_clock.io_in[19] (3.352:3.352:3.352) (1.866:1.866:1.866))
+ (INTERCONNECT io_in[1] wrapped_vga_clock.io_in[1] (2.497:2.497:2.497) (1.387:1.387:1.387))
+ (INTERCONNECT io_in[20] wrapped_vga_clock.io_in[20] (2.227:2.227:2.227) (1.238:1.238:1.238))
+ (INTERCONNECT io_in[21] wrapped_vga_clock.io_in[21] (1.959:1.959:1.959) (1.087:1.087:1.087))
+ (INTERCONNECT io_in[22] wrapped_vga_clock.io_in[22] (2.078:2.078:2.078) (1.153:1.153:1.153))
+ (INTERCONNECT io_in[23] wrapped_vga_clock.io_in[23] (1.918:1.918:1.918) (1.065:1.065:1.065))
+ (INTERCONNECT io_in[24] wrapped_vga_clock.io_in[24] (5.314:5.314:5.314) (2.942:2.942:2.942))
+ (INTERCONNECT io_in[25] wrapped_vga_clock.io_in[25] (2.126:2.126:2.126) (1.181:1.181:1.181))
+ (INTERCONNECT io_in[26] wrapped_vga_clock.io_in[26] (1.716:1.716:1.716) (0.951:0.951:0.951))
+ (INTERCONNECT io_in[27] wrapped_vga_clock.io_in[27] (1.692:1.692:1.692) (0.937:0.937:0.937))
+ (INTERCONNECT io_in[28] wrapped_vga_clock.io_in[28] (4.263:4.263:4.263) (2.358:2.358:2.358))
+ (INTERCONNECT io_in[29] wrapped_vga_clock.io_in[29] (3.300:3.300:3.300) (1.827:1.827:1.827))
+ (INTERCONNECT io_in[2] wrapped_vga_clock.io_in[2] (2.157:2.157:2.157) (1.198:1.198:1.198))
+ (INTERCONNECT io_in[30] wrapped_vga_clock.io_in[30] (1.057:1.057:1.057) (0.584:0.584:0.584))
+ (INTERCONNECT io_in[31] wrapped_vga_clock.io_in[31] (2.248:2.248:2.248) (1.242:1.242:1.242))
+ (INTERCONNECT io_in[32] wrapped_vga_clock.io_in[32] (1.618:1.618:1.618) (0.894:0.894:0.894))
+ (INTERCONNECT io_in[33] wrapped_vga_clock.io_in[33] (0.545:0.545:0.545) (0.300:0.300:0.300))
+ (INTERCONNECT io_in[34] wrapped_vga_clock.io_in[34] (0.552:0.552:0.552) (0.304:0.304:0.304))
+ (INTERCONNECT io_in[35] wrapped_vga_clock.io_in[35] (0.784:0.784:0.784) (0.433:0.433:0.433))
+ (INTERCONNECT io_in[36] wrapped_vga_clock.io_in[36] (1.700:1.700:1.700) (0.940:0.940:0.940))
+ (INTERCONNECT io_in[37] wrapped_vga_clock.io_in[37] (1.277:1.277:1.277) (0.706:0.706:0.706))
+ (INTERCONNECT io_in[3] wrapped_vga_clock.io_in[3] (4.665:4.665:4.665) (2.589:2.589:2.589))
+ (INTERCONNECT io_in[4] wrapped_vga_clock.io_in[4] (1.816:1.816:1.816) (1.007:1.007:1.007))
+ (INTERCONNECT io_in[5] wrapped_vga_clock.io_in[5] (1.727:1.727:1.727) (0.959:0.959:0.959))
+ (INTERCONNECT io_in[6] wrapped_vga_clock.io_in[6] (2.718:2.718:2.718) (1.508:1.508:1.508))
+ (INTERCONNECT io_in[7] wrapped_vga_clock.io_in[7] (2.117:2.117:2.117) (1.175:1.175:1.175))
+ (INTERCONNECT io_in[8] wrapped_vga_clock.io_in[8] (2.576:2.576:2.576) (1.431:1.431:1.431))
+ (INTERCONNECT io_in[9] wrapped_vga_clock.io_in[9] (2.403:2.403:2.403) (1.336:1.336:1.336))
+ (INTERCONNECT wb_clk_i wrapped_vga_clock.wb_clk_i (1.415:1.415:1.415) (0.783:0.783:0.783))
+ (INTERCONNECT wb_rst_i wrapped_vga_clock.wb_rst_i (1.850:1.850:1.850) (1.025:1.025:1.025))
+ (INTERCONNECT wrapped_vga_clock.io_oeb[0] io_oeb[0] (0.124:0.124:0.124))
+ (INTERCONNECT wrapped_vga_clock.io_oeb[10] io_oeb[10] (0.119:0.119:0.119))
+ (INTERCONNECT wrapped_vga_clock.io_oeb[11] io_oeb[11] (0.166:0.166:0.166))
+ (INTERCONNECT wrapped_vga_clock.io_oeb[12] io_oeb[12] (0.193:0.193:0.193))
+ (INTERCONNECT wrapped_vga_clock.io_oeb[13] io_oeb[13] (0.174:0.174:0.174))
+ (INTERCONNECT wrapped_vga_clock.io_oeb[14] io_oeb[14] (0.213:0.213:0.213))
+ (INTERCONNECT wrapped_vga_clock.io_oeb[15] io_oeb[15] (0.260:0.260:0.260))
+ (INTERCONNECT wrapped_vga_clock.io_oeb[16] io_oeb[16] (0.148:0.148:0.148))
+ (INTERCONNECT wrapped_vga_clock.io_oeb[17] io_oeb[17] (0.140:0.140:0.140))
+ (INTERCONNECT wrapped_vga_clock.io_oeb[18] io_oeb[18] (0.126:0.126:0.126))
+ (INTERCONNECT wrapped_vga_clock.io_oeb[19] io_oeb[19] (0.099:0.099:0.099))
+ (INTERCONNECT wrapped_vga_clock.io_oeb[1] io_oeb[1] (0.118:0.118:0.118))
+ (INTERCONNECT wrapped_vga_clock.io_oeb[20] io_oeb[20] (0.084:0.084:0.084))
+ (INTERCONNECT wrapped_vga_clock.io_oeb[21] io_oeb[21] (0.058:0.058:0.058))
+ (INTERCONNECT wrapped_vga_clock.io_oeb[22] io_oeb[22] (0.099:0.099:0.099))
+ (INTERCONNECT wrapped_vga_clock.io_oeb[23] io_oeb[23] (0.106:0.106:0.106))
+ (INTERCONNECT wrapped_vga_clock.io_oeb[24] io_oeb[24] (0.106:0.106:0.106))
+ (INTERCONNECT wrapped_vga_clock.io_oeb[25] io_oeb[25] (0.077:0.077:0.077))
+ (INTERCONNECT wrapped_vga_clock.io_oeb[26] io_oeb[26] (0.116:0.116:0.116))
+ (INTERCONNECT wrapped_vga_clock.io_oeb[27] io_oeb[27] (0.060:0.060:0.060))
+ (INTERCONNECT wrapped_vga_clock.io_oeb[28] io_oeb[28] (0.069:0.069:0.069))
+ (INTERCONNECT wrapped_vga_clock.io_oeb[29] io_oeb[29] (0.089:0.089:0.089))
+ (INTERCONNECT wrapped_vga_clock.io_oeb[2] io_oeb[2] (0.104:0.104:0.104))
+ (INTERCONNECT wrapped_vga_clock.io_oeb[30] io_oeb[30] (0.025:0.025:0.025))
+ (INTERCONNECT wrapped_vga_clock.io_oeb[31] io_oeb[31] (0.047:0.047:0.047))
+ (INTERCONNECT wrapped_vga_clock.io_oeb[32] io_oeb[32] (0.027:0.027:0.027))
+ (INTERCONNECT wrapped_vga_clock.io_oeb[33] io_oeb[33] (0.018:0.018:0.018))
+ (INTERCONNECT wrapped_vga_clock.io_oeb[34] io_oeb[34] (0.042:0.042:0.042))
+ (INTERCONNECT wrapped_vga_clock.io_oeb[35] io_oeb[35] (0.027:0.027:0.027))
+ (INTERCONNECT wrapped_vga_clock.io_oeb[36] io_oeb[36] (0.040:0.040:0.040))
+ (INTERCONNECT wrapped_vga_clock.io_oeb[37] io_oeb[37] (0.050:0.050:0.050))
+ (INTERCONNECT wrapped_vga_clock.io_oeb[3] io_oeb[3] (0.101:0.101:0.101))
+ (INTERCONNECT wrapped_vga_clock.io_oeb[4] io_oeb[4] (0.190:0.190:0.190))
+ (INTERCONNECT wrapped_vga_clock.io_oeb[5] io_oeb[5] (0.165:0.165:0.165))
+ (INTERCONNECT wrapped_vga_clock.io_oeb[6] io_oeb[6] (0.115:0.115:0.115))
+ (INTERCONNECT wrapped_vga_clock.io_oeb[7] io_oeb[7] (0.214:0.214:0.214))
+ (INTERCONNECT wrapped_vga_clock.io_oeb[8] io_oeb[8] (0.124:0.124:0.124))
+ (INTERCONNECT wrapped_vga_clock.io_oeb[9] io_oeb[9] (0.115:0.115:0.115))
+ (INTERCONNECT wrapped_vga_clock.io_out[0] io_out[0] (0.111:0.111:0.111))
+ (INTERCONNECT wrapped_vga_clock.io_out[10] io_out[10] (0.175:0.175:0.175))
+ (INTERCONNECT wrapped_vga_clock.io_out[11] io_out[11] (0.530:0.530:0.530))
+ (INTERCONNECT wrapped_vga_clock.io_out[12] io_out[12] (0.157:0.157:0.157))
+ (INTERCONNECT wrapped_vga_clock.io_out[13] io_out[13] (0.187:0.187:0.187))
+ (INTERCONNECT wrapped_vga_clock.io_out[14] io_out[14] (0.217:0.217:0.217))
+ (INTERCONNECT wrapped_vga_clock.io_out[15] io_out[15] (0.169:0.169:0.169))
+ (INTERCONNECT wrapped_vga_clock.io_out[16] io_out[16] (0.173:0.173:0.173))
+ (INTERCONNECT wrapped_vga_clock.io_out[17] io_out[17] (0.161:0.161:0.161))
+ (INTERCONNECT wrapped_vga_clock.io_out[18] io_out[18] (0.136:0.136:0.136))
+ (INTERCONNECT wrapped_vga_clock.io_out[19] io_out[19] (0.219:0.219:0.219))
+ (INTERCONNECT wrapped_vga_clock.io_out[1] io_out[1] (0.118:0.118:0.118))
+ (INTERCONNECT wrapped_vga_clock.io_out[20] io_out[20] (0.104:0.104:0.104))
+ (INTERCONNECT wrapped_vga_clock.io_out[21] io_out[21] (0.115:0.115:0.115))
+ (INTERCONNECT wrapped_vga_clock.io_out[22] io_out[22] (0.063:0.063:0.063))
+ (INTERCONNECT wrapped_vga_clock.io_out[23] io_out[23] (0.085:0.085:0.085))
+ (INTERCONNECT wrapped_vga_clock.io_out[24] io_out[24] (0.100:0.100:0.100))
+ (INTERCONNECT wrapped_vga_clock.io_out[25] io_out[25] (0.081:0.081:0.081))
+ (INTERCONNECT wrapped_vga_clock.io_out[26] io_out[26] (0.077:0.077:0.077))
+ (INTERCONNECT wrapped_vga_clock.io_out[27] io_out[27] (0.065:0.065:0.065))
+ (INTERCONNECT wrapped_vga_clock.io_out[28] io_out[28] (0.051:0.051:0.051))
+ (INTERCONNECT wrapped_vga_clock.io_out[29] io_out[29] (0.041:0.041:0.041))
+ (INTERCONNECT wrapped_vga_clock.io_out[2] io_out[2] (0.093:0.093:0.093))
+ (INTERCONNECT wrapped_vga_clock.io_out[30] io_out[30] (0.047:0.047:0.047))
+ (INTERCONNECT wrapped_vga_clock.io_out[31] io_out[31] (0.062:0.062:0.062))
+ (INTERCONNECT wrapped_vga_clock.io_out[32] io_out[32] (0.014:0.014:0.014))
+ (INTERCONNECT wrapped_vga_clock.io_out[33] io_out[33] (0.013:0.013:0.013))
+ (INTERCONNECT wrapped_vga_clock.io_out[34] io_out[34] (0.017:0.017:0.017))
+ (INTERCONNECT wrapped_vga_clock.io_out[35] io_out[35] (0.024:0.024:0.024))
+ (INTERCONNECT wrapped_vga_clock.io_out[36] io_out[36] (0.031:0.031:0.031))
+ (INTERCONNECT wrapped_vga_clock.io_out[37] io_out[37] (0.059:0.059:0.059))
+ (INTERCONNECT wrapped_vga_clock.io_out[3] io_out[3] (0.078:0.078:0.078))
+ (INTERCONNECT wrapped_vga_clock.io_out[4] io_out[4] (0.155:0.155:0.155))
+ (INTERCONNECT wrapped_vga_clock.io_out[5] io_out[5] (0.109:0.109:0.109))
+ (INTERCONNECT wrapped_vga_clock.io_out[6] io_out[6] (0.093:0.093:0.093))
+ (INTERCONNECT wrapped_vga_clock.io_out[7] io_out[7] (0.102:0.102:0.102))
+ (INTERCONNECT wrapped_vga_clock.io_out[8] io_out[8] (0.133:0.133:0.133))
+ (INTERCONNECT wrapped_vga_clock.io_out[9] io_out[9] (0.142:0.142:0.142))
)
)
)
diff --git a/sdf/user_proj_example.sdf b/sdf/user_proj_example.sdf
index 57b3567..612bd0f 100644
--- a/sdf/user_proj_example.sdf
+++ b/sdf/user_proj_example.sdf
@@ -1,7 +1,7 @@
(DELAYFILE
(SDFVERSION "3.0")
(DESIGN "user_proj_example")
- (DATE "Mon Nov 21 16:18:08 2022")
+ (DATE "Wed Nov 23 09:14:01 2022")
(VENDOR "Parallax")
(PROGRAM "STA")
(VERSION "2.3.2")
diff --git a/sdf/user_project_wrapper.sdf b/sdf/user_project_wrapper.sdf
index 7c62719..66ff965 100644
--- a/sdf/user_project_wrapper.sdf
+++ b/sdf/user_project_wrapper.sdf
@@ -1,7 +1,7 @@
(DELAYFILE
(SDFVERSION "3.0")
(DESIGN "user_project_wrapper")
- (DATE "Mon Nov 21 16:20:25 2022")
+ (DATE "Wed Nov 23 09:34:44 2022")
(VENDOR "Parallax")
(PROGRAM "STA")
(VERSION "2.3.2")
@@ -12,421 +12,122 @@
(INSTANCE)
(DELAY
(ABSOLUTE
- (INTERCONNECT io_in[0] mprj.io_in[0] (3.522:3.522:3.522) (1.964:1.964:1.964))
- (INTERCONNECT io_in[10] mprj.io_in[10] (2.498:2.498:2.498) (1.388:1.388:1.388))
- (INTERCONNECT io_in[11] mprj.io_in[11] (2.450:2.450:2.450) (1.363:1.363:1.363))
- (INTERCONNECT io_in[12] mprj.io_in[12] (2.604:2.604:2.604) (1.449:1.449:1.449))
- (INTERCONNECT io_in[13] mprj.io_in[13] (2.936:2.936:2.936) (1.635:1.635:1.635))
- (INTERCONNECT io_in[14] mprj.io_in[14] (2.996:2.996:2.996) (1.669:1.669:1.669))
- (INTERCONNECT io_in[15] mprj.io_in[15] (3.191:3.191:3.191) (1.778:1.778:1.778))
- (INTERCONNECT io_in[16] mprj.io_in[16] (3.530:3.530:3.530) (1.966:1.966:1.966))
- (INTERCONNECT io_in[17] mprj.io_in[17] (2.542:2.542:2.542) (1.412:1.412:1.412))
- (INTERCONNECT io_in[18] mprj.io_in[18] (4.839:4.839:4.839) (2.681:2.681:2.681))
- (INTERCONNECT io_in[19] mprj.io_in[19] (4.281:4.281:4.281) (2.371:2.371:2.371))
- (INTERCONNECT io_in[1] mprj.io_in[1] (5.113:5.113:5.113) (2.844:2.844:2.844))
- (INTERCONNECT io_in[20] mprj.io_in[20] (1.559:1.559:1.559) (0.863:0.863:0.863))
- (INTERCONNECT io_in[21] mprj.io_in[21] (1.494:1.494:1.494) (0.828:0.828:0.828))
- (INTERCONNECT io_in[22] mprj.io_in[22] (2.181:2.181:2.181) (1.209:1.209:1.209))
- (INTERCONNECT io_in[23] mprj.io_in[23] (2.079:2.079:2.079) (1.153:1.153:1.153))
- (INTERCONNECT io_in[24] mprj.io_in[24] (2.875:2.875:2.875) (1.598:1.598:1.598))
- (INTERCONNECT io_in[25] mprj.io_in[25] (2.288:2.288:2.288) (1.270:1.270:1.270))
- (INTERCONNECT io_in[26] mprj.io_in[26] (1.940:1.940:1.940) (1.076:1.076:1.076))
- (INTERCONNECT io_in[27] mprj.io_in[27] (5.627:5.627:5.627) (3.109:3.109:3.109))
- (INTERCONNECT io_in[28] mprj.io_in[28] (1.717:1.717:1.717) (0.951:0.951:0.951))
- (INTERCONNECT io_in[29] mprj.io_in[29] (1.686:1.686:1.686) (0.933:0.933:0.933))
- (INTERCONNECT io_in[2] mprj.io_in[2] (7.009:7.009:7.009) (3.880:3.880:3.880))
- (INTERCONNECT io_in[30] mprj.io_in[30] (1.271:1.271:1.271) (0.703:0.703:0.703))
- (INTERCONNECT io_in[31] mprj.io_in[31] (4.178:4.178:4.178) (2.301:2.301:2.301))
- (INTERCONNECT io_in[32] mprj.io_in[32] (6.366:6.366:6.366) (3.508:3.508:3.508))
- (INTERCONNECT io_in[33] mprj.io_in[33] (3.621:3.621:3.621) (2.002:2.002:2.002))
- (INTERCONNECT io_in[34] mprj.io_in[34] (6.625:6.625:6.625) (3.657:3.657:3.657))
- (INTERCONNECT io_in[35] mprj.io_in[35] (2.058:2.058:2.058) (1.141:1.141:1.141))
- (INTERCONNECT io_in[36] mprj.io_in[36] (3.127:3.127:3.127) (1.732:1.732:1.732))
- (INTERCONNECT io_in[37] mprj.io_in[37] (2.524:2.524:2.524) (1.402:1.402:1.402))
- (INTERCONNECT io_in[3] mprj.io_in[3] (4.976:4.976:4.976) (2.760:2.760:2.760))
- (INTERCONNECT io_in[4] mprj.io_in[4] (5.053:5.053:5.053) (2.809:2.809:2.809))
- (INTERCONNECT io_in[5] mprj.io_in[5] (6.232:6.232:6.232) (3.445:3.445:3.445))
- (INTERCONNECT io_in[6] mprj.io_in[6] (5.258:5.258:5.258) (2.911:2.911:2.911))
- (INTERCONNECT io_in[7] mprj.io_in[7] (6.411:6.411:6.411) (3.533:3.533:3.533))
- (INTERCONNECT io_in[8] mprj.io_in[8] (1.973:1.973:1.973) (1.097:1.097:1.097))
- (INTERCONNECT io_in[9] mprj.io_in[9] (4.089:4.089:4.089) (2.268:2.268:2.268))
- (INTERCONNECT la_data_in[0] mprj.la_data_in[0] (3.415:3.415:3.415) (1.882:1.882:1.882))
- (INTERCONNECT la_data_in[10] mprj.la_data_in[10] (1.801:1.801:1.801) (0.994:0.994:0.994))
- (INTERCONNECT la_data_in[11] mprj.la_data_in[11] (4.467:4.467:4.467) (2.467:2.467:2.467))
- (INTERCONNECT la_data_in[12] mprj.la_data_in[12] (1.851:1.851:1.851) (1.022:1.022:1.022))
- (INTERCONNECT la_data_in[13] mprj.la_data_in[13] (2.098:2.098:2.098) (1.159:1.159:1.159))
- (INTERCONNECT la_data_in[14] mprj.la_data_in[14] (6.118:6.118:6.118) (3.377:3.377:3.377))
- (INTERCONNECT la_data_in[15] mprj.la_data_in[15] (1.679:1.679:1.679) (0.928:0.928:0.928))
- (INTERCONNECT la_data_in[16] mprj.la_data_in[16] (4.353:4.353:4.353) (2.404:2.404:2.404))
- (INTERCONNECT la_data_in[17] mprj.la_data_in[17] (4.731:4.731:4.731) (2.612:2.612:2.612))
- (INTERCONNECT la_data_in[18] mprj.la_data_in[18] (4.448:4.448:4.448) (2.456:2.456:2.456))
- (INTERCONNECT la_data_in[19] mprj.la_data_in[19] (2.992:2.992:2.992) (1.652:1.652:1.652))
- (INTERCONNECT la_data_in[1] mprj.la_data_in[1] (3.345:3.345:3.345) (1.845:1.845:1.845))
- (INTERCONNECT la_data_in[20] mprj.la_data_in[20] (2.570:2.570:2.570) (1.419:1.419:1.419))
- (INTERCONNECT la_data_in[21] mprj.la_data_in[21] (4.161:4.161:4.161) (2.298:2.298:2.298))
- (INTERCONNECT la_data_in[22] mprj.la_data_in[22] (3.221:3.221:3.221) (1.779:1.779:1.779))
- (INTERCONNECT la_data_in[23] mprj.la_data_in[23] (3.602:3.602:3.602) (1.985:1.985:1.985))
- (INTERCONNECT la_data_in[24] mprj.la_data_in[24] (5.845:5.845:5.845) (3.228:3.228:3.228))
- (INTERCONNECT la_data_in[25] mprj.la_data_in[25] (2.723:2.723:2.723) (1.504:1.504:1.504))
- (INTERCONNECT la_data_in[26] mprj.la_data_in[26] (2.904:2.904:2.904) (1.604:1.604:1.604))
- (INTERCONNECT la_data_in[27] mprj.la_data_in[27] (4.486:4.486:4.486) (2.479:2.479:2.479))
- (INTERCONNECT la_data_in[28] mprj.la_data_in[28] (3.151:3.151:3.151) (1.740:1.740:1.740))
- (INTERCONNECT la_data_in[29] mprj.la_data_in[29] (3.310:3.310:3.310) (1.827:1.827:1.827))
- (INTERCONNECT la_data_in[2] mprj.la_data_in[2] (2.734:2.734:2.734) (1.505:1.505:1.505))
- (INTERCONNECT la_data_in[30] mprj.la_data_in[30] (4.827:4.827:4.827) (2.667:2.667:2.667))
- (INTERCONNECT la_data_in[31] mprj.la_data_in[31] (4.735:4.735:4.735) (2.614:2.614:2.614))
- (INTERCONNECT la_data_in[32] mprj.la_data_in[32] (4.909:4.909:4.909) (2.710:2.710:2.710))
- (INTERCONNECT la_data_in[33] mprj.la_data_in[33] (3.683:3.683:3.683) (2.036:2.036:2.036))
- (INTERCONNECT la_data_in[34] mprj.la_data_in[34] (3.850:3.850:3.850) (2.128:2.128:2.128))
- (INTERCONNECT la_data_in[35] mprj.la_data_in[35] (4.399:4.399:4.399) (2.432:2.432:2.432))
- (INTERCONNECT la_data_in[36] mprj.la_data_in[36] (3.938:3.938:3.938) (2.177:2.177:2.177))
- (INTERCONNECT la_data_in[37] mprj.la_data_in[37] (3.864:3.864:3.864) (2.136:2.136:2.136))
- (INTERCONNECT la_data_in[38] mprj.la_data_in[38] (5.105:5.105:5.105) (2.819:2.819:2.819))
- (INTERCONNECT la_data_in[39] mprj.la_data_in[39] (4.326:4.326:4.326) (2.392:2.392:2.392))
- (INTERCONNECT la_data_in[3] mprj.la_data_in[3] (1.170:1.170:1.170) (0.646:0.646:0.646))
- (INTERCONNECT la_data_in[40] mprj.la_data_in[40] (6.186:6.186:6.186) (3.414:3.414:3.414))
- (INTERCONNECT la_data_in[41] mprj.la_data_in[41] (3.956:3.956:3.956) (2.187:2.187:2.187))
- (INTERCONNECT la_data_in[42] mprj.la_data_in[42] (5.018:5.018:5.018) (2.772:2.772:2.772))
- (INTERCONNECT la_data_in[43] mprj.la_data_in[43] (6.910:6.910:6.910) (3.813:3.813:3.813))
- (INTERCONNECT la_data_in[44] mprj.la_data_in[44] (3.544:3.544:3.544) (1.961:1.961:1.961))
- (INTERCONNECT la_data_in[45] mprj.la_data_in[45] (6.138:6.138:6.138) (3.389:3.389:3.389))
- (INTERCONNECT la_data_in[46] mprj.la_data_in[46] (5.284:5.284:5.284) (2.922:2.922:2.922))
- (INTERCONNECT la_data_in[47] mprj.la_data_in[47] (7.020:7.020:7.020) (3.874:3.874:3.874))
- (INTERCONNECT la_data_in[48] mprj.la_data_in[48] (6.404:6.404:6.404) (3.535:3.535:3.535))
- (INTERCONNECT la_data_in[49] mprj.la_data_in[49] (5.757:5.757:5.757) (3.184:3.184:3.184))
- (INTERCONNECT la_data_in[4] mprj.la_data_in[4] (3.333:3.333:3.333) (1.838:1.838:1.838))
- (INTERCONNECT la_data_in[50] mprj.la_data_in[50] (7.864:7.864:7.864) (4.337:4.337:4.337))
- (INTERCONNECT la_data_in[51] mprj.la_data_in[51] (8.004:8.004:8.004) (4.414:4.414:4.414))
- (INTERCONNECT la_data_in[52] mprj.la_data_in[52] (7.654:7.654:7.654) (4.222:4.222:4.222))
- (INTERCONNECT la_data_in[53] mprj.la_data_in[53] (7.175:7.175:7.175) (3.959:3.959:3.959))
- (INTERCONNECT la_data_in[54] mprj.la_data_in[54] (3.638:3.638:3.638) (2.014:2.014:2.014))
- (INTERCONNECT la_data_in[55] mprj.la_data_in[55] (3.663:3.663:3.663) (2.029:2.029:2.029))
- (INTERCONNECT la_data_in[56] mprj.la_data_in[56] (7.451:7.451:7.451) (4.105:4.105:4.105))
- (INTERCONNECT la_data_in[57] mprj.la_data_in[57] (5.056:5.056:5.056) (2.796:2.796:2.796))
- (INTERCONNECT la_data_in[58] mprj.la_data_in[58] (4.399:4.399:4.399) (2.434:2.434:2.434))
- (INTERCONNECT la_data_in[59] mprj.la_data_in[59] (4.653:4.653:4.653) (2.575:2.575:2.575))
- (INTERCONNECT la_data_in[5] mprj.la_data_in[5] (3.324:3.324:3.324) (1.834:1.834:1.834))
- (INTERCONNECT la_data_in[60] mprj.la_data_in[60] (5.118:5.118:5.118) (2.831:2.831:2.831))
- (INTERCONNECT la_data_in[61] mprj.la_data_in[61] (6.112:6.112:6.112) (3.381:3.381:3.381))
- (INTERCONNECT la_data_in[62] mprj.la_data_in[62] (5.200:5.200:5.200) (2.876:2.876:2.876))
- (INTERCONNECT la_data_in[63] mprj.la_data_in[63] (4.443:4.443:4.443) (2.460:2.460:2.460))
- (INTERCONNECT la_data_in[6] mprj.la_data_in[6] (2.899:2.899:2.899) (1.601:1.601:1.601))
- (INTERCONNECT la_data_in[7] mprj.la_data_in[7] (5.217:5.217:5.217) (2.877:2.877:2.877))
- (INTERCONNECT la_data_in[8] mprj.la_data_in[8] (5.641:5.641:5.641) (3.112:3.112:3.112))
- (INTERCONNECT la_data_in[9] mprj.la_data_in[9] (1.443:1.443:1.443) (0.797:0.797:0.797))
- (INTERCONNECT la_oenb[0] mprj.la_oenb[0] (4.261:4.261:4.261) (2.347:2.347:2.347))
- (INTERCONNECT la_oenb[10] mprj.la_oenb[10] (3.551:3.551:3.551) (1.960:1.960:1.960))
- (INTERCONNECT la_oenb[11] mprj.la_oenb[11] (3.517:3.517:3.517) (1.941:1.941:1.941))
- (INTERCONNECT la_oenb[12] mprj.la_oenb[12] (2.461:2.461:2.461) (1.360:1.360:1.360))
- (INTERCONNECT la_oenb[13] mprj.la_oenb[13] (3.861:3.861:3.861) (2.131:2.131:2.131))
- (INTERCONNECT la_oenb[14] mprj.la_oenb[14] (2.113:2.113:2.113) (1.168:1.168:1.168))
- (INTERCONNECT la_oenb[15] mprj.la_oenb[15] (1.943:1.943:1.943) (1.074:1.074:1.074))
- (INTERCONNECT la_oenb[16] mprj.la_oenb[16] (1.268:1.268:1.268) (0.701:0.701:0.701))
- (INTERCONNECT la_oenb[17] mprj.la_oenb[17] (5.331:5.331:5.331) (2.945:2.945:2.945))
- (INTERCONNECT la_oenb[18] mprj.la_oenb[18] (2.540:2.540:2.540) (1.403:1.403:1.403))
- (INTERCONNECT la_oenb[19] mprj.la_oenb[19] (2.602:2.602:2.602) (1.437:1.437:1.437))
- (INTERCONNECT la_oenb[1] mprj.la_oenb[1] (2.673:2.673:2.673) (1.472:1.472:1.472))
- (INTERCONNECT la_oenb[20] mprj.la_oenb[20] (4.646:4.646:4.646) (2.567:2.567:2.567))
- (INTERCONNECT la_oenb[21] mprj.la_oenb[21] (2.131:2.131:2.131) (1.177:1.177:1.177))
- (INTERCONNECT la_oenb[22] mprj.la_oenb[22] (1.428:1.428:1.428) (0.789:0.789:0.789))
- (INTERCONNECT la_oenb[23] mprj.la_oenb[23] (4.791:4.791:4.791) (2.647:2.647:2.647))
- (INTERCONNECT la_oenb[24] mprj.la_oenb[24] (3.953:3.953:3.953) (2.183:2.183:2.183))
- (INTERCONNECT la_oenb[25] mprj.la_oenb[25] (6.508:6.508:6.508) (3.594:3.594:3.594))
- (INTERCONNECT la_oenb[26] mprj.la_oenb[26] (5.703:5.703:5.703) (3.150:3.150:3.150))
- (INTERCONNECT la_oenb[27] mprj.la_oenb[27] (3.663:3.663:3.663) (2.023:2.023:2.023))
- (INTERCONNECT la_oenb[28] mprj.la_oenb[28] (3.658:3.658:3.658) (2.020:2.020:2.020))
- (INTERCONNECT la_oenb[29] mprj.la_oenb[29] (4.609:4.609:4.609) (2.547:2.547:2.547))
- (INTERCONNECT la_oenb[2] mprj.la_oenb[2] (1.587:1.587:1.587) (0.876:0.876:0.876))
- (INTERCONNECT la_oenb[30] mprj.la_oenb[30] (5.252:5.252:5.252) (2.898:2.898:2.898))
- (INTERCONNECT la_oenb[31] mprj.la_oenb[31] (1.695:1.695:1.695) (0.938:0.938:0.938))
- (INTERCONNECT la_oenb[32] mprj.la_oenb[32] (5.393:5.393:5.393) (2.980:2.980:2.980))
- (INTERCONNECT la_oenb[33] mprj.la_oenb[33] (5.465:5.465:5.465) (3.016:3.016:3.016))
- (INTERCONNECT la_oenb[34] mprj.la_oenb[34] (3.961:3.961:3.961) (2.190:2.190:2.190))
- (INTERCONNECT la_oenb[35] mprj.la_oenb[35] (5.352:5.352:5.352) (2.949:2.949:2.949))
- (INTERCONNECT la_oenb[36] mprj.la_oenb[36] (5.455:5.455:5.455) (3.014:3.014:3.014))
- (INTERCONNECT la_oenb[37] mprj.la_oenb[37] (2.721:2.721:2.721) (1.502:1.502:1.502))
- (INTERCONNECT la_oenb[38] mprj.la_oenb[38] (7.995:7.995:7.995) (4.414:4.414:4.414))
- (INTERCONNECT la_oenb[39] mprj.la_oenb[39] (7.123:7.123:7.123) (3.929:3.929:3.929))
- (INTERCONNECT la_oenb[3] mprj.la_oenb[3] (1.475:1.475:1.475) (0.815:0.815:0.815))
- (INTERCONNECT la_oenb[40] mprj.la_oenb[40] (1.888:1.888:1.888) (1.046:1.046:1.046))
- (INTERCONNECT la_oenb[41] mprj.la_oenb[41] (3.556:3.556:3.556) (1.966:1.966:1.966))
- (INTERCONNECT la_oenb[42] mprj.la_oenb[42] (2.585:2.585:2.585) (1.429:1.429:1.429))
- (INTERCONNECT la_oenb[43] mprj.la_oenb[43] (1.829:1.829:1.829) (1.013:1.013:1.013))
- (INTERCONNECT la_oenb[44] mprj.la_oenb[44] (6.541:6.541:6.541) (3.609:3.609:3.609))
- (INTERCONNECT la_oenb[45] mprj.la_oenb[45] (4.854:4.854:4.854) (2.686:2.686:2.686))
- (INTERCONNECT la_oenb[46] mprj.la_oenb[46] (6.861:6.861:6.861) (3.785:3.785:3.785))
- (INTERCONNECT la_oenb[47] mprj.la_oenb[47] (5.004:5.004:5.004) (2.765:2.765:2.765))
- (INTERCONNECT la_oenb[48] mprj.la_oenb[48] (2.594:2.594:2.594) (1.435:1.435:1.435))
- (INTERCONNECT la_oenb[49] mprj.la_oenb[49] (3.974:3.974:3.974) (2.196:2.196:2.196))
- (INTERCONNECT la_oenb[4] mprj.la_oenb[4] (5.116:5.116:5.116) (2.820:2.820:2.820))
- (INTERCONNECT la_oenb[50] mprj.la_oenb[50] (7.357:7.357:7.357) (4.058:4.058:4.058))
- (INTERCONNECT la_oenb[51] mprj.la_oenb[51] (7.814:7.814:7.814) (4.308:4.308:4.308))
- (INTERCONNECT la_oenb[52] mprj.la_oenb[52] (4.841:4.841:4.841) (2.675:2.675:2.675))
- (INTERCONNECT la_oenb[53] mprj.la_oenb[53] (5.512:5.512:5.512) (3.045:3.045:3.045))
- (INTERCONNECT la_oenb[54] mprj.la_oenb[54] (10.004:10.004:10.004) (5.522:5.522:5.522))
- (INTERCONNECT la_oenb[55] mprj.la_oenb[55] (8.296:8.296:8.296) (4.567:4.567:4.567))
- (INTERCONNECT la_oenb[56] mprj.la_oenb[56] (6.400:6.400:6.400) (3.534:3.534:3.534))
- (INTERCONNECT la_oenb[57] mprj.la_oenb[57] (6.471:6.471:6.471) (3.571:3.571:3.571))
- (INTERCONNECT la_oenb[58] mprj.la_oenb[58] (8.783:8.783:8.783) (4.837:4.837:4.837))
- (INTERCONNECT la_oenb[59] mprj.la_oenb[59] (3.912:3.912:3.912) (2.167:2.167:2.167))
- (INTERCONNECT la_oenb[5] mprj.la_oenb[5] (3.923:3.923:3.923) (2.166:2.166:2.166))
- (INTERCONNECT la_oenb[60] mprj.la_oenb[60] (2.011:2.011:2.011) (1.115:1.115:1.115))
- (INTERCONNECT la_oenb[61] mprj.la_oenb[61] (5.338:5.338:5.338) (2.955:2.955:2.955))
- (INTERCONNECT la_oenb[62] mprj.la_oenb[62] (8.717:8.717:8.717) (4.800:4.800:4.800))
- (INTERCONNECT la_oenb[63] mprj.la_oenb[63] (2.274:2.274:2.274) (1.260:1.260:1.260))
- (INTERCONNECT la_oenb[6] mprj.la_oenb[6] (4.483:4.483:4.483) (2.476:2.476:2.476))
- (INTERCONNECT la_oenb[7] mprj.la_oenb[7] (2.119:2.119:2.119) (1.171:1.171:1.171))
- (INTERCONNECT la_oenb[8] mprj.la_oenb[8] (3.528:3.528:3.528) (1.948:1.948:1.948))
- (INTERCONNECT la_oenb[9] mprj.la_oenb[9] (4.341:4.341:4.341) (2.397:2.397:2.397))
- (INTERCONNECT wb_clk_i mprj.wb_clk_i (1.732:1.732:1.732) (0.958:0.958:0.958))
- (INTERCONNECT wb_rst_i mprj.wb_rst_i (3.406:3.406:3.406) (1.880:1.880:1.880))
- (INTERCONNECT wbs_adr_i[0] mprj.wbs_adr_i[0] (2.336:2.336:2.336) (1.290:1.290:1.290))
- (INTERCONNECT wbs_adr_i[10] mprj.wbs_adr_i[10] (1.260:1.260:1.260) (0.695:0.695:0.695))
- (INTERCONNECT wbs_adr_i[11] mprj.wbs_adr_i[11] (2.027:2.027:2.027) (1.119:1.119:1.119))
- (INTERCONNECT wbs_adr_i[12] mprj.wbs_adr_i[12] (1.958:1.958:1.958) (1.081:1.081:1.081))
- (INTERCONNECT wbs_adr_i[13] mprj.wbs_adr_i[13] (1.769:1.769:1.769) (0.977:0.977:0.977))
- (INTERCONNECT wbs_adr_i[14] mprj.wbs_adr_i[14] (1.793:1.793:1.793) (0.990:0.990:0.990))
- (INTERCONNECT wbs_adr_i[15] mprj.wbs_adr_i[15] (1.747:1.747:1.747) (0.964:0.964:0.964))
- (INTERCONNECT wbs_adr_i[16] mprj.wbs_adr_i[16] (3.247:3.247:3.247) (1.788:1.788:1.788))
- (INTERCONNECT wbs_adr_i[17] mprj.wbs_adr_i[17] (3.020:3.020:3.020) (1.663:1.663:1.663))
- (INTERCONNECT wbs_adr_i[18] mprj.wbs_adr_i[18] (2.607:2.607:2.607) (1.437:1.437:1.437))
- (INTERCONNECT wbs_adr_i[19] mprj.wbs_adr_i[19] (1.151:1.151:1.151) (0.635:0.635:0.635))
- (INTERCONNECT wbs_adr_i[1] mprj.wbs_adr_i[1] (1.767:1.767:1.767) (0.976:0.976:0.976))
- (INTERCONNECT wbs_adr_i[20] mprj.wbs_adr_i[20] (2.704:2.704:2.704) (1.489:1.489:1.489))
- (INTERCONNECT wbs_adr_i[21] mprj.wbs_adr_i[21] (1.384:1.384:1.384) (0.762:0.762:0.762))
- (INTERCONNECT wbs_adr_i[22] mprj.wbs_adr_i[22] (1.226:1.226:1.226) (0.675:0.675:0.675))
- (INTERCONNECT wbs_adr_i[23] mprj.wbs_adr_i[23] (1.340:1.340:1.340) (0.738:0.738:0.738))
- (INTERCONNECT wbs_adr_i[24] mprj.wbs_adr_i[24] (2.734:2.734:2.734) (1.504:1.504:1.504))
- (INTERCONNECT wbs_adr_i[25] mprj.wbs_adr_i[25] (0.840:0.840:0.840) (0.463:0.463:0.463))
- (INTERCONNECT wbs_adr_i[26] mprj.wbs_adr_i[26] (0.930:0.930:0.930) (0.513:0.513:0.513))
- (INTERCONNECT wbs_adr_i[27] mprj.wbs_adr_i[27] (1.070:1.070:1.070) (0.590:0.590:0.590))
- (INTERCONNECT wbs_adr_i[28] mprj.wbs_adr_i[28] (1.522:1.522:1.522) (0.840:0.840:0.840))
- (INTERCONNECT wbs_adr_i[29] mprj.wbs_adr_i[29] (3.800:3.800:3.800) (2.094:2.094:2.094))
- (INTERCONNECT wbs_adr_i[2] mprj.wbs_adr_i[2] (2.721:2.721:2.721) (1.501:1.501:1.501))
- (INTERCONNECT wbs_adr_i[30] mprj.wbs_adr_i[30] (2.806:2.806:2.806) (1.549:1.549:1.549))
- (INTERCONNECT wbs_adr_i[31] mprj.wbs_adr_i[31] (2.082:2.082:2.082) (1.151:1.151:1.151))
- (INTERCONNECT wbs_adr_i[3] mprj.wbs_adr_i[3] (3.360:3.360:3.360) (1.855:1.855:1.855))
- (INTERCONNECT wbs_adr_i[4] mprj.wbs_adr_i[4] (2.586:2.586:2.586) (1.427:1.427:1.427))
- (INTERCONNECT wbs_adr_i[5] mprj.wbs_adr_i[5] (2.031:2.031:2.031) (1.122:1.122:1.122))
- (INTERCONNECT wbs_adr_i[6] mprj.wbs_adr_i[6] (2.897:2.897:2.897) (1.598:1.598:1.598))
- (INTERCONNECT wbs_adr_i[7] mprj.wbs_adr_i[7] (2.724:2.724:2.724) (1.502:1.502:1.502))
- (INTERCONNECT wbs_adr_i[8] mprj.wbs_adr_i[8] (2.434:2.434:2.434) (1.343:1.343:1.343))
- (INTERCONNECT wbs_adr_i[9] mprj.wbs_adr_i[9] (2.086:2.086:2.086) (1.152:1.152:1.152))
- (INTERCONNECT wbs_cyc_i mprj.wbs_cyc_i (2.537:2.537:2.537) (1.401:1.401:1.401))
- (INTERCONNECT wbs_dat_i[0] mprj.wbs_dat_i[0] (3.631:3.631:3.631) (2.004:2.004:2.004))
- (INTERCONNECT wbs_dat_i[10] mprj.wbs_dat_i[10] (1.968:1.968:1.968) (1.086:1.086:1.086))
- (INTERCONNECT wbs_dat_i[11] mprj.wbs_dat_i[11] (2.175:2.175:2.175) (1.200:1.200:1.200))
- (INTERCONNECT wbs_dat_i[12] mprj.wbs_dat_i[12] (1.945:1.945:1.945) (1.073:1.073:1.073))
- (INTERCONNECT wbs_dat_i[13] mprj.wbs_dat_i[13] (1.557:1.557:1.557) (0.859:0.859:0.859))
- (INTERCONNECT wbs_dat_i[14] mprj.wbs_dat_i[14] (1.595:1.595:1.595) (0.881:0.881:0.881))
- (INTERCONNECT wbs_dat_i[15] mprj.wbs_dat_i[15] (2.201:2.201:2.201) (1.216:1.216:1.216))
- (INTERCONNECT wbs_dat_i[16] mprj.wbs_dat_i[16] (1.302:1.302:1.302) (0.718:0.718:0.718))
- (INTERCONNECT wbs_dat_i[17] mprj.wbs_dat_i[17] (2.500:2.500:2.500) (1.378:1.378:1.378))
- (INTERCONNECT wbs_dat_i[18] mprj.wbs_dat_i[18] (1.293:1.293:1.293) (0.714:0.714:0.714))
- (INTERCONNECT wbs_dat_i[19] mprj.wbs_dat_i[19] (1.074:1.074:1.074) (0.593:0.593:0.593))
- (INTERCONNECT wbs_dat_i[1] mprj.wbs_dat_i[1] (2.241:2.241:2.241) (1.238:1.238:1.238))
- (INTERCONNECT wbs_dat_i[20] mprj.wbs_dat_i[20] (1.556:1.556:1.556) (0.858:0.858:0.858))
- (INTERCONNECT wbs_dat_i[21] mprj.wbs_dat_i[21] (1.344:1.344:1.344) (0.741:0.741:0.741))
- (INTERCONNECT wbs_dat_i[22] mprj.wbs_dat_i[22] (1.290:1.290:1.290) (0.710:0.710:0.710))
- (INTERCONNECT wbs_dat_i[23] mprj.wbs_dat_i[23] (1.225:1.225:1.225) (0.675:0.675:0.675))
- (INTERCONNECT wbs_dat_i[24] mprj.wbs_dat_i[24] (0.836:0.836:0.836) (0.461:0.461:0.461))
- (INTERCONNECT wbs_dat_i[25] mprj.wbs_dat_i[25] (2.847:2.847:2.847) (1.567:1.567:1.567))
- (INTERCONNECT wbs_dat_i[26] mprj.wbs_dat_i[26] (1.402:1.402:1.402) (0.772:0.772:0.772))
- (INTERCONNECT wbs_dat_i[27] mprj.wbs_dat_i[27] (1.665:1.665:1.665) (0.919:0.919:0.919))
- (INTERCONNECT wbs_dat_i[28] mprj.wbs_dat_i[28] (1.505:1.505:1.505) (0.831:0.831:0.831))
- (INTERCONNECT wbs_dat_i[29] mprj.wbs_dat_i[29] (1.542:1.542:1.542) (0.851:0.851:0.851))
- (INTERCONNECT wbs_dat_i[2] mprj.wbs_dat_i[2] (1.126:1.126:1.126) (0.622:0.622:0.622))
- (INTERCONNECT wbs_dat_i[30] mprj.wbs_dat_i[30] (2.828:2.828:2.828) (1.557:1.557:1.557))
- (INTERCONNECT wbs_dat_i[31] mprj.wbs_dat_i[31] (2.725:2.725:2.725) (1.502:1.502:1.502))
- (INTERCONNECT wbs_dat_i[3] mprj.wbs_dat_i[3] (3.188:3.188:3.188) (1.759:1.759:1.759))
- (INTERCONNECT wbs_dat_i[4] mprj.wbs_dat_i[4] (2.926:2.926:2.926) (1.614:1.614:1.614))
- (INTERCONNECT wbs_dat_i[5] mprj.wbs_dat_i[5] (2.664:2.664:2.664) (1.470:1.470:1.470))
- (INTERCONNECT wbs_dat_i[6] mprj.wbs_dat_i[6] (2.037:2.037:2.037) (1.125:1.125:1.125))
- (INTERCONNECT wbs_dat_i[7] mprj.wbs_dat_i[7] (2.524:2.524:2.524) (1.392:1.392:1.392))
- (INTERCONNECT wbs_dat_i[8] mprj.wbs_dat_i[8] (1.785:1.785:1.785) (0.986:0.986:0.986))
- (INTERCONNECT wbs_dat_i[9] mprj.wbs_dat_i[9] (1.780:1.780:1.780) (0.983:0.983:0.983))
- (INTERCONNECT wbs_sel_i[0] mprj.wbs_sel_i[0] (1.277:1.277:1.277) (0.706:0.706:0.706))
- (INTERCONNECT wbs_sel_i[1] mprj.wbs_sel_i[1] (2.470:2.470:2.470) (1.364:1.364:1.364))
- (INTERCONNECT wbs_sel_i[2] mprj.wbs_sel_i[2] (1.919:1.919:1.919) (1.061:1.061:1.061))
- (INTERCONNECT wbs_sel_i[3] mprj.wbs_sel_i[3] (2.956:2.956:2.956) (1.631:1.631:1.631))
- (INTERCONNECT wbs_stb_i mprj.wbs_stb_i (2.056:2.056:2.056) (1.136:1.136:1.136))
- (INTERCONNECT wbs_we_i mprj.wbs_we_i (2.122:2.122:2.122) (1.173:1.173:1.173))
- (INTERCONNECT mprj.io_oeb[0] io_oeb[0] (0.399:0.399:0.399))
- (INTERCONNECT mprj.io_oeb[10] io_oeb[10] (0.104:0.104:0.104))
- (INTERCONNECT mprj.io_oeb[11] io_oeb[11] (0.114:0.114:0.114))
- (INTERCONNECT mprj.io_oeb[12] io_oeb[12] (0.135:0.135:0.135))
- (INTERCONNECT mprj.io_oeb[13] io_oeb[13] (0.134:0.134:0.134))
- (INTERCONNECT mprj.io_oeb[14] io_oeb[14] (0.147:0.147:0.147))
- (INTERCONNECT mprj.io_oeb[15] io_oeb[15] (0.288:0.288:0.288))
- (INTERCONNECT mprj.io_oeb[16] io_oeb[16] (0.232:0.232:0.232))
- (INTERCONNECT mprj.io_oeb[17] io_oeb[17] (0.092:0.092:0.092))
- (INTERCONNECT mprj.io_oeb[18] io_oeb[18] (0.074:0.074:0.074))
- (INTERCONNECT mprj.io_oeb[19] io_oeb[19] (0.060:0.060:0.060))
- (INTERCONNECT mprj.io_oeb[1] io_oeb[1] (0.266:0.266:0.266))
- (INTERCONNECT mprj.io_oeb[20] io_oeb[20] (0.044:0.044:0.044))
- (INTERCONNECT mprj.io_oeb[21] io_oeb[21] (0.067:0.067:0.067))
- (INTERCONNECT mprj.io_oeb[22] io_oeb[22] (0.076:0.076:0.076))
- (INTERCONNECT mprj.io_oeb[23] io_oeb[23] (0.094:0.094:0.094))
- (INTERCONNECT mprj.io_oeb[24] io_oeb[24] (0.085:0.085:0.085))
- (INTERCONNECT mprj.io_oeb[25] io_oeb[25] (0.076:0.076:0.076))
- (INTERCONNECT mprj.io_oeb[26] io_oeb[26] (0.284:0.284:0.284))
- (INTERCONNECT mprj.io_oeb[27] io_oeb[27] (0.242:0.242:0.242))
- (INTERCONNECT mprj.io_oeb[28] io_oeb[28] (0.051:0.051:0.051))
- (INTERCONNECT mprj.io_oeb[29] io_oeb[29] (0.043:0.043:0.043))
- (INTERCONNECT mprj.io_oeb[2] io_oeb[2] (0.306:0.306:0.306))
- (INTERCONNECT mprj.io_oeb[30] io_oeb[30] (0.148:0.148:0.148))
- (INTERCONNECT mprj.io_oeb[31] io_oeb[31] (0.055:0.055:0.055))
- (INTERCONNECT mprj.io_oeb[32] io_oeb[32] (0.176:0.176:0.176))
- (INTERCONNECT mprj.io_oeb[33] io_oeb[33] (0.183:0.183:0.183))
- (INTERCONNECT mprj.io_oeb[34] io_oeb[34] (0.161:0.161:0.161))
- (INTERCONNECT mprj.io_oeb[35] io_oeb[35] (0.147:0.147:0.147))
- (INTERCONNECT mprj.io_oeb[36] io_oeb[36] (0.234:0.234:0.234))
- (INTERCONNECT mprj.io_oeb[37] io_oeb[37] (0.246:0.246:0.246))
- (INTERCONNECT mprj.io_oeb[3] io_oeb[3] (0.255:0.255:0.255))
- (INTERCONNECT mprj.io_oeb[4] io_oeb[4] (0.161:0.161:0.161))
- (INTERCONNECT mprj.io_oeb[5] io_oeb[5] (0.116:0.116:0.116))
- (INTERCONNECT mprj.io_oeb[6] io_oeb[6] (0.151:0.151:0.151))
- (INTERCONNECT mprj.io_oeb[7] io_oeb[7] (0.177:0.177:0.177))
- (INTERCONNECT mprj.io_oeb[8] io_oeb[8] (0.084:0.084:0.084))
- (INTERCONNECT mprj.io_oeb[9] io_oeb[9] (0.094:0.094:0.094))
- (INTERCONNECT mprj.io_out[0] io_out[0] (0.406:0.406:0.406))
- (INTERCONNECT mprj.io_out[10] io_out[10] (0.099:0.099:0.099))
- (INTERCONNECT mprj.io_out[11] io_out[11] (0.110:0.110:0.110))
- (INTERCONNECT mprj.io_out[12] io_out[12] (0.119:0.119:0.119))
- (INTERCONNECT mprj.io_out[13] io_out[13] (0.129:0.129:0.129))
- (INTERCONNECT mprj.io_out[14] io_out[14] (0.167:0.167:0.167))
- (INTERCONNECT mprj.io_out[15] io_out[15] (0.244:0.244:0.244))
- (INTERCONNECT mprj.io_out[16] io_out[16] (0.117:0.117:0.117))
- (INTERCONNECT mprj.io_out[17] io_out[17] (0.171:0.171:0.171))
- (INTERCONNECT mprj.io_out[18] io_out[18] (0.133:0.133:0.133))
- (INTERCONNECT mprj.io_out[19] io_out[19] (0.078:0.078:0.078))
- (INTERCONNECT mprj.io_out[1] io_out[1] (0.194:0.194:0.194))
- (INTERCONNECT mprj.io_out[20] io_out[20] (0.048:0.048:0.048))
- (INTERCONNECT mprj.io_out[21] io_out[21] (0.059:0.059:0.059))
- (INTERCONNECT mprj.io_out[22] io_out[22] (0.092:0.092:0.092))
- (INTERCONNECT mprj.io_out[23] io_out[23] (0.105:0.105:0.105))
- (INTERCONNECT mprj.io_out[24] io_out[24] (0.095:0.095:0.095))
- (INTERCONNECT mprj.io_out[25] io_out[25] (0.245:0.245:0.245))
- (INTERCONNECT mprj.io_out[26] io_out[26] (0.077:0.077:0.077))
- (INTERCONNECT mprj.io_out[27] io_out[27] (0.063:0.063:0.063))
- (INTERCONNECT mprj.io_out[28] io_out[28] (0.055:0.055:0.055))
- (INTERCONNECT mprj.io_out[29] io_out[29] (0.204:0.204:0.204))
- (INTERCONNECT mprj.io_out[2] io_out[2] (0.210:0.210:0.210))
- (INTERCONNECT mprj.io_out[30] io_out[30] (0.039:0.039:0.039))
- (INTERCONNECT mprj.io_out[31] io_out[31] (0.049:0.049:0.049))
- (INTERCONNECT mprj.io_out[32] io_out[32] (0.085:0.085:0.085))
- (INTERCONNECT mprj.io_out[33] io_out[33] (0.118:0.118:0.118))
- (INTERCONNECT mprj.io_out[34] io_out[34] (0.147:0.147:0.147))
- (INTERCONNECT mprj.io_out[35] io_out[35] (0.160:0.160:0.160))
- (INTERCONNECT mprj.io_out[36] io_out[36] (0.125:0.125:0.125))
- (INTERCONNECT mprj.io_out[37] io_out[37] (0.103:0.103:0.103))
- (INTERCONNECT mprj.io_out[3] io_out[3] (0.191:0.191:0.191))
- (INTERCONNECT mprj.io_out[4] io_out[4] (0.136:0.136:0.136))
- (INTERCONNECT mprj.io_out[5] io_out[5] (0.159:0.159:0.159))
- (INTERCONNECT mprj.io_out[6] io_out[6] (0.135:0.135:0.135))
- (INTERCONNECT mprj.io_out[7] io_out[7] (0.126:0.126:0.126))
- (INTERCONNECT mprj.io_out[8] io_out[8] (0.080:0.080:0.080))
- (INTERCONNECT mprj.io_out[9] io_out[9] (0.091:0.091:0.091))
- (INTERCONNECT mprj.irq[0] user_irq[0] (0.160:0.160:0.160))
- (INTERCONNECT mprj.irq[1] user_irq[1] (0.164:0.164:0.164))
- (INTERCONNECT mprj.irq[2] user_irq[2] (0.096:0.096:0.096))
- (INTERCONNECT mprj.la_data_out[0] la_data_out[0] (0.047:0.047:0.047))
- (INTERCONNECT mprj.la_data_out[10] la_data_out[10] (0.100:0.100:0.100))
- (INTERCONNECT mprj.la_data_out[11] la_data_out[11] (0.080:0.080:0.080))
- (INTERCONNECT mprj.la_data_out[12] la_data_out[12] (0.080:0.080:0.080))
- (INTERCONNECT mprj.la_data_out[13] la_data_out[13] (0.100:0.100:0.100))
- (INTERCONNECT mprj.la_data_out[14] la_data_out[14] (0.064:0.064:0.064))
- (INTERCONNECT mprj.la_data_out[15] la_data_out[15] (0.080:0.080:0.080))
- (INTERCONNECT mprj.la_data_out[16] la_data_out[16] (0.045:0.045:0.045))
- (INTERCONNECT mprj.la_data_out[17] la_data_out[17] (0.129:0.129:0.129))
- (INTERCONNECT mprj.la_data_out[18] la_data_out[18] (0.073:0.073:0.073))
- (INTERCONNECT mprj.la_data_out[19] la_data_out[19] (0.051:0.051:0.051))
- (INTERCONNECT mprj.la_data_out[1] la_data_out[1] (0.061:0.061:0.061))
- (INTERCONNECT mprj.la_data_out[20] la_data_out[20] (0.131:0.131:0.131))
- (INTERCONNECT mprj.la_data_out[21] la_data_out[21] (0.045:0.045:0.045))
- (INTERCONNECT mprj.la_data_out[22] la_data_out[22] (0.054:0.054:0.054))
- (INTERCONNECT mprj.la_data_out[23] la_data_out[23] (0.062:0.062:0.062))
- (INTERCONNECT mprj.la_data_out[24] la_data_out[24] (0.076:0.076:0.076))
- (INTERCONNECT mprj.la_data_out[25] la_data_out[25] (0.075:0.075:0.075))
- (INTERCONNECT mprj.la_data_out[26] la_data_out[26] (0.095:0.095:0.095))
- (INTERCONNECT mprj.la_data_out[27] la_data_out[27] (0.071:0.071:0.071))
- (INTERCONNECT mprj.la_data_out[28] la_data_out[28] (0.102:0.102:0.102))
- (INTERCONNECT mprj.la_data_out[29] la_data_out[29] (0.072:0.072:0.072))
- (INTERCONNECT mprj.la_data_out[2] la_data_out[2] (0.038:0.038:0.038))
- (INTERCONNECT mprj.la_data_out[30] la_data_out[30] (0.102:0.102:0.102))
- (INTERCONNECT mprj.la_data_out[31] la_data_out[31] (0.080:0.080:0.080))
- (INTERCONNECT mprj.la_data_out[32] la_data_out[32] (0.101:0.101:0.101))
- (INTERCONNECT mprj.la_data_out[33] la_data_out[33] (0.107:0.107:0.107))
- (INTERCONNECT mprj.la_data_out[34] la_data_out[34] (0.119:0.119:0.119))
- (INTERCONNECT mprj.la_data_out[35] la_data_out[35] (0.119:0.119:0.119))
- (INTERCONNECT mprj.la_data_out[36] la_data_out[36] (0.072:0.072:0.072))
- (INTERCONNECT mprj.la_data_out[37] la_data_out[37] (0.095:0.095:0.095))
- (INTERCONNECT mprj.la_data_out[38] la_data_out[38] (0.142:0.142:0.142))
- (INTERCONNECT mprj.la_data_out[39] la_data_out[39] (0.137:0.137:0.137))
- (INTERCONNECT mprj.la_data_out[3] la_data_out[3] (0.055:0.055:0.055))
- (INTERCONNECT mprj.la_data_out[40] la_data_out[40] (0.104:0.104:0.104))
- (INTERCONNECT mprj.la_data_out[41] la_data_out[41] (0.141:0.141:0.141))
- (INTERCONNECT mprj.la_data_out[42] la_data_out[42] (0.156:0.156:0.156))
- (INTERCONNECT mprj.la_data_out[43] la_data_out[43] (0.160:0.160:0.160))
- (INTERCONNECT mprj.la_data_out[44] la_data_out[44] (0.135:0.135:0.135))
- (INTERCONNECT mprj.la_data_out[45] la_data_out[45] (0.072:0.072:0.072))
- (INTERCONNECT mprj.la_data_out[46] la_data_out[46] (0.155:0.155:0.155))
- (INTERCONNECT mprj.la_data_out[47] la_data_out[47] (0.142:0.142:0.142))
- (INTERCONNECT mprj.la_data_out[48] la_data_out[48] (0.184:0.184:0.184))
- (INTERCONNECT mprj.la_data_out[49] la_data_out[49] (0.126:0.126:0.126))
- (INTERCONNECT mprj.la_data_out[4] la_data_out[4] (0.087:0.087:0.087))
- (INTERCONNECT mprj.la_data_out[50] la_data_out[50] (0.198:0.198:0.198))
- (INTERCONNECT mprj.la_data_out[51] la_data_out[51] (0.205:0.205:0.205))
- (INTERCONNECT mprj.la_data_out[52] la_data_out[52] (0.141:0.141:0.141))
- (INTERCONNECT mprj.la_data_out[53] la_data_out[53] (0.144:0.144:0.144))
- (INTERCONNECT mprj.la_data_out[54] la_data_out[54] (0.126:0.126:0.126))
- (INTERCONNECT mprj.la_data_out[55] la_data_out[55] (0.220:0.220:0.220))
- (INTERCONNECT mprj.la_data_out[56] la_data_out[56] (0.238:0.238:0.238))
- (INTERCONNECT mprj.la_data_out[57] la_data_out[57] (0.126:0.126:0.126))
- (INTERCONNECT mprj.la_data_out[58] la_data_out[58] (0.158:0.158:0.158))
- (INTERCONNECT mprj.la_data_out[59] la_data_out[59] (0.151:0.151:0.151))
- (INTERCONNECT mprj.la_data_out[5] la_data_out[5] (0.083:0.083:0.083))
- (INTERCONNECT mprj.la_data_out[60] la_data_out[60] (0.247:0.247:0.247))
- (INTERCONNECT mprj.la_data_out[61] la_data_out[61] (0.105:0.105:0.105))
- (INTERCONNECT mprj.la_data_out[62] la_data_out[62] (0.165:0.165:0.165))
- (INTERCONNECT mprj.la_data_out[63] la_data_out[63] (0.172:0.172:0.172))
- (INTERCONNECT mprj.la_data_out[6] la_data_out[6] (0.047:0.047:0.047))
- (INTERCONNECT mprj.la_data_out[7] la_data_out[7] (0.066:0.066:0.066))
- (INTERCONNECT mprj.la_data_out[8] la_data_out[8] (0.059:0.059:0.059))
- (INTERCONNECT mprj.la_data_out[9] la_data_out[9] (0.065:0.065:0.065))
- (INTERCONNECT mprj.wbs_ack_o wbs_ack_o (0.037:0.037:0.037))
- (INTERCONNECT mprj.wbs_dat_o[0] wbs_dat_o[0] (0.035:0.035:0.035))
- (INTERCONNECT mprj.wbs_dat_o[10] wbs_dat_o[10] (0.031:0.031:0.031))
- (INTERCONNECT mprj.wbs_dat_o[11] wbs_dat_o[11] (0.047:0.047:0.047))
- (INTERCONNECT mprj.wbs_dat_o[12] wbs_dat_o[12] (0.031:0.031:0.031))
- (INTERCONNECT mprj.wbs_dat_o[13] wbs_dat_o[13] (0.026:0.026:0.026))
- (INTERCONNECT mprj.wbs_dat_o[14] wbs_dat_o[14] (0.040:0.040:0.040))
- (INTERCONNECT mprj.wbs_dat_o[15] wbs_dat_o[15] (0.027:0.027:0.027))
- (INTERCONNECT mprj.wbs_dat_o[16] wbs_dat_o[16] (0.033:0.033:0.033))
- (INTERCONNECT mprj.wbs_dat_o[17] wbs_dat_o[17] (0.030:0.030:0.030))
- (INTERCONNECT mprj.wbs_dat_o[18] wbs_dat_o[18] (0.038:0.038:0.038))
- (INTERCONNECT mprj.wbs_dat_o[19] wbs_dat_o[19] (0.027:0.027:0.027))
- (INTERCONNECT mprj.wbs_dat_o[1] wbs_dat_o[1] (0.059:0.059:0.059))
- (INTERCONNECT mprj.wbs_dat_o[20] wbs_dat_o[20] (0.038:0.038:0.038))
- (INTERCONNECT mprj.wbs_dat_o[21] wbs_dat_o[21] (0.031:0.031:0.031))
- (INTERCONNECT mprj.wbs_dat_o[22] wbs_dat_o[22] (0.050:0.050:0.050))
- (INTERCONNECT mprj.wbs_dat_o[23] wbs_dat_o[23] (0.048:0.048:0.048))
- (INTERCONNECT mprj.wbs_dat_o[24] wbs_dat_o[24] (0.049:0.049:0.049))
- (INTERCONNECT mprj.wbs_dat_o[25] wbs_dat_o[25] (0.059:0.059:0.059))
- (INTERCONNECT mprj.wbs_dat_o[26] wbs_dat_o[26] (0.047:0.047:0.047))
- (INTERCONNECT mprj.wbs_dat_o[27] wbs_dat_o[27] (0.038:0.038:0.038))
- (INTERCONNECT mprj.wbs_dat_o[28] wbs_dat_o[28] (0.056:0.056:0.056))
- (INTERCONNECT mprj.wbs_dat_o[29] wbs_dat_o[29] (0.050:0.050:0.050))
- (INTERCONNECT mprj.wbs_dat_o[2] wbs_dat_o[2] (0.052:0.052:0.052))
- (INTERCONNECT mprj.wbs_dat_o[30] wbs_dat_o[30] (0.044:0.044:0.044))
- (INTERCONNECT mprj.wbs_dat_o[31] wbs_dat_o[31] (0.059:0.059:0.059))
- (INTERCONNECT mprj.wbs_dat_o[3] wbs_dat_o[3] (0.052:0.052:0.052))
- (INTERCONNECT mprj.wbs_dat_o[4] wbs_dat_o[4] (0.047:0.047:0.047))
- (INTERCONNECT mprj.wbs_dat_o[5] wbs_dat_o[5] (0.034:0.034:0.034))
- (INTERCONNECT mprj.wbs_dat_o[6] wbs_dat_o[6] (0.042:0.042:0.042))
- (INTERCONNECT mprj.wbs_dat_o[7] wbs_dat_o[7] (0.059:0.059:0.059))
- (INTERCONNECT mprj.wbs_dat_o[8] wbs_dat_o[8] (0.037:0.037:0.037))
- (INTERCONNECT mprj.wbs_dat_o[9] wbs_dat_o[9] (0.061:0.061:0.061))
+ (INTERCONNECT io_in[0] wrapped_vga_clock.io_in[0] (2.678:2.678:2.678) (1.488:1.488:1.488))
+ (INTERCONNECT io_in[10] wrapped_vga_clock.io_in[10] (2.697:2.697:2.697) (1.501:1.501:1.501))
+ (INTERCONNECT io_in[11] wrapped_vga_clock.io_in[11] (2.904:2.904:2.904) (1.618:1.618:1.618))
+ (INTERCONNECT io_in[12] wrapped_vga_clock.io_in[12] (3.636:3.636:3.636) (2.030:2.030:2.030))
+ (INTERCONNECT io_in[13] wrapped_vga_clock.io_in[13] (3.055:3.055:3.055) (1.703:1.703:1.703))
+ (INTERCONNECT io_in[14] wrapped_vga_clock.io_in[14] (3.291:3.291:3.291) (1.836:1.836:1.836))
+ (INTERCONNECT io_in[15] wrapped_vga_clock.io_in[15] (4.225:4.225:4.225) (2.362:2.362:2.362))
+ (INTERCONNECT io_in[16] wrapped_vga_clock.io_in[16] (10.791:10.791:10.791) (5.953:5.953:5.953))
+ (INTERCONNECT io_in[17] wrapped_vga_clock.io_in[17] (5.887:5.887:5.887) (3.268:3.268:3.268))
+ (INTERCONNECT io_in[18] wrapped_vga_clock.io_in[18] (4.298:4.298:4.298) (2.395:2.395:2.395))
+ (INTERCONNECT io_in[19] wrapped_vga_clock.io_in[19] (3.352:3.352:3.352) (1.866:1.866:1.866))
+ (INTERCONNECT io_in[1] wrapped_vga_clock.io_in[1] (2.497:2.497:2.497) (1.387:1.387:1.387))
+ (INTERCONNECT io_in[20] wrapped_vga_clock.io_in[20] (2.227:2.227:2.227) (1.238:1.238:1.238))
+ (INTERCONNECT io_in[21] wrapped_vga_clock.io_in[21] (1.959:1.959:1.959) (1.087:1.087:1.087))
+ (INTERCONNECT io_in[22] wrapped_vga_clock.io_in[22] (2.078:2.078:2.078) (1.153:1.153:1.153))
+ (INTERCONNECT io_in[23] wrapped_vga_clock.io_in[23] (1.918:1.918:1.918) (1.065:1.065:1.065))
+ (INTERCONNECT io_in[24] wrapped_vga_clock.io_in[24] (5.314:5.314:5.314) (2.942:2.942:2.942))
+ (INTERCONNECT io_in[25] wrapped_vga_clock.io_in[25] (2.126:2.126:2.126) (1.181:1.181:1.181))
+ (INTERCONNECT io_in[26] wrapped_vga_clock.io_in[26] (1.716:1.716:1.716) (0.951:0.951:0.951))
+ (INTERCONNECT io_in[27] wrapped_vga_clock.io_in[27] (1.692:1.692:1.692) (0.937:0.937:0.937))
+ (INTERCONNECT io_in[28] wrapped_vga_clock.io_in[28] (4.263:4.263:4.263) (2.358:2.358:2.358))
+ (INTERCONNECT io_in[29] wrapped_vga_clock.io_in[29] (3.300:3.300:3.300) (1.827:1.827:1.827))
+ (INTERCONNECT io_in[2] wrapped_vga_clock.io_in[2] (2.157:2.157:2.157) (1.198:1.198:1.198))
+ (INTERCONNECT io_in[30] wrapped_vga_clock.io_in[30] (1.057:1.057:1.057) (0.584:0.584:0.584))
+ (INTERCONNECT io_in[31] wrapped_vga_clock.io_in[31] (2.248:2.248:2.248) (1.242:1.242:1.242))
+ (INTERCONNECT io_in[32] wrapped_vga_clock.io_in[32] (1.618:1.618:1.618) (0.894:0.894:0.894))
+ (INTERCONNECT io_in[33] wrapped_vga_clock.io_in[33] (0.545:0.545:0.545) (0.300:0.300:0.300))
+ (INTERCONNECT io_in[34] wrapped_vga_clock.io_in[34] (0.552:0.552:0.552) (0.304:0.304:0.304))
+ (INTERCONNECT io_in[35] wrapped_vga_clock.io_in[35] (0.784:0.784:0.784) (0.433:0.433:0.433))
+ (INTERCONNECT io_in[36] wrapped_vga_clock.io_in[36] (1.700:1.700:1.700) (0.940:0.940:0.940))
+ (INTERCONNECT io_in[37] wrapped_vga_clock.io_in[37] (1.277:1.277:1.277) (0.706:0.706:0.706))
+ (INTERCONNECT io_in[3] wrapped_vga_clock.io_in[3] (4.665:4.665:4.665) (2.589:2.589:2.589))
+ (INTERCONNECT io_in[4] wrapped_vga_clock.io_in[4] (1.816:1.816:1.816) (1.007:1.007:1.007))
+ (INTERCONNECT io_in[5] wrapped_vga_clock.io_in[5] (1.727:1.727:1.727) (0.959:0.959:0.959))
+ (INTERCONNECT io_in[6] wrapped_vga_clock.io_in[6] (2.718:2.718:2.718) (1.508:1.508:1.508))
+ (INTERCONNECT io_in[7] wrapped_vga_clock.io_in[7] (2.117:2.117:2.117) (1.175:1.175:1.175))
+ (INTERCONNECT io_in[8] wrapped_vga_clock.io_in[8] (2.576:2.576:2.576) (1.431:1.431:1.431))
+ (INTERCONNECT io_in[9] wrapped_vga_clock.io_in[9] (2.403:2.403:2.403) (1.336:1.336:1.336))
+ (INTERCONNECT wb_clk_i wrapped_vga_clock.wb_clk_i (1.415:1.415:1.415) (0.783:0.783:0.783))
+ (INTERCONNECT wb_rst_i wrapped_vga_clock.wb_rst_i (1.850:1.850:1.850) (1.025:1.025:1.025))
+ (INTERCONNECT wrapped_vga_clock.io_oeb[0] io_oeb[0] (0.124:0.124:0.124))
+ (INTERCONNECT wrapped_vga_clock.io_oeb[10] io_oeb[10] (0.119:0.119:0.119))
+ (INTERCONNECT wrapped_vga_clock.io_oeb[11] io_oeb[11] (0.166:0.166:0.166))
+ (INTERCONNECT wrapped_vga_clock.io_oeb[12] io_oeb[12] (0.193:0.193:0.193))
+ (INTERCONNECT wrapped_vga_clock.io_oeb[13] io_oeb[13] (0.174:0.174:0.174))
+ (INTERCONNECT wrapped_vga_clock.io_oeb[14] io_oeb[14] (0.213:0.213:0.213))
+ (INTERCONNECT wrapped_vga_clock.io_oeb[15] io_oeb[15] (0.260:0.260:0.260))
+ (INTERCONNECT wrapped_vga_clock.io_oeb[16] io_oeb[16] (0.148:0.148:0.148))
+ (INTERCONNECT wrapped_vga_clock.io_oeb[17] io_oeb[17] (0.140:0.140:0.140))
+ (INTERCONNECT wrapped_vga_clock.io_oeb[18] io_oeb[18] (0.126:0.126:0.126))
+ (INTERCONNECT wrapped_vga_clock.io_oeb[19] io_oeb[19] (0.099:0.099:0.099))
+ (INTERCONNECT wrapped_vga_clock.io_oeb[1] io_oeb[1] (0.118:0.118:0.118))
+ (INTERCONNECT wrapped_vga_clock.io_oeb[20] io_oeb[20] (0.084:0.084:0.084))
+ (INTERCONNECT wrapped_vga_clock.io_oeb[21] io_oeb[21] (0.058:0.058:0.058))
+ (INTERCONNECT wrapped_vga_clock.io_oeb[22] io_oeb[22] (0.099:0.099:0.099))
+ (INTERCONNECT wrapped_vga_clock.io_oeb[23] io_oeb[23] (0.106:0.106:0.106))
+ (INTERCONNECT wrapped_vga_clock.io_oeb[24] io_oeb[24] (0.106:0.106:0.106))
+ (INTERCONNECT wrapped_vga_clock.io_oeb[25] io_oeb[25] (0.077:0.077:0.077))
+ (INTERCONNECT wrapped_vga_clock.io_oeb[26] io_oeb[26] (0.116:0.116:0.116))
+ (INTERCONNECT wrapped_vga_clock.io_oeb[27] io_oeb[27] (0.060:0.060:0.060))
+ (INTERCONNECT wrapped_vga_clock.io_oeb[28] io_oeb[28] (0.069:0.069:0.069))
+ (INTERCONNECT wrapped_vga_clock.io_oeb[29] io_oeb[29] (0.089:0.089:0.089))
+ (INTERCONNECT wrapped_vga_clock.io_oeb[2] io_oeb[2] (0.104:0.104:0.104))
+ (INTERCONNECT wrapped_vga_clock.io_oeb[30] io_oeb[30] (0.025:0.025:0.025))
+ (INTERCONNECT wrapped_vga_clock.io_oeb[31] io_oeb[31] (0.047:0.047:0.047))
+ (INTERCONNECT wrapped_vga_clock.io_oeb[32] io_oeb[32] (0.027:0.027:0.027))
+ (INTERCONNECT wrapped_vga_clock.io_oeb[33] io_oeb[33] (0.018:0.018:0.018))
+ (INTERCONNECT wrapped_vga_clock.io_oeb[34] io_oeb[34] (0.042:0.042:0.042))
+ (INTERCONNECT wrapped_vga_clock.io_oeb[35] io_oeb[35] (0.027:0.027:0.027))
+ (INTERCONNECT wrapped_vga_clock.io_oeb[36] io_oeb[36] (0.040:0.040:0.040))
+ (INTERCONNECT wrapped_vga_clock.io_oeb[37] io_oeb[37] (0.050:0.050:0.050))
+ (INTERCONNECT wrapped_vga_clock.io_oeb[3] io_oeb[3] (0.101:0.101:0.101))
+ (INTERCONNECT wrapped_vga_clock.io_oeb[4] io_oeb[4] (0.190:0.190:0.190))
+ (INTERCONNECT wrapped_vga_clock.io_oeb[5] io_oeb[5] (0.165:0.165:0.165))
+ (INTERCONNECT wrapped_vga_clock.io_oeb[6] io_oeb[6] (0.115:0.115:0.115))
+ (INTERCONNECT wrapped_vga_clock.io_oeb[7] io_oeb[7] (0.214:0.214:0.214))
+ (INTERCONNECT wrapped_vga_clock.io_oeb[8] io_oeb[8] (0.124:0.124:0.124))
+ (INTERCONNECT wrapped_vga_clock.io_oeb[9] io_oeb[9] (0.115:0.115:0.115))
+ (INTERCONNECT wrapped_vga_clock.io_out[0] io_out[0] (0.111:0.111:0.111))
+ (INTERCONNECT wrapped_vga_clock.io_out[10] io_out[10] (0.175:0.175:0.175))
+ (INTERCONNECT wrapped_vga_clock.io_out[11] io_out[11] (0.530:0.530:0.530))
+ (INTERCONNECT wrapped_vga_clock.io_out[12] io_out[12] (0.157:0.157:0.157))
+ (INTERCONNECT wrapped_vga_clock.io_out[13] io_out[13] (0.187:0.187:0.187))
+ (INTERCONNECT wrapped_vga_clock.io_out[14] io_out[14] (0.217:0.217:0.217))
+ (INTERCONNECT wrapped_vga_clock.io_out[15] io_out[15] (0.169:0.169:0.169))
+ (INTERCONNECT wrapped_vga_clock.io_out[16] io_out[16] (0.173:0.173:0.173))
+ (INTERCONNECT wrapped_vga_clock.io_out[17] io_out[17] (0.161:0.161:0.161))
+ (INTERCONNECT wrapped_vga_clock.io_out[18] io_out[18] (0.136:0.136:0.136))
+ (INTERCONNECT wrapped_vga_clock.io_out[19] io_out[19] (0.219:0.219:0.219))
+ (INTERCONNECT wrapped_vga_clock.io_out[1] io_out[1] (0.118:0.118:0.118))
+ (INTERCONNECT wrapped_vga_clock.io_out[20] io_out[20] (0.104:0.104:0.104))
+ (INTERCONNECT wrapped_vga_clock.io_out[21] io_out[21] (0.115:0.115:0.115))
+ (INTERCONNECT wrapped_vga_clock.io_out[22] io_out[22] (0.063:0.063:0.063))
+ (INTERCONNECT wrapped_vga_clock.io_out[23] io_out[23] (0.085:0.085:0.085))
+ (INTERCONNECT wrapped_vga_clock.io_out[24] io_out[24] (0.100:0.100:0.100))
+ (INTERCONNECT wrapped_vga_clock.io_out[25] io_out[25] (0.081:0.081:0.081))
+ (INTERCONNECT wrapped_vga_clock.io_out[26] io_out[26] (0.077:0.077:0.077))
+ (INTERCONNECT wrapped_vga_clock.io_out[27] io_out[27] (0.065:0.065:0.065))
+ (INTERCONNECT wrapped_vga_clock.io_out[28] io_out[28] (0.051:0.051:0.051))
+ (INTERCONNECT wrapped_vga_clock.io_out[29] io_out[29] (0.041:0.041:0.041))
+ (INTERCONNECT wrapped_vga_clock.io_out[2] io_out[2] (0.093:0.093:0.093))
+ (INTERCONNECT wrapped_vga_clock.io_out[30] io_out[30] (0.047:0.047:0.047))
+ (INTERCONNECT wrapped_vga_clock.io_out[31] io_out[31] (0.062:0.062:0.062))
+ (INTERCONNECT wrapped_vga_clock.io_out[32] io_out[32] (0.014:0.014:0.014))
+ (INTERCONNECT wrapped_vga_clock.io_out[33] io_out[33] (0.013:0.013:0.013))
+ (INTERCONNECT wrapped_vga_clock.io_out[34] io_out[34] (0.017:0.017:0.017))
+ (INTERCONNECT wrapped_vga_clock.io_out[35] io_out[35] (0.024:0.024:0.024))
+ (INTERCONNECT wrapped_vga_clock.io_out[36] io_out[36] (0.031:0.031:0.031))
+ (INTERCONNECT wrapped_vga_clock.io_out[37] io_out[37] (0.059:0.059:0.059))
+ (INTERCONNECT wrapped_vga_clock.io_out[3] io_out[3] (0.078:0.078:0.078))
+ (INTERCONNECT wrapped_vga_clock.io_out[4] io_out[4] (0.155:0.155:0.155))
+ (INTERCONNECT wrapped_vga_clock.io_out[5] io_out[5] (0.109:0.109:0.109))
+ (INTERCONNECT wrapped_vga_clock.io_out[6] io_out[6] (0.093:0.093:0.093))
+ (INTERCONNECT wrapped_vga_clock.io_out[7] io_out[7] (0.102:0.102:0.102))
+ (INTERCONNECT wrapped_vga_clock.io_out[8] io_out[8] (0.133:0.133:0.133))
+ (INTERCONNECT wrapped_vga_clock.io_out[9] io_out[9] (0.142:0.142:0.142))
)
)
)
diff --git a/signoff/user_proj_example/metrics.csv b/signoff/user_proj_example/metrics.csv
index 2a48d38..e79acb8 100644
--- a/signoff/user_proj_example/metrics.csv
+++ b/signoff/user_proj_example/metrics.csv
@@ -1,2 +1,2 @@
design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,CoreArea_um^2,power_slowest_internal_uW,power_slowest_switching_uW,power_slowest_leakage_uW,power_typical_internal_uW,power_typical_switching_uW,power_typical_leakage_uW,power_fastest_internal_uW,power_fastest_switching_uW,power_fastest_leakage_uW,critical_path_ns,suggested_clock_period,suggested_clock_frequency,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GRT_ADJUSTMENT,STD_CELL_LIBRARY,DIODE_INSERTION_STRATEGY
-/home/marwan/caravel_user_project-gf180mcu/openlane/user_proj_example,user_proj_example,22_11_21_08_16,flow completed,0h2m56s0ms,0h1m26s0ms,604.1666666666666,2.16,241.66666666666666,2.34,655.25,522,0,0,0,0,0,0,0,-1,0,-1,-1,100565,6021,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,147541649.0,0.0,6.95,9.44,0.44,-1,5.65,342,957,29,644,0,0,0,378,37,0,14,31,46,17,15,127,169,65,13,290,3236,0,3526,503875.2320000001,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,24.0,41.666666666666664,24.0,AREA 0,4,40,1,153.6,153.18,0.45,0.3,gf180mcu_fd_sc_mcu7t5v0,4
+/home/matt/work/asic-workshop/shuttle8/gf180-vga-clock/openlane/user_proj_example,user_proj_example,22_11_23_10_12,flow completed,0h2m5s0ms,0h0m59s0ms,604.1666666666666,2.16,241.66666666666666,2.34,640.42,522,0,0,0,0,0,0,0,-1,0,-1,-1,100565,6021,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,147541649.0,0.0,6.95,9.44,0.44,-1,5.65,342,957,29,644,0,0,0,378,37,0,14,31,46,17,15,127,169,65,13,290,3236,0,3526,503875.2320000001,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,24.0,41.666666666666664,24.0,AREA 0,4,40,1,153.6,153.18,0.45,0.3,gf180mcu_fd_sc_mcu7t5v0,4
diff --git a/signoff/user_project_wrapper/metrics.csv b/signoff/user_project_wrapper/metrics.csv
index 61428a6..af167e8 100644
--- a/signoff/user_project_wrapper/metrics.csv
+++ b/signoff/user_project_wrapper/metrics.csv
@@ -1,2 +1,2 @@
design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,CoreArea_um^2,power_slowest_internal_uW,power_slowest_switching_uW,power_slowest_leakage_uW,power_typical_internal_uW,power_typical_switching_uW,power_typical_leakage_uW,power_fastest_internal_uW,power_fastest_switching_uW,power_fastest_leakage_uW,critical_path_ns,suggested_clock_period,suggested_clock_frequency,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GRT_ADJUSTMENT,STD_CELL_LIBRARY,DIODE_INSERTION_STRATEGY
-/home/marwan/caravel_user_project-gf180mcu/openlane/user_project_wrapper,user_project_wrapper,22_11_21_08_19,flow completed,0h2m0s0ms,0h0m42s0ms,-2.0,-1,-1,-1,558.56,1,0,0,0,0,0,0,0,-1,0,-1,-1,727742,1241,0.0,-1,0.0,0.0,0.0,0.0,-1,0.0,0.0,0.0,-1,0.0,3.87,3.98,0.0,-1,2.67,18,416,18,416,0,0,0,1,0,0,0,0,0,0,0,0,-1,-1,-1,0,0,0,0,8726110.9824,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,10.0,100.0,10,AREA 0,10,50,1,90,90,0.55,0.3,gf180mcu_fd_sc_mcu7t5v0,0
+/home/matt/work/asic-workshop/shuttle8/gf180-vga-clock/openlane/user_project_wrapper,user_project_wrapper,22_11_23_10_34,flow completed,0h0m48s0ms,0h0m27s0ms,-2.0,-1,-1,-1,544.14,1,0,0,0,0,0,0,0,-1,0,-1,-1,289162,379,0.0,-1,0.0,0.0,0.0,0.0,-1,0.0,0.0,0.0,-1,0.0,1.35,1.65,0.0,-1,1.02,18,416,18,416,0,0,0,1,0,0,0,0,0,0,0,0,-1,-1,-1,0,0,0,0,8726110.9824,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,10.0,100.0,10,AREA 0,10,50,1,90,90,0.55,0.3,gf180mcu_fd_sc_mcu7t5v0,0
diff --git a/spef/multicorner/user_project_wrapper.nom.spef b/spef/multicorner/user_project_wrapper.nom.spef
index c1d9e0e..dd72921 100644
--- a/spef/multicorner/user_project_wrapper.nom.spef
+++ b/spef/multicorner/user_project_wrapper.nom.spef
@@ -430,7 +430,7 @@
*416 wbs_sel_i[3]
*417 wbs_stb_i
*418 wbs_we_i
-*419 mprj
+*419 wrapped_vga_clock
*PORTS
io_in[0] I
@@ -850,11365 +850,2714 @@
wbs_stb_i I
wbs_we_i I
-*D_NET *1 0.256024
+*D_NET *1 0.195403
*CONN
*P io_in[0] I
-*I *419:io_in[0] I *D user_proj_example
+*I *419:io_in[0] I *D wrapped_vga_clock
*CAP
-1 io_in[0] 0.00159288
-2 *419:io_in[0] 0.000159855
-3 *1:14 0.0387637
-4 *1:13 0.0386039
-5 *1:11 0.0806066
-6 *1:10 0.0806066
-7 *1:8 0.00660359
-8 *1:7 0.00819647
-9 *419:io_in[0] *63:27 0.00028598
-10 *419:io_in[0] *69:8 0
-11 *1:14 *66:13 0
-12 *1:14 *101:13 0.000604551
+1 io_in[0] 0.0323536
+2 *419:io_in[0] 0.0298529
+3 *1:10 0.0298529
+4 *1:8 0.0354948
+5 *1:7 0.0354948
+6 *1:5 0.0323536
*RES
-1 io_in[0] *1:7 21.825
-2 *1:7 *1:8 65.97
-3 *1:8 *1:10 4.5
-4 *1:10 *1:11 757.35
-5 *1:11 *1:13 4.5
-6 *1:13 *1:14 386.37
-7 *1:14 *419:io_in[0] 11.07
+1 io_in[0] *1:5 354.825
+2 *1:5 *1:7 4.5
+3 *1:7 *1:8 353.79
+4 *1:8 *1:10 4.5
+5 *1:10 *419:io_in[0] 324.045
*END
-*D_NET *2 0.182426
+*D_NET *2 0.196605
*CONN
*P io_in[10] I
-*I *419:io_in[10] I *D user_proj_example
+*I *419:io_in[10] I *D wrapped_vga_clock
*CAP
-1 io_in[10] 0.000619745
-2 *419:io_in[10] 0.00328993
-3 *2:11 0.0671602
-4 *2:10 0.0638703
-5 *2:8 0.0150246
-6 *2:7 0.0156443
-7 *419:io_in[10] *114:14 0
-8 *2:8 *70:15 0.0065672
-9 *2:8 *110:17 0.0102497
-10 *2:11 *32:11 0
-11 *2:11 *101:10 0
+1 io_in[10] 0.000890476
+2 *419:io_in[10] 0.0614299
+3 *2:10 0.0614299
+4 *2:8 0.0359821
+5 *2:7 0.0368726
*RES
-1 io_in[10] *2:7 10.665
-2 *2:7 *2:8 160.83
+1 io_in[10] *2:7 13.725
+2 *2:7 *2:8 359.19
3 *2:8 *2:10 4.5
-4 *2:10 *2:11 692.91
-5 *2:11 *419:io_in[10] 35.235
+4 *2:10 *419:io_in[10] 669.645
*END
-*D_NET *3 0.178745
+*D_NET *3 0.211313
*CONN
*P io_in[11] I
-*I *419:io_in[11] I *D user_proj_example
+*I *419:io_in[11] I *D wrapped_vga_clock
*CAP
1 io_in[11] 0.000280649
-2 *419:io_in[11] 0.00253971
-3 *3:16 0.0256241
-4 *3:15 0.0230844
-5 *3:13 0.0634675
-6 *3:11 0.0637482
+2 *419:io_in[11] 0.000253574
+3 *3:16 0.0350765
+4 *3:15 0.034823
+5 *3:13 0.0702994
+6 *3:11 0.0705801
+7 *3:16 *91:10 0
*RES
1 io_in[11] *3:11 2.655
-2 *3:11 *3:13 690.93
+2 *3:11 *3:13 766.53
3 *3:13 *3:15 4.5
-4 *3:15 *3:16 229.68
-5 *3:16 *419:io_in[11] 23.355
+4 *3:15 *3:16 347.49
+5 *3:16 *419:io_in[11] 11.5904
*END
-*D_NET *4 0.189839
+*D_NET *4 0.263763
*CONN
*P io_in[12] I
-*I *419:io_in[12] I *D user_proj_example
+*I *419:io_in[12] I *D wrapped_vga_clock
*CAP
1 io_in[12] 0.000215438
-2 *419:io_in[12] 9.37343e-05
-3 *4:16 0.0320508
-4 *4:15 0.031957
-5 *4:13 0.0626533
-6 *4:11 0.0628687
+2 *419:io_in[12] 0.000881417
+3 *4:16 0.0445163
+4 *4:15 0.0436348
+5 *4:13 0.0717957
+6 *4:11 0.0720111
+7 *4:16 *7:17 0.000572841
+8 *4:16 *8:19 0.0301355
*RES
1 io_in[12] *4:11 2.115
-2 *4:11 *4:13 682.83
+2 *4:11 *4:13 782.91
3 *4:13 *4:15 4.5
-4 *4:15 *4:16 316.17
-5 *4:16 *419:io_in[12] 0.945
+4 *4:15 *4:16 455.85
+5 *4:16 *419:io_in[12] 13.005
*END
-*D_NET *5 0.21382
+*D_NET *5 0.222276
*CONN
*P io_in[13] I
-*I *419:io_in[13] I *D user_proj_example
+*I *419:io_in[13] I *D wrapped_vga_clock
*CAP
1 io_in[13] 0.000145659
-2 *419:io_in[13] 0.00334128
-3 *5:16 0.03984
-4 *5:15 0.0364988
-5 *5:13 0.0599306
-6 *5:11 0.0600762
-7 *419:io_in[13] *30:11 0
-8 *419:io_in[13] *40:11 0
-9 *419:io_in[13] *93:10 0.0139871
-10 *5:16 *419:io_in[16] 0
+2 *419:io_in[13] 0.00107029
+3 *5:16 0.0481195
+4 *5:15 0.0470492
+5 *5:13 0.0628727
+6 *5:11 0.0630183
+7 *419:io_in[13] *37:19 0
+8 *5:16 *100:12 0
*RES
1 io_in[13] *5:11 1.575
-2 *5:11 *5:13 654.57
+2 *5:11 *5:13 686.97
3 *5:13 *5:15 4.5
-4 *5:15 *5:16 363.15
-5 *5:16 *419:io_in[13] 47.565
+4 *5:15 *5:16 470.07
+5 *5:16 *419:io_in[13] 27.3874
*END
-*D_NET *6 0.218162
+*D_NET *6 0.239127
*CONN
*P io_in[14] I
-*I *419:io_in[14] I *D user_proj_example
+*I *419:io_in[14] I *D wrapped_vga_clock
*CAP
1 io_in[14] 0.00397136
-2 *419:io_in[14] 0.0025078
-3 *6:12 0.0459485
-4 *6:11 0.0434407
-5 *6:9 0.0557252
-6 *6:7 0.0596966
-7 *419:io_in[14] *38:15 0.002321
-8 *419:io_in[14] *45:10 0.00428972
-9 *419:io_in[14] *81:5 0
-10 *6:12 *419:io_in[16] 0.000260847
-11 *6:12 *46:9 0
+2 *419:io_in[14] 0.000353687
+3 *6:12 0.0543311
+4 *6:11 0.0539774
+5 *6:9 0.0607997
+6 *6:7 0.064771
+7 *419:io_in[14] *93:10 5.4397e-05
+8 *6:12 *38:12 0
+9 *6:12 *93:10 0.000868212
*RES
1 io_in[14] *6:7 43.425
-2 *6:7 *6:9 608.94
+2 *6:7 *6:9 664.2
3 *6:9 *6:11 4.5
-4 *6:11 *6:12 432.99
-5 *6:12 *419:io_in[14] 39.465
+4 *6:11 *6:12 541.89
+5 *6:12 *419:io_in[14] 12.9052
*END
-*D_NET *7 0.23226
+*D_NET *7 0.305791
*CONN
*P io_in[15] I
-*I *419:io_in[15] I *D user_proj_example
+*I *419:io_in[15] I *D wrapped_vga_clock
*CAP
-1 io_in[15] 0.000255689
-2 *419:io_in[15] 0.00261809
-3 *7:11 0.0503314
-4 *7:10 0.0477133
-5 *7:8 0.0655429
-6 *7:7 0.0657986
-7 *7:11 *14:10 0
-8 *7:11 *82:13 0
-9 *7:11 *95:13 0
+1 io_in[15] 0.00433622
+2 *419:io_in[15] 0.000941763
+3 *7:17 0.00325416
+4 *7:12 0.0704213
+5 *7:11 0.0681089
+6 *7:9 0.055017
+7 *7:7 0.0593532
+8 *7:12 *32:19 0
+9 *7:12 *39:17 0
+10 *7:12 *39:21 0
+11 *7:12 *61:11 0
+12 *7:12 *70:11 0.00370839
+13 *7:12 *72:14 0
+14 *7:12 *87:13 0.0143612
+15 *7:17 *8:19 0.0257164
+16 *4:16 *7:17 0.000572841
*RES
-1 io_in[15] *7:7 6.885
-2 *7:7 *7:8 642.87
-3 *7:8 *7:10 4.5
-4 *7:10 *7:11 475.38
-5 *7:11 *419:io_in[15] 23.895
+1 io_in[15] *7:7 43.245
+2 *7:7 *7:9 549.54
+3 *7:9 *7:11 4.5
+4 *7:11 *7:12 764.73
+5 *7:12 *7:17 49.23
+6 *7:17 *419:io_in[15] 8.865
*END
-*D_NET *8 0.257024
+*D_NET *8 0.785433
*CONN
*P io_in[16] I
-*I *419:io_in[16] I *D user_proj_example
+*I *419:io_in[16] I *D wrapped_vga_clock
*CAP
1 io_in[16] 0.000164983
-2 *419:io_in[16] 0.00227919
-3 *8:16 0.0467308
-4 *8:15 0.0444516
-5 *8:13 0.0480074
-6 *8:11 0.0481724
-7 *8:16 *15:16 0.0316444
-8 *8:16 *18:21 0.0146099
-9 *8:16 *22:13 0.0207025
-10 *8:16 *30:11 0
-11 *8:16 *102:10 0
-12 *5:16 *419:io_in[16] 0
-13 *6:12 *419:io_in[16] 0.000260847
+2 *419:io_in[16] 0.00089733
+3 *8:19 0.00409443
+4 *8:18 0.0031971
+5 *8:16 0.0290178
+6 *8:15 0.0290178
+7 *8:13 0.0595723
+8 *8:11 0.0597373
+9 *8:16 *40:12 0.000683868
+10 *8:16 *61:11 0
+11 *8:16 *71:11 0.000746036
+12 *8:16 *79:11 0.447808
+13 *8:16 *81:13 0.000663143
+14 *8:16 *101:11 0.0732974
+15 *8:19 *50:8 0.0206836
+16 *4:16 *8:19 0.0301355
+17 *7:17 *8:19 0.0257164
*RES
1 io_in[16] *8:11 1.935
-2 *8:11 *8:13 479.07
+2 *8:11 *8:13 594.99
3 *8:13 *8:15 4.5
-4 *8:15 *8:16 526.41
-5 *8:16 *419:io_in[16] 26.235
+4 *8:15 *8:16 656.55
+5 *8:16 *8:18 4.5
+6 *8:18 *8:19 80.91
+7 *8:19 *419:io_in[16] 13.185
*END
-*D_NET *9 0.185702
+*D_NET *9 0.430438
*CONN
*P io_in[17] I
-*I *419:io_in[17] I *D user_proj_example
+*I *419:io_in[17] I *D wrapped_vga_clock
*CAP
-1 io_in[17] 0.000291323
-2 *419:io_in[17] 0.00404386
-3 *9:16 0.0461628
-4 *9:15 0.0421189
-5 *9:13 0.046397
-6 *9:11 0.0466883
-7 *9:16 *70:12 0
+1 io_in[17] 0.00073246
+2 *419:io_in[17] 0.00223037
+3 *9:14 0.00824978
+4 *9:13 0.00601941
+5 *9:11 0.0569686
+6 *9:10 0.0569686
+7 *9:8 0.0238198
+8 *9:7 0.0245522
+9 *9:8 *13:10 0
+10 *9:8 *46:13 0.00389597
+11 *9:8 *46:15 0.0129313
+12 *9:8 *48:11 0.0164128
+13 *9:8 *85:11 0.056388
+14 *9:8 *87:17 0.115698
+15 *9:14 *49:17 0.0455705
*RES
-1 io_in[17] *9:11 3.015
-2 *9:11 *9:13 462.87
-3 *9:13 *9:15 4.5
-4 *9:15 *9:16 410.49
-5 *9:16 *419:io_in[17] 42.075
+1 io_in[17] *9:7 11.025
+2 *9:7 *9:8 416.97
+3 *9:8 *9:10 4.5
+4 *9:10 *9:11 569.61
+5 *9:11 *9:13 4.5
+6 *9:13 *9:14 93.15
+7 *9:14 *419:io_in[17] 34.963
*END
-*D_NET *10 0.354135
+*D_NET *10 0.312395
*CONN
*P io_in[18] I
-*I *419:io_in[18] I *D user_proj_example
+*I *419:io_in[18] I *D wrapped_vga_clock
*CAP
1 io_in[18] 0.000104982
-2 *419:io_in[18] 0.000612886
-3 *10:16 0.0060937
-4 *10:15 0.00548082
-5 *10:13 0.0496023
-6 *10:11 0.0497072
-7 *10:16 *23:19 0.0035359
-8 *10:16 *25:13 0.000696278
-9 *10:16 *57:8 0.0011605
-10 *10:16 *62:8 0.000507719
-11 *10:16 *74:8 0.0158066
-12 *10:16 *86:8 0.177246
-13 *10:16 *94:8 0.0400991
-14 *10:16 *98:8 0.00348148
+2 *419:io_in[18] 0.000707736
+3 *10:22 0.00438518
+4 *10:21 0.00391463
+5 *10:16 0.0183155
+6 *10:15 0.0180783
+7 *10:13 0.0693492
+8 *10:11 0.0694542
+9 *10:16 *45:14 0.0777535
+10 *10:16 *75:10 6.21698e-05
+11 *10:21 *30:16 0.00411217
+12 *10:21 *68:10 0.00046262
+13 *10:22 *59:8 0.0439538
+14 *10:22 *90:8 0.00174075
*RES
1 io_in[18] *10:11 1.395
-2 *10:11 *10:13 494.37
+2 *10:11 *10:13 692.01
3 *10:13 *10:15 4.5
-4 *10:15 *10:16 296.73
-5 *10:16 *419:io_in[18] 9.585
+4 *10:15 *10:16 337.77
+5 *10:16 *10:21 15.03
+6 *10:21 *10:22 71.19
+7 *10:22 *419:io_in[18] 10.845
*END
-*D_NET *11 0.313931
+*D_NET *11 0.243974
*CONN
*P io_in[19] I
-*I *419:io_in[19] I *D user_proj_example
+*I *419:io_in[19] I *D wrapped_vga_clock
*CAP
-1 io_in[19] 0.000224243
-2 *419:io_in[19] 0.000626102
-3 *11:16 0.00281522
-4 *11:15 0.00218912
-5 *11:13 0.0495846
-6 *11:11 0.0498088
-7 *419:io_in[19] *49:9 0
-8 *11:16 *23:19 0.020806
-9 *11:16 *25:13 0.0627291
-10 *11:16 *86:8 0.125147
+1 io_in[19] 0.000950832
+2 *419:io_in[19] 0.00112027
+3 *11:11 0.0649591
+4 *11:10 0.0638389
+5 *11:8 0.0311276
+6 *11:7 0.0320784
+7 *11:8 io_oeb[14] 0
+8 *11:8 io_oeb[21] 0
+9 *11:8 *13:10 0
+10 *11:8 *14:10 0
+11 *11:11 *74:8 0.0498985
*RES
-1 io_in[19] *11:11 2.475
-2 *11:11 *11:13 494.01
-3 *11:13 *11:15 4.5
-4 *11:15 *11:16 181.17
-5 *11:16 *419:io_in[19] 9.945
+1 io_in[19] *11:7 13.725
+2 *11:7 *11:8 339.57
+3 *11:8 *11:10 4.5
+4 *11:10 *11:11 669.87
+5 *11:11 *419:io_in[19] 15.705
*END
-*D_NET *12 0.37121
+*D_NET *12 0.182383
*CONN
*P io_in[1] I
-*I *419:io_in[1] I *D user_proj_example
+*I *419:io_in[1] I *D wrapped_vga_clock
*CAP
-1 io_in[1] 0.00148585
-2 *419:io_in[1] 0.000406751
-3 *12:14 0.0282624
-4 *12:13 0.0278557
-5 *12:11 0.0733365
-6 *12:10 0.0748223
-7 *419:io_in[1] *63:27 0.00491141
-8 *419:io_in[1] *69:8 0
-9 *12:10 *39:13 0
-10 *12:14 *39:7 0.160129
-11 *12:14 *66:13 0
-12 *12:14 *322:11 0
+1 io_in[1] 0.000280649
+2 *419:io_in[1] 0.038048
+3 *12:18 0.038048
+4 *12:16 0.0286075
+5 *12:15 0.0286075
+6 *12:13 0.0242554
+7 *12:11 0.0245361
*RES
-1 io_in[1] *12:10 23.895
-2 *12:10 *12:11 764.37
-3 *12:11 *12:13 4.5
-4 *12:13 *12:14 380.61
-5 *12:14 *419:io_in[1] 16.56
+1 io_in[1] *12:11 2.655
+2 *12:11 *12:13 265.77
+3 *12:13 *12:15 4.5
+4 *12:15 *12:16 285.21
+5 *12:16 *12:18 4.5
+6 *12:18 *419:io_in[1] 413.145
*END
-*D_NET *13 0.114427
+*D_NET *13 0.162664
*CONN
*P io_in[20] I
-*I *419:io_in[20] I *D user_proj_example
+*I *419:io_in[20] I *D wrapped_vga_clock
*CAP
-1 io_in[20] 0.00434068
-2 *419:io_in[20] 0.00263431
-3 *13:15 0.0107507
-4 *13:14 0.00811643
-5 *13:12 0.00656792
-6 *13:11 0.00656792
-7 *13:9 0.0355544
-8 *13:7 0.0398951
-9 *13:12 *75:12 0
-10 *13:15 *87:13 0
+1 io_in[20] 0.00097235
+2 *419:io_in[20] 0.0090363
+3 *13:13 0.0090363
+4 *13:11 0.0682775
+5 *13:10 0.0692499
+6 *419:io_in[20] *89:14 0.00609185
+7 *9:8 *13:10 0
+8 *11:8 *13:10 0
*RES
-1 io_in[20] *13:7 43.245
-2 *13:7 *13:9 355.14
-3 *13:9 *13:11 4.5
-4 *13:11 *13:12 70.29
-5 *13:12 *13:14 4.5
-6 *13:14 *13:15 79.74
-7 *13:15 *419:io_in[20] 23.895
+1 io_in[20] *13:10 18.495
+2 *13:10 *13:11 681.03
+3 *13:11 *13:13 4.5
+4 *13:13 *419:io_in[20] 124.245
*END
-*D_NET *14 0.109615
+*D_NET *14 0.143401
*CONN
*P io_in[21] I
-*I *419:io_in[21] I *D user_proj_example
+*I *419:io_in[21] I *D wrapped_vga_clock
*CAP
-1 io_in[21] 0.00109286
-2 *419:io_in[21] 0.00255376
-3 *14:19 0.0052569
-4 *14:14 0.00662667
-5 *14:11 0.048458
-6 *14:10 0.0456273
-7 *14:19 *89:17 0
-8 *7:11 *14:10 0
+1 io_in[21] 0.00115169
+2 *419:io_in[21] 7.31006e-05
+3 *14:17 0.00256769
+4 *14:11 0.0604352
+5 *14:10 0.0590923
+6 *14:10 *87:17 0
+7 *14:17 *37:19 0.0200808
+8 *11:8 *14:10 0
*RES
-1 io_in[21] *14:10 19.215
-2 *14:10 *14:11 444.33
-3 *14:11 *14:14 46.53
-4 *14:14 *14:19 30.51
-5 *14:19 *419:io_in[21] 23.085
+1 io_in[21] *14:10 19.575
+2 *14:10 *14:11 579.15
+3 *14:11 *14:17 46.8
+4 *14:17 *419:io_in[21] 9.74739
*END
-*D_NET *15 0.159723
+*D_NET *15 0.152061
*CONN
*P io_in[22] I
-*I *419:io_in[22] I *D user_proj_example
+*I *419:io_in[22] I *D wrapped_vga_clock
*CAP
1 io_in[22] 0.000290594
-2 *419:io_in[22] 0.00239432
-3 *15:16 0.0157859
-4 *15:15 0.0133916
-5 *15:13 0.0479627
-6 *15:11 0.0482533
-7 *419:io_in[22] *90:7 0
-8 *15:16 *30:11 0
-9 *15:16 *102:10 0
-10 *8:16 *15:16 0.0316444
+2 *419:io_in[22] 0.000416581
+3 *15:19 0.00269729
+4 *15:13 0.0616461
+5 *15:11 0.059656
+6 *15:13 *91:10 0.000393572
+7 *15:19 *87:8 0.0208064
+8 *15:19 *101:11 0.00615481
*RES
1 io_in[22] *15:11 3.015
-2 *15:11 *15:13 478.89
-3 *15:13 *15:15 4.5
-4 *15:15 *15:16 162.09
-5 *15:16 *419:io_in[22] 26.055
+2 *15:11 *15:13 594.63
+3 *15:13 *15:19 48.42
+4 *15:19 *419:io_in[22] 8.145
*END
-*D_NET *16 0.152159
+*D_NET *16 0.140372
*CONN
*P io_in[23] I
-*I *419:io_in[23] I *D user_proj_example
+*I *419:io_in[23] I *D wrapped_vga_clock
*CAP
1 io_in[23] 0.000104982
-2 *419:io_in[23] 0.00455443
-3 *16:16 0.0301942
-4 *16:15 0.0256398
-5 *16:13 0.0457802
-6 *16:11 0.0458852
-7 *16:16 *110:14 0
-8 *16:16 *111:10 0
+2 *419:io_in[23] 0.0094561
+3 *16:15 0.0094561
+4 *16:13 0.0606248
+5 *16:11 0.0607298
+6 *16:13 *18:16 0
*RES
1 io_in[23] *16:11 1.395
-2 *16:11 *16:13 457.47
+2 *16:11 *16:13 605.61
3 *16:13 *16:15 4.5
-4 *16:15 *16:16 275.49
-5 *16:16 *419:io_in[23] 46.935
+4 *16:15 *419:io_in[23] 100.125
*END
-*D_NET *17 0.210024
+*D_NET *17 0.388068
*CONN
*P io_in[24] I
-*I *419:io_in[24] I *D user_proj_example
+*I *419:io_in[24] I *D wrapped_vga_clock
*CAP
-1 io_in[24] 0.00112395
-2 *419:io_in[24] 0.00264576
-3 *17:11 0.0330545
-4 *17:10 0.0304088
-5 *17:8 0.0463462
-6 *17:7 0.0474702
-7 *419:io_in[24] *55:11 0
-8 *419:io_in[24] *92:9 0.000420424
-9 *17:11 *82:14 0.0485546
-10 *17:11 *102:10 0
+1 io_in[24] 0.0262269
+2 *419:io_in[24] 0.00014207
+3 *17:8 0.0478583
+4 *17:7 0.0477163
+5 *17:5 0.0262269
+6 *17:8 *21:16 0.214017
+7 *17:8 *40:12 0.00153439
+8 *17:8 *55:14 0
+9 *17:8 *66:8 0.0206836
+10 *17:8 *101:8 0.00366209
*RES
-1 io_in[24] *17:7 16.065
-2 *17:7 *17:8 463.05
-3 *17:8 *17:10 4.5
-4 *17:10 *17:11 357.93
-5 *17:11 *419:io_in[24] 30.555
+1 io_in[24] *17:5 285.705
+2 *17:5 *17:7 4.5
+3 *17:7 *17:8 635.67
+4 *17:8 *419:io_in[24] 5.985
*END
-*D_NET *18 0.167353
+*D_NET *18 0.155465
*CONN
*P io_in[25] I
-*I *419:io_in[25] I *D user_proj_example
+*I *419:io_in[25] I *D wrapped_vga_clock
*CAP
1 io_in[25] 0.000237175
-2 *419:io_in[25] 0.00240246
-3 *18:21 0.00350526
-4 *18:16 0.0408795
-5 *18:15 0.0397767
-6 *18:13 0.0328464
-7 *18:11 0.0330835
-8 *419:io_in[25] *22:8 1.22751e-05
-9 *18:21 *102:10 0
-10 *8:16 *18:21 0.0146099
+2 *419:io_in[25] 0.00952647
+3 *18:18 0.00952647
+4 *18:16 0.0599673
+5 *18:15 0.0599673
+6 *18:13 0.00800164
+7 *18:11 0.00823881
+8 *16:13 *18:16 0
*RES
1 io_in[25] *18:11 2.295
-2 *18:11 *18:13 357.21
+2 *18:11 *18:13 87.21
3 *18:13 *18:15 4.5
-4 *18:15 *18:16 395.55
-5 *18:16 *18:21 30.15
-6 *18:21 *419:io_in[25] 21.915
+4 *18:15 *18:16 598.95
+5 *18:16 *18:18 4.5
+6 *18:18 *419:io_in[25] 101.565
*END
-*D_NET *19 0.142081
+*D_NET *19 0.125748
*CONN
*P io_in[26] I
-*I *419:io_in[26] I *D user_proj_example
+*I *419:io_in[26] I *D wrapped_vga_clock
*CAP
1 io_in[26] 0.00010158
-2 *419:io_in[26] 0.00256146
-3 *19:16 0.0354208
-4 *19:15 0.0328593
-5 *19:13 0.0355184
-6 *19:11 0.0356199
-7 *419:io_in[26] *94:7 0
+2 *419:io_in[26] 0.0015846
+3 *19:16 0.0467772
+4 *19:15 0.0451926
+5 *19:13 0.0159954
+6 *19:11 0.0160969
*RES
1 io_in[26] *19:11 1.215
-2 *19:11 *19:13 385.65
+2 *19:11 *19:13 173.61
3 *19:13 *19:15 4.5
-4 *19:15 *19:16 326.88
-5 *19:16 *419:io_in[26] 23.355
+4 *19:15 *19:16 451.53
+5 *19:16 *419:io_in[26] 19.665
*END
-*D_NET *20 0.41346
+*D_NET *20 0.124098
*CONN
*P io_in[27] I
-*I *419:io_in[27] I *D user_proj_example
+*I *419:io_in[27] I *D wrapped_vga_clock
*CAP
-1 io_in[27] 0.00242728
-2 *419:io_in[27] 0.00291745
-3 *20:19 0.0185027
-4 *20:18 0.0155853
-5 *20:16 0.0252776
-6 *20:15 0.0277049
-7 *20:19 *58:10 0.25844
-8 *20:19 *95:10 0.062605
-9 *20:19 *101:10 0
+1 io_in[27] 0.000310538
+2 *419:io_in[27] 0.000985163
+3 *20:16 0.0377683
+4 *20:15 0.0367831
+5 *20:13 0.023934
+6 *20:11 0.0242445
+7 *419:io_in[27] *52:14 6.90477e-06
+8 *419:io_in[27] *93:11 0
+9 *419:io_in[27] *98:13 6.52783e-05
*RES
-1 io_in[27] *20:15 27.045
-2 *20:15 *20:16 252.45
-3 *20:16 *20:18 4.5
-4 *20:18 *20:19 374.13
-5 *20:19 *419:io_in[27] 31.455
+1 io_in[27] *20:11 2.835
+2 *20:11 *20:13 233.01
+3 *20:13 *20:15 4.5
+4 *20:15 *20:16 367.47
+5 *20:16 *419:io_in[27] 27.7474
*END
-*D_NET *21 0.125944
+*D_NET *21 0.31322
*CONN
*P io_in[28] I
-*I *419:io_in[28] I *D user_proj_example
+*I *419:io_in[28] I *D wrapped_vga_clock
*CAP
1 io_in[28] 0.000167681
-2 *419:io_in[28] 4.01718e-05
-3 *21:16 0.0214632
-4 *21:15 0.021423
-5 *21:13 0.0413413
-6 *21:11 0.041509
-7 *21:16 *97:13 0
+2 *419:io_in[28] 0.000172243
+3 *21:16 0.0173921
+4 *21:15 0.0172199
+5 *21:13 0.0294332
+6 *21:11 0.0296009
+7 *21:16 *101:8 0.00521694
+8 *17:8 *21:16 0.214017
*RES
1 io_in[28] *21:11 1.755
-2 *21:11 *21:13 401.85
+2 *21:11 *21:13 285.93
3 *21:13 *21:15 4.5
-4 *21:15 *21:16 210.87
-5 *21:16 *419:io_in[28] 0.405
+4 *21:15 *21:16 313.83
+5 *21:16 *419:io_in[28] 6.165
*END
-*D_NET *22 0.123662
+*D_NET *22 0.242186
*CONN
*P io_in[29] I
-*I *419:io_in[29] I *D user_proj_example
+*I *419:io_in[29] I *D wrapped_vga_clock
*CAP
-1 io_in[29] 0.035057
-2 *419:io_in[29] 0.00220971
-3 *22:13 0.0038167
-4 *22:8 0.0140212
-5 *22:7 0.0124142
-6 *22:5 0.035057
-7 *419:io_in[29] *97:12 0.000371323
-8 *22:8 *56:11 0
-9 *22:13 *102:10 0
-10 *419:io_in[25] *22:8 1.22751e-05
-11 *8:16 *22:13 0.0207025
+1 io_in[29] 0.0155824
+2 *419:io_in[29] 0.000295132
+3 *22:11 0.00283812
+4 *22:10 0.00254299
+5 *22:8 0.0339271
+6 *22:7 0.0339271
+7 *22:5 0.0155824
+8 *22:11 *42:8 0.0551395
+9 *22:11 *58:8 0.00615439
+10 *22:11 *64:8 0.00225883
+11 *22:11 *73:8 0.0573774
+12 *22:11 *89:8 0.000335457
+13 *22:11 *96:8 0.0162253
*RES
-1 io_in[29] *22:5 378.765
+1 io_in[29] *22:5 168.165
2 *22:5 *22:7 4.5
-3 *22:7 *22:8 122.85
-4 *22:8 *22:13 38.97
-5 *22:13 *419:io_in[29] 21.735
+3 *22:7 *22:8 338.13
+4 *22:8 *22:10 4.5
+5 *22:10 *22:11 113.13
+6 *22:11 *419:io_in[29] 7.065
*END
-*D_NET *23 0.510622
+*D_NET *23 0.157699
*CONN
*P io_in[2] I
-*I *419:io_in[2] I *D user_proj_example
+*I *419:io_in[2] I *D wrapped_vga_clock
*CAP
1 io_in[2] 0.000215438
-2 *419:io_in[2] 0.000626809
-3 *23:19 0.0107835
-4 *23:18 0.0101567
-5 *23:16 0.0336736
-6 *23:15 0.0336736
-7 *23:13 0.0309457
-8 *23:11 0.0311611
-9 *419:io_in[2] *61:9 0
-10 *23:16 *140:13 0
-11 *23:19 *25:13 0.151507
-12 *23:19 *26:19 0.156729
-13 *23:19 *28:11 0.00348146
-14 *23:19 *74:8 0
-15 *23:19 *86:8 0.0100715
-16 *23:19 *108:8 0.0132545
-17 *10:16 *23:19 0.0035359
-18 *11:16 *23:19 0.020806
+2 *419:io_in[2] 0.0493593
+3 *23:18 0.0493593
+4 *23:16 0.016359
+5 *23:15 0.016359
+6 *23:13 0.0129157
+7 *23:11 0.0131311
*RES
1 io_in[2] *23:11 2.115
-2 *23:11 *23:13 327.87
+2 *23:11 *23:13 141.57
3 *23:13 *23:15 4.5
-4 *23:15 *23:16 332.37
+4 *23:15 *23:16 163.17
5 *23:16 *23:18 4.5
-6 *23:18 *23:19 429.75
-7 *23:19 *419:io_in[2] 10.305
+6 *23:18 *419:io_in[2] 537.345
*END
-*D_NET *24 0.0932576
+*D_NET *24 0.0777088
*CONN
*P io_in[30] I
-*I *419:io_in[30] I *D user_proj_example
+*I *419:io_in[30] I *D wrapped_vga_clock
*CAP
1 io_in[30] 0.000237175
-2 *419:io_in[30] 0.00257955
-3 *24:16 0.00780899
-4 *24:15 0.00522944
-5 *24:13 0.0385826
-6 *24:11 0.0388198
-7 *419:io_in[30] *98:7 0
+2 *419:io_in[30] 0.00121317
+3 *24:16 0.0174712
+4 *24:15 0.0162581
+5 *24:13 0.0211227
+6 *24:11 0.0213599
+7 *419:io_in[30] *49:13 0
+8 *419:io_in[30] *93:11 0
+9 *419:io_in[30] *98:13 4.66274e-05
+10 *419:io_in[30] *98:14 0
*RES
1 io_in[30] *24:11 2.295
-2 *24:11 *24:13 415.35
+2 *24:11 *24:13 227.61
3 *24:13 *24:15 4.5
-4 *24:15 *24:16 51.48
-5 *24:16 *419:io_in[30] 23.895
+4 *24:15 *24:16 162.27
+5 *24:16 *419:io_in[30] 29.9074
*END
-*D_NET *25 0.308633
+*D_NET *25 0.165314
*CONN
*P io_in[31] I
-*I *419:io_in[31] I *D user_proj_example
+*I *419:io_in[31] I *D wrapped_vga_clock
*CAP
1 io_in[31] 0.00010158
-2 *419:io_in[31] 0.000620624
-3 *25:13 0.00922407
-4 *25:11 0.00870503
-5 *25:13 *26:19 0.0421925
-6 *25:13 *86:8 0.00058025
-7 *25:13 *94:8 0.0322763
-8 *10:16 *25:13 0.000696278
-9 *11:16 *25:13 0.0627291
-10 *23:19 *25:13 0.151507
+2 *419:io_in[31] 0.000588953
+3 *25:19 0.00163467
+4 *25:18 0.00104572
+5 *25:16 0.0204448
+6 *25:15 0.0204448
+7 *25:13 0.0158561
+8 *25:11 0.0159577
+9 *25:19 *54:8 0.032266
+10 *25:19 *59:8 0.00160165
+11 *25:19 *63:8 0.0531548
+12 *25:19 *86:13 0.00221731
*RES
1 io_in[31] *25:11 1.215
-2 *25:11 *25:13 424.89
-3 *25:13 *419:io_in[31] 10.125
+2 *25:11 *25:13 170.91
+3 *25:13 *25:15 4.5
+4 *25:15 *25:16 203.13
+5 *25:16 *25:18 4.5
+6 *25:18 *25:19 76.95
+7 *25:19 *419:io_in[31] 9.765
*END
-*D_NET *26 0.469592
+*D_NET *26 0.119046
*CONN
*P io_in[32] I
-*I *419:io_in[32] I *D user_proj_example
+*I *419:io_in[32] I *D wrapped_vga_clock
*CAP
-1 io_in[32] 0.00247302
-2 *419:io_in[32] 0.000662159
-3 *26:19 0.00835342
-4 *26:18 0.00769126
-5 *26:16 0.00710132
-6 *26:15 0.00957434
-7 *419:io_in[32] *64:9 0
-8 *26:19 *28:11 0.234815
-9 *23:19 *26:19 0.156729
-10 *25:13 *26:19 0.0421925
+1 io_in[32] 0.000310538
+2 *419:io_in[32] 0.000751389
+3 *26:16 0.00527137
+4 *26:15 0.00451998
+5 *26:13 0.0272117
+6 *26:11 0.0275223
+7 *26:16 *60:8 0.0534583
*RES
-1 io_in[32] *26:15 29.745
-2 *26:15 *26:16 70.65
-3 *26:16 *26:18 4.5
-4 *26:18 *26:19 410.13
-5 *26:19 *419:io_in[32] 10.485
+1 io_in[32] *26:11 2.835
+2 *26:11 *26:13 291.51
+3 *26:13 *26:15 4.5
+4 *26:15 *26:16 78.39
+5 *26:16 *419:io_in[32] 11.745
*END
-*D_NET *27 0.266088
+*D_NET *27 0.0400662
*CONN
*P io_in[33] I
-*I *419:io_in[33] I *D user_proj_example
+*I *419:io_in[33] I *D wrapped_vga_clock
*CAP
-1 io_in[33] 0.000167681
-2 *419:io_in[33] 0.00072738
-3 *27:19 0.0149681
-4 *27:18 0.0142408
-5 *27:16 0.0139219
-6 *27:15 0.0139219
-7 *27:13 0.0127525
-8 *27:11 0.0129202
-9 *27:19 *28:11 0.0183608
-10 *27:19 *40:10 0.00486988
-11 *27:19 *44:10 0.00598901
-12 *27:19 *50:10 0
-13 *27:19 *108:8 0.153248
+1 io_in[33] 0.00156645
+2 *419:io_in[33] 0.0184666
+3 *27:10 0.0200331
*RES
-1 io_in[33] *27:11 1.755
-2 *27:11 *27:13 138.51
-3 *27:13 *27:15 4.5
-4 *27:15 *27:16 138.69
-5 *27:16 *27:18 4.5
-6 *27:18 *27:19 301.59
-7 *27:19 *419:io_in[33] 11.025
+1 io_in[33] *27:10 24.795
+2 *27:10 *419:io_in[33] 178.425
*END
-*D_NET *28 0.48709
+*D_NET *28 0.0405681
*CONN
*P io_in[34] I
-*I *419:io_in[34] I *D user_proj_example
+*I *419:io_in[34] I *D wrapped_vga_clock
*CAP
-1 io_in[34] 0.00847721
-2 *419:io_in[34] 0.000729584
-3 *28:11 0.0067326
-4 *28:10 0.00600301
-5 *28:8 0.0206553
-6 *28:7 0.0206553
-7 *28:5 0.00847721
-8 *419:io_in[34] *66:9 0
-9 *28:5 *316:16 0
-10 *28:5 *342:16 0.000233137
-11 *28:5 *403:8 0
-12 *28:5 *418:14 0
-13 *28:11 *108:8 0.15847
-14 *23:19 *28:11 0.00348146
-15 *26:19 *28:11 0.234815
-16 *27:19 *28:11 0.0183608
+1 io_in[34] 0.0194104
+2 *419:io_in[34] 0.0008736
+3 *28:5 0.020284
+4 *28:5 *59:8 0
+5 *28:5 *314:8 0
*RES
-1 io_in[34] *28:5 92.565
-2 *28:5 *28:7 4.5
-3 *28:7 *28:8 205.83
-4 *28:8 *28:10 4.5
-5 *28:10 *28:11 355.05
-6 *28:11 *419:io_in[34] 10.665
+1 io_in[34] *28:5 211.005
+2 *28:5 *419:io_in[34] 11.925
*END
-*D_NET *29 0.150721
+*D_NET *29 0.0577165
*CONN
*P io_in[35] I
-*I *419:io_in[35] I *D user_proj_example
+*I *419:io_in[35] I *D wrapped_vga_clock
*CAP
1 io_in[35] 0.000237175
-2 *419:io_in[35] 0.00132881
-3 *29:19 0.0271911
-4 *29:18 0.0258623
-5 *29:16 0.0284093
-6 *29:15 0.0284093
-7 *29:13 0.017005
-8 *29:11 0.0172421
-9 *29:16 *321:13 0
-10 *29:19 *38:15 0
-11 *29:19 *45:10 0
-12 *29:19 *53:10 0
-13 *29:19 *92:10 0
-14 *29:19 *97:12 0.00503575
+2 *419:io_in[35] 0.000147297
+3 *29:22 0.00758816
+4 *29:21 0.00744087
+5 *29:19 0.0126837
+6 *29:18 0.0131
+7 *29:13 0.00834915
+8 *29:11 0.00817004
+9 *29:13 *105:10 0
*RES
1 io_in[35] *29:11 2.295
-2 *29:11 *29:13 179.01
-3 *29:13 *29:15 4.5
-4 *29:15 *29:16 280.89
-5 *29:16 *29:18 4.5
-6 *29:18 *29:19 274.95
-7 *29:19 *419:io_in[35] 16.875
+2 *29:11 *29:13 85.95
+3 *29:13 *29:18 13.05
+4 *29:18 *29:19 137.79
+5 *29:19 *29:21 4.5
+6 *29:21 *29:22 73.71
+7 *29:22 *419:io_in[35] 1.485
*END
-*D_NET *30 0.229358
+*D_NET *30 0.124911
*CONN
*P io_in[36] I
-*I *419:io_in[36] I *D user_proj_example
+*I *419:io_in[36] I *D wrapped_vga_clock
*CAP
-1 io_in[36] 0.000641502
-2 *419:io_in[36] 0.00215269
-3 *30:11 0.0457181
-4 *30:10 0.0435654
-5 *30:8 0.0307077
-6 *30:7 0.0313492
-7 *30:8 io_oeb[30] 1.38095e-05
-8 *30:8 *57:11 0.00988149
-9 *30:8 *94:11 0.00975874
-10 *30:8 *98:11 2.45503e-05
-11 *30:8 *106:17 0.055545
-12 *30:11 *93:10 0
-13 *419:io_in[13] *30:11 0
-14 *8:16 *30:11 0
-15 *15:16 *30:11 0
+1 io_in[36] 0.00010158
+2 *419:io_in[36] 0.00014207
+3 *30:16 0.0121588
+4 *30:15 0.0120168
+5 *30:13 0.0262048
+6 *30:11 0.0263064
+7 *30:16 *66:8 0.0427789
+8 *30:16 *68:10 0.00108942
+9 *30:16 *68:12 0
+10 *10:21 *30:16 0.00411217
*RES
-1 io_in[36] *30:7 10.845
-2 *30:7 *30:8 355.59
-3 *30:8 *30:10 4.5
-4 *30:10 *30:11 455.13
-5 *30:11 *419:io_in[36] 24.975
+1 io_in[36] *30:11 1.215
+2 *30:11 *30:13 285.75
+3 *30:13 *30:15 4.5
+4 *30:15 *30:16 154.53
+5 *30:16 *419:io_in[36] 5.985
*END
-*D_NET *31 0.184317
+*D_NET *31 0.0937783
*CONN
*P io_in[37] I
-*I *419:io_in[37] I *D user_proj_example
+*I *419:io_in[37] I *D wrapped_vga_clock
*CAP
1 io_in[37] 0.000310538
-2 *419:io_in[37] 0.00101523
-3 *31:16 0.0426983
-4 *31:15 0.0416831
-5 *31:13 0.0466316
-6 *31:11 0.0469421
-7 *419:io_in[37] *72:8 0
-8 *419:io_in[37] *74:8 0
-9 *419:io_in[37] *106:10 0.00503564
-10 *31:13 *127:8 0
-11 *31:13 *165:8 0
-12 *31:16 *34:8 0
+2 *419:io_in[37] 0.00937309
+3 *31:18 0.00937309
+4 *31:16 0.0289142
+5 *31:15 0.0289142
+6 *31:13 0.00829137
+7 *31:11 0.00860191
*RES
1 io_in[37] *31:11 2.835
-2 *31:11 *31:13 480.15
+2 *31:11 *31:13 89.91
3 *31:13 *31:15 4.5
-4 *31:15 *31:16 410.49
-5 *31:16 *419:io_in[37] 21.915
+4 *31:15 *31:16 288.45
+5 *31:16 *31:18 4.5
+6 *31:18 *419:io_in[37] 98.865
*END
-*D_NET *32 0.364549
+*D_NET *32 0.340504
*CONN
*P io_in[3] I
-*I *419:io_in[3] I *D user_proj_example
+*I *419:io_in[3] I *D wrapped_vga_clock
*CAP
-1 io_in[3] 0.000651608
-2 *419:io_in[3] 0.00320864
-3 *32:11 0.0716685
-4 *32:10 0.0684599
-5 *32:8 0.0170118
-6 *32:7 0.0176634
-7 *32:8 *39:13 0.0166328
-8 *32:8 *70:15 0.168845
-9 *32:11 *87:14 0
-10 *32:11 *89:16 0.000407989
-11 *2:11 *32:11 0
+1 io_in[3] 0.000145659
+2 *419:io_in[3] 0.000587619
+3 *32:19 0.0169639
+4 *32:18 0.0163763
+5 *32:16 0.0172074
+6 *32:15 0.0172074
+7 *32:13 0.0402882
+8 *32:11 0.0404339
+9 *32:19 *39:17 0.00700417
+10 *32:19 *39:21 0.0165993
+11 *32:19 *49:13 0.000686965
+12 *32:19 *72:14 0.143674
+13 *32:19 *92:11 0.000264222
+14 *32:19 *110:13 0.0230646
+15 *7:12 *32:19 0
*RES
-1 io_in[3] *32:7 11.025
-2 *32:7 *32:8 290.43
-3 *32:8 *32:10 4.5
-4 *32:10 *32:11 743.85
-5 *32:11 *419:io_in[3] 34.875
+1 io_in[3] *32:11 1.575
+2 *32:11 *32:13 441.27
+3 *32:13 *32:15 4.5
+4 *32:15 *32:16 170.37
+5 *32:16 *32:18 4.5
+6 *32:18 *32:19 304.47
+7 *32:19 *419:io_in[3] 19.0174
*END
-*D_NET *33 0.368612
+*D_NET *33 0.133035
*CONN
*P io_in[4] I
-*I *419:io_in[4] I *D user_proj_example
+*I *419:io_in[4] I *D wrapped_vga_clock
*CAP
-1 io_in[4] 0.00398561
-2 *419:io_in[4] 0.000180312
-3 *33:15 0.0308478
-4 *33:14 0.0306675
-5 *33:12 0.0194994
-6 *33:11 0.0194994
-7 *33:9 0.016465
-8 *33:7 0.0204506
-9 *33:9 *168:16 0
-10 *33:9 *217:14 0.0514144
-11 *33:9 *294:16 0.00648742
-12 *33:9 *296:16 0
-13 *33:9 *308:8 0
-14 *33:15 *71:9 0.00368042
-15 *33:15 *77:9 0
-16 *33:15 *88:9 0
-17 *33:15 *105:9 0.165434
+1 io_in[4] 0.00395713
+2 *419:io_in[4] 0.0285873
+3 *33:14 0.0324349
+4 *33:9 0.0333411
+5 *33:7 0.0334507
+6 *33:9 *75:11 0.00126412
*RES
1 io_in[4] *33:7 43.425
-2 *33:7 *33:9 244.44
-3 *33:9 *33:11 4.5
-4 *33:11 *33:12 194.49
-5 *33:12 *33:14 4.5
-6 *33:14 *33:15 455.13
-7 *33:15 *419:io_in[4] 15.03
+2 *33:7 *33:9 325.44
+3 *33:9 *33:14 46.89
+4 *33:14 *419:io_in[4] 310.545
*END
-*D_NET *34 0.455944
+*D_NET *34 0.126264
*CONN
*P io_in[5] I
-*I *419:io_in[5] I *D user_proj_example
+*I *419:io_in[5] I *D wrapped_vga_clock
*CAP
-1 io_in[5] 0.044307
-2 *419:io_in[5] 4.40767e-05
-3 *34:11 0.00258666
-4 *34:10 0.00254258
-5 *34:8 0.013807
-6 *34:7 0.013807
-7 *34:5 0.044307
-8 *419:io_in[5] *63:23 0.000165786
-9 *34:8 *106:11 0
-10 *34:11 *35:19 0.158471
-11 *34:11 *63:23 0.00288778
-12 *34:11 *71:9 0.173018
-13 *31:16 *34:8 0
+1 io_in[5] 0.0602513
+2 *419:io_in[5] 0.00288057
+3 *34:5 0.0631318
*RES
-1 io_in[5] *34:5 484.425
-2 *34:5 *34:7 4.5
-3 *34:7 *34:8 130.41
-4 *34:8 *34:10 4.5
-5 *34:10 *34:11 250.47
-6 *34:11 *419:io_in[5] 5.31
+1 io_in[5] *34:5 657.585
+2 *34:5 *419:io_in[5] 37.935
*END
-*D_NET *35 0.385036
+*D_NET *35 0.19885
*CONN
*P io_in[6] I
-*I *419:io_in[6] I *D user_proj_example
+*I *419:io_in[6] I *D wrapped_vga_clock
*CAP
1 io_in[6] 0.000280649
-2 *419:io_in[6] 0.000826912
-3 *35:19 0.00562476
-4 *35:18 0.00479785
-5 *35:16 0.00687912
-6 *35:15 0.00687912
-7 *35:13 0.0438408
-8 *35:11 0.0441215
-9 *419:io_in[6] *63:23 0.0092633
-10 *419:io_in[6] *69:8 0
-11 *419:io_in[6] *73:10 0
-12 *35:19 *63:7 0.00503574
-13 *35:19 *63:9 0.0977309
-14 *35:19 *63:23 4.14464e-05
-15 *35:19 *71:9 0.00124339
-16 *35:19 *73:10 0
-17 *34:11 *35:19 0.158471
+2 *419:io_in[6] 0.0015154
+3 *35:19 0.0268495
+4 *35:18 0.0268491
+5 *35:13 0.0386924
+6 *35:11 0.037458
+7 *419:io_in[6] *52:13 0
+8 *35:19 *419:io_in[9] 0
+9 *35:19 *51:17 0.0672054
*RES
1 io_in[6] *35:11 2.655
-2 *35:11 *35:13 479.07
-3 *35:13 *35:15 4.5
-4 *35:15 *35:16 68.49
-5 *35:16 *35:18 4.5
-6 *35:18 *35:19 234.81
-7 *35:19 *419:io_in[6] 27.81
+2 *35:11 *35:13 404.73
+3 *35:13 *35:18 24.03
+4 *35:18 *35:19 318.69
+5 *35:19 *419:io_in[6] 27.3404
*END
-*D_NET *36 0.470964
+*D_NET *36 0.154907
*CONN
*P io_in[7] I
-*I *419:io_in[7] I *D user_proj_example
+*I *419:io_in[7] I *D wrapped_vga_clock
*CAP
-1 io_in[7] 0.0040141
-2 *419:io_in[7] 0.000415593
-3 *36:9 0.039208
-4 *36:7 0.0428065
-5 *36:9 *77:9 0.38452
+1 io_in[7] 0.000215438
+2 *419:io_in[7] 0.0300633
+3 *36:18 0.0300633
+4 *36:16 0.0148348
+5 *36:15 0.0148348
+6 *36:13 0.0323397
+7 *36:11 0.0325552
*RES
-1 io_in[7] *36:7 43.425
-2 *36:7 *36:9 676.8
-3 *36:9 *419:io_in[7] 16.83
+1 io_in[7] *36:11 2.115
+2 *36:11 *36:13 352.17
+3 *36:13 *36:15 4.5
+4 *36:15 *36:16 147.51
+5 *36:16 *36:18 4.5
+6 *36:18 *419:io_in[7] 326.745
*END
-*D_NET *37 0.144111
+*D_NET *37 0.188182
*CONN
*P io_in[8] I
-*I *419:io_in[8] I *D user_proj_example
+*I *419:io_in[8] I *D wrapped_vga_clock
*CAP
1 io_in[8] 0.000145659
-2 *419:io_in[8] 4.01718e-05
-3 *37:16 0.0062618
-4 *37:15 0.00622163
-5 *37:13 0.0656478
-6 *37:11 0.0657934
-7 *37:13 *54:12 0
+2 *419:io_in[8] 0.000980041
+3 *37:19 0.0291341
+4 *37:18 0.0281541
+5 *37:16 0.0147484
+6 *37:15 0.0147484
+7 *37:13 0.0362613
+8 *37:11 0.0364069
+9 *37:19 *93:11 0.00752255
+10 *37:19 *97:13 0
+11 *419:io_in[13] *37:19 0
+12 *14:17 *37:19 0.0200808
*RES
1 io_in[8] *37:11 1.575
-2 *37:11 *37:13 712.53
+2 *37:11 *37:13 395.37
3 *37:13 *37:15 4.5
-4 *37:15 *37:16 59.67
-5 *37:16 *419:io_in[8] 0.405
+4 *37:15 *37:16 147.33
+5 *37:16 *37:18 4.5
+6 *37:18 *37:19 323.37
+7 *37:19 *419:io_in[8] 22.7974
*END
-*D_NET *38 0.29889
+*D_NET *38 0.175364
*CONN
*P io_in[9] I
-*I *419:io_in[9] I *D user_proj_example
+*I *419:io_in[9] I *D wrapped_vga_clock
*CAP
-1 io_in[9] 0.0039856
-2 *419:io_in[9] 0.00152778
-3 *38:15 0.00740946
-4 *38:14 0.00588168
-5 *38:12 0.0113518
-6 *38:11 0.0113518
-7 *38:9 0.045339
-8 *38:7 0.0493246
-9 *419:io_in[9] *113:5 0
-10 *38:15 *45:10 0.0826234
-11 *38:15 *92:10 0.0777741
-12 *419:io_in[14] *38:15 0.002321
-13 *29:19 *38:15 0
+1 io_in[9] 0.00401407
+2 *419:io_in[9] 0.00139047
+3 *38:12 0.0225204
+4 *38:11 0.0211299
+5 *38:9 0.0610837
+6 *38:7 0.0650977
+7 *419:io_in[9] *93:11 0.000127448
+8 *6:12 *38:12 0
+9 *35:19 *419:io_in[9] 0
*RES
1 io_in[9] *38:7 43.425
-2 *38:7 *38:9 495.54
+2 *38:7 *38:9 665.64
3 *38:9 *38:11 4.5
-4 *38:11 *38:12 112.05
-5 *38:12 *38:14 4.5
-6 *38:14 *38:15 167.49
-7 *38:15 *419:io_in[9] 18.315
+4 *38:11 *38:12 210.87
+5 *38:12 *419:io_in[9] 32.2474
*END
-*D_NET *39 0.665746
+*D_NET *39 0.214907
*CONN
*P io_oeb[0] O
-*I *419:io_oeb[0] O *D user_proj_example
+*I *419:io_oeb[0] O *D wrapped_vga_clock
*CAP
-1 io_oeb[0] 0.000621435
-2 *419:io_oeb[0] 0.000218713
-3 *39:13 0.0170058
-4 *39:12 0.0163844
-5 *39:10 0.0510574
-6 *39:9 0.0510574
-7 *39:7 0.00665096
-8 *39:5 0.00686968
-9 *39:7 *66:13 0.00281101
-10 *39:7 *103:13 0.0151892
-11 *39:10 *220:14 0.00109419
-12 *39:10 *224:10 0.00621689
-13 *39:10 *235:10 0.305937
-14 *39:10 *252:16 0.00786962
-15 *12:10 *39:13 0
-16 *12:14 *39:7 0.160129
-17 *32:8 *39:13 0.0166328
+1 io_oeb[0] 0.000310538
+2 *419:io_oeb[0] 0.00130657
+3 *39:25 0.0607264
+4 *39:24 0.0604159
+5 *39:22 0.032346
+6 *39:21 0.0336188
+7 *39:17 0.00257944
+8 *7:12 *39:17 0
+9 *7:12 *39:21 0
+10 *32:19 *39:17 0.00700417
+11 *32:19 *39:21 0.0165993
*RES
-1 *419:io_oeb[0] *39:5 2.205
-2 *39:5 *39:7 235.17
-3 *39:7 *39:9 4.5
-4 *39:9 *39:10 765.99
-5 *39:10 *39:12 4.5
-6 *39:12 *39:13 174.33
-7 *39:13 io_oeb[0] 10.845
+1 *419:io_oeb[0] *39:17 31.0774
+2 *39:17 *39:21 28.53
+3 *39:21 *39:22 321.39
+4 *39:22 *39:24 4.5
+5 *39:24 *39:25 662.67
+6 *39:25 io_oeb[0] 2.835
*END
-*D_NET *40 0.178336
+*D_NET *40 0.204425
*CONN
*P io_oeb[10] O
-*I *419:io_oeb[10] O *D user_proj_example
+*I *419:io_oeb[10] O *D wrapped_vga_clock
*CAP
1 io_oeb[10] 0.000310538
-2 *419:io_oeb[10] 0.00203937
-3 *40:14 0.0621581
-4 *40:13 0.0618476
-5 *40:11 0.0225356
-6 *40:10 0.024575
-7 *40:10 *50:10 0
-8 *40:10 *78:9 0
-9 *40:10 *90:11 0
-10 *40:11 *43:7 0
-11 *40:11 *43:9 0
-12 *419:io_in[13] *40:11 0
-13 *27:19 *40:10 0.00486988
+2 *419:io_oeb[10] 0.00106035
+3 *40:16 0.0604927
+4 *40:15 0.0601822
+5 *40:13 0.0324695
+6 *40:12 0.0335298
+7 *40:12 *55:14 0
+8 *40:12 *61:11 0.0141125
+9 *40:12 *101:11 4.89586e-05
+10 *8:16 *40:12 0.000683868
+11 *17:8 *40:12 0.00153439
*RES
-1 *419:io_oeb[10] *40:10 37.035
-2 *40:10 *40:11 222.93
-3 *40:11 *40:13 4.5
-4 *40:13 *40:14 673.47
-5 *40:14 io_oeb[10] 2.835
+1 *419:io_oeb[10] *40:12 32.625
+2 *40:12 *40:13 324.27
+3 *40:13 *40:15 4.5
+4 *40:15 *40:16 657.27
+5 *40:16 io_oeb[10] 2.835
*END
-*D_NET *41 0.193148
+*D_NET *41 0.249775
*CONN
*P io_oeb[11] O
-*I *419:io_oeb[11] O *D user_proj_example
+*I *419:io_oeb[11] O *D wrapped_vga_clock
*CAP
-1 io_oeb[11] 0.000237175
-2 *419:io_oeb[11] 0.000131093
-3 *41:10 0.0633868
-4 *41:9 0.0631496
-5 *41:7 0.0330559
-6 *41:5 0.033187
+1 io_oeb[11] 0.00111512
+2 *419:io_oeb[11] 0.0375001
+3 *41:8 0.0420594
+4 *41:7 0.0409443
+5 *41:5 0.0375001
+6 *41:5 *110:17 0.0906558
*RES
-1 *419:io_oeb[11] *41:5 1.305
-2 *41:5 *41:7 294.57
-3 *41:7 *41:9 4.5
-4 *41:9 *41:10 688.23
-5 *41:10 io_oeb[11] 2.295
+1 *419:io_oeb[11] *41:5 666.945
+2 *41:5 *41:7 4.5
+3 *41:7 *41:8 408.87
+4 *41:8 io_oeb[11] 16.425
*END
-*D_NET *42 0.271318
+*D_NET *42 0.372954
*CONN
*P io_oeb[12] O
-*I *419:io_oeb[12] O *D user_proj_example
+*I *419:io_oeb[12] O *D wrapped_vga_clock
*CAP
1 io_oeb[12] 0.000167681
-2 *419:io_oeb[12] 0.00373079
-3 *42:16 0.0486713
-4 *42:15 0.0485037
-5 *42:13 0.0326239
-6 *42:12 0.0326239
-7 *42:10 0.00913484
-8 *42:9 0.0128656
-9 *42:10 *46:10 0.0829967
+2 *419:io_oeb[12] 0.000308523
+3 *42:14 0.0598027
+4 *42:13 0.059635
+5 *42:11 0.0556261
+6 *42:10 0.0556261
+7 *42:8 0.00248335
+8 *42:7 0.00279187
+9 *42:8 *44:8 0.0551395
+10 *42:8 *53:8 0.000725313
+11 *42:8 *64:8 0.0185872
+12 *42:8 *73:8 0.00692089
+13 *22:11 *42:8 0.0551395
*RES
-1 *419:io_oeb[12] *42:9 39.375
-2 *42:9 *42:10 149.85
-3 *42:10 *42:12 4.5
-4 *42:12 *42:13 325.35
-5 *42:13 *42:15 4.5
-6 *42:15 *42:16 530.37
-7 *42:16 io_oeb[12] 1.755
+1 *419:io_oeb[12] *42:7 7.245
+2 *42:7 *42:8 109.89
+3 *42:8 *42:10 4.5
+4 *42:10 *42:11 554.31
+5 *42:11 *42:13 4.5
+6 *42:13 *42:14 651.87
+7 *42:14 io_oeb[12] 1.755
*END
-*D_NET *43 0.208971
+*D_NET *43 0.244656
*CONN
*P io_oeb[13] O
-*I *419:io_oeb[13] O *D user_proj_example
+*I *419:io_oeb[13] O *D wrapped_vga_clock
*CAP
1 io_oeb[13] 0.00010158
-2 *419:io_oeb[13] 0.00240663
-3 *43:12 0.0616661
-4 *43:11 0.0615645
-5 *43:9 0.040413
-6 *43:7 0.0428196
-7 *40:11 *43:7 0
-8 *40:11 *43:9 0
+2 *419:io_oeb[13] 0.000379914
+3 *43:13 0.0698042
+4 *43:12 0.0697026
+5 *43:10 0.0520407
+6 *43:9 0.0524206
+7 *43:10 *70:10 0.000205865
*RES
-1 *419:io_oeb[13] *43:7 22.005
-2 *43:7 *43:9 402.48
-3 *43:9 *43:11 4.5
-4 *43:11 *43:12 672.03
-5 *43:12 io_oeb[13] 1.215
+1 *419:io_oeb[13] *43:9 12.9052
+2 *43:9 *43:10 520.29
+3 *43:10 *43:12 4.5
+4 *43:12 *43:13 761.13
+5 *43:13 io_oeb[13] 1.215
*END
-*D_NET *44 0.224485
+*D_NET *44 0.348745
*CONN
*P io_oeb[14] O
-*I *419:io_oeb[14] O *D user_proj_example
+*I *419:io_oeb[14] O *D wrapped_vga_clock
*CAP
-1 io_oeb[14] 0.0584334
-2 *419:io_oeb[14] 0.00225091
-3 *44:13 0.0584334
-4 *44:11 0.0485635
-5 *44:10 0.0508144
-6 *44:10 *50:10 0
-7 *44:10 *82:13 0
-8 *44:11 *85:9 0
-9 *27:19 *44:10 0.00598901
+1 io_oeb[14] 0.0568877
+2 *419:io_oeb[14] 0.000332209
+3 *44:13 0.0568877
+4 *44:11 0.0686129
+5 *44:10 0.0686129
+6 *44:8 0.00253211
+7 *44:7 0.00286432
+8 *44:8 *53:8 0.0231874
+9 *44:8 *73:8 0.000745992
+10 *44:8 *78:8 0.00244792
+11 *44:8 *86:14 0.0104942
+12 *11:8 io_oeb[14] 0
+13 *42:8 *44:8 0.0551395
*RES
-1 *419:io_oeb[14] *44:10 41.895
-2 *44:10 *44:11 482.13
-3 *44:11 *44:13 4.5
-4 *44:13 io_oeb[14] 638.325
+1 *419:io_oeb[14] *44:7 7.425
+2 *44:7 *44:8 109.53
+3 *44:8 *44:10 4.5
+4 *44:10 *44:11 684.09
+5 *44:11 *44:13 4.5
+6 *44:13 io_oeb[14] 622.125
*END
-*D_NET *45 0.475664
+*D_NET *45 0.39008
*CONN
*P io_oeb[15] O
-*I *419:io_oeb[15] O *D user_proj_example
+*I *419:io_oeb[15] O *D wrapped_vga_clock
*CAP
-1 io_oeb[15] 0.000675824
-2 *419:io_oeb[15] 0.00156531
-3 *45:16 0.0285077
-4 *45:15 0.0278319
-5 *45:13 0.0482092
-6 *45:12 0.0482092
-7 *45:10 0.00636367
-8 *45:9 0.00792898
-9 *45:13 *101:9 0
-10 *45:16 io_oeb[19] 0
-11 *45:16 *46:16 0.182095
-12 *45:16 *87:20 0.037364
-13 *419:io_in[14] *45:10 0.00428972
-14 *29:19 *45:10 0
-15 *38:15 *45:10 0.0826234
+1 io_oeb[15] 0.000224243
+2 *419:io_oeb[15] 0.00238098
+3 *45:17 0.0695672
+4 *45:16 0.0693429
+5 *45:14 0.0201261
+6 *45:13 0.0225071
+7 *45:13 *53:8 0
+8 *45:13 *63:7 0
+9 *45:13 *63:8 0.0163505
+10 *45:13 *72:8 0.00012693
+11 *45:13 *86:14 0
+12 *45:14 *75:10 0.000901462
+13 *45:14 *82:11 0.034504
+14 *45:14 *109:11 0.0762946
+15 *10:16 *45:14 0.0777535
*RES
-1 *419:io_oeb[15] *45:9 18.495
-2 *45:9 *45:10 122.31
-3 *45:10 *45:12 4.5
-4 *45:12 *45:13 480.33
-5 *45:13 *45:15 4.5
-6 *45:15 *45:16 446.13
-7 *45:16 io_oeb[15] 11.025
+1 *419:io_oeb[15] *45:13 47.565
+2 *45:13 *45:14 602.19
+3 *45:14 *45:16 4.5
+4 *45:16 *45:17 692.37
+5 *45:17 io_oeb[15] 2.475
*END
-*D_NET *46 0.418426
+*D_NET *46 0.225466
*CONN
*P io_oeb[16] O
-*I *419:io_oeb[16] O *D user_proj_example
+*I *419:io_oeb[16] O *D wrapped_vga_clock
*CAP
-1 io_oeb[16] 0.000712394
-2 *419:io_oeb[16] 0.00379565
-3 *46:16 0.0141149
-4 *46:15 0.0134025
-5 *46:13 0.0460361
-6 *46:12 0.0460361
-7 *46:10 0.0127204
-8 *46:9 0.016516
-9 *6:12 *46:9 0
-10 *42:10 *46:10 0.0829967
-11 *45:16 *46:16 0.182095
+1 io_oeb[16] 0.000708774
+2 *419:io_oeb[16] 0.0377949
+3 *46:15 0.00491899
+4 *46:13 0.00520844
+5 *46:8 0.0613695
+6 *46:7 0.0603713
+7 *46:5 0.0377949
+8 *46:8 io_out[17] 3.68254e-05
+9 *46:13 *85:11 0.000435189
+10 *9:8 *46:13 0.00389597
+11 *9:8 *46:15 0.0129313
*RES
-1 *419:io_oeb[16] *46:9 39.735
-2 *46:9 *46:10 190.35
-3 *46:10 *46:12 4.5
-4 *46:12 *46:13 459.27
-5 *46:13 *46:15 4.5
-6 *46:15 *46:16 263.61
-7 *46:16 io_oeb[16] 10.845
+1 *419:io_oeb[16] *46:5 410.445
+2 *46:5 *46:7 4.5
+3 *46:7 *46:8 602.73
+4 *46:8 *46:13 22.41
+5 *46:13 *46:15 54.36
+6 *46:15 io_oeb[16] 10.845
*END
-*D_NET *47 0.163543
+*D_NET *47 0.217291
*CONN
*P io_oeb[17] O
-*I *419:io_oeb[17] O *D user_proj_example
+*I *419:io_oeb[17] O *D wrapped_vga_clock
*CAP
1 io_oeb[17] 0.000164983
-2 *419:io_oeb[17] 7.58801e-05
-3 *47:13 0.0451834
-4 *47:12 0.0450184
-5 *47:10 0.0311744
-6 *47:9 0.0311744
-7 *47:7 0.00533812
-8 *47:5 0.005414
-9 *47:10 *100:14 0
+2 *419:io_oeb[17] 0.00310524
+3 *47:17 0.0684647
+4 *47:16 0.0682997
+5 *47:14 0.0336875
+6 *47:13 0.0336875
+7 *47:11 0.00310524
+8 *47:11 *75:11 0.00428972
+9 *47:11 *84:10 0.00248679
+10 *47:11 *86:14 0
*RES
-1 *419:io_oeb[17] *47:5 0.765
-2 *47:5 *47:7 50.13
-3 *47:7 *47:9 4.5
-4 *47:9 *47:10 337.59
-5 *47:10 *47:12 4.5
-6 *47:12 *47:13 449.37
-7 *47:13 io_oeb[17] 1.935
+1 *419:io_oeb[17] *47:11 45.945
+2 *47:11 *47:13 4.5
+3 *47:13 *47:14 366.75
+4 *47:14 *47:16 4.5
+5 *47:16 *47:17 681.57
+6 *47:17 io_oeb[17] 1.935
*END
-*D_NET *48 0.142381
+*D_NET *48 0.214596
*CONN
*P io_oeb[18] O
-*I *419:io_oeb[18] O *D user_proj_example
+*I *419:io_oeb[18] O *D wrapped_vga_clock
*CAP
-1 io_oeb[18] 0.000290594
-2 *419:io_oeb[18] 0.00242914
-3 *48:15 0.0447814
-4 *48:14 0.0444908
-5 *48:12 0.0204943
-6 *48:11 0.0239799
-7 *48:7 0.00591475
+1 io_oeb[18] 0.000635658
+2 *419:io_oeb[18] 0.0139917
+3 *48:11 0.00675403
+4 *48:10 0.00611837
+5 *48:8 0.0624614
+6 *48:7 0.0624614
+7 *48:5 0.0139917
+8 *48:11 *87:17 0.0317688
+9 *9:8 *48:11 0.0164128
*RES
-1 *419:io_oeb[18] *48:7 22.005
-2 *48:7 *48:11 38.34
-3 *48:11 *48:12 221.49
-4 *48:12 *48:14 4.5
-5 *48:14 *48:15 443.97
-6 *48:15 io_oeb[18] 3.015
+1 *419:io_oeb[18] *48:5 151.245
+2 *48:5 *48:7 4.5
+3 *48:7 *48:8 623.25
+4 *48:8 *48:10 4.5
+5 *48:10 *48:11 117.27
+6 *48:11 io_oeb[18] 10.665
*END
-*D_NET *49 0.14018
+*D_NET *49 0.210993
*CONN
*P io_oeb[19] O
-*I *419:io_oeb[19] O *D user_proj_example
+*I *419:io_oeb[19] O *D wrapped_vga_clock
*CAP
-1 io_oeb[19] 0.00226796
-2 *419:io_oeb[19] 0.00190966
-3 *49:13 0.0500275
-4 *49:12 0.0477595
-5 *49:10 0.0021327
-6 *49:9 0.00404236
-7 *49:10 *52:10 0.0105067
-8 *49:10 *85:10 0.0094995
-9 *49:10 *91:10 0.00248675
-10 *49:10 *112:16 0.00954693
-11 *49:13 *101:9 0
-12 *419:io_in[19] *49:9 0
-13 *45:16 io_oeb[19] 0
+1 io_oeb[19] 0.000104982
+2 *419:io_oeb[19] 0.00158787
+3 *49:20 0.0577727
+4 *49:19 0.0576677
+5 *49:17 0.0155125
+6 *49:16 0.0169152
+7 *49:13 0.00299053
+8 *49:13 *98:13 0.0121229
+9 *49:16 *98:13 6.13758e-05
+10 *419:io_in[30] *49:13 0
+11 *9:14 *49:17 0.0455705
+12 *32:19 *49:13 0.000686965
*RES
-1 *419:io_oeb[19] *49:9 21.555
-2 *49:9 *49:10 94.77
-3 *49:10 *49:12 4.5
-4 *49:12 *49:13 476.01
-5 *49:13 io_oeb[19] 32.535
+1 *419:io_oeb[19] *49:13 44.4874
+2 *49:13 *49:16 18.09
+3 *49:16 *49:17 197.01
+4 *49:17 *49:19 4.5
+5 *49:19 *49:20 576.27
+6 *49:20 io_oeb[19] 1.395
*END
-*D_NET *50 0.533333
+*D_NET *50 0.20375
*CONN
*P io_oeb[1] O
-*I *419:io_oeb[1] O *D user_proj_example
+*I *419:io_oeb[1] O *D wrapped_vga_clock
*CAP
1 io_oeb[1] 0.000237175
-2 *419:io_oeb[1] 0.00103768
-3 *50:16 0.0240483
-4 *50:15 0.0238111
-5 *50:13 0.0360209
-6 *50:12 0.0360209
-7 *50:10 0.0307159
-8 *50:9 0.0317536
-9 *50:10 *61:10 0.347822
-10 *50:10 *64:10 0.00186502
-11 *50:13 *149:5 0
-12 *27:19 *50:10 0
-13 *40:10 *50:10 0
-14 *44:10 *50:10 0
+2 *419:io_oeb[1] 0.000867157
+3 *50:11 0.0716912
+4 *50:10 0.0714541
+5 *50:8 0.018975
+6 *50:7 0.0198422
+7 *8:19 *50:8 0.0206836
*RES
-1 *419:io_oeb[1] *50:9 14.175
-2 *50:9 *50:10 511.65
-3 *50:10 *50:12 4.5
-4 *50:12 *50:13 356.49
-5 *50:13 *50:15 4.5
-6 *50:15 *50:16 252.27
-7 *50:16 io_oeb[1] 2.295
+1 *419:io_oeb[1] *50:7 13.005
+2 *50:7 *50:8 202.05
+3 *50:8 *50:10 4.5
+4 *50:10 *50:11 782.91
+5 *50:11 io_oeb[1] 2.295
*END
-*D_NET *51 0.101935
+*D_NET *51 0.207378
*CONN
*P io_oeb[20] O
-*I *419:io_oeb[20] O *D user_proj_example
+*I *419:io_oeb[20] O *D wrapped_vga_clock
*CAP
-1 io_oeb[20] 0.00111678
-2 *419:io_oeb[20] 0.00261639
-3 *51:11 0.0483511
-4 *51:9 0.0498507
+1 io_oeb[20] 0.000224243
+2 *419:io_oeb[20] 0.0017478
+3 *51:20 0.0586936
+4 *51:19 0.0584693
+5 *51:17 0.00712691
+6 *51:16 0.00887471
+7 *51:16 *92:11 0.00503575
+8 *35:19 *51:17 0.0672054
*RES
-1 *419:io_oeb[20] *51:9 23.715
-2 *51:9 *51:11 469.98
-3 *51:11 io_oeb[20] 20.115
+1 *419:io_oeb[20] *51:16 42.0574
+2 *51:16 *51:17 118.89
+3 *51:17 *51:19 4.5
+4 *51:19 *51:20 584.19
+5 *51:20 io_oeb[20] 2.475
*END
-*D_NET *52 0.19808
+*D_NET *52 0.12065
*CONN
*P io_oeb[21] O
-*I *419:io_oeb[21] O *D user_proj_example
+*I *419:io_oeb[21] O *D wrapped_vga_clock
*CAP
-1 io_oeb[21] 0.00190563
-2 *419:io_oeb[21] 0.00188598
-3 *52:13 0.0496387
-4 *52:12 0.047733
-5 *52:10 0.00317576
-6 *52:9 0.00506174
-7 io_oeb[21] *53:16 0
-8 *52:10 *66:10 0.00219459
-9 *52:10 *91:10 0.0737954
-10 *52:10 *112:16 0.00218216
-11 *49:10 *52:10 0.0105067
+1 io_oeb[21] 0.00112874
+2 *419:io_oeb[21] 0.00103053
+3 *52:14 0.0592491
+4 *52:13 0.0591509
+5 io_oeb[21] *87:17 0
+6 *52:13 *93:11 0
+7 *52:13 *98:13 8.39292e-05
+8 *419:io_in[27] *52:14 6.90477e-06
+9 *419:io_in[6] *52:13 0
+10 *11:8 io_oeb[21] 0
*RES
-1 *419:io_oeb[21] *52:9 21.375
-2 *52:9 *52:10 106.83
-3 *52:10 *52:12 4.5
-4 *52:12 *52:13 476.19
-5 *52:13 io_oeb[21] 28.395
+1 *419:io_oeb[21] *52:13 28.2874
+2 *52:13 *52:14 580.77
+3 *52:14 io_oeb[21] 20.295
*END
-*D_NET *53 0.152375
+*D_NET *53 0.249316
*CONN
*P io_oeb[22] O
-*I *419:io_oeb[22] O *D user_proj_example
+*I *419:io_oeb[22] O *D wrapped_vga_clock
*CAP
1 io_oeb[22] 0.000671366
-2 *419:io_oeb[22] 0.00119076
-3 *53:16 0.0107725
-4 *53:15 0.0101011
-5 *53:13 0.0484647
-6 *53:12 0.0484647
-7 *53:10 0.00726104
-8 *53:9 0.0084518
-9 *53:10 *109:10 0.0169971
-10 *53:16 io_out[22] 0
-11 io_oeb[21] *53:16 0
-12 *29:19 *53:10 0
+2 *419:io_oeb[22] 0.000360359
+3 *53:16 0.00438783
+4 *53:11 0.0726604
+5 *53:10 0.0689439
+6 *53:8 0.00395757
+7 *53:7 0.00431793
+8 *53:8 *64:8 0.0378595
+9 *53:8 *86:14 0.00333644
+10 *53:8 *95:8 0.0270431
+11 *53:8 *96:8 0.00186498
+12 *53:16 io_out[22] 0
+13 *42:8 *53:8 0.000725313
+14 *44:8 *53:8 0.0231874
+15 *45:13 *53:8 0
*RES
-1 *419:io_oeb[22] *53:9 14.895
-2 *53:9 *53:10 123.03
-3 *53:10 *53:12 4.5
-4 *53:12 *53:13 483.39
-5 *53:13 *53:15 4.5
-6 *53:15 *53:16 110.43
-7 *53:16 io_oeb[22] 11.025
+1 *419:io_oeb[22] *53:7 7.605
+2 *53:7 *53:8 99.63
+3 *53:8 *53:10 4.5
+4 *53:10 *53:11 688.23
+5 *53:11 *53:16 49.23
+6 *53:16 io_oeb[22] 6.525
*END
-*D_NET *54 0.166234
+*D_NET *54 0.211562
*CONN
*P io_oeb[23] O
-*I *419:io_oeb[23] O *D user_proj_example
+*I *419:io_oeb[23] O *D wrapped_vga_clock
*CAP
1 io_oeb[23] 0.000290594
-2 *419:io_oeb[23] 0.00242331
-3 *54:15 0.0444604
-4 *54:14 0.0441698
-5 *54:12 0.03248
-6 *54:11 0.0362334
-7 *54:7 0.00617674
-8 *37:13 *54:12 0
+2 *419:io_oeb[23] 0.000606807
+3 *54:17 0.00718315
+4 *54:16 0.00689256
+5 *54:14 0.0127092
+6 *54:13 0.0127092
+7 *54:11 0.0629723
+8 *54:10 0.0629723
+9 *54:8 0.0011428
+10 *54:7 0.00174961
+11 *54:8 *59:8 0.00633741
+12 *54:8 *63:8 0.00373018
+13 *25:19 *54:8 0.032266
*RES
-1 *419:io_oeb[23] *54:7 22.005
-2 *54:7 *54:11 41.04
-3 *54:11 *54:12 351.09
-4 *54:12 *54:14 4.5
-5 *54:14 *54:15 441.27
-6 *54:15 io_oeb[23] 3.015
+1 *419:io_oeb[23] *54:7 9.945
+2 *54:7 *54:8 62.91
+3 *54:8 *54:10 4.5
+4 *54:10 *54:11 628.47
+5 *54:11 *54:13 4.5
+6 *54:13 *54:14 139.05
+7 *54:14 *54:16 4.5
+8 *54:16 *54:17 68.67
+9 *54:17 io_oeb[23] 3.015
*END
-*D_NET *55 0.157848
+*D_NET *55 0.243444
*CONN
*P io_oeb[24] O
-*I *419:io_oeb[24] O *D user_proj_example
+*I *419:io_oeb[24] O *D wrapped_vga_clock
*CAP
-1 io_oeb[24] 0.00126685
-2 *419:io_oeb[24] 0.00264131
-3 *55:14 0.0342216
-4 *55:13 0.0329547
-5 *55:11 0.0420612
-6 *55:9 0.0447025
-7 *419:io_in[24] *55:11 0
+1 io_oeb[24] 0.00125262
+2 *419:io_oeb[24] 0.000469779
+3 *55:17 0.0261522
+4 *55:16 0.0248996
+5 *55:14 0.0537262
+6 *55:13 0.0537835
+7 *55:8 0.00260507
+8 *55:7 0.00301758
+9 *55:8 *90:11 0.0483027
+10 *55:8 *107:8 0.0228931
+11 *55:13 *71:11 0.00317066
+12 *55:13 *79:11 0.00317066
+13 *17:8 *55:14 0
+14 *40:12 *55:14 0
*RES
-1 *419:io_oeb[24] *55:9 24.255
-2 *55:9 *55:11 418.68
-3 *55:11 *55:13 4.5
-4 *55:13 *55:14 359.28
-5 *55:14 io_oeb[24] 13.185
+1 *419:io_oeb[24] *55:7 9.045
+2 *55:7 *55:8 70.83
+3 *55:8 *55:13 13.59
+4 *55:13 *55:14 536.31
+5 *55:14 *55:16 4.5
+6 *55:16 *55:17 271.44
+7 *55:17 io_oeb[24] 13.185
*END
-*D_NET *56 0.145737
+*D_NET *56 0.204769
*CONN
*P io_oeb[25] O
-*I *419:io_oeb[25] O *D user_proj_example
+*I *419:io_oeb[25] O *D wrapped_vga_clock
*CAP
1 io_oeb[25] 0.000258912
-2 *419:io_oeb[25] 0.00258278
-3 *56:14 0.0352556
-4 *56:13 0.0349967
-5 *56:11 0.0350301
-6 *56:9 0.0376128
-7 *22:8 *56:11 0
+2 *419:io_oeb[25] 0.000974214
+3 *56:17 0.00878101
+4 *56:16 0.0085221
+5 *56:14 0.0458284
+6 *56:13 0.0458284
+7 *56:11 0.00660797
+8 *56:10 0.00758218
+9 *56:11 *93:11 0.0803856
*RES
-1 *419:io_oeb[25] *56:9 23.715
-2 *56:9 *56:11 348.48
+1 *419:io_oeb[25] *56:10 22.7974
+2 *56:10 *56:11 121.77
3 *56:11 *56:13 4.5
-4 *56:13 *56:14 380.25
-5 *56:14 io_oeb[25] 2.475
+4 *56:13 *56:14 457.83
+5 *56:14 *56:16 4.5
+6 *56:16 *56:17 92.61
+7 *56:17 io_oeb[25] 2.475
*END
-*D_NET *57 0.757642
+*D_NET *57 0.273654
*CONN
*P io_oeb[26] O
-*I *419:io_oeb[26] O *D user_proj_example
+*I *419:io_oeb[26] O *D wrapped_vga_clock
*CAP
-1 io_oeb[26] 0.000657415
-2 *419:io_oeb[26] 0.000561886
-3 *57:11 0.0127702
-4 *57:10 0.0121128
-5 *57:8 0.00418302
-6 *57:7 0.0047449
-7 *57:7 *95:9 0
-8 *57:8 *94:8 0.261174
-9 *57:8 *98:8 0.264407
-10 *57:11 *58:13 0.142576
-11 *57:11 *94:11 0.0170829
-12 *57:11 *98:11 0.0263302
-13 *10:16 *57:8 0.0011605
-14 *30:8 *57:11 0.00988149
+1 io_oeb[26] 0.000123625
+2 *419:io_oeb[26] 0.000691043
+3 *57:11 0.02702
+4 *57:10 0.0268964
+5 *57:8 0.0330405
+6 *57:7 0.0337316
+7 *57:8 *60:8 0.15215
*RES
-1 *419:io_oeb[26] *57:7 9.225
-2 *57:7 *57:8 383.13
+1 *419:io_oeb[26] *57:7 11.385
+2 *57:7 *57:8 428.31
3 *57:8 *57:10 4.5
-4 *57:10 *57:11 298.71
-5 *57:11 io_oeb[26] 11.025
+4 *57:10 *57:11 291.15
+5 *57:11 io_oeb[26] 1.395
*END
-*D_NET *58 0.59721
+*D_NET *58 0.130419
*CONN
*P io_oeb[27] O
-*I *419:io_oeb[27] O *D user_proj_example
+*I *419:io_oeb[27] O *D wrapped_vga_clock
*CAP
-1 io_oeb[27] 0.000641502
-2 *419:io_oeb[27] 0.00287591
-3 *58:13 0.00299826
-4 *58:12 0.00235676
-5 *58:10 0.0209352
-6 *58:9 0.0238112
-7 *58:10 *101:10 0
-8 *58:13 *94:11 0.142576
-9 *20:19 *58:10 0.25844
-10 *57:11 *58:13 0.142576
+1 io_oeb[27] 0.000332275
+2 *419:io_oeb[27] 0.000241929
+3 *58:14 0.0138566
+4 *58:13 0.0135243
+5 *58:11 0.0427975
+6 *58:10 0.0427975
+7 *58:8 0.00286209
+8 *58:7 0.00310402
+9 *58:8 *89:8 0.00151268
+10 *58:8 *96:8 0.00298401
+11 *58:8 *109:11 0.000251762
+12 *22:11 *58:8 0.00615439
*RES
-1 *419:io_oeb[27] *58:9 31.095
-2 *58:9 *58:10 390.15
-3 *58:10 *58:12 4.5
-4 *58:12 *58:13 209.07
-5 *58:13 io_oeb[27] 10.845
+1 *419:io_oeb[27] *58:7 6.705
+2 *58:7 *58:8 48.33
+3 *58:8 *58:10 4.5
+4 *58:10 *58:11 426.87
+5 *58:11 *58:13 4.5
+6 *58:13 *58:14 146.61
+7 *58:14 io_oeb[27] 3.015
*END
-*D_NET *59 0.109025
+*D_NET *59 0.184414
*CONN
*P io_oeb[28] O
-*I *419:io_oeb[28] O *D user_proj_example
+*I *419:io_oeb[28] O *D wrapped_vga_clock
*CAP
1 io_oeb[28] 0.000191629
-2 *419:io_oeb[28] 0.00240718
-3 *59:12 0.0376679
-4 *59:11 0.0374763
-5 *59:9 0.0144375
-6 *59:7 0.0168447
+2 *419:io_oeb[28] 0.000707367
+3 *59:14 0.0139588
+4 *59:13 0.0137672
+5 *59:11 0.0364681
+6 *59:10 0.0364681
+7 *59:8 0.00486682
+8 *59:7 0.00557419
+9 *59:8 *63:8 0.000202052
+10 *59:8 *86:13 0.00172827
+11 *59:8 *90:8 0.0185888
+12 *10:22 *59:8 0.0439538
+13 *25:19 *59:8 0.00160165
+14 *28:5 *59:8 0
+15 *54:8 *59:8 0.00633741
*RES
-1 *419:io_oeb[28] *59:7 22.005
-2 *59:7 *59:9 143.28
-3 *59:9 *59:11 4.5
-4 *59:11 *59:12 404.55
-5 *59:12 io_oeb[28] 1.935
+1 *419:io_oeb[28] *59:7 10.665
+2 *59:7 *59:8 128.79
+3 *59:8 *59:10 4.5
+4 *59:10 *59:11 363.33
+5 *59:11 *59:13 4.5
+6 *59:13 *59:14 149.31
+7 *59:14 io_oeb[28] 1.935
*END
-*D_NET *60 0.0967207
+*D_NET *60 0.288947
*CONN
*P io_oeb[29] O
-*I *419:io_oeb[29] O *D user_proj_example
+*I *419:io_oeb[29] O *D wrapped_vga_clock
*CAP
-1 io_oeb[29] 0.00132382
-2 *419:io_oeb[29] 0.00261935
-3 *60:14 0.0380685
-4 *60:13 0.0367447
-5 *60:11 0.00767252
-6 *60:9 0.0102919
+1 io_oeb[29] 0.00125262
+2 *419:io_oeb[29] 0.000706956
+3 *60:11 0.0271149
+4 *60:10 0.0258623
+5 *60:8 0.0138473
+6 *60:7 0.0145542
+7 *26:16 *60:8 0.0534583
+8 *57:8 *60:8 0.15215
*RES
-1 *419:io_oeb[29] *60:9 24.255
-2 *60:9 *60:11 75.78
-3 *60:11 *60:13 4.5
-4 *60:13 *60:14 397.08
-5 *60:14 io_oeb[29] 13.185
+1 *419:io_oeb[29] *60:7 11.565
+2 *60:7 *60:8 270.63
+3 *60:8 *60:10 4.5
+4 *60:10 *60:11 278.46
+5 *60:11 io_oeb[29] 13.185
*END
-*D_NET *61 0.656647
+*D_NET *61 0.193072
*CONN
*P io_oeb[2] O
-*I *419:io_oeb[2] O *D user_proj_example
+*I *419:io_oeb[2] O *D wrapped_vga_clock
*CAP
1 io_oeb[2] 0.000167681
-2 *419:io_oeb[2] 0.00101364
-3 *61:16 0.0232294
-4 *61:15 0.0230617
-5 *61:13 0.0295498
-6 *61:12 0.0295498
-7 *61:10 0.0178695
-8 *61:9 0.0188831
-9 *61:10 *64:10 0.15673
-10 *61:10 *65:8 0.0019065
-11 *61:10 *109:10 0.00686353
-12 *61:13 *150:13 0
-13 *419:io_in[2] *61:9 0
-14 *50:10 *61:10 0.347822
+2 *419:io_oeb[2] 0.000290299
+3 *61:17 0.0335267
+4 *61:16 0.033359
+5 *61:14 0.0190607
+6 *61:13 0.0190607
+7 *61:11 0.0270467
+8 *61:10 0.027337
+9 *61:11 *70:11 0.0189618
+10 *61:11 *101:11 0.000149208
+11 *7:12 *61:11 0
+12 *8:16 *61:11 0
+13 *40:12 *61:11 0.0141125
*RES
-1 *419:io_oeb[2] *61:9 13.815
-2 *61:9 *61:10 511.65
-3 *61:10 *61:12 4.5
-4 *61:12 *61:13 291.87
-5 *61:13 *61:15 4.5
-6 *61:15 *61:16 244.17
-7 *61:16 io_oeb[2] 1.755
+1 *419:io_oeb[2] *61:10 16.1374
+2 *61:10 *61:11 316.35
+3 *61:11 *61:13 4.5
+4 *61:13 *61:14 189.09
+5 *61:14 *61:16 4.5
+6 *61:16 *61:17 365.67
+7 *61:17 io_oeb[2] 1.755
*END
-*D_NET *62 0.44202
+*D_NET *62 0.0637209
*CONN
*P io_oeb[30] O
-*I *419:io_oeb[30] O *D user_proj_example
+*I *419:io_oeb[30] O *D wrapped_vga_clock
*CAP
-1 io_oeb[30] 0.00225899
-2 *419:io_oeb[30] 0.000478155
-3 *62:8 0.0166092
-4 *62:7 0.0148283
-5 io_oeb[30] *98:11 0.0055852
-6 *62:7 *100:9 0
-7 *62:8 *74:8 0.120173
-8 *62:8 *98:8 0.281566
-9 *10:16 *62:8 0.000507719
-10 *30:8 io_oeb[30] 1.38095e-05
+1 io_oeb[30] 0.00112395
+2 *419:io_oeb[30] 0.0165351
+3 *62:8 0.0153254
+4 *62:7 0.0142014
+5 *62:5 0.0165351
*RES
-1 *419:io_oeb[30] *62:7 8.865
-2 *62:7 *62:8 412.65
-3 *62:8 io_oeb[30] 40.995
+1 *419:io_oeb[30] *62:5 177.165
+2 *62:5 *62:7 4.5
+3 *62:7 *62:8 141.75
+4 *62:8 io_oeb[30] 16.065
*END
-*D_NET *63 0.195672
+*D_NET *63 0.148048
*CONN
*P io_oeb[31] O
-*I *419:io_oeb[31] O *D user_proj_example
+*I *419:io_oeb[31] O *D wrapped_vga_clock
*CAP
-1 io_oeb[31] 0.000123625
-2 *419:io_oeb[31] 0.00202486
-3 *63:31 0.0190512
-4 *63:30 0.0228234
-5 *63:27 0.00456517
-6 *63:23 0.0029359
-7 *63:9 0.00941107
-8 *63:7 0.00916932
-9 *63:7 *73:10 0
-10 *63:9 *73:10 0
-11 *63:23 *69:8 0
-12 *63:23 *71:9 0.000668324
-13 *63:23 *73:10 0
-14 *63:23 *104:9 0.00213967
-15 *63:27 *104:9 0.00243705
-16 *419:io_in[0] *63:27 0.00028598
-17 *419:io_in[1] *63:27 0.00491141
-18 *419:io_in[5] *63:23 0.000165786
-19 *419:io_in[6] *63:23 0.0092633
-20 *34:11 *63:23 0.00288778
-21 *35:19 *63:7 0.00503574
-22 *35:19 *63:9 0.0977309
-23 *35:19 *63:23 4.14464e-05
+1 io_oeb[31] 0.00357479
+2 *419:io_oeb[31] 0.000605598
+3 *63:11 0.019339
+4 *63:10 0.0157643
+5 *63:8 0.0161618
+6 *63:7 0.0167674
+7 *63:8 *72:8 0.0013553
+8 *63:8 *86:13 0.000397886
+9 *63:8 *90:8 0.000335716
+10 *63:8 *95:8 0
+11 *63:8 *113:8 0.000308258
+12 *25:19 *63:8 0.0531548
+13 *45:13 *63:7 0
+14 *45:13 *63:8 0.0163505
+15 *54:8 *63:8 0.00373018
+16 *59:8 *63:8 0.000202052
*RES
-1 *419:io_oeb[31] *63:7 41.49
-2 *63:7 *63:9 141.48
-3 *63:9 *63:23 49.5
-4 *63:23 *63:27 22.14
-5 *63:27 *63:30 43.29
-6 *63:30 *63:31 184.41
-7 *63:31 io_oeb[31] 1.395
+1 *419:io_oeb[31] *63:7 9.585
+2 *63:7 *63:8 235.17
+3 *63:8 *63:10 4.5
+4 *63:10 *63:11 157.05
+5 *63:11 io_oeb[31] 39.105
*END
-*D_NET *64 0.494865
+*D_NET *64 0.124688
*CONN
*P io_oeb[32] O
-*I *419:io_oeb[32] O *D user_proj_example
+*I *419:io_oeb[32] O *D wrapped_vga_clock
*CAP
-1 io_oeb[32] 0.00123761
-2 *419:io_oeb[32] 0.00105118
-3 *64:13 0.0129594
-4 *64:12 0.0117218
-5 *64:10 0.0127817
-6 *64:9 0.0138329
-7 *64:10 *65:8 0.282686
-8 *419:io_in[32] *64:9 0
-9 *50:10 *64:10 0.00186502
-10 *61:10 *64:10 0.15673
+1 io_oeb[32] 0.000332275
+2 *419:io_oeb[32] 0.000332209
+3 *64:14 0.0140223
+4 *64:13 0.01369
+5 *64:11 0.00852887
+6 *64:10 0.00852887
+7 *64:8 0.00117903
+8 *64:7 0.00151124
+9 *64:8 *96:8 0.0124956
+10 *64:14 *419:wb_clk_i 0.00536215
+11 *22:11 *64:8 0.00225883
+12 *42:8 *64:8 0.0185872
+13 *53:8 *64:8 0.0378595
*RES
-1 *419:io_oeb[32] *64:9 13.995
-2 *64:9 *64:10 422.73
-3 *64:10 *64:12 4.5
-4 *64:12 *64:13 116.73
-5 *64:13 io_oeb[32] 16.065
+1 *419:io_oeb[32] *64:7 7.425
+2 *64:7 *64:8 54.81
+3 *64:8 *64:10 4.5
+4 *64:10 *64:11 84.69
+5 *64:11 *64:13 4.5
+6 *64:13 *64:14 173.61
+7 *64:14 io_oeb[32] 3.015
*END
-*D_NET *65 0.505224
+*D_NET *65 0.0481863
*CONN
*P io_oeb[33] O
-*I *419:io_oeb[33] O *D user_proj_example
+*I *419:io_oeb[33] O *D wrapped_vga_clock
*CAP
-1 io_oeb[33] 0.00256853
-2 *419:io_oeb[33] 0.00104495
-3 *65:11 0.0213229
-4 *65:10 0.0187544
-5 *65:8 0.0126298
-6 *65:7 0.0136748
-7 *65:8 *109:10 0.150637
-8 *61:10 *65:8 0.0019065
-9 *64:10 *65:8 0.282686
+1 io_oeb[33] 0.000191629
+2 *419:io_oeb[33] 0.00911997
+3 *65:11 0.00874013
+4 *65:10 0.0085485
+5 *65:8 0.00623303
+6 *65:7 0.00623303
+7 *65:5 0.00911997
*RES
-1 *419:io_oeb[33] *65:7 13.365
-2 *65:7 *65:8 417.51
-3 *65:8 *65:10 4.5
-4 *65:10 *65:11 186.93
-5 *65:11 io_oeb[33] 31.545
+1 *419:io_oeb[33] *65:5 96.165
+2 *65:5 *65:7 4.5
+3 *65:7 *65:8 62.19
+4 *65:8 *65:10 4.5
+5 *65:10 *65:11 92.61
+6 *65:11 io_oeb[33] 1.935
*END
-*D_NET *66 0.475454
+*D_NET *66 0.1729
*CONN
*P io_oeb[34] O
-*I *419:io_oeb[34] O *D user_proj_example
+*I *419:io_oeb[34] O *D wrapped_vga_clock
*CAP
-1 io_oeb[34] 0.00126685
-2 *419:io_oeb[34] 0.00193258
-3 *66:16 0.0180914
-4 *66:15 0.0168246
-5 *66:13 0.0163481
-6 *66:12 0.0163481
-7 *66:10 0.00695318
-8 *66:9 0.00888576
-9 *66:10 *91:10 0
-10 *66:10 *93:10 1.2434e-05
-11 *66:10 *103:10 0.176375
-12 *66:10 *112:16 0.0977931
-13 *66:13 *101:13 0.0241207
-14 *66:13 *102:13 0.0701525
-15 *66:13 *103:13 0.0153439
-16 *419:io_in[34] *66:9 0
-17 *1:14 *66:13 0
-18 *12:14 *66:13 0
-19 *39:7 *66:13 0.00281101
-20 *52:10 *66:10 0.00219459
+1 io_oeb[34] 0.00125262
+2 *419:io_oeb[34] 0.000172243
+3 *66:11 0.026324
+4 *66:10 0.0250714
+5 *66:8 0.00513483
+6 *66:7 0.00530707
+7 *66:8 *101:8 0.0413059
+8 *66:8 *314:11 0.00486914
+9 *17:8 *66:8 0.0206836
+10 *30:16 *66:8 0.0427789
*RES
-1 *419:io_oeb[34] *66:9 22.455
-2 *66:9 *66:10 259.11
-3 *66:10 *66:12 4.5
-4 *66:12 *66:13 262.17
-5 *66:13 *66:15 4.5
-6 *66:15 *66:16 176.94
-7 *66:16 io_oeb[34] 13.185
+1 *419:io_oeb[34] *66:7 6.165
+2 *66:7 *66:8 126.45
+3 *66:8 *66:10 4.5
+4 *66:10 *66:11 273.06
+5 *66:11 io_oeb[34] 13.185
*END
-*D_NET *67 0.446112
+*D_NET *67 0.0690405
*CONN
*P io_oeb[35] O
-*I *419:io_oeb[35] O *D user_proj_example
+*I *419:io_oeb[35] O *D wrapped_vga_clock
*CAP
1 io_oeb[35] 0.000258912
-2 *419:io_oeb[35] 0.000121436
-3 *67:14 0.0159841
-4 *67:13 0.0157252
-5 *67:11 0.0319093
-6 *67:10 0.0319093
-7 *67:8 0.00614837
-8 *67:7 0.0062698
-9 *67:8 *68:8 0.010403
-10 *67:8 *72:8 0.156729
-11 *67:8 *99:8 0.170654
-12 *67:11 *352:9 0
-13 *67:11 *384:17 0
-14 *67:14 *352:12 0
+2 *419:io_oeb[35] 0.00853611
+3 *67:11 0.00929364
+4 *67:10 0.00903473
+5 *67:8 0.0166905
+6 *67:7 0.0166905
+7 *67:5 0.00853611
*RES
-1 *419:io_oeb[35] *67:7 5.445
-2 *67:7 *67:8 292.23
-3 *67:8 *67:10 4.5
-4 *67:10 *67:11 316.71
-5 *67:11 *67:13 4.5
-6 *67:13 *67:14 165.51
-7 *67:14 io_oeb[35] 2.475
+1 *419:io_oeb[35] *67:5 90.765
+2 *67:5 *67:7 4.5
+3 *67:7 *67:8 166.41
+4 *67:8 *67:10 4.5
+5 *67:10 *67:11 98.01
+6 *67:11 io_oeb[35] 2.475
*END
-*D_NET *68 0.591978
+*D_NET *68 0.0923118
*CONN
*P io_oeb[36] O
-*I *419:io_oeb[36] O *D user_proj_example
+*I *419:io_oeb[36] O *D wrapped_vga_clock
*CAP
-1 io_oeb[36] 0.00275085
-2 *419:io_oeb[36] 7.40635e-05
-3 *68:11 0.0411754
-4 *68:10 0.0384246
-5 *68:8 0.0104967
-6 *68:7 0.0105708
-7 *68:8 *69:8 0.302206
-8 *68:8 *99:8 0.175877
-9 *68:11 *315:15 0
-10 *68:11 *348:13 0
-11 *67:8 *68:8 0.010403
+1 io_oeb[36] 0.000123625
+2 *419:io_oeb[36] 0.00329798
+3 *68:15 0.0261444
+4 *68:14 0.0260207
+5 *68:12 0.0159375
+6 *68:10 0.0192355
+7 *10:21 *68:10 0.00046262
+8 *30:16 *68:10 0.00108942
+9 *30:16 *68:12 0
*RES
-1 *419:io_oeb[36] *68:7 5.085
-2 *68:7 *68:8 437.49
-3 *68:8 *68:10 4.5
-4 *68:10 *68:11 383.85
-5 *68:11 io_oeb[36] 33.705
+1 *419:io_oeb[36] *68:10 43.335
+2 *68:10 *68:12 159.3
+3 *68:12 *68:14 4.5
+4 *68:14 *68:15 284.31
+5 *68:15 io_oeb[36] 1.395
*END
-*D_NET *69 0.588293
+*D_NET *69 0.115587
*CONN
*P io_oeb[37] O
-*I *419:io_oeb[37] O *D user_proj_example
+*I *419:io_oeb[37] O *D wrapped_vga_clock
*CAP
-1 io_oeb[37] 0.00163658
-2 *419:io_oeb[37] 5.03775e-05
-3 *69:11 0.0468165
-4 *69:10 0.0451799
-5 *69:8 0.0145796
-6 *69:7 0.01463
-7 *69:8 *73:10 0.161453
-8 *69:8 *99:8 0.00174075
-9 *69:11 *313:13 0
-10 *419:io_in[0] *69:8 0
-11 *419:io_in[1] *69:8 0
-12 *419:io_in[6] *69:8 0
-13 *63:23 *69:8 0
-14 *68:8 *69:8 0.302206
+1 io_oeb[37] 0.000332275
+2 *419:io_oeb[37] 2.05233e-05
+3 *69:13 0.00987936
+4 *69:12 0.00954708
+5 *69:10 0.0358178
+6 *69:9 0.0358178
+7 *69:7 0.00519845
+8 *69:5 0.00521897
+9 *69:7 *71:11 0.0080199
+10 *69:7 *101:11 0.00573516
*RES
-1 *419:io_oeb[37] *69:7 4.905
-2 *69:7 *69:8 455.85
-3 *69:8 *69:10 4.5
-4 *69:10 *69:11 451.35
-5 *69:11 io_oeb[37] 21.465
+1 *419:io_oeb[37] *69:5 0.225
+2 *69:5 *69:7 85.41
+3 *69:7 *69:9 4.5
+4 *69:9 *69:10 357.21
+5 *69:10 *69:12 4.5
+6 *69:12 *69:13 103.41
+7 *69:13 io_oeb[37] 3.015
*END
-*D_NET *70 0.374207
+*D_NET *70 0.183167
*CONN
*P io_oeb[3] O
-*I *419:io_oeb[3] O *D user_proj_example
+*I *419:io_oeb[3] O *D wrapped_vga_clock
*CAP
-1 io_oeb[3] 0.000621435
-2 *419:io_oeb[3] 0.00401224
-3 *70:15 0.00906623
-4 *70:14 0.0084448
-5 *70:12 0.0705047
-6 *70:11 0.0745169
-7 *70:15 *110:17 0.031629
-8 *2:8 *70:15 0.0065672
-9 *9:16 *70:12 0
-10 *32:8 *70:15 0.168845
+1 io_oeb[3] 0.00010158
+2 *419:io_oeb[3] 0.000235193
+3 *70:17 0.0598038
+4 *70:16 0.0597022
+5 *70:14 0.012643
+6 *70:13 0.012643
+7 *70:11 0.00746326
+8 *70:10 0.00769846
+9 *70:11 *101:11 0
+10 *7:12 *70:11 0.00370839
+11 *43:10 *70:10 0.000205865
+12 *61:11 *70:11 0.0189618
*RES
-1 *419:io_oeb[3] *70:11 42.885
-2 *70:11 *70:12 741.33
-3 *70:12 *70:14 4.5
-4 *70:14 *70:15 255.69
-5 *70:15 io_oeb[3] 10.845
+1 *419:io_oeb[3] *70:10 16.3174
+2 *70:10 *70:11 107.37
+3 *70:11 *70:13 4.5
+4 *70:13 *70:14 124.47
+5 *70:14 *70:16 4.5
+6 *70:16 *70:17 654.57
+7 *70:17 io_oeb[3] 1.215
*END
-*D_NET *71 0.46228
+*D_NET *71 0.316031
*CONN
*P io_oeb[4] O
-*I *419:io_oeb[4] O *D user_proj_example
+*I *419:io_oeb[4] O *D wrapped_vga_clock
*CAP
-1 io_oeb[4] 0.0435619
-2 *419:io_oeb[4] 0.00010681
-3 *71:14 0.0435619
-4 *71:12 0.015202
-5 *71:11 0.015202
-6 *71:9 0.00285826
-7 *71:8 0.00296507
-8 *71:9 *104:9 0.158471
-9 *71:9 *105:9 0.00174075
-10 *33:15 *71:9 0.00368042
-11 *34:11 *71:9 0.173018
-12 *35:19 *71:9 0.00124339
-13 *63:23 *71:9 0.000668324
+1 io_oeb[4] 0.00060551
+2 *419:io_oeb[4] 0.00316539
+3 *71:14 0.00635202
+4 *71:13 0.00574651
+5 *71:11 0.0415401
+6 *71:10 0.0415401
+7 *71:8 0.00316539
+8 *71:8 *74:8 0.0231386
+9 *71:11 *79:11 0.175505
+10 *71:11 *81:13 0.00304632
+11 *71:11 *101:11 0.000290125
+12 *8:16 *71:11 0.000746036
+13 *55:13 *71:11 0.00317066
+14 *69:7 *71:11 0.0080199
*RES
-1 *419:io_oeb[4] *71:8 14.49
-2 *71:8 *71:9 263.61
-3 *71:9 *71:11 4.5
-4 *71:11 *71:12 151.83
-5 *71:12 *71:14 4.5
-6 *71:14 io_oeb[4] 476.325
+1 *419:io_oeb[4] *71:8 49.995
+2 *71:8 *71:10 4.5
+3 *71:10 *71:11 779.85
+4 *71:11 *71:13 4.5
+5 *71:13 *71:14 57.33
+6 *71:14 io_oeb[4] 10.665
*END
-*D_NET *72 0.298276
+*D_NET *72 0.319848
*CONN
*P io_oeb[5] O
-*I *419:io_oeb[5] O *D user_proj_example
+*I *419:io_oeb[5] O *D wrapped_vga_clock
*CAP
1 io_oeb[5] 0.000310538
-2 *419:io_oeb[5] 0.00013929
-3 *72:14 0.0436533
-4 *72:13 0.0433427
-5 *72:11 0.00931207
-6 *72:10 0.00931207
-7 *72:8 0.014001
-8 *72:7 0.0141403
-9 *72:7 *110:13 0
-10 *72:8 *99:8 0.00733598
-11 *419:io_in[37] *72:8 0
-12 *67:8 *72:8 0.156729
+2 *419:io_oeb[5] 0.000630482
+3 *72:14 0.0513453
+4 *72:13 0.0510348
+5 *72:11 0.0108207
+6 *72:10 0.0108207
+7 *72:8 0.000871017
+8 *72:7 0.0015015
+9 *72:8 *75:11 0.00114392
+10 *72:8 *84:10 0.0078541
+11 *72:8 *113:8 0.0383588
+12 *7:12 *72:14 0
+13 *32:19 *72:14 0.143674
+14 *45:13 *72:8 0.00012693
+15 *63:8 *72:8 0.0013553
*RES
-1 *419:io_oeb[5] *72:7 5.625
-2 *72:7 *72:8 258.75
+1 *419:io_oeb[5] *72:7 10.125
+2 *72:7 *72:8 55.53
3 *72:8 *72:10 4.5
-4 *72:10 *72:11 92.79
+4 *72:10 *72:11 106.29
5 *72:11 *72:13 4.5
-6 *72:13 *72:14 473.67
+6 *72:13 *72:14 649.17
7 *72:14 io_oeb[5] 2.835
*END
-*D_NET *73 0.286786
+*D_NET *73 0.271272
*CONN
*P io_oeb[6] O
-*I *419:io_oeb[6] O *D user_proj_example
+*I *419:io_oeb[6] O *D wrapped_vga_clock
*CAP
-1 io_oeb[6] 0.00434283
-2 *419:io_oeb[6] 0.000103026
-3 *73:15 0.00706424
-4 *73:10 0.0535071
-5 *73:9 0.0508887
-6 *73:9 *111:9 2.68519e-05
-7 *73:10 *99:8 0.00940003
-8 *419:io_in[6] *73:10 0
-9 *35:19 *73:10 0
-10 *63:7 *73:10 0
-11 *63:9 *73:10 0
-12 *63:23 *73:10 0
-13 *69:8 *73:10 0.161453
+1 io_oeb[6] 0.000237175
+2 *419:io_oeb[6] 0.000261151
+3 *73:14 0.0595411
+4 *73:13 0.0593039
+5 *73:11 0.0169829
+6 *73:10 0.0169829
+7 *73:8 0.002999
+8 *73:7 0.00326015
+9 *73:8 *78:8 0.0378574
+10 *73:8 *89:8 0.00880242
+11 *22:11 *73:8 0.0573774
+12 *42:8 *73:8 0.00692089
+13 *44:8 *73:8 0.000745992
*RES
-1 *419:io_oeb[6] *73:9 5.535
-2 *73:9 *73:10 679.77
-3 *73:10 *73:15 36.09
-4 *73:15 io_oeb[6] 46.665
+1 *419:io_oeb[6] *73:7 6.885
+2 *73:7 *73:8 118.53
+3 *73:8 *73:10 4.5
+4 *73:10 *73:11 167.85
+5 *73:11 *73:13 4.5
+6 *73:13 *73:14 646.47
+7 *73:14 io_oeb[6] 2.295
*END
-*D_NET *74 0.323465
+*D_NET *74 0.397559
*CONN
*P io_oeb[7] O
-*I *419:io_oeb[7] O *D user_proj_example
+*I *419:io_oeb[7] O *D wrapped_vga_clock
*CAP
-1 io_oeb[7] 0.00253818
-2 *419:io_oeb[7] 0.000490828
-3 *74:8 0.0508995
-4 *74:7 0.0488522
-5 io_oeb[7] *111:13 0.0238752
-6 *74:8 *90:8 0.0604907
-7 *74:8 *106:10 0.00033882
-8 *419:io_in[37] *74:8 0
-9 *10:16 *74:8 0.0158066
-10 *23:19 *74:8 0
-11 *62:8 *74:8 0.120173
+1 io_oeb[7] 0.000621435
+2 *419:io_oeb[7] 0.00116469
+3 *74:14 0.00724455
+4 *74:13 0.00662311
+5 *74:11 0.0757531
+6 *74:10 0.0757531
+7 *74:8 0.00265287
+8 *74:7 0.00381756
+9 *74:11 *112:13 0.0699371
+10 *74:14 *79:14 0.0809546
+11 *11:11 *74:8 0.0498985
+12 *71:8 *74:8 0.0231386
*RES
-1 *419:io_oeb[7] *74:7 8.685
-2 *74:7 *74:8 711.63
-3 *74:8 io_oeb[7] 49.635
+1 *419:io_oeb[7] *74:7 15.885
+2 *74:7 *74:8 73.17
+3 *74:8 *74:10 4.5
+4 *74:10 *74:11 779.49
+5 *74:11 *74:13 4.5
+6 *74:13 *74:14 118.71
+7 *74:14 io_oeb[7] 10.845
*END
-*D_NET *75 0.152063
+*D_NET *75 0.213002
*CONN
*P io_oeb[8] O
-*I *419:io_oeb[8] O *D user_proj_example
+*I *419:io_oeb[8] O *D wrapped_vga_clock
*CAP
1 io_oeb[8] 0.00010158
-2 *419:io_oeb[8] 0.00238831
-3 *75:12 0.0654529
-4 *75:11 0.0653513
-5 *75:9 0.00819008
-6 *75:7 0.0105784
-7 *13:12 *75:12 0
+2 *419:io_oeb[8] 0.000682717
+3 *75:17 0.0333774
+4 *75:16 0.0332758
+5 *75:14 0.0301742
+6 *75:13 0.0301742
+7 *75:11 0.0185225
+8 *75:10 0.0192052
+9 *75:11 *84:10 0.0139882
+10 *75:11 *86:14 0
+11 *75:11 *113:8 0.0258393
+12 *10:16 *75:10 6.21698e-05
+13 *33:9 *75:11 0.00126412
+14 *45:14 *75:10 0.000901462
+15 *47:11 *75:11 0.00428972
+16 *72:8 *75:11 0.00114392
*RES
-1 *419:io_oeb[8] *75:7 22.005
-2 *75:7 *75:9 81.18
-3 *75:9 *75:11 4.5
-4 *75:11 *75:12 709.83
-5 *75:12 io_oeb[8] 1.215
+1 *419:io_oeb[8] *75:10 14.895
+2 *75:10 *75:11 314.73
+3 *75:11 *75:13 4.5
+4 *75:13 *75:14 300.15
+5 *75:14 *75:16 4.5
+6 *75:16 *75:17 362.97
+7 *75:17 io_oeb[8] 1.215
*END
-*D_NET *76 0.164228
+*D_NET *76 0.193028
*CONN
*P io_oeb[9] O
-*I *419:io_oeb[9] O *D user_proj_example
+*I *419:io_oeb[9] O *D wrapped_vga_clock
*CAP
-1 io_oeb[9] 0.064805
-2 *419:io_oeb[9] 0.00261797
-3 *76:13 0.064805
-4 *76:11 0.0146912
-5 *76:9 0.0173092
-6 *76:9 *114:14 0
+1 io_oeb[9] 0.0305436
+2 *419:io_oeb[9] 0.0354635
+3 *76:10 0.0305436
+4 *76:8 0.0305068
+5 *76:7 0.0305068
+6 *76:5 0.0354635
*RES
-1 *419:io_oeb[9] *76:9 24.255
-2 *76:9 *76:11 145.98
-3 *76:11 *76:13 4.5
-4 *76:13 io_oeb[9] 704.385
+1 *419:io_oeb[9] *76:5 345.645
+2 *76:5 *76:7 4.5
+3 *76:7 *76:8 304.11
+4 *76:8 *76:10 4.5
+5 *76:10 io_oeb[9] 333.225
*END
-*D_NET *77 0.761989
+*D_NET *77 0.189791
*CONN
*P io_out[0] O
-*I *419:io_out[0] O *D user_proj_example
+*I *419:io_out[0] O *D wrapped_vga_clock
*CAP
1 io_out[0] 0.000332275
-2 *419:io_out[0] 0.000313186
-3 *77:15 0.0157572
-4 *77:14 0.0154249
-5 *77:12 0.0433316
-6 *77:11 0.0433316
-7 *77:9 0.0191987
-8 *77:8 0.0195119
-9 *77:9 *88:9 0.220268
-10 *77:9 *105:9 0
-11 *77:15 *302:16 0
-12 *33:15 *77:9 0
-13 *36:9 *77:9 0.38452
+2 *419:io_out[0] 0.0431193
+3 *77:11 0.0238301
+4 *77:10 0.0234978
+5 *77:8 0.0279462
+6 *77:7 0.0279462
+7 *77:5 0.0431193
*RES
-1 *419:io_out[0] *77:8 16.47
-2 *77:8 *77:9 604.53
-3 *77:9 *77:11 4.5
-4 *77:11 *77:12 430.65
-5 *77:12 *77:14 4.5
-6 *77:14 *77:15 163.17
-7 *77:15 io_out[0] 3.015
+1 *419:io_out[0] *77:5 421.245
+2 *77:5 *77:7 4.5
+3 *77:7 *77:8 278.73
+4 *77:8 *77:10 4.5
+5 *77:10 *77:11 257.67
+6 *77:11 io_out[0] 3.015
*END
-*D_NET *78 0.170837
+*D_NET *78 0.269199
*CONN
*P io_out[10] O
-*I *419:io_out[10] O *D user_proj_example
+*I *419:io_out[10] O *D wrapped_vga_clock
*CAP
1 io_out[10] 0.000332275
-2 *419:io_out[10] 0.00257912
-3 *78:14 0.0640895
-4 *78:13 0.0637573
-5 *78:11 0.0187497
-6 *78:9 0.0213288
-7 *40:10 *78:9 0
+2 *419:io_out[10] 0.000241929
+3 *78:14 0.00490958
+4 *78:13 0.00457731
+5 *78:11 0.0403274
+6 *78:10 0.0403274
+7 *78:8 0.0412168
+8 *78:7 0.0414587
+9 *78:8 *86:14 0
+10 *78:8 *89:8 0.00735578
+11 *78:8 *109:11 0.0481469
+12 *44:8 *78:8 0.00244792
+13 *73:8 *78:8 0.0378574
*RES
-1 *419:io_out[10] *78:9 23.535
-2 *78:9 *78:11 186.48
-3 *78:11 *78:13 4.5
-4 *78:13 *78:14 693.63
-5 *78:14 io_out[10] 3.015
+1 *419:io_out[10] *78:7 6.705
+2 *78:7 *78:8 651.51
+3 *78:8 *78:10 4.5
+4 *78:10 *78:11 402.57
+5 *78:11 *78:13 4.5
+6 *78:13 *78:14 49.77
+7 *78:14 io_out[10] 3.015
*END
-*D_NET *79 0.181952
+*D_NET *79 0.808062
*CONN
*P io_out[11] O
-*I *419:io_out[11] O *D user_proj_example
+*I *419:io_out[11] O *D wrapped_vga_clock
*CAP
-1 io_out[11] 0.000258912
-2 *419:io_out[11] 0.000111588
-3 *79:16 0.054998
-4 *79:15 0.0547391
-5 *79:13 0.00990568
-6 *79:12 0.00990568
-7 *79:10 0.00821087
-8 *79:9 0.00821087
-9 *79:7 0.0177496
-10 *79:5 0.0178612
+1 io_out[11] 0.000637361
+2 *419:io_out[11] 0.00278466
+3 *79:14 0.0324703
+4 *79:13 0.031833
+5 *79:11 0.0145285
+6 *79:10 0.0173131
+7 *79:11 *81:13 0.00105689
+8 *8:16 *79:11 0.447808
+9 *55:13 *79:11 0.00317066
+10 *71:11 *79:11 0.175505
+11 *74:14 *79:14 0.0809546
*RES
-1 *419:io_out[11] *79:5 1.125
-2 *79:5 *79:7 174.33
-3 *79:7 *79:9 4.5
-4 *79:9 *79:10 87.75
-5 *79:10 *79:12 4.5
-6 *79:12 *79:13 98.73
-7 *79:13 *79:15 4.5
-8 *79:15 *79:16 597.87
-9 *79:16 io_out[11] 2.475
+1 *419:io_out[11] *79:10 36.135
+2 *79:10 *79:11 768.33
+3 *79:11 *79:13 4.5
+4 *79:13 *79:14 370.53
+5 *79:14 io_out[11] 11.025
*END
-*D_NET *80 0.193063
+*D_NET *80 0.227987
*CONN
*P io_out[12] O
-*I *419:io_out[12] O *D user_proj_example
+*I *419:io_out[12] O *D wrapped_vga_clock
*CAP
1 io_out[12] 0.000191629
-2 *419:io_out[12] 5.8026e-05
-3 *80:10 0.0623366
-4 *80:9 0.062145
-5 *80:7 0.0341368
-6 *80:5 0.0341948
+2 *419:io_out[12] 0.0428997
+3 *80:11 0.019579
+4 *80:10 0.0193874
+5 *80:8 0.0515147
+6 *80:7 0.0515147
+7 *80:5 0.0428997
*RES
-1 *419:io_out[12] *80:5 0.585
-2 *80:5 *80:7 337.77
-3 *80:7 *80:9 4.5
-4 *80:9 *80:10 677.43
-5 *80:10 io_out[12] 1.935
+1 *419:io_out[12] *80:5 467.145
+2 *80:5 *80:7 4.5
+3 *80:7 *80:8 514.17
+4 *80:8 *80:10 4.5
+5 *80:10 *80:11 211.77
+6 *80:11 io_out[12] 1.935
*END
-*D_NET *81 0.20417
+*D_NET *81 0.312799
*CONN
*P io_out[13] O
-*I *419:io_out[13] O *D user_proj_example
+*I *419:io_out[13] O *D wrapped_vga_clock
*CAP
1 io_out[13] 0.000123625
-2 *419:io_out[13] 0.0406213
-3 *81:8 0.0614638
-4 *81:7 0.0613401
-5 *81:5 0.0406213
-6 *419:io_in[14] *81:5 0
+2 *419:io_out[13] 0.000356235
+3 *81:17 0.0709379
+4 *81:16 0.0708143
+5 *81:14 0.0499169
+6 *81:13 0.0500119
+7 *81:8 0.000705618
+8 *81:7 0.000966833
+9 *81:8 *87:8 0.0320995
+10 *81:8 *114:8 0.0320995
+11 *81:14 *111:12 0
+12 *8:16 *81:13 0.000663143
+13 *71:11 *81:13 0.00304632
+14 *79:11 *81:13 0.00105689
*RES
-1 *419:io_out[13] *81:5 402.525
-2 *81:5 *81:7 4.5
-3 *81:7 *81:8 669.33
-4 *81:8 io_out[13] 1.395
+1 *419:io_out[13] *81:7 7.785
+2 *81:7 *81:8 47.07
+3 *81:8 *81:13 13.41
+4 *81:13 *81:14 498.51
+5 *81:14 *81:16 4.5
+6 *81:16 *81:17 773.37
+7 *81:17 io_out[13] 1.395
*END
-*D_NET *82 0.25987
+*D_NET *82 0.325779
*CONN
*P io_out[14] O
-*I *419:io_out[14] O *D user_proj_example
+*I *419:io_out[14] O *D wrapped_vga_clock
*CAP
-1 io_out[14] 0.000271078
-2 *419:io_out[14] 0.00277105
-3 *82:17 0.0447839
-4 *82:16 0.0445129
-5 *82:14 0.0581028
-6 *82:13 0.0608739
-7 *82:14 *102:10 0
-8 *7:11 *82:13 0
-9 *17:11 *82:14 0.0485546
-10 *44:10 *82:13 0
+1 io_out[14] 0.00395544
+2 *419:io_out[14] 0.000324123
+3 *82:17 0.0589211
+4 *82:16 0.0549657
+5 *82:14 0.066237
+6 *82:13 0.066237
+7 *82:11 0.00516239
+8 *82:10 0.00548651
+9 *82:11 *109:11 0.0299862
+10 *45:14 *82:11 0.034504
*RES
-1 *419:io_out[14] *82:13 30.015
-2 *82:13 *82:14 661.59
-3 *82:14 *82:16 4.5
-4 *82:16 *82:17 444.51
-5 *82:17 io_out[14] 6.885
+1 *419:io_out[14] *82:10 12.735
+2 *82:10 *82:11 130.23
+3 *82:11 *82:13 4.5
+4 *82:13 *82:14 660.51
+5 *82:14 *82:16 4.5
+6 *82:16 *82:17 600.84
+7 *82:17 io_out[14] 43.245
*END
-*D_NET *83 0.439303
+*D_NET *83 0.239471
*CONN
*P io_out[15] O
-*I *419:io_out[15] O *D user_proj_example
+*I *419:io_out[15] O *D wrapped_vga_clock
*CAP
1 io_out[15] 0.000290594
-2 *419:io_out[15] 0.00180908
-3 *83:13 0.0488505
-4 *83:12 0.0485599
-5 *83:10 0.0393784
-6 *83:9 0.0411875
-7 *83:10 *85:10 0.25558
-8 *83:10 *91:10 0.00364729
-9 *83:10 *112:16 0
+2 *419:io_out[15] 0.0571613
+3 *83:8 0.0625743
+4 *83:7 0.0622837
+5 *83:5 0.0571613
*RES
-1 *419:io_out[15] *83:9 20.835
-2 *83:9 *83:10 599.13
-3 *83:10 *83:12 4.5
-4 *83:12 *83:13 484.47
-5 *83:13 io_out[15] 3.015
+1 *419:io_out[15] *83:5 622.485
+2 *83:5 *83:7 4.5
+3 *83:7 *83:8 621.81
+4 *83:8 io_out[15] 3.015
*END
-*D_NET *84 0.190551
+*D_NET *84 0.267977
*CONN
*P io_out[16] O
-*I *419:io_out[16] O *D user_proj_example
+*I *419:io_out[16] O *D wrapped_vga_clock
*CAP
1 io_out[16] 0.000104982
-2 *419:io_out[16] 0.000111588
-3 *84:13 0.043763
-4 *84:12 0.043658
-5 *84:10 0.0447105
-6 *84:9 0.0447105
-7 *84:7 0.0066902
-8 *84:5 0.00680179
+2 *419:io_out[16] 0.0012354
+3 *84:17 0.0686425
+4 *84:16 0.0685375
+5 *84:14 0.0505971
+6 *84:13 0.051946
+7 *84:10 0.00258423
+8 *84:10 *86:14 0
+9 *47:11 *84:10 0.00248679
+10 *72:8 *84:10 0.0078541
+11 *75:11 *84:10 0.0139882
*RES
-1 *419:io_out[16] *84:5 1.125
-2 *84:5 *84:7 63.63
-3 *84:7 *84:9 4.5
-4 *84:9 *84:10 486.09
-5 *84:10 *84:12 4.5
-6 *84:12 *84:13 435.87
-7 *84:13 io_out[16] 1.395
+1 *419:io_out[16] *84:10 48.375
+2 *84:10 *84:13 17.19
+3 *84:13 *84:14 495.81
+4 *84:14 *84:16 4.5
+5 *84:16 *84:17 684.27
+6 *84:17 io_out[16] 1.395
*END
-*D_NET *85 0.422189
+*D_NET *85 0.249124
*CONN
*P io_out[17] O
-*I *419:io_out[17] O *D user_proj_example
+*I *419:io_out[17] O *D wrapped_vga_clock
*CAP
-1 io_out[17] 0.000224243
-2 *419:io_out[17] 0.00175551
-3 *85:13 0.0487886
-4 *85:12 0.0485643
-5 *85:10 0.0149242
-6 *85:9 0.0166797
-7 *85:10 *91:10 0.0261734
-8 *85:10 *112:16 0
-9 *44:11 *85:9 0
-10 *49:10 *85:10 0.0094995
-11 *83:10 *85:10 0.25558
+1 io_out[17] 0.000649026
+2 *419:io_out[17] 0.0303307
+3 *85:11 0.00478877
+4 *85:10 0.00413975
+5 *85:8 0.0610124
+6 *85:7 0.0610124
+7 *85:5 0.0303307
+8 *9:8 *85:11 0.056388
+9 *46:8 io_out[17] 3.68254e-05
+10 *46:13 *85:11 0.000435189
*RES
-1 *419:io_out[17] *85:9 20.295
-2 *85:9 *85:10 369.99
-3 *85:10 *85:12 4.5
-4 *85:12 *85:13 484.29
-5 *85:13 io_out[17] 2.475
+1 *419:io_out[17] *85:5 329.445
+2 *85:5 *85:7 4.5
+3 *85:7 *85:8 609.03
+4 *85:8 *85:10 4.5
+5 *85:10 *85:11 81.63
+6 *85:11 io_out[17] 10.845
*END
-*D_NET *86 0.419666
+*D_NET *86 0.215459
*CONN
*P io_out[18] O
-*I *419:io_out[18] O *D user_proj_example
+*I *419:io_out[18] O *D wrapped_vga_clock
*CAP
-1 io_out[18] 0.00434651
-2 *419:io_out[18] 0.000602416
-3 *86:11 0.0496191
-4 *86:10 0.0452725
-5 *86:8 0.00308938
-6 *86:7 0.0036918
-7 *10:16 *86:8 0.177246
-8 *11:16 *86:8 0.125147
-9 *23:19 *86:8 0.0100715
-10 *25:13 *86:8 0.00058025
+1 io_out[18] 0.00434204
+2 *419:io_out[18] 0.00105257
+3 *86:17 0.0697319
+4 *86:16 0.0653899
+5 *86:14 0.0277043
+6 *86:13 0.0287569
+7 *86:13 *90:8 0.000306879
+8 *86:13 *108:7 0
+9 *25:19 *86:13 0.00221731
+10 *44:8 *86:14 0.0104942
+11 *45:13 *86:14 0
+12 *47:11 *86:14 0
+13 *53:8 *86:14 0.00333644
+14 *59:8 *86:13 0.00172827
+15 *63:8 *86:13 0.000397886
+16 *75:11 *86:14 0
+17 *78:8 *86:14 0
+18 *84:10 *86:14 0
*RES
-1 *419:io_out[18] *86:7 9.765
-2 *86:7 *86:8 256.59
-3 *86:8 *86:10 4.5
-4 *86:10 *86:11 451.26
-5 *86:11 io_out[18] 43.245
+1 *419:io_out[18] *86:13 33.885
+2 *86:13 *86:14 337.59
+3 *86:14 *86:16 4.5
+4 *86:16 *86:17 652.14
+5 *86:17 io_out[18] 43.245
*END
-*D_NET *87 0.161306
+*D_NET *87 0.406301
*CONN
*P io_out[19] O
-*I *419:io_out[19] O *D user_proj_example
+*I *419:io_out[19] O *D wrapped_vga_clock
*CAP
-1 io_out[19] 0.00065797
-2 *419:io_out[19] 0.00365166
-3 *87:20 0.00638019
-4 *87:19 0.00572222
-5 *87:17 0.0463433
-6 *87:16 0.0463433
-7 *87:14 0.00531621
-8 *87:13 0.00896788
-9 *87:14 *89:16 0.000559527
-10 *13:15 *87:13 0
-11 *32:11 *87:14 0
-12 *45:16 *87:20 0.037364
+1 io_out[19] 0.000659344
+2 *419:io_out[19] 0.00037216
+3 *87:17 0.0163588
+4 *87:16 0.0156994
+5 *87:14 0.0586533
+6 *87:13 0.0597674
+7 *87:8 0.00426673
+8 *87:7 0.00352487
+9 *87:8 *88:8 0.0117228
+10 *87:8 *109:10 0.0022709
+11 *87:8 *114:8 0.00366209
+12 *87:14 *112:12 0
+13 *87:17 io_out[21] 0.0146098
+14 io_oeb[21] *87:17 0
+15 *7:12 *87:13 0.0143612
+16 *9:8 *87:17 0.115698
+17 *14:10 *87:17 0
+18 *15:19 *87:8 0.0208064
+19 *48:11 *87:17 0.0317688
+20 *81:8 *87:8 0.0320995
*RES
-1 *419:io_out[19] *87:13 38.115
-2 *87:13 *87:14 58.05
-3 *87:14 *87:16 4.5
-4 *87:16 *87:17 461.97
-5 *87:17 *87:19 4.5
-6 *87:19 *87:20 86.49
-7 *87:20 io_out[19] 10.845
+1 *419:io_out[19] *87:7 7.965
+2 *87:7 *87:8 80.37
+3 *87:8 *87:13 29.79
+4 *87:13 *87:14 585.99
+5 *87:14 *87:16 4.5
+6 *87:16 *87:17 275.49
+7 *87:17 io_out[19] 10.845
*END
-*D_NET *88 0.410326
+*D_NET *88 0.205674
*CONN
*P io_out[1] O
-*I *419:io_out[1] O *D user_proj_example
+*I *419:io_out[1] O *D wrapped_vga_clock
*CAP
1 io_out[1] 0.000258912
-2 *419:io_out[1] 0.000283831
-3 *88:15 0.0418329
-4 *88:14 0.0415739
-5 *88:12 0.0371492
-6 *88:11 0.0371492
-7 *88:9 0.0157632
-8 *88:8 0.0160471
-9 *88:9 *105:9 0
-10 *88:12 *189:15 0
-11 *88:12 *253:13 0
-12 *33:15 *88:9 0
-13 *77:9 *88:9 0.220268
+2 *419:io_out[1] 0.000379173
+3 *88:11 0.071202
+4 *88:10 0.0709431
+5 *88:8 0.019431
+6 *88:7 0.0198101
+7 *88:8 *109:10 0.00462364
+8 *88:8 *114:8 0.00730371
+9 *87:8 *88:8 0.0117228
*RES
-1 *419:io_out[1] *88:8 16.29
-2 *88:8 *88:9 318.87
-3 *88:9 *88:11 4.5
-4 *88:11 *88:12 366.03
-5 *88:12 *88:14 4.5
-6 *88:14 *88:15 441.27
-7 *88:15 io_out[1] 2.475
+1 *419:io_out[1] *88:7 7.785
+2 *88:7 *88:8 213.75
+3 *88:8 *88:10 4.5
+4 *88:10 *88:11 777.69
+5 *88:11 io_out[1] 2.475
*END
-*D_NET *89 0.10716
+*D_NET *89 0.193819
*CONN
*P io_out[20] O
-*I *419:io_out[20] O *D user_proj_example
+*I *419:io_out[20] O *D wrapped_vga_clock
*CAP
-1 io_out[20] 0.00303197
-2 *419:io_out[20] 0.00363627
-3 *89:17 0.0494598
-4 *89:16 0.0500641
-5 *14:19 *89:17 0
-6 *32:11 *89:16 0.000407989
-7 *87:14 *89:16 0.000559527
+1 io_out[20] 0.000290594
+2 *419:io_out[20] 0.0001932
+3 *89:17 0.069461
+4 *89:16 0.0691704
+5 *89:14 0.00479522
+6 *89:13 0.00521114
+7 *89:8 0.00311859
+8 *89:7 0.00289587
+9 *89:8 *109:11 0.0145848
+10 *419:io_in[20] *89:14 0.00609185
+11 *22:11 *89:8 0.000335457
+12 *58:8 *89:8 0.00151268
+13 *73:8 *89:8 0.00880242
+14 *78:8 *89:8 0.00735578
*RES
-1 *419:io_out[20] *89:16 45.585
-2 *89:16 *89:17 462.33
-3 *89:17 io_out[20] 40.995
+1 *419:io_out[20] *89:7 6.345
+2 *89:7 *89:8 105.57
+3 *89:8 *89:13 12.87
+4 *89:13 *89:14 78.39
+5 *89:14 *89:16 4.5
+6 *89:16 *89:17 689.67
+7 *89:17 io_out[20] 3.015
*END
-*D_NET *90 0.170734
+*D_NET *90 0.250224
*CONN
*P io_out[21] O
-*I *419:io_out[21] O *D user_proj_example
+*I *419:io_out[21] O *D wrapped_vga_clock
*CAP
-1 io_out[21] 0.000104982
-2 *419:io_out[21] 0.000436614
-3 *90:11 0.0499327
-4 *90:10 0.0498277
-5 *90:8 0.00475218
-6 *90:7 0.0051888
-7 *90:11 *114:17 0
-8 *419:io_in[22] *90:7 0
-9 *40:10 *90:11 0
-10 *74:8 *90:8 0.0604907
+1 io_out[21] 0.00183833
+2 *419:io_out[21] 0.00119657
+3 *90:11 0.0667981
+4 *90:10 0.0649597
+5 *90:8 0.00119657
+6 *90:8 *113:8 0.0231893
+7 *90:11 *107:8 0.00716051
+8 *10:22 *90:8 0.00174075
+9 *55:8 *90:11 0.0483027
+10 *59:8 *90:8 0.0185888
+11 *63:8 *90:8 0.000335716
+12 *86:13 *90:8 0.000306879
+13 *87:17 io_out[21] 0.0146098
*RES
-1 *419:io_out[21] *90:7 8.505
-2 *90:7 *90:8 87.57
-3 *90:8 *90:10 4.5
-4 *90:10 *90:11 495.45
-5 *90:11 io_out[21] 1.395
+1 *419:io_out[21] *90:8 48.375
+2 *90:8 *90:10 4.5
+3 *90:10 *90:11 691.11
+4 *90:11 io_out[21] 36.675
*END
-*D_NET *91 0.266554
+*D_NET *91 0.145543
*CONN
*P io_out[22] O
-*I *419:io_out[22] O *D user_proj_example
+*I *419:io_out[22] O *D wrapped_vga_clock
*CAP
1 io_out[22] 0.000987786
-2 *419:io_out[22] 0.00189419
-3 *91:13 0.0486851
-4 *91:12 0.0476973
-5 *91:10 0.00909946
-6 *91:9 0.0109937
-7 *91:10 *112:10 0.0410941
-8 *49:10 *91:10 0.00248675
-9 *52:10 *91:10 0.0737954
-10 *53:16 io_out[22] 0
-11 *66:10 *91:10 0
-12 *83:10 *91:10 0.00364729
-13 *85:10 *91:10 0.0261734
+2 *419:io_out[22] 0.000554422
+3 *91:14 0.0591939
+4 *91:13 0.0599354
+5 *91:10 0.00228371
+6 *91:13 *92:11 0.0221946
+7 *3:16 *91:10 0
+8 *15:13 *91:10 0.000393572
+9 *53:16 io_out[22] 0
*RES
-1 *419:io_out[22] *91:9 20.475
-2 *91:9 *91:10 198.63
-3 *91:10 *91:12 4.5
-4 *91:12 *91:13 476.37
-5 *91:13 io_out[22] 18.675
+1 *419:io_out[22] *91:10 20.2774
+2 *91:10 *91:13 36.63
+3 *91:13 *91:14 581.85
+4 *91:14 io_out[22] 18.675
*END
-*D_NET *92 0.22799
+*D_NET *92 0.175355
*CONN
*P io_out[23] O
-*I *419:io_out[23] O *D user_proj_example
+*I *419:io_out[23] O *D wrapped_vga_clock
*CAP
-1 io_out[23] 0.00433039
-2 *419:io_out[23] 0.00125537
-3 *92:13 0.0488039
-4 *92:12 0.0444735
-5 *92:10 0.0248387
-6 *92:9 0.0260941
-7 *419:io_in[24] *92:9 0.000420424
-8 *29:19 *92:10 0
-9 *38:15 *92:10 0.0777741
+1 io_out[23] 0.000671366
+2 *419:io_out[23] 0.00070057
+3 *92:17 0.00619088
+4 *92:16 0.00551951
+5 *92:14 0.0583694
+6 *92:13 0.0583694
+7 *92:11 0.00866932
+8 *92:10 0.00936989
+9 *32:19 *92:11 0.000264222
+10 *51:16 *92:11 0.00503575
+11 *91:13 *92:11 0.0221946
*RES
-1 *419:io_out[23] *92:9 17.415
-2 *92:9 *92:10 316.35
-3 *92:10 *92:12 4.5
-4 *92:12 *92:13 444.24
-5 *92:13 io_out[23] 43.245
+1 *419:io_out[23] *92:10 20.0974
+2 *92:10 *92:11 110.97
+3 *92:11 *92:13 4.5
+4 *92:13 *92:14 583.29
+5 *92:14 *92:16 4.5
+6 *92:16 *92:17 60.21
+7 *92:17 io_out[23] 11.025
*END
-*D_NET *93 0.18078
+*D_NET *93 0.237667
*CONN
*P io_out[24] O
-*I *419:io_out[24] O *D user_proj_example
+*I *419:io_out[24] O *D wrapped_vga_clock
*CAP
1 io_out[24] 0.000215438
-2 *419:io_out[24] 0.00210569
-3 *93:16 0.016159
-4 *93:15 0.0159436
-5 *93:13 0.0444893
-6 *93:12 0.0444893
-7 *93:10 0.0134218
-8 *93:9 0.0155275
-9 *93:10 *103:10 0.0144288
-10 *419:io_in[13] *93:10 0.0139871
-11 *30:11 *93:10 0
-12 *66:10 *93:10 1.2434e-05
+2 *419:io_out[24] 0.00066151
+3 *93:17 0.00923593
+4 *93:16 0.00902049
+5 *93:14 0.0549872
+6 *93:13 0.0549872
+7 *93:11 0.00946995
+8 *93:10 0.0101315
+9 *419:io_in[14] *93:10 5.4397e-05
+10 *419:io_in[27] *93:11 0
+11 *419:io_in[30] *93:11 0
+12 *419:io_in[9] *93:11 0.000127448
+13 *6:12 *93:10 0.000868212
+14 *37:19 *93:11 0.00752255
+15 *52:13 *93:11 0
+16 *56:11 *93:11 0.0803856
*RES
-1 *419:io_out[24] *93:9 23.535
-2 *93:9 *93:10 202.23
-3 *93:10 *93:12 4.5
-4 *93:12 *93:13 444.33
-5 *93:13 *93:15 4.5
-6 *93:15 *93:16 173.61
-7 *93:16 io_out[24] 2.115
+1 *419:io_out[24] *93:10 22.9774
+2 *93:10 *93:11 157.41
+3 *93:11 *93:13 4.5
+4 *93:13 *93:14 549.45
+5 *93:14 *93:16 4.5
+6 *93:16 *93:17 98.01
+7 *93:17 io_out[24] 2.115
*END
-*D_NET *94 0.570308
+*D_NET *94 0.151475
*CONN
*P io_out[25] O
-*I *419:io_out[25] O *D user_proj_example
+*I *419:io_out[25] O *D wrapped_vga_clock
*CAP
-1 io_out[25] 0.000611329
-2 *419:io_out[25] 0.000585572
-3 *94:11 0.0266476
-4 *94:10 0.0260363
-5 *94:8 0.00643738
-6 *94:7 0.00702295
-7 *419:io_in[26] *94:7 0
-8 *10:16 *94:8 0.0400991
-9 *25:13 *94:8 0.0322763
-10 *30:8 *94:11 0.00975874
-11 *57:8 *94:8 0.261174
-12 *57:11 *94:11 0.0170829
-13 *58:13 *94:11 0.142576
+1 io_out[25] 0.00163658
+2 *419:io_out[25] 0.0159227
+3 *94:8 0.0598149
+4 *94:7 0.0581783
+5 *94:5 0.0159227
+6 *94:8 *313:13 0
*RES
-1 *419:io_out[25] *94:7 9.405
-2 *94:7 *94:8 378.45
-3 *94:8 *94:10 4.5
-4 *94:10 *94:11 389.97
-5 *94:11 io_out[25] 10.665
+1 *419:io_out[25] *94:5 171.765
+2 *94:5 *94:7 4.5
+3 *94:7 *94:8 580.95
+4 *94:8 io_out[25] 21.465
*END
-*D_NET *95 0.194237
+*D_NET *95 0.171554
*CONN
*P io_out[26] O
-*I *419:io_out[26] O *D user_proj_example
+*I *419:io_out[26] O *D wrapped_vga_clock
*CAP
1 io_out[26] 0.000280649
-2 *419:io_out[26] 0.00297936
-3 *95:16 0.0279168
-4 *95:15 0.0276361
-5 *95:13 0.0299438
-6 *95:12 0.0299438
-7 *95:10 0.00341125
-8 *95:9 0.00639061
-9 *95:10 *101:10 0.00313025
-10 *7:11 *95:13 0
-11 *20:19 *95:10 0.062605
-12 *57:7 *95:9 0
+2 *419:io_out[26] 0.000379581
+3 *95:14 0.0105789
+4 *95:13 0.0102983
+5 *95:11 0.0520932
+6 *95:10 0.0520932
+7 *95:8 0.0054738
+8 *95:7 0.00585338
+9 *95:8 *96:8 0.00746025
+10 *53:8 *95:8 0.0270431
+11 *63:8 *95:8 0
*RES
-1 *419:io_out[26] *95:9 31.815
-2 *95:9 *95:10 90.63
-3 *95:10 *95:12 4.5
-4 *95:12 *95:13 298.17
-5 *95:13 *95:15 4.5
-6 *95:15 *95:16 300.51
-7 *95:16 io_out[26] 2.655
+1 *419:io_out[26] *95:7 7.785
+2 *95:7 *95:8 93.15
+3 *95:8 *95:10 4.5
+4 *95:10 *95:11 519.75
+5 *95:11 *95:13 4.5
+6 *95:13 *95:14 111.51
+7 *95:14 io_out[26] 2.655
*END
-*D_NET *96 0.127212
+*D_NET *96 0.160215
*CONN
*P io_out[27] O
-*I *419:io_out[27] O *D user_proj_example
+*I *419:io_out[27] O *D wrapped_vga_clock
*CAP
1 io_out[27] 0.000145659
-2 *419:io_out[27] 0.00306749
-3 *96:16 0.0369004
-4 *96:15 0.0367547
-5 *96:13 0.0231095
-6 *96:12 0.026177
-7 *96:12 *97:13 0
-8 *96:12 *101:10 0.00105689
+2 *419:io_out[27] 0.000308516
+3 *96:14 0.00996161
+4 *96:13 0.00981595
+5 *96:11 0.0452794
+6 *96:10 0.0452794
+7 *96:8 0.00404306
+8 *96:7 0.00435158
+9 *22:11 *96:8 0.0162253
+10 *53:8 *96:8 0.00186498
+11 *58:8 *96:8 0.00298401
+12 *64:8 *96:8 0.0124956
+13 *95:8 *96:8 0.00746025
*RES
-1 *419:io_out[27] *96:12 38.205
-2 *96:12 *96:13 229.77
-3 *96:13 *96:15 4.5
-4 *96:15 *96:16 397.71
-5 *96:16 io_out[27] 1.575
+1 *419:io_out[27] *96:7 7.245
+2 *96:7 *96:8 85.59
+3 *96:8 *96:10 4.5
+4 *96:10 *96:11 451.71
+5 *96:11 *96:13 4.5
+6 *96:13 *96:14 106.11
+7 *96:14 io_out[27] 1.575
*END
-*D_NET *97 0.118615
+*D_NET *97 0.107268
*CONN
*P io_out[28] O
-*I *419:io_out[28] O *D user_proj_example
+*I *419:io_out[28] O *D wrapped_vga_clock
*CAP
-1 io_out[28] 0.0370721
-2 *419:io_out[28] 0.00149395
-3 *97:15 0.0370721
-4 *97:13 0.0180378
-5 *97:12 0.0195318
-6 *97:12 *109:10 0
-7 *419:io_in[29] *97:12 0.000371323
-8 *21:16 *97:13 0
-9 *29:19 *97:12 0.00503575
-10 *96:12 *97:13 0
+1 io_out[28] 0.0240675
+2 *419:io_out[28] 0.00168424
+3 *97:16 0.0240675
+4 *97:14 0.0278823
+5 *97:13 0.0295665
+6 *37:19 *97:13 0
*RES
-1 *419:io_out[28] *97:12 27.765
-2 *97:12 *97:13 178.47
-3 *97:13 *97:15 4.5
-4 *97:15 io_out[28] 400.365
+1 *419:io_out[28] *97:13 34.2274
+2 *97:13 *97:14 278.37
+3 *97:14 *97:16 4.5
+4 *97:16 io_out[28] 259.965
*END
-*D_NET *98 0.604697
+*D_NET *98 0.100649
*CONN
*P io_out[29] O
-*I *419:io_out[29] O *D user_proj_example
+*I *419:io_out[29] O *D wrapped_vga_clock
*CAP
-1 io_out[29] 0.000717761
-2 *419:io_out[29] 0.000501841
-3 *98:11 0.00655782
-4 *98:10 0.00584006
-5 *98:8 0.00459181
-6 *98:7 0.00509365
-7 io_oeb[30] *98:11 0.0055852
-8 *419:io_in[30] *98:7 0
-9 *10:16 *98:8 0.00348148
-10 *30:8 *98:11 2.45503e-05
-11 *57:8 *98:8 0.264407
-12 *57:11 *98:11 0.0263302
-13 *62:8 *98:8 0.281566
+1 io_out[29] 0.000215438
+2 *419:io_out[29] 0.0015994
+3 *98:17 0.021577
+4 *98:16 0.0213616
+5 *98:14 0.0209582
+6 *98:13 0.0225576
+7 *419:io_in[27] *98:13 6.52783e-05
+8 *419:io_in[30] *98:13 4.66274e-05
+9 *419:io_in[30] *98:14 0
+10 *49:13 *98:13 0.0121229
+11 *49:16 *98:13 6.13758e-05
+12 *52:13 *98:13 8.39292e-05
*RES
-1 *419:io_out[29] *98:7 9.045
-2 *98:7 *98:8 407.97
-3 *98:8 *98:10 4.5
-4 *98:10 *98:11 116.01
-5 *98:11 io_out[29] 11.385
+1 *419:io_out[29] *98:13 42.3274
+2 *98:13 *98:14 209.25
+3 *98:14 *98:16 4.5
+4 *98:16 *98:17 230.31
+5 *98:17 io_out[29] 2.115
*END
-*D_NET *99 0.519917
+*D_NET *99 0.170622
*CONN
*P io_out[2] O
-*I *419:io_out[2] O *D user_proj_example
+*I *419:io_out[2] O *D wrapped_vga_clock
*CAP
-1 io_out[2] 0.000191629
-2 *419:io_out[2] 9.52214e-05
-3 *99:14 0.0400074
-4 *99:13 0.0398158
-5 *99:11 0.0311121
-6 *99:10 0.0311121
-7 *99:8 0.0062397
-8 *99:7 0.00633492
-9 *99:11 *192:15 0
-10 *99:11 *256:13 0
-11 *99:14 *257:12 0
-12 *67:8 *99:8 0.170654
-13 *68:8 *99:8 0.175877
-14 *69:8 *99:8 0.00174075
-15 *72:8 *99:8 0.00733598
-16 *73:10 *99:8 0.00940003
+1 io_out[2] 0.00100159
+2 *419:io_out[2] 4.01718e-05
+3 *99:10 0.0743241
+4 *99:9 0.0733225
+5 *99:7 0.0109467
+6 *99:5 0.0109868
*RES
-1 *419:io_out[2] *99:7 5.265
-2 *99:7 *99:8 330.21
-3 *99:8 *99:10 4.5
-4 *99:10 *99:11 305.73
-5 *99:11 *99:13 4.5
-6 *99:13 *99:14 422.37
-7 *99:14 io_out[2] 1.935
+1 *419:io_out[2] *99:5 0.405
+2 *99:5 *99:7 108.81
+3 *99:7 *99:9 4.5
+4 *99:9 *99:10 720.99
+5 *99:10 io_out[2] 19.215
*END
-*D_NET *100 0.0895814
+*D_NET *100 0.134535
*CONN
*P io_out[30] O
-*I *419:io_out[30] O *D user_proj_example
+*I *419:io_out[30] O *D wrapped_vga_clock
*CAP
-1 io_out[30] 0.00133974
-2 *419:io_out[30] 0.00253788
-3 *100:14 0.0392006
-4 *100:13 0.0409131
-5 *100:9 0.00559011
-6 *47:10 *100:14 0
-7 *62:7 *100:9 0
+1 io_out[30] 0.00188969
+2 *419:io_out[30] 0.00160183
+3 *100:16 0.0153237
+4 *100:15 0.013434
+5 *100:13 0.0204696
+6 *100:12 0.0220714
+7 *100:13 *111:13 0.0597452
+8 *5:16 *100:12 0
*RES
-1 *419:io_out[30] *100:9 23.535
-2 *100:9 *100:13 34.38
-3 *100:13 *100:14 407.88
-4 *100:14 io_out[30] 13.365
+1 *419:io_out[30] *100:12 28.7257
+2 *100:12 *100:13 258.03
+3 *100:13 *100:15 4.5
+4 *100:15 *100:16 134.19
+5 *100:16 io_out[30] 24.165
*END
-*D_NET *101 0.119448
+*D_NET *101 0.220741
*CONN
*P io_out[31] O
-*I *419:io_out[31] O *D user_proj_example
+*I *419:io_out[31] O *D wrapped_vga_clock
*CAP
-1 io_out[31] 0.000280649
-2 *419:io_out[31] 0.00302165
-3 *101:16 0.0178453
-4 *101:15 0.0175646
-5 *101:13 0.00268155
-6 *101:12 0.00268155
-7 *101:10 0.0211262
-8 *101:9 0.0241479
-9 *101:13 *102:13 0.0011866
-10 *1:14 *101:13 0.000604551
-11 *2:11 *101:10 0
-12 *20:19 *101:10 0
-13 *45:13 *101:9 0
-14 *49:13 *101:9 0
-15 *58:10 *101:10 0
-16 *66:13 *101:13 0.0241207
-17 *95:10 *101:10 0.00313025
-18 *96:12 *101:10 0.00105689
+1 io_out[31] 0.000611329
+2 *419:io_out[31] 0.000188168
+3 *101:14 0.00849793
+4 *101:13 0.0078866
+5 *101:11 0.0189137
+6 *101:10 0.0189137
+7 *101:8 0.00339369
+8 *101:7 0.00358186
+9 *101:8 *314:11 0.0228931
+10 *8:16 *101:11 0.0732974
+11 *15:19 *101:11 0.00615481
+12 *17:8 *101:8 0.00366209
+13 *21:16 *101:8 0.00521694
+14 *40:12 *101:11 4.89586e-05
+15 *61:11 *101:11 0.000149208
+16 *66:8 *101:8 0.0413059
+17 *69:7 *101:11 0.00573516
+18 *70:11 *101:11 0
+19 *71:11 *101:11 0.000290125
*RES
-1 *419:io_out[31] *101:9 32.895
-2 *101:9 *101:10 239.31
-3 *101:10 *101:12 4.5
-4 *101:12 *101:13 45.99
-5 *101:13 *101:15 4.5
-6 *101:15 *101:16 189.63
-7 *101:16 io_out[31] 2.655
+1 *419:io_out[31] *101:7 6.345
+2 *101:7 *101:8 84.33
+3 *101:8 *101:10 4.5
+4 *101:10 *101:11 279.99
+5 *101:11 *101:13 4.5
+6 *101:13 *101:14 78.75
+7 *101:14 io_out[31] 10.665
*END
-*D_NET *102 0.233849
+*D_NET *102 0.0383944
*CONN
*P io_out[32] O
-*I *419:io_out[32] O *D user_proj_example
+*I *419:io_out[32] O *D wrapped_vga_clock
*CAP
-1 io_out[32] 0.000145659
-2 *419:io_out[32] 0.00240112
-3 *102:16 0.0177233
-4 *102:15 0.0175777
-5 *102:13 0.00157499
-6 *102:12 0.00157499
-7 *102:10 0.024418
-8 *102:9 0.0268192
-9 *102:13 *103:13 0.0702752
-10 *8:16 *102:10 0
-11 *15:16 *102:10 0
-12 *17:11 *102:10 0
-13 *18:21 *102:10 0
-14 *22:13 *102:10 0
-15 *66:13 *102:13 0.0701525
-16 *82:14 *102:10 0
-17 *101:13 *102:13 0.0011866
+1 io_out[32] 0.00342789
+2 *419:io_out[32] 0.0157693
+3 *102:5 0.0191972
*RES
-1 *419:io_out[32] *102:9 26.955
-2 *102:9 *102:10 247.05
-3 *102:10 *102:12 4.5
-4 *102:12 *102:13 108.09
-5 *102:13 *102:15 4.5
-6 *102:15 *102:16 189.99
-7 *102:16 io_out[32] 1.575
+1 *419:io_out[32] *102:5 169.065
+2 *102:5 io_out[32] 43.875
*END
-*D_NET *103 0.354329
+*D_NET *103 0.0363852
*CONN
*P io_out[33] O
-*I *419:io_out[33] O *D user_proj_example
+*I *419:io_out[33] O *D wrapped_vga_clock
*CAP
-1 io_out[33] 0.0175724
-2 *419:io_out[33] 0.00186371
-3 *103:15 0.0175724
-4 *103:13 0.0044099
-5 *103:12 0.0044099
-6 *103:10 0.00751222
-7 *103:9 0.00937593
-8 *39:7 *103:13 0.0151892
-9 *66:10 *103:10 0.176375
-10 *66:13 *103:13 0.0153439
-11 *93:10 *103:10 0.0144288
-12 *102:13 *103:13 0.0702752
+1 io_out[33] 0.00122119
+2 *419:io_out[33] 0.0169714
+3 *103:5 0.0181926
*RES
-1 *419:io_out[33] *103:9 21.915
-2 *103:9 *103:10 255.33
-3 *103:10 *103:12 4.5
-4 *103:12 *103:13 170.55
-5 *103:13 *103:15 4.5
-6 *103:15 io_out[33] 190.125
+1 *419:io_out[33] *103:5 182.025
+2 *103:5 io_out[33] 21.195
*END
-*D_NET *104 0.460372
+*D_NET *104 0.0494266
*CONN
*P io_out[34] O
-*I *419:io_out[34] O *D user_proj_example
+*I *419:io_out[34] O *D wrapped_vga_clock
*CAP
1 io_out[34] 0.000215438
-2 *419:io_out[34] 0.000150744
-3 *104:15 0.015648
-4 *104:14 0.0154326
-5 *104:12 0.02231
-6 *104:11 0.02231
-7 *104:9 0.00480456
-8 *104:8 0.00495531
-9 *104:9 *105:9 0.211191
-10 *104:12 *317:11 0.000306879
-11 *63:23 *104:9 0.00213967
-12 *63:27 *104:9 0.00243705
-13 *71:9 *104:9 0.158471
+2 *419:io_out[34] 0.00329621
+3 *104:10 0.0214171
+4 *104:9 0.0244978
*RES
-1 *419:io_out[34] *104:8 14.67
-2 *104:8 *104:9 305.73
-3 *104:9 *104:11 4.5
-4 *104:11 *104:12 221.85
-5 *104:12 *104:14 4.5
-6 *104:14 *104:15 146.97
-7 *104:15 io_out[34] 2.115
+1 *419:io_out[34] *104:9 36.675
+2 *104:9 *104:10 207.45
+3 *104:10 io_out[34] 2.115
*END
-*D_NET *105 0.477203
+*D_NET *105 0.0608946
*CONN
*P io_out[35] O
-*I *419:io_out[35] O *D user_proj_example
+*I *419:io_out[35] O *D wrapped_vga_clock
*CAP
-1 io_out[35] 0.00129702
-2 *419:io_out[35] 0.000165521
-3 *105:15 0.0137047
-4 *105:14 0.0124076
-5 *105:12 0.0291098
-6 *105:11 0.0291098
-7 *105:9 0.00643877
-8 *105:8 0.00660429
-9 *33:15 *105:9 0.165434
-10 *71:9 *105:9 0.00174075
-11 *77:9 *105:9 0
-12 *88:9 *105:9 0
-13 *104:9 *105:9 0.211191
+1 io_out[35] 0.00238169
+2 *419:io_out[35] 9.37343e-05
+3 *105:15 0.00465455
+4 *105:10 0.0202574
+5 *105:9 0.0179845
+6 *105:7 0.00771451
+7 *105:5 0.00780824
+8 *105:15 *314:5 0
+9 *29:13 *105:10 0
*RES
-1 *419:io_out[35] *105:8 14.85
-2 *105:8 *105:9 316.35
-3 *105:9 *105:11 4.5
-4 *105:11 *105:12 289.17
-5 *105:12 *105:14 4.5
-6 *105:14 *105:15 131.04
-7 *105:15 io_out[35] 13.365
+1 *419:io_out[35] *105:5 0.945
+2 *105:5 *105:7 76.41
+3 *105:7 *105:9 4.5
+4 *105:9 *105:10 195.93
+5 *105:10 *105:15 31.59
+6 *105:15 io_out[35] 25.065
*END
-*D_NET *106 0.225236
+*D_NET *106 0.0754244
*CONN
*P io_out[36] O
-*I *419:io_out[36] O *D user_proj_example
+*I *419:io_out[36] O *D wrapped_vga_clock
*CAP
-1 io_out[36] 0.000611329
-2 *419:io_out[36] 0.000855431
-3 *106:17 0.00743855
-4 *106:16 0.00682722
-5 *106:14 0.0460512
-6 *106:13 0.0460512
-7 *106:11 0.0278132
-8 *106:10 0.0286686
-9 *106:11 *107:7 0
-10 *419:io_in[37] *106:10 0.00503564
-11 *30:8 *106:17 0.055545
-12 *34:8 *106:11 0
-13 *74:8 *106:10 0.00033882
+1 io_out[36] 0.000280649
+2 *419:io_out[36] 0.00751146
+3 *106:11 0.0103258
+4 *106:10 0.0100452
+5 *106:8 0.0198749
+6 *106:7 0.0198749
+7 *106:5 0.00751146
*RES
-1 *419:io_out[36] *106:10 21.915
-2 *106:10 *106:11 258.21
-3 *106:11 *106:13 4.5
-4 *106:13 *106:14 471.33
-5 *106:14 *106:16 4.5
-6 *106:16 *106:17 104.31
-7 *106:17 io_out[36] 10.665
+1 *419:io_out[36] *106:5 79.965
+2 *106:5 *106:7 4.5
+3 *106:7 *106:8 198.27
+4 *106:8 *106:10 4.5
+5 *106:10 *106:11 108.81
+6 *106:11 io_out[36] 2.655
*END
-*D_NET *107 0.179835
+*D_NET *107 0.137536
*CONN
*P io_out[37] O
-*I *419:io_out[37] O *D user_proj_example
+*I *419:io_out[37] O *D wrapped_vga_clock
*CAP
-1 io_out[37] 0.000145659
-2 *419:io_out[37] 4.01718e-05
-3 *107:10 0.0439415
-4 *107:9 0.0437958
-5 *107:7 0.043519
-6 *107:5 0.0435592
-7 *107:7 *248:13 0
-8 *107:10 *115:8 0
-9 *107:10 *131:16 0
-10 *107:10 *141:16 0
-11 *107:10 *242:16 0
-12 *107:10 *247:16 0.00483367
-13 *107:10 *254:16 0
-14 *106:11 *107:7 0
+1 io_out[37] 0.000611329
+2 *419:io_out[37] 0.000439606
+3 *107:16 0.00414716
+4 *107:11 0.0293644
+5 *107:10 0.0258285
+6 *107:8 0.0233257
+7 *107:7 0.0237653
+8 *55:8 *107:8 0.0228931
+9 *90:11 *107:8 0.00716051
*RES
-1 *419:io_out[37] *107:5 0.405
-2 *107:5 *107:7 428.13
-3 *107:7 *107:9 4.5
-4 *107:9 *107:10 475.65
-5 *107:10 io_out[37] 1.575
+1 *419:io_out[37] *107:7 8.865
+2 *107:7 *107:8 259.65
+3 *107:8 *107:10 4.5
+4 *107:10 *107:11 282.51
+5 *107:11 *107:16 44.19
+6 *107:16 io_out[37] 6.165
*END
-*D_NET *108 0.473305
+*D_NET *108 0.143424
*CONN
*P io_out[3] O
-*I *419:io_out[3] O *D user_proj_example
+*I *419:io_out[3] O *D wrapped_vga_clock
*CAP
1 io_out[3] 0.000123625
-2 *419:io_out[3] 0.000703704
-3 *108:14 0.0352042
-4 *108:13 0.0350806
-5 *108:11 0.0251431
-6 *108:10 0.0251431
-7 *108:8 0.00823989
-8 *108:7 0.0089436
-9 *108:11 *256:13 0
-10 *108:14 *226:10 0.00975133
-11 *108:14 *232:10 0
-12 *108:14 *233:10 0
-13 *108:14 *293:16 0
-14 *23:19 *108:8 0.0132545
-15 *27:19 *108:8 0.153248
-16 *28:11 *108:8 0.15847
+2 *419:io_out[3] 0.00552949
+3 *108:10 0.0661827
+4 *108:9 0.0660591
+5 *108:7 0.00552949
+6 *86:13 *108:7 0
*RES
-1 *419:io_out[3] *108:7 10.845
-2 *108:7 *108:8 325.35
-3 *108:8 *108:10 4.5
-4 *108:10 *108:11 246.51
-5 *108:11 *108:13 4.5
-6 *108:13 *108:14 419.67
-7 *108:14 io_out[3] 1.395
+1 *419:io_out[3] *108:7 49.455
+2 *108:7 *108:9 4.5
+3 *108:9 *108:10 723.33
+4 *108:10 io_out[3] 1.395
*END
-*D_NET *109 0.319728
+*D_NET *109 0.235729
*CONN
*P io_out[4] O
-*I *419:io_out[4] O *D user_proj_example
+*I *419:io_out[4] O *D wrapped_vga_clock
*CAP
-1 io_out[4] 0.00396969
-2 *419:io_out[4] 0.00114993
-3 *109:16 0.0430942
-4 *109:15 0.0391245
-5 *109:13 0.0185328
-6 *109:12 0.0185328
-7 *109:10 0.00983816
-8 *109:9 0.0109881
-9 *53:10 *109:10 0.0169971
-10 *61:10 *109:10 0.00686353
-11 *65:8 *109:10 0.150637
-12 *97:12 *109:10 0
+1 io_out[4] 0.00248495
+2 *419:io_out[4] 0.00180316
+3 *109:11 0.0279821
+4 *109:10 0.0273003
+5 *45:14 *109:11 0.0762946
+6 *58:8 *109:11 0.000251762
+7 *78:8 *109:11 0.0481469
+8 *82:11 *109:11 0.0299862
+9 *87:8 *109:10 0.0022709
+10 *88:8 *109:10 0.00462364
+11 *89:8 *109:11 0.0145848
*RES
-1 *419:io_out[4] *109:9 14.895
-2 *109:9 *109:10 267.75
-3 *109:10 *109:12 4.5
-4 *109:12 *109:13 184.41
-5 *109:13 *109:15 4.5
-6 *109:15 *109:16 428.04
-7 *109:16 io_out[4] 43.245
+1 *419:io_out[4] *109:10 36.315
+2 *109:10 *109:11 771.57
+3 *109:11 io_out[4] 33.975
*END
-*D_NET *110 0.256021
+*D_NET *110 0.198925
*CONN
*P io_out[5] O
-*I *419:io_out[5] O *D user_proj_example
+*I *419:io_out[5] O *D wrapped_vga_clock
*CAP
-1 io_out[5] 0.000589585
-2 *419:io_out[5] 0.00472906
-3 *110:17 0.0057673
-4 *110:16 0.00517772
-5 *110:14 0.0668995
-6 *110:13 0.0716285
-7 *110:17 *111:13 0.0593503
-8 *2:8 *110:17 0.0102497
-9 *16:16 *110:14 0
-10 *70:15 *110:17 0.031629
-11 *72:7 *110:13 0
+1 io_out[5] 0.000332275
+2 *419:io_out[5] 0.000611305
+3 *110:17 0.0379026
+4 *110:16 0.0398618
+5 *110:13 0.00408854
+6 *110:10 0.00240841
+7 *32:19 *110:13 0.0230646
+8 *41:5 *110:17 0.0906558
*RES
-1 *419:io_out[5] *110:13 49.815
-2 *110:13 *110:14 725.49
-3 *110:14 *110:16 4.5
-4 *110:16 *110:17 154.17
-5 *110:17 io_out[5] 10.485
+1 *419:io_out[5] *110:10 19.1974
+2 *110:10 *110:13 37.89
+3 *110:13 *110:16 26.55
+4 *110:16 *110:17 668.07
+5 *110:17 io_out[5] 3.015
*END
-*D_NET *111 0.232937
+*D_NET *111 0.205394
*CONN
*P io_out[6] O
-*I *419:io_out[6] O *D user_proj_example
+*I *419:io_out[6] O *D wrapped_vga_clock
*CAP
-1 io_out[6] 0.000573659
-2 *419:io_out[6] 0.00478588
-3 *111:13 0.00387924
-4 *111:12 0.00330558
-5 *111:10 0.0661771
-6 *111:9 0.070963
-7 io_oeb[7] *111:13 0.0238752
-8 *16:16 *111:10 0
-9 *73:9 *111:9 2.68519e-05
-10 *110:17 *111:13 0.0593503
+1 io_out[6] 0.000258912
+2 *419:io_out[6] 0.00161168
+3 *111:19 0.0616348
+4 *111:18 0.0647837
+5 *111:13 0.00957803
+6 *111:12 0.00778195
+7 *81:14 *111:12 0
+8 *100:13 *111:13 0.0597452
*RES
-1 *419:io_out[6] *111:9 46.395
-2 *111:9 *111:10 717.57
-3 *111:10 *111:12 4.5
-4 *111:12 *111:13 87.03
-5 *111:13 io_out[6] 10.305
+1 *419:io_out[6] *111:12 28.9057
+2 *111:12 *111:13 103.95
+3 *111:13 *111:18 42.75
+4 *111:18 *111:19 668.07
+5 *111:19 io_out[6] 2.475
*END
-*D_NET *112 0.261831
+*D_NET *112 0.226107
*CONN
*P io_out[7] O
-*I *419:io_out[7] O *D user_proj_example
+*I *419:io_out[7] O *D wrapped_vga_clock
*CAP
1 io_out[7] 0.000191629
-2 *419:io_out[7] 0.00172636
-3 *112:16 0.0505202
-4 *112:15 0.0504829
-5 *112:10 0.00336084
-6 *112:9 0.00493289
-7 *49:10 *112:16 0.00954693
-8 *52:10 *112:16 0.00218216
-9 *66:10 *112:16 0.0977931
-10 *83:10 *112:16 0
-11 *85:10 *112:16 0
-12 *91:10 *112:10 0.0410941
+2 *419:io_out[7] 0.0018716
+3 *112:19 0.0602243
+4 *112:18 0.0600327
+5 *112:16 0.00959966
+6 *112:15 0.00959966
+7 *112:13 0.0063891
+8 *112:12 0.0082607
+9 *74:11 *112:13 0.0699371
+10 *87:14 *112:12 0
*RES
-1 *419:io_out[7] *112:9 20.295
-2 *112:9 *112:10 59.49
-3 *112:10 *112:15 10.35
-4 *112:15 *112:16 655.83
-5 *112:16 io_out[7] 1.935
+1 *419:io_out[7] *112:12 31.6057
+2 *112:12 *112:13 101.25
+3 *112:13 *112:15 4.5
+4 *112:15 *112:16 95.85
+5 *112:16 *112:18 4.5
+6 *112:18 *112:19 654.57
+7 *112:19 io_out[7] 1.935
*END
-*D_NET *113 0.147273
+*D_NET *113 0.250246
*CONN
*P io_out[8] O
-*I *419:io_out[8] O *D user_proj_example
+*I *419:io_out[8] O *D wrapped_vga_clock
*CAP
1 io_out[8] 0.000123625
-2 *419:io_out[8] 0.0083911
-3 *113:8 0.0652453
-4 *113:7 0.0651217
-5 *113:5 0.0083911
-6 *419:io_in[9] *113:5 0
+2 *419:io_out[8] 0.000648337
+3 *113:14 0.0361315
+4 *113:13 0.0360078
+5 *113:11 0.0281038
+6 *113:10 0.0281038
+7 *113:8 0.0163917
+8 *113:7 0.01704
+9 *63:8 *113:8 0.000308258
+10 *72:8 *113:8 0.0383588
+11 *75:11 *113:8 0.0258393
+12 *90:8 *113:8 0.0231893
*RES
-1 *419:io_out[8] *113:5 81.225
-2 *113:5 *113:7 4.5
-3 *113:7 *113:8 707.13
-4 *113:8 io_out[8] 1.395
+1 *419:io_out[8] *113:7 10.305
+2 *113:7 *113:8 315.09
+3 *113:8 *113:10 4.5
+4 *113:10 *113:11 279.27
+5 *113:11 *113:13 4.5
+6 *113:13 *113:14 392.67
+7 *113:14 io_out[8] 1.395
*END
-*D_NET *114 0.159546
+*D_NET *114 0.243096
*CONN
*P io_out[9] O
-*I *419:io_out[9] O *D user_proj_example
+*I *419:io_out[9] O *D wrapped_vga_clock
*CAP
-1 io_out[9] 0.00396967
-2 *419:io_out[9] 0.004372
-3 *114:20 0.0642542
-4 *114:19 0.0602845
-5 *114:17 0.011147
-6 *114:16 0.011147
-7 *114:14 0.004372
-8 *419:io_in[10] *114:14 0
-9 *76:9 *114:14 0
-10 *90:11 *114:17 0
+1 io_out[9] 0.00399814
+2 *419:io_out[9] 0.000326062
+3 *114:11 0.0714666
+4 *114:10 0.0674685
+5 *114:8 0.0282229
+6 *114:7 0.0285489
+7 *81:8 *114:8 0.0320995
+8 *87:8 *114:8 0.00366209
+9 *88:8 *114:8 0.00730371
*RES
-1 *419:io_out[9] *114:14 46.305
-2 *114:14 *114:16 4.5
-3 *114:16 *114:17 110.79
-4 *114:17 *114:19 4.5
-5 *114:19 *114:20 654.84
-6 *114:20 io_out[9] 43.245
+1 *419:io_out[9] *114:7 7.605
+2 *114:7 *114:8 312.75
+3 *114:8 *114:10 4.5
+4 *114:10 *114:11 734.58
+5 *114:11 io_out[9] 43.245
*END
-*D_NET *115 0.252151
-*CONN
-*P la_data_in[0] I
-*I *419:la_data_in[0] I *D user_proj_example
-*CAP
-1 la_data_in[0] 0.00378843
-2 *419:la_data_in[0] 0.00125105
-3 *115:11 0.0105662
-4 *115:10 0.00931519
-5 *115:8 0.00429878
-6 *115:7 0.00808721
-7 *419:la_data_in[0] *419:wbs_dat_i[31] 0
-8 *419:la_data_in[0] *126:11 0.000156508
-9 *419:la_data_in[0] *179:17 0
-10 *419:la_data_in[0] *372:19 0.000296905
-11 *419:la_data_in[0] *405:12 0.00111883
-12 *115:7 *188:15 0
-13 *115:8 *242:16 0.0185885
-14 *115:11 *419:wbs_dat_i[31] 0.0448657
-15 *115:11 *405:13 0.149818
-16 *107:10 *115:8 0
-*RES
-1 la_data_in[0] *115:7 40.365
-2 *115:7 *115:8 53.91
-3 *115:8 *115:10 4.5
-4 *115:10 *115:11 219.69
-5 *115:11 *419:la_data_in[0] 27.178
-*END
-
-*D_NET *116 0.132651
-*CONN
-*P la_data_in[10] I
-*I *419:la_data_in[10] I *D user_proj_example
-*CAP
-1 la_data_in[10] 0.0223521
-2 *419:la_data_in[10] 0.000960764
-3 *116:11 0.00573394
-4 *116:8 0.0119015
-5 *116:7 0.00712829
-6 *116:5 0.0223521
-7 *419:la_data_in[10] *419:la_data_in[12] 0.000435114
-8 *419:la_data_in[10] *419:la_oenb[3] 0.000419646
-9 *419:la_data_in[10] *419:la_oenb[9] 0
-10 *419:la_data_in[10] *180:7 0.000479882
-11 *419:la_data_in[10] *180:9 4.47532e-05
-12 *419:la_data_in[10] *265:11 0.000103572
-13 *419:la_data_in[10] *372:19 0
-14 *116:8 *182:14 0.0607397
-15 *116:11 *119:11 0
-16 *116:11 *183:5 0
-17 *116:11 *372:13 0
-*RES
-1 la_data_in[10] *116:5 219.645
-2 *116:5 *116:7 4.5
-3 *116:7 *116:8 109.53
-4 *116:8 *116:11 49.41
-5 *116:11 *419:la_data_in[10] 22.995
-*END
-
-*D_NET *117 0.329202
-*CONN
-*P la_data_in[11] I
-*I *419:la_data_in[11] I *D user_proj_example
-*CAP
-1 la_data_in[11] 0.000412634
-2 *419:la_data_in[11] 0.000752417
-3 *117:11 0.0153929
-4 *117:10 0.0146405
-5 *117:8 0.0049766
-6 *117:7 0.00538923
-7 *419:la_data_in[11] *419:la_oenb[10] 0.000655953
-8 *419:la_data_in[11] *181:7 0.000291535
-9 *117:7 la_data_out[11] 0
-10 *117:8 *159:8 0.042213
-11 *117:8 *251:8 0.0735462
-12 *117:11 *180:9 0.161848
-13 *117:11 *265:11 0
-14 *117:11 *370:11 0.00908361
-*RES
-1 la_data_in[11] *117:7 8.325
-2 *117:7 *117:8 125.37
-3 *117:8 *117:10 4.5
-4 *117:10 *117:11 258.93
-5 *117:11 *419:la_data_in[11] 20.1972
-*END
-
-*D_NET *118 0.136363
-*CONN
-*P la_data_in[12] I
-*I *419:la_data_in[12] I *D user_proj_example
-*CAP
-1 la_data_in[12] 0.000271935
-2 *419:la_data_in[12] 0.000723518
-3 *118:19 0.00366156
-4 *118:18 0.00293805
-5 *118:16 0.00847023
-6 *118:15 0.00847023
-7 *118:13 0.0220341
-8 *118:11 0.022306
-9 *419:la_data_in[12] *419:la_oenb[11] 0
-10 *419:la_data_in[12] *419:la_oenb[12] 0
-11 *419:la_data_in[12] *419:la_oenb[3] 0.000634086
-12 *419:la_data_in[12] *119:11 3.68254e-05
-13 *419:la_data_in[12] *182:10 0.00039012
-14 *118:13 *245:15 1.87963e-05
-15 *118:16 *262:12 0.0594963
-16 *118:19 *419:la_data_in[14] 0.000756968
-17 *118:19 *419:la_oenb[13] 0.00343704
-18 *118:19 *184:7 0
-19 *118:19 *247:19 0.00228241
-20 *419:la_data_in[10] *419:la_data_in[12] 0.000435114
-*RES
-1 la_data_in[12] *118:11 2.835
-2 *118:11 *118:13 216.81
-3 *118:13 *118:15 4.5
-4 *118:15 *118:16 123.03
-5 *118:16 *118:18 4.5
-6 *118:18 *118:19 48.15
-7 *118:19 *419:la_data_in[12] 19.935
-*END
-
-*D_NET *119 0.154945
-*CONN
-*P la_data_in[13] I
-*I *419:la_data_in[13] I *D user_proj_example
-*CAP
-1 la_data_in[13] 0.00157513
-2 *419:la_data_in[13] 0.000659385
-3 *119:11 0.0286786
-4 *119:10 0.0280192
-5 *119:8 0.00754969
-6 *119:7 0.00912482
-7 *419:la_data_in[13] *419:la_oenb[12] 0.00123774
-8 *419:la_data_in[13] *419:la_oenb[13] 0
-9 *419:la_data_in[13] *183:5 0
-10 *119:8 *212:12 0.00874512
-11 *119:8 *261:8 0.0693187
-12 *419:la_data_in[12] *119:11 3.68254e-05
-13 *116:11 *119:11 0
-*RES
-1 la_data_in[13] *119:7 19.125
-2 *119:7 *119:8 138.33
-3 *119:8 *119:10 4.5
-4 *119:10 *119:11 250.47
-5 *119:11 *419:la_data_in[13] 8.505
-*END
-
-*D_NET *120 0.451063
-*CONN
-*P la_data_in[14] I
-*I *419:la_data_in[14] I *D user_proj_example
-*CAP
-1 la_data_in[14] 0.00232097
-2 *419:la_data_in[14] 0.000764452
-3 *120:19 0.00407408
-4 *120:18 0.00330963
-5 *120:16 0.00768896
-6 *120:15 0.0100099
-7 *419:la_data_in[14] *419:la_oenb[13] 0.000483334
-8 *419:la_data_in[14] *184:7 0.00032836
-9 *120:15 la_data_out[14] 7.67196e-06
-10 *120:16 *270:16 0.0597446
-11 *120:16 *287:16 0.0392289
-12 *120:19 *183:5 0.157429
-13 *120:19 *372:13 0.164917
-14 *118:19 *419:la_data_in[14] 0.000756968
-*RES
-1 la_data_in[14] *120:15 26.685
-2 *120:15 *120:16 143.01
-3 *120:16 *120:18 4.5
-4 *120:18 *120:19 241.83
-5 *120:19 *419:la_data_in[14] 21.058
-*END
-
-*D_NET *121 0.123456
-*CONN
-*P la_data_in[15] I
-*I *419:la_data_in[15] I *D user_proj_example
-*CAP
-1 la_data_in[15] 0.0270387
-2 *419:la_data_in[15] 0.000406287
-3 *121:8 0.0124994
-4 *121:7 0.0120931
-5 *121:5 0.0270387
-6 *419:la_data_in[15] *419:la_oenb[14] 0.000431548
-7 *419:la_data_in[15] *122:19 0.000282328
-8 *419:la_data_in[15] *185:7 0.000479882
-9 *121:8 *419:la_data_in[19] 0.000352295
-10 *121:8 *419:la_oenb[57] 0.000683535
-11 *121:8 *150:16 0.00609255
-12 *121:8 *166:16 0.0265462
-13 *121:8 *238:14 0.00951187
-*RES
-1 la_data_in[15] *121:5 262.845
-2 *121:5 *121:7 4.5
-3 *121:7 *121:8 149.13
-4 *121:8 *419:la_data_in[15] 12.825
-*END
-
-*D_NET *122 0.320702
-*CONN
-*P la_data_in[16] I
-*I *419:la_data_in[16] I *D user_proj_example
-*CAP
-1 la_data_in[16] 0.00311369
-2 *419:la_data_in[16] 0.000685614
-3 *122:19 0.014599
-4 *122:18 0.0139134
-5 *122:16 0.00769301
-6 *122:15 0.0108067
-7 *419:la_data_in[16] *419:la_oenb[15] 0.000441905
-8 *419:la_data_in[16] *419:la_oenb[16] 0
-9 *419:la_data_in[16] *419:la_oenb[3] 0.000186509
-10 *419:la_data_in[16] *186:7 0
-11 *419:la_data_in[16] *248:24 3.62657e-05
-12 *419:la_data_in[16] *276:19 0.00014321
-13 *122:16 *123:16 0.106372
-14 *122:16 *240:8 0.000621697
-15 *122:16 *243:16 0.0112527
-16 *122:19 *185:9 0.150555
-17 *122:19 *276:19 0
-18 *419:la_data_in[15] *122:19 0.000282328
-*RES
-1 la_data_in[16] *122:15 34.425
-2 *122:15 *122:16 156.69
-3 *122:16 *122:18 4.5
-4 *122:18 *122:19 236.79
-5 *122:19 *419:la_data_in[16] 17.685
-*END
-
-*D_NET *123 0.348762
-*CONN
-*P la_data_in[17] I
-*I *419:la_data_in[17] I *D user_proj_example
-*CAP
-1 la_data_in[17] 0.00322552
-2 *419:la_data_in[17] 0.00103001
-3 *123:19 0.0144403
-4 *123:18 0.0134103
-5 *123:16 0.00431445
-6 *123:15 0.00753997
-7 *419:la_data_in[17] *419:la_oenb[16] 0.000918335
-8 *419:la_data_in[17] *419:la_oenb[17] 0
-9 *419:la_data_in[17] *187:11 0
-10 *419:la_data_in[17] *251:11 0.000199471
-11 *123:15 *250:11 1.87963e-05
-12 *123:16 *240:8 0.0522846
-13 *123:16 *302:16 0.0243083
-14 *123:19 *419:la_oenb[16] 0.000751853
-15 *123:19 *186:7 0.00272099
-16 *123:19 *250:19 0.0068127
-17 *123:19 *276:19 0
-18 *123:19 *373:13 0.110415
-19 *122:16 *123:16 0.106372
-*RES
-1 la_data_in[17] *123:15 35.325
-2 *123:15 *123:16 162.09
-3 *123:16 *123:18 4.5
-4 *123:18 *123:19 231.39
-5 *123:19 *419:la_data_in[17] 23.6172
-*END
-
-*D_NET *124 0.327838
-*CONN
-*P la_data_in[18] I
-*I *419:la_data_in[18] I *D user_proj_example
-*CAP
-1 la_data_in[18] 0.00441495
-2 *419:la_data_in[18] 0.0012105
-3 *124:19 0.00587567
-4 *124:18 0.00466518
-5 *124:16 0.00830204
-6 *124:15 0.012717
-7 *419:la_data_in[18] *419:la_oenb[17] 0.00117074
-8 *419:la_data_in[18] *419:la_oenb[18] 0
-9 *419:la_data_in[18] *187:11 0.000122752
-10 *419:la_data_in[18] *187:13 0.00247038
-11 *419:la_data_in[18] *188:7 0
-12 *419:la_data_in[18] *304:11 0.00597391
-13 *124:16 *244:16 0.0706867
-14 *124:16 *285:16 0.0597446
-15 *124:19 *187:13 0.135272
-16 *124:19 *304:11 0.0152112
-*RES
-1 la_data_in[18] *124:15 47.205
-2 *124:15 *124:16 169.83
-3 *124:16 *124:18 4.5
-4 *124:18 *124:19 198.36
-5 *124:19 *419:la_data_in[18] 33.615
-*END
-
-*D_NET *125 0.220409
-*CONN
-*P la_data_in[19] I
-*I *419:la_data_in[19] I *D user_proj_example
-*CAP
-1 la_data_in[19] 0.00508527
-2 *419:la_data_in[19] 0.000735607
-3 *125:19 0.0134146
-4 *125:18 0.012679
-5 *125:16 0.0130581
-6 *125:15 0.0130581
-7 *125:13 0.00508527
-8 *419:la_data_in[19] *419:la_oenb[18] 0.000614525
-9 *419:la_data_in[19] *419:la_oenb[19] 0
-10 *419:la_data_in[19] *189:7 0
-11 *419:la_data_in[19] *189:9 0
-12 *125:13 *189:15 7.67196e-06
-13 *125:16 *143:8 0.0913213
-14 *125:19 *188:7 0.00300741
-15 *125:19 *188:9 0.0413059
-16 *125:19 *252:26 0.0206836
-17 *125:19 *304:11 0
-18 *121:8 *419:la_data_in[19] 0.000352295
-*RES
-1 la_data_in[19] *125:13 49.185
-2 *125:13 *125:15 4.5
-3 *125:15 *125:16 175.41
-4 *125:16 *125:18 4.5
-5 *125:18 *125:19 216.45
-6 *125:19 *419:la_data_in[19] 19.125
-*END
-
-*D_NET *126 0.246766
-*CONN
-*P la_data_in[1] I
-*I *419:la_data_in[1] I *D user_proj_example
-*CAP
-1 la_data_in[1] 0.00130048
-2 *419:la_data_in[1] 0.000822663
-3 *126:11 0.0149669
-4 *126:10 0.0141443
-5 *126:8 0.00186653
-6 *126:7 0.00316701
-7 *419:la_data_in[1] *419:la_oenb[0] 0.00111883
-8 *419:la_data_in[1] *190:7 0.000383598
-9 *126:7 *258:11 0
-10 *126:8 *170:8 0.0048741
-11 *126:8 *187:16 0.000248679
-12 *126:8 *304:8 0.0092633
-13 *126:8 *405:16 0.0333852
-14 *126:11 wbs_dat_o[26] 0.0060762
-15 *126:11 *419:la_oenb[0] 0.000386667
-16 *126:11 *243:19 0.154605
-17 *126:11 *335:11 0
-18 *419:la_data_in[0] *126:11 0.000156508
-*RES
-1 la_data_in[1] *126:7 16.605
-2 *126:7 *126:8 60.57
-3 *126:8 *126:10 4.5
-4 *126:10 *126:11 247.95
-5 *126:11 *419:la_data_in[1] 22.545
-*END
-
-*D_NET *127 0.189114
-*CONN
-*P la_data_in[20] I
-*I *419:la_data_in[20] I *D user_proj_example
-*CAP
-1 la_data_in[20] 0.0062322
-2 *419:la_data_in[20] 0.00102417
-3 *127:11 0.0142766
-4 *127:10 0.0132524
-5 *127:8 0.0175454
-6 *127:7 0.0175454
-7 *127:5 0.0062322
-8 *419:la_data_in[20] *419:la_oenb[19] 0.000918335
-9 *419:la_data_in[20] *419:la_oenb[20] 0
-10 *419:la_data_in[20] *191:11 0
-11 *419:la_data_in[20] *255:11 0.000199471
-12 *127:11 *189:9 0.111888
-13 *31:13 *127:8 0
-*RES
-1 la_data_in[20] *127:5 54.765
-2 *127:5 *127:7 4.5
-3 *127:7 *127:8 183.69
-4 *127:8 *127:10 4.5
-5 *127:10 *127:11 204.57
-6 *127:11 *419:la_data_in[20] 23.6172
-*END
-
-*D_NET *128 0.306562
-*CONN
-*P la_data_in[21] I
-*I *419:la_data_in[21] I *D user_proj_example
-*CAP
-1 la_data_in[21] 0.00014502
-2 *419:la_data_in[21] 0.00120089
-3 *128:19 0.0100762
-4 *128:18 0.00887528
-5 *128:16 0.0121698
-6 *128:15 0.0121698
-7 *128:13 0.00542032
-8 *128:11 0.00556534
-9 *419:la_data_in[21] *419:la_oenb[20] 0.00127968
-10 *419:la_data_in[21] *419:la_oenb[21] 0
-11 *419:la_data_in[21] *182:11 0.00601483
-12 *419:la_data_in[21] *191:11 0.000122752
-13 *419:la_data_in[21] *191:13 0.00247037
-14 *419:la_data_in[21] *192:7 0
-15 *128:16 *147:16 0.0969223
-16 *128:19 la_data_out[0] 0.0146688
-17 *128:19 *182:11 0.00155357
-18 *128:19 *191:13 0.127907
-*RES
-1 la_data_in[21] *128:11 1.755
-2 *128:11 *128:13 52.29
-3 *128:13 *128:15 4.5
-4 *128:15 *128:16 188.73
-5 *128:16 *128:18 4.5
-6 *128:18 *128:19 187.56
-7 *128:19 *419:la_data_in[21] 33.615
-*END
-
-*D_NET *129 0.237172
-*CONN
-*P la_data_in[22] I
-*I *419:la_data_in[22] I *D user_proj_example
-*CAP
-1 la_data_in[22] 0.00484382
-2 *419:la_data_in[22] 0.00074291
-3 *129:19 0.0182888
-4 *129:18 0.0175459
-5 *129:16 0.0128439
-6 *129:15 0.0128439
-7 *129:13 0.00484382
-8 *419:la_data_in[22] *419:la_oenb[21] 0.000504048
-9 *419:la_data_in[22] *193:10 0
-10 *129:13 *256:11 1.87963e-05
-11 *129:16 *185:12 0.0933163
-12 *129:19 *182:11 0
-13 *129:19 *192:9 0.07138
-*RES
-1 la_data_in[22] *129:13 46.845
-2 *129:13 *129:15 4.5
-3 *129:15 *129:16 194.49
-4 *129:16 *129:18 4.5
-5 *129:18 *129:19 220.77
-6 *129:19 *419:la_data_in[22] 18.2172
-*END
-
-*D_NET *130 0.266044
-*CONN
-*P la_data_in[23] I
-*I *419:la_data_in[23] I *D user_proj_example
-*CAP
-1 la_data_in[23] 0.00412382
-2 *419:la_data_in[23] 0.00322903
-3 *130:19 0.0234575
-4 *130:18 0.0202285
-5 *130:16 0.00750841
-6 *130:15 0.0116322
-7 *419:la_data_in[23] *419:la_oenb[22] 0.00119683
-8 *419:la_data_in[23] *194:15 0
-9 *419:la_data_in[23] *258:11 0.000699683
-10 *130:16 *138:8 0.126763
-11 *130:16 *245:16 0.0672049
-*RES
-1 la_data_in[23] *130:15 44.505
-2 *130:15 *130:16 202.59
-3 *130:16 *130:18 4.5
-4 *130:18 *130:19 201.06
-5 *130:19 *419:la_data_in[23] 33.795
-*END
-
-*D_NET *131 0.430634
-*CONN
-*P la_data_in[24] I
-*I *419:la_data_in[24] I *D user_proj_example
-*CAP
-1 la_data_in[24] 0.00397602
-2 *419:la_data_in[24] 0.000949548
-3 *131:19 0.0129624
-4 *131:18 0.0120129
-5 *131:16 0.00674822
-6 *131:15 0.0107242
-7 *419:la_data_in[24] *419:la_oenb[23] 0.00102932
-8 *419:la_data_in[24] *419:la_oenb[24] 0
-9 *419:la_data_in[24] *195:10 0
-10 *131:15 *195:17 7.67196e-06
-11 *131:15 *258:7 0
-12 *131:16 *136:16 0.134348
-13 *131:16 *247:16 0.0782711
-14 *131:16 *254:16 0.00180292
-15 *131:19 *194:15 0.013073
-16 *131:19 *258:11 0.154728
-17 *107:10 *131:16 0
-*RES
-1 la_data_in[24] *131:15 40.185
-2 *131:15 *131:16 207.81
-3 *131:16 *131:18 4.5
-4 *131:18 *131:19 227.61
-5 *131:19 *419:la_data_in[24] 21.465
-*END
-
-*D_NET *132 0.200309
-*CONN
-*P la_data_in[25] I
-*I *419:la_data_in[25] I *D user_proj_example
-*CAP
-1 la_data_in[25] 0.0266649
-2 *419:la_data_in[25] 0.000813334
-3 *132:8 0.0144016
-4 *132:7 0.0135883
-5 *132:5 0.0266649
-6 *419:la_data_in[25] *419:la_oenb[24] 0
-7 *419:la_data_in[25] *419:la_oenb[25] 3.45239e-06
-8 *419:la_data_in[25] *196:11 0.00395055
-9 *132:8 *419:la_data_in[27] 0.000236245
-10 *132:8 *419:la_data_in[29] 0.000236245
-11 *132:8 *419:la_data_in[39] 0.000154129
-12 *132:8 *419:la_oenb[30] 0.000136773
-13 *132:8 *419:la_oenb[32] 0.000186509
-14 *132:8 *419:la_oenb[34] 0.000186509
-15 *132:8 *419:la_oenb[36] 0.000186509
-16 *132:8 *419:la_oenb[39] 0.000186509
-17 *132:8 *419:la_oenb[40] 0.000186509
-18 *132:8 *419:la_oenb[41] 0.000186509
-19 *132:8 *419:la_oenb[42] 0.000186509
-20 *132:8 *419:la_oenb[43] 0.000186509
-21 *132:8 *146:16 0.111967
-*RES
-1 la_data_in[25] *132:5 260.505
-2 *132:5 *132:7 4.5
-3 *132:7 *132:8 213.39
-4 *132:8 *419:la_data_in[25] 15.975
-*END
-
-*D_NET *133 0.213701
-*CONN
-*P la_data_in[26] I
-*I *419:la_data_in[26] I *D user_proj_example
-*CAP
-1 la_data_in[26] 0.00014502
-2 *419:la_data_in[26] 0.000498468
-3 *133:26 0.0041588
-4 *133:24 0.00492309
-5 *133:16 0.00858045
-6 *133:15 0.00731769
-7 *133:13 0.0263754
-8 *133:11 0.0265204
-9 *419:la_data_in[26] *419:la_oenb[25] 0
-10 *419:la_data_in[26] *197:17 0.000272738
-11 *133:13 *197:23 0
-12 *133:16 *139:16 0.00310848
-13 *133:16 *259:16 0.0866022
-14 *133:24 *419:la_data_in[56] 0.000306879
-15 *133:24 *419:la_oenb[49] 5.43985e-05
-16 *133:24 *419:la_oenb[54] 0.000310848
-17 *133:24 *419:la_oenb[55] 0.00020538
-18 *133:24 *142:21 0.000908361
-19 *133:24 *142:22 0.00337781
-20 *133:24 *230:7 0.000171852
-21 *133:26 *419:la_oenb[22] 0.000746036
-22 *133:26 *419:la_oenb[44] 0.00187752
-23 *133:26 *142:22 0.0302144
-24 *133:26 *193:12 0
-25 *133:26 *248:24 0.00690085
-26 *133:26 *269:24 0.000124339
-*RES
-1 la_data_in[26] *133:11 1.755
-2 *133:11 *133:13 258.03
-3 *133:13 *133:15 4.5
-4 *133:15 *133:16 138.87
-5 *133:16 *133:24 31.86
-6 *133:24 *133:26 65.34
-7 *133:26 *419:la_data_in[26] 10.305
-*END
-
-*D_NET *134 0.330138
-*CONN
-*P la_data_in[27] I
-*I *419:la_data_in[27] I *D user_proj_example
-*CAP
-1 la_data_in[27] 0.000388835
-2 *419:la_data_in[27] 0.000934354
-3 *134:11 0.016118
-4 *134:10 0.0151836
-5 *134:8 0.0158798
-6 *134:7 0.0162686
-7 *419:la_data_in[27] *419:la_oenb[26] 0.000537038
-8 *419:la_data_in[27] *419:la_oenb[27] 0
-9 *419:la_data_in[27] *198:11 0
-10 *419:la_data_in[27] *246:11 0.00132981
-11 *134:8 *251:8 0.0990357
-12 *134:11 *419:la_oenb[26] 0.000414286
-13 *134:11 *246:11 0
-14 *134:11 *261:11 0.163812
-15 *132:8 *419:la_data_in[27] 0.000236245
-*RES
-1 la_data_in[27] *134:7 7.965
-2 *134:7 *134:8 229.05
-3 *134:8 *134:10 4.5
-4 *134:10 *134:11 256.59
-5 *134:11 *419:la_data_in[27] 22.545
-*END
-
-*D_NET *135 0.232012
-*CONN
-*P la_data_in[28] I
-*I *419:la_data_in[28] I *D user_proj_example
-*CAP
-1 la_data_in[28] 0.000119863
-2 *419:la_data_in[28] 0.00243186
-3 *135:15 0.0168606
-4 *135:14 0.0144287
-5 *135:12 0.0149918
-6 *135:11 0.0151117
-7 *419:la_data_in[28] *419:la_oenb[27] 0.0015881
-8 *419:la_data_in[28] *136:19 0.000693546
-9 *419:la_data_in[28] *199:17 0
-10 *419:la_data_in[28] *262:17 0
-11 *135:12 *188:16 0.100902
-12 *135:15 la_data_out[2] 0.049295
-13 *135:15 *262:17 0.0155894
-*RES
-1 la_data_in[28] *135:11 5.805
-2 *135:11 *135:12 234.81
-3 *135:12 *135:14 4.5
-4 *135:14 *135:15 240.3
-5 *135:15 *419:la_data_in[28] 33.255
-*END
-
-*D_NET *136 0.243939
-*CONN
-*P la_data_in[29] I
-*I *419:la_data_in[29] I *D user_proj_example
-*CAP
-1 la_data_in[29] 0.00364017
-2 *419:la_data_in[29] 0.000956008
-3 *136:19 0.0215747
-4 *136:18 0.0206187
-5 *136:16 0.0146281
-6 *136:15 0.0182682
-7 *419:la_data_in[29] *419:la_oenb[28] 0.00111883
-8 *419:la_data_in[29] *419:la_oenb[29] 0
-9 *419:la_data_in[29] *200:7 0
-10 *136:15 *200:11 7.67196e-06
-11 *136:19 *419:la_oenb[28] 0.000414286
-12 *136:19 *263:21 0.0274349
-13 *419:la_data_in[28] *136:19 0.000693546
-14 *131:16 *136:16 0.134348
-15 *132:8 *419:la_data_in[29] 0.000236245
-*RES
-1 la_data_in[29] *136:15 40.005
-2 *136:15 *136:16 240.39
-3 *136:16 *136:18 4.5
-4 *136:18 *136:19 226.89
-5 *136:19 *419:la_data_in[29] 22.545
-*END
-
-*D_NET *137 0.202109
-*CONN
-*P la_data_in[2] I
-*I *419:la_data_in[2] I *D user_proj_example
-*CAP
-1 la_data_in[2] 0.000247279
-2 *419:la_data_in[2] 0.000711893
-3 *137:19 0.0039038
-4 *137:16 0.00958762
-5 *137:15 0.00639571
-6 *137:13 0.0154104
-7 *137:11 0.0156577
-8 *419:la_data_in[2] *419:la_oenb[1] 0
-9 *419:la_data_in[2] *201:11 0.000528215
-10 *419:la_data_in[2] *372:19 0
-11 *419:la_data_in[2] *401:10 0
-12 *137:13 *254:15 7.67196e-06
-13 *137:13 *260:11 0.146627
-14 *137:19 *419:la_data_in[3] 0.00100247
-15 *137:19 *148:15 0
-16 *137:19 *159:11 0
-17 *137:19 *201:11 0.00203
-*RES
-1 la_data_in[2] *137:11 2.655
-2 *137:11 *137:13 222.21
-3 *137:13 *137:15 4.5
-4 *137:15 *137:16 61.11
-5 *137:16 *137:19 46.71
-6 *137:19 *419:la_data_in[2] 17.775
-*END
-
-*D_NET *138 0.355374
-*CONN
-*P la_data_in[30] I
-*I *419:la_data_in[30] I *D user_proj_example
-*CAP
-1 la_data_in[30] 0.00398698
-2 *419:la_data_in[30] 0.00115028
-3 *138:11 0.00903739
-4 *138:10 0.00788711
-5 *138:8 0.0158099
-6 *138:7 0.0197969
-7 *419:la_data_in[30] *419:la_oenb[29] 0.0130815
-8 *419:la_data_in[30] *202:15 0
-9 *419:la_data_in[30] *248:19 0.00589207
-10 *419:la_data_in[30] *264:11 0.000821668
-11 *138:11 *148:9 0.00742646
-12 *138:11 *248:19 0.00648434
-13 *138:11 *264:11 0.137236
-14 *130:16 *138:8 0.126763
-*RES
-1 la_data_in[30] *138:7 43.065
-2 *138:7 *138:8 248.31
-3 *138:8 *138:10 4.5
-4 *138:10 *138:11 201.24
-5 *138:11 *419:la_data_in[30] 33.795
-*END
-
-*D_NET *139 0.348672
-*CONN
-*P la_data_in[31] I
-*I *419:la_data_in[31] I *D user_proj_example
-*CAP
-1 la_data_in[31] 0.00014502
-2 *419:la_data_in[31] 0.000889888
-3 *139:16 0.0079247
-4 *139:15 0.00703481
-5 *139:13 0.0262675
-6 *139:11 0.0264125
-7 *419:la_data_in[31] *419:la_oenb[30] 0.000447532
-8 *419:la_data_in[31] *419:la_oenb[31] 0
-9 *419:la_data_in[31] *195:13 0.00206632
-10 *419:la_data_in[31] *203:15 0
-11 *419:la_data_in[31] *267:19 8.28572e-05
-12 *139:16 *158:18 0.141063
-13 *139:16 *259:16 0.133229
-14 *133:16 *139:16 0.00310848
-*RES
-1 la_data_in[31] *139:11 1.755
-2 *139:11 *139:13 257.67
-3 *139:13 *139:15 4.5
-4 *139:15 *139:16 252.27
-5 *139:16 *419:la_data_in[31] 18.675
-*END
-
-*D_NET *140 0.361551
-*CONN
-*P la_data_in[32] I
-*I *419:la_data_in[32] I *D user_proj_example
-*CAP
-1 la_data_in[32] 0.000271935
-2 *419:la_data_in[32] 0.00103121
-3 *140:16 0.00836189
-4 *140:15 0.00733068
-5 *140:13 0.0259563
-6 *140:11 0.0262282
-7 *419:la_data_in[32] *419:la_oenb[31] 0.000400477
-8 *419:la_data_in[32] *257:15 0.00255732
-9 *419:la_data_in[32] *268:11 0.000181058
-10 *140:13 *267:11 1.87963e-05
-11 *140:16 *142:16 0.133603
-12 *140:16 *153:16 0.15561
-13 *23:16 *140:13 0
-*RES
-1 la_data_in[32] *140:11 2.835
-2 *140:11 *140:13 254.79
-3 *140:13 *140:15 4.5
-4 *140:15 *140:16 257.67
-5 *140:16 *419:la_data_in[32] 21.555
-*END
-
-*D_NET *141 0.270824
-*CONN
-*P la_data_in[33] I
-*I *419:la_data_in[33] I *D user_proj_example
-*CAP
-1 la_data_in[33] 0.00378052
-2 *419:la_data_in[33] 0.000951084
-3 *141:19 0.0132093
-4 *141:18 0.0122582
-5 *141:16 0.0232995
-6 *141:15 0.0270801
-7 *419:la_data_in[33] *419:la_oenb[32] 0.00254709
-8 *419:la_data_in[33] *204:9 4.47532e-06
-9 *419:la_data_in[33] *205:7 0
-10 *141:15 *205:11 0
-11 *141:16 *242:16 0.0335095
-12 *141:19 *204:9 0.00129784
-13 *141:19 *268:11 0.152887
-14 *107:10 *141:16 0
-*RES
-1 la_data_in[33] *141:15 41.625
-2 *141:15 *141:16 267.21
-3 *141:16 *141:18 4.5
-4 *141:18 *141:19 224.19
-5 *141:19 *419:la_data_in[33] 22.678
-*END
-
-*D_NET *142 0.283289
-*CONN
-*P la_data_in[34] I
-*I *419:la_data_in[34] I *D user_proj_example
-*CAP
-1 la_data_in[34] 0.000203572
-2 *419:la_data_in[34] 0.000447276
-3 *142:22 0.00146477
-4 *142:21 0.00172911
-5 *142:16 0.0118327
-6 *142:15 0.0111211
-7 *142:13 0.0259516
-8 *142:11 0.0261552
-9 *419:la_data_in[34] *419:la_oenb[33] 0.000403929
-10 *419:la_data_in[34] *206:9 0
-11 *142:11 *206:13 7.67196e-06
-12 *142:16 *153:16 0.00435188
-13 *142:21 *419:la_oenb[55] 0.000675133
-14 *142:21 *229:9 0.000365186
-15 *142:21 *230:7 0
-16 *142:22 *419:la_data_in[38] 0.0116258
-17 *142:22 *419:la_data_in[41] 0.000419633
-18 *142:22 *419:la_oenb[49] 0.000663069
-19 *142:22 *144:16 0
-20 *142:22 *207:10 0.000111905
-21 *142:22 *219:13 0.0153559
-22 *142:22 *269:24 0.00230028
-23 *133:24 *142:21 0.000908361
-24 *133:24 *142:22 0.00337781
-25 *133:26 *142:22 0.0302144
-26 *140:16 *142:16 0.133603
-*RES
-1 la_data_in[34] *142:11 2.295
-2 *142:11 *142:13 254.97
-3 *142:13 *142:15 4.5
-4 *142:15 *142:16 212.31
-5 *142:16 *142:21 19.71
-6 *142:21 *142:22 58.41
-7 *142:22 *419:la_data_in[34] 10.125
-*END
-
-*D_NET *143 0.323472
-*CONN
-*P la_data_in[35] I
-*I *419:la_data_in[35] I *D user_proj_example
-*CAP
-1 la_data_in[35] 0.0047788
-2 *419:la_data_in[35] 0.000967206
-3 *143:11 0.0122069
-4 *143:10 0.0112397
-5 *143:8 0.0238757
-6 *143:7 0.0238757
-7 *143:5 0.0047788
-8 *419:la_data_in[35] *419:la_oenb[34] 0.00254709
-9 *419:la_data_in[35] *419:la_oenb[35] 0
-10 *419:la_data_in[35] *206:9 4.47532e-06
-11 *419:la_data_in[35] *207:10 0
-12 *143:11 *206:9 0.00235402
-13 *143:11 *270:19 0.145522
-14 *125:16 *143:8 0.0913213
-*RES
-1 la_data_in[35] *143:5 46.665
-2 *143:5 *143:7 4.5
-3 *143:7 *143:8 280.71
-4 *143:8 *143:10 4.5
-5 *143:10 *143:11 213.39
-6 *143:11 *419:la_data_in[35] 22.678
-*END
-
-*D_NET *144 0.289666
-*CONN
-*P la_data_in[36] I
-*I *419:la_data_in[36] I *D user_proj_example
-*CAP
-1 la_data_in[36] 0.00014502
-2 *419:la_data_in[36] 0.000440451
-3 *144:16 0.00718842
-4 *144:15 0.00674797
-5 *144:13 0.0271678
-6 *144:11 0.0273128
-7 *419:la_data_in[36] *419:la_oenb[35] 0
-8 *419:la_data_in[36] *208:9 0.000150371
-9 *144:16 *419:la_data_in[38] 2.79764e-05
-10 *144:16 *419:la_data_in[41] 0.00269402
-11 *144:16 *419:la_data_in[47] 0.00136773
-12 *144:16 *419:la_oenb[50] 0.00553311
-13 *144:16 *419:la_oenb[53] 0.0055744
-14 *144:16 *193:12 0.00563664
-15 *144:16 *207:10 0.0012421
-16 *144:16 *217:13 0.00167847
-17 *144:16 *217:14 0.179111
-18 *144:16 *219:13 6.21698e-05
-19 *144:16 *238:13 0.00341934
-20 *144:16 *290:14 1.81328e-05
-21 *144:16 *294:16 0.00275412
-22 *144:16 *301:20 0.00340688
-23 *144:16 *310:8 0.00798725
-24 *142:22 *144:16 0
-*RES
-1 la_data_in[36] *144:11 1.755
-2 *144:11 *144:13 266.85
-3 *144:13 *144:15 4.5
-4 *144:15 *144:16 283.77
-5 *144:16 *419:la_data_in[36] 9.315
-*END
-
-*D_NET *145 0.284173
-*CONN
-*P la_data_in[37] I
-*I *419:la_data_in[37] I *D user_proj_example
-*CAP
-1 la_data_in[37] 0.000271935
-2 *419:la_data_in[37] 0.00128217
-3 *145:16 0.0171152
-4 *145:15 0.015833
-5 *145:13 0.0256498
-6 *145:11 0.0259217
-7 *419:la_data_in[37] *419:la_oenb[36] 0.00254709
-8 *419:la_data_in[37] *419:la_oenb[37] 0
-9 *419:la_data_in[37] *208:9 0.000756329
-10 *419:la_data_in[37] *209:11 0
-11 *145:13 *272:15 1.87963e-05
-12 *145:16 *149:8 0.194777
-*RES
-1 la_data_in[37] *145:11 2.835
-2 *145:11 *145:13 252.45
-3 *145:13 *145:15 4.5
-4 *145:15 *145:16 290.07
-5 *145:16 *419:la_data_in[37] 23.895
-*END
-
-*D_NET *146 0.375781
-*CONN
-*P la_data_in[38] I
-*I *419:la_data_in[38] I *D user_proj_example
-*CAP
-1 la_data_in[38] 8.61527e-05
-2 *419:la_data_in[38] 0.00125501
-3 *146:16 0.0104195
-4 *146:15 0.00916452
-5 *146:13 0.026448
-6 *146:11 0.0265342
-7 *419:la_data_in[38] *419:la_data_in[41] 0.000879442
-8 *419:la_data_in[38] *419:la_data_in[44] 0.000187196
-9 *419:la_data_in[38] *419:la_oenb[37] 0
-10 *419:la_data_in[38] *419:la_oenb[44] 0
-11 *419:la_data_in[38] *207:10 0.00167858
-12 *419:la_data_in[38] *210:13 0.000417739
-13 *419:la_data_in[38] *269:24 2.07143e-05
-14 *146:16 *419:la_oenb[45] 0.000310848
-15 *146:16 *219:14 0.174759
-16 *132:8 *146:16 0.111967
-17 *142:22 *419:la_data_in[38] 0.0116258
-18 *144:16 *419:la_data_in[38] 2.79764e-05
-*RES
-1 la_data_in[38] *146:11 1.215
-2 *146:11 *146:13 260.37
-3 *146:13 *146:15 4.5
-4 *146:15 *146:16 280.89
-5 *146:16 *419:la_data_in[38] 41.265
-*END
-
-*D_NET *147 0.318034
-*CONN
-*P la_data_in[39] I
-*I *419:la_data_in[39] I *D user_proj_example
-*CAP
-1 la_data_in[39] 0.000208583
-2 *419:la_data_in[39] 0.00101273
-3 *147:19 0.0122866
-4 *147:18 0.0112739
-5 *147:16 0.022855
-6 *147:15 0.022855
-7 *147:13 0.00492118
-8 *147:11 0.00512976
-9 *419:la_data_in[39] *419:la_oenb[38] 0.000876906
-10 *419:la_data_in[39] *275:11 9.20636e-06
-11 *147:11 *211:13 7.67196e-06
-12 *147:13 *158:13 0.000853122
-13 *147:13 *158:15 0
-14 *147:13 *274:7 0
-15 *147:19 *210:13 0.00603528
-16 *147:19 *269:24 0
-17 *147:19 *274:11 0.132633
-18 *128:16 *147:16 0.0969223
-19 *132:8 *419:la_data_in[39] 0.000154129
-*RES
-1 la_data_in[39] *147:11 2.295
-2 *147:11 *147:13 52.11
-3 *147:13 *147:15 4.5
-4 *147:15 *147:16 305.01
-5 *147:16 *147:18 4.5
-6 *147:18 *147:19 207.81
-7 *147:19 *419:la_data_in[39] 22.545
-*END
-
-*D_NET *148 0.0861221
-*CONN
-*P la_data_in[3] I
-*I *419:la_data_in[3] I *D user_proj_example
-*CAP
-1 la_data_in[3] 0.00362048
-2 *419:la_data_in[3] 0.00100172
-3 *148:15 0.0210724
-4 *148:14 0.0200707
-5 *148:12 0.00750009
-6 *148:11 0.00750009
-7 *148:9 0.00362048
-8 *419:la_data_in[3] *419:la_oenb[2] 0.00123774
-9 *419:la_data_in[3] *159:11 3.06879e-06
-10 *419:la_data_in[3] *201:11 0
-11 *419:la_data_in[3] *212:7 0
-12 *148:9 *264:11 0.00464001
-13 *148:15 *201:11 0.00742647
-14 *137:19 *419:la_data_in[3] 0.00100247
-15 *137:19 *148:15 0
-16 *138:11 *148:9 0.00742646
-*RES
-1 la_data_in[3] *148:9 49.725
-2 *148:9 *148:11 4.5
-3 *148:11 *148:12 73.35
-4 *148:12 *148:14 4.5
-5 *148:14 *148:15 210.69
-6 *148:15 *419:la_data_in[3] 22.545
-*END
-
-*D_NET *149 0.455499
-*CONN
-*P la_data_in[40] I
-*I *419:la_data_in[40] I *D user_proj_example
-*CAP
-1 la_data_in[40] 0.0256001
-2 *419:la_data_in[40] 0.00117811
-3 *149:8 0.00744273
-4 *149:7 0.00626462
-5 *149:5 0.0256001
-6 *419:la_data_in[40] *419:la_oenb[39] 0.00254709
-7 *419:la_data_in[40] *419:la_oenb[40] 0
-8 *419:la_data_in[40] *211:9 0.00077423
-9 *419:la_data_in[40] *213:15 0
-10 *419:la_data_in[40] *277:19 0.000266984
-11 *149:8 *163:16 0.191047
-12 *50:13 *149:5 0
-13 *145:16 *149:8 0.194777
-*RES
-1 la_data_in[40] *149:5 252.225
-2 *149:5 *149:7 4.5
-3 *149:7 *149:8 311.67
-4 *149:8 *419:la_data_in[40] 24.075
-*END
-
-*D_NET *150 0.290799
-*CONN
-*P la_data_in[41] I
-*I *419:la_data_in[41] I *D user_proj_example
-*CAP
-1 la_data_in[41] 0.00014502
-2 *419:la_data_in[41] 0.00115729
-3 *150:16 0.0170919
-4 *150:15 0.0159346
-5 *150:13 0.0267174
-6 *150:11 0.0268624
-7 *419:la_data_in[41] *419:la_data_in[46] 0.000113545
-8 *419:la_data_in[41] *419:la_oenb[40] 0
-9 *419:la_data_in[41] *419:la_oenb[46] 0
-10 *419:la_data_in[41] *214:13 0
-11 *419:la_data_in[41] *217:13 0.00167858
-12 *419:la_data_in[41] *219:13 0.000184127
-13 *150:16 *419:la_data_in[60] 0
-14 *150:16 *419:la_data_in[62] 0.000154129
-15 *150:16 *419:la_oenb[44] 0
-16 *150:16 *419:la_oenb[54] 0
-17 *150:16 *419:la_oenb[55] 0
-18 *150:16 *166:16 0.190674
-19 *150:16 *283:22 0
-20 *419:la_data_in[38] *419:la_data_in[41] 0.000879442
-21 *61:13 *150:13 0
-22 *121:8 *150:16 0.00609255
-23 *142:22 *419:la_data_in[41] 0.000419633
-24 *144:16 *419:la_data_in[41] 0.00269402
-*RES
-1 la_data_in[41] *150:11 1.755
-2 *150:11 *150:13 263.25
-3 *150:13 *150:15 4.5
-4 *150:15 *150:16 302.49
-5 *150:16 *419:la_data_in[41] 35.685
-*END
-
-*D_NET *151 0.369108
-*CONN
-*P la_data_in[42] I
-*I *419:la_data_in[42] I *D user_proj_example
-*CAP
-1 la_data_in[42] 0.000271935
-2 *419:la_data_in[42] 0.0013428
-3 *151:16 0.018228
-4 *151:15 0.0168852
-5 *151:13 0.0253087
-6 *151:11 0.0255806
-7 *419:la_data_in[42] *419:la_oenb[41] 0.00254709
-8 *419:la_data_in[42] *214:13 0.000944292
-9 *419:la_data_in[42] *279:11 0.00035291
-10 *151:13 *278:11 1.87963e-05
-11 *151:16 *152:16 0.220876
-12 *151:16 *249:16 0.056752
-*RES
-1 la_data_in[42] *151:11 2.835
-2 *151:11 *151:13 249.75
-3 *151:13 *151:15 4.5
-4 *151:15 *151:16 322.47
-5 *151:16 *419:la_data_in[42] 26.595
-*END
-
-*D_NET *152 0.50875
-*CONN
-*P la_data_in[43] I
-*I *419:la_data_in[43] I *D user_proj_example
-*CAP
-1 la_data_in[43] 8.61527e-05
-2 *419:la_data_in[43] 0.00136369
-3 *152:16 0.00982429
-4 *152:15 0.0084606
-5 *152:13 0.0252686
-6 *152:11 0.0253547
-7 *419:la_data_in[43] *419:la_oenb[42] 0.00254709
-8 *419:la_data_in[43] *215:13 0.000944292
-9 *419:la_data_in[43] *280:19 0.000359048
-10 *152:16 *156:16 0.213666
-11 *151:16 *152:16 0.220876
-*RES
-1 la_data_in[43] *152:11 1.215
-2 *152:11 *152:13 249.57
-3 *152:13 *152:15 4.5
-4 *152:15 *152:16 330.57
-5 *152:16 *419:la_data_in[43] 26.775
-*END
-
-*D_NET *153 0.260268
-*CONN
-*P la_data_in[44] I
-*I *419:la_data_in[44] I *D user_proj_example
-*CAP
-1 la_data_in[44] 0.000203572
-2 *419:la_data_in[44] 0.00105893
-3 *153:16 0.0225276
-4 *153:15 0.0214686
-5 *153:13 0.02578
-6 *153:11 0.0259836
-7 *419:la_data_in[44] *419:la_oenb[43] 0.00254709
-8 *419:la_data_in[44] *216:13 0.000541513
-9 *419:la_data_in[44] *217:13 0
-10 *153:11 *217:17 7.67196e-06
-11 *419:la_data_in[38] *419:la_data_in[44] 0.000187196
-12 *140:16 *153:16 0.15561
-13 *142:16 *153:16 0.00435188
-*RES
-1 la_data_in[44] *153:11 2.295
-2 *153:11 *153:13 254.61
-3 *153:13 *153:15 4.5
-4 *153:15 *153:16 335.97
-5 *153:16 *419:la_data_in[44] 21.735
-*END
-
-*D_NET *154 0.45144
-*CONN
-*P la_data_in[45] I
-*I *419:la_data_in[45] I *D user_proj_example
-*CAP
-1 la_data_in[45] 0.000699672
-2 *419:la_data_in[45] 0.000216663
-3 *154:14 0.0112337
-4 *154:13 0.011017
-5 *154:11 0.0265972
-6 *154:10 0.0272968
-7 *419:la_data_in[45] *419:la_oenb[44] 0.000224405
-8 *419:la_data_in[45] *218:9 0
-9 *154:10 *295:8 0.00105689
-10 *154:14 *168:16 0.212061
-11 *154:14 *193:12 0.00121229
-12 *154:14 *205:8 0.159824
-13 *154:14 *299:14 0
-*RES
-1 la_data_in[45] *154:10 16.515
-2 *154:10 *154:11 262.35
-3 *154:11 *154:13 4.5
-4 *154:13 *154:14 342.09
-5 *154:14 *419:la_data_in[45] 7.425
-*END
-
-*D_NET *155 0.388258
-*CONN
-*P la_data_in[46] I
-*I *419:la_data_in[46] I *D user_proj_example
-*CAP
-1 la_data_in[46] 0.00014763
-2 *419:la_data_in[46] 0.000943412
-3 *155:19 0.00474454
-4 *155:18 0.00380113
-5 *155:16 0.0305328
-6 *155:15 0.0305328
-7 *155:13 0.00553659
-8 *155:11 0.00568422
-9 *419:la_data_in[46] *419:la_oenb[45] 0.00254709
-10 *419:la_data_in[46] *218:9 4.47532e-06
-11 *419:la_data_in[46] *219:13 0
-12 *155:16 *248:16 0.0428347
-13 *155:19 *218:9 0.00201389
-14 *155:19 *218:11 0.115141
-15 *155:19 *282:11 0.143681
-16 *419:la_data_in[41] *419:la_data_in[46] 0.000113545
-*RES
-1 la_data_in[46] *155:11 1.755
-2 *155:11 *155:13 49.41
-3 *155:13 *155:15 4.5
-4 *155:15 *155:16 350.91
-5 *155:16 *155:18 4.5
-6 *155:18 *155:19 210.69
-7 *155:19 *419:la_data_in[46] 22.678
-*END
-
-*D_NET *156 0.516736
-*CONN
-*P la_data_in[47] I
-*I *419:la_data_in[47] I *D user_proj_example
-*CAP
-1 la_data_in[47] 0.000271935
-2 *419:la_data_in[47] 0.00193191
-3 *156:16 0.0116408
-4 *156:15 0.00970887
-5 *156:13 0.0252089
-6 *156:11 0.0254808
-7 *419:la_data_in[47] *419:la_data_in[51] 0.00192208
-8 *419:la_data_in[47] *419:la_oenb[46] 0.00111499
-9 *419:la_data_in[47] *419:la_oenb[49] 0.00064242
-10 *419:la_data_in[47] *419:la_oenb[50] 2.07232e-05
-11 *419:la_data_in[47] *219:13 0.000994715
-12 *419:la_data_in[47] *220:13 0
-13 *419:la_data_in[47] *224:9 0
-14 *419:la_data_in[47] *289:11 0
-15 *156:13 *283:11 1.87963e-05
-16 *156:16 *169:16 0.222745
-17 *144:16 *419:la_data_in[47] 0.00136773
-18 *152:16 *156:16 0.213666
-*RES
-1 la_data_in[47] *156:11 2.835
-2 *156:11 *156:13 249.39
-3 *156:13 *156:15 4.5
-4 *156:15 *156:16 344.43
-5 *156:16 *419:la_data_in[47] 45.405
-*END
-
-*D_NET *157 0.471186
-*CONN
-*P la_data_in[48] I
-*I *419:la_data_in[48] I *D user_proj_example
-*CAP
-1 la_data_in[48] 8.61527e-05
-2 *419:la_data_in[48] 0.00199631
-3 *157:16 0.0123293
-4 *157:15 0.010333
-5 *157:13 0.0249329
-6 *157:11 0.0250191
-7 *419:la_data_in[48] *419:la_oenb[47] 0.00144233
-8 *419:la_data_in[48] *220:13 4.02619e-05
-9 *419:la_data_in[48] *221:17 0.000240133
-10 *419:la_data_in[48] *285:19 0.000610688
-11 *157:13 *221:21 0
-12 *157:16 *162:16 0.24327
-13 *157:16 *204:10 0.150886
-*RES
-1 la_data_in[48] *157:11 1.215
-2 *157:11 *157:13 246.87
-3 *157:13 *157:15 4.5
-4 *157:15 *157:16 362.97
-5 *157:16 *419:la_data_in[48] 29.475
-*END
-
-*D_NET *158 0.422867
-*CONN
-*P la_data_in[49] I
-*I *419:la_data_in[49] I *D user_proj_example
-*CAP
-1 la_data_in[49] 0.000674064
-2 *419:la_data_in[49] 0.000830822
-3 *158:18 0.00804994
-4 *158:17 0.00721912
-5 *158:15 0.0228851
-6 *158:13 0.0250848
-7 *158:8 0.00731563
-8 *158:7 0.00579003
-9 *419:la_data_in[49] *419:la_oenb[48] 0.000571781
-10 *419:la_data_in[49] *221:17 0.000552382
-11 *419:la_data_in[49] *222:11 0
-12 *419:la_data_in[49] *283:22 0.00497143
-13 *158:7 *222:15 0.000234762
-14 *158:8 la_data_out[48] 0.000708712
-15 *158:8 *275:8 0.00615481
-16 *158:8 *289:8 0.0197283
-17 *158:13 *274:7 2.04586e-05
-18 *158:18 *297:16 0.170159
-19 *139:16 *158:18 0.141063
-20 *147:13 *158:13 0.000853122
-21 *147:13 *158:15 0
-*RES
-1 la_data_in[49] *158:7 11.385
-2 *158:7 *158:8 94.59
-3 *158:8 *158:13 29.97
-4 *158:13 *158:15 225.72
-5 *158:15 *158:17 4.5
-6 *158:17 *158:18 275.67
-7 *158:18 *419:la_data_in[49] 19.575
-*END
-
-*D_NET *159 0.245762
-*CONN
-*P la_data_in[4] I
-*I *419:la_data_in[4] I *D user_proj_example
-*CAP
-1 la_data_in[4] 0.000374224
-2 *419:la_data_in[4] 0.00127671
-3 *159:11 0.0160589
-4 *159:10 0.0147822
-5 *159:8 0.00512859
-6 *159:7 0.00550282
-7 *419:la_data_in[4] *419:la_oenb[3] 0.00131958
-8 *419:la_data_in[4] *170:11 3.06879e-06
-9 *419:la_data_in[4] *212:7 0
-10 *419:la_data_in[4] *223:17 0
-11 *159:7 la_data_out[4] 0.000136561
-12 *159:11 *212:7 0.00460318
-13 *159:11 *212:9 0.153808
-14 *159:11 *368:20 0.000552382
-15 *419:la_data_in[3] *159:11 3.06879e-06
-16 *117:8 *159:8 0.042213
-17 *137:19 *159:11 0
-*RES
-1 la_data_in[4] *159:7 8.505
-2 *159:7 *159:8 80.01
-3 *159:8 *159:10 4.5
-4 *159:10 *159:11 256.05
-5 *159:11 *419:la_data_in[4] 22.545
-*END
-
-*D_NET *160 0.578794
-*CONN
-*P la_data_in[50] I
-*I *419:la_data_in[50] I *D user_proj_example
-*CAP
-1 la_data_in[50] 0.000699672
-2 *419:la_data_in[50] 0.00198998
-3 *160:14 0.00621877
-4 *160:13 0.00422879
-5 *160:11 0.0240238
-6 *160:10 0.0247234
-7 *419:la_data_in[50] *419:la_oenb[49] 0.00119683
-8 *419:la_data_in[50] *222:11 0.00456227
-9 *419:la_data_in[50] *224:9 0.000242434
-10 *419:la_data_in[50] *281:21 0.000184127
-11 *419:la_data_in[50] *283:22 0
-12 *160:10 *295:8 0.00105689
-13 *160:14 *161:16 0.258191
-14 *160:14 *172:14 0.00435188
-15 *160:14 *221:18 0.247124
-*RES
-1 la_data_in[50] *160:10 16.515
-2 *160:10 *160:11 238.23
-3 *160:11 *160:13 4.5
-4 *160:13 *160:14 376.65
-5 *160:14 *419:la_data_in[50] 43.3272
-*END
-
-*D_NET *161 0.589119
-*CONN
-*P la_data_in[51] I
-*I *419:la_data_in[51] I *D user_proj_example
-*CAP
-1 la_data_in[51] 0.00014502
-2 *419:la_data_in[51] 0.00177186
-3 *161:16 0.00686936
-4 *161:15 0.0050975
-5 *161:13 0.024588
-6 *161:11 0.024733
-7 *419:la_data_in[51] *419:la_oenb[50] 0.00103316
-8 *419:la_data_in[51] *224:9 0.010618
-9 *419:la_data_in[51] *289:11 0.000187196
-10 *161:16 *167:16 0.25359
-11 *161:16 *172:14 0.000373018
-12 *419:la_data_in[47] *419:la_data_in[51] 0.00192208
-13 *160:14 *161:16 0.258191
-*RES
-1 la_data_in[51] *161:11 1.755
-2 *161:11 *161:13 243.99
-3 *161:13 *161:15 4.5
-4 *161:15 *161:16 383.31
-5 *161:16 *419:la_data_in[51] 43.288
-*END
-
-*D_NET *162 0.563232
-*CONN
-*P la_data_in[52] I
-*I *419:la_data_in[52] I *D user_proj_example
-*CAP
-1 la_data_in[52] 0.000271935
-2 *419:la_data_in[52] 0.00202838
-3 *162:16 0.00871635
-4 *162:15 0.00668797
-5 *162:13 0.0246523
-6 *162:11 0.0249243
-7 *419:la_data_in[52] *419:la_oenb[51] 0.00144233
-8 *419:la_data_in[52] *225:11 4.02779e-05
-9 *419:la_data_in[52] *226:7 0.000837779
-10 *162:13 *289:7 0.000500596
-11 *162:16 *173:16 0.24986
-12 *162:16 *253:16 0
-13 *157:16 *162:16 0.24327
-*RES
-1 la_data_in[52] *162:11 2.835
-2 *162:11 *162:13 246.69
-3 *162:13 *162:15 4.5
-4 *162:15 *162:16 387.27
-5 *162:16 *419:la_data_in[52] 29.655
-*END
-
-*D_NET *163 0.527703
-*CONN
-*P la_data_in[53] I
-*I *419:la_data_in[53] I *D user_proj_example
-*CAP
-1 la_data_in[53] 8.61527e-05
-2 *419:la_data_in[53] 0.00171198
-3 *163:16 0.0115489
-4 *163:15 0.00983687
-5 *163:13 0.0253918
-6 *163:11 0.0254779
-7 *419:la_data_in[53] *419:la_data_in[54] 0.000395873
-8 *419:la_data_in[53] *419:la_oenb[52] 0.00115591
-9 *419:la_data_in[53] *226:7 0
-10 *419:la_data_in[53] *227:5 0
-11 *163:16 *171:8 0.261051
-12 *149:8 *163:16 0.191047
-*RES
-1 la_data_in[53] *163:11 1.215
-2 *163:11 *163:13 252.09
-3 *163:13 *163:15 4.5
-4 *163:15 *163:16 395.37
-5 *163:16 *419:la_data_in[53] 24.255
-*END
-
-*D_NET *164 0.266836
-*CONN
-*P la_data_in[54] I
-*I *419:la_data_in[54] I *D user_proj_example
-*CAP
-1 la_data_in[54] 0.000203572
-2 *419:la_data_in[54] 0.00210117
-3 *164:16 0.0307942
-4 *164:15 0.0286931
-5 *164:13 0.02426
-6 *164:11 0.0244636
-7 *419:la_data_in[54] *419:la_oenb[53] 0.00107408
-8 *419:la_data_in[54] *227:5 0.00513511
-9 *419:la_data_in[54] *228:15 0
-10 *419:la_data_in[54] *288:25 0.000392805
-11 *419:la_data_in[54] *292:11 4.60318e-05
-12 *164:11 *228:19 7.67196e-06
-13 *164:16 *269:16 0.149269
-14 *419:la_data_in[53] *419:la_data_in[54] 0.000395873
-*RES
-1 la_data_in[54] *164:11 2.295
-2 *164:11 *164:13 241.11
-3 *164:13 *164:15 4.5
-4 *164:15 *164:16 402.39
-5 *164:16 *419:la_data_in[54] 46.3872
-*END
-
-*D_NET *165 0.26853
-*CONN
-*P la_data_in[55] I
-*I *419:la_data_in[55] I *D user_proj_example
-*CAP
-1 la_data_in[55] 0.0058005
-2 *419:la_data_in[55] 0.00090884
-3 *165:11 0.0114522
-4 *165:10 0.0105433
-5 *165:8 0.0387114
-6 *165:7 0.0387114
-7 *165:5 0.0058005
-8 *419:la_data_in[55] *419:la_oenb[54] 0.00144233
-9 *419:la_data_in[55] *219:13 0.000465433
-10 *419:la_data_in[55] *228:15 0
-11 *419:la_data_in[55] *229:9 0.000395873
-12 *165:5 *229:13 0
-13 *165:11 *228:15 0.0163873
-14 *165:11 *292:11 0.137911
-15 *31:13 *165:8 0
-*RES
-1 la_data_in[55] *165:5 57.465
-2 *165:5 *165:7 4.5
-3 *165:7 *165:8 410.31
-4 *165:8 *165:10 4.5
-5 *165:10 *165:11 202.23
-6 *165:11 *419:la_data_in[55] 23.038
-*END
-
-*D_NET *166 0.547779
-*CONN
-*P la_data_in[56] I
-*I *419:la_data_in[56] I *D user_proj_example
-*CAP
-1 la_data_in[56] 0.00014502
-2 *419:la_data_in[56] 0.000295836
-3 *166:16 0.0102094
-4 *166:15 0.0099136
-5 *166:13 0.0264588
-6 *166:11 0.0266038
-7 *419:la_data_in[56] *419:la_oenb[55] 0.000452263
-8 *419:la_data_in[56] *230:7 0.0011109
-9 *166:16 *238:14 0.00209305
-10 *166:16 *301:12 0.252969
-11 *121:8 *166:16 0.0265462
-12 *133:24 *419:la_data_in[56] 0.000306879
-13 *150:16 *166:16 0.190674
-*RES
-1 la_data_in[56] *166:11 1.755
-2 *166:11 *166:13 263.07
-3 *166:13 *166:15 4.5
-4 *166:15 *166:16 413.73
-5 *166:16 *419:la_data_in[56] 12.645
-*END
-
-*D_NET *167 0.37115
-*CONN
-*P la_data_in[57] I
-*I *419:la_data_in[57] I *D user_proj_example
-*CAP
-1 la_data_in[57] 0.000271935
-2 *419:la_data_in[57] 0.00169014
-3 *167:16 0.0257569
-4 *167:15 0.0240668
-5 *167:13 0.0244921
-6 *167:11 0.024764
-7 *419:la_data_in[57] *419:la_oenb[56] 0.00123774
-8 *419:la_data_in[57] *230:7 0.014546
-9 *419:la_data_in[57] *231:15 0
-10 *419:la_data_in[57] *293:19 0.000715027
-11 *167:13 *294:11 1.87963e-05
-12 *161:16 *167:16 0.25359
-*RES
-1 la_data_in[57] *167:11 2.835
-2 *167:11 *167:13 243.81
-3 *167:13 *167:15 4.5
-4 *167:15 *167:16 421.11
-5 *167:16 *419:la_data_in[57] 34.155
-*END
-
-*D_NET *168 0.322639
-*CONN
-*P la_data_in[58] I
-*I *419:la_data_in[58] I *D user_proj_example
-*CAP
-1 la_data_in[58] 8.61527e-05
-2 *419:la_data_in[58] 0.000215942
-3 *168:16 0.0206826
-4 *168:15 0.0204666
-5 *168:13 0.0269516
-6 *168:11 0.0270378
-7 *419:la_data_in[58] *419:la_oenb[57] 0
-8 *419:la_data_in[58] *232:7 0.000423492
-9 *168:16 *193:12 0.00781239
-10 *168:16 *217:14 0.00690085
-11 *168:16 *299:14 0
-12 *33:9 *168:16 0
-13 *154:14 *168:16 0.212061
-*RES
-1 la_data_in[58] *168:11 1.215
-2 *168:11 *168:13 268.11
-3 *168:13 *168:15 4.5
-4 *168:15 *168:16 427.23
-5 *168:16 *419:la_data_in[58] 7.605
-*END
-
-*D_NET *169 0.341336
-*CONN
-*P la_data_in[59] I
-*I *419:la_data_in[59] I *D user_proj_example
-*CAP
-1 la_data_in[59] 0.000203572
-2 *419:la_data_in[59] 0.00186839
-3 *169:16 0.0330558
-4 *169:15 0.0311874
-5 *169:13 0.0250169
-6 *169:11 0.0252205
-7 *419:la_data_in[59] *419:la_oenb[58] 0.00127866
-8 *419:la_data_in[59] *232:7 0
-9 *419:la_data_in[59] *233:7 0.000751853
-10 *169:11 *233:13 7.67196e-06
-11 *169:16 *186:8 0
-12 *156:16 *169:16 0.222745
-*RES
-1 la_data_in[59] *169:11 2.295
-2 *169:11 *169:13 249.21
-3 *169:13 *169:15 4.5
-4 *169:15 *169:16 433.17
-5 *169:16 *419:la_data_in[59] 27.135
-*END
-
-*D_NET *170 0.245124
-*CONN
-*P la_data_in[5] I
-*I *419:la_data_in[5] I *D user_proj_example
-*CAP
-1 la_data_in[5] 0.00125187
-2 *419:la_data_in[5] 0.000971078
-3 *170:11 0.015009
-4 *170:10 0.0140379
-5 *170:8 0.00488913
-6 *170:7 0.006141
-7 *419:la_data_in[5] *419:la_oenb[4] 0.00111883
-8 *419:la_data_in[5] *234:11 0
-9 *419:la_data_in[5] *298:11 8.28572e-05
-10 *170:8 *187:16 0.0353744
-11 *170:11 wbs_dat_o[27] 0.00084136
-12 *170:11 *419:la_oenb[4] 0.000400477
-13 *170:11 *287:19 0.160129
-14 *419:la_data_in[4] *170:11 3.06879e-06
-15 *126:8 *170:8 0.0048741
-*RES
-1 la_data_in[5] *170:7 16.065
-2 *170:7 *170:8 86.49
-3 *170:8 *170:10 4.5
-4 *170:10 *170:11 248.49
-5 *170:11 *419:la_data_in[5] 22.545
-*END
-
-*D_NET *171 0.375561
-*CONN
-*P la_data_in[60] I
-*I *419:la_data_in[60] I *D user_proj_example
-*CAP
-1 la_data_in[60] 0.0252958
-2 *419:la_data_in[60] 0.00109448
-3 *171:8 0.0265568
-4 *171:7 0.0254623
-5 *171:5 0.0252958
-6 *419:la_data_in[60] *419:la_oenb[59] 0.00153363
-7 *419:la_data_in[60] *233:7 0.00889948
-8 *419:la_data_in[60] *235:9 0.000217884
-9 *419:la_data_in[60] *296:16 0.000154129
-10 *171:5 *299:11 0
-11 *150:16 *419:la_data_in[60] 0
-12 *163:16 *171:8 0.261051
-*RES
-1 la_data_in[60] *171:5 251.865
-2 *171:5 *171:7 4.5
-3 *171:7 *171:8 442.71
-4 *171:8 *419:la_data_in[60] 35.055
-*END
-
-*D_NET *172 0.448373
-*CONN
-*P la_data_in[61] I
-*I *419:la_data_in[61] I *D user_proj_example
-*CAP
-1 la_data_in[61] 0.000753499
-2 *419:la_data_in[61] 0.00175155
-3 *172:14 0.0148771
-4 *172:13 0.0131255
-5 *172:11 0.0239735
-6 *172:10 0.0239735
-7 *172:8 0.00601946
-8 *172:7 0.00677296
-9 *419:la_data_in[61] *419:la_oenb[60] 0.000378484
-10 *419:la_data_in[61] *235:9 0.0149143
-11 *419:la_data_in[61] *236:11 0
-12 *419:la_data_in[61] *286:19 0.00073344
-13 *172:7 *236:19 0
-14 *172:8 la_data_out[55] 0.00317055
-15 *172:8 la_data_out[58] 0.00242462
-16 *172:8 user_irq[0] 0.000360562
-17 *172:8 *289:8 0.00976066
-18 *172:8 *292:8 0.00634127
-19 *172:8 *295:8 0.00319545
-20 *172:8 *299:10 0.000770645
-21 *172:11 la_data_out[50] 0
-22 *172:11 *224:13 0
-23 *172:14 *196:12 0.083867
-24 *172:14 *221:18 0.226484
-25 *160:14 *172:14 0.00435188
-26 *161:16 *172:14 0.000373018
-*RES
-1 la_data_in[61] *172:7 11.205
-2 *172:7 *172:8 99.81
-3 *172:8 *172:10 4.5
-4 *172:10 *172:11 237.87
-5 *172:11 *172:13 4.5
-6 *172:13 *172:14 349.47
-7 *172:14 *419:la_data_in[61] 33.435
-*END
-
-*D_NET *173 0.381441
-*CONN
-*P la_data_in[62] I
-*I *419:la_data_in[62] I *D user_proj_example
-*CAP
-1 la_data_in[62] 0.000271935
-2 *419:la_data_in[62] 0.000957605
-3 *173:16 0.0282017
-4 *173:15 0.0272441
-5 *173:13 0.0245473
-6 *173:11 0.0248192
-7 *419:la_data_in[62] *419:la_oenb[61] 0.000698442
-8 *419:la_data_in[62] *236:11 0
-9 *419:la_data_in[62] *236:13 0.0119683
-10 *419:la_data_in[62] *237:7 0.000248572
-11 *419:la_data_in[62] *296:16 0
-12 *419:la_data_in[62] *300:17 0.0119683
-13 *173:13 *300:13 0.000500596
-14 *173:16 *196:12 0
-15 *173:16 *253:16 0
-16 *150:16 *419:la_data_in[62] 0.000154129
-17 *162:16 *173:16 0.24986
-*RES
-1 la_data_in[62] *173:11 2.835
-2 *173:11 *173:13 246.51
-3 *173:13 *173:15 4.5
-4 *173:15 *173:16 453.51
-5 *173:16 *419:la_data_in[62] 40.455
-*END
-
-*D_NET *174 0.325687
-*CONN
-*P la_data_in[63] I
-*I *419:la_data_in[63] I *D user_proj_example
-*CAP
-1 la_data_in[63] 8.61527e-05
-2 *419:la_data_in[63] 0.000819548
-3 *174:16 0.0306359
-4 *174:15 0.0298163
-5 *174:13 0.0260563
-6 *174:11 0.0261425
-7 *419:la_data_in[63] *419:la_oenb[62] 0.00037631
-8 *419:la_data_in[63] *419:la_oenb[63] 0
-9 *419:la_data_in[63] *238:13 0.000348691
-10 *419:la_data_in[63] *291:23 0.000214815
-11 *174:16 *219:14 0.211191
-*RES
-1 la_data_in[63] *174:11 1.215
-2 *174:11 *174:13 260.01
-3 *174:13 *174:15 4.5
-4 *174:15 *174:16 459.63
-5 *174:16 *419:la_data_in[63] 15.705
-*END
-
-*D_NET *175 0.213859
-*CONN
-*P la_data_in[6] I
-*I *419:la_data_in[6] I *D user_proj_example
-*CAP
-1 la_data_in[6] 0.000125413
-2 *419:la_data_in[6] 0.00269857
-3 *175:19 0.0111893
-4 *175:18 0.00849073
-5 *175:16 0.00927325
-6 *175:15 0.00927325
-7 *175:13 0.00547588
-8 *175:11 0.0056013
-9 *419:la_data_in[6] *419:la_oenb[5] 0.00201517
-10 *419:la_data_in[6] *234:9 4.47532e-06
-11 *419:la_data_in[6] *234:11 0
-12 *419:la_data_in[6] *239:11 0
-13 *419:la_data_in[6] *239:13 0
-14 *419:la_data_in[6] *303:11 0.000687408
-15 *175:13 *275:11 0.0549313
-16 *175:19 *234:11 0.104093
-*RES
-1 la_data_in[6] *175:11 1.575
-2 *175:11 *175:13 87.21
-3 *175:13 *175:15 4.5
-4 *175:15 *175:16 91.71
-5 *175:16 *175:18 4.5
-6 *175:18 *175:19 152.64
-7 *175:19 *419:la_data_in[6] 33.435
-*END
-
-*D_NET *176 0.384917
-*CONN
-*P la_data_in[7] I
-*I *419:la_data_in[7] I *D user_proj_example
-*CAP
-1 la_data_in[7] 0.00186401
-2 *419:la_data_in[7] 0.000929509
-3 *176:11 0.00573594
-4 *176:10 0.00480643
-5 *176:8 0.00542807
-6 *176:7 0.00729208
-7 *419:la_data_in[7] *419:la_oenb[6] 0.00129412
-8 *419:la_data_in[7] *239:13 0
-9 *419:la_data_in[7] *240:5 0
-10 *419:la_data_in[7] *401:11 0.000211746
-11 *176:8 *177:8 0.0052429
-12 *176:8 *190:10 0.0326389
-13 *176:8 *268:8 0.0202052
-14 *176:11 *239:13 0.134106
-15 *176:11 *303:11 0.165162
-*RES
-1 la_data_in[7] *176:7 21.825
-2 *176:7 *176:8 99.27
-3 *176:8 *176:10 4.5
-4 *176:10 *176:11 242.19
-5 *176:11 *419:la_data_in[7] 23.218
-*END
-
-*D_NET *177 0.416254
-*CONN
-*P la_data_in[8] I
-*I *419:la_data_in[8] I *D user_proj_example
-*CAP
-1 la_data_in[8] 0.00195844
-2 *419:la_data_in[8] 0.000803717
-3 *177:11 0.00412007
-4 *177:10 0.00331635
-5 *177:8 0.00578674
-6 *177:7 0.00774518
-7 *419:la_data_in[8] *419:la_oenb[7] 0.00119683
-8 *419:la_data_in[8] *240:5 0
-9 *419:la_data_in[8] *305:11 8.28572e-05
-10 *419:la_data_in[8] *372:19 0.00105689
-11 *177:8 *190:10 0.0307738
-12 *177:8 *268:8 0.0265464
-13 *177:11 *240:5 0.160129
-14 *177:11 *401:11 0.167494
-15 *176:8 *177:8 0.0052429
-*RES
-1 la_data_in[8] *177:7 21.465
-2 *177:7 *177:8 105.75
-3 *177:8 *177:10 4.5
-4 *177:10 *177:11 245.61
-5 *177:11 *419:la_data_in[8] 19.845
-*END
-
-*D_NET *178 0.106189
-*CONN
-*P la_data_in[9] I
-*I *419:la_data_in[9] I *D user_proj_example
-*CAP
-1 la_data_in[9] 0.000203572
-2 *419:la_data_in[9] 0.00253293
-3 *178:16 0.0108678
-4 *178:15 0.00833492
-5 *178:13 0.0242469
-6 *178:11 0.0244505
-7 *419:la_data_in[9] *419:la_oenb[8] 0.00144233
-8 *419:la_data_in[9] *241:9 7.60804e-05
-9 *419:la_data_in[9] *241:11 0
-10 *419:la_data_in[9] *242:11 0
-11 *419:la_data_in[9] *242:13 0
-12 *419:la_data_in[9] *306:11 0.000604551
-13 *178:11 la_data_out[9] 7.67196e-06
-14 *178:13 *222:11 0.00497143
-15 *178:13 *283:22 0
-16 *178:13 *305:7 0
-17 *178:16 *194:16 0.000834078
-18 *178:16 *197:20 0.00144234
-19 *178:16 *202:16 0.00460055
-20 *178:16 *269:16 0.0215729
-*RES
-1 la_data_in[9] *178:11 2.295
-2 *178:11 *178:13 241.11
-3 *178:13 *178:15 4.5
-4 *178:15 *178:16 109.17
-5 *178:16 *419:la_data_in[9] 35.235
-*END
-
-*D_NET *179 0.187865
-*CONN
-*P la_data_out[0] O
-*I *419:la_data_out[0] O *D user_proj_example
-*CAP
-1 la_data_out[0] 0.00485609
-2 *419:la_data_out[0] 0.00185789
-3 *179:26 0.00485609
-4 *179:24 0.00566591
-5 *179:23 0.00566591
-6 *179:21 0.00386174
-7 *179:19 0.00389057
-8 *179:17 0.00188673
-9 la_data_out[0] *191:13 0.00491006
-10 la_data_out[0] *255:11 0.00336339
-11 *179:17 *419:la_oenb[0] 0.00231387
-12 *179:17 *243:19 0.00337567
-13 *179:17 *335:11 0.000268519
-14 *179:17 *372:19 0.000384877
-15 *179:21 *243:19 0.1133
-16 *179:21 *335:11 0.0127393
-17 *419:la_data_in[0] *179:17 0
-18 *128:19 la_data_out[0] 0.0146688
-*RES
-1 *419:la_data_out[0] *179:17 49.995
-2 *179:17 *179:19 0.27
-3 *179:19 *179:21 166.14
-4 *179:21 *179:23 4.5
-5 *179:23 *179:24 54.27
-6 *179:24 *179:26 4.5
-7 *179:26 la_data_out[0] 73.665
-*END
-
-*D_NET *180 0.421484
-*CONN
-*P la_data_out[10] O
-*I *419:la_data_out[10] O *D user_proj_example
-*CAP
-1 la_data_out[10] 0.00191518
-2 *419:la_data_out[10] 0.000209676
-3 *180:12 0.00846022
-4 *180:11 0.00654504
-5 *180:9 0.00301878
-6 *180:7 0.00322845
-7 la_data_out[10] *292:11 0.00435768
-8 *180:7 *419:la_oenb[10] 0.00144233
-9 *180:9 *419:la_oenb[10] 0.00341249
-10 *180:9 *244:19 0.135149
-11 *180:9 *265:11 0
-12 *180:9 *370:11 0.0108635
-13 *180:12 *181:10 0.0805093
-14 *419:la_data_in[10] *180:7 0.000479882
-15 *419:la_data_in[10] *180:9 4.47532e-05
-16 *117:11 *180:9 0.161848
-*RES
-1 *419:la_data_out[10] *180:7 6.615
-2 *180:7 *180:9 239.49
-3 *180:9 *180:11 4.5
-4 *180:11 *180:12 119.07
-5 *180:12 la_data_out[10] 29.925
-*END
-
-*D_NET *181 0.29831
-*CONN
-*P la_data_out[11] O
-*I *419:la_data_out[11] O *D user_proj_example
-*CAP
-1 la_data_out[11] 0.00220613
-2 *419:la_data_out[11] 4.01718e-05
-3 *181:10 0.00814167
-4 *181:9 0.00593554
-5 *181:7 0.0145605
-6 *181:5 0.0146007
-7 la_data_out[11] *295:11 0.013073
-8 *181:7 *419:la_oenb[11] 0.00312377
-9 *181:7 *245:19 0.136991
-10 *181:10 *284:8 0.0188371
-11 *419:la_data_in[11] *181:7 0.000291535
-12 *117:7 la_data_out[11] 0
-13 *180:12 *181:10 0.0805093
-*RES
-1 *419:la_data_out[11] *181:5 0.405
-2 *181:5 *181:7 245.97
-3 *181:7 *181:9 4.5
-4 *181:9 *181:10 124.47
-5 *181:10 la_data_out[11] 31.725
-*END
-
-*D_NET *182 0.280076
-*CONN
-*P la_data_out[12] O
-*I *419:la_data_out[12] O *D user_proj_example
-*CAP
-1 la_data_out[12] 0.013198
-2 *419:la_data_out[12] 0.00163308
-3 *182:16 0.013198
-4 *182:14 0.00606044
-5 *182:13 0.00606044
-6 *182:11 0.0029882
-7 *182:10 0.00462128
-8 la_data_out[12] *236:13 0.00190265
-9 la_data_out[12] *300:17 0.138157
-10 *182:10 *419:la_oenb[12] 0.00039012
-11 *182:10 *419:la_oenb[7] 0.0100093
-12 *182:10 *246:16 0.00186509
-13 *182:11 *192:7 0
-14 *182:11 *192:9 0
-15 *182:14 *227:8 0.0017822
-16 *182:14 *230:10 0.00951176
-17 *419:la_data_in[12] *182:10 0.00039012
-18 *419:la_data_in[21] *182:11 0.00601483
-19 *116:8 *182:14 0.0607397
-20 *128:19 *182:11 0.00155357
-21 *129:19 *182:11 0
-*RES
-1 *419:la_data_out[12] *182:10 36.675
-2 *182:10 *182:11 46.71
-3 *182:11 *182:13 4.5
-4 *182:13 *182:14 109.71
-5 *182:14 *182:16 4.5
-6 *182:16 la_data_out[12] 219.465
-*END
-
-*D_NET *183 0.417501
-*CONN
-*P la_data_out[13] O
-*I *419:la_data_out[13] O *D user_proj_example
-*CAP
-1 la_data_out[13] 0.00338483
-2 *419:la_data_out[13] 0.0034092
-3 *183:8 0.0116021
-4 *183:7 0.00821729
-5 *183:5 0.0034092
-6 *183:5 *419:la_oenb[13] 0.00712982
-7 *183:5 *247:19 0.140673
-8 *183:5 *372:13 0.000245503
-9 *183:8 *191:16 0.0820013
-10 *419:la_data_in[13] *183:5 0
-11 *116:11 *183:5 0
-12 *120:19 *183:5 0.157429
-*RES
-1 *419:la_data_out[13] *183:5 240.345
-2 *183:5 *183:7 4.5
-3 *183:7 *183:8 137.43
-4 *183:8 la_data_out[13] 36.945
-*END
-
-*D_NET *184 0.191568
-*CONN
-*P la_data_out[14] O
-*I *419:la_data_out[14] O *D user_proj_example
-*CAP
-1 la_data_out[14] 0.00265038
-2 *419:la_data_out[14] 4.34776e-05
-3 *184:10 0.00856979
-4 *184:9 0.00591941
-5 *184:7 0.0248621
-6 *184:5 0.0249056
-7 la_data_out[14] *248:13 2.5829e-05
-8 *184:7 *419:la_oenb[14] 0
-9 *184:10 *223:24 0.0354987
-10 *184:10 *234:14 0.00184437
-11 *184:10 *272:16 0.0578795
-12 *184:10 *276:18 0.0290331
-13 *419:la_data_in[14] *184:7 0.00032836
-14 *118:19 *184:7 0
-15 *120:15 la_data_out[14] 7.67196e-06
-*RES
-1 *419:la_data_out[14] *184:5 0.405
-2 *184:5 *184:7 248.49
-3 *184:7 *184:9 4.5
-4 *184:9 *184:10 143.19
-5 *184:10 la_data_out[14] 29.925
-*END
-
-*D_NET *185 0.299586
-*CONN
-*P la_data_out[15] O
-*I *419:la_data_out[15] O *D user_proj_example
-*CAP
-1 la_data_out[15] 0.00446336
-2 *419:la_data_out[15] 0.000230323
-3 *185:12 0.0133098
-4 *185:11 0.00884645
-5 *185:9 0.00857424
-6 *185:7 0.00880456
-7 la_data_out[15] *290:11 0.000510953
-8 *185:7 *419:la_oenb[15] 0.00144233
-9 *185:9 *419:la_oenb[15] 0.00203767
-10 *185:9 *276:19 0.00701524
-11 *419:la_data_in[15] *185:7 0.000479882
-12 *122:19 *185:9 0.150555
-13 *129:16 *185:12 0.0933163
-*RES
-1 *419:la_data_out[15] *185:7 6.615
-2 *185:7 *185:9 220.77
-3 *185:9 *185:11 4.5
-4 *185:11 *185:12 151.11
-5 *185:12 la_data_out[15] 49.185
-*END
-
-*D_NET *186 0.163872
-*CONN
-*P la_data_out[16] O
-*I *419:la_data_out[16] O *D user_proj_example
-*CAP
-1 la_data_out[16] 0.000187838
-2 *419:la_data_out[16] 0.000947304
-3 *186:11 0.0255468
-4 *186:10 0.0253589
-5 *186:8 0.0107483
-6 *186:7 0.0116956
-7 *186:7 *419:la_oenb[16] 0.0054113
-8 *186:7 *276:19 0
-9 *186:8 *195:14 0.0812554
-10 *419:la_data_in[16] *186:7 0
-11 *123:19 *186:7 0.00272099
-12 *169:16 *186:8 0
-*RES
-1 *419:la_data_out[16] *186:7 28.305
-2 *186:7 *186:8 156.33
-3 *186:8 *186:10 4.5
-4 *186:10 *186:11 247.41
-5 *186:11 la_data_out[16] 2.115
-*END
-
-*D_NET *187 0.493522
-*CONN
-*P la_data_out[17] O
-*I *419:la_data_out[17] O *D user_proj_example
-*CAP
-1 la_data_out[17] 0.00127197
-2 *419:la_data_out[17] 0.000457518
-3 *187:16 0.00759046
-4 *187:15 0.00631849
-5 *187:13 0.00414378
-6 *187:11 0.0046013
-7 *187:11 *419:la_oenb[17] 0.00332452
-8 *187:11 *251:11 4.91006e-05
-9 *187:13 *251:11 0.172527
-10 *187:13 *304:11 0.00100656
-11 *187:16 *279:8 0.0672048
-12 *187:16 *304:8 0.0515384
-13 *419:la_data_in[17] *187:11 0
-14 *419:la_data_in[18] *187:11 0.000122752
-15 *419:la_data_in[18] *187:13 0.00247038
-16 *124:19 *187:13 0.135272
-17 *126:8 *187:16 0.000248679
-18 *170:8 *187:16 0.0353744
-*RES
-1 *419:la_data_out[17] *187:11 7.335
-2 *187:11 *187:13 252.99
-3 *187:13 *187:15 4.5
-4 *187:15 *187:16 164.61
-5 *187:16 la_data_out[17] 16.245
-*END
-
-*D_NET *188 0.223945
-*CONN
-*P la_data_out[18] O
-*I *419:la_data_out[18] O *D user_proj_example
-*CAP
-1 la_data_out[18] 0.000101471
-2 *419:la_data_out[18] 0.000583433
-3 *188:16 0.00950469
-4 *188:15 0.0128749
-5 *188:9 0.017457
-6 *188:7 0.0145687
-7 *188:7 *419:la_oenb[18] 0.00277214
-8 *188:7 *304:11 0
-9 *188:9 *419:la_oenb[18] 0.000184127
-10 *188:9 *252:26 0.0206836
-11 *188:15 wbs_dat_o[31] 0
-12 *419:la_data_in[18] *188:7 0
-13 *115:7 *188:15 0
-14 *125:19 *188:7 0.00300741
-15 *125:19 *188:9 0.0413059
-16 *135:12 *188:16 0.100902
-*RES
-1 *419:la_data_out[18] *188:7 12.555
-2 *188:7 *188:9 227.16
-3 *188:9 *188:15 37.35
-4 *188:15 *188:16 169.83
-5 *188:16 la_data_out[18] 5.625
-*END
-
-*D_NET *189 0.192162
-*CONN
-*P la_data_out[19] O
-*I *419:la_data_out[19] O *D user_proj_example
-*CAP
-1 la_data_out[19] 0.000236116
-2 *419:la_data_out[19] 0.000418152
-3 *189:15 0.0100172
-4 *189:14 0.00978113
-5 *189:12 0.0186371
-6 *189:11 0.0186371
-7 *189:9 0.00896391
-8 *189:7 0.00938206
-9 la_data_out[19] *253:13 2.5829e-05
-10 *189:7 *419:la_oenb[19] 0.00144233
-11 *189:9 *419:la_oenb[19] 0.00272508
-12 *419:la_data_in[19] *189:7 0
-13 *419:la_data_in[19] *189:9 0
-14 *88:12 *189:15 0
-15 *125:13 *189:15 7.67196e-06
-16 *127:11 *189:9 0.111888
-*RES
-1 *419:la_data_out[19] *189:7 6.615
-2 *189:7 *189:9 169.65
-3 *189:9 *189:11 4.5
-4 *189:11 *189:12 175.41
-5 *189:12 *189:14 4.5
-6 *189:14 *189:15 95.31
-7 *189:15 la_data_out[19] 2.655
-*END
-
-*D_NET *190 0.245661
-*CONN
-*P la_data_out[1] O
-*I *419:la_data_out[1] O *D user_proj_example
-*CAP
-1 la_data_out[1] 0.0018237
-2 *419:la_data_out[1] 4.12737e-05
-3 *190:10 0.00386525
-4 *190:9 0.00204154
-5 *190:7 0.0150046
-6 *190:5 0.0150459
-7 la_data_out[1] *254:15 0
-8 la_data_out[1] *258:11 0
-9 *190:7 *419:la_oenb[0] 0
-10 *190:7 *419:la_oenb[1] 0.00312377
-11 *190:7 *254:19 0.140919
-12 *190:7 *335:11 0
-13 *419:la_data_in[1] *190:7 0.000383598
-14 *176:8 *190:10 0.0326389
-15 *177:8 *190:10 0.0307738
-*RES
-1 *419:la_data_out[1] *190:5 0.405
-2 *190:5 *190:7 254.07
-3 *190:7 *190:9 4.5
-4 *190:9 *190:10 60.93
-5 *190:10 la_data_out[1] 21.645
-*END
-
-*D_NET *191 0.502773
-*CONN
-*P la_data_out[20] O
-*I *419:la_data_out[20] O *D user_proj_example
-*CAP
-1 la_data_out[20] 0.00321373
-2 *419:la_data_out[20] 0.000451681
-3 *191:16 0.00994698
-4 *191:15 0.00673325
-5 *191:13 0.00306122
-6 *191:11 0.0035129
-7 *191:11 *419:la_oenb[20] 0.00332452
-8 *191:11 *255:11 4.91006e-05
-9 *191:13 *255:11 0.159638
-10 *191:16 *273:8 0.0954299
-11 la_data_out[0] *191:13 0.00491006
-12 *419:la_data_in[20] *191:11 0
-13 *419:la_data_in[21] *191:11 0.000122752
-14 *419:la_data_in[21] *191:13 0.00247037
-15 *128:19 *191:13 0.127907
-16 *183:8 *191:16 0.0820013
-*RES
-1 *419:la_data_out[20] *191:11 7.335
-2 *191:11 *191:13 234.09
-3 *191:13 *191:15 4.5
-4 *191:15 *191:16 183.87
-5 *191:16 la_data_out[20] 35.145
-*END
-
-*D_NET *192 0.164488
-*CONN
-*P la_data_out[21] O
-*I *419:la_data_out[21] O *D user_proj_example
-*CAP
-1 la_data_out[21] 0.000187838
-2 *419:la_data_out[21] 0.000415293
-3 *192:15 0.0164344
-4 *192:14 0.0162466
-5 *192:12 0.018061
-6 *192:11 0.018061
-7 *192:9 0.00430561
-8 *192:7 0.0047209
-9 *192:7 *419:la_oenb[21] 0.00144233
-10 *192:9 *419:la_oenb[21] 0.00341249
-11 *192:9 *256:21 0.00982012
-12 *419:la_data_in[21] *192:7 0
-13 *99:11 *192:15 0
-14 *129:19 *192:9 0.07138
-15 *182:11 *192:7 0
-16 *182:11 *192:9 0
-*RES
-1 *419:la_data_out[21] *192:7 6.615
-2 *192:7 *192:9 104.85
-3 *192:9 *192:11 4.5
-4 *192:11 *192:12 188.91
-5 *192:12 *192:14 4.5
-6 *192:14 *192:15 160.11
-7 *192:15 la_data_out[21] 2.115
-*END
-
-*D_NET *193 0.183382
-*CONN
-*P la_data_out[22] O
-*I *419:la_data_out[22] O *D user_proj_example
-*CAP
-1 la_data_out[22] 0.0274305
-2 *419:la_data_out[22] 0.000746113
-3 *193:14 0.0274305
-4 *193:12 0.0078876
-5 *193:10 0.00863371
-6 *193:10 *419:la_oenb[22] 0.000756647
-7 *193:10 *246:16 6.99409e-05
-8 *193:12 *419:la_oenb[22] 0
-9 *193:12 *195:10 0.00237479
-10 *193:12 *200:8 0
-11 *193:12 *205:8 0
-12 *193:12 *207:10 7.46038e-05
-13 *193:12 *217:14 0.0933163
-14 *193:12 *269:24 0
-15 *419:la_data_in[22] *193:10 0
-16 *133:26 *193:12 0
-17 *144:16 *193:12 0.00563664
-18 *154:14 *193:12 0.00121229
-19 *168:16 *193:12 0.00781239
-*RES
-1 *419:la_data_out[22] *193:10 14.625
-2 *193:10 *193:12 191.97
-3 *193:12 *193:14 4.5
-4 *193:14 la_data_out[22] 267.165
-*END
-
-*D_NET *194 0.224709
-*CONN
-*P la_data_out[23] O
-*I *419:la_data_out[23] O *D user_proj_example
-*CAP
-1 la_data_out[23] 0.000125413
-2 *419:la_data_out[23] 0.0018423
-3 *194:19 0.0247714
-4 *194:18 0.024646
-5 *194:16 0.0111309
-6 *194:15 0.0129732
-7 *194:15 *419:la_oenb[23] 0.00133748
-8 *194:16 *197:20 0.133975
-9 *419:la_data_in[23] *194:15 0
-10 *131:19 *194:15 0.013073
-11 *178:16 *194:16 0.000834078
-*RES
-1 *419:la_data_out[23] *194:15 34.605
-2 *194:15 *194:16 202.23
-3 *194:16 *194:18 4.5
-4 *194:18 *194:19 241.83
-5 *194:19 la_data_out[23] 1.575
-*END
-
-*D_NET *195 0.284686
-*CONN
-*P la_data_out[24] O
-*I *419:la_data_out[24] O *D user_proj_example
-*CAP
-1 la_data_out[24] 0.000236116
-2 *419:la_data_out[24] 0.000799389
-3 *195:17 0.0254656
-4 *195:16 0.0252295
-5 *195:14 0.00551467
-6 *195:13 0.00647075
-7 *195:10 0.00175546
-8 la_data_out[24] *259:13 2.5829e-05
-9 *195:10 *419:la_oenb[22] 0.00173162
-10 *195:10 *419:la_oenb[24] 0.00103316
-11 *195:13 *419:la_oenb[30] 0.00153439
-12 *195:13 *202:15 0.00105336
-13 *195:13 *267:19 0
-14 *195:14 *204:10 0.128131
-15 *419:la_data_in[24] *195:10 0
-16 *419:la_data_in[31] *195:13 0.00206632
-17 *131:15 *195:17 7.67196e-06
-18 *186:8 *195:14 0.0812554
-19 *193:12 *195:10 0.00237479
-*RES
-1 *419:la_data_out[24] *195:10 30.735
-2 *195:10 *195:13 24.03
-3 *195:13 *195:14 190.53
-4 *195:14 *195:16 4.5
-5 *195:16 *195:17 247.23
-6 *195:17 la_data_out[24] 2.655
-*END
-
-*D_NET *196 0.286847
-*CONN
-*P la_data_out[25] O
-*I *419:la_data_out[25] O *D user_proj_example
-*CAP
-1 la_data_out[25] 0.00335391
-2 *419:la_data_out[25] 0.0014771
-3 *196:15 0.0250017
-4 *196:14 0.0216478
-5 *196:12 0.00763669
-6 *196:11 0.0091138
-7 *196:11 *419:la_oenb[25] 0.00185966
-8 *196:11 *260:11 0.00963588
-9 *196:12 *221:18 0.00746021
-10 *196:12 *253:16 0.111843
-11 *419:la_data_in[25] *196:11 0.00395055
-12 *172:14 *196:12 0.083867
-13 *173:16 *196:12 0
-*RES
-1 *419:la_data_out[25] *196:11 31.365
-2 *196:11 *196:12 215.91
-3 *196:12 *196:14 4.5
-4 *196:14 *196:15 212.94
-5 *196:15 la_data_out[25] 32.265
-*END
-
-*D_NET *197 0.348127
-*CONN
-*P la_data_out[26] O
-*I *419:la_data_out[26] O *D user_proj_example
-*CAP
-1 la_data_out[26] 0.000995799
-2 *419:la_data_out[26] 0.00172621
-3 *197:23 0.0249528
-4 *197:22 0.023957
-5 *197:20 0.00353975
-6 *197:19 0.00353975
-7 *197:17 0.00172621
-8 la_data_out[26] *295:8 0.00391659
-9 *197:17 *419:la_oenb[26] 0.00231387
-10 *197:17 *246:11 0.000921915
-11 *197:17 *261:11 0.00210723
-12 *197:20 *202:16 0.142555
-13 *197:23 *260:7 0.000184127
-14 *419:la_data_in[26] *197:17 0.000272738
-15 *133:13 *197:23 0
-16 *178:16 *197:20 0.00144234
-17 *194:16 *197:20 0.133975
-*RES
-1 *419:la_data_out[26] *197:17 48.105
-2 *197:17 *197:19 4.5
-3 *197:19 *197:20 216.81
-4 *197:20 *197:22 4.5
-5 *197:22 *197:23 235.71
-6 *197:23 la_data_out[26] 20.655
-*END
-
-*D_NET *198 0.245204
-*CONN
-*P la_data_out[27] O
-*I *419:la_data_out[27] O *D user_proj_example
-*CAP
-1 la_data_out[27] 0.0243205
-2 *419:la_data_out[27] 0.00203097
-3 *198:14 0.0243205
-4 *198:12 0.0125999
-5 *198:11 0.0146309
-6 la_data_out[27] *310:11 0
-7 *198:11 *419:la_oenb[27] 0.00296445
-8 *198:11 *246:11 0
-9 *198:11 *262:17 0.00785609
-10 *198:12 *199:24 0.156481
-11 *419:la_data_in[27] *198:11 0
-*RES
-1 *419:la_data_out[27] *198:11 36.945
-2 *198:11 *198:12 229.41
-3 *198:12 *198:14 4.5
-4 *198:14 la_data_out[27] 239.085
-*END
-
-*D_NET *199 0.363549
-*CONN
-*P la_data_out[28] O
-*I *419:la_data_out[28] O *D user_proj_example
-*CAP
-1 la_data_out[28] 0.000125413
-2 *419:la_data_out[28] 0.00226709
-3 *199:27 0.0244092
-4 *199:26 0.0242838
-5 *199:24 0.00451316
-6 *199:23 0.00459889
-7 *199:17 0.00235283
-8 *199:17 *419:la_oenb[28] 0.00231387
-9 *199:17 *263:21 0.00251641
-10 *199:23 *263:21 0.000613757
-11 *199:24 *207:14 0.139073
-12 *419:la_data_in[28] *199:17 0
-13 *198:12 *199:24 0.156481
-*RES
-1 *419:la_data_out[28] *199:17 49.995
-2 *199:17 *199:23 5.67
-3 *199:23 *199:24 234.63
-4 *199:24 *199:26 4.5
-5 *199:26 *199:27 238.95
-6 *199:27 la_data_out[28] 1.575
-*END
-
-*D_NET *200 0.249
-*CONN
-*P la_data_out[29] O
-*I *419:la_data_out[29] O *D user_proj_example
-*CAP
-1 la_data_out[29] 0.000245505
-2 *419:la_data_out[29] 0.00015814
-3 *200:11 0.0277182
-4 *200:10 0.0274727
-5 *200:8 0.0111267
-6 *200:7 0.0112848
-7 *200:7 *419:la_oenb[29] 0.00058307
-8 *200:8 *205:8 0.158325
-9 *200:8 *299:14 0.0120783
-10 *419:la_data_in[29] *200:7 0
-11 *136:15 *200:11 7.67196e-06
-12 *193:12 *200:8 0
-*RES
-1 *419:la_data_out[29] *200:7 7.065
-2 *200:7 *200:8 240.03
-3 *200:8 *200:10 4.5
-4 *200:10 *200:11 268.65
-5 *200:11 la_data_out[29] 2.655
-*END
-
-*D_NET *201 0.117559
-*CONN
-*P la_data_out[2] O
-*I *419:la_data_out[2] O *D user_proj_example
-*CAP
-1 la_data_out[2] 0.0141292
-2 *419:la_data_out[2] 0.00132637
-3 *201:14 0.0141292
-4 *201:12 0.00706171
-5 *201:11 0.00838808
-6 la_data_out[2] *246:11 0
-7 la_data_out[2] *262:17 0.0128275
-8 *201:11 *419:la_oenb[2] 0.000417739
-9 *419:la_data_in[2] *201:11 0.000528215
-10 *419:la_data_in[3] *201:11 0
-11 *135:15 la_data_out[2] 0.049295
-12 *137:19 *201:11 0.00203
-13 *148:15 *201:11 0.00742647
-*RES
-1 *419:la_data_out[2] *201:11 40.365
-2 *201:11 *201:12 67.59
-3 *201:12 *201:14 4.5
-4 *201:14 la_data_out[2] 235.665
-*END
-
-*D_NET *202 0.377365
-*CONN
-*P la_data_out[30] O
-*I *419:la_data_out[30] O *D user_proj_example
-*CAP
-1 la_data_out[30] 0.00333642
-2 *419:la_data_out[30] 0.00152082
-3 *202:19 0.024587
-4 *202:18 0.0212506
-5 *202:16 0.00463592
-6 *202:15 0.00615674
-7 *202:15 *419:la_oenb[30] 0.0023957
-8 *202:15 *266:19 0.00754921
-9 *202:16 *269:16 0.157724
-10 *419:la_data_in[30] *202:15 0
-11 *178:16 *202:16 0.00460055
-12 *195:13 *202:15 0.00105336
-13 *197:20 *202:16 0.142555
-*RES
-1 *419:la_data_out[30] *202:15 35.145
-2 *202:15 *202:16 248.31
-3 *202:16 *202:18 4.5
-4 *202:18 *202:19 209.7
-5 *202:19 la_data_out[30] 32.265
-*END
-
-*D_NET *203 0.272522
-*CONN
-*P la_data_out[31] O
-*I *419:la_data_out[31] O *D user_proj_example
-*CAP
-1 la_data_out[31] 0.000187838
-2 *419:la_data_out[31] 0.00176272
-3 *203:19 0.0241932
-4 *203:18 0.0240054
-5 *203:16 0.0139799
-6 *203:15 0.0157426
-7 *203:15 *419:la_oenb[31] 0.00666336
-8 *203:15 *257:15 0.000804022
-9 *203:15 *267:19 0.0160191
-10 *203:16 *206:10 0.169163
-11 *203:16 *231:16 0
-12 *419:la_data_in[31] *203:15 0
-*RES
-1 *419:la_data_out[31] *203:15 40.005
-2 *203:15 *203:16 253.71
-3 *203:16 *203:18 4.5
-4 *203:18 *203:19 236.61
-5 *203:19 la_data_out[31] 2.115
-*END
-
-*D_NET *204 0.353292
-*CONN
-*P la_data_out[32] O
-*I *419:la_data_out[32] O *D user_proj_example
-*CAP
-1 la_data_out[32] 0.000699672
-2 *419:la_data_out[32] 0.00163298
-3 *204:13 0.0252293
-4 *204:12 0.0245296
-5 *204:10 0.00782225
-6 *204:9 0.00945523
-7 la_data_out[32] *295:8 0.00105689
-8 *204:9 *419:la_oenb[32] 0.00254709
-9 *419:la_data_in[33] *204:9 4.47532e-06
-10 *141:19 *204:9 0.00129784
-11 *157:16 *204:10 0.150886
-12 *195:14 *204:10 0.128131
-*RES
-1 *419:la_data_out[32] *204:9 29.295
-2 *204:9 *204:10 259.65
-3 *204:10 *204:12 4.5
-4 *204:12 *204:13 241.11
-5 *204:13 la_data_out[32] 16.515
-*END
-
-*D_NET *205 0.394974
-*CONN
-*P la_data_out[33] O
-*I *419:la_data_out[33] O *D user_proj_example
-*CAP
-1 la_data_out[33] 0.000919192
-2 *419:la_data_out[33] 0.000198808
-3 *205:11 0.0276032
-4 *205:10 0.0266841
-5 *205:8 0.00796025
-6 *205:7 0.00815906
-7 la_data_out[33] *269:13 0
-8 la_data_out[33] *295:8 0.00354368
-9 *205:7 *419:la_oenb[33] 0.000210596
-10 *205:8 *299:14 0.00116255
-11 *205:11 *268:7 0.000383598
-12 *419:la_data_in[33] *205:7 0
-13 *141:15 *205:11 0
-14 *154:14 *205:8 0.159824
-15 *193:12 *205:8 0
-16 *200:8 *205:8 0.158325
-*RES
-1 *419:la_data_out[33] *205:7 7.245
-2 *205:7 *205:8 262.89
-3 *205:8 *205:10 4.5
-4 *205:10 *205:11 262.53
-5 *205:11 la_data_out[33] 20.115
-*END
-
-*D_NET *206 0.415415
-*CONN
-*P la_data_out[34] O
-*I *419:la_data_out[34] O *D user_proj_example
-*CAP
-1 la_data_out[34] 0.000236116
-2 *419:la_data_out[34] 0.00241532
-3 *206:13 0.0242027
-4 *206:12 0.0239665
-5 *206:10 0.00479356
-6 *206:9 0.00720887
-7 la_data_out[34] *270:15 2.5829e-05
-8 *206:9 *419:la_oenb[34] 0.00254709
-9 *206:10 *211:10 0.178489
-10 *419:la_data_in[34] *206:9 0
-11 *419:la_data_in[35] *206:9 4.47532e-06
-12 *142:11 *206:13 7.67196e-06
-13 *143:11 *206:9 0.00235402
-14 *203:16 *206:10 0.169163
-*RES
-1 *419:la_data_out[34] *206:9 40.095
-2 *206:9 *206:10 271.89
-3 *206:10 *206:12 4.5
-4 *206:12 *206:13 236.43
-5 *206:13 la_data_out[34] 2.655
-*END
-
-*D_NET *207 0.398045
-*CONN
-*P la_data_out[35] O
-*I *419:la_data_out[35] O *D user_proj_example
-*CAP
-1 la_data_out[35] 0.00332477
-2 *419:la_data_out[35] 0.000750232
-3 *207:17 0.0242513
-4 *207:16 0.0209265
-5 *207:14 0.00568898
-6 *207:13 0.00801116
-7 *207:10 0.00307241
-8 *207:10 *419:la_oenb[35] 0.00115591
-9 *207:10 *269:24 0.00441406
-10 *207:13 *419:la_oenb[40] 0.000822435
-11 *207:13 *213:15 0.000730371
-12 *207:13 *278:19 0
-13 *207:14 *214:14 0.182716
-14 *419:la_data_in[35] *207:10 0
-15 *419:la_data_in[38] *207:10 0.00167858
-16 *142:22 *207:10 0.000111905
-17 *144:16 *207:10 0.0012421
-18 *193:12 *207:10 7.46038e-05
-19 *199:24 *207:14 0.139073
-*RES
-1 *419:la_data_out[35] *207:10 28.575
-2 *207:10 *207:13 31.95
-3 *207:13 *207:14 266.13
-4 *207:14 *207:16 4.5
-5 *207:16 *207:17 207
-6 *207:17 la_data_out[35] 32.265
-*END
-
-*D_NET *208 0.228348
-*CONN
-*P la_data_out[36] O
-*I *419:la_data_out[36] O *D user_proj_example
-*CAP
-1 la_data_out[36] 0.000187838
-2 *419:la_data_out[36] 0.00255198
-3 *208:17 0.00686514
-4 *208:16 0.0066773
-5 *208:14 0.025681
-6 *208:13 0.025681
-7 *208:11 0.00932257
-8 *208:9 0.0118745
-9 *208:9 *419:la_oenb[36] 0.00254709
-10 *208:9 *272:19 0.002175
-11 *208:9 *273:11 0
-12 *208:11 *272:19 0.1133
-13 *208:14 *241:14 0.0205782
-14 *419:la_data_in[36] *208:9 0.000150371
-15 *419:la_data_in[37] *208:9 0.000756329
-*RES
-1 *419:la_data_out[36] *208:9 41.175
-2 *208:9 *208:11 166.14
-3 *208:11 *208:13 4.5
-4 *208:13 *208:14 286.11
-5 *208:14 *208:16 4.5
-6 *208:16 *208:17 65.61
-7 *208:17 la_data_out[36] 2.115
-*END
-
-*D_NET *209 0.290924
-*CONN
-*P la_data_out[37] O
-*I *419:la_data_out[37] O *D user_proj_example
-*CAP
-1 la_data_out[37] 0.0236298
-2 *419:la_data_out[37] 0.00248474
-3 *209:14 0.0236298
-4 *209:12 0.0157266
-5 *209:11 0.0182114
-6 *209:11 *419:la_oenb[37] 0.00612325
-7 *209:12 *210:16 0.201119
-8 *419:la_data_in[37] *209:11 0
-*RES
-1 *419:la_data_out[37] *209:11 42.525
-2 *209:11 *209:12 294.21
-3 *209:12 *209:14 4.5
-4 *209:14 la_data_out[37] 233.505
-*END
-
-*D_NET *210 0.467462
-*CONN
-*P la_data_out[38] O
-*I *419:la_data_out[38] O *D user_proj_example
-*CAP
-1 la_data_out[38] 0.000125413
-2 *419:la_data_out[38] 0.00172833
-3 *210:19 0.0237186
-4 *210:18 0.0235932
-5 *210:16 0.00480799
-6 *210:15 0.00480799
-7 *210:13 0.00172833
-8 *210:13 *419:la_oenb[38] 0.0118148
-9 *210:13 *269:24 0
-10 *210:16 *283:16 0.187566
-11 *419:la_data_in[38] *210:13 0.000417739
-12 *147:19 *210:13 0.00603528
-13 *209:12 *210:16 0.201119
-*RES
-1 *419:la_data_out[38] *210:13 47.4907
-2 *210:13 *210:15 4.5
-3 *210:15 *210:16 299.25
-4 *210:16 *210:18 4.5
-5 *210:18 *210:19 233.37
-6 *210:19 la_data_out[38] 1.575
-*END
-
-*D_NET *211 0.443557
-*CONN
-*P la_data_out[39] O
-*I *419:la_data_out[39] O *D user_proj_example
-*CAP
-1 la_data_out[39] 0.000245505
-2 *419:la_data_out[39] 0.00224249
-3 *211:13 0.0241373
-4 *211:12 0.0238918
-5 *211:10 0.0056268
-6 *211:9 0.00786929
-7 *211:9 *419:la_oenb[39] 0.00254709
-8 *211:9 *275:11 0.00182976
-9 *211:9 *277:19 0
-10 *211:10 *215:14 0.00460055
-11 *211:10 *281:16 0.191296
-12 *419:la_data_in[40] *211:9 0.00077423
-13 *147:11 *211:13 7.67196e-06
-14 *206:10 *211:10 0.178489
-*RES
-1 *419:la_data_out[39] *211:9 40.275
-2 *211:9 *211:10 304.29
-3 *211:10 *211:12 4.5
-4 *211:12 *211:13 236.25
-5 *211:13 la_data_out[39] 2.655
-*END
-
-*D_NET *212 0.218542
-*CONN
-*P la_data_out[3] O
-*I *419:la_data_out[3] O *D user_proj_example
-*CAP
-1 la_data_out[3] 0.00153717
-2 *419:la_data_out[3] 0.00217097
-3 *212:12 0.00669164
-4 *212:11 0.00515447
-5 *212:9 0.0125978
-6 *212:7 0.0147688
-7 la_data_out[3] *276:15 0
-8 *212:7 *419:la_oenb[3] 0.000445358
-9 *212:12 *261:8 0.0080199
-10 *419:la_data_in[3] *212:7 0
-11 *419:la_data_in[4] *212:7 0
-12 *119:8 *212:12 0.00874512
-13 *159:11 *212:7 0.00460318
-14 *159:11 *212:9 0.153808
-*RES
-1 *419:la_data_out[3] *212:7 31.725
-2 *212:7 *212:9 225.54
-3 *212:9 *212:11 4.5
-4 *212:11 *212:12 73.71
-5 *212:12 la_data_out[3] 18.765
-*END
-
-*D_NET *213 0.322832
-*CONN
-*P la_data_out[40] O
-*I *419:la_data_out[40] O *D user_proj_example
-*CAP
-1 la_data_out[40] 0.00330144
-2 *419:la_data_out[40] 0.002178
-3 *213:19 0.0233903
-4 *213:18 0.0200888
-5 *213:16 0.0168921
-6 *213:15 0.0190701
-7 *213:15 *419:la_oenb[40] 0.00666336
-8 *213:15 *277:19 0.0198244
-9 *213:16 *216:14 0.210693
-10 *419:la_data_in[40] *213:15 0
-11 *207:13 *213:15 0.000730371
-*RES
-1 *419:la_data_out[40] *213:15 45.585
-2 *213:15 *213:16 313.11
-3 *213:16 *213:18 4.5
-4 *213:18 *213:19 199.26
-5 *213:19 la_data_out[40] 32.265
-*END
-
-*D_NET *214 0.453106
-*CONN
-*P la_data_out[41] O
-*I *419:la_data_out[41] O *D user_proj_example
-*CAP
-1 la_data_out[41] 0.000187838
-2 *419:la_data_out[41] 0.00194462
-3 *214:17 0.0243152
-4 *214:16 0.0241273
-5 *214:14 0.00762583
-6 *214:13 0.00957045
-7 *214:13 *419:la_oenb[41] 0.00254709
-8 *214:13 *278:19 0.00894935
-9 *214:14 *231:16 0.190177
-10 *419:la_data_in[41] *214:13 0
-11 *419:la_data_in[42] *214:13 0.000944292
-12 *207:14 *214:14 0.182716
-*RES
-1 *419:la_data_out[41] *214:13 38.655
-2 *214:13 *214:14 318.51
-3 *214:14 *214:16 4.5
-4 *214:16 *214:17 238.59
-5 *214:17 la_data_out[41] 2.115
-*END
-
-*D_NET *215 0.495861
-*CONN
-*P la_data_out[42] O
-*I *419:la_data_out[42] O *D user_proj_example
-*CAP
-1 la_data_out[42] 0.0238386
-2 *419:la_data_out[42] 0.00212026
-3 *215:16 0.0238386
-4 *215:14 0.00507003
-5 *215:13 0.00719029
-6 *215:13 *419:la_oenb[42] 0.00254709
-7 *215:13 *279:11 0.0107906
-8 *215:14 *228:16 0.203108
-9 *215:14 *281:16 0.211812
-10 *419:la_data_in[43] *215:13 0.000944292
-11 *211:10 *215:14 0.00460055
-*RES
-1 *419:la_data_out[42] *215:13 41.355
-2 *215:13 *215:14 326.61
-3 *215:14 *215:16 4.5
-4 *215:16 la_data_out[42] 235.845
-*END
-
-*D_NET *216 0.501955
-*CONN
-*P la_data_out[43] O
-*I *419:la_data_out[43] O *D user_proj_example
-*CAP
-1 la_data_out[43] 0.000125413
-2 *419:la_data_out[43] 0.00256679
-3 *216:17 0.0234278
-4 *216:16 0.0233024
-5 *216:14 0.006005
-6 *216:13 0.00857178
-7 *216:13 *419:la_oenb[43] 0.00254709
-8 *216:13 *280:19 0.0142277
-9 *216:14 *288:16 0.209947
-10 *419:la_data_in[44] *216:13 0.000541513
-11 *213:16 *216:14 0.210693
-*RES
-1 *419:la_data_out[43] *216:13 46.395
-2 *216:13 *216:14 332.01
-3 *216:14 *216:16 4.5
-4 *216:16 *216:17 230.85
-5 *216:17 la_data_out[43] 1.575
-*END
-
-*D_NET *217 0.407507
-*CONN
-*P la_data_out[44] O
-*I *419:la_data_out[44] O *D user_proj_example
-*CAP
-1 la_data_out[44] 0.000236116
-2 *419:la_data_out[44] 0.000445781
-3 *217:17 0.0273029
-4 *217:16 0.0270668
-5 *217:14 0.00874703
-6 *217:13 0.00919281
-7 la_data_out[44] *281:13 2.5829e-05
-8 *217:13 *419:la_oenb[44] 0.000348691
-9 *217:13 *218:9 3.45239e-05
-10 *217:14 *294:16 0
-11 *419:la_data_in[41] *217:13 0.00167858
-12 *419:la_data_in[44] *217:13 0
-13 *33:9 *217:14 0.0514144
-14 *144:16 *217:13 0.00167847
-15 *144:16 *217:14 0.179111
-16 *153:11 *217:17 7.67196e-06
-17 *168:16 *217:14 0.00690085
-18 *193:12 *217:14 0.0933163
-*RES
-1 *419:la_data_out[44] *217:13 20.925
-2 *217:13 *217:14 334.89
-3 *217:14 *217:16 4.5
-4 *217:16 *217:17 267.03
-5 *217:17 la_data_out[44] 2.655
-*END
-
-*D_NET *218 0.222872
-*CONN
-*P la_data_out[45] O
-*I *419:la_data_out[45] O *D user_proj_example
-*CAP
-1 la_data_out[45] 0.00325098
-2 *419:la_data_out[45] 0.00227556
-3 *218:19 0.00723673
-4 *218:14 0.0365055
-5 *218:13 0.0325198
-6 *218:11 0.00953376
-7 *218:9 0.0118093
-8 *218:9 *419:la_oenb[45] 0.00254709
-9 *419:la_data_in[45] *218:9 0
-10 *419:la_data_in[46] *218:9 4.47532e-06
-11 *155:19 *218:9 0.00201389
-12 *155:19 *218:11 0.115141
-13 *217:13 *218:9 3.45239e-05
-*RES
-1 *419:la_data_out[45] *218:9 32.715
-2 *218:9 *218:11 168.84
-3 *218:11 *218:13 4.5
-4 *218:13 *218:14 345.33
-5 *218:14 *218:19 44.19
-6 *218:19 la_data_out[45] 31.815
-*END
-
-*D_NET *219 0.483691
-*CONN
-*P la_data_out[46] O
-*I *419:la_data_out[46] O *D user_proj_example
-*CAP
-1 la_data_out[46] 0.000187838
-2 *419:la_data_out[46] 0.00113974
-3 *219:17 0.0265097
-4 *219:16 0.0263219
-5 *219:14 0.00764174
-6 *219:13 0.00878148
-7 *219:13 *419:la_oenb[46] 0
-8 *219:13 *419:la_oenb[49] 0.00913896
-9 *219:13 *419:la_oenb[54] 0.000225045
-10 *219:13 *228:15 0.00073344
-11 *419:la_data_in[41] *219:13 0.000184127
-12 *419:la_data_in[46] *219:13 0
-13 *419:la_data_in[47] *219:13 0.000994715
-14 *419:la_data_in[55] *219:13 0.000465433
-15 *142:22 *219:13 0.0153559
-16 *144:16 *219:13 6.21698e-05
-17 *146:16 *219:14 0.174759
-18 *174:16 *219:14 0.211191
-*RES
-1 *419:la_data_out[46] *219:13 46.845
-2 *219:13 *219:14 328.59
-3 *219:14 *219:16 4.5
-4 *219:16 *219:17 260.19
-5 *219:17 la_data_out[46] 2.115
-*END
-
-*D_NET *220 0.416704
-*CONN
-*P la_data_out[47] O
-*I *419:la_data_out[47] O *D user_proj_example
-*CAP
-1 la_data_out[47] 0.0229951
-2 *419:la_data_out[47] 0.00283722
-3 *220:16 0.0229951
-4 *220:14 0.0149188
-5 *220:13 0.0177561
-6 *220:13 *419:la_oenb[46] 0
-7 *220:13 *419:la_oenb[47] 0.00144233
-8 *220:13 *284:11 0.0248848
-9 *220:14 *224:10 0.242524
-10 *220:14 *252:16 0.0652158
-11 *419:la_data_in[47] *220:13 0
-12 *419:la_data_in[48] *220:13 4.02619e-05
-13 *39:10 *220:14 0.00109419
-*RES
-1 *419:la_data_out[47] *220:13 49.275
-2 *220:13 *220:14 359.01
-3 *220:14 *220:16 4.5
-4 *220:16 la_data_out[47] 228.105
-*END
-
-*D_NET *221 0.558419
-*CONN
-*P la_data_out[48] O
-*I *419:la_data_out[48] O *D user_proj_example
-*CAP
-1 la_data_out[48] 0.00114801
-2 *419:la_data_out[48] 0.00127573
-3 *221:21 0.0247748
-4 *221:20 0.0236268
-5 *221:18 0.00405017
-6 *221:17 0.00532589
-7 la_data_out[48] *285:15 0
-8 la_data_out[48] *310:14 0
-9 *221:17 *419:la_oenb[48] 0.000662325
-10 *221:17 *283:22 0.000448043
-11 *221:17 *285:19 0.0139323
-12 *221:21 *284:7 0.000604551
-13 *419:la_data_in[48] *221:17 0.000240133
-14 *419:la_data_in[49] *221:17 0.000552382
-15 *157:13 *221:21 0
-16 *158:8 la_data_out[48] 0.000708712
-17 *160:14 *221:18 0.247124
-18 *172:14 *221:18 0.226484
-19 *196:12 *221:18 0.00746021
-*RES
-1 *419:la_data_out[48] *221:17 32.715
-2 *221:17 *221:18 360.27
-3 *221:18 *221:20 4.5
-4 *221:20 *221:21 236.97
-5 *221:21 la_data_out[48] 21.555
-*END
-
-*D_NET *222 0.342919
-*CONN
-*P la_data_out[49] O
-*I *419:la_data_out[49] O *D user_proj_example
-*CAP
-1 la_data_out[49] 0.000236116
-2 *419:la_data_out[49] 0.00190293
-3 *222:15 0.0236357
-4 *222:14 0.0233996
-5 *222:12 0.0204576
-6 *222:11 0.0223605
-7 la_data_out[49] *286:15 2.5829e-05
-8 *222:11 *419:la_oenb[49] 0.000403929
-9 *222:11 *281:21 0.00205916
-10 *222:11 *283:22 0
-11 *222:12 *283:16 0.238669
-12 *419:la_data_in[49] *222:11 0
-13 *419:la_data_in[50] *222:11 0.00456227
-14 *158:7 *222:15 0.000234762
-15 *178:13 *222:11 0.00497143
-*RES
-1 *419:la_data_out[49] *222:11 43.065
-2 *222:11 *222:12 369.81
-3 *222:12 *222:14 4.5
-4 *222:14 *222:15 233.01
-5 *222:15 la_data_out[49] 2.655
-*END
-
-*D_NET *223 0.350223
-*CONN
-*P la_data_out[4] O
-*I *419:la_data_out[4] O *D user_proj_example
-*CAP
-1 la_data_out[4] 0.00258828
-2 *419:la_data_out[4] 0.00226562
-3 *223:24 0.00475721
-4 *223:23 0.00216893
-5 *223:21 0.00652495
-6 *223:19 0.00655379
-7 *223:17 0.00229446
-8 la_data_out[4] *287:15 1.87963e-05
-9 *223:17 *419:la_oenb[4] 0.00231387
-10 *223:17 *287:19 0.00251641
-11 *223:21 wbs_dat_o[27] 0.00210723
-12 *223:21 *287:19 0.148161
-13 *223:21 *400:17 0.0801567
-14 *223:24 *234:14 0.05216
-15 *419:la_data_in[4] *223:17 0
-16 *159:7 la_data_out[4] 0.000136561
-17 *184:10 *223:24 0.0354987
-*RES
-1 *419:la_data_out[4] *223:17 49.995
-2 *223:17 *223:19 0.27
-3 *223:19 *223:21 217.26
-4 *223:21 *223:23 4.5
-5 *223:23 *223:24 78.03
-6 *223:24 la_data_out[4] 29.745
-*END
-
-*D_NET *224 0.566525
-*CONN
-*P la_data_out[50] O
-*I *419:la_data_out[50] O *D user_proj_example
-*CAP
-1 la_data_out[50] 0.00328396
-2 *419:la_data_out[50] 0.00388316
-3 *224:13 0.0230052
-4 *224:12 0.0197212
-5 *224:10 0.00531124
-6 *224:9 0.0091944
-7 *224:9 *419:la_oenb[50] 0
-8 *224:9 *281:21 0
-9 *224:10 *235:10 0.242524
-10 *419:la_data_in[47] *224:9 0
-11 *419:la_data_in[50] *224:9 0.000242434
-12 *419:la_data_in[51] *224:9 0.010618
-13 *39:10 *224:10 0.00621689
-14 *172:11 la_data_out[50] 0
-15 *172:11 *224:13 0
-16 *220:14 *224:10 0.242524
-*RES
-1 *419:la_data_out[50] *224:9 48.195
-2 *224:9 *224:10 378.09
-3 *224:10 *224:12 4.5
-4 *224:12 *224:13 196.2
-5 *224:13 la_data_out[50] 32.265
-*END
-
-*D_NET *225 0.591146
-*CONN
-*P la_data_out[51] O
-*I *419:la_data_out[51] O *D user_proj_example
-*CAP
-1 la_data_out[51] 0.000187838
-2 *419:la_data_out[51] 0.00306997
-3 *225:17 0.0228362
-4 *225:16 0.0226484
-5 *225:14 0.00514428
-6 *225:13 0.00514428
-7 *225:11 0.00306997
-8 *225:11 *419:la_oenb[51] 0.00144233
-9 *225:11 *289:11 0.0269716
-10 *225:14 *233:10 0.249985
-11 *225:14 *256:16 0.00708727
-12 *225:14 *291:16 0.243519
-13 *419:la_data_in[52] *225:11 4.02779e-05
-*RES
-1 *419:la_data_out[51] *225:11 47.835
-2 *225:11 *225:13 4.5
-3 *225:13 *225:14 383.31
-4 *225:14 *225:16 4.5
-5 *225:16 *225:17 225.09
-6 *225:17 la_data_out[51] 2.115
-*END
-
-*D_NET *226 0.360733
-*CONN
-*P la_data_out[52] O
-*I *419:la_data_out[52] O *D user_proj_example
-*CAP
-1 la_data_out[52] 0.0223775
-2 *419:la_data_out[52] 0.00487001
-3 *226:12 0.0223775
-4 *226:10 0.0167396
-5 *226:9 0.0167396
-6 *226:7 0.00487001
-7 *226:7 *419:la_oenb[52] 0
-8 *226:10 *293:16 0.26217
-9 *419:la_data_in[52] *226:7 0.000837779
-10 *419:la_data_in[53] *226:7 0
-11 *108:14 *226:10 0.00975133
-*RES
-1 *419:la_data_out[52] *226:7 49.095
-2 *226:7 *226:9 4.5
-3 *226:9 *226:10 391.59
-4 *226:10 *226:12 4.5
-5 *226:12 la_data_out[52] 222.525
-*END
-
-*D_NET *227 0.371405
-*CONN
-*P la_data_out[53] O
-*I *419:la_data_out[53] O *D user_proj_example
-*CAP
-1 la_data_out[53] 0.000125413
-2 *419:la_data_out[53] 0.00324321
-3 *227:11 0.0221958
-4 *227:10 0.0220704
-5 *227:8 0.0208396
-6 *227:7 0.0208396
-7 *227:5 0.00324321
-8 *227:5 *419:la_oenb[53] 0.000341786
-9 *227:5 *288:25 0.00295294
-10 *227:8 *230:10 0.268635
-11 *419:la_data_in[53] *227:5 0
-12 *419:la_data_in[54] *227:5 0.00513511
-13 *182:14 *227:8 0.0017822
-*RES
-1 *419:la_data_out[53] *227:5 51.345
-2 *227:5 *227:7 4.5
-3 *227:7 *227:8 396.63
-4 *227:8 *227:10 4.5
-5 *227:10 *227:11 219.87
-6 *227:11 la_data_out[53] 1.575
-*END
-
-*D_NET *228 0.328166
-*CONN
-*P la_data_out[54] O
-*I *419:la_data_out[54] O *D user_proj_example
-*CAP
-1 la_data_out[54] 0.000245505
-2 *419:la_data_out[54] 0.00230855
-3 *228:19 0.0239438
-4 *228:18 0.0236983
-5 *228:16 0.0247529
-6 *228:15 0.0270615
-7 *228:15 *419:la_oenb[54] 0.000257394
-8 *228:15 *292:11 0.00130935
-9 *228:16 *281:16 0.00435188
-10 *419:la_data_in[54] *228:15 0
-11 *419:la_data_in[55] *228:15 0
-12 *164:11 *228:19 7.67196e-06
-13 *165:11 *228:15 0.0163873
-14 *215:14 *228:16 0.203108
-15 *219:13 *228:15 0.00073344
-*RES
-1 *419:la_data_out[54] *228:15 40.725
-2 *228:15 *228:16 402.03
-3 *228:16 *228:18 4.5
-4 *228:18 *228:19 235.71
-5 *228:19 la_data_out[54] 2.655
-*END
-
-*D_NET *229 0.591538
-*CONN
-*P la_data_out[55] O
-*I *419:la_data_out[55] O *D user_proj_example
-*CAP
-1 la_data_out[55] 0.00104047
-2 *419:la_data_out[55] 0.00441602
-3 *229:13 0.0235167
-4 *229:12 0.0224763
-5 *229:10 0.00705793
-6 *229:9 0.0114739
-7 *229:9 *419:la_oenb[55] 0
-8 *229:10 *288:16 0.253715
-9 *229:10 *309:10 0.263911
-10 *419:la_data_in[55] *229:9 0.000395873
-11 *142:21 *229:9 0.000365186
-12 *165:5 *229:13 0
-13 *172:8 la_data_out[55] 0.00317055
-*RES
-1 *419:la_data_out[55] *229:9 45.675
-2 *229:9 *229:10 406.35
-3 *229:10 *229:12 4.5
-4 *229:12 *229:13 223.65
-5 *229:13 la_data_out[55] 20.475
-*END
-
-*D_NET *230 0.634529
-*CONN
-*P la_data_out[56] O
-*I *419:la_data_out[56] O *D user_proj_example
-*CAP
-1 la_data_out[56] 0.000187838
-2 *419:la_data_out[56] 4.01718e-05
-3 *230:13 0.0222277
-4 *230:12 0.0220398
-5 *230:10 0.00573559
-6 *230:9 0.00573559
-7 *230:7 0.00422506
-8 *230:5 0.00426523
-9 *230:7 *419:la_oenb[56] 0
-10 *230:7 *293:19 0
-11 *230:10 *237:10 0.276096
-12 *419:la_data_in[56] *230:7 0.0011109
-13 *419:la_data_in[57] *230:7 0.014546
-14 *133:24 *230:7 0.000171852
-15 *142:21 *230:7 0
-16 *182:14 *230:10 0.00951176
-17 *227:8 *230:10 0.268635
-*RES
-1 *419:la_data_out[56] *230:5 0.405
-2 *230:5 *230:7 51.57
-3 *230:7 *230:9 4.5
-4 *230:9 *230:10 415.89
-5 *230:10 *230:12 4.5
-6 *230:12 *230:13 219.69
-7 *230:13 la_data_out[56] 2.115
-*END
-
-*D_NET *231 0.315635
-*CONN
-*P la_data_out[57] O
-*I *419:la_data_out[57] O *D user_proj_example
-*CAP
-1 la_data_out[57] 0.023945
-2 *419:la_data_out[57] 0.00249609
-3 *231:18 0.023945
-4 *231:16 0.0281608
-5 *231:15 0.0306569
-6 la_data_out[57] *232:13 0
-7 *231:15 *419:la_oenb[57] 0.00178194
-8 *231:15 *295:11 0.0144724
-9 *419:la_data_in[57] *231:15 0
-10 *203:16 *231:16 0
-11 *214:14 *231:16 0.190177
-*RES
-1 *419:la_data_out[57] *231:15 38.205
-2 *231:15 *231:16 423.81
-3 *231:16 *231:18 4.5
-4 *231:18 la_data_out[57] 238.365
-*END
-
-*D_NET *232 0.38685
-*CONN
-*P la_data_out[58] O
-*I *419:la_data_out[58] O *D user_proj_example
-*CAP
-1 la_data_out[58] 0.00106742
-2 *419:la_data_out[58] 0.00524529
-3 *232:13 0.0227293
-4 *232:12 0.0216619
-5 *232:10 0.0225903
-6 *232:9 0.0225903
-7 *232:7 0.00524529
-8 la_data_out[58] *295:8 0.00304632
-9 la_data_out[58] *296:13 0
-10 *232:7 *419:la_oenb[57] 0
-11 *232:7 *419:la_oenb[58] 0
-12 *232:10 *293:16 0.279826
-13 la_data_out[57] *232:13 0
-14 *419:la_data_in[58] *232:7 0.000423492
-15 *419:la_data_in[59] *232:7 0
-16 *108:14 *232:10 0
-17 *172:8 la_data_out[58] 0.00242462
-*RES
-1 *419:la_data_out[58] *232:7 49.455
-2 *232:7 *232:9 4.5
-3 *232:9 *232:10 419.85
-4 *232:10 *232:12 4.5
-5 *232:12 *232:13 215.91
-6 *232:13 la_data_out[58] 25.875
-*END
-
-*D_NET *233 0.368736
-*CONN
-*P la_data_out[59] O
-*I *419:la_data_out[59] O *D user_proj_example
-*CAP
-1 la_data_out[59] 0.000236116
-2 *419:la_data_out[59] 0.0039496
-3 *233:13 0.022799
-4 *233:12 0.0225629
-5 *233:10 0.0249848
-6 *233:9 0.0249848
-7 *233:7 0.0039496
-8 la_data_out[59] *297:13 2.5829e-05
-9 *233:7 *419:la_oenb[59] 0.000626544
-10 *233:10 *291:16 0.00497357
-11 *419:la_data_in[59] *233:7 0.000751853
-12 *419:la_data_in[60] *233:7 0.00889948
-13 *108:14 *233:10 0
-14 *169:11 *233:13 7.67196e-06
-15 *225:14 *233:10 0.249985
-*RES
-1 *419:la_data_out[59] *233:7 46.755
-2 *233:7 *233:9 4.5
-3 *233:9 *233:10 434.79
-4 *233:10 *233:12 4.5
-5 *233:12 *233:13 224.91
-6 *233:13 la_data_out[59] 2.655
-*END
-
-*D_NET *234 0.354569
-*CONN
-*P la_data_out[5] O
-*I *419:la_data_out[5] O *D user_proj_example
-*CAP
-1 la_data_out[5] 0.00238438
-2 *419:la_data_out[5] 0.000553466
-3 *234:14 0.00714188
-4 *234:13 0.0047575
-5 *234:11 0.00680686
-6 *234:9 0.00736032
-7 *234:9 *419:la_oenb[5] 0.00152417
-8 *234:11 *419:la_oenb[5] 7.36509e-05
-9 *234:11 *298:11 0.163689
-10 *234:14 *272:16 0.00217594
-11 *419:la_data_in[5] *234:11 0
-12 *419:la_data_in[6] *234:9 4.47532e-06
-13 *419:la_data_in[6] *234:11 0
-14 *175:19 *234:11 0.104093
-15 *184:10 *234:14 0.00184437
-16 *223:24 *234:14 0.05216
-*RES
-1 *419:la_data_out[5] *234:9 8.145
-2 *234:9 *234:11 242.19
-3 *234:11 *234:13 4.5
-4 *234:13 *234:14 86.67
-5 *234:14 la_data_out[5] 26.865
-*END
-
-*D_NET *235 0.634032
-*CONN
-*P la_data_out[60] O
-*I *419:la_data_out[60] O *D user_proj_example
-*CAP
-1 la_data_out[60] 0.00326646
-2 *419:la_data_out[60] 0.00373331
-3 *235:13 0.0229115
-4 *235:12 0.019645
-5 *235:10 0.00857449
-6 *235:9 0.0123078
-7 *235:9 *419:la_oenb[60] 0
-8 *235:9 *286:19 0
-9 *419:la_data_in[60] *235:9 0.000217884
-10 *419:la_data_in[61] *235:9 0.0149143
-11 *39:10 *235:10 0.305937
-12 *224:10 *235:10 0.242524
-*RES
-1 *419:la_data_out[60] *235:9 48.375
-2 *235:9 *235:10 442.89
-3 *235:10 *235:12 4.5
-4 *235:12 *235:13 196.02
-5 *235:13 la_data_out[60] 32.265
-*END
-
-*D_NET *236 0.241921
-*CONN
-*P la_data_out[61] O
-*I *419:la_data_out[61] O *D user_proj_example
-*CAP
-1 la_data_out[61] 0.000187838
-2 *419:la_data_out[61] 0.000542157
-3 *236:19 0.0219572
-4 *236:18 0.0217694
-5 *236:16 0.0363809
-6 *236:15 0.0363809
-7 *236:13 0.00317548
-8 *236:11 0.00371764
-9 *236:11 *419:la_oenb[61] 0.000695848
-10 *236:11 *286:19 0
-11 *236:11 *300:17 0.000184127
-12 *236:13 *300:17 0.00626033
-13 *236:16 *262:12 0.0967983
-14 *236:19 *300:13 0
-15 la_data_out[12] *236:13 0.00190265
-16 *419:la_data_in[61] *236:11 0
-17 *419:la_data_in[62] *236:11 0
-18 *419:la_data_in[62] *236:13 0.0119683
-19 *172:7 *236:19 0
-*RES
-1 *419:la_data_out[61] *236:11 7.155
-2 *236:11 *236:13 47.97
-3 *236:13 *236:15 4.5
-4 *236:15 *236:16 447.93
-5 *236:16 *236:18 4.5
-6 *236:18 *236:19 216.81
-7 *236:19 la_data_out[61] 2.115
-*END
-
-*D_NET *237 0.384244
-*CONN
-*P la_data_out[62] O
-*I *419:la_data_out[62] O *D user_proj_example
-*CAP
-1 la_data_out[62] 0.0220011
-2 *419:la_data_out[62] 4.01718e-05
-3 *237:12 0.0220011
-4 *237:10 0.0263466
-5 *237:9 0.0263466
-6 *237:7 0.00542669
-7 *237:5 0.00546686
-8 *237:7 *419:la_oenb[62] 0
-9 *237:7 *291:23 0.000270053
-10 *419:la_data_in[62] *237:7 0.000248572
-11 *230:10 *237:10 0.276096
-*RES
-1 *419:la_data_out[62] *237:5 0.405
-2 *237:5 *237:7 51.75
-3 *237:7 *237:9 4.5
-4 *237:9 *237:10 456.39
-5 *237:10 *237:12 4.5
-6 *237:12 la_data_out[62] 219.465
-*END
-
-*D_NET *238 0.414871
-*CONN
-*P la_data_out[63] O
-*I *419:la_data_out[63] O *D user_proj_example
-*CAP
-1 la_data_out[63] 0.000125413
-2 *419:la_data_out[63] 0.000707279
-3 *238:17 0.0264504
-4 *238:16 0.026325
-5 *238:14 0.0235718
-6 *238:13 0.024279
-7 *238:13 *419:la_oenb[63] 0.00103316
-8 *238:13 *301:20 0.00113978
-9 *238:13 *310:7 0
-10 *238:14 *301:12 0.295866
-11 *419:la_data_in[63] *238:13 0.000348691
-12 *121:8 *238:14 0.00951187
-13 *144:16 *238:13 0.00341934
-14 *166:16 *238:14 0.00209305
-*RES
-1 *419:la_data_out[63] *238:13 27.045
-2 *238:13 *238:14 456.57
-3 *238:14 *238:16 4.5
-4 *238:16 *238:17 262.71
-5 *238:17 la_data_out[63] 1.575
-*END
-
-*D_NET *239 0.191117
-*CONN
-*P la_data_out[6] O
-*I *419:la_data_out[6] O *D user_proj_example
-*CAP
-1 la_data_out[6] 0.000187838
-2 *419:la_data_out[6] 0.000484588
-3 *239:19 0.00678475
-4 *239:18 0.00659691
-5 *239:16 0.00920035
-6 *239:15 0.00920035
-7 *239:13 0.0113015
-8 *239:11 0.0117861
-9 *239:11 *419:la_oenb[6] 0.000686897
-10 *239:13 *419:la_oenb[6] 0.000699683
-11 *239:13 *303:11 8.18344e-05
-12 *419:la_data_in[6] *239:11 0
-13 *419:la_data_in[6] *239:13 0
-14 *419:la_data_in[7] *239:13 0
-15 *176:11 *239:13 0.134106
-*RES
-1 *419:la_data_out[6] *239:11 6.975
-2 *239:11 *239:13 202.05
-3 *239:13 *239:15 4.5
-4 *239:15 *239:16 91.53
-5 *239:16 *239:18 4.5
-6 *239:18 *239:19 62.91
-7 *239:19 la_data_out[6] 2.115
-*END
-
-*D_NET *240 0.261909
-*CONN
-*P la_data_out[7] O
-*I *419:la_data_out[7] O *D user_proj_example
-*CAP
-1 la_data_out[7] 0.00319092
-2 *419:la_data_out[7] 0.0137089
-3 *240:8 0.00871082
-4 *240:7 0.00551991
-5 *240:5 0.0137089
-6 *240:5 *419:la_oenb[7] 0.000403929
-7 *240:5 *401:11 0.000695592
-8 *240:8 *243:16 0.00293436
-9 *419:la_data_in[7] *240:5 0
-10 *419:la_data_in[8] *240:5 0
-11 *122:16 *240:8 0.000621697
-12 *123:16 *240:8 0.0522846
-13 *177:11 *240:5 0.160129
-*RES
-1 *419:la_data_out[7] *240:5 243.405
-2 *240:5 *240:7 4.5
-3 *240:7 *240:8 99.63
-4 *240:8 la_data_out[7] 32.265
-*END
-
-*D_NET *241 0.239274
-*CONN
-*P la_data_out[8] O
-*I *419:la_data_out[8] O *D user_proj_example
-*CAP
-1 la_data_out[8] 0.00010579
-2 *419:la_data_out[8] 0.000561158
-3 *241:17 0.00517772
-4 *241:16 0.00507193
-5 *241:14 0.0101926
-6 *241:13 0.0101926
-7 *241:11 0.0110611
-8 *241:9 0.0116223
-9 *241:9 *419:la_oenb[8] 0.00144233
-10 *241:9 *305:11 5.52382e-05
-11 *241:11 *305:11 0.135333
-12 *241:17 *284:11 0.0278032
-13 *419:la_data_in[9] *241:9 7.60804e-05
-14 *419:la_data_in[9] *241:11 0
-15 *208:14 *241:14 0.0205782
-*RES
-1 *419:la_data_out[8] *241:9 8.505
-2 *241:9 *241:11 198.45
-3 *241:11 *241:13 4.5
-4 *241:13 *241:14 105.39
-5 *241:14 *241:16 4.5
-6 *241:16 *241:17 65.79
-7 *241:17 la_data_out[8] 1.395
-*END
-
-*D_NET *242 0.257181
-*CONN
-*P la_data_out[9] O
-*I *419:la_data_out[9] O *D user_proj_example
-*CAP
-1 la_data_out[9] 0.00405805
-2 *419:la_data_out[9] 0.000822328
-3 *242:16 0.0116317
-4 *242:15 0.00757369
-5 *242:13 0.00900543
-6 *242:11 0.00982776
-7 *242:11 *419:la_oenb[9] 0.0026412
-8 *242:13 *419:la_oenb[9] 1.79013e-05
-9 *242:13 *265:11 0.00759218
-10 *242:13 *306:11 0.151905
-11 *419:la_data_in[9] *242:11 0
-12 *419:la_data_in[9] *242:13 0
-13 *107:10 *242:16 0
-14 *115:8 *242:16 0.0185885
-15 *141:16 *242:16 0.0335095
-16 *178:11 la_data_out[9] 7.67196e-06
-*RES
-1 *419:la_data_out[9] *242:11 13.095
-2 *242:11 *242:13 222.93
-3 *242:13 *242:15 4.5
-4 *242:15 *242:16 110.61
-5 *242:16 la_data_out[9] 43.245
-*END
-
-*D_NET *243 0.314811
-*CONN
-*P la_oenb[0] I
-*I *419:la_oenb[0] I *D user_proj_example
-*CAP
-1 la_oenb[0] 0.00311348
-2 *419:la_oenb[0] 0.000760027
-3 *243:19 0.00469748
-4 *243:18 0.00393745
-5 *243:16 0.00417767
-6 *243:15 0.00729115
-7 *243:19 *335:11 0.00154667
-8 *419:la_data_in[1] *419:la_oenb[0] 0.00111883
-9 *122:16 *243:16 0.0112527
-10 *126:11 *419:la_oenb[0] 0.000386667
-11 *126:11 *243:19 0.154605
-12 *179:17 *419:la_oenb[0] 0.00231387
-13 *179:17 *243:19 0.00337567
-14 *179:21 *243:19 0.1133
-15 *190:7 *419:la_oenb[0] 0
-16 *240:8 *243:16 0.00293436
-*RES
-1 la_oenb[0] *243:15 34.245
-2 *243:15 *243:16 56.61
-3 *243:16 *243:18 4.5
-4 *243:18 *243:19 226.71
-5 *243:19 *419:la_oenb[0] 17.505
-*END
-
-*D_NET *244 0.261803
-*CONN
-*P la_oenb[10] I
-*I *419:la_oenb[10] I *D user_proj_example
-*CAP
-1 la_oenb[10] 0.00488603
-2 *419:la_oenb[10] 0.00179682
-3 *244:19 0.0128521
-4 *244:18 0.0110552
-5 *244:16 0.00747962
-6 *244:15 0.0123656
-7 *244:16 *370:14 2.07232e-05
-8 *419:la_data_in[11] *419:la_oenb[10] 0.000655953
-9 *124:16 *244:16 0.0706867
-10 *180:7 *419:la_oenb[10] 0.00144233
-11 *180:9 *419:la_oenb[10] 0.00341249
-12 *180:9 *244:19 0.135149
-*RES
-1 la_oenb[10] *244:15 47.565
-2 *244:15 *244:16 121.23
-3 *244:16 *244:18 4.5
-4 *244:18 *244:19 198.18
-5 *244:19 *419:la_oenb[10] 32.535
-*END
-
-*D_NET *245 0.259262
-*CONN
-*P la_oenb[11] I
-*I *419:la_oenb[11] I *D user_proj_example
-*CAP
-1 la_oenb[11] 0.00433682
-2 *419:la_oenb[11] 0.00219515
-3 *245:19 0.0134042
-4 *245:18 0.0112091
-5 *245:16 0.00822103
-6 *245:15 0.0125579
-7 *419:la_data_in[12] *419:la_oenb[11] 0
-8 *118:13 *245:15 1.87963e-05
-9 *130:16 *245:16 0.0672049
-10 *181:7 *419:la_oenb[11] 0.00312377
-11 *181:7 *245:19 0.136991
-*RES
-1 la_oenb[11] *245:15 45.945
-2 *245:15 *245:16 126.81
-3 *245:16 *245:18 4.5
-4 *245:18 *245:19 200.88
-5 *245:19 *419:la_oenb[11] 32.715
-*END
-
-*D_NET *246 0.181347
-*CONN
-*P la_oenb[12] I
-*I *419:la_oenb[12] I *D user_proj_example
-*CAP
-1 la_oenb[12] 0.00101531
-2 *419:la_oenb[12] 0.000199423
-3 *246:16 0.00102936
-4 *246:11 0.0222134
-5 *246:10 0.0213835
-6 *246:8 0.00615912
-7 *246:7 0.00717443
-8 *246:8 *264:8 0.0617286
-9 *246:8 *265:8 0.00304577
-10 *246:8 *305:8 0.00055949
-11 *246:11 *419:la_oenb[26] 0.00255732
-12 *246:11 *261:11 0.00787144
-13 *246:11 *262:17 0
-14 *246:16 *419:la_oenb[22] 0.00752188
-15 *246:16 *419:la_oenb[3] 0.00124339
-16 *246:16 *419:la_oenb[7] 0.00938764
-17 *246:16 *248:24 0.0224426
-18 la_data_out[2] *246:11 0
-19 *419:la_data_in[12] *419:la_oenb[12] 0
-20 *419:la_data_in[13] *419:la_oenb[12] 0.00123774
-21 *419:la_data_in[27] *246:11 0.00132981
-22 *134:11 *246:11 0
-23 *182:10 *419:la_oenb[12] 0.00039012
-24 *182:10 *246:16 0.00186509
-25 *193:10 *246:16 6.99409e-05
-26 *197:17 *246:11 0.000921915
-27 *198:11 *246:11 0
-*RES
-1 la_oenb[12] *246:7 13.725
-2 *246:7 *246:8 96.21
-3 *246:8 *246:10 4.5
-4 *246:10 *246:11 256.59
-5 *246:11 *246:16 46.89
-6 *246:16 *419:la_oenb[12] 5.445
-*END
-
-*D_NET *247 0.284607
-*CONN
-*P la_oenb[13] I
-*I *419:la_oenb[13] I *D user_proj_example
-*CAP
-1 la_oenb[13] 0.0037109
-2 *419:la_oenb[13] 0.000813343
-3 *247:19 0.0115491
-4 *247:18 0.0107357
-5 *247:16 0.00542109
-6 *247:15 0.00913199
-7 *247:16 *254:16 0.00613407
-8 *419:la_data_in[13] *419:la_oenb[13] 0
-9 *419:la_data_in[14] *419:la_oenb[13] 0.000483334
-10 *107:10 *247:16 0.00483367
-11 *118:19 *419:la_oenb[13] 0.00343704
-12 *118:19 *247:19 0.00228241
-13 *131:16 *247:16 0.0782711
-14 *183:5 *419:la_oenb[13] 0.00712982
-15 *183:5 *247:19 0.140673
-*RES
-1 la_oenb[13] *247:15 40.005
-2 *247:15 *247:16 139.95
-3 *247:16 *247:18 4.5
-4 *247:18 *247:19 206.28
-5 *247:19 *419:la_oenb[13] 32.355
-*END
-
-*D_NET *248 0.155561
-*CONN
-*P la_oenb[14] I
-*I *419:la_oenb[14] I *D user_proj_example
-*CAP
-1 la_oenb[14] 0.000291782
-2 *419:la_oenb[14] 0.000406377
-3 *248:24 0.00220361
-4 *248:19 0.0195443
-5 *248:18 0.017747
-6 *248:16 0.00733989
-7 *248:15 0.00733989
-8 *248:13 0.00559122
-9 *248:11 0.005883
-10 *248:19 *266:19 0
-11 *248:24 *419:la_oenb[17] 0.000186509
-12 *248:24 *419:la_oenb[20] 0.000186509
-13 *248:24 *419:la_oenb[22] 0.00186509
-14 *248:24 *419:la_oenb[3] 0.00192726
-15 la_data_out[14] *248:13 2.5829e-05
-16 *419:la_data_in[15] *419:la_oenb[14] 0.000431548
-17 *419:la_data_in[16] *248:24 3.62657e-05
-18 *419:la_data_in[30] *248:19 0.00589207
-19 *107:7 *248:13 0
-20 *133:26 *248:24 0.00690085
-21 *138:11 *248:19 0.00648434
-22 *155:16 *248:16 0.0428347
-23 *184:7 *419:la_oenb[14] 0
-24 *246:16 *248:24 0.0224426
-*RES
-1 la_oenb[14] *248:11 3.015
-2 *248:11 *248:13 49.59
-3 *248:13 *248:15 4.5
-4 *248:15 *248:16 104.13
-5 *248:16 *248:18 4.5
-6 *248:18 *248:19 216.09
-7 *248:19 *248:24 49.59
-8 *248:24 *419:la_oenb[14] 5.625
-*END
-
-*D_NET *249 0.142973
-*CONN
-*P la_oenb[15] I
-*I *419:la_oenb[15] I *D user_proj_example
-*CAP
-1 la_oenb[15] 0.00010579
-2 *419:la_oenb[15] 0.000615613
-3 *249:16 0.0143431
-4 *249:15 0.0137275
-5 *249:13 0.0256388
-6 *249:11 0.0257445
-7 *419:la_oenb[15] *276:19 0.0021236
-8 *249:13 *290:11 0
-9 *419:la_data_in[16] *419:la_oenb[15] 0.000441905
-10 *151:16 *249:16 0.056752
-11 *185:7 *419:la_oenb[15] 0.00144233
-12 *185:9 *419:la_oenb[15] 0.00203767
-*RES
-1 la_oenb[15] *249:11 1.395
-2 *249:11 *249:13 249.93
-3 *249:13 *249:15 4.5
-4 *249:15 *249:16 153.27
-5 *249:16 *419:la_oenb[15] 26.415
-*END
-
-*D_NET *250 0.0932115
-*CONN
-*P la_oenb[16] I
-*I *419:la_oenb[16] I *D user_proj_example
-*CAP
-1 la_oenb[16] 0.000218295
-2 *419:la_oenb[16] 0.00165005
-3 *250:19 0.00476849
-4 *250:18 0.00311844
-5 *250:16 0.0153844
-6 *250:15 0.0153844
-7 *250:13 0.0192678
-8 *250:11 0.0194861
-9 *250:19 *373:13 2.04586e-05
-10 *419:la_data_in[16] *419:la_oenb[16] 0
-11 *419:la_data_in[17] *419:la_oenb[16] 0.000918335
-12 *123:15 *250:11 1.87963e-05
-13 *123:19 *419:la_oenb[16] 0.000751853
-14 *123:19 *250:19 0.0068127
-15 *186:7 *419:la_oenb[16] 0.0054113
-*RES
-1 la_oenb[16] *250:11 2.475
-2 *250:11 *250:13 189.81
-3 *250:13 *250:15 4.5
-4 *250:15 *250:16 158.85
-5 *250:16 *250:18 4.5
-6 *250:18 *250:19 50.04
-7 *250:19 *419:la_oenb[16] 32.355
-*END
-
-*D_NET *251 0.392735
-*CONN
-*P la_oenb[17] I
-*I *419:la_oenb[17] I *D user_proj_example
-*CAP
-1 la_oenb[17] 0.000388948
-2 *419:la_oenb[17] 0.000309168
-3 *251:11 0.015399
-4 *251:10 0.0150898
-5 *251:8 0.00555972
-6 *251:7 0.00594866
-7 *419:la_data_in[17] *419:la_oenb[17] 0
-8 *419:la_data_in[17] *251:11 0.000199471
-9 *419:la_data_in[18] *419:la_oenb[17] 0.00117074
-10 *117:8 *251:8 0.0735462
-11 *134:8 *251:8 0.0990357
-12 *187:11 *419:la_oenb[17] 0.00332452
-13 *187:11 *251:11 4.91006e-05
-14 *187:13 *251:11 0.172527
-15 *248:24 *419:la_oenb[17] 0.000186509
-*RES
-1 la_oenb[17] *251:7 8.145
-2 *251:7 *251:8 167.67
-3 *251:8 *251:10 4.5
-4 *251:10 *251:11 261.45
-5 *251:11 *419:la_oenb[17] 16.695
-*END
-
-*D_NET *252 0.18696
-*CONN
-*P la_oenb[18] I
-*I *419:la_oenb[18] I *D user_proj_example
-*CAP
-1 la_oenb[18] 0.000166523
-2 *419:la_oenb[18] 0.000568329
-3 *252:26 0.00101885
-4 *252:16 0.0105306
-5 *252:15 0.0100801
-6 *252:13 0.0232026
-7 *252:11 0.0233691
-8 *419:la_data_in[18] *419:la_oenb[18] 0
-9 *419:la_data_in[19] *419:la_oenb[18] 0.000614525
-10 *39:10 *252:16 0.00786962
-11 *125:19 *252:26 0.0206836
-12 *188:7 *419:la_oenb[18] 0.00277214
-13 *188:9 *419:la_oenb[18] 0.000184127
-14 *188:9 *252:26 0.0206836
-15 *220:14 *252:16 0.0652158
-*RES
-1 la_oenb[18] *252:11 1.935
-2 *252:11 *252:13 228.33
-3 *252:13 *252:15 4.5
-4 *252:15 *252:16 172.53
-5 *252:16 *252:26 44.55
-6 *252:26 *419:la_oenb[18] 13.095
-*END
-
-*D_NET *253 0.191539
-*CONN
-*P la_oenb[19] I
-*I *419:la_oenb[19] I *D user_proj_example
-*CAP
-1 la_oenb[19] 0.000291157
-2 *419:la_oenb[19] 0.00132496
-3 *253:16 0.0119674
-4 *253:15 0.0106424
-5 *253:13 0.0250337
-6 *253:11 0.0253249
-7 la_data_out[19] *253:13 2.5829e-05
-8 *419:la_data_in[19] *419:la_oenb[19] 0
-9 *419:la_data_in[20] *419:la_oenb[19] 0.000918335
-10 *88:12 *253:13 0
-11 *162:16 *253:16 0
-12 *173:16 *253:16 0
-13 *189:7 *419:la_oenb[19] 0.00144233
-14 *189:9 *419:la_oenb[19] 0.00272508
-15 *196:12 *253:16 0.111843
-*RES
-1 la_oenb[19] *253:11 3.015
-2 *253:11 *253:13 244.89
-3 *253:13 *253:15 4.5
-4 *253:15 *253:16 177.57
-5 *253:16 *419:la_oenb[19] 31.455
-*END
-
-*D_NET *254 0.197297
-*CONN
-*P la_oenb[1] I
-*I *419:la_oenb[1] I *D user_proj_example
-*CAP
-1 la_oenb[1] 0.00372571
-2 *419:la_oenb[1] 0.00236403
-3 *254:19 0.0138834
-4 *254:18 0.0115193
-5 *254:16 0.00504569
-6 *254:15 0.00877139
-7 la_data_out[1] *254:15 0
-8 *419:la_data_in[2] *419:la_oenb[1] 0
-9 *107:10 *254:16 0
-10 *131:16 *254:16 0.00180292
-11 *137:13 *254:15 7.67196e-06
-12 *190:7 *419:la_oenb[1] 0.00312377
-13 *190:7 *254:19 0.140919
-14 *247:16 *254:16 0.00613407
-*RES
-1 la_oenb[1] *254:15 40.185
-2 *254:15 *254:16 62.01
-3 *254:16 *254:18 4.5
-4 *254:18 *254:19 206.64
-5 *254:19 *419:la_oenb[1] 32.715
-*END
-
-*D_NET *255 0.342102
-*CONN
-*P la_oenb[20] I
-*I *419:la_oenb[20] I *D user_proj_example
-*CAP
-1 la_oenb[20] 0.000673267
-2 *419:la_oenb[20] 0.000301165
-3 *255:11 0.0150767
-4 *255:10 0.0147756
-5 *255:8 0.0100876
-6 *255:7 0.0107608
-7 *255:8 *289:8 0.000783338
-8 *255:8 *292:8 0.00186502
-9 *255:8 *295:8 0.0602419
-10 *255:8 *306:8 0.0594961
-11 la_data_out[0] *255:11 0.00336339
-12 *419:la_data_in[20] *419:la_oenb[20] 0
-13 *419:la_data_in[20] *255:11 0.000199471
-14 *419:la_data_in[21] *419:la_oenb[20] 0.00127968
-15 *191:11 *419:la_oenb[20] 0.00332452
-16 *191:11 *255:11 4.91006e-05
-17 *191:13 *255:11 0.159638
-18 *248:24 *419:la_oenb[20] 0.000186509
-*RES
-1 la_oenb[20] *255:7 10.485
-2 *255:7 *255:8 187.11
-3 *255:8 *255:10 4.5
-4 *255:10 *255:11 259.11
-5 *255:11 *419:la_oenb[20] 16.695
-*END
-
-*D_NET *256 0.156739
-*CONN
-*P la_oenb[21] I
-*I *419:la_oenb[21] I *D user_proj_example
-*CAP
-1 la_oenb[21] 0.000218295
-2 *419:la_oenb[21] 0.0018232
-3 *256:21 0.00267924
-4 *256:16 0.0147497
-5 *256:15 0.0138937
-6 *256:13 0.0228634
-7 *256:11 0.0230817
-8 *256:16 *291:16 0.0551445
-9 *419:la_data_in[21] *419:la_oenb[21] 0
-10 *419:la_data_in[22] *419:la_oenb[21] 0.000504048
-11 *99:11 *256:13 0
-12 *108:11 *256:13 0
-13 *129:13 *256:11 1.87963e-05
-14 *192:7 *419:la_oenb[21] 0.00144233
-15 *192:9 *419:la_oenb[21] 0.00341249
-16 *192:9 *256:21 0.00982012
-17 *225:14 *256:16 0.00708727
-*RES
-1 la_oenb[21] *256:11 2.475
-2 *256:11 *256:13 225.45
-3 *256:13 *256:15 4.5
-4 *256:15 *256:16 191.43
-5 *256:16 *256:21 19.35
-6 *256:21 *419:la_oenb[21] 32.085
-*END
-
-*D_NET *257 0.104856
-*CONN
-*P la_oenb[22] I
-*I *419:la_oenb[22] I *D user_proj_example
-*CAP
-1 la_oenb[22] 0.00334189
-2 *419:la_oenb[22] 0.00097066
-3 *257:15 0.0109377
-4 *257:14 0.00996706
-5 *257:12 0.0165047
-6 *257:11 0.0165047
-7 *257:9 0.0126549
-8 *257:7 0.0159967
-9 *257:15 *419:la_oenb[31] 0.000797884
-10 *257:15 *267:19 0
-11 *257:15 *268:11 0
-12 *419:la_data_in[23] *419:la_oenb[22] 0.00119683
-13 *419:la_data_in[32] *257:15 0.00255732
-14 *99:14 *257:12 0
-15 *133:26 *419:la_oenb[22] 0.000746036
-16 *193:10 *419:la_oenb[22] 0.000756647
-17 *193:12 *419:la_oenb[22] 0
-18 *195:10 *419:la_oenb[22] 0.00173162
-19 *203:15 *257:15 0.000804022
-20 *246:16 *419:la_oenb[22] 0.00752188
-21 *248:24 *419:la_oenb[22] 0.00186509
-*RES
-1 la_oenb[22] *257:7 32.085
-2 *257:7 *257:9 125.64
-3 *257:9 *257:11 4.5
-4 *257:11 *257:12 174.33
-5 *257:12 *257:14 4.5
-6 *257:14 *257:15 108.63
-7 *257:15 *419:la_oenb[22] 38.655
-*END
-
-*D_NET *258 0.352731
-*CONN
-*P la_oenb[23] I
-*I *419:la_oenb[23] I *D user_proj_example
-*CAP
-1 la_oenb[23] 0.000804702
-2 *419:la_oenb[23] 0.000549266
-3 *258:11 0.0158592
-4 *258:10 0.0153099
-5 *258:8 0.0111204
-6 *258:7 0.0119251
-7 *258:8 *260:8 0.138948
-8 *258:8 *264:8 0
-9 *258:8 *298:8 0.000419646
-10 *258:8 *305:8 0
-11 la_data_out[1] *258:11 0
-12 *419:la_data_in[23] *258:11 0.000699683
-13 *419:la_data_in[24] *419:la_oenb[23] 0.00102932
-14 *126:7 *258:11 0
-15 *131:15 *258:7 0
-16 *131:19 *258:11 0.154728
-17 *194:15 *419:la_oenb[23] 0.00133748
-*RES
-1 la_oenb[23] *258:7 11.925
-2 *258:7 *258:8 206.55
-3 *258:8 *258:10 4.5
-4 *258:10 *258:11 252.81
-5 *258:11 *419:la_oenb[23] 21.6607
-*END
-
-*D_NET *259 0.291161
-*CONN
-*P la_oenb[24] I
-*I *419:la_oenb[24] I *D user_proj_example
-*CAP
-1 la_oenb[24] 0.000291157
-2 *419:la_oenb[24] 0.001253
-3 *259:16 0.00847509
-4 *259:15 0.00722209
-5 *259:13 0.0263692
-6 *259:11 0.0266603
-7 la_data_out[24] *259:13 2.5829e-05
-8 *419:la_data_in[24] *419:la_oenb[24] 0
-9 *419:la_data_in[25] *419:la_oenb[24] 0
-10 *133:16 *259:16 0.0866022
-11 *139:16 *259:16 0.133229
-12 *195:10 *419:la_oenb[24] 0.00103316
-*RES
-1 la_oenb[24] *259:11 3.015
-2 *259:11 *259:13 257.85
-3 *259:13 *259:15 4.5
-4 *259:15 *259:16 209.97
-5 *259:16 *419:la_oenb[24] 18.495
-*END
-
-*D_NET *260 0.479559
-*CONN
-*P la_oenb[25] I
-*I *419:la_oenb[25] I *D user_proj_example
-*CAP
-1 la_oenb[25] 0.000729427
-2 *419:la_oenb[25] 0.001044
-3 *260:11 0.0191253
-4 *260:10 0.0180813
-5 *260:8 0.00344568
-6 *260:7 0.00417511
-7 *260:8 *264:8 0
-8 *260:8 *271:8 0.13298
-9 *260:8 *298:8 0.00271989
-10 *419:la_data_in[25] *419:la_oenb[25] 3.45239e-06
-11 *419:la_data_in[26] *419:la_oenb[25] 0
-12 *137:13 *260:11 0.146627
-13 *196:11 *419:la_oenb[25] 0.00185966
-14 *196:11 *260:11 0.00963588
-15 *197:23 *260:7 0.000184127
-16 *258:8 *260:8 0.138948
-*RES
-1 la_oenb[25] *260:7 11.745
-2 *260:7 *260:8 219.51
-3 *260:8 *260:10 4.5
-4 *260:10 *260:11 251.55
-5 *260:11 *419:la_oenb[25] 23.0615
-*END
-
-*D_NET *261 0.420004
-*CONN
-*P la_oenb[26] I
-*I *419:la_oenb[26] I *D user_proj_example
-*CAP
-1 la_oenb[26] 0.00152228
-2 *419:la_oenb[26] 0.000566526
-3 *261:11 0.0102271
-4 *261:10 0.00966056
-5 *261:8 0.00944163
-6 *261:7 0.0109639
-7 *261:8 *282:8 0.12067
-8 *419:la_data_in[27] *419:la_oenb[26] 0.000537038
-9 *119:8 *261:8 0.0693187
-10 *134:11 *419:la_oenb[26] 0.000414286
-11 *134:11 *261:11 0.163812
-12 *197:17 *419:la_oenb[26] 0.00231387
-13 *197:17 *261:11 0.00210723
-14 *212:12 *261:8 0.0080199
-15 *246:11 *419:la_oenb[26] 0.00255732
-16 *246:11 *261:11 0.00787144
-*RES
-1 la_oenb[26] *261:7 18.945
-2 *261:7 *261:8 225.81
-3 *261:8 *261:10 4.5
-4 *261:10 *261:11 240.21
-5 *261:11 *419:la_oenb[26] 17.865
-*END
-
-*D_NET *262 0.269756
-*CONN
-*P la_oenb[27] I
-*I *419:la_oenb[27] I *D user_proj_example
-*CAP
-1 la_oenb[27] 0.00332303
-2 *419:la_oenb[27] 0.000702498
-3 *262:17 0.00182638
-4 *262:12 0.013671
-5 *262:11 0.0125471
-6 *262:9 0.0186216
-7 *262:7 0.0219447
-8 la_data_out[2] *262:17 0.0128275
-9 *419:la_data_in[27] *419:la_oenb[27] 0
-10 *419:la_data_in[28] *419:la_oenb[27] 0.0015881
-11 *419:la_data_in[28] *262:17 0
-12 *118:16 *262:12 0.0594963
-13 *135:15 *262:17 0.0155894
-14 *198:11 *419:la_oenb[27] 0.00296445
-15 *198:11 *262:17 0.00785609
-16 *236:16 *262:12 0.0967983
-17 *246:11 *262:17 0
-*RES
-1 la_oenb[27] *262:7 32.085
-2 *262:7 *262:9 185.22
-3 *262:9 *262:11 4.5
-4 *262:11 *262:12 231.93
-5 *262:12 *262:17 38.61
-6 *262:17 *419:la_oenb[27] 21.285
-*END
-
-*D_NET *263 0.269365
-*CONN
-*P la_oenb[28] I
-*I *419:la_oenb[28] I *D user_proj_example
-*CAP
-1 la_oenb[28] 0.000166523
-2 *419:la_oenb[28] 0.000736492
-3 *263:21 0.00263866
-4 *263:16 0.014692
-5 *263:15 0.0127898
-6 *263:13 0.0216513
-7 *263:11 0.0218178
-8 *263:16 *266:16 0.16046
-9 *419:la_data_in[29] *419:la_oenb[28] 0.00111883
-10 *136:19 *419:la_oenb[28] 0.000414286
-11 *136:19 *263:21 0.0274349
-12 *199:17 *419:la_oenb[28] 0.00231387
-13 *199:17 *263:21 0.00251641
-14 *199:23 *263:21 0.000613757
-*RES
-1 la_oenb[28] *263:11 1.935
-2 *263:11 *263:13 214.47
-3 *263:13 *263:15 4.5
-4 *263:15 *263:16 237.51
-5 *263:16 *263:21 45.54
-6 *263:21 *419:la_oenb[28] 17.055
-*END
-
-*D_NET *264 0.33917
-*CONN
-*P la_oenb[29] I
-*I *419:la_oenb[29] I *D user_proj_example
-*CAP
-1 la_oenb[29] 0.000966934
-2 *419:la_oenb[29] 0.00124737
-3 *264:11 0.0153057
-4 *264:10 0.0140583
-5 *264:8 0.0182203
-6 *264:7 0.0191872
-7 *264:8 *305:8 0.0363659
-8 *264:8 *310:14 0.0157274
-9 *419:la_data_in[29] *419:la_oenb[29] 0
-10 *419:la_data_in[30] *419:la_oenb[29] 0.0130815
-11 *419:la_data_in[30] *264:11 0.000821668
-12 *138:11 *264:11 0.137236
-13 *148:9 *264:11 0.00464001
-14 *200:7 *419:la_oenb[29] 0.00058307
-15 *246:8 *264:8 0.0617286
-16 *258:8 *264:8 0
-17 *260:8 *264:8 0
-*RES
-1 la_oenb[29] *264:7 13.545
-2 *264:7 *264:8 245.43
-3 *264:8 *264:10 4.5
-4 *264:10 *264:11 241.56
-5 *264:11 *419:la_oenb[29] 22.095
-*END
-
-*D_NET *265 0.116989
-*CONN
-*P la_oenb[2] I
-*I *419:la_oenb[2] I *D user_proj_example
-*CAP
-1 la_oenb[2] 0.000990251
-2 *419:la_oenb[2] 0.00107028
-3 *265:11 0.0231172
-4 *265:10 0.0220469
-5 *265:8 0.00308448
-6 *265:7 0.00407473
-7 *419:la_oenb[2] *419:la_oenb[3] 0.00153352
-8 *419:la_oenb[2] *419:la_oenb[7] 0.00379236
-9 *419:la_oenb[2] *401:10 0.00851682
-10 *265:8 *305:8 0.0347489
-11 *265:11 *419:la_oenb[9] 0.00161623
-12 *265:11 *306:11 0
-13 *419:la_data_in[10] *265:11 0.000103572
-14 *419:la_data_in[3] *419:la_oenb[2] 0.00123774
-15 *117:11 *265:11 0
-16 *180:9 *265:11 0
-17 *201:11 *419:la_oenb[2] 0.000417739
-18 *242:13 *265:11 0.00759218
-19 *246:8 *265:8 0.00304577
-*RES
-1 la_oenb[2] *265:7 13.545
-2 *265:7 *265:8 50.31
-3 *265:8 *265:10 4.5
-4 *265:10 *265:11 256.77
-5 *265:11 *419:la_oenb[2] 33.435
-*END
-
-*D_NET *266 0.387232
-*CONN
-*P la_oenb[30] I
-*I *419:la_oenb[30] I *D user_proj_example
-*CAP
-1 la_oenb[30] 0.00010579
-2 *419:la_oenb[30] 0.00039485
-3 *266:19 0.00430625
-4 *266:18 0.0039114
-5 *266:16 0.00483386
-6 *266:15 0.00483386
-7 *266:13 0.0216084
-8 *266:11 0.0217142
-9 *266:16 *278:16 0.153
-10 *419:la_data_in[31] *419:la_oenb[30] 0.000447532
-11 *132:8 *419:la_oenb[30] 0.000136773
-12 *195:13 *419:la_oenb[30] 0.00153439
-13 *202:15 *419:la_oenb[30] 0.0023957
-14 *202:15 *266:19 0.00754921
-15 *248:19 *266:19 0
-16 *263:16 *266:16 0.16046
-*RES
-1 la_oenb[30] *266:11 1.395
-2 *266:11 *266:13 214.29
-3 *266:13 *266:15 4.5
-4 *266:15 *266:16 251.19
-5 *266:16 *266:18 4.5
-6 *266:18 *266:19 45.81
-7 *266:19 *419:la_oenb[30] 21.645
-*END
-
-*D_NET *267 0.124386
-*CONN
-*P la_oenb[31] I
-*I *419:la_oenb[31] I *D user_proj_example
-*CAP
-1 la_oenb[31] 0.000218295
-2 *419:la_oenb[31] 0.000460428
-3 *267:19 0.0170763
-4 *267:18 0.0166159
-5 *267:16 0.0242796
-6 *267:15 0.0242796
-7 *267:13 0.00862731
-8 *267:11 0.00884561
-9 *419:la_data_in[31] *419:la_oenb[31] 0
-10 *419:la_data_in[31] *267:19 8.28572e-05
-11 *419:la_data_in[32] *419:la_oenb[31] 0.000400477
-12 *140:13 *267:11 1.87963e-05
-13 *195:13 *267:19 0
-14 *203:15 *419:la_oenb[31] 0.00666336
-15 *203:15 *267:19 0.0160191
-16 *257:15 *419:la_oenb[31] 0.000797884
-17 *257:15 *267:19 0
-*RES
-1 la_oenb[31] *267:11 2.475
-2 *267:11 *267:13 84.51
-3 *267:13 *267:15 4.5
-4 *267:15 *267:16 256.59
-5 *267:16 *267:18 4.5
-6 *267:18 *267:19 175.59
-7 *267:19 *419:la_oenb[31] 21.9307
-*END
-
-*D_NET *268 0.396907
-*CONN
-*P la_oenb[32] I
-*I *419:la_oenb[32] I *D user_proj_example
-*CAP
-1 la_oenb[32] 0.00177507
-2 *419:la_oenb[32] 0.000352449
-3 *268:11 0.014949
-4 *268:10 0.0145966
-5 *268:8 0.0145489
-6 *268:7 0.0163239
-7 *268:8 *300:14 0.128877
-8 *419:la_data_in[32] *268:11 0.000181058
-9 *419:la_data_in[33] *419:la_oenb[32] 0.00254709
-10 *132:8 *419:la_oenb[32] 0.000186509
-11 *141:19 *268:11 0.152887
-12 *176:8 *268:8 0.0202052
-13 *177:8 *268:8 0.0265464
-14 *204:9 *419:la_oenb[32] 0.00254709
-15 *205:11 *268:7 0.000383598
-16 *257:15 *268:11 0
-*RES
-1 la_oenb[32] *268:7 21.645
-2 *268:7 *268:8 264.87
-3 *268:8 *268:10 4.5
-4 *268:10 *268:11 242.91
-5 *268:11 *419:la_oenb[32] 21.555
-*END
-
-*D_NET *269 0.402658
-*CONN
-*P la_oenb[33] I
-*I *419:la_oenb[33] I *D user_proj_example
-*CAP
-1 la_oenb[33] 0.000166523
-2 *419:la_oenb[33] 0.000329373
-3 *269:24 0.00236862
-4 *269:16 0.00663301
-5 *269:15 0.00459377
-6 *269:13 0.0244923
-7 *269:11 0.0246589
-8 *269:24 *419:la_oenb[37] 0.00337566
-9 *269:24 *274:11 0
-10 la_data_out[33] *269:13 0
-11 *419:la_data_in[34] *419:la_oenb[33] 0.000403929
-12 *419:la_data_in[38] *269:24 2.07143e-05
-13 *133:26 *269:24 0.000124339
-14 *142:22 *269:24 0.00230028
-15 *147:19 *269:24 0
-16 *164:16 *269:16 0.149269
-17 *178:16 *269:16 0.0215729
-18 *193:12 *269:24 0
-19 *202:16 *269:16 0.157724
-20 *205:7 *419:la_oenb[33] 0.000210596
-21 *207:10 *269:24 0.00441406
-22 *210:13 *269:24 0
-*RES
-1 la_oenb[33] *269:11 1.935
-2 *269:11 *269:13 241.29
-3 *269:13 *269:15 4.5
-4 *269:15 *269:16 258.03
-5 *269:16 *269:24 49.14
-6 *269:24 *419:la_oenb[33] 5.265
-*END
-
-*D_NET *270 0.291203
-*CONN
-*P la_oenb[34] I
-*I *419:la_oenb[34] I *D user_proj_example
-*CAP
-1 la_oenb[34] 0.00233542
-2 *419:la_oenb[34] 0.000368571
-3 *270:19 0.0152515
-4 *270:18 0.0148829
-5 *270:16 0.0225746
-6 *270:15 0.02491
-7 *270:19 *287:15 0.000306879
-8 la_data_out[34] *270:15 2.5829e-05
-9 *419:la_data_in[35] *419:la_oenb[34] 0.00254709
-10 *120:16 *270:16 0.0597446
-11 *132:8 *419:la_oenb[34] 0.000186509
-12 *143:11 *270:19 0.145522
-13 *206:9 *419:la_oenb[34] 0.00254709
-*RES
-1 la_oenb[34] *270:15 27.225
-2 *270:15 *270:16 275.49
-3 *270:16 *270:18 4.5
-4 *270:18 *270:19 240.39
-5 *270:19 *419:la_oenb[34] 21.555
-*END
-
-*D_NET *271 0.395395
-*CONN
-*P la_oenb[35] I
-*I *419:la_oenb[35] I *D user_proj_example
-*CAP
-1 la_oenb[35] 0.000751504
-2 *419:la_oenb[35] 0.00403545
-3 *271:11 0.0268337
-4 *271:10 0.0227982
-5 *271:8 0.00708574
-6 *271:7 0.00783724
-7 *271:8 *274:8 0.190798
-8 *271:8 *298:8 0.00111905
-9 *271:8 *310:14 0
-10 *419:la_data_in[35] *419:la_oenb[35] 0
-11 *419:la_data_in[36] *419:la_oenb[35] 0
-12 *207:10 *419:la_oenb[35] 0.00115591
-13 *260:8 *271:8 0.13298
-*RES
-1 la_oenb[35] *271:7 11.565
-2 *271:7 *271:8 284.31
-3 *271:8 *271:10 4.5
-4 *271:10 *271:11 224.64
-5 *271:11 *419:la_oenb[35] 40.995
-*END
-
-*D_NET *272 0.401576
-*CONN
-*P la_oenb[36] I
-*I *419:la_oenb[36] I *D user_proj_example
-*CAP
-1 la_oenb[36] 0.00276732
-2 *419:la_oenb[36] 0.000354746
-3 *272:19 0.0161455
-4 *272:18 0.0157908
-5 *272:16 0.0144632
-6 *272:15 0.0172305
-7 *272:16 *286:16 0.153994
-8 *419:la_data_in[37] *419:la_oenb[36] 0.00254709
-9 *132:8 *419:la_oenb[36] 0.000186509
-10 *145:13 *272:15 1.87963e-05
-11 *184:10 *272:16 0.0578795
-12 *208:9 *419:la_oenb[36] 0.00254709
-13 *208:9 *272:19 0.002175
-14 *208:11 *272:19 0.1133
-15 *234:14 *272:16 0.00217594
-*RES
-1 la_oenb[36] *272:15 29.565
-2 *272:15 *272:16 288.99
-3 *272:16 *272:18 4.5
-4 *272:18 *272:19 237.51
-5 *272:19 *419:la_oenb[36] 21.555
-*END
-
-*D_NET *273 0.20035
-*CONN
-*P la_oenb[37] I
-*I *419:la_oenb[37] I *D user_proj_example
-*CAP
-1 la_oenb[37] 0.00313757
-2 *419:la_oenb[37] 0.00183898
-3 *273:11 0.0221776
-4 *273:10 0.0203386
-5 *273:8 0.0223954
-6 *273:7 0.025533
-7 *419:la_data_in[37] *419:la_oenb[37] 0
-8 *419:la_data_in[38] *419:la_oenb[37] 0
-9 *191:16 *273:8 0.0954299
-10 *208:9 *273:11 0
-11 *209:11 *419:la_oenb[37] 0.00612325
-12 *269:24 *419:la_oenb[37] 0.00337566
-*RES
-1 la_oenb[37] *273:7 34.965
-2 *273:7 *273:8 297.27
-3 *273:8 *273:10 4.5
-4 *273:10 *273:11 201.24
-5 *273:11 *419:la_oenb[37] 40.995
-*END
-
-*D_NET *274 0.589318
-*CONN
-*P la_oenb[38] I
-*I *419:la_oenb[38] I *D user_proj_example
-*CAP
-1 la_oenb[38] 0.000724101
-2 *419:la_oenb[38] 0.00134881
-3 *274:11 0.0170946
-4 *274:10 0.0157458
-5 *274:8 0.00456685
-6 *274:7 0.00529095
-7 *274:8 *275:8 0.207957
-8 *274:8 *298:8 0.000186509
-9 *274:8 *303:8 0.000261113
-10 *419:la_data_in[39] *419:la_oenb[38] 0.000876906
-11 *147:13 *274:7 0
-12 *147:19 *274:11 0.132633
-13 *158:13 *274:7 2.04586e-05
-14 *210:13 *419:la_oenb[38] 0.0118148
-15 *269:24 *274:11 0
-16 *271:8 *274:8 0.190798
-*RES
-1 la_oenb[38] *274:7 11.385
-2 *274:7 *274:8 303.75
-3 *274:8 *274:10 4.5
-4 *274:10 *274:11 239.67
-5 *274:11 *419:la_oenb[38] 35.3015
-*END
-
-*D_NET *275 0.525633
-*CONN
-*P la_oenb[39] I
-*I *419:la_oenb[39] I *D user_proj_example
-*CAP
-1 la_oenb[39] 0.000704132
-2 *419:la_oenb[39] 0.000354746
-3 *275:11 0.0218169
-4 *275:10 0.0214622
-5 *275:8 0.00368224
-6 *275:7 0.00438637
-7 *275:8 *289:8 0.191917
-8 *275:8 *303:8 0.00167858
-9 *275:8 *306:8 0.00346902
-10 *419:la_data_in[39] *275:11 9.20636e-06
-11 *419:la_data_in[40] *419:la_oenb[39] 0.00254709
-12 *132:8 *419:la_oenb[39] 0.000186509
-13 *158:8 *275:8 0.00615481
-14 *175:13 *275:11 0.0549313
-15 *211:9 *419:la_oenb[39] 0.00254709
-16 *211:9 *275:11 0.00182976
-17 *274:8 *275:8 0.207957
-*RES
-1 la_oenb[39] *275:7 11.205
-2 *275:7 *275:8 310.23
-3 *275:8 *275:10 4.5
-4 *275:10 *275:11 253.35
-5 *275:11 *419:la_oenb[39] 21.555
-*END
-
-*D_NET *276 0.108617
-*CONN
-*P la_oenb[3] I
-*I *419:la_oenb[3] I *D user_proj_example
-*CAP
-1 la_oenb[3] 0.00261964
-2 *419:la_oenb[3] 0.00180851
-3 *276:19 0.02241
-4 *276:18 0.0228955
-5 *276:15 0.00491363
-6 *419:la_oenb[3] *419:la_oenb[7] 0.00110662
-7 *419:la_oenb[3] *419:la_oenb[8] 0.000186509
-8 *419:la_oenb[3] *401:10 0.00665184
-9 *276:19 *373:13 0
-10 la_data_out[3] *276:15 0
-11 *419:la_data_in[10] *419:la_oenb[3] 0.000419646
-12 *419:la_data_in[12] *419:la_oenb[3] 0.000634086
-13 *419:la_data_in[16] *419:la_oenb[3] 0.000186509
-14 *419:la_data_in[16] *276:19 0.00014321
-15 *419:la_data_in[4] *419:la_oenb[3] 0.00131958
-16 *419:la_oenb[15] *276:19 0.0021236
-17 *419:la_oenb[2] *419:la_oenb[3] 0.00153352
-18 *122:19 *276:19 0
-19 *123:19 *276:19 0
-20 *184:10 *276:18 0.0290331
-21 *185:9 *276:19 0.00701524
-22 *186:7 *276:19 0
-23 *212:7 *419:la_oenb[3] 0.000445358
-24 *246:16 *419:la_oenb[3] 0.00124339
-25 *248:24 *419:la_oenb[3] 0.00192726
-*RES
-1 la_oenb[3] *276:15 29.385
-2 *276:15 *276:18 46.53
-3 *276:18 *276:19 242.55
-4 *276:19 *419:la_oenb[3] 47.295
-*END
-
-*D_NET *277 0.138476
-*CONN
-*P la_oenb[40] I
-*I *419:la_oenb[40] I *D user_proj_example
-*CAP
-1 la_oenb[40] 0.00010579
-2 *419:la_oenb[40] 0.000597498
-3 *277:19 0.0180327
-4 *277:18 0.0174352
-5 *277:16 0.0297488
-6 *277:15 0.0297488
-7 *277:13 0.00746908
-8 *277:11 0.00757487
-9 *419:la_data_in[40] *419:la_oenb[40] 0
-10 *419:la_data_in[40] *277:19 0.000266984
-11 *419:la_data_in[41] *419:la_oenb[40] 0
-12 *132:8 *419:la_oenb[40] 0.000186509
-13 *207:13 *419:la_oenb[40] 0.000822435
-14 *211:9 *277:19 0
-15 *213:15 *419:la_oenb[40] 0.00666336
-16 *213:15 *277:19 0.0198244
-*RES
-1 la_oenb[40] *277:11 1.395
-2 *277:11 *277:13 73.71
-3 *277:13 *277:15 4.5
-4 *277:15 *277:16 315.99
-5 *277:16 *277:18 4.5
-6 *277:18 *277:19 186.39
-7 *277:19 *419:la_oenb[40] 21.735
-*END
-
-*D_NET *278 0.26147
-*CONN
-*P la_oenb[41] I
-*I *419:la_oenb[41] I *D user_proj_example
-*CAP
-1 la_oenb[41] 0.000218295
-2 *419:la_oenb[41] 0.000354746
-3 *278:19 0.00430649
-4 *278:18 0.00395175
-5 *278:16 0.0210474
-6 *278:15 0.0210474
-7 *278:13 0.0215388
-8 *278:11 0.0217571
-9 *419:la_data_in[42] *419:la_oenb[41] 0.00254709
-10 *132:8 *419:la_oenb[41] 0.000186509
-11 *151:13 *278:11 1.87963e-05
-12 *207:13 *278:19 0
-13 *214:13 *419:la_oenb[41] 0.00254709
-14 *214:13 *278:19 0.00894935
-15 *266:16 *278:16 0.153
-*RES
-1 la_oenb[41] *278:11 2.475
-2 *278:11 *278:13 214.11
-3 *278:13 *278:15 4.5
-4 *278:15 *278:16 321.39
-5 *278:16 *278:18 4.5
-6 *278:18 *278:19 45.99
-7 *278:19 *419:la_oenb[41] 21.555
-*END
-
-*D_NET *279 0.190023
-*CONN
-*P la_oenb[42] I
-*I *419:la_oenb[42] I *D user_proj_example
-*CAP
-1 la_oenb[42] 0.00130956
-2 *419:la_oenb[42] 0.000354746
-3 *279:11 0.0245512
-4 *279:10 0.0241965
-5 *279:8 0.027336
-6 *279:7 0.0286456
-7 *419:la_data_in[42] *279:11 0.00035291
-8 *419:la_data_in[43] *419:la_oenb[42] 0.00254709
-9 *132:8 *419:la_oenb[42] 0.000186509
-10 *187:16 *279:8 0.0672048
-11 *215:13 *419:la_oenb[42] 0.00254709
-12 *215:13 *279:11 0.0107906
-*RES
-1 la_oenb[42] *279:7 16.065
-2 *279:7 *279:8 329.67
-3 *279:8 *279:10 4.5
-4 *279:10 *279:11 248.49
-5 *279:11 *419:la_oenb[42] 21.555
-*END
-
-*D_NET *280 0.134112
-*CONN
-*P la_oenb[43] I
-*I *419:la_oenb[43] I *D user_proj_example
-*CAP
-1 la_oenb[43] 0.000166523
-2 *419:la_oenb[43] 0.000354746
-3 *280:19 0.019261
-4 *280:18 0.0189063
-5 *280:16 0.0315903
-6 *280:15 0.0315903
-7 *280:13 0.00610461
-8 *280:11 0.00627113
-9 *419:la_data_in[43] *280:19 0.000359048
-10 *419:la_data_in[44] *419:la_oenb[43] 0.00254709
-11 *132:8 *419:la_oenb[43] 0.000186509
-12 *216:13 *419:la_oenb[43] 0.00254709
-13 *216:13 *280:19 0.0142277
-*RES
-1 la_oenb[43] *280:11 1.935
-2 *280:11 *280:13 60.21
-3 *280:13 *280:15 4.5
-4 *280:15 *280:16 334.89
-5 *280:16 *280:18 4.5
-6 *280:18 *280:19 199.89
-7 *280:19 *419:la_oenb[43] 21.555
-*END
-
-*D_NET *281 0.481709
-*CONN
-*P la_oenb[44] I
-*I *419:la_oenb[44] I *D user_proj_example
-*CAP
-1 la_oenb[44] 0.000291157
-2 *419:la_oenb[44] 0.00116057
-3 *281:21 0.00334269
-4 *281:16 0.00776877
-5 *281:15 0.00558665
-6 *281:13 0.0238344
-7 *281:11 0.0241256
-8 *419:la_oenb[44] *283:22 0.00341934
-9 la_data_out[44] *281:13 2.5829e-05
-10 *419:la_data_in[38] *419:la_oenb[44] 0
-11 *419:la_data_in[45] *419:la_oenb[44] 0.000224405
-12 *419:la_data_in[50] *281:21 0.000184127
-13 *133:26 *419:la_oenb[44] 0.00187752
-14 *150:16 *419:la_oenb[44] 0
-15 *211:10 *281:16 0.191296
-16 *215:14 *281:16 0.211812
-17 *217:13 *419:la_oenb[44] 0.000348691
-18 *222:11 *281:21 0.00205916
-19 *224:9 *281:21 0
-20 *228:16 *281:16 0.00435188
-*RES
-1 la_oenb[44] *281:11 3.015
-2 *281:11 *281:13 236.07
-3 *281:13 *281:15 4.5
-4 *281:15 *281:16 325.53
-5 *281:16 *281:21 37.89
-6 *281:21 *419:la_oenb[44] 24.435
-*END
-
-*D_NET *282 0.35671
-*CONN
-*P la_oenb[45] I
-*I *419:la_oenb[45] I *D user_proj_example
-*CAP
-1 la_oenb[45] 0.00147528
-2 *419:la_oenb[45] 0.000390713
-3 *282:11 0.016088
-4 *282:10 0.0156973
-5 *282:8 0.0259136
-6 *282:7 0.0273889
-7 *419:la_data_in[46] *419:la_oenb[45] 0.00254709
-8 *146:16 *419:la_oenb[45] 0.000310848
-9 *155:19 *282:11 0.143681
-10 *218:9 *419:la_oenb[45] 0.00254709
-11 *261:8 *282:8 0.12067
-*RES
-1 la_oenb[45] *282:7 18.765
-2 *282:7 *282:8 349.11
-3 *282:8 *282:10 4.5
-4 *282:10 *282:11 245.79
-5 *282:11 *419:la_oenb[45] 21.555
-*END
-
-*D_NET *283 0.50516
-*CONN
-*P la_oenb[46] I
-*I *419:la_oenb[46] I *D user_proj_example
-*CAP
-1 la_oenb[46] 0.000218295
-2 *419:la_oenb[46] 0.000568408
-3 *283:22 0.00371505
-4 *283:16 0.0101576
-5 *283:15 0.00701094
-6 *283:13 0.0235218
-7 *283:11 0.0237401
-8 *419:la_oenb[46] *284:11 2.07143e-05
-9 *283:22 *285:19 0
-10 *419:la_data_in[41] *419:la_oenb[46] 0
-11 *419:la_data_in[47] *419:la_oenb[46] 0.00111499
-12 *419:la_data_in[49] *283:22 0.00497143
-13 *419:la_data_in[50] *283:22 0
-14 *419:la_oenb[44] *283:22 0.00341934
-15 *150:16 *283:22 0
-16 *156:13 *283:11 1.87963e-05
-17 *178:13 *283:22 0
-18 *210:16 *283:16 0.187566
-19 *219:13 *419:la_oenb[46] 0
-20 *220:13 *419:la_oenb[46] 0
-21 *221:17 *283:22 0.000448043
-22 *222:11 *283:22 0
-23 *222:12 *283:16 0.238669
-*RES
-1 la_oenb[46] *283:11 2.475
-2 *283:11 *283:13 233.19
-3 *283:13 *283:15 4.5
-4 *283:15 *283:16 347.13
-5 *283:16 *283:22 45.54
-6 *283:22 *419:la_oenb[46] 11.655
-*END
-
-*D_NET *284 0.368441
-*CONN
-*P la_oenb[47] I
-*I *419:la_oenb[47] I *D user_proj_example
-*CAP
-1 la_oenb[47] 0.00229207
-2 *419:la_oenb[47] 0.000346686
-3 *284:11 0.0213534
-4 *284:10 0.0210067
-5 *284:8 0.0208198
-6 *284:7 0.0231119
-7 *284:8 *290:8 0.204476
-8 *419:la_data_in[48] *419:la_oenb[47] 0.00144233
-9 *419:la_oenb[46] *284:11 2.07143e-05
-10 *181:10 *284:8 0.0188371
-11 *220:13 *419:la_oenb[47] 0.00144233
-12 *220:13 *284:11 0.0248848
-13 *221:21 *284:7 0.000604551
-14 *241:17 *284:11 0.0278032
-*RES
-1 la_oenb[47] *284:7 29.565
-2 *284:7 *284:8 362.07
-3 *284:8 *284:10 4.5
-4 *284:10 *284:11 239.85
-5 *284:11 *419:la_oenb[47] 16.9689
-*END
-
-*D_NET *285 0.190521
-*CONN
-*P la_oenb[48] I
-*I *419:la_oenb[48] I *D user_proj_example
-*CAP
-1 la_oenb[48] 0.00439232
-2 *419:la_oenb[48] 0.000445715
-3 *285:19 0.0219883
-4 *285:18 0.0215426
-5 *285:16 0.0311188
-6 *285:15 0.0355111
-7 la_data_out[48] *285:15 0
-8 *419:la_data_in[48] *285:19 0.000610688
-9 *419:la_data_in[49] *419:la_oenb[48] 0.000571781
-10 *124:16 *285:16 0.0597446
-11 *221:17 *419:la_oenb[48] 0.000662325
-12 *221:17 *285:19 0.0139323
-13 *283:22 *285:19 0
-*RES
-1 la_oenb[48] *285:15 47.745
-2 *285:15 *285:16 367.29
-3 *285:16 *285:18 4.5
-4 *285:18 *285:19 223.47
-5 *285:19 *419:la_oenb[48] 17.1215
-*END
-
-*D_NET *286 0.292352
-*CONN
-*P la_oenb[49] I
-*I *419:la_oenb[49] I *D user_proj_example
-*CAP
-1 la_oenb[49] 0.00257408
-2 *419:la_oenb[49] 0.000816741
-3 *286:19 0.0254965
-4 *286:18 0.0246798
-5 *286:16 0.023159
-6 *286:15 0.0257331
-7 *419:la_oenb[49] *419:la_oenb[50] 0.000534918
-8 *419:la_oenb[49] *419:la_oenb[55] 0
-9 *419:la_oenb[49] *290:14 0.0149825
-10 *419:la_oenb[49] *294:16 0.00752232
-11 *286:19 *300:17 0
-12 la_data_out[49] *286:15 2.5829e-05
-13 *419:la_data_in[47] *419:la_oenb[49] 0.00064242
-14 *419:la_data_in[50] *419:la_oenb[49] 0.00119683
-15 *419:la_data_in[61] *286:19 0.00073344
-16 *133:24 *419:la_oenb[49] 5.43985e-05
-17 *142:22 *419:la_oenb[49] 0.000663069
-18 *219:13 *419:la_oenb[49] 0.00913896
-19 *222:11 *419:la_oenb[49] 0.000403929
-20 *235:9 *286:19 0
-21 *236:11 *286:19 0
-22 *272:16 *286:16 0.153994
-*RES
-1 la_oenb[49] *286:15 29.925
-2 *286:15 *286:16 341.73
-3 *286:16 *286:18 4.5
-4 *286:18 *286:19 243.63
-5 *286:19 *419:la_oenb[49] 44.055
-*END
-
-*D_NET *287 0.377699
-*CONN
-*P la_oenb[4] I
-*I *419:la_oenb[4] I *D user_proj_example
-*CAP
-1 la_oenb[4] 0.00240104
-2 *419:la_oenb[4] 0.000783713
-3 *287:19 0.00368581
-4 *287:18 0.00290209
-5 *287:16 0.00549356
-6 *287:15 0.0078946
-7 *419:la_oenb[4] *298:11 0
-8 *287:19 wbs_dat_o[27] 0.000343704
-9 la_data_out[4] *287:15 1.87963e-05
-10 *419:la_data_in[5] *419:la_oenb[4] 0.00111883
-11 *120:16 *287:16 0.0392289
-12 *170:11 *419:la_oenb[4] 0.000400477
-13 *170:11 *287:19 0.160129
-14 *223:17 *419:la_oenb[4] 0.00231387
-15 *223:17 *287:19 0.00251641
-16 *223:21 *287:19 0.148161
-17 *270:19 *287:15 0.000306879
-*RES
-1 la_oenb[4] *287:15 27.405
-2 *287:15 *287:16 81.09
-3 *287:16 *287:18 4.5
-4 *287:18 *287:19 234.81
-5 *287:19 *419:la_oenb[4] 17.685
-*END
-
-*D_NET *288 0.541614
-*CONN
-*P la_oenb[50] I
-*I *419:la_oenb[50] I *D user_proj_example
-*CAP
-1 la_oenb[50] 0.00010579
-2 *419:la_oenb[50] 0.000474052
-3 *288:25 0.00309349
-4 *288:16 0.00965882
-5 *288:15 0.00703938
-6 *288:13 0.0232317
-7 *288:11 0.0233375
-8 *419:la_oenb[50] *290:14 0.000360584
-9 *288:25 *419:la_oenb[53] 0.000184127
-10 *288:25 *292:11 0
-11 *419:la_data_in[47] *419:la_oenb[50] 2.07232e-05
-12 *419:la_data_in[51] *419:la_oenb[50] 0.00103316
-13 *419:la_data_in[54] *288:25 0.000392805
-14 *419:la_oenb[49] *419:la_oenb[50] 0.000534918
-15 *144:16 *419:la_oenb[50] 0.00553311
-16 *216:14 *288:16 0.209947
-17 *224:9 *419:la_oenb[50] 0
-18 *227:5 *288:25 0.00295294
-19 *229:10 *288:16 0.253715
-*RES
-1 la_oenb[50] *288:11 1.395
-2 *288:11 *288:13 230.67
-3 *288:13 *288:15 4.5
-4 *288:15 *288:16 371.43
-5 *288:16 *288:25 45.45
-6 *288:25 *419:la_oenb[50] 17.055
-*END
-
-*D_NET *289 0.576735
-*CONN
-*P la_oenb[51] I
-*I *419:la_oenb[51] I *D user_proj_example
-*CAP
-1 la_oenb[51] 0.000469055
-2 *419:la_oenb[51] 0.000348149
-3 *289:11 0.0249639
-4 *289:10 0.0246157
-5 *289:8 0.0050796
-6 *289:7 0.00554866
-7 *289:8 *292:8 0.262417
-8 *289:8 *306:8 0.000559527
-9 *419:la_data_in[47] *289:11 0
-10 *419:la_data_in[51] *289:11 0.000187196
-11 *419:la_data_in[52] *419:la_oenb[51] 0.00144233
-12 *158:8 *289:8 0.0197283
-13 *162:13 *289:7 0.000500596
-14 *172:8 *289:8 0.00976066
-15 *225:11 *419:la_oenb[51] 0.00144233
-16 *225:11 *289:11 0.0269716
-17 *255:8 *289:8 0.000783338
-18 *275:8 *289:8 0.191917
-*RES
-1 la_oenb[51] *289:7 11.025
-2 *289:7 *289:8 387.99
-3 *289:8 *289:10 4.5
-4 *289:10 *289:11 258.39
-5 *289:11 *419:la_oenb[51] 16.9689
-*END
-
-*D_NET *290 0.356177
-*CONN
-*P la_oenb[52] I
-*I *419:la_oenb[52] I *D user_proj_example
-*CAP
-1 la_oenb[52] 0.00257317
-2 *419:la_oenb[52] 0.00034434
-3 *290:14 0.00117245
-4 *290:13 0.000828109
-5 *290:11 0.0245188
-6 *290:10 0.0245188
-7 *290:8 0.0200688
-8 *290:7 0.022642
-9 *290:14 *419:la_oenb[53] 0.0055744
-10 *290:14 *294:16 0.00246606
-11 *290:14 *301:20 0.0168479
-12 *290:14 *310:8 0.0131177
-13 la_data_out[15] *290:11 0.000510953
-14 *419:la_data_in[53] *419:la_oenb[52] 0.00115591
-15 *419:la_oenb[49] *290:14 0.0149825
-16 *419:la_oenb[50] *290:14 0.000360584
-17 *144:16 *290:14 1.81328e-05
-18 *226:7 *419:la_oenb[52] 0
-19 *249:13 *290:11 0
-20 *284:8 *290:8 0.204476
-*RES
-1 la_oenb[52] *290:7 29.745
-2 *290:7 *290:8 341.91
-3 *290:8 *290:10 4.5
-4 *290:10 *290:11 240.93
-5 *290:11 *290:13 4.5
-6 *290:13 *290:14 51.39
-7 *290:14 *419:la_oenb[52] 9.585
-*END
-
-*D_NET *291 0.405326
-*CONN
-*P la_oenb[53] I
-*I *419:la_oenb[53] I *D user_proj_example
-*CAP
-1 la_oenb[53] 0.000166523
-2 *419:la_oenb[53] 0.000684452
-3 *291:23 0.00499857
-4 *291:16 0.020644
-5 *291:15 0.0163298
-6 *291:13 0.0226408
-7 *291:11 0.0228073
-8 *291:23 *419:la_oenb[62] 0.000184127
-9 *291:23 *302:19 0
-10 *419:la_data_in[54] *419:la_oenb[53] 0.00107408
-11 *419:la_data_in[63] *291:23 0.000214815
-12 *144:16 *419:la_oenb[53] 0.0055744
-13 *225:14 *291:16 0.243519
-14 *227:5 *419:la_oenb[53] 0.000341786
-15 *233:10 *291:16 0.00497357
-16 *237:7 *291:23 0.000270053
-17 *256:16 *291:16 0.0551445
-18 *288:25 *419:la_oenb[53] 0.000184127
-19 *290:14 *419:la_oenb[53] 0.0055744
-*RES
-1 la_oenb[53] *291:11 1.935
-2 *291:11 *291:13 225.27
-3 *291:13 *291:15 4.5
-4 *291:15 *291:16 374.13
-5 *291:16 *291:23 46.17
-6 *291:23 *419:la_oenb[53] 37.935
-*END
-
-*D_NET *292 0.736984
-*CONN
-*P la_oenb[54] I
-*I *419:la_oenb[54] I *D user_proj_example
-*CAP
-1 la_oenb[54] 0.00071339
-2 *419:la_oenb[54] 0.000391578
-3 *292:11 0.0169028
-4 *292:10 0.0165113
-5 *292:8 0.00471127
-6 *292:7 0.00542467
-7 *292:8 *295:8 0.275846
-8 la_data_out[10] *292:11 0.00435768
-9 *419:la_data_in[54] *292:11 4.60318e-05
-10 *419:la_data_in[55] *419:la_oenb[54] 0.00144233
-11 *133:24 *419:la_oenb[54] 0.000310848
-12 *150:16 *419:la_oenb[54] 0
-13 *165:11 *292:11 0.137911
-14 *172:8 *292:8 0.00634127
-15 *219:13 *419:la_oenb[54] 0.000225045
-16 *228:15 *419:la_oenb[54] 0.000257394
-17 *228:15 *292:11 0.00130935
-18 *255:8 *292:8 0.00186502
-19 *288:25 *292:11 0
-20 *289:8 *292:8 0.262417
-*RES
-1 la_oenb[54] *292:7 10.845
-2 *292:7 *292:8 407.43
-3 *292:8 *292:10 4.5
-4 *292:10 *292:11 258.57
-5 *292:11 *419:la_oenb[54] 16.695
-*END
-
-*D_NET *293 0.610674
-*CONN
-*P la_oenb[55] I
-*I *419:la_oenb[55] I *D user_proj_example
-*CAP
-1 la_oenb[55] 0.00010579
-2 *419:la_oenb[55] 0.000773579
-3 *293:19 0.00502889
-4 *293:16 0.0101115
-5 *293:15 0.00585619
-6 *293:13 0.0223229
-7 *293:11 0.0224287
-8 *419:la_oenb[55] *294:16 3.10849e-06
-9 *293:19 *295:11 0
-10 *419:la_data_in[56] *419:la_oenb[55] 0.000452263
-11 *419:la_data_in[57] *293:19 0.000715027
-12 *419:la_oenb[49] *419:la_oenb[55] 0
-13 *108:14 *293:16 0
-14 *133:24 *419:la_oenb[55] 0.00020538
-15 *142:21 *419:la_oenb[55] 0.000675133
-16 *150:16 *419:la_oenb[55] 0
-17 *226:10 *293:16 0.26217
-18 *229:9 *419:la_oenb[55] 0
-19 *230:7 *293:19 0
-20 *232:10 *293:16 0.279826
-*RES
-1 la_oenb[55] *293:11 1.395
-2 *293:11 *293:13 222.39
-3 *293:13 *293:15 4.5
-4 *293:15 *293:16 409.23
-5 *293:16 *293:19 46.89
-6 *293:19 *419:la_oenb[55] 18.315
-*END
-
-*D_NET *294 0.470277
-*CONN
-*P la_oenb[56] I
-*I *419:la_oenb[56] I *D user_proj_example
-*CAP
-1 la_oenb[56] 0.000218295
-2 *419:la_oenb[56] 0.000376839
-3 *294:16 0.0118024
-4 *294:15 0.0114255
-5 *294:13 0.0267368
-6 *294:11 0.0269551
-7 *294:16 *296:16 0.284551
-8 *294:16 *310:8 0.0877215
-9 *419:la_data_in[57] *419:la_oenb[56] 0.00123774
-10 *419:la_oenb[49] *294:16 0.00752232
-11 *419:la_oenb[55] *294:16 3.10849e-06
-12 *33:9 *294:16 0.00648742
-13 *144:16 *294:16 0.00275412
-14 *167:13 *294:11 1.87963e-05
-15 *217:14 *294:16 0
-16 *230:7 *419:la_oenb[56] 0
-17 *290:14 *294:16 0.00246606
-*RES
-1 la_oenb[56] *294:11 2.475
-2 *294:11 *294:13 265.77
-3 *294:13 *294:15 4.5
-4 *294:15 *294:16 417.33
-5 *294:16 *419:la_oenb[56] 9.945
-*END
-
-*D_NET *295 0.476876
-*CONN
-*P la_oenb[57] I
-*I *419:la_oenb[57] I *D user_proj_example
-*CAP
-1 la_oenb[57] 0.000633074
-2 *419:la_oenb[57] 0.000761337
-3 *295:11 0.0277287
-4 *295:10 0.0269673
-5 *295:8 0.0185906
-6 *295:7 0.0192237
-7 la_data_out[11] *295:11 0.013073
-8 la_data_out[26] *295:8 0.00391659
-9 la_data_out[32] *295:8 0.00105689
-10 la_data_out[33] *295:8 0.00354368
-11 la_data_out[58] *295:8 0.00304632
-12 *419:la_data_in[58] *419:la_oenb[57] 0
-13 *121:8 *419:la_oenb[57] 0.000683535
-14 *154:10 *295:8 0.00105689
-15 *160:10 *295:8 0.00105689
-16 *172:8 *295:8 0.00319545
-17 *231:15 *419:la_oenb[57] 0.00178194
-18 *231:15 *295:11 0.0144724
-19 *232:7 *419:la_oenb[57] 0
-20 *255:8 *295:8 0.0602419
-21 *292:8 *295:8 0.275846
-22 *293:19 *295:11 0
-*RES
-1 la_oenb[57] *295:7 10.665
-2 *295:7 *295:8 426.87
-3 *295:8 *295:10 4.5
-4 *295:10 *295:11 256.59
-5 *295:11 *419:la_oenb[57] 18.945
-*END
-
-*D_NET *296 0.645735
-*CONN
-*P la_oenb[58] I
-*I *419:la_oenb[58] I *D user_proj_example
-*CAP
-1 la_oenb[58] 0.000167461
-2 *419:la_oenb[58] 0.000398924
-3 *296:16 0.0061703
-4 *296:15 0.00577138
-5 *296:13 0.0296584
-6 *296:11 0.0298258
-7 *296:16 *419:la_oenb[61] 9.97306e-05
-8 *296:16 *308:8 0.287659
-9 la_data_out[58] *296:13 0
-10 *419:la_data_in[59] *419:la_oenb[58] 0.00127866
-11 *419:la_data_in[60] *296:16 0.000154129
-12 *419:la_data_in[62] *296:16 0
-13 *33:9 *296:16 0
-14 *232:7 *419:la_oenb[58] 0
-15 *294:16 *296:16 0.284551
-*RES
-1 la_oenb[58] *296:11 1.935
-2 *296:11 *296:13 265.59
-3 *296:13 *296:15 4.5
-4 *296:15 *296:16 430.83
-5 *296:16 *419:la_oenb[58] 10.125
-*END
-
-*D_NET *297 0.28677
-*CONN
-*P la_oenb[59] I
-*I *419:la_oenb[59] I *D user_proj_example
-*CAP
-1 la_oenb[59] 0.000291157
-2 *419:la_oenb[59] 0.000862799
-3 *297:16 0.0310945
-4 *297:15 0.0302317
-5 *297:13 0.0258269
-6 *297:11 0.026118
-7 la_data_out[59] *297:13 2.5829e-05
-8 *419:la_data_in[60] *419:la_oenb[59] 0.00153363
-9 *158:18 *297:16 0.170159
-10 *233:7 *419:la_oenb[59] 0.000626544
-*RES
-1 la_oenb[59] *297:11 3.015
-2 *297:11 *297:13 257.31
-3 *297:13 *297:15 4.5
-4 *297:15 *297:16 436.77
-5 *297:16 *419:la_oenb[59] 19.035
-*END
-
-*D_NET *298 0.289203
-*CONN
-*P la_oenb[5] I
-*I *419:la_oenb[5] I *D user_proj_example
-*CAP
-1 la_oenb[5] 0.000703768
-2 *419:la_oenb[5] 0.00041151
-3 *298:11 0.0154172
-4 *298:10 0.0150057
-5 *298:8 0.00220081
-6 *298:7 0.00290458
-7 *298:8 *303:8 0.0602422
-8 *298:8 *337:15 0.000621697
-9 *298:8 *340:8 0.0198321
-10 *298:11 *336:10 3.37566e-05
-11 *419:la_data_in[5] *298:11 8.28572e-05
-12 *419:la_data_in[6] *419:la_oenb[5] 0.00201517
-13 *419:la_oenb[4] *298:11 0
-14 *234:9 *419:la_oenb[5] 0.00152417
-15 *234:11 *419:la_oenb[5] 7.36509e-05
-16 *234:11 *298:11 0.163689
-17 *258:8 *298:8 0.000419646
-18 *260:8 *298:8 0.00271989
-19 *271:8 *298:8 0.00111905
-20 *274:8 *298:8 0.000186509
-*RES
-1 la_oenb[5] *298:7 11.025
-2 *298:7 *298:8 89.91
-3 *298:8 *298:10 4.5
-4 *298:10 *298:11 255.87
-5 *298:11 *419:la_oenb[5] 19.4889
-*END
-
-*D_NET *299 0.147175
-*CONN
-*P la_oenb[60] I
-*I *419:la_oenb[60] I *D user_proj_example
-*CAP
-1 la_oenb[60] 0.00116776
-2 *419:la_oenb[60] 9.91926e-05
-3 *299:14 0.0387947
-4 *299:13 0.0386955
-5 *299:11 0.026338
-6 *299:10 0.0275058
-7 *299:10 *308:11 0.000184127
-8 *299:10 *310:14 0
-9 *419:la_data_in[61] *419:la_oenb[60] 0.000378484
-10 *154:14 *299:14 0
-11 *168:16 *299:14 0
-12 *171:5 *299:11 0
-13 *172:8 *299:10 0.000770645
-14 *200:8 *299:14 0.0120783
-15 *205:8 *299:14 0.00116255
-16 *235:9 *419:la_oenb[60] 0
-*RES
-1 la_oenb[60] *299:10 24.075
-2 *299:10 *299:11 262.17
-3 *299:11 *299:13 4.5
-4 *299:13 *299:14 437.49
-5 *299:14 *419:la_oenb[60] 6.165
-*END
-
-*D_NET *300 0.391517
-*CONN
-*P la_oenb[61] I
-*I *419:la_oenb[61] I *D user_proj_example
-*CAP
-1 la_oenb[61] 0.00178378
-2 *419:la_oenb[61] 0.000356512
-3 *300:17 0.0148878
-4 *300:16 0.0145313
-5 *300:14 0.0350244
-6 *300:13 0.0368082
-7 *300:13 user_irq[0] 0.000683829
-8 la_data_out[12] *300:17 0.138157
-9 *419:la_data_in[62] *419:la_oenb[61] 0.000698442
-10 *419:la_data_in[62] *300:17 0.0119683
-11 *173:13 *300:13 0.000500596
-12 *236:11 *419:la_oenb[61] 0.000695848
-13 *236:11 *300:17 0.000184127
-14 *236:13 *300:17 0.00626033
-15 *236:19 *300:13 0
-16 *268:8 *300:14 0.128877
-17 *286:19 *300:17 0
-18 *296:16 *419:la_oenb[61] 9.97306e-05
-*RES
-1 la_oenb[61] *300:13 33.525
-2 *300:13 *300:14 449.91
-3 *300:14 *300:16 4.5
-4 *300:16 *300:17 247.95
-5 *300:17 *419:la_oenb[61] 16.785
-*END
-
-*D_NET *301 0.641032
-*CONN
-*P la_oenb[62] I
-*I *419:la_oenb[62] I *D user_proj_example
-*CAP
-1 la_oenb[62] 0.00323696
-2 *419:la_oenb[62] 0.000372926
-3 *301:20 0.00125744
-4 *301:12 0.00775841
-5 *301:11 0.0068739
-6 *301:9 0.0231519
-7 *301:7 0.0263889
-8 *301:20 *310:8 0.00120195
-9 *419:la_data_in[63] *419:la_oenb[62] 0.00037631
-10 *144:16 *301:20 0.00340688
-11 *166:16 *301:12 0.252969
-12 *237:7 *419:la_oenb[62] 0
-13 *238:13 *301:20 0.00113978
-14 *238:14 *301:12 0.295866
-15 *290:14 *301:20 0.0168479
-16 *291:23 *419:la_oenb[62] 0.000184127
-*RES
-1 la_oenb[62] *301:7 32.085
-2 *301:7 *301:9 231.12
-3 *301:9 *301:11 4.5
-4 *301:11 *301:12 428.31
-5 *301:12 *301:20 46.62
-6 *301:20 *419:la_oenb[62] 4.905
-*END
-
-*D_NET *302 0.166635
-*CONN
-*P la_oenb[63] I
-*I *419:la_oenb[63] I *D user_proj_example
-*CAP
-1 la_oenb[63] 0.00296767
-2 *419:la_oenb[63] 0.00341248
-3 *302:19 0.0250251
-4 *302:18 0.0216126
-5 *302:16 0.0426542
-6 *302:15 0.0456218
-7 *419:la_oenb[63] *308:7 0
-8 *419:la_data_in[63] *419:la_oenb[63] 0
-9 *77:15 *302:16 0
-10 *123:16 *302:16 0.0243083
-11 *238:13 *419:la_oenb[63] 0.00103316
-12 *291:23 *302:19 0
-*RES
-1 la_oenb[63] *302:15 34.245
-2 *302:15 *302:16 464.49
-3 *302:16 *302:18 4.5
-4 *302:18 *302:19 212.04
-5 *302:19 *419:la_oenb[63] 32.895
-*END
-
-*D_NET *303 0.330489
-*CONN
-*P la_oenb[6] I
-*I *419:la_oenb[6] I *D user_proj_example
-*CAP
-1 la_oenb[6] 0.000680082
-2 *419:la_oenb[6] 0.000478609
-3 *303:11 0.014891
-4 *303:10 0.0144124
-5 *303:8 0.00114005
-6 *303:7 0.00182014
-7 *303:8 *306:8 0.0609882
-8 *303:8 *337:15 0.00528443
-9 *303:11 *336:10 0
-10 *419:la_data_in[6] *303:11 0.000687408
-11 *419:la_data_in[7] *419:la_oenb[6] 0.00129412
-12 *176:11 *303:11 0.165162
-13 *239:11 *419:la_oenb[6] 0.000686897
-14 *239:13 *419:la_oenb[6] 0.000699683
-15 *239:13 *303:11 8.18344e-05
-16 *274:8 *303:8 0.000261113
-17 *275:8 *303:8 0.00167858
-18 *298:8 *303:8 0.0602422
-*RES
-1 la_oenb[6] *303:7 10.845
-2 *303:7 *303:8 96.39
-3 *303:8 *303:10 4.5
-4 *303:10 *303:11 253.53
-5 *303:11 *419:la_oenb[6] 22.0207
-*END
-
-*D_NET *304 0.156223
-*CONN
-*P la_oenb[7] I
-*I *419:la_oenb[7] I *D user_proj_example
-*CAP
-1 la_oenb[7] 0.00129924
-2 *419:la_oenb[7] 0.00118481
-3 *304:11 0.018873
-4 *304:10 0.0176882
-5 *304:8 0.00348657
-6 *304:7 0.00478581
-7 *304:11 wbs_dat_o[31] 1.53439e-05
-8 *419:la_data_in[18] *304:11 0.00597391
-9 *419:la_data_in[8] *419:la_oenb[7] 0.00119683
-10 *419:la_oenb[2] *419:la_oenb[7] 0.00379236
-11 *419:la_oenb[3] *419:la_oenb[7] 0.00110662
-12 *124:19 *304:11 0.0152112
-13 *125:19 *304:11 0
-14 *126:8 *304:8 0.0092633
-15 *182:10 *419:la_oenb[7] 0.0100093
-16 *187:13 *304:11 0.00100656
-17 *187:16 *304:8 0.0515384
-18 *188:7 *304:11 0
-19 *240:5 *419:la_oenb[7] 0.000403929
-20 *246:16 *419:la_oenb[7] 0.00938764
-*RES
-1 la_oenb[7] *304:7 16.425
-2 *304:7 *304:8 74.61
-3 *304:8 *304:10 4.5
-4 *304:10 *304:11 254.07
-5 *304:11 *419:la_oenb[7] 41.355
-*END
-
-*D_NET *305 0.259978
-*CONN
-*P la_oenb[8] I
-*I *419:la_oenb[8] I *D user_proj_example
-*CAP
-1 la_oenb[8] 0.000966565
-2 *419:la_oenb[8] 0.000235988
-3 *305:11 0.0171015
-4 *305:10 0.0168655
-5 *305:8 0.00681213
-6 *305:7 0.0077787
-7 *305:8 *339:13 0
-8 *305:8 *402:20 0
-9 *419:la_data_in[8] *305:11 8.28572e-05
-10 *419:la_data_in[9] *419:la_oenb[8] 0.00144233
-11 *419:la_oenb[3] *419:la_oenb[8] 0.000186509
-12 *178:13 *305:7 0
-13 *241:9 *419:la_oenb[8] 0.00144233
-14 *241:9 *305:11 5.52382e-05
-15 *241:11 *305:11 0.135333
-16 *246:8 *305:8 0.00055949
-17 *258:8 *305:8 0
-18 *264:8 *305:8 0.0363659
-19 *265:8 *305:8 0.0347489
-*RES
-1 la_oenb[8] *305:7 13.365
-2 *305:7 *305:8 109.35
-3 *305:8 *305:10 4.5
-4 *305:10 *305:11 256.05
-5 *305:11 *419:la_oenb[8] 16.695
-*END
-
-*D_NET *306 0.319944
-*CONN
-*P la_oenb[9] I
-*I *419:la_oenb[9] I *D user_proj_example
-*CAP
-1 la_oenb[9] 0.000656396
-2 *419:la_oenb[9] 0.000644021
-3 *306:11 0.0159234
-4 *306:10 0.0152794
-5 *306:8 0.002737
-6 *306:7 0.00339339
-7 *306:11 *337:15 1.22751e-05
-8 *419:la_data_in[10] *419:la_oenb[9] 0
-9 *419:la_data_in[9] *306:11 0.000604551
-10 *242:11 *419:la_oenb[9] 0.0026412
-11 *242:13 *419:la_oenb[9] 1.79013e-05
-12 *242:13 *306:11 0.151905
-13 *255:8 *306:8 0.0594961
-14 *265:11 *419:la_oenb[9] 0.00161623
-15 *265:11 *306:11 0
-16 *275:8 *306:8 0.00346902
-17 *289:8 *306:8 0.000559527
-18 *303:8 *306:8 0.0609882
-*RES
-1 la_oenb[9] *306:7 10.665
-2 *306:7 *306:8 115.83
-3 *306:8 *306:10 4.5
-4 *306:10 *306:11 252.63
-5 *306:11 *419:la_oenb[9] 23.1007
-*END
-
-*D_NET *308 0.396119
-*CONN
-*P user_irq[0] O
-*I *419:irq[0] O *D user_proj_example
-*CAP
-1 user_irq[0] 0.00339766
-2 *419:irq[0] 0.000437504
-3 *308:11 0.0293714
-4 *308:10 0.0259737
-5 *308:8 0.0231042
-6 *308:7 0.0235417
-7 user_irq[0] *309:13 0.000613118
-8 *308:7 *309:9 0.000791747
-9 *419:la_oenb[63] *308:7 0
-10 *33:9 *308:8 0
-11 *172:8 user_irq[0] 0.000360562
-12 *296:16 *308:8 0.287659
-13 *299:10 *308:11 0.000184127
-14 *300:13 user_irq[0] 0.000683829
-*RES
-1 *419:irq[0] *308:7 10.305
-2 *308:7 *308:8 436.59
-3 *308:8 *308:10 4.5
-4 *308:10 *308:11 259.29
-5 *308:11 user_irq[0] 48.375
-*END
-
-*D_NET *309 0.376726
-*CONN
-*P user_irq[1] O
-*I *419:irq[1] O *D user_proj_example
-*CAP
-1 user_irq[1] 0.000291157
-2 *419:irq[1] 0.00434033
-3 *309:13 0.023162
-4 *309:12 0.0228708
-5 *309:10 0.0282027
-6 *309:9 0.032543
-7 *309:9 *310:7 0
-8 user_irq[0] *309:13 0.000613118
-9 *229:10 *309:10 0.263911
-10 *308:7 *309:9 0.000791747
-*RES
-1 *419:irq[1] *309:9 45.855
-2 *309:9 *309:10 469.89
-3 *309:10 *309:12 4.5
-4 *309:12 *309:13 230.31
-5 *309:13 user_irq[1] 3.015
-*END
-
-*D_NET *310 0.256525
-*CONN
-*P user_irq[2] O
-*I *419:irq[2] O *D user_proj_example
-*CAP
-1 user_irq[2] 0.000908262
-2 *419:irq[2] 0.000594117
-3 *310:14 0.0362163
-4 *310:13 0.035308
-5 *310:11 0.0262794
-6 *310:10 0.0262794
-7 *310:8 0.00229456
-8 *310:7 0.00288867
-9 la_data_out[27] *310:11 0
-10 la_data_out[48] *310:14 0
-11 *144:16 *310:8 0.00798725
-12 *238:13 *310:7 0
-13 *264:8 *310:14 0.0157274
-14 *271:8 *310:14 0
-15 *290:14 *310:8 0.0131177
-16 *294:16 *310:8 0.0877215
-17 *299:10 *310:14 0
-18 *301:20 *310:8 0.00120195
-19 *309:9 *310:7 0
-*RES
-1 *419:irq[2] *310:7 9.765
-2 *310:7 *310:8 126.99
-3 *310:8 *310:10 4.5
-4 *310:10 *310:11 257.13
-5 *310:11 *310:13 4.5
-6 *310:13 *310:14 347.13
-7 *310:14 user_irq[2] 13.365
-*END
-
-*D_NET *313 0.127298
+*D_NET *313 0.10389
*CONN
*P wb_clk_i I
-*I *419:wb_clk_i I *D user_proj_example
+*I *419:wb_clk_i I *D wrapped_vga_clock
*CAP
1 wb_clk_i 0.000291157
-2 *419:wb_clk_i 0.00232083
-3 *313:16 0.0181487
-4 *313:15 0.0158278
-5 *313:13 0.0236068
-6 *313:11 0.023898
-7 *419:wb_clk_i *314:11 0.0242434
-8 *313:16 *320:16 0.0189618
-9 *69:11 *313:13 0
+2 *419:wb_clk_i 0.0134678
+3 *313:15 0.0134678
+4 *313:13 0.0355052
+5 *313:11 0.0357963
+6 *64:14 *419:wb_clk_i 0.00536215
+7 *94:8 *313:13 0
*RES
1 wb_clk_i *313:11 3.015
-2 *313:11 *313:13 235.71
+2 *313:11 *313:13 354.33
3 *313:13 *313:15 4.5
-4 *313:15 *313:16 178.65
-5 *313:16 *419:wb_clk_i 40.995
+4 *313:15 *419:wb_clk_i 170.325
*END
-*D_NET *314 0.250946
+*D_NET *314 0.135663
*CONN
*P wb_rst_i I
-*I *419:wb_rst_i I *D user_proj_example
+*I *419:wb_rst_i I *D wrapped_vga_clock
*CAP
-1 wb_rst_i 0.00252754
-2 *419:wb_rst_i 0.000272069
-3 *314:11 0.0129759
-4 *314:10 0.0127039
-5 *314:8 0.0164332
-6 *314:7 0.0189607
-7 *314:11 *323:13 0.16283
-8 *419:wb_clk_i *314:11 0.0242434
+1 wb_rst_i 0.026316
+2 *419:wb_rst_i 0.000232589
+3 *314:11 0.00350075
+4 *314:10 0.00326817
+5 *314:8 0.0241334
+6 *314:7 0.0241334
+7 *314:5 0.026316
+8 *28:5 *314:8 0
+9 *66:8 *314:11 0.00486914
+10 *101:8 *314:11 0.0228931
+11 *105:15 *314:5 0
*RES
-1 wb_rst_i *314:7 29.565
-2 *314:7 *314:8 173.07
-3 *314:8 *314:10 4.5
-4 *314:10 *314:11 246.15
-5 *314:11 *419:wb_rst_i 11.115
-*END
-
-*D_NET *315 0.100448
-*CONN
-*P wbs_ack_o O
-*I *419:wbs_ack_o O *D user_proj_example
-*CAP
-1 wbs_ack_o 0.0032387
-2 *419:wbs_ack_o 0.00215583
-3 *315:15 0.0231176
-4 *315:14 0.0198789
-5 *315:12 0.0165186
-6 *315:11 0.0186744
-7 *315:11 *419:wbs_cyc_i 0.00270667
-8 *315:11 *419:wbs_stb_i 0.00840847
-9 *315:11 *356:13 0.00574886
-10 *68:11 *315:15 0
-*RES
-1 *419:wbs_ack_o *315:11 45.765
-2 *315:11 *315:12 173.07
-3 *315:12 *315:14 4.5
-4 *315:14 *315:15 198.54
-5 *315:15 wbs_ack_o 32.265
-*END
-
-*D_NET *316 0.171842
-*CONN
-*P wbs_adr_i[0] I
-*I *419:wbs_adr_i[0] I *D user_proj_example
-*CAP
-1 wbs_adr_i[0] 0.000220069
-2 *419:wbs_adr_i[0] 0.000458216
-3 *316:16 0.0105568
-4 *316:15 0.0100986
-5 *316:13 0.0291208
-6 *316:11 0.0293408
-7 *419:wbs_adr_i[0] *419:wbs_dat_i[0] 0.00102191
-8 *419:wbs_adr_i[0] *419:wbs_stb_i 0
-9 *419:wbs_adr_i[0] *419:wbs_we_i 0.00131958
-10 *316:11 *349:13 1.87963e-05
-11 *316:13 *418:10 0.000472977
-12 *316:16 *403:8 0.0892137
-13 *28:5 *316:16 0
-*RES
-1 wbs_adr_i[0] *316:11 2.475
-2 *316:11 *316:13 262.71
-3 *316:13 *316:15 4.5
-4 *316:15 *316:16 165.51
-5 *316:16 *419:wbs_adr_i[0] 13.635
-*END
-
-*D_NET *317 0.0926521
-*CONN
-*P wbs_adr_i[10] I
-*I *419:wbs_adr_i[10] I *D user_proj_example
-*CAP
-1 wbs_adr_i[10] 0.000967586
-2 *419:wbs_adr_i[10] 0.00190221
-3 *317:14 0.00919053
-4 *317:13 0.00728832
-5 *317:11 0.0233847
-6 *317:10 0.0243523
-7 *419:wbs_adr_i[10] wbs_dat_o[19] 0.00111704
-8 *419:wbs_adr_i[10] *419:wbs_dat_i[10] 0
-9 *419:wbs_adr_i[10] *419:wbs_dat_i[11] 0.00460318
-10 *419:wbs_adr_i[10] *419:wbs_dat_i[9] 0.00118072
-11 *419:wbs_adr_i[10] *382:9 0
-12 *419:wbs_adr_i[10] *412:12 0.000571817
-13 *317:10 *412:16 0.000317324
-14 *317:10 *413:8 0
-15 *317:11 wbs_dat_o[10] 0
-16 *317:14 *324:8 0.0174695
-17 *104:12 *317:11 0.000306879
-*RES
-1 wbs_adr_i[10] *317:10 19.575
-2 *317:10 *317:11 233.73
-3 *317:11 *317:13 4.5
-4 *317:13 *317:14 86.31
-5 *317:14 *419:wbs_adr_i[10] 35.955
-*END
-
-*D_NET *318 0.149293
-*CONN
-*P wbs_adr_i[11] I
-*I *419:wbs_adr_i[11] I *D user_proj_example
-*CAP
-1 wbs_adr_i[11] 0.00105029
-2 *419:wbs_adr_i[11] 0.000628996
-3 *318:14 0.00211491
-4 *318:13 0.00148592
-5 *318:11 0.0259341
-6 *318:10 0.0269844
-7 *419:wbs_adr_i[11] *419:wbs_dat_i[11] 0.000500596
-8 *419:wbs_adr_i[11] *382:9 0
-9 *419:wbs_adr_i[11] *383:9 0
-10 *318:10 *338:12 0.00702485
-11 *318:10 *351:13 0.000595217
-12 *318:11 *319:10 8.9762e-05
-13 *318:11 *352:7 0
-14 *318:11 *352:9 0
-15 *318:14 *319:14 0.0435808
-16 *318:14 *342:16 0.0363691
-17 *318:14 *389:12 0.00293441
-*RES
-1 wbs_adr_i[11] *318:10 25.155
-2 *318:10 *318:11 257.31
-3 *318:11 *318:13 4.5
-4 *318:13 *318:14 73.89
-5 *318:14 *419:wbs_adr_i[11] 12.465
-*END
-
-*D_NET *319 0.144221
-*CONN
-*P wbs_adr_i[12] I
-*I *419:wbs_adr_i[12] I *D user_proj_example
-*CAP
-1 wbs_adr_i[12] 0.00134328
-2 *419:wbs_adr_i[12] 0.000582501
-3 *319:14 0.00229191
-4 *319:13 0.00170941
-5 *319:11 0.0258711
-6 *319:10 0.0272143
-7 *419:wbs_adr_i[12] *419:wbs_dat_i[12] 0.000424643
-8 *419:wbs_adr_i[12] *383:9 0
-9 *419:wbs_adr_i[12] *393:11 0.000306879
-10 *319:10 *383:14 0.00814424
-11 *319:10 *413:8 0
-12 *319:11 wbs_dat_o[13] 0
-13 *319:11 *353:13 0
-14 *319:14 *322:14 0.0323901
-15 *319:14 *389:12 0.000271992
-16 *318:11 *319:10 8.9762e-05
-17 *318:14 *319:14 0.0435808
-*RES
-1 wbs_adr_i[12] *319:10 27.855
-2 *319:10 *319:11 256.41
-3 *319:11 *319:13 4.5
-4 *319:13 *319:14 65.79
-5 *319:14 *419:wbs_adr_i[12] 12.285
-*END
-
-*D_NET *320 0.130408
-*CONN
-*P wbs_adr_i[13] I
-*I *419:wbs_adr_i[13] I *D user_proj_example
-*CAP
-1 wbs_adr_i[13] 0.00014502
-2 *419:wbs_adr_i[13] 0.0035647
-3 *320:16 0.00639688
-4 *320:15 0.00283218
-5 *320:13 0.0236817
-6 *320:11 0.0238267
-7 *419:wbs_adr_i[13] *419:wbs_dat_i[12] 0
-8 *419:wbs_adr_i[13] *419:wbs_dat_i[13] 0
-9 *419:wbs_adr_i[13] *352:15 0.00270053
-10 *419:wbs_adr_i[13] *384:13 0.0013605
-11 *419:wbs_adr_i[13] *385:9 0
-12 *320:16 *353:16 0.0469379
-13 *313:16 *320:16 0.0189618
-*RES
-1 wbs_adr_i[13] *320:11 1.755
-2 *320:11 *320:13 235.89
-3 *320:13 *320:15 4.5
-4 *320:15 *320:16 70.65
-5 *320:16 *419:wbs_adr_i[13] 41.895
-*END
-
-*D_NET *321 0.132126
-*CONN
-*P wbs_adr_i[14] I
-*I *419:wbs_adr_i[14] I *D user_proj_example
-*CAP
-1 wbs_adr_i[14] 0.000271935
-2 *419:wbs_adr_i[14] 0.000761622
-3 *321:16 0.00298037
-4 *321:15 0.00221874
-5 *321:13 0.0262748
-6 *321:11 0.0265468
-7 *419:wbs_adr_i[14] *419:wbs_dat_i[14] 0.000936364
-8 *419:wbs_adr_i[14] *385:9 0
-9 *321:13 wbs_dat_o[13] 1.87963e-05
-10 *321:13 *414:21 0
-11 *321:16 *347:16 0.0369908
-12 *321:16 *387:8 0.0351256
-13 *29:16 *321:13 0
-*RES
-1 wbs_adr_i[14] *321:11 2.835
-2 *321:11 *321:13 260.37
-3 *321:13 *321:15 4.5
-4 *321:15 *321:16 67.05
-5 *321:16 *419:wbs_adr_i[14] 15.345
-*END
-
-*D_NET *322 0.128672
-*CONN
-*P wbs_adr_i[15] I
-*I *419:wbs_adr_i[15] I *D user_proj_example
-*CAP
-1 wbs_adr_i[15] 0.000789617
-2 *419:wbs_adr_i[15] 0.000577735
-3 *322:14 0.00163762
-4 *322:13 0.00105988
-5 *322:11 0.0259966
-6 *322:10 0.0267863
-7 *419:wbs_adr_i[15] *419:wbs_dat_i[15] 0.000583453
-8 *419:wbs_adr_i[15] *386:9 0
-9 *322:10 *338:12 0.00217594
-10 *322:11 *355:7 0.000920636
-11 *322:11 *387:11 0
-12 *322:14 *323:16 0.035125
-13 *322:14 *389:12 0.000629418
-14 *322:14 *418:14 0
-15 *12:14 *322:11 0
-16 *319:14 *322:14 0.0323901
-*RES
-1 wbs_adr_i[15] *322:10 18.135
-2 *322:10 *322:11 257.67
-3 *322:11 *322:13 4.5
-4 *322:13 *322:14 54.99
-5 *322:14 *419:wbs_adr_i[15] 12.105
-*END
-
-*D_NET *323 0.239962
-*CONN
-*P wbs_adr_i[16] I
-*I *419:wbs_adr_i[16] I *D user_proj_example
-*CAP
-1 wbs_adr_i[16] 0.00020706
-2 *419:wbs_adr_i[16] 0.00026907
-3 *323:16 0.00283071
-4 *323:15 0.00256164
-5 *323:13 0.0160755
-6 *323:11 0.0162825
-7 *419:wbs_adr_i[16] *419:wbs_dat_i[16] 0.000676028
-8 *419:wbs_adr_i[16] *387:7 0.000569644
-9 *323:16 *419:wbs_adr_i[19] 0
-10 *323:16 *419:wbs_dat_i[11] 0.000356699
-11 *323:16 *419:wbs_sel_i[0] 0.000216817
-12 *323:16 *419:wbs_stb_i 5.90613e-05
-13 *323:16 *384:13 0
-14 *323:16 *389:12 1.55425e-05
-15 *323:16 *394:10 0.000174852
-16 *323:16 *406:13 0.0010071
-17 *323:16 *408:10 0.00064242
-18 *323:16 *412:12 6.29468e-05
-19 *323:16 *416:14 0
-20 *323:16 *418:14 0
-21 *314:11 *323:13 0.16283
-22 *322:14 *323:16 0.035125
-*RES
-1 wbs_adr_i[16] *323:11 2.295
-2 *323:11 *323:13 263.79
-3 *323:13 *323:15 4.5
-4 *323:15 *323:16 53.55
-5 *323:16 *419:wbs_adr_i[16] 11.925
-*END
-
-*D_NET *324 0.223229
-*CONN
-*P wbs_adr_i[17] I
-*I *419:wbs_adr_i[17] I *D user_proj_example
-*CAP
-1 wbs_adr_i[17] 0.014408
-2 *419:wbs_adr_i[17] 0.00171729
-3 *324:8 0.00495893
-4 *324:5 0.0176496
-5 *419:wbs_adr_i[17] *419:wbs_dat_i[16] 0.00288466
-6 *419:wbs_adr_i[17] *419:wbs_dat_i[17] 0
-7 *419:wbs_adr_i[17] *357:17 0
-8 *419:wbs_adr_i[17] *361:11 0.000438836
-9 *419:wbs_adr_i[17] *388:12 0.00115463
-10 *419:wbs_adr_i[17] *388:13 0.0122138
-11 *419:wbs_adr_i[17] *389:9 0
-12 *324:5 *392:9 0.000208677
-13 *324:5 *392:11 0.150125
-14 *317:14 *324:8 0.0174695
-*RES
-1 wbs_adr_i[17] *324:5 241.245
-2 *324:5 *324:8 47.79
-3 *324:8 *419:wbs_adr_i[17] 45.675
-*END
-
-*D_NET *325 0.192443
-*CONN
-*P wbs_adr_i[18] I
-*I *419:wbs_adr_i[18] I *D user_proj_example
-*CAP
-1 wbs_adr_i[18] 0.00235195
-2 *419:wbs_adr_i[18] 0.00195159
-3 *325:17 0.0152283
-4 *325:16 0.0159844
-5 *325:13 0.00505962
-6 *419:wbs_adr_i[18] *419:wbs_dat_i[18] 0.000217884
-7 *419:wbs_adr_i[18] *357:17 0.00175381
-8 *419:wbs_adr_i[18] *359:13 0.00484868
-9 *419:wbs_adr_i[18] *389:9 0.000994799
-10 *419:wbs_adr_i[18] *390:11 0
-11 *325:13 *357:10 0.00192726
-12 *325:13 *358:10 6.13758e-05
-13 *325:13 *408:11 0.00939048
-14 *325:13 *410:14 0.00064242
-15 *325:16 *382:14 0.0105067
-16 *325:17 *357:17 0.121524
-17 *325:17 *362:11 0
-*RES
-1 wbs_adr_i[18] *325:13 44.325
-2 *325:13 *325:16 38.61
-3 *325:16 *325:17 211.86
-4 *325:17 *419:wbs_adr_i[18] 33.615
-*END
-
-*D_NET *326 0.0847193
-*CONN
-*P wbs_adr_i[19] I
-*I *419:wbs_adr_i[19] I *D user_proj_example
-*CAP
-1 wbs_adr_i[19] 0.000271935
-2 *419:wbs_adr_i[19] 0.00240214
-3 *326:13 0.0281318
-4 *326:11 0.0260016
-5 *419:wbs_adr_i[19] *419:wbs_dat_i[19] 0.000572806
-6 *419:wbs_adr_i[19] *384:13 0.00839248
-7 *419:wbs_adr_i[19] *390:9 0
-8 *419:wbs_adr_i[19] *393:10 0.0127444
-9 *419:wbs_adr_i[19] *409:8 0.000186509
-10 *419:wbs_adr_i[19] *411:8 0.000543985
-11 *326:13 wbs_dat_o[18] 0.000840847
-12 *326:13 *419:wbs_adr_i[6] 0.000273122
-13 *326:13 *419:wbs_dat_i[6] 0.00435768
-14 *323:16 *419:wbs_adr_i[19] 0
-*RES
-1 wbs_adr_i[19] *326:11 2.835
-2 *326:11 *326:13 265.41
-3 *326:13 *419:wbs_adr_i[19] 49.455
-*END
-
-*D_NET *327 0.129923
-*CONN
-*P wbs_adr_i[1] I
-*I *419:wbs_adr_i[1] I *D user_proj_example
-*CAP
-1 wbs_adr_i[1] 8.61527e-05
-2 *419:wbs_adr_i[1] 0.000628651
-3 *327:16 0.0121149
-4 *327:15 0.0114863
-5 *327:13 0.026068
-6 *327:11 0.0261541
-7 *419:wbs_adr_i[1] *419:wbs_dat_i[1] 0.000972167
-8 *419:wbs_adr_i[1] *419:wbs_sel_i[0] 0.000500596
-9 *419:wbs_adr_i[1] *381:5 0
-10 *327:13 *418:11 0
-11 *327:16 *347:16 0.0519118
-12 *327:16 *384:14 0
-*RES
-1 wbs_adr_i[1] *327:11 1.215
-2 *327:11 *327:13 260.01
-3 *327:13 *327:15 4.5
-4 *327:15 *327:16 156.15
-5 *327:16 *419:wbs_adr_i[1] 15.705
-*END
-
-*D_NET *328 0.199801
-*CONN
-*P wbs_adr_i[20] I
-*I *419:wbs_adr_i[20] I *D user_proj_example
-*CAP
-1 wbs_adr_i[20] 0.00265236
-2 *419:wbs_adr_i[20] 0.0010894
-3 *328:19 0.0137448
-4 *328:18 0.0151254
-5 *328:15 0.00512229
-6 *419:wbs_adr_i[20] *419:wbs_dat_i[20] 0
-7 *419:wbs_adr_i[20] *329:19 0
-8 *419:wbs_adr_i[20] *391:9 0.000918335
-9 *328:15 *358:11 0
-10 *328:19 *391:9 0.00138709
-11 *328:19 *395:11 0.159761
-*RES
-1 wbs_adr_i[20] *328:15 30.825
-2 *328:15 *328:18 29.07
-3 *328:18 *328:19 234.27
-4 *328:19 *419:wbs_adr_i[20] 23.398
-*END
-
-*D_NET *329 0.10192
-*CONN
-*P wbs_adr_i[21] I
-*I *419:wbs_adr_i[21] I *D user_proj_example
-*CAP
-1 wbs_adr_i[21] 0.00410607
-2 *419:wbs_adr_i[21] 0.000517273
-3 *329:19 0.0149092
-4 *329:18 0.0143919
-5 *329:16 0.00410607
-6 *419:wbs_adr_i[21] *419:wbs_adr_i[23] 0.000808207
-7 *419:wbs_adr_i[21] *419:wbs_dat_i[20] 0
-8 *419:wbs_adr_i[21] *419:wbs_dat_i[21] 0
-9 *419:wbs_adr_i[21] *331:13 9.20636e-06
-10 *419:wbs_adr_i[21] *393:10 0.00131493
-11 *419:wbs_adr_i[21] *395:10 0.00105689
-12 *329:16 *357:11 0
-13 *329:19 *419:wbs_dat_i[20] 0.00742646
-14 *329:19 *331:13 0.0532742
-15 *419:wbs_adr_i[20] *329:19 0
-*RES
-1 wbs_adr_i[21] *329:16 45.675
-2 *329:16 *329:18 4.5
-3 *329:18 *329:19 245.25
-4 *329:19 *419:wbs_adr_i[21] 17.505
-*END
-
-*D_NET *330 0.0902637
-*CONN
-*P wbs_adr_i[22] I
-*I *419:wbs_adr_i[22] I *D user_proj_example
-*CAP
-1 wbs_adr_i[22] 0.00274454
-2 *419:wbs_adr_i[22] 0.00303709
-3 *330:17 0.0158877
-4 *330:16 0.0155951
-5 *419:wbs_adr_i[22] *419:wbs_dat_i[22] 0
-6 *419:wbs_adr_i[22] *362:19 0
-7 *419:wbs_adr_i[22] *364:13 0
-8 *419:wbs_adr_i[22] *394:10 0.00189242
-9 *330:16 wbs_dat_o[18] 0
-10 *330:16 *331:13 0.00135155
-11 *330:16 *362:11 0
-12 *330:16 *364:13 0
-13 *330:17 *364:13 0.0497553
-*RES
-1 wbs_adr_i[22] *330:16 49.995
-2 *330:16 *330:17 218.88
-3 *330:17 *419:wbs_adr_i[22] 33.435
-*END
-
-*D_NET *331 0.0987657
-*CONN
-*P wbs_adr_i[23] I
-*I *419:wbs_adr_i[23] I *D user_proj_example
-*CAP
-1 wbs_adr_i[23] 8.61527e-05
-2 *419:wbs_adr_i[23] 0.000667921
-3 *331:13 0.0165587
-4 *331:11 0.0159769
-5 *419:wbs_adr_i[23] *419:wbs_dat_i[23] 0.000285014
-6 *419:wbs_adr_i[23] *363:14 0.000453321
-7 *419:wbs_adr_i[23] *393:10 0.000111905
-8 *419:wbs_adr_i[23] *395:10 0.00163344
-9 *331:13 *419:wbs_dat_i[20] 0.00754921
-10 *419:wbs_adr_i[21] *419:wbs_adr_i[23] 0.000808207
-11 *419:wbs_adr_i[21] *331:13 9.20636e-06
-12 *329:19 *331:13 0.0532742
-13 *330:16 *331:13 0.00135155
-*RES
-1 wbs_adr_i[23] *331:11 1.215
-2 *331:11 *331:13 265.05
-3 *331:13 *419:wbs_adr_i[23] 22.275
-*END
-
-*D_NET *332 0.202102
-*CONN
-*P wbs_adr_i[24] I
-*I *419:wbs_adr_i[24] I *D user_proj_example
-*CAP
-1 wbs_adr_i[24] 0.000962013
-2 *419:wbs_adr_i[24] 0.00153306
-3 *332:19 0.0152512
-4 *332:18 0.0146801
-5 *419:wbs_adr_i[24] *419:wbs_dat_i[24] 0
-6 *419:wbs_adr_i[24] *396:9 0.00165587
-7 *419:wbs_adr_i[24] *396:11 0
-8 *332:18 *396:11 3.45239e-05
-9 *332:19 *396:11 0.167985
-*RES
-1 wbs_adr_i[24] *332:18 18.495
-2 *332:18 *332:19 246.33
-3 *332:19 *419:wbs_adr_i[24] 30.0972
-*END
-
-*D_NET *333 0.061814
-*CONN
-*P wbs_adr_i[25] I
-*I *419:wbs_adr_i[25] I *D user_proj_example
-*CAP
-1 wbs_adr_i[25] 0.00111261
-2 *419:wbs_adr_i[25] 0.00040743
-3 *333:11 0.0267407
-4 *333:10 0.0274459
-5 *419:wbs_adr_i[25] *419:wbs_dat_i[24] 0.000435078
-6 *419:wbs_adr_i[25] *419:wbs_dat_i[25] 0.000486786
-7 *419:wbs_adr_i[25] *397:14 0.00181986
-8 *333:10 *419:wbs_dat_i[27] 0.000184127
-9 *333:10 *334:11 0.000116358
-10 *333:10 *336:10 0.000435189
-11 *333:10 *368:20 0.000186509
-12 *333:11 wbs_dat_o[24] 0
-13 *333:11 *365:5 0
-14 *333:11 *397:14 0.00244352
-15 *333:11 *399:11 0
-*RES
-1 wbs_adr_i[25] *333:10 21.015
-2 *333:10 *333:11 257.13
-3 *333:11 *419:wbs_adr_i[25] 17.775
-*END
-
-*D_NET *334 0.0684225
-*CONN
-*P wbs_adr_i[26] I
-*I *419:wbs_adr_i[26] I *D user_proj_example
-*CAP
-1 wbs_adr_i[26] 0.000916191
-2 *419:wbs_adr_i[26] 0.000615517
-3 *334:11 0.0179281
-4 *334:10 0.0182288
-5 *419:wbs_adr_i[26] *419:wbs_dat_i[25] 0.000262926
-6 *419:wbs_adr_i[26] *419:wbs_dat_i[26] 0.000445358
-7 *419:wbs_adr_i[26] *397:14 0.000306879
-8 *419:wbs_adr_i[26] *398:10 0.000761708
-9 *419:wbs_adr_i[26] *399:9 0
-10 *419:wbs_adr_i[26] *400:10 1.24339e-05
-11 *334:10 *337:15 0.000184127
-12 *334:10 *337:18 0.00478707
-13 *334:10 *339:20 0.00304632
-14 *334:10 *368:20 0.000142991
-15 *334:11 *419:wbs_adr_i[28] 0.000961554
-16 *334:11 *419:wbs_dat_i[27] 0.0197062
-17 *334:11 *366:13 0
-18 *333:10 *334:11 0.000116358
-*RES
-1 wbs_adr_i[26] *334:10 23.715
-2 *334:10 *334:11 258.03
-3 *334:11 *419:wbs_adr_i[26] 20.655
-*END
-
-*D_NET *335 0.0787499
-*CONN
-*P wbs_adr_i[27] I
-*I *419:wbs_adr_i[27] I *D user_proj_example
-*CAP
-1 wbs_adr_i[27] 0.000851661
-2 *419:wbs_adr_i[27] 0.000742326
-3 *335:19 0.00282804
-4 *335:11 0.019284
-5 *335:10 0.0180499
-6 *419:wbs_adr_i[27] *419:wbs_dat_i[27] 0
-7 *419:wbs_adr_i[27] *398:11 0.00969736
-8 *419:wbs_adr_i[27] *399:9 0.00438658
-9 *419:wbs_adr_i[27] *399:11 6.13757e-06
-10 *335:10 *336:10 0.00292198
-11 *335:10 *402:20 0.00292198
-12 *335:11 wbs_dat_o[26] 0.000469524
-13 *335:19 *398:11 0.000814508
-14 *335:19 *399:9 9.2064e-05
-15 *335:19 *399:11 0.00112931
-16 *126:11 *335:11 0
-17 *179:17 *335:11 0.000268519
-18 *179:21 *335:11 0.0127393
-19 *190:7 *335:11 0
-20 *243:19 *335:11 0.00154667
-*RES
-1 wbs_adr_i[27] *335:10 20.475
-2 *335:10 *335:11 235.17
-3 *335:11 *335:19 34.92
-4 *335:19 *419:wbs_adr_i[27] 22.005
-*END
-
-*D_NET *336 0.112156
-*CONN
-*P wbs_adr_i[28] I
-*I *419:wbs_adr_i[28] I *D user_proj_example
-*CAP
-1 wbs_adr_i[28] 0.00240383
-2 *419:wbs_adr_i[28] 0.00088921
-3 *336:11 0.0157515
-4 *336:10 0.0172661
-5 *419:wbs_adr_i[28] *419:wbs_dat_i[27] 0
-6 *419:wbs_adr_i[28] *419:wbs_dat_i[28] 0
-7 *419:wbs_adr_i[28] *366:13 0.000168783
-8 *419:wbs_adr_i[28] *369:15 0
-9 *419:wbs_adr_i[28] *400:10 0.00148325
-10 *336:10 *368:20 0.00882811
-11 *336:10 *402:20 0.00358512
-12 *336:11 *419:wbs_dat_i[27] 0.0574273
-13 *336:11 *398:11 0
-14 *298:11 *336:10 3.37566e-05
-15 *303:11 *336:10 0
-16 *333:10 *336:10 0.000435189
-17 *334:11 *419:wbs_adr_i[28] 0.000961554
-18 *335:10 *336:10 0.00292198
-*RES
-1 wbs_adr_i[28] *336:10 44.595
-2 *336:10 *336:11 252.63
-3 *336:11 *419:wbs_adr_i[28] 22.545
-*END
-
-*D_NET *337 0.280619
-*CONN
-*P wbs_adr_i[29] I
-*I *419:wbs_adr_i[29] I *D user_proj_example
-*CAP
-1 wbs_adr_i[29] 0.00129959
-2 *419:wbs_adr_i[29] 0.00109167
-3 *337:19 0.00476234
-4 *337:18 0.00377896
-5 *337:15 0.00140788
-6 *419:wbs_adr_i[29] *419:wbs_dat_i[29] 0
-7 *419:wbs_adr_i[29] *339:21 9.20636e-06
-8 *419:wbs_adr_i[29] *369:15 0.000196402
-9 *419:wbs_adr_i[29] *401:10 0.00127866
-10 *419:wbs_adr_i[29] *402:9 0
-11 *337:15 *339:20 0.00302559
-12 *337:15 *340:8 0.000136773
-13 *337:15 *368:20 0.00590613
-14 *337:15 *369:14 0.0143861
-15 *337:18 *339:20 4.14464e-05
-16 *337:18 *369:14 0.00155424
-17 *337:19 *366:13 0.173141
-18 *337:19 *369:15 0.0577137
-19 *298:8 *337:15 0.000621697
-20 *303:8 *337:15 0.00528443
-21 *306:11 *337:15 1.22751e-05
-22 *334:10 *337:15 0.000184127
-23 *334:10 *337:18 0.00478707
-*RES
-1 wbs_adr_i[29] *337:15 47.475
-2 *337:15 *337:18 11.61
-3 *337:18 *337:19 253.89
-4 *337:19 *419:wbs_adr_i[29] 22.858
-*END
-
-*D_NET *338 0.201119
-*CONN
-*P wbs_adr_i[2] I
-*I *419:wbs_adr_i[2] I *D user_proj_example
-*CAP
-1 wbs_adr_i[2] 0.00100319
-2 *419:wbs_adr_i[2] 0.00117375
-3 *338:15 0.029451
-4 *338:14 0.0282773
-5 *338:12 0.00543915
-6 *338:10 0.00644233
-7 *419:wbs_adr_i[2] *419:wbs_dat_i[2] 0.000238215
-8 *419:wbs_adr_i[2] *419:wbs_sel_i[1] 0.00037631
-9 *419:wbs_adr_i[2] *403:7 0
-10 *419:wbs_adr_i[2] *406:13 0
-11 *338:10 *371:10 0.00105689
-12 *338:10 *417:8 0.000417055
-13 *338:12 wbs_dat_o[2] 0.00254896
-14 *338:12 wbs_dat_o[4] 0.00615448
-15 *338:12 wbs_dat_o[6] 0.00105689
-16 *338:12 wbs_dat_o[8] 0.00317066
-17 *338:12 *341:8 0.0929433
-18 *338:12 *350:10 0.00192726
-19 *338:12 *379:10 0.00194798
-20 *338:12 *415:10 0.00789556
-21 *338:12 *417:8 0.000397886
-22 *318:10 *338:12 0.00702485
-23 *322:10 *338:12 0.00217594
-*RES
-1 wbs_adr_i[2] *338:10 16.515
-2 *338:10 *338:12 141.12
-3 *338:12 *338:14 4.5
-4 *338:14 *338:15 252.54
-5 *338:15 *419:wbs_adr_i[2] 12.825
-*END
-
-*D_NET *339 0.20706
-*CONN
-*P wbs_adr_i[30] I
-*I *419:wbs_adr_i[30] I *D user_proj_example
-*CAP
-1 wbs_adr_i[30] 0.00127533
-2 *419:wbs_adr_i[30] 0.000927145
-3 *339:21 0.0155342
-4 *339:20 0.0149424
-5 *339:13 0.00161069
-6 *419:wbs_adr_i[30] *419:wbs_dat_i[30] 0
-7 *419:wbs_adr_i[30] *340:11 0.000168783
-8 *419:wbs_adr_i[30] *400:11 0.00108431
-9 *419:wbs_adr_i[30] *402:9 0.000497144
-10 *419:wbs_adr_i[30] *404:9 0
-11 *339:13 *402:20 0.0121231
-12 *339:13 *404:14 0.0142368
-13 *339:20 *340:8 0.00924258
-14 *339:20 *367:10 0.00242462
-15 *339:20 *368:20 0.00593411
-16 *339:20 *369:14 2.71992e-05
-17 *339:20 *402:20 0.000235727
-18 *339:21 *398:17 0.0983853
-19 *339:21 *402:9 0.00201389
-20 *339:21 *402:11 0.0202745
-21 *419:wbs_adr_i[29] *339:21 9.20636e-06
-22 *305:8 *339:13 0
-23 *334:10 *339:20 0.00304632
-24 *337:15 *339:20 0.00302559
-25 *337:18 *339:20 4.14464e-05
-*RES
-1 wbs_adr_i[30] *339:13 41.805
-2 *339:13 *339:20 25.47
-3 *339:20 *339:21 253.71
-4 *339:21 *419:wbs_adr_i[30] 22.545
-*END
-
-*D_NET *340 0.153632
-*CONN
-*P wbs_adr_i[31] I
-*I *419:wbs_adr_i[31] I *D user_proj_example
-*CAP
-1 wbs_adr_i[31] 0.00071579
-2 *419:wbs_adr_i[31] 0.000558136
-3 *340:11 0.0158522
-4 *340:10 0.015294
-5 *340:8 0.000718576
-6 *340:7 0.00143437
-7 *419:wbs_adr_i[31] *419:wbs_dat_i[26] 0.000186509
-8 *419:wbs_adr_i[31] *419:wbs_dat_i[29] 0.000393741
-9 *419:wbs_adr_i[31] *419:wbs_dat_i[31] 0
-10 *419:wbs_adr_i[31] *367:11 0.00014321
-11 *419:wbs_adr_i[31] *401:10 3.62657e-05
-12 *419:wbs_adr_i[31] *404:9 0.000441905
-13 *340:7 *373:13 0
-14 *340:8 *367:10 0.00242462
-15 *340:8 *402:20 8.28929e-05
-16 *340:8 *404:14 0.0305253
-17 *340:11 *367:11 0
-18 *340:11 *400:11 0
-19 *340:11 *404:9 0.00249723
-20 *340:11 *404:11 0.0529468
-21 *419:wbs_adr_i[30] *340:11 0.000168783
-22 *298:8 *340:8 0.0198321
-23 *337:15 *340:8 0.000136773
-24 *339:20 *340:8 0.00924258
-*RES
-1 wbs_adr_i[31] *340:7 11.205
-2 *340:7 *340:8 47.61
-3 *340:8 *340:10 4.5
-4 *340:10 *340:11 258.21
-5 *340:11 *419:wbs_adr_i[31] 17.685
-*END
-
-*D_NET *341 0.24817
-*CONN
-*P wbs_adr_i[3] I
-*I *419:wbs_adr_i[3] I *D user_proj_example
-*CAP
-1 wbs_adr_i[3] 0.000662592
-2 *419:wbs_adr_i[3] 0.000853967
-3 *341:11 0.0161644
-4 *341:10 0.0153104
-5 *341:8 0.00166673
-6 *341:7 0.00232932
-7 *419:wbs_adr_i[3] *419:wbs_dat_i[3] 0.00147072
-8 *419:wbs_adr_i[3] *419:wbs_sel_i[2] 0.00185559
-9 *419:wbs_adr_i[3] *389:13 0.00804022
-10 *341:7 *374:13 0
-11 *341:8 *357:10 0.000476597
-12 *341:8 *410:14 0.0627289
-13 *341:8 *417:8 0.0105688
-14 *341:11 wbs_dat_o[17] 0.00253303
-15 *341:11 *419:wbs_sel_i[2] 0.00128889
-16 *341:11 *389:13 0.0292762
-17 *338:12 *341:8 0.0929433
-*RES
-1 wbs_adr_i[3] *341:7 10.845
-2 *341:7 *341:8 136.71
-3 *341:8 *341:10 4.5
-4 *341:10 *341:11 244.71
-5 *341:11 *419:wbs_adr_i[3] 30.8015
-*END
-
-*D_NET *342 0.190473
-*CONN
-*P wbs_adr_i[4] I
-*I *419:wbs_adr_i[4] I *D user_proj_example
-*CAP
-1 wbs_adr_i[4] 0.000271935
-2 *419:wbs_adr_i[4] 0.000597672
-3 *342:16 0.00514429
-4 *342:15 0.00454662
-5 *342:13 0.0261698
-6 *342:11 0.0264417
-7 *419:wbs_adr_i[4] *419:wbs_dat_i[3] 0.000269286
-8 *419:wbs_adr_i[4] *419:wbs_dat_i[4] 0.000362501
-9 *419:wbs_adr_i[4] *419:wbs_sel_i[3] 0.000362501
-10 *419:wbs_adr_i[4] *406:13 0.000306879
-11 *419:wbs_adr_i[4] *411:8 0.000559453
-12 *342:13 *415:11 0
-13 *342:13 *416:10 0.0010127
-14 *342:16 *389:12 0.000476634
-15 *342:16 *403:8 0.0873483
-16 *28:5 *342:16 0.000233137
-17 *318:14 *342:16 0.0363691
-*RES
-1 wbs_adr_i[4] *342:11 2.835
-2 *342:11 *342:13 263.07
-3 *342:13 *342:15 4.5
-4 *342:15 *342:16 129.51
-5 *342:16 *419:wbs_adr_i[4] 24.165
-*END
-
-*D_NET *343 0.149542
-*CONN
-*P wbs_adr_i[5] I
-*I *419:wbs_adr_i[5] I *D user_proj_example
-*CAP
-1 wbs_adr_i[5] 8.61527e-05
-2 *419:wbs_adr_i[5] 0.00108854
-3 *343:16 0.00807064
-4 *343:15 0.00698211
-5 *343:13 0.0258585
-6 *343:11 0.0259446
-7 *419:wbs_adr_i[5] *419:wbs_dat_i[4] 0
-8 *419:wbs_adr_i[5] *419:wbs_dat_i[5] 0
-9 *419:wbs_adr_i[5] *407:9 0.000421191
-10 *419:wbs_adr_i[5] *408:11 0.00157531
-11 *343:16 *344:16 0.079515
-12 *343:16 *356:16 0
-*RES
-1 wbs_adr_i[5] *343:11 1.215
-2 *343:11 *343:13 257.31
-3 *343:13 *343:15 4.5
-4 *343:15 *343:16 123.21
-5 *343:16 *419:wbs_adr_i[5] 19.035
-*END
-
-*D_NET *344 0.213605
-*CONN
-*P wbs_adr_i[6] I
-*I *419:wbs_adr_i[6] I *D user_proj_example
-*CAP
-1 wbs_adr_i[6] 0.000203572
-2 *419:wbs_adr_i[6] 0.00110784
-3 *344:16 0.00302558
-4 *344:15 0.00191774
-5 *344:13 0.0256695
-6 *344:11 0.025873
-7 *419:wbs_adr_i[6] *419:wbs_dat_i[5] 0
-8 *419:wbs_adr_i[6] *419:wbs_dat_i[6] 0
-9 *419:wbs_adr_i[6] *408:10 0.001606
-10 *344:11 *377:13 7.67196e-06
-11 *344:13 wbs_dat_o[5] 0.000486403
-12 *344:13 *407:13 0
-13 *344:16 *345:8 0.0739197
-14 *326:13 *419:wbs_adr_i[6] 0.000273122
-15 *343:16 *344:16 0.079515
-*RES
-1 wbs_adr_i[6] *344:11 2.295
-2 *344:11 *344:13 257.49
-3 *344:13 *344:15 4.5
-4 *344:15 *344:16 117.81
-5 *344:16 *419:wbs_adr_i[6] 18.855
-*END
-
-*D_NET *345 0.200812
-*CONN
-*P wbs_adr_i[7] I
-*I *419:wbs_adr_i[7] I *D user_proj_example
-*CAP
-1 wbs_adr_i[7] 0.0259227
-2 *419:wbs_adr_i[7] 0.00128267
-3 *345:8 0.00319801
-4 *345:7 0.00191534
-5 *345:5 0.0259227
-6 *419:wbs_adr_i[7] *419:wbs_dat_i[6] 0
-7 *419:wbs_adr_i[7] *419:wbs_dat_i[7] 0
-8 *419:wbs_adr_i[7] *409:7 0.00119683
-9 *419:wbs_adr_i[7] *410:9 0
-10 *345:5 *409:11 0
-11 *345:8 *346:14 0.067454
-12 *344:16 *345:8 0.0739197
-*RES
-1 wbs_adr_i[7] *345:5 257.625
-2 *345:5 *345:7 4.5
-3 *345:7 *345:8 109.71
-4 *345:8 *419:wbs_adr_i[7] 18.675
-*END
-
-*D_NET *346 0.179397
-*CONN
-*P wbs_adr_i[8] I
-*I *419:wbs_adr_i[8] I *D user_proj_example
-*CAP
-1 wbs_adr_i[8] 0.000938494
-2 *419:wbs_adr_i[8] 0.000928794
-3 *346:14 0.00332624
-4 *346:13 0.00239745
-5 *346:11 0.0252002
-6 *346:10 0.0261387
-7 *419:wbs_adr_i[8] *419:wbs_dat_i[8] 0
-8 *419:wbs_adr_i[8] *384:13 0.000242434
-9 *419:wbs_adr_i[8] *410:9 0.00102881
-10 *346:10 *410:14 0.000202829
-11 *346:10 *413:8 0
-12 *346:14 *351:16 0.0515385
-13 *345:8 *346:14 0.067454
-*RES
-1 wbs_adr_i[8] *346:10 19.035
-2 *346:10 *346:11 250.47
-3 *346:11 *346:13 4.5
-4 *346:13 *346:14 100.35
-5 *346:14 *419:wbs_adr_i[8] 18.495
-*END
-
-*D_NET *347 0.153672
-*CONN
-*P wbs_adr_i[9] I
-*I *419:wbs_adr_i[9] I *D user_proj_example
-*CAP
-1 wbs_adr_i[9] 0.000271935
-2 *419:wbs_adr_i[9] 0.0005771
-3 *347:16 0.00473954
-4 *347:15 0.00416244
-5 *347:13 0.0259896
-6 *347:11 0.0262616
-7 *419:wbs_adr_i[9] *419:wbs_dat_i[8] 0
-8 *419:wbs_adr_i[9] *419:wbs_dat_i[9] 0.000934701
-9 *419:wbs_adr_i[9] *411:7 0.00039012
-10 *419:wbs_adr_i[9] *412:13 0.000626032
-11 *347:13 wbs_dat_o[8] 0.000816297
-12 *321:16 *347:16 0.0369908
-13 *327:16 *347:16 0.0519118
-*RES
-1 wbs_adr_i[9] *347:11 2.835
-2 *347:11 *347:13 260.19
-3 *347:13 *347:15 4.5
-4 *347:15 *347:16 99.45
-5 *347:16 *419:wbs_adr_i[9] 15.525
-*END
-
-*D_NET *348 0.18673
-*CONN
-*P wbs_cyc_i I
-*I *419:wbs_cyc_i I *D user_proj_example
-*CAP
-1 wbs_cyc_i 0.00010579
-2 *419:wbs_cyc_i 0.00103184
-3 *348:16 0.010518
-4 *348:15 0.0094862
-5 *348:13 0.025505
-6 *348:11 0.0256108
-7 *419:wbs_cyc_i *419:wbs_stb_i 0.000490239
-8 *419:wbs_cyc_i *356:13 0.000675133
-9 *348:16 *349:16 0.1106
-10 *68:11 *348:13 0
-11 *315:11 *419:wbs_cyc_i 0.00270667
-*RES
-1 wbs_cyc_i *348:11 1.395
-2 *348:11 *348:13 254.61
-3 *348:13 *348:15 4.5
-4 *348:15 *348:16 170.91
-5 *348:16 *419:wbs_cyc_i 21.735
-*END
-
-*D_NET *349 0.267667
-*CONN
-*P wbs_dat_i[0] I
-*I *419:wbs_dat_i[0] I *D user_proj_example
-*CAP
-1 wbs_dat_i[0] 0.000271935
-2 *419:wbs_dat_i[0] 0.0011819
-3 *349:16 0.0039345
-4 *349:15 0.0027526
-5 *349:13 0.0255447
-6 *349:11 0.0258167
-7 *419:wbs_dat_i[0] *381:5 0
-8 *419:wbs_dat_i[0] *413:11 0.00681271
-9 *349:16 *406:14 0.0847374
-10 *349:16 *414:16 0.00497357
-11 *419:wbs_adr_i[0] *419:wbs_dat_i[0] 0.00102191
-12 *316:11 *349:13 1.87963e-05
-13 *348:16 *349:16 0.1106
-*RES
-1 wbs_dat_i[0] *349:11 2.835
-2 *349:11 *349:13 254.79
-3 *349:13 *349:15 4.5
-4 *349:15 *349:16 163.17
-5 *349:16 *419:wbs_dat_i[0] 22.275
-*END
-
-*D_NET *350 0.144962
-*CONN
-*P wbs_dat_i[10] I
-*I *419:wbs_dat_i[10] I *D user_proj_example
-*CAP
-1 wbs_dat_i[10] 0.000772387
-2 *419:wbs_dat_i[10] 0.00106381
-3 *350:14 0.00428783
-4 *350:13 0.00322403
-5 *350:11 0.0251106
-6 *350:10 0.025883
-7 *419:wbs_dat_i[10] *419:wbs_dat_i[11] 0
-8 *419:wbs_dat_i[10] *382:9 0.0027435
-9 *350:10 wbs_dat_o[10] 0
-10 *350:11 wbs_dat_o[10] 0
-11 *350:14 *354:8 0.0356231
-12 *350:14 *356:16 0.0240595
-13 *350:14 *406:14 0.00155424
-14 *350:14 *414:16 0.0187131
-15 *419:wbs_adr_i[10] *419:wbs_dat_i[10] 0
-16 *338:12 *350:10 0.00192726
-*RES
-1 wbs_dat_i[10] *350:10 17.775
-2 *350:10 *350:11 249.39
-3 *350:11 *350:13 4.5
-4 *350:13 *350:14 85.41
-5 *350:14 *419:wbs_dat_i[10] 20.745
-*END
-
-*D_NET *351 0.160319
-*CONN
-*P wbs_dat_i[11] I
-*I *419:wbs_dat_i[11] I *D user_proj_example
-*CAP
-1 wbs_dat_i[11] 0.000245505
-2 *419:wbs_dat_i[11] 0.000744755
-3 *351:16 0.00254973
-4 *351:15 0.00180497
-5 *351:13 0.0258248
-6 *351:11 0.0260703
-7 *419:wbs_dat_i[11] *383:9 0.00148325
-8 *419:wbs_dat_i[11] *384:13 0.000634131
-9 *351:16 *359:13 0.000407989
-10 *351:16 *384:14 0.0429591
-11 *419:wbs_adr_i[10] *419:wbs_dat_i[11] 0.00460318
-12 *419:wbs_adr_i[11] *419:wbs_dat_i[11] 0.000500596
-13 *419:wbs_dat_i[10] *419:wbs_dat_i[11] 0
-14 *318:10 *351:13 0.000595217
-15 *323:16 *419:wbs_dat_i[11] 0.000356699
-16 *346:14 *351:16 0.0515385
-*RES
-1 wbs_dat_i[11] *351:11 2.655
-2 *351:11 *351:13 258.03
-3 *351:13 *351:15 4.5
-4 *351:15 *351:16 79.65
-5 *351:16 *419:wbs_dat_i[11] 31.365
-*END
-
-*D_NET *352 0.143319
-*CONN
-*P wbs_dat_i[12] I
-*I *419:wbs_dat_i[12] I *D user_proj_example
-*CAP
-1 wbs_dat_i[12] 0.00330364
-2 *419:wbs_dat_i[12] 0.00030841
-3 *352:15 0.00793422
-4 *352:14 0.00762581
-5 *352:12 0.00735965
-6 *352:11 0.00735965
-7 *352:9 0.0117538
-8 *352:7 0.0150575
-9 *419:wbs_dat_i[12] *384:13 0.000459167
-10 *419:wbs_dat_i[12] *393:11 0.000163669
-11 *352:15 *393:11 0.0788678
-12 *419:wbs_adr_i[12] *419:wbs_dat_i[12] 0.000424643
-13 *419:wbs_adr_i[13] *419:wbs_dat_i[12] 0
-14 *419:wbs_adr_i[13] *352:15 0.00270053
-15 *67:11 *352:9 0
-16 *67:14 *352:12 0
-17 *318:11 *352:7 0
-18 *318:11 *352:9 0
-*RES
-1 wbs_dat_i[12] *352:7 32.265
-2 *352:7 *352:9 117.54
-3 *352:9 *352:11 4.5
-4 *352:11 *352:12 75.87
-5 *352:12 *352:14 4.5
-6 *352:14 *352:15 115.65
-7 *352:15 *419:wbs_dat_i[12] 6.615
-*END
-
-*D_NET *353 0.114641
-*CONN
-*P wbs_dat_i[13] I
-*I *419:wbs_dat_i[13] I *D user_proj_example
-*CAP
-1 wbs_dat_i[13] 0.000187838
-2 *419:wbs_dat_i[13] 0.00223675
-3 *353:16 0.00623746
-4 *353:15 0.00400071
-5 *353:13 0.0237097
-6 *353:11 0.0238976
-7 *419:wbs_dat_i[13] *385:9 0.00485482
-8 *419:wbs_dat_i[13] *385:11 0.00257778
-9 *419:wbs_adr_i[13] *419:wbs_dat_i[13] 0
-10 *319:11 *353:13 0
-11 *320:16 *353:16 0.0469379
-*RES
-1 wbs_dat_i[13] *353:11 2.115
-2 *353:11 *353:13 236.07
-3 *353:13 *353:15 4.5
-4 *353:15 *353:16 70.47
-5 *353:16 *419:wbs_dat_i[13] 40.005
-*END
-
-*D_NET *354 0.117504
-*CONN
-*P wbs_dat_i[14] I
-*I *419:wbs_dat_i[14] I *D user_proj_example
-*CAP
-1 wbs_dat_i[14] 0.025702
-2 *419:wbs_dat_i[14] 0.000806638
-3 *354:8 0.00328358
-4 *354:7 0.00247694
-5 *354:5 0.025702
-6 *419:wbs_dat_i[14] *386:9 0.00276805
-7 *354:8 *356:16 0.00248671
-8 *354:8 *406:14 0.0177184
-9 *419:wbs_adr_i[14] *419:wbs_dat_i[14] 0.000936364
-10 *350:14 *354:8 0.0356231
-*RES
-1 wbs_dat_i[14] *354:5 255.105
-2 *354:5 *354:7 4.5
-3 *354:7 *354:8 62.37
-4 *354:8 *419:wbs_dat_i[14] 20.925
-*END
-
-*D_NET *355 0.16236
-*CONN
-*P wbs_dat_i[15] I
-*I *419:wbs_dat_i[15] I *D user_proj_example
-*CAP
-1 wbs_dat_i[15] 0.000721044
-2 *419:wbs_dat_i[15] 0.0153497
-3 *355:10 0.0153497
-4 *355:8 0.00121075
-5 *355:7 0.0019318
-6 *419:wbs_dat_i[15] *387:7 0.000818215
-7 *419:wbs_dat_i[15] *394:11 0.0581229
-8 *355:7 *387:11 0
-9 *355:8 *361:10 0.000209823
-10 *355:8 *386:14 0.0368661
-11 *355:8 *388:16 0.030276
-12 *355:8 *413:8 0
-13 *419:wbs_adr_i[15] *419:wbs_dat_i[15] 0.000583453
-14 *322:11 *355:7 0.000920636
-*RES
-1 wbs_dat_i[15] *355:7 11.745
-2 *355:7 *355:8 56.07
-3 *355:8 *355:10 4.5
-4 *355:10 *419:wbs_dat_i[15] 263.925
-*END
-
-*D_NET *356 0.095816
-*CONN
-*P wbs_dat_i[16] I
-*I *419:wbs_dat_i[16] I *D user_proj_example
-*CAP
-1 wbs_dat_i[16] 0.000187838
-2 *419:wbs_dat_i[16] 0.000791386
-3 *356:16 0.00405504
-4 *356:15 0.00326365
-5 *356:13 0.0246573
-6 *356:11 0.0248451
-7 *419:wbs_dat_i[16] *387:7 0
-8 *419:wbs_dat_i[16] *388:12 0.00148478
-9 *356:16 *359:13 0
-10 *419:wbs_adr_i[16] *419:wbs_dat_i[16] 0.000676028
-11 *419:wbs_adr_i[17] *419:wbs_dat_i[16] 0.00288466
-12 *419:wbs_cyc_i *356:13 0.000675133
-13 *315:11 *356:13 0.00574886
-14 *343:16 *356:16 0
-15 *350:14 *356:16 0.0240595
-16 *354:8 *356:16 0.00248671
-*RES
-1 wbs_dat_i[16] *356:11 2.115
-2 *356:11 *356:13 255.51
-3 *356:13 *356:15 4.5
-4 *356:15 *356:16 51.21
-5 *356:16 *419:wbs_dat_i[16] 20.925
-*END
-
-*D_NET *357 0.184401
-*CONN
-*P wbs_dat_i[17] I
-*I *419:wbs_dat_i[17] I *D user_proj_example
-*CAP
-1 wbs_dat_i[17] 0.00234997
-2 *419:wbs_dat_i[17] 0.000412325
-3 *357:17 0.0120401
-4 *357:16 0.0128904
-5 *357:11 0.00720232
-6 *357:10 0.00828965
-7 *419:wbs_dat_i[17] *389:9 0.00144233
-8 *357:10 wbs_dat_o[18] 0.0124959
-9 *357:10 *358:10 0.000704589
-10 *357:10 *410:14 0.000596807
-11 *357:11 *385:11 0
-12 *357:11 *393:11 0
-13 *357:17 *361:11 0
-14 *357:17 *362:11 0
-15 *357:17 *389:9 0.000294603
-16 *419:wbs_adr_i[17] *419:wbs_dat_i[17] 0
-17 *419:wbs_adr_i[17] *357:17 0
-18 *419:wbs_adr_i[18] *357:17 0.00175381
-19 *325:13 *357:10 0.00192726
-20 *325:17 *357:17 0.121524
-21 *329:16 *357:11 0
-22 *341:8 *357:10 0.000476597
-*RES
-1 wbs_dat_i[17] *357:10 45.315
-2 *357:10 *357:11 55.71
-3 *357:11 *357:16 21.51
-4 *357:16 *357:17 203.31
-5 *357:17 *419:wbs_dat_i[17] 6.615
-*END
-
-*D_NET *358 0.095205
-*CONN
-*P wbs_dat_i[18] I
-*I *419:wbs_dat_i[18] I *D user_proj_example
-*CAP
-1 wbs_dat_i[18] 0.00082736
-2 *419:wbs_dat_i[18] 0.00206634
-3 *358:11 0.0197407
-4 *358:10 0.0185017
-5 *419:wbs_dat_i[18] *359:13 0.0131174
-6 *419:wbs_dat_i[18] *390:9 0.000554939
-7 *419:wbs_dat_i[18] *390:11 0.00558519
-8 *358:10 wbs_dat_o[18] 0.00876594
-9 *358:10 *383:14 0.000547093
-10 *358:10 *410:14 0.00466273
-11 *358:10 *412:16 0.0011605
-12 *358:11 *382:9 0.00243048
-13 *358:11 *382:11 0.0162607
-14 *358:11 *383:11 0
-15 *419:wbs_adr_i[18] *419:wbs_dat_i[18] 0.000217884
-16 *325:13 *358:10 6.13758e-05
-17 *328:15 *358:11 0
-18 *357:10 *358:10 0.000704589
-*RES
-1 wbs_dat_i[18] *358:10 31.095
-2 *358:10 *358:11 251.19
-3 *358:11 *419:wbs_dat_i[18] 43.605
-*END
-
-*D_NET *359 0.0790191
-*CONN
-*P wbs_dat_i[19] I
-*I *419:wbs_dat_i[19] I *D user_proj_example
-*CAP
-1 wbs_dat_i[19] 0.025549
-2 *419:wbs_dat_i[19] 0.000623942
-3 *359:13 0.00271166
-4 *359:5 0.0276367
-5 *419:wbs_dat_i[19] *391:9 0.00156508
-6 *419:wbs_dat_i[19] *393:10 0
-7 *419:wbs_dat_i[19] *394:10 0
-8 *419:wbs_dat_i[19] *395:10 0.000103616
-9 *419:wbs_dat_i[19] *395:11 0.000102293
-10 *359:5 *419:wbs_dat_i[8] 0.0017799
-11 *419:wbs_adr_i[18] *359:13 0.00484868
-12 *419:wbs_adr_i[19] *419:wbs_dat_i[19] 0.000572806
-13 *419:wbs_dat_i[18] *359:13 0.0131174
-14 *351:16 *359:13 0.000407989
-15 *356:16 *359:13 0
-*RES
-1 wbs_dat_i[19] *359:5 257.265
-2 *359:5 *359:13 46.26
-3 *359:13 *419:wbs_dat_i[19] 15.975
-*END
-
-*D_NET *360 0.164983
-*CONN
-*P wbs_dat_i[1] I
-*I *419:wbs_dat_i[1] I *D user_proj_example
-*CAP
-1 wbs_dat_i[1] 0.000125413
-2 *419:wbs_dat_i[1] 0.000988536
-3 *360:16 0.010166
-4 *360:15 0.00917747
-5 *360:13 0.0252537
-6 *360:11 0.0253791
-7 *419:wbs_dat_i[1] *392:9 0.00320995
-8 *360:16 *374:16 0.089711
-9 *419:wbs_adr_i[1] *419:wbs_dat_i[1] 0.000972167
-*RES
-1 wbs_dat_i[1] *360:11 1.575
-2 *360:11 *360:13 251.91
-3 *360:13 *360:15 4.5
-4 *360:15 *360:16 154.17
-5 *360:16 *419:wbs_dat_i[1] 24.165
-*END
-
-*D_NET *361 0.11471
-*CONN
-*P wbs_dat_i[20] I
-*I *419:wbs_dat_i[20] I *D user_proj_example
-*CAP
-1 wbs_dat_i[20] 0.00106237
-2 *419:wbs_dat_i[20] 0.00160564
-3 *361:11 0.0165375
-4 *361:10 0.0159942
-5 *419:wbs_dat_i[20] *393:10 0.000431548
-6 *361:10 wbs_dat_o[18] 0.00621676
-7 *361:10 *362:10 0.00304632
-8 *361:10 *386:14 0.000734347
-9 *361:10 *388:16 8.08207e-05
-10 *361:10 *393:11 0
-11 *361:11 *362:11 0.0533765
-12 *361:11 *388:13 0
-13 *419:wbs_adr_i[17] *361:11 0.000438836
-14 *419:wbs_adr_i[20] *419:wbs_dat_i[20] 0
-15 *419:wbs_adr_i[21] *419:wbs_dat_i[20] 0
-16 *329:19 *419:wbs_dat_i[20] 0.00742646
-17 *331:13 *419:wbs_dat_i[20] 0.00754921
-18 *355:8 *361:10 0.000209823
-19 *357:17 *361:11 0
-*RES
-1 wbs_dat_i[20] *361:10 28.935
-2 *361:10 *361:11 247.77
-3 *361:11 *419:wbs_dat_i[20] 36.135
-*END
-
-*D_NET *362 0.09907
-*CONN
-*P wbs_dat_i[21] I
-*I *419:wbs_dat_i[21] I *D user_proj_example
-*CAP
-1 wbs_dat_i[21] 0.00044692
-2 *419:wbs_dat_i[21] 0.00044271
-3 *362:19 0.00400012
-4 *362:11 0.017405
-5 *362:10 0.0142945
-6 *419:wbs_dat_i[21] *394:10 0.000486786
-7 *362:10 wbs_dat_o[18] 0.003295
-8 *362:10 *394:11 0.00140141
-9 *362:19 *364:13 0.000797884
-10 *362:19 *364:25 9.32547e-06
-11 *362:19 *394:10 6.75133e-05
-12 *419:wbs_adr_i[21] *419:wbs_dat_i[21] 0
-13 *419:wbs_adr_i[22] *362:19 0
-14 *325:17 *362:11 0
-15 *330:16 *362:11 0
-16 *357:17 *362:11 0
-17 *361:10 *362:10 0.00304632
-18 *361:11 *362:11 0.0533765
-*RES
-1 wbs_dat_i[21] *362:10 19.935
-2 *362:10 *362:11 234.99
-3 *362:11 *362:19 45.27
-4 *362:19 *419:wbs_dat_i[21] 6.345
-*END
-
-*D_NET *363 0.0950924
-*CONN
-*P wbs_dat_i[22] I
-*I *419:wbs_dat_i[22] I *D user_proj_example
-*CAP
-1 wbs_dat_i[22] 0.0143507
-2 *419:wbs_dat_i[22] 0.000379046
-3 *363:14 0.00279175
-4 *363:5 0.0167634
-5 *419:wbs_dat_i[22] *395:10 0.000417739
-6 *363:5 *390:11 0.0531514
-7 *363:14 *390:9 0.000184127
-8 *363:14 *390:11 0.00255988
-9 *363:14 *393:10 0.00404104
-10 *363:14 *395:11 0
-11 *419:wbs_adr_i[22] *419:wbs_dat_i[22] 0
-12 *419:wbs_adr_i[23] *363:14 0.000453321
-*RES
-1 wbs_dat_i[22] *363:5 239.715
-2 *363:5 *363:14 45.9
-3 *363:14 *419:wbs_dat_i[22] 5.445
-*END
-
-*D_NET *364 0.0902672
-*CONN
-*P wbs_dat_i[23] I
-*I *419:wbs_dat_i[23] I *D user_proj_example
-*CAP
-1 wbs_dat_i[23] 0.000187838
-2 *419:wbs_dat_i[23] 0.000582022
-3 *364:25 0.00274069
-4 *364:13 0.0173227
-5 *364:11 0.0153519
-6 *419:wbs_dat_i[23] *396:9 0.00231387
-7 *364:25 *396:11 0.000920637
-8 *419:wbs_adr_i[22] *364:13 0
-9 *419:wbs_adr_i[23] *419:wbs_dat_i[23] 0.000285014
-10 *330:16 *364:13 0
-11 *330:17 *364:13 0.0497553
-12 *362:19 *364:13 0.000797884
-13 *362:19 *364:25 9.32547e-06
-*RES
-1 wbs_dat_i[23] *364:11 2.115
-2 *364:11 *364:13 242.19
-3 *364:13 *364:25 46.89
-4 *364:25 *419:wbs_dat_i[23] 15.705
-*END
-
-*D_NET *365 0.061483
-*CONN
-*P wbs_dat_i[24] I
-*I *419:wbs_dat_i[24] I *D user_proj_example
-*CAP
-1 wbs_dat_i[24] 0.0294545
-2 *419:wbs_dat_i[24] 0.00070864
-3 *365:5 0.0301631
-4 *419:wbs_dat_i[24] *397:14 0.000721638
-5 *419:wbs_adr_i[24] *419:wbs_dat_i[24] 0
-6 *419:wbs_adr_i[25] *419:wbs_dat_i[24] 0.000435078
-7 *333:11 *365:5 0
-*RES
-1 wbs_dat_i[24] *365:5 264.105
-2 *365:5 *419:wbs_dat_i[24] 18.495
-*END
-
-*D_NET *366 0.21046
-*CONN
-*P wbs_dat_i[25] I
-*I *419:wbs_dat_i[25] I *D user_proj_example
-*CAP
-1 wbs_dat_i[25] 0.000125413
-2 *419:wbs_dat_i[25] 0.000538418
-3 *366:13 0.0155133
-4 *366:11 0.0151003
-5 *419:wbs_dat_i[25] *419:wbs_dat_i[26] 0.000708734
-6 *419:wbs_dat_i[25] *397:14 0.000207232
-7 *419:wbs_dat_i[25] *398:10 0.00241405
-8 *419:wbs_dat_i[25] *400:10 0.00105689
-9 *366:13 *369:15 0.000736509
-10 *419:wbs_adr_i[25] *419:wbs_dat_i[25] 0.000486786
-11 *419:wbs_adr_i[26] *419:wbs_dat_i[25] 0.000262926
-12 *419:wbs_adr_i[28] *366:13 0.000168783
-13 *334:11 *366:13 0
-14 *337:19 *366:13 0.173141
-*RES
-1 wbs_dat_i[25] *366:11 1.575
-2 *366:11 *366:13 264.87
-3 *366:13 *419:wbs_dat_i[25] 23.175
-*END
-
-*D_NET *367 0.103361
-*CONN
-*P wbs_dat_i[26] I
-*I *419:wbs_dat_i[26] I *D user_proj_example
-*CAP
-1 wbs_dat_i[26] 0.000504708
-2 *419:wbs_dat_i[26] 0.000694078
-3 *367:11 0.00888234
-4 *367:10 0.00869297
-5 *419:wbs_dat_i[26] *419:wbs_dat_i[29] 0.000104911
-6 *419:wbs_dat_i[26] *399:9 0.00131958
-7 *419:wbs_dat_i[26] *400:10 0.000398922
-8 *419:wbs_dat_i[26] *401:10 0.00379236
-9 *367:10 wbs_dat_o[26] 0.000479882
-10 *367:10 *368:20 2.68519e-05
-11 *367:11 *419:wbs_dat_i[31] 0
-12 *367:11 *370:15 0.0507578
-13 *367:11 *404:9 0.00351069
-14 *367:11 *404:11 0.0178626
-15 *367:11 *405:13 0
-16 *419:wbs_adr_i[26] *419:wbs_dat_i[26] 0.000445358
-17 *419:wbs_adr_i[31] *419:wbs_dat_i[26] 0.000186509
-18 *419:wbs_adr_i[31] *367:11 0.00014321
-19 *419:wbs_dat_i[25] *419:wbs_dat_i[26] 0.000708734
-20 *339:20 *367:10 0.00242462
-21 *340:8 *367:10 0.00242462
-22 *340:11 *367:11 0
-*RES
-1 wbs_dat_i[26] *367:10 19.035
-2 *367:10 *367:11 258.93
-3 *367:11 *419:wbs_dat_i[26] 26.595
-*END
-
-*D_NET *368 0.122709
-*CONN
-*P wbs_dat_i[27] I
-*I *419:wbs_dat_i[27] I *D user_proj_example
-*CAP
-1 wbs_dat_i[27] 0.00111434
-2 *419:wbs_dat_i[27] 0.00750078
-3 *368:20 0.00861512
-4 *419:wbs_dat_i[27] *398:11 0
-5 *419:wbs_dat_i[27] *400:10 0.000500596
-6 *368:20 wbs_dat_o[26] 0.000675133
-7 *368:20 *402:20 0.00540877
-8 *419:wbs_adr_i[27] *419:wbs_dat_i[27] 0
-9 *419:wbs_adr_i[28] *419:wbs_dat_i[27] 0
-10 *159:11 *368:20 0.000552382
-11 *333:10 *419:wbs_dat_i[27] 0.000184127
-12 *333:10 *368:20 0.000186509
-13 *334:10 *368:20 0.000142991
-14 *334:11 *419:wbs_dat_i[27] 0.0197062
-15 *336:10 *368:20 0.00882811
-16 *336:11 *419:wbs_dat_i[27] 0.0574273
-17 *337:15 *368:20 0.00590613
-18 *339:20 *368:20 0.00593411
-19 *367:10 *368:20 2.68519e-05
-*RES
-1 wbs_dat_i[27] *368:20 47.475
-2 *368:20 *419:wbs_dat_i[27] 264.105
-*END
-
-*D_NET *369 0.110894
-*CONN
-*P wbs_dat_i[28] I
-*I *419:wbs_dat_i[28] I *D user_proj_example
-*CAP
-1 wbs_dat_i[28] 0.00219533
-2 *419:wbs_dat_i[28] 0.000146375
-3 *369:15 0.0156839
-4 *369:14 0.0177328
-5 *419:wbs_dat_i[28] *401:10 0.000127738
-6 *369:14 *401:11 0
-7 *369:15 *401:10 0.000393828
-8 *419:wbs_adr_i[28] *419:wbs_dat_i[28] 0
-9 *419:wbs_adr_i[28] *369:15 0
-10 *419:wbs_adr_i[29] *369:15 0.000196402
-11 *337:15 *369:14 0.0143861
-12 *337:18 *369:14 0.00155424
-13 *337:19 *369:15 0.0577137
-14 *339:20 *369:14 2.71992e-05
-15 *366:13 *369:15 0.000736509
-*RES
-1 wbs_dat_i[28] *369:14 43.515
-2 *369:14 *369:15 263.88
-3 *369:15 *419:wbs_dat_i[28] 2.025
-*END
-
-*D_NET *370 0.113621
-*CONN
-*P wbs_dat_i[29] I
-*I *419:wbs_dat_i[29] I *D user_proj_example
-*CAP
-1 wbs_dat_i[29] 0.00270397
-2 *419:wbs_dat_i[29] 0.000706488
-3 *370:15 0.0104354
-4 *370:14 0.0129536
-5 *370:11 0.00592866
-6 *419:wbs_dat_i[29] *400:10 0.000683868
-7 *419:wbs_dat_i[29] *402:9 0.00152417
-8 *370:15 *419:wbs_dat_i[31] 0
-9 *370:15 *405:13 0.00746022
-10 *419:wbs_adr_i[29] *419:wbs_dat_i[29] 0
-11 *419:wbs_adr_i[31] *419:wbs_dat_i[29] 0.000393741
-12 *419:wbs_dat_i[26] *419:wbs_dat_i[29] 0.000104911
-13 *117:11 *370:11 0.00908361
-14 *180:9 *370:11 0.0108635
-15 *244:16 *370:14 2.07232e-05
-16 *367:11 *370:15 0.0507578
-*RES
-1 wbs_dat_i[29] *370:11 46.125
-2 *370:11 *370:14 35.73
-3 *370:14 *370:15 223.29
-4 *370:15 *419:wbs_dat_i[29] 19.755
-*END
-
-*D_NET *371 0.0827699
-*CONN
-*P wbs_dat_i[2] I
-*I *419:wbs_dat_i[2] I *D user_proj_example
-*CAP
-1 wbs_dat_i[2] 0.00066129
-2 *419:wbs_dat_i[2] 0.000134844
-3 *371:14 0.0135495
-4 *371:13 0.0134146
-5 *371:11 0.0263018
-6 *371:10 0.0269631
-7 *419:wbs_dat_i[2] *403:7 0.000238215
-8 *371:10 *417:8 0.000211377
-9 *371:11 wbs_dat_o[2] 0
-10 *371:14 *419:wbs_sel_i[1] 0
-11 *419:wbs_adr_i[2] *419:wbs_dat_i[2] 0.000238215
-12 *338:10 *371:10 0.00105689
-*RES
-1 wbs_dat_i[2] *371:10 16.695
-2 *371:10 *371:11 261.99
-3 *371:11 *371:13 4.5
-4 *371:13 *371:14 143.19
-5 *371:14 *419:wbs_dat_i[2] 7.605
-*END
-
-*D_NET *372 0.209046
-*CONN
-*P wbs_dat_i[30] I
-*I *419:wbs_dat_i[30] I *D user_proj_example
-*CAP
-1 wbs_dat_i[30] 0.000125413
-2 *419:wbs_dat_i[30] 0.000645876
-3 *372:19 0.00450359
-4 *372:13 0.0195722
-5 *372:11 0.0158399
-6 *419:wbs_dat_i[30] *401:10 0.000384675
-7 *419:wbs_dat_i[30] *404:9 0.00107408
-8 *419:la_data_in[0] *372:19 0.000296905
-9 *419:la_data_in[10] *372:19 0
-10 *419:la_data_in[2] *372:19 0
-11 *419:la_data_in[8] *372:19 0.00105689
-12 *419:wbs_adr_i[30] *419:wbs_dat_i[30] 0
-13 *116:11 *372:13 0
-14 *120:19 *372:13 0.164917
-15 *179:17 *372:19 0.000384877
-16 *183:5 *372:13 0.000245503
-*RES
-1 wbs_dat_i[30] *372:11 1.575
-2 *372:11 *372:13 262.71
-3 *372:13 *372:19 48.24
-4 *372:19 *419:wbs_dat_i[30] 18.675
-*END
-
-*D_NET *373 0.201261
-*CONN
-*P wbs_dat_i[31] I
-*I *419:wbs_dat_i[31] I *D user_proj_example
-*CAP
-1 wbs_dat_i[31] 0.000226282
-2 *419:wbs_dat_i[31] 0.0046476
-3 *373:18 0.0046476
-4 *373:16 0.0048035
-5 *373:15 0.0048035
-6 *373:13 0.0120271
-7 *373:11 0.0122534
-8 *419:wbs_dat_i[31] *405:12 0.00152826
-9 *419:wbs_dat_i[31] *405:13 0.00102293
-10 *419:la_data_in[0] *419:wbs_dat_i[31] 0
-11 *419:wbs_adr_i[31] *419:wbs_dat_i[31] 0
-12 *115:11 *419:wbs_dat_i[31] 0.0448657
-13 *123:19 *373:13 0.110415
-14 *250:19 *373:13 2.04586e-05
-15 *276:19 *373:13 0
-16 *340:7 *373:13 0
-17 *367:11 *419:wbs_dat_i[31] 0
-18 *370:15 *419:wbs_dat_i[31] 0
-*RES
-1 wbs_dat_i[31] *373:11 2.475
-2 *373:11 *373:13 189.81
-3 *373:13 *373:15 4.5
-4 *373:15 *373:16 45.81
-5 *373:16 *373:18 4.5
-6 *373:18 *419:wbs_dat_i[31] 81.405
-*END
-
-*D_NET *374 0.235046
-*CONN
-*P wbs_dat_i[3] I
-*I *419:wbs_dat_i[3] I *D user_proj_example
-*CAP
-1 wbs_dat_i[3] 0.00014502
-2 *419:wbs_dat_i[3] 0.00138585
-3 *374:16 0.00379628
-4 *374:15 0.00241043
-5 *374:13 0.0253011
-6 *374:11 0.0254461
-7 *419:wbs_dat_i[3] *406:13 0
-8 *374:16 *375:8 0.0851102
-9 *419:wbs_adr_i[3] *419:wbs_dat_i[3] 0.00147072
-10 *419:wbs_adr_i[4] *419:wbs_dat_i[3] 0.000269286
-11 *341:7 *374:13 0
-12 *360:16 *374:16 0.089711
-*RES
-1 wbs_dat_i[3] *374:11 1.755
-2 *374:11 *374:13 252.09
-3 *374:13 *374:15 4.5
-4 *374:15 *374:16 136.71
-5 *374:16 *419:wbs_dat_i[3] 24.255
-*END
-
-*D_NET *375 0.215703
-*CONN
-*P wbs_dat_i[4] I
-*I *419:wbs_dat_i[4] I *D user_proj_example
-*CAP
-1 wbs_dat_i[4] 0.0253316
-2 *419:wbs_dat_i[4] 0.00125744
-3 *375:8 0.00404579
-4 *375:7 0.00278835
-5 *375:5 0.0253316
-6 *419:wbs_dat_i[4] *419:wbs_sel_i[3] 0
-7 *419:wbs_dat_i[4] *407:9 0.00123774
-8 *419:wbs_dat_i[4] *408:11 0.000918335
-9 *375:5 *416:11 0
-10 *375:8 *378:12 0.0693191
-11 *419:wbs_adr_i[4] *419:wbs_dat_i[4] 0.000362501
-12 *419:wbs_adr_i[5] *419:wbs_dat_i[4] 0
-13 *374:16 *375:8 0.0851102
-*RES
-1 wbs_dat_i[4] *375:5 252.225
-2 *375:5 *375:7 4.5
-3 *375:7 *375:8 127.35
-4 *375:8 *419:wbs_dat_i[4] 23.445
-*END
-
-*D_NET *376 0.19637
-*CONN
-*P wbs_dat_i[5] I
-*I *419:wbs_dat_i[5] I *D user_proj_example
-*CAP
-1 wbs_dat_i[5] 0.0014798
-2 *419:wbs_dat_i[5] 0.00208127
-3 *376:14 0.00574002
-4 *376:13 0.00365874
-5 *376:11 0.0242971
-6 *376:10 0.0257769
-7 *419:wbs_dat_i[5] *408:10 0.000542025
-8 *419:wbs_dat_i[5] *408:11 0
-9 *376:10 *413:8 0
-10 *376:10 *417:8 0.00150448
-11 *376:14 *377:16 0.0759018
-12 *376:14 *379:14 0.0553874
-13 *419:wbs_adr_i[5] *419:wbs_dat_i[5] 0
-14 *419:wbs_adr_i[6] *419:wbs_dat_i[5] 0
-*RES
-1 wbs_dat_i[5] *376:10 27.135
-2 *376:10 *376:11 242.19
-3 *376:11 *376:13 4.5
-4 *376:13 *376:14 109.89
-5 *376:14 *419:wbs_dat_i[5] 26.325
-*END
-
-*D_NET *377 0.150055
-*CONN
-*P wbs_dat_i[6] I
-*I *419:wbs_dat_i[6] I *D user_proj_example
-*CAP
-1 wbs_dat_i[6] 0.000245505
-2 *419:wbs_dat_i[6] 0.00149941
-3 *377:16 0.00914297
-4 *377:15 0.00764357
-5 *377:13 0.0250134
-6 *377:11 0.0252589
-7 *419:wbs_dat_i[6] *409:7 0.000403929
-8 *377:16 *379:14 0.000580213
-9 *419:wbs_adr_i[6] *419:wbs_dat_i[6] 0
-10 *419:wbs_adr_i[7] *419:wbs_dat_i[6] 0
-11 *326:13 *419:wbs_dat_i[6] 0.00435768
-12 *344:11 *377:13 7.67196e-06
-13 *376:14 *377:16 0.0759018
-*RES
-1 wbs_dat_i[6] *377:11 2.655
-2 *377:11 *377:13 249.21
-3 *377:13 *377:15 4.5
-4 *377:15 *377:16 116.37
-5 *377:16 *419:wbs_dat_i[6] 26.865
-*END
-
-*D_NET *378 0.186056
-*CONN
-*P wbs_dat_i[7] I
-*I *419:wbs_dat_i[7] I *D user_proj_example
-*CAP
-1 wbs_dat_i[7] 0.00327812
-2 *419:wbs_dat_i[7] 0.00119726
-3 *378:12 0.00418063
-4 *378:11 0.00298337
-5 *378:9 0.0221373
-6 *378:7 0.0254154
-7 *419:wbs_dat_i[7] *410:9 0.00426562
-8 *378:12 *417:14 0.0532795
-9 *419:wbs_adr_i[7] *419:wbs_dat_i[7] 0
-10 *375:8 *378:12 0.0693191
-*RES
-1 wbs_dat_i[7] *378:7 32.265
-2 *378:7 *378:9 220.68
-3 *378:9 *378:11 4.5
-4 *378:11 *378:12 108.45
-5 *378:12 *419:wbs_dat_i[7] 23.265
-*END
-
-*D_NET *379 0.131442
-*CONN
-*P wbs_dat_i[8] I
-*I *419:wbs_dat_i[8] I *D user_proj_example
-*CAP
-1 wbs_dat_i[8] 0.00133042
-2 *419:wbs_dat_i[8] 0.00148295
-3 *379:14 0.00744711
-4 *379:13 0.00596416
-5 *379:11 0.0244579
-6 *379:10 0.0257883
-7 *419:wbs_dat_i[8] *384:13 0.00161623
-8 *419:wbs_dat_i[8] *411:7 0.00039012
-9 *379:10 wbs_dat_o[8] 0.00317066
-10 *379:11 wbs_dat_o[9] 9.8457e-05
-11 *419:wbs_adr_i[8] *419:wbs_dat_i[8] 0
-12 *419:wbs_adr_i[9] *419:wbs_dat_i[8] 0
-13 *338:12 *379:10 0.00194798
-14 *359:5 *419:wbs_dat_i[8] 0.0017799
-15 *376:14 *379:14 0.0553874
-16 *377:16 *379:14 0.000580213
-*RES
-1 wbs_dat_i[8] *379:10 27.855
-2 *379:10 *379:11 243.81
-3 *379:11 *379:13 4.5
-4 *379:13 *379:14 88.29
-5 *379:14 *419:wbs_dat_i[8] 26.145
-*END
-
-*D_NET *380 0.131081
-*CONN
-*P wbs_dat_i[9] I
-*I *419:wbs_dat_i[9] I *D user_proj_example
-*CAP
-1 wbs_dat_i[9] 0.0247693
-2 *419:wbs_dat_i[9] 0.000750533
-3 *380:8 0.00665073
-4 *380:7 0.00590019
-5 *380:5 0.0247693
-6 *419:wbs_dat_i[9] wbs_dat_o[19] 0.000593299
-7 *419:wbs_dat_i[9] *412:12 0.000662347
-8 *419:wbs_dat_i[9] *412:13 0.0123365
-9 *380:5 *411:11 0
-10 *380:8 *415:14 0.0525333
-11 *419:wbs_adr_i[10] *419:wbs_dat_i[9] 0.00118072
-12 *419:wbs_adr_i[9] *419:wbs_dat_i[9] 0.000934701
-*RES
-1 wbs_dat_i[9] *380:5 246.645
-2 *380:5 *380:7 4.5
-3 *380:7 *380:8 94.77
-4 *380:8 *419:wbs_dat_i[9] 30.375
-*END
-
-*D_NET *381 0.0852526
-*CONN
-*P wbs_dat_o[0] O
-*I *419:wbs_dat_o[0] O *D user_proj_example
-*CAP
-1 wbs_dat_o[0] 0.00119134
-2 *419:wbs_dat_o[0] 0.0260072
-3 *381:8 0.0163688
-4 *381:7 0.0151775
-5 *381:5 0.0260072
-6 *381:5 *419:wbs_sel_i[0] 0.000500596
-7 *381:5 *413:11 0
-8 *419:wbs_adr_i[1] *381:5 0
-9 *419:wbs_dat_i[0] *381:5 0
-*RES
-1 *419:wbs_dat_o[0] *381:5 259.605
-2 *381:5 *381:7 4.5
-3 *381:7 *381:8 159.57
-4 *381:8 wbs_dat_o[0] 16.065
-*END
-
-*D_NET *382 0.0861607
-*CONN
-*P wbs_dat_o[10] O
-*I *419:wbs_dat_o[10] O *D user_proj_example
-*CAP
-1 wbs_dat_o[10] 0.0030143
-2 *419:wbs_dat_o[10] 0.00203445
-3 *382:14 0.0107101
-4 *382:13 0.00769577
-5 *382:11 0.0143651
-6 *382:9 0.0163996
-7 *419:wbs_adr_i[10] *382:9 0
-8 *419:wbs_adr_i[11] *382:9 0
-9 *419:wbs_dat_i[10] *382:9 0.0027435
-10 *317:11 wbs_dat_o[10] 0
-11 *325:16 *382:14 0.0105067
-12 *350:10 wbs_dat_o[10] 0
-13 *350:11 wbs_dat_o[10] 0
-14 *358:11 *382:9 0.00243048
-15 *358:11 *382:11 0.0162607
-*RES
-1 *419:wbs_dat_o[10] *382:9 32.535
-2 *382:9 *382:11 212.04
-3 *382:11 *382:13 4.5
-4 *382:13 *382:14 86.85
-5 *382:14 wbs_dat_o[10] 34.245
-*END
-
-*D_NET *383 0.15384
-*CONN
-*P wbs_dat_o[11] O
-*I *419:wbs_dat_o[11] O *D user_proj_example
-*CAP
-1 wbs_dat_o[11] 0.000788076
-2 *419:wbs_dat_o[11] 0.00306965
-3 *383:14 0.00236147
-4 *383:13 0.00157339
-5 *383:11 0.0233517
-6 *383:9 0.0264214
-7 *383:14 wbs_dat_o[18] 0.000181328
-8 *383:14 *386:14 0.0353744
-9 *383:14 *412:16 0.0505437
-10 *419:wbs_adr_i[11] *383:9 0
-11 *419:wbs_adr_i[12] *383:9 0
-12 *419:wbs_dat_i[11] *383:9 0.00148325
-13 *319:10 *383:14 0.00814424
-14 *358:10 *383:14 0.000547093
-15 *358:11 *383:11 0
-*RES
-1 *419:wbs_dat_o[11] *383:9 32.535
-2 *383:9 *383:11 232.92
-3 *383:11 *383:13 4.5
-4 *383:13 *383:14 78.93
-5 *383:14 wbs_dat_o[11] 11.385
-*END
-
-*D_NET *384 0.117267
-*CONN
-*P wbs_dat_o[12] O
-*I *419:wbs_dat_o[12] O *D user_proj_example
-*CAP
-1 wbs_dat_o[12] 0.00010579
-2 *419:wbs_dat_o[12] 0.00111222
-3 *384:17 0.0261387
-4 *384:16 0.0260329
-5 *384:14 0.00349478
-6 *384:13 0.00460699
-7 *384:13 *412:12 0.000111905
-8 *419:wbs_adr_i[13] *384:13 0.0013605
-9 *419:wbs_adr_i[19] *384:13 0.00839248
-10 *419:wbs_adr_i[8] *384:13 0.000242434
-11 *419:wbs_dat_i[11] *384:13 0.000634131
-12 *419:wbs_dat_i[12] *384:13 0.000459167
-13 *419:wbs_dat_i[8] *384:13 0.00161623
-14 *67:11 *384:17 0
-15 *323:16 *384:13 0
-16 *327:16 *384:14 0
-17 *351:16 *384:14 0.0429591
-*RES
-1 *419:wbs_dat_o[12] *384:13 38.745
-2 *384:13 *384:14 62.19
-3 *384:14 *384:16 4.5
-4 *384:16 *384:17 258.21
-5 *384:17 wbs_dat_o[12] 1.395
-*END
-
-*D_NET *385 0.0730662
-*CONN
-*P wbs_dat_o[13] O
-*I *419:wbs_dat_o[13] O *D user_proj_example
-*CAP
-1 wbs_dat_o[13] 0.00252671
-2 *419:wbs_dat_o[13] 0.00211002
-3 *385:14 0.00910166
-4 *385:13 0.00657494
-5 *385:11 0.0215957
-6 *385:9 0.0237058
-7 *419:wbs_adr_i[13] *385:9 0
-8 *419:wbs_adr_i[14] *385:9 0
-9 *419:wbs_dat_i[13] *385:9 0.00485482
-10 *419:wbs_dat_i[13] *385:11 0.00257778
-11 *319:11 wbs_dat_o[13] 0
-12 *321:13 wbs_dat_o[13] 1.87963e-05
-13 *357:11 *385:11 0
-*RES
-1 *419:wbs_dat_o[13] *385:9 32.535
-2 *385:9 *385:11 217.44
-3 *385:11 *385:13 4.5
-4 *385:13 *385:14 67.95
-5 *385:14 wbs_dat_o[13] 29.385
-*END
-
-*D_NET *386 0.137355
-*CONN
-*P wbs_dat_o[14] O
-*I *419:wbs_dat_o[14] O *D user_proj_example
-*CAP
-1 wbs_dat_o[14] 0.000751504
-2 *419:wbs_dat_o[14] 0.00302336
-3 *386:14 0.00177444
-4 *386:13 0.00102293
-5 *386:11 0.0259768
-6 *386:9 0.0290001
-7 *386:14 wbs_dat_o[18] 6.29468e-05
-8 *386:14 *413:8 0
-9 *419:wbs_adr_i[15] *386:9 0
-10 *419:wbs_dat_i[14] *386:9 0.00276805
-11 *355:8 *386:14 0.0368661
-12 *361:10 *386:14 0.000734347
-13 *383:14 *386:14 0.0353744
-*RES
-1 *419:wbs_dat_o[14] *386:9 32.535
-2 *386:9 *386:11 232.74
-3 *386:11 *386:13 4.5
-4 *386:13 *386:14 59.31
-5 *386:14 wbs_dat_o[14] 11.565
-*END
-
-*D_NET *387 0.0974756
-*CONN
-*P wbs_dat_o[15] O
-*I *419:wbs_dat_o[15] O *D user_proj_example
-*CAP
-1 wbs_dat_o[15] 0.000166523
-2 *419:wbs_dat_o[15] 0.000516299
-3 *387:11 0.0264864
-4 *387:10 0.0263199
-5 *387:8 0.00347837
-6 *387:7 0.00399466
-7 *419:wbs_adr_i[16] *387:7 0.000569644
-8 *419:wbs_dat_i[15] *387:7 0.000818215
-9 *419:wbs_dat_i[16] *387:7 0
-10 *321:16 *387:8 0.0351256
-11 *322:11 *387:11 0
-12 *355:7 *387:11 0
-*RES
-1 *419:wbs_dat_o[15] *387:7 15.165
-2 *387:7 *387:8 55.35
-3 *387:8 *387:10 4.5
-4 *387:10 *387:11 260.55
-5 *387:11 wbs_dat_o[15] 1.935
-*END
-
-*D_NET *388 0.102042
-*CONN
-*P wbs_dat_o[16] O
-*I *419:wbs_dat_o[16] O *D user_proj_example
-*CAP
-1 wbs_dat_o[16] 0.000798876
-2 *419:wbs_dat_o[16] 0.000564881
-3 *388:16 0.00340385
-4 *388:15 0.00260497
-5 *388:13 0.0244471
-6 *388:12 0.025012
-7 *419:wbs_adr_i[17] *388:12 0.00115463
-8 *419:wbs_adr_i[17] *388:13 0.0122138
-9 *419:wbs_dat_i[16] *388:12 0.00148478
-10 *355:8 *388:16 0.030276
-11 *361:10 *388:16 8.08207e-05
-12 *361:11 *388:13 0
-*RES
-1 *419:wbs_dat_o[16] *388:12 22.7407
-2 *388:12 *388:13 251.73
-3 *388:13 *388:15 4.5
-4 *388:15 *388:16 46.17
-5 *388:16 wbs_dat_o[16] 11.925
-*END
-
-*D_NET *389 0.0951863
-*CONN
-*P wbs_dat_o[17] O
-*I *419:wbs_dat_o[17] O *D user_proj_example
-*CAP
-1 wbs_dat_o[17] 0.00237777
-2 *419:wbs_dat_o[17] 0.000297394
-3 *389:13 0.0162074
-4 *389:12 0.0165259
-5 *389:9 0.00299371
-6 *389:12 *394:10 0.00428972
-7 *389:13 *419:wbs_sel_i[2] 0.00558519
-8 *419:wbs_adr_i[17] *389:9 0
-9 *419:wbs_adr_i[18] *389:9 0.000994799
-10 *419:wbs_adr_i[3] *389:13 0.00804022
-11 *419:wbs_dat_i[17] *389:9 0.00144233
-12 *318:14 *389:12 0.00293441
-13 *319:14 *389:12 0.000271992
-14 *322:14 *389:12 0.000629418
-15 *323:16 *389:12 1.55425e-05
-16 *341:11 wbs_dat_o[17] 0.00253303
-17 *341:11 *389:13 0.0292762
-18 *342:16 *389:12 0.000476634
-19 *357:17 *389:9 0.000294603
-*RES
-1 *419:wbs_dat_o[17] *389:9 13.635
-2 *389:9 *389:12 45.27
-3 *389:12 *389:13 230.94
-4 *389:13 wbs_dat_o[17] 32.085
-*END
-
-*D_NET *390 0.128326
-*CONN
-*P wbs_dat_o[18] O
-*I *419:wbs_dat_o[18] O *D user_proj_example
-*CAP
-1 wbs_dat_o[18] 0.0016297
-2 *419:wbs_dat_o[18] 0.000484929
-3 *390:11 0.0167308
-4 *390:9 0.015586
-5 *419:wbs_adr_i[18] *390:11 0
-6 *419:wbs_adr_i[19] *390:9 0
-7 *419:wbs_dat_i[18] *390:9 0.000554939
-8 *419:wbs_dat_i[18] *390:11 0.00558519
-9 *326:13 wbs_dat_o[18] 0.000840847
-10 *330:16 wbs_dat_o[18] 0
-11 *357:10 wbs_dat_o[18] 0.0124959
-12 *358:10 wbs_dat_o[18] 0.00876594
-13 *361:10 wbs_dat_o[18] 0.00621676
-14 *362:10 wbs_dat_o[18] 0.003295
-15 *363:5 *390:11 0.0531514
-16 *363:14 *390:9 0.000184127
-17 *363:14 *390:11 0.00255988
-18 *383:14 wbs_dat_o[18] 0.000181328
-19 *386:14 wbs_dat_o[18] 6.29468e-05
-*RES
-1 *419:wbs_dat_o[18] *390:9 6.885
-2 *390:9 *390:11 259.65
-3 *390:11 wbs_dat_o[18] 48.735
-*END
-
-*D_NET *391 0.0780058
-*CONN
-*P wbs_dat_o[19] O
-*I *419:wbs_dat_o[19] O *D user_proj_example
-*CAP
-1 wbs_dat_o[19] 0.01544
-2 *419:wbs_dat_o[19] 0.00107293
-3 *391:12 0.0185306
-4 *391:9 0.00416352
-5 wbs_dat_o[19] *412:13 0.0327255
-6 *391:9 *395:11 0.000492285
-7 *419:wbs_adr_i[10] wbs_dat_o[19] 0.00111704
-8 *419:wbs_adr_i[20] *391:9 0.000918335
-9 *419:wbs_dat_i[19] *391:9 0.00156508
-10 *419:wbs_dat_i[9] wbs_dat_o[19] 0.000593299
-11 *328:19 *391:9 0.00138709
-*RES
-1 *419:wbs_dat_o[19] *391:9 27.135
-2 *391:9 *391:12 31.77
-3 *391:12 wbs_dat_o[19] 249.165
-*END
-
-*D_NET *392 0.21712
-*CONN
-*P wbs_dat_o[1] O
-*I *419:wbs_dat_o[1] O *D user_proj_example
-*CAP
-1 wbs_dat_o[1] 0.00217006
-2 *419:wbs_dat_o[1] 0.00227904
-3 *392:14 0.0166041
-4 *392:13 0.0144341
-5 *392:11 0.0122607
-6 *392:9 0.0145397
-7 *392:9 *419:wbs_sel_i[1] 0
-8 *392:9 *406:13 0.00128889
-9 *419:wbs_dat_i[1] *392:9 0.00320995
-10 *324:5 *392:9 0.000208677
-11 *324:5 *392:11 0.150125
-*RES
-1 *419:wbs_dat_o[1] *392:9 32.535
-2 *392:9 *392:11 220.14
-3 *392:11 *392:13 4.5
-4 *392:13 *392:14 151.65
-5 *392:14 wbs_dat_o[1] 26.145
-*END
-
-*D_NET *393 0.15021
-*CONN
-*P wbs_dat_o[20] O
-*I *419:wbs_dat_o[20] O *D user_proj_example
-*CAP
-1 wbs_dat_o[20] 0.000168297
-2 *419:wbs_dat_o[20] 0.00141362
-3 *393:11 0.0245883
-4 *393:10 0.0258336
-5 *393:10 *395:10 0.000223811
-6 *419:wbs_adr_i[12] *393:11 0.000306879
-7 *419:wbs_adr_i[19] *393:10 0.0127444
-8 *419:wbs_adr_i[21] *393:10 0.00131493
-9 *419:wbs_adr_i[23] *393:10 0.000111905
-10 *419:wbs_dat_i[12] *393:11 0.000163669
-11 *419:wbs_dat_i[19] *393:10 0
-12 *419:wbs_dat_i[20] *393:10 0.000431548
-13 *352:15 *393:11 0.0788678
-14 *357:11 *393:11 0
-15 *361:10 *393:11 0
-16 *363:14 *393:10 0.00404104
-*RES
-1 *419:wbs_dat_o[20] *393:10 37.575
-2 *393:10 *393:11 265.59
-3 *393:11 wbs_dat_o[20] 1.935
-*END
-
-*D_NET *394 0.101714
-*CONN
-*P wbs_dat_o[21] O
-*I *419:wbs_dat_o[21] O *D user_proj_example
-*CAP
-1 wbs_dat_o[21] 0.000291157
-2 *419:wbs_dat_o[21] 0.00175947
-3 *394:11 0.0158799
-4 *394:10 0.0173482
-5 *394:10 *395:10 0
-6 *419:wbs_adr_i[22] *394:10 0.00189242
-7 *419:wbs_dat_i[15] *394:11 0.0581229
-8 *419:wbs_dat_i[19] *394:10 0
-9 *419:wbs_dat_i[21] *394:10 0.000486786
-10 *323:16 *394:10 0.000174852
-11 *362:10 *394:11 0.00140141
-12 *362:19 *394:10 6.75133e-05
-13 *389:12 *394:10 0.00428972
-*RES
-1 *419:wbs_dat_o[21] *394:10 34.875
-2 *394:10 *394:11 262.89
-3 *394:11 wbs_dat_o[21] 3.015
-*END
-
-*D_NET *395 0.197679
-*CONN
-*P wbs_dat_o[22] O
-*I *419:wbs_dat_o[22] O *D user_proj_example
-*CAP
-1 wbs_dat_o[22] 0.00010579
-2 *419:wbs_dat_o[22] 0.000920416
-3 *395:11 0.0160235
-4 *395:10 0.0168381
-5 *419:wbs_adr_i[21] *395:10 0.00105689
-6 *419:wbs_adr_i[23] *395:10 0.00163344
-7 *419:wbs_dat_i[19] *395:10 0.000103616
-8 *419:wbs_dat_i[19] *395:11 0.000102293
-9 *419:wbs_dat_i[22] *395:10 0.000417739
-10 *328:19 *395:11 0.159761
-11 *363:14 *395:11 0
-12 *391:9 *395:11 0.000492285
-13 *393:10 *395:10 0.000223811
-14 *394:10 *395:10 0
-*RES
-1 *419:wbs_dat_o[22] *395:10 24.975
-2 *395:10 *395:11 264.69
-3 *395:11 wbs_dat_o[22] 1.395
-*END
-
-*D_NET *396 0.20344
-*CONN
-*P wbs_dat_o[23] O
-*I *419:wbs_dat_o[23] O *D user_proj_example
-*CAP
-1 wbs_dat_o[23] 0.000764887
-2 *419:wbs_dat_o[23] 0.000751205
-3 *396:11 0.0145135
-4 *396:9 0.0144998
-5 *419:wbs_adr_i[24] *396:9 0.00165587
-6 *419:wbs_adr_i[24] *396:11 0
-7 *419:wbs_dat_i[23] *396:9 0.00231387
-8 *332:18 *396:11 3.45239e-05
-9 *332:19 *396:11 0.167985
-10 *364:25 *396:11 0.000920637
-*RES
-1 *419:wbs_dat_o[23] *396:9 17.865
-2 *396:9 *396:11 248.49
-3 *396:11 wbs_dat_o[23] 6.975
-*END
-
-*D_NET *397 0.188888
-*CONN
-*P wbs_dat_o[24] O
-*I *419:wbs_dat_o[24] O *D user_proj_example
-*CAP
-1 wbs_dat_o[24] 0.0129003
-2 *419:wbs_dat_o[24] 0.00177658
-3 *397:16 0.0129003
-4 *397:14 0.00177658
-5 wbs_dat_o[24] *398:11 0.0030473
-6 wbs_dat_o[24] *399:11 0.149327
-7 *397:14 *398:10 0.000559528
-8 *397:14 *399:9 0
-9 *397:14 *399:11 0.00110093
-10 *419:wbs_adr_i[25] *397:14 0.00181986
-11 *419:wbs_adr_i[26] *397:14 0.000306879
-12 *419:wbs_dat_i[24] *397:14 0.000721638
-13 *419:wbs_dat_i[25] *397:14 0.000207232
-14 *333:11 wbs_dat_o[24] 0
-15 *333:11 *397:14 0.00244352
-*RES
-1 *419:wbs_dat_o[24] *397:14 49.455
-2 *397:14 *397:16 4.5
-3 *397:16 wbs_dat_o[24] 239.805
-*END
-
-*D_NET *398 0.238888
-*CONN
-*P wbs_dat_o[25] O
-*I *419:wbs_dat_o[25] O *D user_proj_example
-*CAP
-1 wbs_dat_o[25] 0.00014502
-2 *419:wbs_dat_o[25] 0.000309145
-3 *398:17 0.00246486
-4 *398:16 0.00306992
-5 *398:11 0.00988296
-6 *398:10 0.00944203
-7 *398:11 *399:11 0
-8 *398:17 *402:11 0.0978943
-9 wbs_dat_o[24] *398:11 0.0030473
-10 *419:wbs_adr_i[26] *398:10 0.000761708
-11 *419:wbs_adr_i[27] *398:11 0.00969736
-12 *419:wbs_dat_i[25] *398:10 0.00241405
-13 *419:wbs_dat_i[27] *398:11 0
-14 *335:19 *398:11 0.000814508
-15 *336:11 *398:11 0
-16 *339:21 *398:17 0.0983853
-17 *397:14 *398:10 0.000559528
-*RES
-1 *419:wbs_dat_o[25] *398:10 18.315
-2 *398:10 *398:11 114.21
-3 *398:11 *398:16 16.11
-4 *398:16 *398:17 150.57
-5 *398:17 wbs_dat_o[25] 1.755
-*END
-
-*D_NET *399 0.199003
-*CONN
-*P wbs_dat_o[26] O
-*I *419:wbs_dat_o[26] O *D user_proj_example
-*CAP
-1 wbs_dat_o[26] 0.00329027
-2 *419:wbs_dat_o[26] 0.00111438
-3 *399:11 0.015856
-4 *399:9 0.0136801
-5 wbs_dat_o[24] *399:11 0.149327
-6 *419:wbs_adr_i[26] *399:9 0
-7 *419:wbs_adr_i[27] *399:9 0.00438658
-8 *419:wbs_adr_i[27] *399:11 6.13757e-06
-9 *419:wbs_dat_i[26] *399:9 0.00131958
-10 *126:11 wbs_dat_o[26] 0.0060762
-11 *333:11 *399:11 0
-12 *335:11 wbs_dat_o[26] 0.000469524
-13 *335:19 *399:9 9.2064e-05
-14 *335:19 *399:11 0.00112931
-15 *367:10 wbs_dat_o[26] 0.000479882
-16 *368:20 wbs_dat_o[26] 0.000675133
-17 *397:14 *399:9 0
-18 *397:14 *399:11 0.00110093
-19 *398:11 *399:11 0
-*RES
-1 *419:wbs_dat_o[26] *399:9 21.825
-2 *399:9 *399:11 229.95
-3 *399:11 wbs_dat_o[26] 49.275
-*END
-
-*D_NET *400 0.137136
-*CONN
-*P wbs_dat_o[27] O
-*I *419:wbs_dat_o[27] O *D user_proj_example
-*CAP
-1 wbs_dat_o[27] 0.00252954
-2 *419:wbs_dat_o[27] 0.000505867
-3 *400:17 0.00909687
-4 *400:16 0.00853698
-5 *400:11 0.00945452
-6 *400:10 0.00799073
-7 *400:11 *402:9 0.00341249
-8 *400:11 *402:11 0.0069393
-9 *419:wbs_adr_i[26] *400:10 1.24339e-05
-10 *419:wbs_adr_i[28] *400:10 0.00148325
-11 *419:wbs_adr_i[30] *400:11 0.00108431
-12 *419:wbs_dat_i[25] *400:10 0.00105689
-13 *419:wbs_dat_i[26] *400:10 0.000398922
-14 *419:wbs_dat_i[27] *400:10 0.000500596
-15 *419:wbs_dat_i[29] *400:10 0.000683868
-16 *170:11 wbs_dat_o[27] 0.00084136
-17 *223:21 wbs_dat_o[27] 0.00210723
-18 *223:21 *400:17 0.0801567
-19 *287:19 wbs_dat_o[27] 0.000343704
-20 *340:11 *400:11 0
-*RES
-1 *419:wbs_dat_o[27] *400:10 21.015
-2 *400:10 *400:11 115.47
-3 *400:11 *400:16 27.27
-4 *400:16 *400:17 117.54
-5 *400:17 wbs_dat_o[27] 32.085
-*END
-
-*D_NET *401 0.224785
-*CONN
-*P wbs_dat_o[28] O
-*I *419:wbs_dat_o[28] O *D user_proj_example
-*CAP
-1 wbs_dat_o[28] 0.000226282
-2 *419:wbs_dat_o[28] 0.00175684
-3 *401:11 0.0158436
-4 *401:10 0.0173742
-5 *419:la_data_in[2] *401:10 0
-6 *419:la_data_in[7] *401:11 0.000211746
-7 *419:la_oenb[2] *401:10 0.00851682
-8 *419:la_oenb[3] *401:10 0.00665184
-9 *419:wbs_adr_i[29] *401:10 0.00127866
-10 *419:wbs_adr_i[31] *401:10 3.62657e-05
-11 *419:wbs_dat_i[26] *401:10 0.00379236
-12 *419:wbs_dat_i[28] *401:10 0.000127738
-13 *419:wbs_dat_i[30] *401:10 0.000384675
-14 *177:11 *401:11 0.167494
-15 *240:5 *401:11 0.000695592
-16 *369:14 *401:11 0
-17 *369:15 *401:10 0.000393828
-*RES
-1 *419:wbs_dat_o[28] *401:10 43.155
-2 *401:10 *401:11 265.59
-3 *401:11 wbs_dat_o[28] 2.475
-*END
-
-*D_NET *402 0.195579
-*CONN
-*P wbs_dat_o[29] O
-*I *419:wbs_dat_o[29] O *D user_proj_example
-*CAP
-1 wbs_dat_o[29] 0.000786848
-2 *419:wbs_dat_o[29] 0.0011306
-3 *402:20 0.00192496
-4 *402:11 0.0114469
-5 *402:9 0.0114394
-6 *402:20 *404:14 0.0119366
-7 *419:wbs_adr_i[29] *402:9 0
-8 *419:wbs_adr_i[30] *402:9 0.000497144
-9 *419:wbs_dat_i[29] *402:9 0.00152417
-10 *305:8 *402:20 0
-11 *335:10 *402:20 0.00292198
-12 *336:10 *402:20 0.00358512
-13 *339:13 *402:20 0.0121231
-14 *339:20 *402:20 0.000235727
-15 *339:21 *402:9 0.00201389
-16 *339:21 *402:11 0.0202745
-17 *340:8 *402:20 8.28929e-05
-18 *368:20 *402:20 0.00540877
-19 *398:17 *402:11 0.0978943
-20 *400:11 *402:9 0.00341249
-21 *400:11 *402:11 0.0069393
-*RES
-1 *419:wbs_dat_o[29] *402:9 32.535
-2 *402:9 *402:11 232.74
-3 *402:11 *402:20 47.07
-4 *402:20 wbs_dat_o[29] 7.245
-*END
-
-*D_NET *403 0.239793
-*CONN
-*P wbs_dat_o[2] O
-*I *419:wbs_dat_o[2] O *D user_proj_example
-*CAP
-1 wbs_dat_o[2] 0.000736551
-2 *419:wbs_dat_o[2] 0.000550074
-3 *403:11 0.0264941
-4 *403:10 0.0257575
-5 *403:8 0.00242655
-6 *403:7 0.00297662
-7 wbs_dat_o[2] *417:8 0.000849652
-8 *403:7 *419:wbs_sel_i[2] 0.000653012
-9 *419:wbs_adr_i[2] *403:7 0
-10 *419:wbs_dat_i[2] *403:7 0.000238215
-11 *28:5 *403:8 0
-12 *316:16 *403:8 0.0892137
-13 *338:12 wbs_dat_o[2] 0.00254896
-14 *342:16 *403:8 0.0873483
-15 *371:11 wbs_dat_o[2] 0
-*RES
-1 *419:wbs_dat_o[2] *403:7 12.825
-2 *403:7 *403:8 138.69
-3 *403:8 *403:10 4.5
-4 *403:10 *403:11 256.59
-5 *403:11 wbs_dat_o[2] 19.035
-*END
-
-*D_NET *404 0.152533
-*CONN
-*P wbs_dat_o[30] O
-*I *419:wbs_dat_o[30] O *D user_proj_example
-*CAP
-1 wbs_dat_o[30] 0.000739476
-2 *419:wbs_dat_o[30] 0.00103686
-3 *404:14 0.00154847
-4 *404:11 0.00697433
-5 *404:9 0.0072022
-6 *419:wbs_adr_i[30] *404:9 0
-7 *419:wbs_adr_i[31] *404:9 0.000441905
-8 *419:wbs_dat_i[30] *404:9 0.00107408
-9 *339:13 *404:14 0.0142368
-10 *340:8 *404:14 0.0305253
-11 *340:11 *404:9 0.00249723
-12 *340:11 *404:11 0.0529468
-13 *367:11 *404:9 0.00351069
-14 *367:11 *404:11 0.0178626
-15 *402:20 *404:14 0.0119366
-*RES
-1 *419:wbs_dat_o[30] *404:9 32.535
-2 *404:9 *404:11 232.92
-3 *404:11 *404:14 48.69
-4 *404:14 wbs_dat_o[30] 11.385
-*END
-
-*D_NET *405 0.226656
-*CONN
-*P wbs_dat_o[31] O
-*I *419:wbs_dat_o[31] O *D user_proj_example
-*CAP
-1 wbs_dat_o[31] 0.00131136
-2 *419:wbs_dat_o[31] 0.000481536
-3 *405:16 0.00420659
-4 *405:15 0.00289523
-5 *405:13 0.0114655
-6 *405:12 0.011947
-7 *419:la_data_in[0] *405:12 0.00111883
-8 *419:wbs_dat_i[31] *405:12 0.00152826
-9 *419:wbs_dat_i[31] *405:13 0.00102293
-10 *115:11 *405:13 0.149818
-11 *126:8 *405:16 0.0333852
-12 *188:15 wbs_dat_o[31] 0
-13 *304:11 wbs_dat_o[31] 1.53439e-05
-14 *367:11 *405:13 0
-15 *370:15 *405:13 0.00746022
-*RES
-1 *419:wbs_dat_o[31] *405:12 21.645
-2 *405:12 *405:13 247.77
-3 *405:13 *405:15 4.5
-4 *405:15 *405:16 51.03
-5 *405:16 wbs_dat_o[31] 16.785
-*END
-
-*D_NET *406 0.2315
-*CONN
-*P wbs_dat_o[3] O
-*I *419:wbs_dat_o[3] O *D user_proj_example
-*CAP
-1 wbs_dat_o[3] 0.000187838
-2 *419:wbs_dat_o[3] 0.00164154
-3 *406:17 0.0257965
-4 *406:16 0.0256086
-5 *406:14 0.00168444
-6 *406:13 0.00332598
-7 *406:13 *419:wbs_sel_i[3] 0.000431548
-8 *406:13 *416:14 0
-9 *406:14 *414:16 0.0662108
-10 *419:wbs_adr_i[2] *406:13 0
-11 *419:wbs_adr_i[4] *406:13 0.000306879
-12 *419:wbs_dat_i[3] *406:13 0
-13 *323:16 *406:13 0.0010071
-14 *349:16 *406:14 0.0847374
-15 *350:14 *406:14 0.00155424
-16 *354:8 *406:14 0.0177184
-17 *392:9 *406:13 0.00128889
-*RES
-1 *419:wbs_dat_o[3] *406:13 37.125
-2 *406:13 *406:14 128.25
-3 *406:14 *406:16 4.5
-4 *406:16 *406:17 254.97
-5 *406:17 wbs_dat_o[3] 2.115
-*END
-
-*D_NET *407 0.21866
-*CONN
-*P wbs_dat_o[4] O
-*I *419:wbs_dat_o[4] O *D user_proj_example
-*CAP
-1 wbs_dat_o[4] 0.0011973
-2 *419:wbs_dat_o[4] 0.000226904
-3 *407:13 0.0270005
-4 *407:12 0.0258032
-5 *407:10 0.00183295
-6 *407:9 0.00205986
-7 *407:10 *409:8 0.0724274
-8 *407:10 *416:14 0.0783958
-9 *407:13 wbs_dat_o[5] 0.00190265
-10 *419:wbs_adr_i[5] *407:9 0.000421191
-11 *419:wbs_dat_i[4] *407:9 0.00123774
-12 *338:12 wbs_dat_o[4] 0.00615448
-13 *344:13 *407:13 0
-*RES
-1 *419:wbs_dat_o[4] *407:9 10.575
-2 *407:9 *407:10 115.65
-3 *407:10 *407:12 4.5
-4 *407:12 *407:13 259.83
-5 *407:13 wbs_dat_o[4] 23.895
-*END
-
-*D_NET *408 0.0895384
-*CONN
-*P wbs_dat_o[5] O
-*I *419:wbs_dat_o[5] O *D user_proj_example
-*CAP
-1 wbs_dat_o[5] 0.000914306
-2 *419:wbs_dat_o[5] 0.000380094
-3 *408:14 0.0119782
-4 *408:13 0.0110639
-5 *408:11 0.0238791
-6 *408:10 0.0242592
-7 *408:10 *409:8 0
-8 *419:wbs_adr_i[5] *408:11 0.00157531
-9 *419:wbs_adr_i[6] *408:10 0.001606
-10 *419:wbs_dat_i[4] *408:11 0.000918335
-11 *419:wbs_dat_i[5] *408:10 0.000542025
-12 *419:wbs_dat_i[5] *408:11 0
-13 *323:16 *408:10 0.00064242
-14 *325:13 *408:11 0.00939048
-15 *344:13 wbs_dat_o[5] 0.000486403
-16 *407:13 wbs_dat_o[5] 0.00190265
-*RES
-1 *419:wbs_dat_o[5] *408:10 18.855
-2 *408:10 *408:11 249.93
-3 *408:11 *408:13 4.5
-4 *408:13 *408:14 115.83
-5 *408:14 wbs_dat_o[5] 18.765
-*END
-
-*D_NET *409 0.195728
-*CONN
-*P wbs_dat_o[6] O
-*I *419:wbs_dat_o[6] O *D user_proj_example
-*CAP
-1 wbs_dat_o[6] 0.000699672
-2 *419:wbs_dat_o[6] 0.00015545
-3 *409:11 0.026884
-4 *409:10 0.0261843
-5 *409:8 0.00238374
-6 *409:7 0.00253919
-7 *409:8 *411:8 0.0616098
-8 *419:wbs_adr_i[19] *409:8 0.000186509
-9 *419:wbs_adr_i[7] *409:7 0.00119683
-10 *419:wbs_dat_i[6] *409:7 0.000403929
-11 *338:12 wbs_dat_o[6] 0.00105689
-12 *345:5 *409:11 0
-13 *407:10 *409:8 0.0724274
-14 *408:10 *409:8 0
-*RES
-1 *419:wbs_dat_o[6] *409:7 9.765
-2 *409:7 *409:8 110.79
-3 *409:8 *409:10 4.5
-4 *409:10 *409:11 260.01
-5 *409:11 wbs_dat_o[6] 16.515
-*END
-
-*D_NET *410 0.190248
-*CONN
-*P wbs_dat_o[7] O
-*I *419:wbs_dat_o[7] O *D user_proj_example
-*CAP
-1 wbs_dat_o[7] 0.000680446
-2 *419:wbs_dat_o[7] 0.00216185
-3 *410:14 0.00259571
-4 *410:13 0.00191526
-5 *410:11 0.0233991
-6 *410:9 0.0255609
-7 *410:14 *412:16 0.0596204
-8 *410:14 *417:8 0.000186509
-9 *419:wbs_adr_i[7] *410:9 0
-10 *419:wbs_adr_i[8] *410:9 0.00102881
-11 *419:wbs_dat_i[7] *410:9 0.00426562
-12 *325:13 *410:14 0.00064242
-13 *341:8 *410:14 0.0627289
-14 *346:10 *410:14 0.000202829
-15 *357:10 *410:14 0.000596807
-16 *358:10 *410:14 0.00466273
-*RES
-1 *419:wbs_dat_o[7] *410:9 32.535
-2 *410:9 *410:11 233.28
-3 *410:11 *410:13 4.5
-4 *410:13 *410:14 104.67
-5 *410:14 wbs_dat_o[7] 11.025
-*END
-
-*D_NET *411 0.154784
-*CONN
-*P wbs_dat_o[8] O
-*I *419:wbs_dat_o[8] O *D user_proj_example
-*CAP
-1 wbs_dat_o[8] 0.000435426
-2 *419:wbs_dat_o[8] 0.000190262
-3 *411:11 0.0266756
-4 *411:10 0.0262402
-5 *411:8 0.00366813
-6 *411:7 0.00385839
-7 *411:8 *419:wbs_sel_i[1] 0.023065
-8 *419:wbs_adr_i[19] *411:8 0.000543985
-9 *419:wbs_adr_i[4] *411:8 0.000559453
-10 *419:wbs_adr_i[9] *411:7 0.00039012
-11 *419:wbs_dat_i[8] *411:7 0.00039012
-12 *338:12 wbs_dat_o[8] 0.00317066
-13 *347:13 wbs_dat_o[8] 0.000816297
-14 *379:10 wbs_dat_o[8] 0.00317066
-15 *380:5 *411:11 0
-16 *409:8 *411:8 0.0616098
-*RES
-1 *419:wbs_dat_o[8] *411:7 9.585
-2 *411:7 *411:8 94.59
-3 *411:8 *411:10 4.5
-4 *411:10 *411:11 260.19
-5 *411:11 wbs_dat_o[8] 19.575
-*END
-
-*D_NET *412 0.195863
-*CONN
-*P wbs_dat_o[9] O
-*I *419:wbs_dat_o[9] O *D user_proj_example
-*CAP
-1 wbs_dat_o[9] 0.000675064
-2 *419:wbs_dat_o[9] 0.000323938
-3 *412:16 0.00237693
-4 *412:15 0.00170187
-5 *412:13 0.0158118
-6 *412:12 0.0161357
-7 wbs_dat_o[19] *412:13 0.0327255
-8 *419:wbs_adr_i[10] *412:12 0.000571817
-9 *419:wbs_adr_i[9] *412:13 0.000626032
-10 *419:wbs_dat_i[9] *412:12 0.000662347
-11 *419:wbs_dat_i[9] *412:13 0.0123365
-12 *317:10 *412:16 0.000317324
-13 *323:16 *412:12 6.29468e-05
-14 *358:10 *412:16 0.0011605
-15 *379:11 wbs_dat_o[9] 9.8457e-05
-16 *383:14 *412:16 0.0505437
-17 *384:13 *412:12 0.000111905
-18 *410:14 *412:16 0.0596204
-*RES
-1 *419:wbs_dat_o[9] *412:12 16.965
-2 *412:12 *412:13 258.03
-3 *412:13 *412:15 4.5
-4 *412:15 *412:16 91.35
-5 *412:16 wbs_dat_o[9] 11.205
-*END
-
-*D_NET *413 0.0938673
-*CONN
-*P wbs_sel_i[0] I
-*I *419:wbs_sel_i[0] I *D user_proj_example
-*CAP
-1 wbs_sel_i[0] 0.000821577
-2 *419:wbs_sel_i[0] 0.000371289
-3 *413:11 0.0257362
-4 *413:10 0.0253649
-5 *413:8 0.0161134
-6 *413:7 0.016935
-7 *419:wbs_sel_i[0] *416:14 0.000216817
-8 *413:7 *418:11 0.00027747
-9 *413:8 *416:10 0
-10 *419:wbs_adr_i[1] *419:wbs_sel_i[0] 0.000500596
-11 *419:wbs_dat_i[0] *413:11 0.00681271
-12 *317:10 *413:8 0
-13 *319:10 *413:8 0
-14 *323:16 *419:wbs_sel_i[0] 0.000216817
-15 *346:10 *413:8 0
-16 *355:8 *413:8 0
-17 *376:10 *413:8 0
-18 *381:5 *419:wbs_sel_i[0] 0.000500596
-19 *381:5 *413:11 0
-20 *386:14 *413:8 0
-*RES
-1 wbs_sel_i[0] *413:7 13.365
-2 *413:7 *413:8 154.71
-3 *413:8 *413:10 4.5
-4 *413:10 *413:11 255.87
-5 *413:11 *419:wbs_sel_i[0] 18.315
-*END
-
-*D_NET *414 0.181941
-*CONN
-*P wbs_sel_i[1] I
-*I *419:wbs_sel_i[1] I *D user_proj_example
-*CAP
-1 wbs_sel_i[1] 0.00020706
-2 *419:wbs_sel_i[1] 0.00220472
-3 *414:21 0.00344014
-4 *414:16 0.00628637
-5 *414:15 0.00505095
-6 *414:13 0.0256032
-7 *414:11 0.0258102
-8 *419:wbs_adr_i[2] *419:wbs_sel_i[1] 0.00037631
-9 *321:13 *414:21 0
-10 *349:16 *414:16 0.00497357
-11 *350:14 *414:16 0.0187131
-12 *371:14 *419:wbs_sel_i[1] 0
-13 *392:9 *419:wbs_sel_i[1] 0
-14 *406:14 *414:16 0.0662108
-15 *411:8 *419:wbs_sel_i[1] 0.023065
-*RES
-1 wbs_sel_i[1] *414:11 2.295
-2 *414:11 *414:13 255.15
-3 *414:13 *414:15 4.5
-4 *414:15 *414:16 117.45
-5 *414:16 *414:21 20.25
-6 *414:21 *419:wbs_sel_i[1] 42.795
-*END
-
-*D_NET *415 0.14123
-*CONN
-*P wbs_sel_i[2] I
-*I *419:wbs_sel_i[2] I *D user_proj_example
-*CAP
-1 wbs_sel_i[2] 0.00120466
-2 *419:wbs_sel_i[2] 0.00121072
-3 *415:14 0.0103593
-4 *415:13 0.00914858
-5 *415:11 0.0240868
-6 *415:10 0.0252915
-7 *415:11 *416:10 0.000117381
-8 *419:wbs_adr_i[3] *419:wbs_sel_i[2] 0.00185559
-9 *338:12 *415:10 0.00789556
-10 *341:11 *419:wbs_sel_i[2] 0.00128889
-11 *342:13 *415:11 0
-12 *380:8 *415:14 0.0525333
-13 *389:13 *419:wbs_sel_i[2] 0.00558519
-14 *403:7 *419:wbs_sel_i[2] 0.000653012
-*RES
-1 wbs_sel_i[2] *415:10 26.415
-2 *415:10 *415:11 240.57
-3 *415:11 *415:13 4.5
-4 *415:13 *415:14 128.79
-5 *415:14 *419:wbs_sel_i[2] 29.925
-*END
-
-*D_NET *416 0.217826
-*CONN
-*P wbs_sel_i[3] I
-*I *419:wbs_sel_i[3] I *D user_proj_example
-*CAP
-1 wbs_sel_i[3] 0.000718811
-2 *419:wbs_sel_i[3] 0.000285019
-3 *416:14 0.00285398
-4 *416:13 0.00256896
-5 *416:11 0.0259532
-6 *416:10 0.026672
-7 *416:10 *417:8 0.000462387
-8 *416:14 *418:14 0.0777744
-9 *419:wbs_adr_i[4] *419:wbs_sel_i[3] 0.000362501
-10 *419:wbs_dat_i[4] *419:wbs_sel_i[3] 0
-11 *419:wbs_sel_i[0] *416:14 0.000216817
-12 *323:16 *416:14 0
-13 *342:13 *416:10 0.0010127
-14 *375:5 *416:11 0
-15 *406:13 *419:wbs_sel_i[3] 0.000431548
-16 *406:13 *416:14 0
-17 *407:10 *416:14 0.0783958
-18 *413:8 *416:10 0
-19 *415:11 *416:10 0.000117381
-*RES
-1 wbs_sel_i[3] *416:10 21.015
-2 *416:10 *416:11 258.21
-3 *416:11 *416:13 4.5
-4 *416:13 *416:14 126.99
-5 *416:14 *419:wbs_sel_i[3] 10.125
-*END
-
-*D_NET *417 0.151237
-*CONN
-*P wbs_stb_i I
-*I *419:wbs_stb_i I *D user_proj_example
-*CAP
-1 wbs_stb_i 0.000686636
-2 *419:wbs_stb_i 0.00146539
-3 *417:14 0.0056122
-4 *417:13 0.00414681
-5 *417:11 0.0247072
-6 *417:10 0.0247072
-7 *417:8 0.00517514
-8 *417:7 0.00586178
-9 *419:wbs_stb_i *419:wbs_we_i 0
-10 *419:wbs_stb_i *418:14 0.000236245
-11 *417:8 *418:10 0.00180285
-12 wbs_dat_o[2] *417:8 0.000849652
-13 *419:wbs_adr_i[0] *419:wbs_stb_i 0
-14 *419:wbs_cyc_i *419:wbs_stb_i 0.000490239
-15 *315:11 *419:wbs_stb_i 0.00840847
-16 *323:16 *419:wbs_stb_i 5.90613e-05
-17 *338:10 *417:8 0.000417055
-18 *338:12 *417:8 0.000397886
-19 *341:8 *417:8 0.0105688
-20 *371:10 *417:8 0.000211377
-21 *376:10 *417:8 0.00150448
-22 *378:12 *417:14 0.0532795
-23 *410:14 *417:8 0.000186509
-24 *416:10 *417:8 0.000462387
-*RES
-1 wbs_stb_i *417:7 11.205
-2 *417:7 *417:8 89.01
-3 *417:8 *417:10 4.5
-4 *417:10 *417:11 245.97
-5 *417:11 *417:13 4.5
-6 *417:13 *417:14 77.13
-7 *417:14 *419:wbs_stb_i 34.515
-*END
-
-*D_NET *418 0.156108
-*CONN
-*P wbs_we_i I
-*I *419:wbs_we_i I *D user_proj_example
-*CAP
-1 wbs_we_i 0.00130771
-2 *419:wbs_we_i 0.000386439
-3 *418:14 0.00989499
-4 *418:13 0.00950856
-5 *418:11 0.0259095
-6 *418:10 0.0272172
-7 *419:wbs_adr_i[0] *419:wbs_we_i 0.00131958
-8 *419:wbs_stb_i *419:wbs_we_i 0
-9 *419:wbs_stb_i *418:14 0.000236245
-10 *28:5 *418:14 0
-11 *316:13 *418:10 0.000472977
-12 *322:14 *418:14 0
-13 *323:16 *418:14 0
-14 *327:13 *418:11 0
-15 *413:7 *418:11 0.00027747
-16 *416:14 *418:14 0.0777744
-17 *417:8 *418:10 0.00180285
-*RES
-1 wbs_we_i *418:10 28.215
-2 *418:10 *418:11 259.29
-3 *418:11 *418:13 4.5
-4 *418:13 *418:14 153.09
-5 *418:14 *419:wbs_we_i 10.305
+1 wb_rst_i *314:5 262.665
+2 *314:5 *314:7 4.5
+3 *314:7 *314:8 262.53
+4 *314:8 *314:10 4.5
+5 *314:10 *314:11 54.99
+6 *314:11 *419:wb_rst_i 6.525
*END
diff --git a/spef/user_project_wrapper.spef b/spef/user_project_wrapper.spef
index c1d9e0e..dd72921 100644
--- a/spef/user_project_wrapper.spef
+++ b/spef/user_project_wrapper.spef
@@ -430,7 +430,7 @@
*416 wbs_sel_i[3]
*417 wbs_stb_i
*418 wbs_we_i
-*419 mprj
+*419 wrapped_vga_clock
*PORTS
io_in[0] I
@@ -850,11365 +850,2714 @@
wbs_stb_i I
wbs_we_i I
-*D_NET *1 0.256024
+*D_NET *1 0.195403
*CONN
*P io_in[0] I
-*I *419:io_in[0] I *D user_proj_example
+*I *419:io_in[0] I *D wrapped_vga_clock
*CAP
-1 io_in[0] 0.00159288
-2 *419:io_in[0] 0.000159855
-3 *1:14 0.0387637
-4 *1:13 0.0386039
-5 *1:11 0.0806066
-6 *1:10 0.0806066
-7 *1:8 0.00660359
-8 *1:7 0.00819647
-9 *419:io_in[0] *63:27 0.00028598
-10 *419:io_in[0] *69:8 0
-11 *1:14 *66:13 0
-12 *1:14 *101:13 0.000604551
+1 io_in[0] 0.0323536
+2 *419:io_in[0] 0.0298529
+3 *1:10 0.0298529
+4 *1:8 0.0354948
+5 *1:7 0.0354948
+6 *1:5 0.0323536
*RES
-1 io_in[0] *1:7 21.825
-2 *1:7 *1:8 65.97
-3 *1:8 *1:10 4.5
-4 *1:10 *1:11 757.35
-5 *1:11 *1:13 4.5
-6 *1:13 *1:14 386.37
-7 *1:14 *419:io_in[0] 11.07
+1 io_in[0] *1:5 354.825
+2 *1:5 *1:7 4.5
+3 *1:7 *1:8 353.79
+4 *1:8 *1:10 4.5
+5 *1:10 *419:io_in[0] 324.045
*END
-*D_NET *2 0.182426
+*D_NET *2 0.196605
*CONN
*P io_in[10] I
-*I *419:io_in[10] I *D user_proj_example
+*I *419:io_in[10] I *D wrapped_vga_clock
*CAP
-1 io_in[10] 0.000619745
-2 *419:io_in[10] 0.00328993
-3 *2:11 0.0671602
-4 *2:10 0.0638703
-5 *2:8 0.0150246
-6 *2:7 0.0156443
-7 *419:io_in[10] *114:14 0
-8 *2:8 *70:15 0.0065672
-9 *2:8 *110:17 0.0102497
-10 *2:11 *32:11 0
-11 *2:11 *101:10 0
+1 io_in[10] 0.000890476
+2 *419:io_in[10] 0.0614299
+3 *2:10 0.0614299
+4 *2:8 0.0359821
+5 *2:7 0.0368726
*RES
-1 io_in[10] *2:7 10.665
-2 *2:7 *2:8 160.83
+1 io_in[10] *2:7 13.725
+2 *2:7 *2:8 359.19
3 *2:8 *2:10 4.5
-4 *2:10 *2:11 692.91
-5 *2:11 *419:io_in[10] 35.235
+4 *2:10 *419:io_in[10] 669.645
*END
-*D_NET *3 0.178745
+*D_NET *3 0.211313
*CONN
*P io_in[11] I
-*I *419:io_in[11] I *D user_proj_example
+*I *419:io_in[11] I *D wrapped_vga_clock
*CAP
1 io_in[11] 0.000280649
-2 *419:io_in[11] 0.00253971
-3 *3:16 0.0256241
-4 *3:15 0.0230844
-5 *3:13 0.0634675
-6 *3:11 0.0637482
+2 *419:io_in[11] 0.000253574
+3 *3:16 0.0350765
+4 *3:15 0.034823
+5 *3:13 0.0702994
+6 *3:11 0.0705801
+7 *3:16 *91:10 0
*RES
1 io_in[11] *3:11 2.655
-2 *3:11 *3:13 690.93
+2 *3:11 *3:13 766.53
3 *3:13 *3:15 4.5
-4 *3:15 *3:16 229.68
-5 *3:16 *419:io_in[11] 23.355
+4 *3:15 *3:16 347.49
+5 *3:16 *419:io_in[11] 11.5904
*END
-*D_NET *4 0.189839
+*D_NET *4 0.263763
*CONN
*P io_in[12] I
-*I *419:io_in[12] I *D user_proj_example
+*I *419:io_in[12] I *D wrapped_vga_clock
*CAP
1 io_in[12] 0.000215438
-2 *419:io_in[12] 9.37343e-05
-3 *4:16 0.0320508
-4 *4:15 0.031957
-5 *4:13 0.0626533
-6 *4:11 0.0628687
+2 *419:io_in[12] 0.000881417
+3 *4:16 0.0445163
+4 *4:15 0.0436348
+5 *4:13 0.0717957
+6 *4:11 0.0720111
+7 *4:16 *7:17 0.000572841
+8 *4:16 *8:19 0.0301355
*RES
1 io_in[12] *4:11 2.115
-2 *4:11 *4:13 682.83
+2 *4:11 *4:13 782.91
3 *4:13 *4:15 4.5
-4 *4:15 *4:16 316.17
-5 *4:16 *419:io_in[12] 0.945
+4 *4:15 *4:16 455.85
+5 *4:16 *419:io_in[12] 13.005
*END
-*D_NET *5 0.21382
+*D_NET *5 0.222276
*CONN
*P io_in[13] I
-*I *419:io_in[13] I *D user_proj_example
+*I *419:io_in[13] I *D wrapped_vga_clock
*CAP
1 io_in[13] 0.000145659
-2 *419:io_in[13] 0.00334128
-3 *5:16 0.03984
-4 *5:15 0.0364988
-5 *5:13 0.0599306
-6 *5:11 0.0600762
-7 *419:io_in[13] *30:11 0
-8 *419:io_in[13] *40:11 0
-9 *419:io_in[13] *93:10 0.0139871
-10 *5:16 *419:io_in[16] 0
+2 *419:io_in[13] 0.00107029
+3 *5:16 0.0481195
+4 *5:15 0.0470492
+5 *5:13 0.0628727
+6 *5:11 0.0630183
+7 *419:io_in[13] *37:19 0
+8 *5:16 *100:12 0
*RES
1 io_in[13] *5:11 1.575
-2 *5:11 *5:13 654.57
+2 *5:11 *5:13 686.97
3 *5:13 *5:15 4.5
-4 *5:15 *5:16 363.15
-5 *5:16 *419:io_in[13] 47.565
+4 *5:15 *5:16 470.07
+5 *5:16 *419:io_in[13] 27.3874
*END
-*D_NET *6 0.218162
+*D_NET *6 0.239127
*CONN
*P io_in[14] I
-*I *419:io_in[14] I *D user_proj_example
+*I *419:io_in[14] I *D wrapped_vga_clock
*CAP
1 io_in[14] 0.00397136
-2 *419:io_in[14] 0.0025078
-3 *6:12 0.0459485
-4 *6:11 0.0434407
-5 *6:9 0.0557252
-6 *6:7 0.0596966
-7 *419:io_in[14] *38:15 0.002321
-8 *419:io_in[14] *45:10 0.00428972
-9 *419:io_in[14] *81:5 0
-10 *6:12 *419:io_in[16] 0.000260847
-11 *6:12 *46:9 0
+2 *419:io_in[14] 0.000353687
+3 *6:12 0.0543311
+4 *6:11 0.0539774
+5 *6:9 0.0607997
+6 *6:7 0.064771
+7 *419:io_in[14] *93:10 5.4397e-05
+8 *6:12 *38:12 0
+9 *6:12 *93:10 0.000868212
*RES
1 io_in[14] *6:7 43.425
-2 *6:7 *6:9 608.94
+2 *6:7 *6:9 664.2
3 *6:9 *6:11 4.5
-4 *6:11 *6:12 432.99
-5 *6:12 *419:io_in[14] 39.465
+4 *6:11 *6:12 541.89
+5 *6:12 *419:io_in[14] 12.9052
*END
-*D_NET *7 0.23226
+*D_NET *7 0.305791
*CONN
*P io_in[15] I
-*I *419:io_in[15] I *D user_proj_example
+*I *419:io_in[15] I *D wrapped_vga_clock
*CAP
-1 io_in[15] 0.000255689
-2 *419:io_in[15] 0.00261809
-3 *7:11 0.0503314
-4 *7:10 0.0477133
-5 *7:8 0.0655429
-6 *7:7 0.0657986
-7 *7:11 *14:10 0
-8 *7:11 *82:13 0
-9 *7:11 *95:13 0
+1 io_in[15] 0.00433622
+2 *419:io_in[15] 0.000941763
+3 *7:17 0.00325416
+4 *7:12 0.0704213
+5 *7:11 0.0681089
+6 *7:9 0.055017
+7 *7:7 0.0593532
+8 *7:12 *32:19 0
+9 *7:12 *39:17 0
+10 *7:12 *39:21 0
+11 *7:12 *61:11 0
+12 *7:12 *70:11 0.00370839
+13 *7:12 *72:14 0
+14 *7:12 *87:13 0.0143612
+15 *7:17 *8:19 0.0257164
+16 *4:16 *7:17 0.000572841
*RES
-1 io_in[15] *7:7 6.885
-2 *7:7 *7:8 642.87
-3 *7:8 *7:10 4.5
-4 *7:10 *7:11 475.38
-5 *7:11 *419:io_in[15] 23.895
+1 io_in[15] *7:7 43.245
+2 *7:7 *7:9 549.54
+3 *7:9 *7:11 4.5
+4 *7:11 *7:12 764.73
+5 *7:12 *7:17 49.23
+6 *7:17 *419:io_in[15] 8.865
*END
-*D_NET *8 0.257024
+*D_NET *8 0.785433
*CONN
*P io_in[16] I
-*I *419:io_in[16] I *D user_proj_example
+*I *419:io_in[16] I *D wrapped_vga_clock
*CAP
1 io_in[16] 0.000164983
-2 *419:io_in[16] 0.00227919
-3 *8:16 0.0467308
-4 *8:15 0.0444516
-5 *8:13 0.0480074
-6 *8:11 0.0481724
-7 *8:16 *15:16 0.0316444
-8 *8:16 *18:21 0.0146099
-9 *8:16 *22:13 0.0207025
-10 *8:16 *30:11 0
-11 *8:16 *102:10 0
-12 *5:16 *419:io_in[16] 0
-13 *6:12 *419:io_in[16] 0.000260847
+2 *419:io_in[16] 0.00089733
+3 *8:19 0.00409443
+4 *8:18 0.0031971
+5 *8:16 0.0290178
+6 *8:15 0.0290178
+7 *8:13 0.0595723
+8 *8:11 0.0597373
+9 *8:16 *40:12 0.000683868
+10 *8:16 *61:11 0
+11 *8:16 *71:11 0.000746036
+12 *8:16 *79:11 0.447808
+13 *8:16 *81:13 0.000663143
+14 *8:16 *101:11 0.0732974
+15 *8:19 *50:8 0.0206836
+16 *4:16 *8:19 0.0301355
+17 *7:17 *8:19 0.0257164
*RES
1 io_in[16] *8:11 1.935
-2 *8:11 *8:13 479.07
+2 *8:11 *8:13 594.99
3 *8:13 *8:15 4.5
-4 *8:15 *8:16 526.41
-5 *8:16 *419:io_in[16] 26.235
+4 *8:15 *8:16 656.55
+5 *8:16 *8:18 4.5
+6 *8:18 *8:19 80.91
+7 *8:19 *419:io_in[16] 13.185
*END
-*D_NET *9 0.185702
+*D_NET *9 0.430438
*CONN
*P io_in[17] I
-*I *419:io_in[17] I *D user_proj_example
+*I *419:io_in[17] I *D wrapped_vga_clock
*CAP
-1 io_in[17] 0.000291323
-2 *419:io_in[17] 0.00404386
-3 *9:16 0.0461628
-4 *9:15 0.0421189
-5 *9:13 0.046397
-6 *9:11 0.0466883
-7 *9:16 *70:12 0
+1 io_in[17] 0.00073246
+2 *419:io_in[17] 0.00223037
+3 *9:14 0.00824978
+4 *9:13 0.00601941
+5 *9:11 0.0569686
+6 *9:10 0.0569686
+7 *9:8 0.0238198
+8 *9:7 0.0245522
+9 *9:8 *13:10 0
+10 *9:8 *46:13 0.00389597
+11 *9:8 *46:15 0.0129313
+12 *9:8 *48:11 0.0164128
+13 *9:8 *85:11 0.056388
+14 *9:8 *87:17 0.115698
+15 *9:14 *49:17 0.0455705
*RES
-1 io_in[17] *9:11 3.015
-2 *9:11 *9:13 462.87
-3 *9:13 *9:15 4.5
-4 *9:15 *9:16 410.49
-5 *9:16 *419:io_in[17] 42.075
+1 io_in[17] *9:7 11.025
+2 *9:7 *9:8 416.97
+3 *9:8 *9:10 4.5
+4 *9:10 *9:11 569.61
+5 *9:11 *9:13 4.5
+6 *9:13 *9:14 93.15
+7 *9:14 *419:io_in[17] 34.963
*END
-*D_NET *10 0.354135
+*D_NET *10 0.312395
*CONN
*P io_in[18] I
-*I *419:io_in[18] I *D user_proj_example
+*I *419:io_in[18] I *D wrapped_vga_clock
*CAP
1 io_in[18] 0.000104982
-2 *419:io_in[18] 0.000612886
-3 *10:16 0.0060937
-4 *10:15 0.00548082
-5 *10:13 0.0496023
-6 *10:11 0.0497072
-7 *10:16 *23:19 0.0035359
-8 *10:16 *25:13 0.000696278
-9 *10:16 *57:8 0.0011605
-10 *10:16 *62:8 0.000507719
-11 *10:16 *74:8 0.0158066
-12 *10:16 *86:8 0.177246
-13 *10:16 *94:8 0.0400991
-14 *10:16 *98:8 0.00348148
+2 *419:io_in[18] 0.000707736
+3 *10:22 0.00438518
+4 *10:21 0.00391463
+5 *10:16 0.0183155
+6 *10:15 0.0180783
+7 *10:13 0.0693492
+8 *10:11 0.0694542
+9 *10:16 *45:14 0.0777535
+10 *10:16 *75:10 6.21698e-05
+11 *10:21 *30:16 0.00411217
+12 *10:21 *68:10 0.00046262
+13 *10:22 *59:8 0.0439538
+14 *10:22 *90:8 0.00174075
*RES
1 io_in[18] *10:11 1.395
-2 *10:11 *10:13 494.37
+2 *10:11 *10:13 692.01
3 *10:13 *10:15 4.5
-4 *10:15 *10:16 296.73
-5 *10:16 *419:io_in[18] 9.585
+4 *10:15 *10:16 337.77
+5 *10:16 *10:21 15.03
+6 *10:21 *10:22 71.19
+7 *10:22 *419:io_in[18] 10.845
*END
-*D_NET *11 0.313931
+*D_NET *11 0.243974
*CONN
*P io_in[19] I
-*I *419:io_in[19] I *D user_proj_example
+*I *419:io_in[19] I *D wrapped_vga_clock
*CAP
-1 io_in[19] 0.000224243
-2 *419:io_in[19] 0.000626102
-3 *11:16 0.00281522
-4 *11:15 0.00218912
-5 *11:13 0.0495846
-6 *11:11 0.0498088
-7 *419:io_in[19] *49:9 0
-8 *11:16 *23:19 0.020806
-9 *11:16 *25:13 0.0627291
-10 *11:16 *86:8 0.125147
+1 io_in[19] 0.000950832
+2 *419:io_in[19] 0.00112027
+3 *11:11 0.0649591
+4 *11:10 0.0638389
+5 *11:8 0.0311276
+6 *11:7 0.0320784
+7 *11:8 io_oeb[14] 0
+8 *11:8 io_oeb[21] 0
+9 *11:8 *13:10 0
+10 *11:8 *14:10 0
+11 *11:11 *74:8 0.0498985
*RES
-1 io_in[19] *11:11 2.475
-2 *11:11 *11:13 494.01
-3 *11:13 *11:15 4.5
-4 *11:15 *11:16 181.17
-5 *11:16 *419:io_in[19] 9.945
+1 io_in[19] *11:7 13.725
+2 *11:7 *11:8 339.57
+3 *11:8 *11:10 4.5
+4 *11:10 *11:11 669.87
+5 *11:11 *419:io_in[19] 15.705
*END
-*D_NET *12 0.37121
+*D_NET *12 0.182383
*CONN
*P io_in[1] I
-*I *419:io_in[1] I *D user_proj_example
+*I *419:io_in[1] I *D wrapped_vga_clock
*CAP
-1 io_in[1] 0.00148585
-2 *419:io_in[1] 0.000406751
-3 *12:14 0.0282624
-4 *12:13 0.0278557
-5 *12:11 0.0733365
-6 *12:10 0.0748223
-7 *419:io_in[1] *63:27 0.00491141
-8 *419:io_in[1] *69:8 0
-9 *12:10 *39:13 0
-10 *12:14 *39:7 0.160129
-11 *12:14 *66:13 0
-12 *12:14 *322:11 0
+1 io_in[1] 0.000280649
+2 *419:io_in[1] 0.038048
+3 *12:18 0.038048
+4 *12:16 0.0286075
+5 *12:15 0.0286075
+6 *12:13 0.0242554
+7 *12:11 0.0245361
*RES
-1 io_in[1] *12:10 23.895
-2 *12:10 *12:11 764.37
-3 *12:11 *12:13 4.5
-4 *12:13 *12:14 380.61
-5 *12:14 *419:io_in[1] 16.56
+1 io_in[1] *12:11 2.655
+2 *12:11 *12:13 265.77
+3 *12:13 *12:15 4.5
+4 *12:15 *12:16 285.21
+5 *12:16 *12:18 4.5
+6 *12:18 *419:io_in[1] 413.145
*END
-*D_NET *13 0.114427
+*D_NET *13 0.162664
*CONN
*P io_in[20] I
-*I *419:io_in[20] I *D user_proj_example
+*I *419:io_in[20] I *D wrapped_vga_clock
*CAP
-1 io_in[20] 0.00434068
-2 *419:io_in[20] 0.00263431
-3 *13:15 0.0107507
-4 *13:14 0.00811643
-5 *13:12 0.00656792
-6 *13:11 0.00656792
-7 *13:9 0.0355544
-8 *13:7 0.0398951
-9 *13:12 *75:12 0
-10 *13:15 *87:13 0
+1 io_in[20] 0.00097235
+2 *419:io_in[20] 0.0090363
+3 *13:13 0.0090363
+4 *13:11 0.0682775
+5 *13:10 0.0692499
+6 *419:io_in[20] *89:14 0.00609185
+7 *9:8 *13:10 0
+8 *11:8 *13:10 0
*RES
-1 io_in[20] *13:7 43.245
-2 *13:7 *13:9 355.14
-3 *13:9 *13:11 4.5
-4 *13:11 *13:12 70.29
-5 *13:12 *13:14 4.5
-6 *13:14 *13:15 79.74
-7 *13:15 *419:io_in[20] 23.895
+1 io_in[20] *13:10 18.495
+2 *13:10 *13:11 681.03
+3 *13:11 *13:13 4.5
+4 *13:13 *419:io_in[20] 124.245
*END
-*D_NET *14 0.109615
+*D_NET *14 0.143401
*CONN
*P io_in[21] I
-*I *419:io_in[21] I *D user_proj_example
+*I *419:io_in[21] I *D wrapped_vga_clock
*CAP
-1 io_in[21] 0.00109286
-2 *419:io_in[21] 0.00255376
-3 *14:19 0.0052569
-4 *14:14 0.00662667
-5 *14:11 0.048458
-6 *14:10 0.0456273
-7 *14:19 *89:17 0
-8 *7:11 *14:10 0
+1 io_in[21] 0.00115169
+2 *419:io_in[21] 7.31006e-05
+3 *14:17 0.00256769
+4 *14:11 0.0604352
+5 *14:10 0.0590923
+6 *14:10 *87:17 0
+7 *14:17 *37:19 0.0200808
+8 *11:8 *14:10 0
*RES
-1 io_in[21] *14:10 19.215
-2 *14:10 *14:11 444.33
-3 *14:11 *14:14 46.53
-4 *14:14 *14:19 30.51
-5 *14:19 *419:io_in[21] 23.085
+1 io_in[21] *14:10 19.575
+2 *14:10 *14:11 579.15
+3 *14:11 *14:17 46.8
+4 *14:17 *419:io_in[21] 9.74739
*END
-*D_NET *15 0.159723
+*D_NET *15 0.152061
*CONN
*P io_in[22] I
-*I *419:io_in[22] I *D user_proj_example
+*I *419:io_in[22] I *D wrapped_vga_clock
*CAP
1 io_in[22] 0.000290594
-2 *419:io_in[22] 0.00239432
-3 *15:16 0.0157859
-4 *15:15 0.0133916
-5 *15:13 0.0479627
-6 *15:11 0.0482533
-7 *419:io_in[22] *90:7 0
-8 *15:16 *30:11 0
-9 *15:16 *102:10 0
-10 *8:16 *15:16 0.0316444
+2 *419:io_in[22] 0.000416581
+3 *15:19 0.00269729
+4 *15:13 0.0616461
+5 *15:11 0.059656
+6 *15:13 *91:10 0.000393572
+7 *15:19 *87:8 0.0208064
+8 *15:19 *101:11 0.00615481
*RES
1 io_in[22] *15:11 3.015
-2 *15:11 *15:13 478.89
-3 *15:13 *15:15 4.5
-4 *15:15 *15:16 162.09
-5 *15:16 *419:io_in[22] 26.055
+2 *15:11 *15:13 594.63
+3 *15:13 *15:19 48.42
+4 *15:19 *419:io_in[22] 8.145
*END
-*D_NET *16 0.152159
+*D_NET *16 0.140372
*CONN
*P io_in[23] I
-*I *419:io_in[23] I *D user_proj_example
+*I *419:io_in[23] I *D wrapped_vga_clock
*CAP
1 io_in[23] 0.000104982
-2 *419:io_in[23] 0.00455443
-3 *16:16 0.0301942
-4 *16:15 0.0256398
-5 *16:13 0.0457802
-6 *16:11 0.0458852
-7 *16:16 *110:14 0
-8 *16:16 *111:10 0
+2 *419:io_in[23] 0.0094561
+3 *16:15 0.0094561
+4 *16:13 0.0606248
+5 *16:11 0.0607298
+6 *16:13 *18:16 0
*RES
1 io_in[23] *16:11 1.395
-2 *16:11 *16:13 457.47
+2 *16:11 *16:13 605.61
3 *16:13 *16:15 4.5
-4 *16:15 *16:16 275.49
-5 *16:16 *419:io_in[23] 46.935
+4 *16:15 *419:io_in[23] 100.125
*END
-*D_NET *17 0.210024
+*D_NET *17 0.388068
*CONN
*P io_in[24] I
-*I *419:io_in[24] I *D user_proj_example
+*I *419:io_in[24] I *D wrapped_vga_clock
*CAP
-1 io_in[24] 0.00112395
-2 *419:io_in[24] 0.00264576
-3 *17:11 0.0330545
-4 *17:10 0.0304088
-5 *17:8 0.0463462
-6 *17:7 0.0474702
-7 *419:io_in[24] *55:11 0
-8 *419:io_in[24] *92:9 0.000420424
-9 *17:11 *82:14 0.0485546
-10 *17:11 *102:10 0
+1 io_in[24] 0.0262269
+2 *419:io_in[24] 0.00014207
+3 *17:8 0.0478583
+4 *17:7 0.0477163
+5 *17:5 0.0262269
+6 *17:8 *21:16 0.214017
+7 *17:8 *40:12 0.00153439
+8 *17:8 *55:14 0
+9 *17:8 *66:8 0.0206836
+10 *17:8 *101:8 0.00366209
*RES
-1 io_in[24] *17:7 16.065
-2 *17:7 *17:8 463.05
-3 *17:8 *17:10 4.5
-4 *17:10 *17:11 357.93
-5 *17:11 *419:io_in[24] 30.555
+1 io_in[24] *17:5 285.705
+2 *17:5 *17:7 4.5
+3 *17:7 *17:8 635.67
+4 *17:8 *419:io_in[24] 5.985
*END
-*D_NET *18 0.167353
+*D_NET *18 0.155465
*CONN
*P io_in[25] I
-*I *419:io_in[25] I *D user_proj_example
+*I *419:io_in[25] I *D wrapped_vga_clock
*CAP
1 io_in[25] 0.000237175
-2 *419:io_in[25] 0.00240246
-3 *18:21 0.00350526
-4 *18:16 0.0408795
-5 *18:15 0.0397767
-6 *18:13 0.0328464
-7 *18:11 0.0330835
-8 *419:io_in[25] *22:8 1.22751e-05
-9 *18:21 *102:10 0
-10 *8:16 *18:21 0.0146099
+2 *419:io_in[25] 0.00952647
+3 *18:18 0.00952647
+4 *18:16 0.0599673
+5 *18:15 0.0599673
+6 *18:13 0.00800164
+7 *18:11 0.00823881
+8 *16:13 *18:16 0
*RES
1 io_in[25] *18:11 2.295
-2 *18:11 *18:13 357.21
+2 *18:11 *18:13 87.21
3 *18:13 *18:15 4.5
-4 *18:15 *18:16 395.55
-5 *18:16 *18:21 30.15
-6 *18:21 *419:io_in[25] 21.915
+4 *18:15 *18:16 598.95
+5 *18:16 *18:18 4.5
+6 *18:18 *419:io_in[25] 101.565
*END
-*D_NET *19 0.142081
+*D_NET *19 0.125748
*CONN
*P io_in[26] I
-*I *419:io_in[26] I *D user_proj_example
+*I *419:io_in[26] I *D wrapped_vga_clock
*CAP
1 io_in[26] 0.00010158
-2 *419:io_in[26] 0.00256146
-3 *19:16 0.0354208
-4 *19:15 0.0328593
-5 *19:13 0.0355184
-6 *19:11 0.0356199
-7 *419:io_in[26] *94:7 0
+2 *419:io_in[26] 0.0015846
+3 *19:16 0.0467772
+4 *19:15 0.0451926
+5 *19:13 0.0159954
+6 *19:11 0.0160969
*RES
1 io_in[26] *19:11 1.215
-2 *19:11 *19:13 385.65
+2 *19:11 *19:13 173.61
3 *19:13 *19:15 4.5
-4 *19:15 *19:16 326.88
-5 *19:16 *419:io_in[26] 23.355
+4 *19:15 *19:16 451.53
+5 *19:16 *419:io_in[26] 19.665
*END
-*D_NET *20 0.41346
+*D_NET *20 0.124098
*CONN
*P io_in[27] I
-*I *419:io_in[27] I *D user_proj_example
+*I *419:io_in[27] I *D wrapped_vga_clock
*CAP
-1 io_in[27] 0.00242728
-2 *419:io_in[27] 0.00291745
-3 *20:19 0.0185027
-4 *20:18 0.0155853
-5 *20:16 0.0252776
-6 *20:15 0.0277049
-7 *20:19 *58:10 0.25844
-8 *20:19 *95:10 0.062605
-9 *20:19 *101:10 0
+1 io_in[27] 0.000310538
+2 *419:io_in[27] 0.000985163
+3 *20:16 0.0377683
+4 *20:15 0.0367831
+5 *20:13 0.023934
+6 *20:11 0.0242445
+7 *419:io_in[27] *52:14 6.90477e-06
+8 *419:io_in[27] *93:11 0
+9 *419:io_in[27] *98:13 6.52783e-05
*RES
-1 io_in[27] *20:15 27.045
-2 *20:15 *20:16 252.45
-3 *20:16 *20:18 4.5
-4 *20:18 *20:19 374.13
-5 *20:19 *419:io_in[27] 31.455
+1 io_in[27] *20:11 2.835
+2 *20:11 *20:13 233.01
+3 *20:13 *20:15 4.5
+4 *20:15 *20:16 367.47
+5 *20:16 *419:io_in[27] 27.7474
*END
-*D_NET *21 0.125944
+*D_NET *21 0.31322
*CONN
*P io_in[28] I
-*I *419:io_in[28] I *D user_proj_example
+*I *419:io_in[28] I *D wrapped_vga_clock
*CAP
1 io_in[28] 0.000167681
-2 *419:io_in[28] 4.01718e-05
-3 *21:16 0.0214632
-4 *21:15 0.021423
-5 *21:13 0.0413413
-6 *21:11 0.041509
-7 *21:16 *97:13 0
+2 *419:io_in[28] 0.000172243
+3 *21:16 0.0173921
+4 *21:15 0.0172199
+5 *21:13 0.0294332
+6 *21:11 0.0296009
+7 *21:16 *101:8 0.00521694
+8 *17:8 *21:16 0.214017
*RES
1 io_in[28] *21:11 1.755
-2 *21:11 *21:13 401.85
+2 *21:11 *21:13 285.93
3 *21:13 *21:15 4.5
-4 *21:15 *21:16 210.87
-5 *21:16 *419:io_in[28] 0.405
+4 *21:15 *21:16 313.83
+5 *21:16 *419:io_in[28] 6.165
*END
-*D_NET *22 0.123662
+*D_NET *22 0.242186
*CONN
*P io_in[29] I
-*I *419:io_in[29] I *D user_proj_example
+*I *419:io_in[29] I *D wrapped_vga_clock
*CAP
-1 io_in[29] 0.035057
-2 *419:io_in[29] 0.00220971
-3 *22:13 0.0038167
-4 *22:8 0.0140212
-5 *22:7 0.0124142
-6 *22:5 0.035057
-7 *419:io_in[29] *97:12 0.000371323
-8 *22:8 *56:11 0
-9 *22:13 *102:10 0
-10 *419:io_in[25] *22:8 1.22751e-05
-11 *8:16 *22:13 0.0207025
+1 io_in[29] 0.0155824
+2 *419:io_in[29] 0.000295132
+3 *22:11 0.00283812
+4 *22:10 0.00254299
+5 *22:8 0.0339271
+6 *22:7 0.0339271
+7 *22:5 0.0155824
+8 *22:11 *42:8 0.0551395
+9 *22:11 *58:8 0.00615439
+10 *22:11 *64:8 0.00225883
+11 *22:11 *73:8 0.0573774
+12 *22:11 *89:8 0.000335457
+13 *22:11 *96:8 0.0162253
*RES
-1 io_in[29] *22:5 378.765
+1 io_in[29] *22:5 168.165
2 *22:5 *22:7 4.5
-3 *22:7 *22:8 122.85
-4 *22:8 *22:13 38.97
-5 *22:13 *419:io_in[29] 21.735
+3 *22:7 *22:8 338.13
+4 *22:8 *22:10 4.5
+5 *22:10 *22:11 113.13
+6 *22:11 *419:io_in[29] 7.065
*END
-*D_NET *23 0.510622
+*D_NET *23 0.157699
*CONN
*P io_in[2] I
-*I *419:io_in[2] I *D user_proj_example
+*I *419:io_in[2] I *D wrapped_vga_clock
*CAP
1 io_in[2] 0.000215438
-2 *419:io_in[2] 0.000626809
-3 *23:19 0.0107835
-4 *23:18 0.0101567
-5 *23:16 0.0336736
-6 *23:15 0.0336736
-7 *23:13 0.0309457
-8 *23:11 0.0311611
-9 *419:io_in[2] *61:9 0
-10 *23:16 *140:13 0
-11 *23:19 *25:13 0.151507
-12 *23:19 *26:19 0.156729
-13 *23:19 *28:11 0.00348146
-14 *23:19 *74:8 0
-15 *23:19 *86:8 0.0100715
-16 *23:19 *108:8 0.0132545
-17 *10:16 *23:19 0.0035359
-18 *11:16 *23:19 0.020806
+2 *419:io_in[2] 0.0493593
+3 *23:18 0.0493593
+4 *23:16 0.016359
+5 *23:15 0.016359
+6 *23:13 0.0129157
+7 *23:11 0.0131311
*RES
1 io_in[2] *23:11 2.115
-2 *23:11 *23:13 327.87
+2 *23:11 *23:13 141.57
3 *23:13 *23:15 4.5
-4 *23:15 *23:16 332.37
+4 *23:15 *23:16 163.17
5 *23:16 *23:18 4.5
-6 *23:18 *23:19 429.75
-7 *23:19 *419:io_in[2] 10.305
+6 *23:18 *419:io_in[2] 537.345
*END
-*D_NET *24 0.0932576
+*D_NET *24 0.0777088
*CONN
*P io_in[30] I
-*I *419:io_in[30] I *D user_proj_example
+*I *419:io_in[30] I *D wrapped_vga_clock
*CAP
1 io_in[30] 0.000237175
-2 *419:io_in[30] 0.00257955
-3 *24:16 0.00780899
-4 *24:15 0.00522944
-5 *24:13 0.0385826
-6 *24:11 0.0388198
-7 *419:io_in[30] *98:7 0
+2 *419:io_in[30] 0.00121317
+3 *24:16 0.0174712
+4 *24:15 0.0162581
+5 *24:13 0.0211227
+6 *24:11 0.0213599
+7 *419:io_in[30] *49:13 0
+8 *419:io_in[30] *93:11 0
+9 *419:io_in[30] *98:13 4.66274e-05
+10 *419:io_in[30] *98:14 0
*RES
1 io_in[30] *24:11 2.295
-2 *24:11 *24:13 415.35
+2 *24:11 *24:13 227.61
3 *24:13 *24:15 4.5
-4 *24:15 *24:16 51.48
-5 *24:16 *419:io_in[30] 23.895
+4 *24:15 *24:16 162.27
+5 *24:16 *419:io_in[30] 29.9074
*END
-*D_NET *25 0.308633
+*D_NET *25 0.165314
*CONN
*P io_in[31] I
-*I *419:io_in[31] I *D user_proj_example
+*I *419:io_in[31] I *D wrapped_vga_clock
*CAP
1 io_in[31] 0.00010158
-2 *419:io_in[31] 0.000620624
-3 *25:13 0.00922407
-4 *25:11 0.00870503
-5 *25:13 *26:19 0.0421925
-6 *25:13 *86:8 0.00058025
-7 *25:13 *94:8 0.0322763
-8 *10:16 *25:13 0.000696278
-9 *11:16 *25:13 0.0627291
-10 *23:19 *25:13 0.151507
+2 *419:io_in[31] 0.000588953
+3 *25:19 0.00163467
+4 *25:18 0.00104572
+5 *25:16 0.0204448
+6 *25:15 0.0204448
+7 *25:13 0.0158561
+8 *25:11 0.0159577
+9 *25:19 *54:8 0.032266
+10 *25:19 *59:8 0.00160165
+11 *25:19 *63:8 0.0531548
+12 *25:19 *86:13 0.00221731
*RES
1 io_in[31] *25:11 1.215
-2 *25:11 *25:13 424.89
-3 *25:13 *419:io_in[31] 10.125
+2 *25:11 *25:13 170.91
+3 *25:13 *25:15 4.5
+4 *25:15 *25:16 203.13
+5 *25:16 *25:18 4.5
+6 *25:18 *25:19 76.95
+7 *25:19 *419:io_in[31] 9.765
*END
-*D_NET *26 0.469592
+*D_NET *26 0.119046
*CONN
*P io_in[32] I
-*I *419:io_in[32] I *D user_proj_example
+*I *419:io_in[32] I *D wrapped_vga_clock
*CAP
-1 io_in[32] 0.00247302
-2 *419:io_in[32] 0.000662159
-3 *26:19 0.00835342
-4 *26:18 0.00769126
-5 *26:16 0.00710132
-6 *26:15 0.00957434
-7 *419:io_in[32] *64:9 0
-8 *26:19 *28:11 0.234815
-9 *23:19 *26:19 0.156729
-10 *25:13 *26:19 0.0421925
+1 io_in[32] 0.000310538
+2 *419:io_in[32] 0.000751389
+3 *26:16 0.00527137
+4 *26:15 0.00451998
+5 *26:13 0.0272117
+6 *26:11 0.0275223
+7 *26:16 *60:8 0.0534583
*RES
-1 io_in[32] *26:15 29.745
-2 *26:15 *26:16 70.65
-3 *26:16 *26:18 4.5
-4 *26:18 *26:19 410.13
-5 *26:19 *419:io_in[32] 10.485
+1 io_in[32] *26:11 2.835
+2 *26:11 *26:13 291.51
+3 *26:13 *26:15 4.5
+4 *26:15 *26:16 78.39
+5 *26:16 *419:io_in[32] 11.745
*END
-*D_NET *27 0.266088
+*D_NET *27 0.0400662
*CONN
*P io_in[33] I
-*I *419:io_in[33] I *D user_proj_example
+*I *419:io_in[33] I *D wrapped_vga_clock
*CAP
-1 io_in[33] 0.000167681
-2 *419:io_in[33] 0.00072738
-3 *27:19 0.0149681
-4 *27:18 0.0142408
-5 *27:16 0.0139219
-6 *27:15 0.0139219
-7 *27:13 0.0127525
-8 *27:11 0.0129202
-9 *27:19 *28:11 0.0183608
-10 *27:19 *40:10 0.00486988
-11 *27:19 *44:10 0.00598901
-12 *27:19 *50:10 0
-13 *27:19 *108:8 0.153248
+1 io_in[33] 0.00156645
+2 *419:io_in[33] 0.0184666
+3 *27:10 0.0200331
*RES
-1 io_in[33] *27:11 1.755
-2 *27:11 *27:13 138.51
-3 *27:13 *27:15 4.5
-4 *27:15 *27:16 138.69
-5 *27:16 *27:18 4.5
-6 *27:18 *27:19 301.59
-7 *27:19 *419:io_in[33] 11.025
+1 io_in[33] *27:10 24.795
+2 *27:10 *419:io_in[33] 178.425
*END
-*D_NET *28 0.48709
+*D_NET *28 0.0405681
*CONN
*P io_in[34] I
-*I *419:io_in[34] I *D user_proj_example
+*I *419:io_in[34] I *D wrapped_vga_clock
*CAP
-1 io_in[34] 0.00847721
-2 *419:io_in[34] 0.000729584
-3 *28:11 0.0067326
-4 *28:10 0.00600301
-5 *28:8 0.0206553
-6 *28:7 0.0206553
-7 *28:5 0.00847721
-8 *419:io_in[34] *66:9 0
-9 *28:5 *316:16 0
-10 *28:5 *342:16 0.000233137
-11 *28:5 *403:8 0
-12 *28:5 *418:14 0
-13 *28:11 *108:8 0.15847
-14 *23:19 *28:11 0.00348146
-15 *26:19 *28:11 0.234815
-16 *27:19 *28:11 0.0183608
+1 io_in[34] 0.0194104
+2 *419:io_in[34] 0.0008736
+3 *28:5 0.020284
+4 *28:5 *59:8 0
+5 *28:5 *314:8 0
*RES
-1 io_in[34] *28:5 92.565
-2 *28:5 *28:7 4.5
-3 *28:7 *28:8 205.83
-4 *28:8 *28:10 4.5
-5 *28:10 *28:11 355.05
-6 *28:11 *419:io_in[34] 10.665
+1 io_in[34] *28:5 211.005
+2 *28:5 *419:io_in[34] 11.925
*END
-*D_NET *29 0.150721
+*D_NET *29 0.0577165
*CONN
*P io_in[35] I
-*I *419:io_in[35] I *D user_proj_example
+*I *419:io_in[35] I *D wrapped_vga_clock
*CAP
1 io_in[35] 0.000237175
-2 *419:io_in[35] 0.00132881
-3 *29:19 0.0271911
-4 *29:18 0.0258623
-5 *29:16 0.0284093
-6 *29:15 0.0284093
-7 *29:13 0.017005
-8 *29:11 0.0172421
-9 *29:16 *321:13 0
-10 *29:19 *38:15 0
-11 *29:19 *45:10 0
-12 *29:19 *53:10 0
-13 *29:19 *92:10 0
-14 *29:19 *97:12 0.00503575
+2 *419:io_in[35] 0.000147297
+3 *29:22 0.00758816
+4 *29:21 0.00744087
+5 *29:19 0.0126837
+6 *29:18 0.0131
+7 *29:13 0.00834915
+8 *29:11 0.00817004
+9 *29:13 *105:10 0
*RES
1 io_in[35] *29:11 2.295
-2 *29:11 *29:13 179.01
-3 *29:13 *29:15 4.5
-4 *29:15 *29:16 280.89
-5 *29:16 *29:18 4.5
-6 *29:18 *29:19 274.95
-7 *29:19 *419:io_in[35] 16.875
+2 *29:11 *29:13 85.95
+3 *29:13 *29:18 13.05
+4 *29:18 *29:19 137.79
+5 *29:19 *29:21 4.5
+6 *29:21 *29:22 73.71
+7 *29:22 *419:io_in[35] 1.485
*END
-*D_NET *30 0.229358
+*D_NET *30 0.124911
*CONN
*P io_in[36] I
-*I *419:io_in[36] I *D user_proj_example
+*I *419:io_in[36] I *D wrapped_vga_clock
*CAP
-1 io_in[36] 0.000641502
-2 *419:io_in[36] 0.00215269
-3 *30:11 0.0457181
-4 *30:10 0.0435654
-5 *30:8 0.0307077
-6 *30:7 0.0313492
-7 *30:8 io_oeb[30] 1.38095e-05
-8 *30:8 *57:11 0.00988149
-9 *30:8 *94:11 0.00975874
-10 *30:8 *98:11 2.45503e-05
-11 *30:8 *106:17 0.055545
-12 *30:11 *93:10 0
-13 *419:io_in[13] *30:11 0
-14 *8:16 *30:11 0
-15 *15:16 *30:11 0
+1 io_in[36] 0.00010158
+2 *419:io_in[36] 0.00014207
+3 *30:16 0.0121588
+4 *30:15 0.0120168
+5 *30:13 0.0262048
+6 *30:11 0.0263064
+7 *30:16 *66:8 0.0427789
+8 *30:16 *68:10 0.00108942
+9 *30:16 *68:12 0
+10 *10:21 *30:16 0.00411217
*RES
-1 io_in[36] *30:7 10.845
-2 *30:7 *30:8 355.59
-3 *30:8 *30:10 4.5
-4 *30:10 *30:11 455.13
-5 *30:11 *419:io_in[36] 24.975
+1 io_in[36] *30:11 1.215
+2 *30:11 *30:13 285.75
+3 *30:13 *30:15 4.5
+4 *30:15 *30:16 154.53
+5 *30:16 *419:io_in[36] 5.985
*END
-*D_NET *31 0.184317
+*D_NET *31 0.0937783
*CONN
*P io_in[37] I
-*I *419:io_in[37] I *D user_proj_example
+*I *419:io_in[37] I *D wrapped_vga_clock
*CAP
1 io_in[37] 0.000310538
-2 *419:io_in[37] 0.00101523
-3 *31:16 0.0426983
-4 *31:15 0.0416831
-5 *31:13 0.0466316
-6 *31:11 0.0469421
-7 *419:io_in[37] *72:8 0
-8 *419:io_in[37] *74:8 0
-9 *419:io_in[37] *106:10 0.00503564
-10 *31:13 *127:8 0
-11 *31:13 *165:8 0
-12 *31:16 *34:8 0
+2 *419:io_in[37] 0.00937309
+3 *31:18 0.00937309
+4 *31:16 0.0289142
+5 *31:15 0.0289142
+6 *31:13 0.00829137
+7 *31:11 0.00860191
*RES
1 io_in[37] *31:11 2.835
-2 *31:11 *31:13 480.15
+2 *31:11 *31:13 89.91
3 *31:13 *31:15 4.5
-4 *31:15 *31:16 410.49
-5 *31:16 *419:io_in[37] 21.915
+4 *31:15 *31:16 288.45
+5 *31:16 *31:18 4.5
+6 *31:18 *419:io_in[37] 98.865
*END
-*D_NET *32 0.364549
+*D_NET *32 0.340504
*CONN
*P io_in[3] I
-*I *419:io_in[3] I *D user_proj_example
+*I *419:io_in[3] I *D wrapped_vga_clock
*CAP
-1 io_in[3] 0.000651608
-2 *419:io_in[3] 0.00320864
-3 *32:11 0.0716685
-4 *32:10 0.0684599
-5 *32:8 0.0170118
-6 *32:7 0.0176634
-7 *32:8 *39:13 0.0166328
-8 *32:8 *70:15 0.168845
-9 *32:11 *87:14 0
-10 *32:11 *89:16 0.000407989
-11 *2:11 *32:11 0
+1 io_in[3] 0.000145659
+2 *419:io_in[3] 0.000587619
+3 *32:19 0.0169639
+4 *32:18 0.0163763
+5 *32:16 0.0172074
+6 *32:15 0.0172074
+7 *32:13 0.0402882
+8 *32:11 0.0404339
+9 *32:19 *39:17 0.00700417
+10 *32:19 *39:21 0.0165993
+11 *32:19 *49:13 0.000686965
+12 *32:19 *72:14 0.143674
+13 *32:19 *92:11 0.000264222
+14 *32:19 *110:13 0.0230646
+15 *7:12 *32:19 0
*RES
-1 io_in[3] *32:7 11.025
-2 *32:7 *32:8 290.43
-3 *32:8 *32:10 4.5
-4 *32:10 *32:11 743.85
-5 *32:11 *419:io_in[3] 34.875
+1 io_in[3] *32:11 1.575
+2 *32:11 *32:13 441.27
+3 *32:13 *32:15 4.5
+4 *32:15 *32:16 170.37
+5 *32:16 *32:18 4.5
+6 *32:18 *32:19 304.47
+7 *32:19 *419:io_in[3] 19.0174
*END
-*D_NET *33 0.368612
+*D_NET *33 0.133035
*CONN
*P io_in[4] I
-*I *419:io_in[4] I *D user_proj_example
+*I *419:io_in[4] I *D wrapped_vga_clock
*CAP
-1 io_in[4] 0.00398561
-2 *419:io_in[4] 0.000180312
-3 *33:15 0.0308478
-4 *33:14 0.0306675
-5 *33:12 0.0194994
-6 *33:11 0.0194994
-7 *33:9 0.016465
-8 *33:7 0.0204506
-9 *33:9 *168:16 0
-10 *33:9 *217:14 0.0514144
-11 *33:9 *294:16 0.00648742
-12 *33:9 *296:16 0
-13 *33:9 *308:8 0
-14 *33:15 *71:9 0.00368042
-15 *33:15 *77:9 0
-16 *33:15 *88:9 0
-17 *33:15 *105:9 0.165434
+1 io_in[4] 0.00395713
+2 *419:io_in[4] 0.0285873
+3 *33:14 0.0324349
+4 *33:9 0.0333411
+5 *33:7 0.0334507
+6 *33:9 *75:11 0.00126412
*RES
1 io_in[4] *33:7 43.425
-2 *33:7 *33:9 244.44
-3 *33:9 *33:11 4.5
-4 *33:11 *33:12 194.49
-5 *33:12 *33:14 4.5
-6 *33:14 *33:15 455.13
-7 *33:15 *419:io_in[4] 15.03
+2 *33:7 *33:9 325.44
+3 *33:9 *33:14 46.89
+4 *33:14 *419:io_in[4] 310.545
*END
-*D_NET *34 0.455944
+*D_NET *34 0.126264
*CONN
*P io_in[5] I
-*I *419:io_in[5] I *D user_proj_example
+*I *419:io_in[5] I *D wrapped_vga_clock
*CAP
-1 io_in[5] 0.044307
-2 *419:io_in[5] 4.40767e-05
-3 *34:11 0.00258666
-4 *34:10 0.00254258
-5 *34:8 0.013807
-6 *34:7 0.013807
-7 *34:5 0.044307
-8 *419:io_in[5] *63:23 0.000165786
-9 *34:8 *106:11 0
-10 *34:11 *35:19 0.158471
-11 *34:11 *63:23 0.00288778
-12 *34:11 *71:9 0.173018
-13 *31:16 *34:8 0
+1 io_in[5] 0.0602513
+2 *419:io_in[5] 0.00288057
+3 *34:5 0.0631318
*RES
-1 io_in[5] *34:5 484.425
-2 *34:5 *34:7 4.5
-3 *34:7 *34:8 130.41
-4 *34:8 *34:10 4.5
-5 *34:10 *34:11 250.47
-6 *34:11 *419:io_in[5] 5.31
+1 io_in[5] *34:5 657.585
+2 *34:5 *419:io_in[5] 37.935
*END
-*D_NET *35 0.385036
+*D_NET *35 0.19885
*CONN
*P io_in[6] I
-*I *419:io_in[6] I *D user_proj_example
+*I *419:io_in[6] I *D wrapped_vga_clock
*CAP
1 io_in[6] 0.000280649
-2 *419:io_in[6] 0.000826912
-3 *35:19 0.00562476
-4 *35:18 0.00479785
-5 *35:16 0.00687912
-6 *35:15 0.00687912
-7 *35:13 0.0438408
-8 *35:11 0.0441215
-9 *419:io_in[6] *63:23 0.0092633
-10 *419:io_in[6] *69:8 0
-11 *419:io_in[6] *73:10 0
-12 *35:19 *63:7 0.00503574
-13 *35:19 *63:9 0.0977309
-14 *35:19 *63:23 4.14464e-05
-15 *35:19 *71:9 0.00124339
-16 *35:19 *73:10 0
-17 *34:11 *35:19 0.158471
+2 *419:io_in[6] 0.0015154
+3 *35:19 0.0268495
+4 *35:18 0.0268491
+5 *35:13 0.0386924
+6 *35:11 0.037458
+7 *419:io_in[6] *52:13 0
+8 *35:19 *419:io_in[9] 0
+9 *35:19 *51:17 0.0672054
*RES
1 io_in[6] *35:11 2.655
-2 *35:11 *35:13 479.07
-3 *35:13 *35:15 4.5
-4 *35:15 *35:16 68.49
-5 *35:16 *35:18 4.5
-6 *35:18 *35:19 234.81
-7 *35:19 *419:io_in[6] 27.81
+2 *35:11 *35:13 404.73
+3 *35:13 *35:18 24.03
+4 *35:18 *35:19 318.69
+5 *35:19 *419:io_in[6] 27.3404
*END
-*D_NET *36 0.470964
+*D_NET *36 0.154907
*CONN
*P io_in[7] I
-*I *419:io_in[7] I *D user_proj_example
+*I *419:io_in[7] I *D wrapped_vga_clock
*CAP
-1 io_in[7] 0.0040141
-2 *419:io_in[7] 0.000415593
-3 *36:9 0.039208
-4 *36:7 0.0428065
-5 *36:9 *77:9 0.38452
+1 io_in[7] 0.000215438
+2 *419:io_in[7] 0.0300633
+3 *36:18 0.0300633
+4 *36:16 0.0148348
+5 *36:15 0.0148348
+6 *36:13 0.0323397
+7 *36:11 0.0325552
*RES
-1 io_in[7] *36:7 43.425
-2 *36:7 *36:9 676.8
-3 *36:9 *419:io_in[7] 16.83
+1 io_in[7] *36:11 2.115
+2 *36:11 *36:13 352.17
+3 *36:13 *36:15 4.5
+4 *36:15 *36:16 147.51
+5 *36:16 *36:18 4.5
+6 *36:18 *419:io_in[7] 326.745
*END
-*D_NET *37 0.144111
+*D_NET *37 0.188182
*CONN
*P io_in[8] I
-*I *419:io_in[8] I *D user_proj_example
+*I *419:io_in[8] I *D wrapped_vga_clock
*CAP
1 io_in[8] 0.000145659
-2 *419:io_in[8] 4.01718e-05
-3 *37:16 0.0062618
-4 *37:15 0.00622163
-5 *37:13 0.0656478
-6 *37:11 0.0657934
-7 *37:13 *54:12 0
+2 *419:io_in[8] 0.000980041
+3 *37:19 0.0291341
+4 *37:18 0.0281541
+5 *37:16 0.0147484
+6 *37:15 0.0147484
+7 *37:13 0.0362613
+8 *37:11 0.0364069
+9 *37:19 *93:11 0.00752255
+10 *37:19 *97:13 0
+11 *419:io_in[13] *37:19 0
+12 *14:17 *37:19 0.0200808
*RES
1 io_in[8] *37:11 1.575
-2 *37:11 *37:13 712.53
+2 *37:11 *37:13 395.37
3 *37:13 *37:15 4.5
-4 *37:15 *37:16 59.67
-5 *37:16 *419:io_in[8] 0.405
+4 *37:15 *37:16 147.33
+5 *37:16 *37:18 4.5
+6 *37:18 *37:19 323.37
+7 *37:19 *419:io_in[8] 22.7974
*END
-*D_NET *38 0.29889
+*D_NET *38 0.175364
*CONN
*P io_in[9] I
-*I *419:io_in[9] I *D user_proj_example
+*I *419:io_in[9] I *D wrapped_vga_clock
*CAP
-1 io_in[9] 0.0039856
-2 *419:io_in[9] 0.00152778
-3 *38:15 0.00740946
-4 *38:14 0.00588168
-5 *38:12 0.0113518
-6 *38:11 0.0113518
-7 *38:9 0.045339
-8 *38:7 0.0493246
-9 *419:io_in[9] *113:5 0
-10 *38:15 *45:10 0.0826234
-11 *38:15 *92:10 0.0777741
-12 *419:io_in[14] *38:15 0.002321
-13 *29:19 *38:15 0
+1 io_in[9] 0.00401407
+2 *419:io_in[9] 0.00139047
+3 *38:12 0.0225204
+4 *38:11 0.0211299
+5 *38:9 0.0610837
+6 *38:7 0.0650977
+7 *419:io_in[9] *93:11 0.000127448
+8 *6:12 *38:12 0
+9 *35:19 *419:io_in[9] 0
*RES
1 io_in[9] *38:7 43.425
-2 *38:7 *38:9 495.54
+2 *38:7 *38:9 665.64
3 *38:9 *38:11 4.5
-4 *38:11 *38:12 112.05
-5 *38:12 *38:14 4.5
-6 *38:14 *38:15 167.49
-7 *38:15 *419:io_in[9] 18.315
+4 *38:11 *38:12 210.87
+5 *38:12 *419:io_in[9] 32.2474
*END
-*D_NET *39 0.665746
+*D_NET *39 0.214907
*CONN
*P io_oeb[0] O
-*I *419:io_oeb[0] O *D user_proj_example
+*I *419:io_oeb[0] O *D wrapped_vga_clock
*CAP
-1 io_oeb[0] 0.000621435
-2 *419:io_oeb[0] 0.000218713
-3 *39:13 0.0170058
-4 *39:12 0.0163844
-5 *39:10 0.0510574
-6 *39:9 0.0510574
-7 *39:7 0.00665096
-8 *39:5 0.00686968
-9 *39:7 *66:13 0.00281101
-10 *39:7 *103:13 0.0151892
-11 *39:10 *220:14 0.00109419
-12 *39:10 *224:10 0.00621689
-13 *39:10 *235:10 0.305937
-14 *39:10 *252:16 0.00786962
-15 *12:10 *39:13 0
-16 *12:14 *39:7 0.160129
-17 *32:8 *39:13 0.0166328
+1 io_oeb[0] 0.000310538
+2 *419:io_oeb[0] 0.00130657
+3 *39:25 0.0607264
+4 *39:24 0.0604159
+5 *39:22 0.032346
+6 *39:21 0.0336188
+7 *39:17 0.00257944
+8 *7:12 *39:17 0
+9 *7:12 *39:21 0
+10 *32:19 *39:17 0.00700417
+11 *32:19 *39:21 0.0165993
*RES
-1 *419:io_oeb[0] *39:5 2.205
-2 *39:5 *39:7 235.17
-3 *39:7 *39:9 4.5
-4 *39:9 *39:10 765.99
-5 *39:10 *39:12 4.5
-6 *39:12 *39:13 174.33
-7 *39:13 io_oeb[0] 10.845
+1 *419:io_oeb[0] *39:17 31.0774
+2 *39:17 *39:21 28.53
+3 *39:21 *39:22 321.39
+4 *39:22 *39:24 4.5
+5 *39:24 *39:25 662.67
+6 *39:25 io_oeb[0] 2.835
*END
-*D_NET *40 0.178336
+*D_NET *40 0.204425
*CONN
*P io_oeb[10] O
-*I *419:io_oeb[10] O *D user_proj_example
+*I *419:io_oeb[10] O *D wrapped_vga_clock
*CAP
1 io_oeb[10] 0.000310538
-2 *419:io_oeb[10] 0.00203937
-3 *40:14 0.0621581
-4 *40:13 0.0618476
-5 *40:11 0.0225356
-6 *40:10 0.024575
-7 *40:10 *50:10 0
-8 *40:10 *78:9 0
-9 *40:10 *90:11 0
-10 *40:11 *43:7 0
-11 *40:11 *43:9 0
-12 *419:io_in[13] *40:11 0
-13 *27:19 *40:10 0.00486988
+2 *419:io_oeb[10] 0.00106035
+3 *40:16 0.0604927
+4 *40:15 0.0601822
+5 *40:13 0.0324695
+6 *40:12 0.0335298
+7 *40:12 *55:14 0
+8 *40:12 *61:11 0.0141125
+9 *40:12 *101:11 4.89586e-05
+10 *8:16 *40:12 0.000683868
+11 *17:8 *40:12 0.00153439
*RES
-1 *419:io_oeb[10] *40:10 37.035
-2 *40:10 *40:11 222.93
-3 *40:11 *40:13 4.5
-4 *40:13 *40:14 673.47
-5 *40:14 io_oeb[10] 2.835
+1 *419:io_oeb[10] *40:12 32.625
+2 *40:12 *40:13 324.27
+3 *40:13 *40:15 4.5
+4 *40:15 *40:16 657.27
+5 *40:16 io_oeb[10] 2.835
*END
-*D_NET *41 0.193148
+*D_NET *41 0.249775
*CONN
*P io_oeb[11] O
-*I *419:io_oeb[11] O *D user_proj_example
+*I *419:io_oeb[11] O *D wrapped_vga_clock
*CAP
-1 io_oeb[11] 0.000237175
-2 *419:io_oeb[11] 0.000131093
-3 *41:10 0.0633868
-4 *41:9 0.0631496
-5 *41:7 0.0330559
-6 *41:5 0.033187
+1 io_oeb[11] 0.00111512
+2 *419:io_oeb[11] 0.0375001
+3 *41:8 0.0420594
+4 *41:7 0.0409443
+5 *41:5 0.0375001
+6 *41:5 *110:17 0.0906558
*RES
-1 *419:io_oeb[11] *41:5 1.305
-2 *41:5 *41:7 294.57
-3 *41:7 *41:9 4.5
-4 *41:9 *41:10 688.23
-5 *41:10 io_oeb[11] 2.295
+1 *419:io_oeb[11] *41:5 666.945
+2 *41:5 *41:7 4.5
+3 *41:7 *41:8 408.87
+4 *41:8 io_oeb[11] 16.425
*END
-*D_NET *42 0.271318
+*D_NET *42 0.372954
*CONN
*P io_oeb[12] O
-*I *419:io_oeb[12] O *D user_proj_example
+*I *419:io_oeb[12] O *D wrapped_vga_clock
*CAP
1 io_oeb[12] 0.000167681
-2 *419:io_oeb[12] 0.00373079
-3 *42:16 0.0486713
-4 *42:15 0.0485037
-5 *42:13 0.0326239
-6 *42:12 0.0326239
-7 *42:10 0.00913484
-8 *42:9 0.0128656
-9 *42:10 *46:10 0.0829967
+2 *419:io_oeb[12] 0.000308523
+3 *42:14 0.0598027
+4 *42:13 0.059635
+5 *42:11 0.0556261
+6 *42:10 0.0556261
+7 *42:8 0.00248335
+8 *42:7 0.00279187
+9 *42:8 *44:8 0.0551395
+10 *42:8 *53:8 0.000725313
+11 *42:8 *64:8 0.0185872
+12 *42:8 *73:8 0.00692089
+13 *22:11 *42:8 0.0551395
*RES
-1 *419:io_oeb[12] *42:9 39.375
-2 *42:9 *42:10 149.85
-3 *42:10 *42:12 4.5
-4 *42:12 *42:13 325.35
-5 *42:13 *42:15 4.5
-6 *42:15 *42:16 530.37
-7 *42:16 io_oeb[12] 1.755
+1 *419:io_oeb[12] *42:7 7.245
+2 *42:7 *42:8 109.89
+3 *42:8 *42:10 4.5
+4 *42:10 *42:11 554.31
+5 *42:11 *42:13 4.5
+6 *42:13 *42:14 651.87
+7 *42:14 io_oeb[12] 1.755
*END
-*D_NET *43 0.208971
+*D_NET *43 0.244656
*CONN
*P io_oeb[13] O
-*I *419:io_oeb[13] O *D user_proj_example
+*I *419:io_oeb[13] O *D wrapped_vga_clock
*CAP
1 io_oeb[13] 0.00010158
-2 *419:io_oeb[13] 0.00240663
-3 *43:12 0.0616661
-4 *43:11 0.0615645
-5 *43:9 0.040413
-6 *43:7 0.0428196
-7 *40:11 *43:7 0
-8 *40:11 *43:9 0
+2 *419:io_oeb[13] 0.000379914
+3 *43:13 0.0698042
+4 *43:12 0.0697026
+5 *43:10 0.0520407
+6 *43:9 0.0524206
+7 *43:10 *70:10 0.000205865
*RES
-1 *419:io_oeb[13] *43:7 22.005
-2 *43:7 *43:9 402.48
-3 *43:9 *43:11 4.5
-4 *43:11 *43:12 672.03
-5 *43:12 io_oeb[13] 1.215
+1 *419:io_oeb[13] *43:9 12.9052
+2 *43:9 *43:10 520.29
+3 *43:10 *43:12 4.5
+4 *43:12 *43:13 761.13
+5 *43:13 io_oeb[13] 1.215
*END
-*D_NET *44 0.224485
+*D_NET *44 0.348745
*CONN
*P io_oeb[14] O
-*I *419:io_oeb[14] O *D user_proj_example
+*I *419:io_oeb[14] O *D wrapped_vga_clock
*CAP
-1 io_oeb[14] 0.0584334
-2 *419:io_oeb[14] 0.00225091
-3 *44:13 0.0584334
-4 *44:11 0.0485635
-5 *44:10 0.0508144
-6 *44:10 *50:10 0
-7 *44:10 *82:13 0
-8 *44:11 *85:9 0
-9 *27:19 *44:10 0.00598901
+1 io_oeb[14] 0.0568877
+2 *419:io_oeb[14] 0.000332209
+3 *44:13 0.0568877
+4 *44:11 0.0686129
+5 *44:10 0.0686129
+6 *44:8 0.00253211
+7 *44:7 0.00286432
+8 *44:8 *53:8 0.0231874
+9 *44:8 *73:8 0.000745992
+10 *44:8 *78:8 0.00244792
+11 *44:8 *86:14 0.0104942
+12 *11:8 io_oeb[14] 0
+13 *42:8 *44:8 0.0551395
*RES
-1 *419:io_oeb[14] *44:10 41.895
-2 *44:10 *44:11 482.13
-3 *44:11 *44:13 4.5
-4 *44:13 io_oeb[14] 638.325
+1 *419:io_oeb[14] *44:7 7.425
+2 *44:7 *44:8 109.53
+3 *44:8 *44:10 4.5
+4 *44:10 *44:11 684.09
+5 *44:11 *44:13 4.5
+6 *44:13 io_oeb[14] 622.125
*END
-*D_NET *45 0.475664
+*D_NET *45 0.39008
*CONN
*P io_oeb[15] O
-*I *419:io_oeb[15] O *D user_proj_example
+*I *419:io_oeb[15] O *D wrapped_vga_clock
*CAP
-1 io_oeb[15] 0.000675824
-2 *419:io_oeb[15] 0.00156531
-3 *45:16 0.0285077
-4 *45:15 0.0278319
-5 *45:13 0.0482092
-6 *45:12 0.0482092
-7 *45:10 0.00636367
-8 *45:9 0.00792898
-9 *45:13 *101:9 0
-10 *45:16 io_oeb[19] 0
-11 *45:16 *46:16 0.182095
-12 *45:16 *87:20 0.037364
-13 *419:io_in[14] *45:10 0.00428972
-14 *29:19 *45:10 0
-15 *38:15 *45:10 0.0826234
+1 io_oeb[15] 0.000224243
+2 *419:io_oeb[15] 0.00238098
+3 *45:17 0.0695672
+4 *45:16 0.0693429
+5 *45:14 0.0201261
+6 *45:13 0.0225071
+7 *45:13 *53:8 0
+8 *45:13 *63:7 0
+9 *45:13 *63:8 0.0163505
+10 *45:13 *72:8 0.00012693
+11 *45:13 *86:14 0
+12 *45:14 *75:10 0.000901462
+13 *45:14 *82:11 0.034504
+14 *45:14 *109:11 0.0762946
+15 *10:16 *45:14 0.0777535
*RES
-1 *419:io_oeb[15] *45:9 18.495
-2 *45:9 *45:10 122.31
-3 *45:10 *45:12 4.5
-4 *45:12 *45:13 480.33
-5 *45:13 *45:15 4.5
-6 *45:15 *45:16 446.13
-7 *45:16 io_oeb[15] 11.025
+1 *419:io_oeb[15] *45:13 47.565
+2 *45:13 *45:14 602.19
+3 *45:14 *45:16 4.5
+4 *45:16 *45:17 692.37
+5 *45:17 io_oeb[15] 2.475
*END
-*D_NET *46 0.418426
+*D_NET *46 0.225466
*CONN
*P io_oeb[16] O
-*I *419:io_oeb[16] O *D user_proj_example
+*I *419:io_oeb[16] O *D wrapped_vga_clock
*CAP
-1 io_oeb[16] 0.000712394
-2 *419:io_oeb[16] 0.00379565
-3 *46:16 0.0141149
-4 *46:15 0.0134025
-5 *46:13 0.0460361
-6 *46:12 0.0460361
-7 *46:10 0.0127204
-8 *46:9 0.016516
-9 *6:12 *46:9 0
-10 *42:10 *46:10 0.0829967
-11 *45:16 *46:16 0.182095
+1 io_oeb[16] 0.000708774
+2 *419:io_oeb[16] 0.0377949
+3 *46:15 0.00491899
+4 *46:13 0.00520844
+5 *46:8 0.0613695
+6 *46:7 0.0603713
+7 *46:5 0.0377949
+8 *46:8 io_out[17] 3.68254e-05
+9 *46:13 *85:11 0.000435189
+10 *9:8 *46:13 0.00389597
+11 *9:8 *46:15 0.0129313
*RES
-1 *419:io_oeb[16] *46:9 39.735
-2 *46:9 *46:10 190.35
-3 *46:10 *46:12 4.5
-4 *46:12 *46:13 459.27
-5 *46:13 *46:15 4.5
-6 *46:15 *46:16 263.61
-7 *46:16 io_oeb[16] 10.845
+1 *419:io_oeb[16] *46:5 410.445
+2 *46:5 *46:7 4.5
+3 *46:7 *46:8 602.73
+4 *46:8 *46:13 22.41
+5 *46:13 *46:15 54.36
+6 *46:15 io_oeb[16] 10.845
*END
-*D_NET *47 0.163543
+*D_NET *47 0.217291
*CONN
*P io_oeb[17] O
-*I *419:io_oeb[17] O *D user_proj_example
+*I *419:io_oeb[17] O *D wrapped_vga_clock
*CAP
1 io_oeb[17] 0.000164983
-2 *419:io_oeb[17] 7.58801e-05
-3 *47:13 0.0451834
-4 *47:12 0.0450184
-5 *47:10 0.0311744
-6 *47:9 0.0311744
-7 *47:7 0.00533812
-8 *47:5 0.005414
-9 *47:10 *100:14 0
+2 *419:io_oeb[17] 0.00310524
+3 *47:17 0.0684647
+4 *47:16 0.0682997
+5 *47:14 0.0336875
+6 *47:13 0.0336875
+7 *47:11 0.00310524
+8 *47:11 *75:11 0.00428972
+9 *47:11 *84:10 0.00248679
+10 *47:11 *86:14 0
*RES
-1 *419:io_oeb[17] *47:5 0.765
-2 *47:5 *47:7 50.13
-3 *47:7 *47:9 4.5
-4 *47:9 *47:10 337.59
-5 *47:10 *47:12 4.5
-6 *47:12 *47:13 449.37
-7 *47:13 io_oeb[17] 1.935
+1 *419:io_oeb[17] *47:11 45.945
+2 *47:11 *47:13 4.5
+3 *47:13 *47:14 366.75
+4 *47:14 *47:16 4.5
+5 *47:16 *47:17 681.57
+6 *47:17 io_oeb[17] 1.935
*END
-*D_NET *48 0.142381
+*D_NET *48 0.214596
*CONN
*P io_oeb[18] O
-*I *419:io_oeb[18] O *D user_proj_example
+*I *419:io_oeb[18] O *D wrapped_vga_clock
*CAP
-1 io_oeb[18] 0.000290594
-2 *419:io_oeb[18] 0.00242914
-3 *48:15 0.0447814
-4 *48:14 0.0444908
-5 *48:12 0.0204943
-6 *48:11 0.0239799
-7 *48:7 0.00591475
+1 io_oeb[18] 0.000635658
+2 *419:io_oeb[18] 0.0139917
+3 *48:11 0.00675403
+4 *48:10 0.00611837
+5 *48:8 0.0624614
+6 *48:7 0.0624614
+7 *48:5 0.0139917
+8 *48:11 *87:17 0.0317688
+9 *9:8 *48:11 0.0164128
*RES
-1 *419:io_oeb[18] *48:7 22.005
-2 *48:7 *48:11 38.34
-3 *48:11 *48:12 221.49
-4 *48:12 *48:14 4.5
-5 *48:14 *48:15 443.97
-6 *48:15 io_oeb[18] 3.015
+1 *419:io_oeb[18] *48:5 151.245
+2 *48:5 *48:7 4.5
+3 *48:7 *48:8 623.25
+4 *48:8 *48:10 4.5
+5 *48:10 *48:11 117.27
+6 *48:11 io_oeb[18] 10.665
*END
-*D_NET *49 0.14018
+*D_NET *49 0.210993
*CONN
*P io_oeb[19] O
-*I *419:io_oeb[19] O *D user_proj_example
+*I *419:io_oeb[19] O *D wrapped_vga_clock
*CAP
-1 io_oeb[19] 0.00226796
-2 *419:io_oeb[19] 0.00190966
-3 *49:13 0.0500275
-4 *49:12 0.0477595
-5 *49:10 0.0021327
-6 *49:9 0.00404236
-7 *49:10 *52:10 0.0105067
-8 *49:10 *85:10 0.0094995
-9 *49:10 *91:10 0.00248675
-10 *49:10 *112:16 0.00954693
-11 *49:13 *101:9 0
-12 *419:io_in[19] *49:9 0
-13 *45:16 io_oeb[19] 0
+1 io_oeb[19] 0.000104982
+2 *419:io_oeb[19] 0.00158787
+3 *49:20 0.0577727
+4 *49:19 0.0576677
+5 *49:17 0.0155125
+6 *49:16 0.0169152
+7 *49:13 0.00299053
+8 *49:13 *98:13 0.0121229
+9 *49:16 *98:13 6.13758e-05
+10 *419:io_in[30] *49:13 0
+11 *9:14 *49:17 0.0455705
+12 *32:19 *49:13 0.000686965
*RES
-1 *419:io_oeb[19] *49:9 21.555
-2 *49:9 *49:10 94.77
-3 *49:10 *49:12 4.5
-4 *49:12 *49:13 476.01
-5 *49:13 io_oeb[19] 32.535
+1 *419:io_oeb[19] *49:13 44.4874
+2 *49:13 *49:16 18.09
+3 *49:16 *49:17 197.01
+4 *49:17 *49:19 4.5
+5 *49:19 *49:20 576.27
+6 *49:20 io_oeb[19] 1.395
*END
-*D_NET *50 0.533333
+*D_NET *50 0.20375
*CONN
*P io_oeb[1] O
-*I *419:io_oeb[1] O *D user_proj_example
+*I *419:io_oeb[1] O *D wrapped_vga_clock
*CAP
1 io_oeb[1] 0.000237175
-2 *419:io_oeb[1] 0.00103768
-3 *50:16 0.0240483
-4 *50:15 0.0238111
-5 *50:13 0.0360209
-6 *50:12 0.0360209
-7 *50:10 0.0307159
-8 *50:9 0.0317536
-9 *50:10 *61:10 0.347822
-10 *50:10 *64:10 0.00186502
-11 *50:13 *149:5 0
-12 *27:19 *50:10 0
-13 *40:10 *50:10 0
-14 *44:10 *50:10 0
+2 *419:io_oeb[1] 0.000867157
+3 *50:11 0.0716912
+4 *50:10 0.0714541
+5 *50:8 0.018975
+6 *50:7 0.0198422
+7 *8:19 *50:8 0.0206836
*RES
-1 *419:io_oeb[1] *50:9 14.175
-2 *50:9 *50:10 511.65
-3 *50:10 *50:12 4.5
-4 *50:12 *50:13 356.49
-5 *50:13 *50:15 4.5
-6 *50:15 *50:16 252.27
-7 *50:16 io_oeb[1] 2.295
+1 *419:io_oeb[1] *50:7 13.005
+2 *50:7 *50:8 202.05
+3 *50:8 *50:10 4.5
+4 *50:10 *50:11 782.91
+5 *50:11 io_oeb[1] 2.295
*END
-*D_NET *51 0.101935
+*D_NET *51 0.207378
*CONN
*P io_oeb[20] O
-*I *419:io_oeb[20] O *D user_proj_example
+*I *419:io_oeb[20] O *D wrapped_vga_clock
*CAP
-1 io_oeb[20] 0.00111678
-2 *419:io_oeb[20] 0.00261639
-3 *51:11 0.0483511
-4 *51:9 0.0498507
+1 io_oeb[20] 0.000224243
+2 *419:io_oeb[20] 0.0017478
+3 *51:20 0.0586936
+4 *51:19 0.0584693
+5 *51:17 0.00712691
+6 *51:16 0.00887471
+7 *51:16 *92:11 0.00503575
+8 *35:19 *51:17 0.0672054
*RES
-1 *419:io_oeb[20] *51:9 23.715
-2 *51:9 *51:11 469.98
-3 *51:11 io_oeb[20] 20.115
+1 *419:io_oeb[20] *51:16 42.0574
+2 *51:16 *51:17 118.89
+3 *51:17 *51:19 4.5
+4 *51:19 *51:20 584.19
+5 *51:20 io_oeb[20] 2.475
*END
-*D_NET *52 0.19808
+*D_NET *52 0.12065
*CONN
*P io_oeb[21] O
-*I *419:io_oeb[21] O *D user_proj_example
+*I *419:io_oeb[21] O *D wrapped_vga_clock
*CAP
-1 io_oeb[21] 0.00190563
-2 *419:io_oeb[21] 0.00188598
-3 *52:13 0.0496387
-4 *52:12 0.047733
-5 *52:10 0.00317576
-6 *52:9 0.00506174
-7 io_oeb[21] *53:16 0
-8 *52:10 *66:10 0.00219459
-9 *52:10 *91:10 0.0737954
-10 *52:10 *112:16 0.00218216
-11 *49:10 *52:10 0.0105067
+1 io_oeb[21] 0.00112874
+2 *419:io_oeb[21] 0.00103053
+3 *52:14 0.0592491
+4 *52:13 0.0591509
+5 io_oeb[21] *87:17 0
+6 *52:13 *93:11 0
+7 *52:13 *98:13 8.39292e-05
+8 *419:io_in[27] *52:14 6.90477e-06
+9 *419:io_in[6] *52:13 0
+10 *11:8 io_oeb[21] 0
*RES
-1 *419:io_oeb[21] *52:9 21.375
-2 *52:9 *52:10 106.83
-3 *52:10 *52:12 4.5
-4 *52:12 *52:13 476.19
-5 *52:13 io_oeb[21] 28.395
+1 *419:io_oeb[21] *52:13 28.2874
+2 *52:13 *52:14 580.77
+3 *52:14 io_oeb[21] 20.295
*END
-*D_NET *53 0.152375
+*D_NET *53 0.249316
*CONN
*P io_oeb[22] O
-*I *419:io_oeb[22] O *D user_proj_example
+*I *419:io_oeb[22] O *D wrapped_vga_clock
*CAP
1 io_oeb[22] 0.000671366
-2 *419:io_oeb[22] 0.00119076
-3 *53:16 0.0107725
-4 *53:15 0.0101011
-5 *53:13 0.0484647
-6 *53:12 0.0484647
-7 *53:10 0.00726104
-8 *53:9 0.0084518
-9 *53:10 *109:10 0.0169971
-10 *53:16 io_out[22] 0
-11 io_oeb[21] *53:16 0
-12 *29:19 *53:10 0
+2 *419:io_oeb[22] 0.000360359
+3 *53:16 0.00438783
+4 *53:11 0.0726604
+5 *53:10 0.0689439
+6 *53:8 0.00395757
+7 *53:7 0.00431793
+8 *53:8 *64:8 0.0378595
+9 *53:8 *86:14 0.00333644
+10 *53:8 *95:8 0.0270431
+11 *53:8 *96:8 0.00186498
+12 *53:16 io_out[22] 0
+13 *42:8 *53:8 0.000725313
+14 *44:8 *53:8 0.0231874
+15 *45:13 *53:8 0
*RES
-1 *419:io_oeb[22] *53:9 14.895
-2 *53:9 *53:10 123.03
-3 *53:10 *53:12 4.5
-4 *53:12 *53:13 483.39
-5 *53:13 *53:15 4.5
-6 *53:15 *53:16 110.43
-7 *53:16 io_oeb[22] 11.025
+1 *419:io_oeb[22] *53:7 7.605
+2 *53:7 *53:8 99.63
+3 *53:8 *53:10 4.5
+4 *53:10 *53:11 688.23
+5 *53:11 *53:16 49.23
+6 *53:16 io_oeb[22] 6.525
*END
-*D_NET *54 0.166234
+*D_NET *54 0.211562
*CONN
*P io_oeb[23] O
-*I *419:io_oeb[23] O *D user_proj_example
+*I *419:io_oeb[23] O *D wrapped_vga_clock
*CAP
1 io_oeb[23] 0.000290594
-2 *419:io_oeb[23] 0.00242331
-3 *54:15 0.0444604
-4 *54:14 0.0441698
-5 *54:12 0.03248
-6 *54:11 0.0362334
-7 *54:7 0.00617674
-8 *37:13 *54:12 0
+2 *419:io_oeb[23] 0.000606807
+3 *54:17 0.00718315
+4 *54:16 0.00689256
+5 *54:14 0.0127092
+6 *54:13 0.0127092
+7 *54:11 0.0629723
+8 *54:10 0.0629723
+9 *54:8 0.0011428
+10 *54:7 0.00174961
+11 *54:8 *59:8 0.00633741
+12 *54:8 *63:8 0.00373018
+13 *25:19 *54:8 0.032266
*RES
-1 *419:io_oeb[23] *54:7 22.005
-2 *54:7 *54:11 41.04
-3 *54:11 *54:12 351.09
-4 *54:12 *54:14 4.5
-5 *54:14 *54:15 441.27
-6 *54:15 io_oeb[23] 3.015
+1 *419:io_oeb[23] *54:7 9.945
+2 *54:7 *54:8 62.91
+3 *54:8 *54:10 4.5
+4 *54:10 *54:11 628.47
+5 *54:11 *54:13 4.5
+6 *54:13 *54:14 139.05
+7 *54:14 *54:16 4.5
+8 *54:16 *54:17 68.67
+9 *54:17 io_oeb[23] 3.015
*END
-*D_NET *55 0.157848
+*D_NET *55 0.243444
*CONN
*P io_oeb[24] O
-*I *419:io_oeb[24] O *D user_proj_example
+*I *419:io_oeb[24] O *D wrapped_vga_clock
*CAP
-1 io_oeb[24] 0.00126685
-2 *419:io_oeb[24] 0.00264131
-3 *55:14 0.0342216
-4 *55:13 0.0329547
-5 *55:11 0.0420612
-6 *55:9 0.0447025
-7 *419:io_in[24] *55:11 0
+1 io_oeb[24] 0.00125262
+2 *419:io_oeb[24] 0.000469779
+3 *55:17 0.0261522
+4 *55:16 0.0248996
+5 *55:14 0.0537262
+6 *55:13 0.0537835
+7 *55:8 0.00260507
+8 *55:7 0.00301758
+9 *55:8 *90:11 0.0483027
+10 *55:8 *107:8 0.0228931
+11 *55:13 *71:11 0.00317066
+12 *55:13 *79:11 0.00317066
+13 *17:8 *55:14 0
+14 *40:12 *55:14 0
*RES
-1 *419:io_oeb[24] *55:9 24.255
-2 *55:9 *55:11 418.68
-3 *55:11 *55:13 4.5
-4 *55:13 *55:14 359.28
-5 *55:14 io_oeb[24] 13.185
+1 *419:io_oeb[24] *55:7 9.045
+2 *55:7 *55:8 70.83
+3 *55:8 *55:13 13.59
+4 *55:13 *55:14 536.31
+5 *55:14 *55:16 4.5
+6 *55:16 *55:17 271.44
+7 *55:17 io_oeb[24] 13.185
*END
-*D_NET *56 0.145737
+*D_NET *56 0.204769
*CONN
*P io_oeb[25] O
-*I *419:io_oeb[25] O *D user_proj_example
+*I *419:io_oeb[25] O *D wrapped_vga_clock
*CAP
1 io_oeb[25] 0.000258912
-2 *419:io_oeb[25] 0.00258278
-3 *56:14 0.0352556
-4 *56:13 0.0349967
-5 *56:11 0.0350301
-6 *56:9 0.0376128
-7 *22:8 *56:11 0
+2 *419:io_oeb[25] 0.000974214
+3 *56:17 0.00878101
+4 *56:16 0.0085221
+5 *56:14 0.0458284
+6 *56:13 0.0458284
+7 *56:11 0.00660797
+8 *56:10 0.00758218
+9 *56:11 *93:11 0.0803856
*RES
-1 *419:io_oeb[25] *56:9 23.715
-2 *56:9 *56:11 348.48
+1 *419:io_oeb[25] *56:10 22.7974
+2 *56:10 *56:11 121.77
3 *56:11 *56:13 4.5
-4 *56:13 *56:14 380.25
-5 *56:14 io_oeb[25] 2.475
+4 *56:13 *56:14 457.83
+5 *56:14 *56:16 4.5
+6 *56:16 *56:17 92.61
+7 *56:17 io_oeb[25] 2.475
*END
-*D_NET *57 0.757642
+*D_NET *57 0.273654
*CONN
*P io_oeb[26] O
-*I *419:io_oeb[26] O *D user_proj_example
+*I *419:io_oeb[26] O *D wrapped_vga_clock
*CAP
-1 io_oeb[26] 0.000657415
-2 *419:io_oeb[26] 0.000561886
-3 *57:11 0.0127702
-4 *57:10 0.0121128
-5 *57:8 0.00418302
-6 *57:7 0.0047449
-7 *57:7 *95:9 0
-8 *57:8 *94:8 0.261174
-9 *57:8 *98:8 0.264407
-10 *57:11 *58:13 0.142576
-11 *57:11 *94:11 0.0170829
-12 *57:11 *98:11 0.0263302
-13 *10:16 *57:8 0.0011605
-14 *30:8 *57:11 0.00988149
+1 io_oeb[26] 0.000123625
+2 *419:io_oeb[26] 0.000691043
+3 *57:11 0.02702
+4 *57:10 0.0268964
+5 *57:8 0.0330405
+6 *57:7 0.0337316
+7 *57:8 *60:8 0.15215
*RES
-1 *419:io_oeb[26] *57:7 9.225
-2 *57:7 *57:8 383.13
+1 *419:io_oeb[26] *57:7 11.385
+2 *57:7 *57:8 428.31
3 *57:8 *57:10 4.5
-4 *57:10 *57:11 298.71
-5 *57:11 io_oeb[26] 11.025
+4 *57:10 *57:11 291.15
+5 *57:11 io_oeb[26] 1.395
*END
-*D_NET *58 0.59721
+*D_NET *58 0.130419
*CONN
*P io_oeb[27] O
-*I *419:io_oeb[27] O *D user_proj_example
+*I *419:io_oeb[27] O *D wrapped_vga_clock
*CAP
-1 io_oeb[27] 0.000641502
-2 *419:io_oeb[27] 0.00287591
-3 *58:13 0.00299826
-4 *58:12 0.00235676
-5 *58:10 0.0209352
-6 *58:9 0.0238112
-7 *58:10 *101:10 0
-8 *58:13 *94:11 0.142576
-9 *20:19 *58:10 0.25844
-10 *57:11 *58:13 0.142576
+1 io_oeb[27] 0.000332275
+2 *419:io_oeb[27] 0.000241929
+3 *58:14 0.0138566
+4 *58:13 0.0135243
+5 *58:11 0.0427975
+6 *58:10 0.0427975
+7 *58:8 0.00286209
+8 *58:7 0.00310402
+9 *58:8 *89:8 0.00151268
+10 *58:8 *96:8 0.00298401
+11 *58:8 *109:11 0.000251762
+12 *22:11 *58:8 0.00615439
*RES
-1 *419:io_oeb[27] *58:9 31.095
-2 *58:9 *58:10 390.15
-3 *58:10 *58:12 4.5
-4 *58:12 *58:13 209.07
-5 *58:13 io_oeb[27] 10.845
+1 *419:io_oeb[27] *58:7 6.705
+2 *58:7 *58:8 48.33
+3 *58:8 *58:10 4.5
+4 *58:10 *58:11 426.87
+5 *58:11 *58:13 4.5
+6 *58:13 *58:14 146.61
+7 *58:14 io_oeb[27] 3.015
*END
-*D_NET *59 0.109025
+*D_NET *59 0.184414
*CONN
*P io_oeb[28] O
-*I *419:io_oeb[28] O *D user_proj_example
+*I *419:io_oeb[28] O *D wrapped_vga_clock
*CAP
1 io_oeb[28] 0.000191629
-2 *419:io_oeb[28] 0.00240718
-3 *59:12 0.0376679
-4 *59:11 0.0374763
-5 *59:9 0.0144375
-6 *59:7 0.0168447
+2 *419:io_oeb[28] 0.000707367
+3 *59:14 0.0139588
+4 *59:13 0.0137672
+5 *59:11 0.0364681
+6 *59:10 0.0364681
+7 *59:8 0.00486682
+8 *59:7 0.00557419
+9 *59:8 *63:8 0.000202052
+10 *59:8 *86:13 0.00172827
+11 *59:8 *90:8 0.0185888
+12 *10:22 *59:8 0.0439538
+13 *25:19 *59:8 0.00160165
+14 *28:5 *59:8 0
+15 *54:8 *59:8 0.00633741
*RES
-1 *419:io_oeb[28] *59:7 22.005
-2 *59:7 *59:9 143.28
-3 *59:9 *59:11 4.5
-4 *59:11 *59:12 404.55
-5 *59:12 io_oeb[28] 1.935
+1 *419:io_oeb[28] *59:7 10.665
+2 *59:7 *59:8 128.79
+3 *59:8 *59:10 4.5
+4 *59:10 *59:11 363.33
+5 *59:11 *59:13 4.5
+6 *59:13 *59:14 149.31
+7 *59:14 io_oeb[28] 1.935
*END
-*D_NET *60 0.0967207
+*D_NET *60 0.288947
*CONN
*P io_oeb[29] O
-*I *419:io_oeb[29] O *D user_proj_example
+*I *419:io_oeb[29] O *D wrapped_vga_clock
*CAP
-1 io_oeb[29] 0.00132382
-2 *419:io_oeb[29] 0.00261935
-3 *60:14 0.0380685
-4 *60:13 0.0367447
-5 *60:11 0.00767252
-6 *60:9 0.0102919
+1 io_oeb[29] 0.00125262
+2 *419:io_oeb[29] 0.000706956
+3 *60:11 0.0271149
+4 *60:10 0.0258623
+5 *60:8 0.0138473
+6 *60:7 0.0145542
+7 *26:16 *60:8 0.0534583
+8 *57:8 *60:8 0.15215
*RES
-1 *419:io_oeb[29] *60:9 24.255
-2 *60:9 *60:11 75.78
-3 *60:11 *60:13 4.5
-4 *60:13 *60:14 397.08
-5 *60:14 io_oeb[29] 13.185
+1 *419:io_oeb[29] *60:7 11.565
+2 *60:7 *60:8 270.63
+3 *60:8 *60:10 4.5
+4 *60:10 *60:11 278.46
+5 *60:11 io_oeb[29] 13.185
*END
-*D_NET *61 0.656647
+*D_NET *61 0.193072
*CONN
*P io_oeb[2] O
-*I *419:io_oeb[2] O *D user_proj_example
+*I *419:io_oeb[2] O *D wrapped_vga_clock
*CAP
1 io_oeb[2] 0.000167681
-2 *419:io_oeb[2] 0.00101364
-3 *61:16 0.0232294
-4 *61:15 0.0230617
-5 *61:13 0.0295498
-6 *61:12 0.0295498
-7 *61:10 0.0178695
-8 *61:9 0.0188831
-9 *61:10 *64:10 0.15673
-10 *61:10 *65:8 0.0019065
-11 *61:10 *109:10 0.00686353
-12 *61:13 *150:13 0
-13 *419:io_in[2] *61:9 0
-14 *50:10 *61:10 0.347822
+2 *419:io_oeb[2] 0.000290299
+3 *61:17 0.0335267
+4 *61:16 0.033359
+5 *61:14 0.0190607
+6 *61:13 0.0190607
+7 *61:11 0.0270467
+8 *61:10 0.027337
+9 *61:11 *70:11 0.0189618
+10 *61:11 *101:11 0.000149208
+11 *7:12 *61:11 0
+12 *8:16 *61:11 0
+13 *40:12 *61:11 0.0141125
*RES
-1 *419:io_oeb[2] *61:9 13.815
-2 *61:9 *61:10 511.65
-3 *61:10 *61:12 4.5
-4 *61:12 *61:13 291.87
-5 *61:13 *61:15 4.5
-6 *61:15 *61:16 244.17
-7 *61:16 io_oeb[2] 1.755
+1 *419:io_oeb[2] *61:10 16.1374
+2 *61:10 *61:11 316.35
+3 *61:11 *61:13 4.5
+4 *61:13 *61:14 189.09
+5 *61:14 *61:16 4.5
+6 *61:16 *61:17 365.67
+7 *61:17 io_oeb[2] 1.755
*END
-*D_NET *62 0.44202
+*D_NET *62 0.0637209
*CONN
*P io_oeb[30] O
-*I *419:io_oeb[30] O *D user_proj_example
+*I *419:io_oeb[30] O *D wrapped_vga_clock
*CAP
-1 io_oeb[30] 0.00225899
-2 *419:io_oeb[30] 0.000478155
-3 *62:8 0.0166092
-4 *62:7 0.0148283
-5 io_oeb[30] *98:11 0.0055852
-6 *62:7 *100:9 0
-7 *62:8 *74:8 0.120173
-8 *62:8 *98:8 0.281566
-9 *10:16 *62:8 0.000507719
-10 *30:8 io_oeb[30] 1.38095e-05
+1 io_oeb[30] 0.00112395
+2 *419:io_oeb[30] 0.0165351
+3 *62:8 0.0153254
+4 *62:7 0.0142014
+5 *62:5 0.0165351
*RES
-1 *419:io_oeb[30] *62:7 8.865
-2 *62:7 *62:8 412.65
-3 *62:8 io_oeb[30] 40.995
+1 *419:io_oeb[30] *62:5 177.165
+2 *62:5 *62:7 4.5
+3 *62:7 *62:8 141.75
+4 *62:8 io_oeb[30] 16.065
*END
-*D_NET *63 0.195672
+*D_NET *63 0.148048
*CONN
*P io_oeb[31] O
-*I *419:io_oeb[31] O *D user_proj_example
+*I *419:io_oeb[31] O *D wrapped_vga_clock
*CAP
-1 io_oeb[31] 0.000123625
-2 *419:io_oeb[31] 0.00202486
-3 *63:31 0.0190512
-4 *63:30 0.0228234
-5 *63:27 0.00456517
-6 *63:23 0.0029359
-7 *63:9 0.00941107
-8 *63:7 0.00916932
-9 *63:7 *73:10 0
-10 *63:9 *73:10 0
-11 *63:23 *69:8 0
-12 *63:23 *71:9 0.000668324
-13 *63:23 *73:10 0
-14 *63:23 *104:9 0.00213967
-15 *63:27 *104:9 0.00243705
-16 *419:io_in[0] *63:27 0.00028598
-17 *419:io_in[1] *63:27 0.00491141
-18 *419:io_in[5] *63:23 0.000165786
-19 *419:io_in[6] *63:23 0.0092633
-20 *34:11 *63:23 0.00288778
-21 *35:19 *63:7 0.00503574
-22 *35:19 *63:9 0.0977309
-23 *35:19 *63:23 4.14464e-05
+1 io_oeb[31] 0.00357479
+2 *419:io_oeb[31] 0.000605598
+3 *63:11 0.019339
+4 *63:10 0.0157643
+5 *63:8 0.0161618
+6 *63:7 0.0167674
+7 *63:8 *72:8 0.0013553
+8 *63:8 *86:13 0.000397886
+9 *63:8 *90:8 0.000335716
+10 *63:8 *95:8 0
+11 *63:8 *113:8 0.000308258
+12 *25:19 *63:8 0.0531548
+13 *45:13 *63:7 0
+14 *45:13 *63:8 0.0163505
+15 *54:8 *63:8 0.00373018
+16 *59:8 *63:8 0.000202052
*RES
-1 *419:io_oeb[31] *63:7 41.49
-2 *63:7 *63:9 141.48
-3 *63:9 *63:23 49.5
-4 *63:23 *63:27 22.14
-5 *63:27 *63:30 43.29
-6 *63:30 *63:31 184.41
-7 *63:31 io_oeb[31] 1.395
+1 *419:io_oeb[31] *63:7 9.585
+2 *63:7 *63:8 235.17
+3 *63:8 *63:10 4.5
+4 *63:10 *63:11 157.05
+5 *63:11 io_oeb[31] 39.105
*END
-*D_NET *64 0.494865
+*D_NET *64 0.124688
*CONN
*P io_oeb[32] O
-*I *419:io_oeb[32] O *D user_proj_example
+*I *419:io_oeb[32] O *D wrapped_vga_clock
*CAP
-1 io_oeb[32] 0.00123761
-2 *419:io_oeb[32] 0.00105118
-3 *64:13 0.0129594
-4 *64:12 0.0117218
-5 *64:10 0.0127817
-6 *64:9 0.0138329
-7 *64:10 *65:8 0.282686
-8 *419:io_in[32] *64:9 0
-9 *50:10 *64:10 0.00186502
-10 *61:10 *64:10 0.15673
+1 io_oeb[32] 0.000332275
+2 *419:io_oeb[32] 0.000332209
+3 *64:14 0.0140223
+4 *64:13 0.01369
+5 *64:11 0.00852887
+6 *64:10 0.00852887
+7 *64:8 0.00117903
+8 *64:7 0.00151124
+9 *64:8 *96:8 0.0124956
+10 *64:14 *419:wb_clk_i 0.00536215
+11 *22:11 *64:8 0.00225883
+12 *42:8 *64:8 0.0185872
+13 *53:8 *64:8 0.0378595
*RES
-1 *419:io_oeb[32] *64:9 13.995
-2 *64:9 *64:10 422.73
-3 *64:10 *64:12 4.5
-4 *64:12 *64:13 116.73
-5 *64:13 io_oeb[32] 16.065
+1 *419:io_oeb[32] *64:7 7.425
+2 *64:7 *64:8 54.81
+3 *64:8 *64:10 4.5
+4 *64:10 *64:11 84.69
+5 *64:11 *64:13 4.5
+6 *64:13 *64:14 173.61
+7 *64:14 io_oeb[32] 3.015
*END
-*D_NET *65 0.505224
+*D_NET *65 0.0481863
*CONN
*P io_oeb[33] O
-*I *419:io_oeb[33] O *D user_proj_example
+*I *419:io_oeb[33] O *D wrapped_vga_clock
*CAP
-1 io_oeb[33] 0.00256853
-2 *419:io_oeb[33] 0.00104495
-3 *65:11 0.0213229
-4 *65:10 0.0187544
-5 *65:8 0.0126298
-6 *65:7 0.0136748
-7 *65:8 *109:10 0.150637
-8 *61:10 *65:8 0.0019065
-9 *64:10 *65:8 0.282686
+1 io_oeb[33] 0.000191629
+2 *419:io_oeb[33] 0.00911997
+3 *65:11 0.00874013
+4 *65:10 0.0085485
+5 *65:8 0.00623303
+6 *65:7 0.00623303
+7 *65:5 0.00911997
*RES
-1 *419:io_oeb[33] *65:7 13.365
-2 *65:7 *65:8 417.51
-3 *65:8 *65:10 4.5
-4 *65:10 *65:11 186.93
-5 *65:11 io_oeb[33] 31.545
+1 *419:io_oeb[33] *65:5 96.165
+2 *65:5 *65:7 4.5
+3 *65:7 *65:8 62.19
+4 *65:8 *65:10 4.5
+5 *65:10 *65:11 92.61
+6 *65:11 io_oeb[33] 1.935
*END
-*D_NET *66 0.475454
+*D_NET *66 0.1729
*CONN
*P io_oeb[34] O
-*I *419:io_oeb[34] O *D user_proj_example
+*I *419:io_oeb[34] O *D wrapped_vga_clock
*CAP
-1 io_oeb[34] 0.00126685
-2 *419:io_oeb[34] 0.00193258
-3 *66:16 0.0180914
-4 *66:15 0.0168246
-5 *66:13 0.0163481
-6 *66:12 0.0163481
-7 *66:10 0.00695318
-8 *66:9 0.00888576
-9 *66:10 *91:10 0
-10 *66:10 *93:10 1.2434e-05
-11 *66:10 *103:10 0.176375
-12 *66:10 *112:16 0.0977931
-13 *66:13 *101:13 0.0241207
-14 *66:13 *102:13 0.0701525
-15 *66:13 *103:13 0.0153439
-16 *419:io_in[34] *66:9 0
-17 *1:14 *66:13 0
-18 *12:14 *66:13 0
-19 *39:7 *66:13 0.00281101
-20 *52:10 *66:10 0.00219459
+1 io_oeb[34] 0.00125262
+2 *419:io_oeb[34] 0.000172243
+3 *66:11 0.026324
+4 *66:10 0.0250714
+5 *66:8 0.00513483
+6 *66:7 0.00530707
+7 *66:8 *101:8 0.0413059
+8 *66:8 *314:11 0.00486914
+9 *17:8 *66:8 0.0206836
+10 *30:16 *66:8 0.0427789
*RES
-1 *419:io_oeb[34] *66:9 22.455
-2 *66:9 *66:10 259.11
-3 *66:10 *66:12 4.5
-4 *66:12 *66:13 262.17
-5 *66:13 *66:15 4.5
-6 *66:15 *66:16 176.94
-7 *66:16 io_oeb[34] 13.185
+1 *419:io_oeb[34] *66:7 6.165
+2 *66:7 *66:8 126.45
+3 *66:8 *66:10 4.5
+4 *66:10 *66:11 273.06
+5 *66:11 io_oeb[34] 13.185
*END
-*D_NET *67 0.446112
+*D_NET *67 0.0690405
*CONN
*P io_oeb[35] O
-*I *419:io_oeb[35] O *D user_proj_example
+*I *419:io_oeb[35] O *D wrapped_vga_clock
*CAP
1 io_oeb[35] 0.000258912
-2 *419:io_oeb[35] 0.000121436
-3 *67:14 0.0159841
-4 *67:13 0.0157252
-5 *67:11 0.0319093
-6 *67:10 0.0319093
-7 *67:8 0.00614837
-8 *67:7 0.0062698
-9 *67:8 *68:8 0.010403
-10 *67:8 *72:8 0.156729
-11 *67:8 *99:8 0.170654
-12 *67:11 *352:9 0
-13 *67:11 *384:17 0
-14 *67:14 *352:12 0
+2 *419:io_oeb[35] 0.00853611
+3 *67:11 0.00929364
+4 *67:10 0.00903473
+5 *67:8 0.0166905
+6 *67:7 0.0166905
+7 *67:5 0.00853611
*RES
-1 *419:io_oeb[35] *67:7 5.445
-2 *67:7 *67:8 292.23
-3 *67:8 *67:10 4.5
-4 *67:10 *67:11 316.71
-5 *67:11 *67:13 4.5
-6 *67:13 *67:14 165.51
-7 *67:14 io_oeb[35] 2.475
+1 *419:io_oeb[35] *67:5 90.765
+2 *67:5 *67:7 4.5
+3 *67:7 *67:8 166.41
+4 *67:8 *67:10 4.5
+5 *67:10 *67:11 98.01
+6 *67:11 io_oeb[35] 2.475
*END
-*D_NET *68 0.591978
+*D_NET *68 0.0923118
*CONN
*P io_oeb[36] O
-*I *419:io_oeb[36] O *D user_proj_example
+*I *419:io_oeb[36] O *D wrapped_vga_clock
*CAP
-1 io_oeb[36] 0.00275085
-2 *419:io_oeb[36] 7.40635e-05
-3 *68:11 0.0411754
-4 *68:10 0.0384246
-5 *68:8 0.0104967
-6 *68:7 0.0105708
-7 *68:8 *69:8 0.302206
-8 *68:8 *99:8 0.175877
-9 *68:11 *315:15 0
-10 *68:11 *348:13 0
-11 *67:8 *68:8 0.010403
+1 io_oeb[36] 0.000123625
+2 *419:io_oeb[36] 0.00329798
+3 *68:15 0.0261444
+4 *68:14 0.0260207
+5 *68:12 0.0159375
+6 *68:10 0.0192355
+7 *10:21 *68:10 0.00046262
+8 *30:16 *68:10 0.00108942
+9 *30:16 *68:12 0
*RES
-1 *419:io_oeb[36] *68:7 5.085
-2 *68:7 *68:8 437.49
-3 *68:8 *68:10 4.5
-4 *68:10 *68:11 383.85
-5 *68:11 io_oeb[36] 33.705
+1 *419:io_oeb[36] *68:10 43.335
+2 *68:10 *68:12 159.3
+3 *68:12 *68:14 4.5
+4 *68:14 *68:15 284.31
+5 *68:15 io_oeb[36] 1.395
*END
-*D_NET *69 0.588293
+*D_NET *69 0.115587
*CONN
*P io_oeb[37] O
-*I *419:io_oeb[37] O *D user_proj_example
+*I *419:io_oeb[37] O *D wrapped_vga_clock
*CAP
-1 io_oeb[37] 0.00163658
-2 *419:io_oeb[37] 5.03775e-05
-3 *69:11 0.0468165
-4 *69:10 0.0451799
-5 *69:8 0.0145796
-6 *69:7 0.01463
-7 *69:8 *73:10 0.161453
-8 *69:8 *99:8 0.00174075
-9 *69:11 *313:13 0
-10 *419:io_in[0] *69:8 0
-11 *419:io_in[1] *69:8 0
-12 *419:io_in[6] *69:8 0
-13 *63:23 *69:8 0
-14 *68:8 *69:8 0.302206
+1 io_oeb[37] 0.000332275
+2 *419:io_oeb[37] 2.05233e-05
+3 *69:13 0.00987936
+4 *69:12 0.00954708
+5 *69:10 0.0358178
+6 *69:9 0.0358178
+7 *69:7 0.00519845
+8 *69:5 0.00521897
+9 *69:7 *71:11 0.0080199
+10 *69:7 *101:11 0.00573516
*RES
-1 *419:io_oeb[37] *69:7 4.905
-2 *69:7 *69:8 455.85
-3 *69:8 *69:10 4.5
-4 *69:10 *69:11 451.35
-5 *69:11 io_oeb[37] 21.465
+1 *419:io_oeb[37] *69:5 0.225
+2 *69:5 *69:7 85.41
+3 *69:7 *69:9 4.5
+4 *69:9 *69:10 357.21
+5 *69:10 *69:12 4.5
+6 *69:12 *69:13 103.41
+7 *69:13 io_oeb[37] 3.015
*END
-*D_NET *70 0.374207
+*D_NET *70 0.183167
*CONN
*P io_oeb[3] O
-*I *419:io_oeb[3] O *D user_proj_example
+*I *419:io_oeb[3] O *D wrapped_vga_clock
*CAP
-1 io_oeb[3] 0.000621435
-2 *419:io_oeb[3] 0.00401224
-3 *70:15 0.00906623
-4 *70:14 0.0084448
-5 *70:12 0.0705047
-6 *70:11 0.0745169
-7 *70:15 *110:17 0.031629
-8 *2:8 *70:15 0.0065672
-9 *9:16 *70:12 0
-10 *32:8 *70:15 0.168845
+1 io_oeb[3] 0.00010158
+2 *419:io_oeb[3] 0.000235193
+3 *70:17 0.0598038
+4 *70:16 0.0597022
+5 *70:14 0.012643
+6 *70:13 0.012643
+7 *70:11 0.00746326
+8 *70:10 0.00769846
+9 *70:11 *101:11 0
+10 *7:12 *70:11 0.00370839
+11 *43:10 *70:10 0.000205865
+12 *61:11 *70:11 0.0189618
*RES
-1 *419:io_oeb[3] *70:11 42.885
-2 *70:11 *70:12 741.33
-3 *70:12 *70:14 4.5
-4 *70:14 *70:15 255.69
-5 *70:15 io_oeb[3] 10.845
+1 *419:io_oeb[3] *70:10 16.3174
+2 *70:10 *70:11 107.37
+3 *70:11 *70:13 4.5
+4 *70:13 *70:14 124.47
+5 *70:14 *70:16 4.5
+6 *70:16 *70:17 654.57
+7 *70:17 io_oeb[3] 1.215
*END
-*D_NET *71 0.46228
+*D_NET *71 0.316031
*CONN
*P io_oeb[4] O
-*I *419:io_oeb[4] O *D user_proj_example
+*I *419:io_oeb[4] O *D wrapped_vga_clock
*CAP
-1 io_oeb[4] 0.0435619
-2 *419:io_oeb[4] 0.00010681
-3 *71:14 0.0435619
-4 *71:12 0.015202
-5 *71:11 0.015202
-6 *71:9 0.00285826
-7 *71:8 0.00296507
-8 *71:9 *104:9 0.158471
-9 *71:9 *105:9 0.00174075
-10 *33:15 *71:9 0.00368042
-11 *34:11 *71:9 0.173018
-12 *35:19 *71:9 0.00124339
-13 *63:23 *71:9 0.000668324
+1 io_oeb[4] 0.00060551
+2 *419:io_oeb[4] 0.00316539
+3 *71:14 0.00635202
+4 *71:13 0.00574651
+5 *71:11 0.0415401
+6 *71:10 0.0415401
+7 *71:8 0.00316539
+8 *71:8 *74:8 0.0231386
+9 *71:11 *79:11 0.175505
+10 *71:11 *81:13 0.00304632
+11 *71:11 *101:11 0.000290125
+12 *8:16 *71:11 0.000746036
+13 *55:13 *71:11 0.00317066
+14 *69:7 *71:11 0.0080199
*RES
-1 *419:io_oeb[4] *71:8 14.49
-2 *71:8 *71:9 263.61
-3 *71:9 *71:11 4.5
-4 *71:11 *71:12 151.83
-5 *71:12 *71:14 4.5
-6 *71:14 io_oeb[4] 476.325
+1 *419:io_oeb[4] *71:8 49.995
+2 *71:8 *71:10 4.5
+3 *71:10 *71:11 779.85
+4 *71:11 *71:13 4.5
+5 *71:13 *71:14 57.33
+6 *71:14 io_oeb[4] 10.665
*END
-*D_NET *72 0.298276
+*D_NET *72 0.319848
*CONN
*P io_oeb[5] O
-*I *419:io_oeb[5] O *D user_proj_example
+*I *419:io_oeb[5] O *D wrapped_vga_clock
*CAP
1 io_oeb[5] 0.000310538
-2 *419:io_oeb[5] 0.00013929
-3 *72:14 0.0436533
-4 *72:13 0.0433427
-5 *72:11 0.00931207
-6 *72:10 0.00931207
-7 *72:8 0.014001
-8 *72:7 0.0141403
-9 *72:7 *110:13 0
-10 *72:8 *99:8 0.00733598
-11 *419:io_in[37] *72:8 0
-12 *67:8 *72:8 0.156729
+2 *419:io_oeb[5] 0.000630482
+3 *72:14 0.0513453
+4 *72:13 0.0510348
+5 *72:11 0.0108207
+6 *72:10 0.0108207
+7 *72:8 0.000871017
+8 *72:7 0.0015015
+9 *72:8 *75:11 0.00114392
+10 *72:8 *84:10 0.0078541
+11 *72:8 *113:8 0.0383588
+12 *7:12 *72:14 0
+13 *32:19 *72:14 0.143674
+14 *45:13 *72:8 0.00012693
+15 *63:8 *72:8 0.0013553
*RES
-1 *419:io_oeb[5] *72:7 5.625
-2 *72:7 *72:8 258.75
+1 *419:io_oeb[5] *72:7 10.125
+2 *72:7 *72:8 55.53
3 *72:8 *72:10 4.5
-4 *72:10 *72:11 92.79
+4 *72:10 *72:11 106.29
5 *72:11 *72:13 4.5
-6 *72:13 *72:14 473.67
+6 *72:13 *72:14 649.17
7 *72:14 io_oeb[5] 2.835
*END
-*D_NET *73 0.286786
+*D_NET *73 0.271272
*CONN
*P io_oeb[6] O
-*I *419:io_oeb[6] O *D user_proj_example
+*I *419:io_oeb[6] O *D wrapped_vga_clock
*CAP
-1 io_oeb[6] 0.00434283
-2 *419:io_oeb[6] 0.000103026
-3 *73:15 0.00706424
-4 *73:10 0.0535071
-5 *73:9 0.0508887
-6 *73:9 *111:9 2.68519e-05
-7 *73:10 *99:8 0.00940003
-8 *419:io_in[6] *73:10 0
-9 *35:19 *73:10 0
-10 *63:7 *73:10 0
-11 *63:9 *73:10 0
-12 *63:23 *73:10 0
-13 *69:8 *73:10 0.161453
+1 io_oeb[6] 0.000237175
+2 *419:io_oeb[6] 0.000261151
+3 *73:14 0.0595411
+4 *73:13 0.0593039
+5 *73:11 0.0169829
+6 *73:10 0.0169829
+7 *73:8 0.002999
+8 *73:7 0.00326015
+9 *73:8 *78:8 0.0378574
+10 *73:8 *89:8 0.00880242
+11 *22:11 *73:8 0.0573774
+12 *42:8 *73:8 0.00692089
+13 *44:8 *73:8 0.000745992
*RES
-1 *419:io_oeb[6] *73:9 5.535
-2 *73:9 *73:10 679.77
-3 *73:10 *73:15 36.09
-4 *73:15 io_oeb[6] 46.665
+1 *419:io_oeb[6] *73:7 6.885
+2 *73:7 *73:8 118.53
+3 *73:8 *73:10 4.5
+4 *73:10 *73:11 167.85
+5 *73:11 *73:13 4.5
+6 *73:13 *73:14 646.47
+7 *73:14 io_oeb[6] 2.295
*END
-*D_NET *74 0.323465
+*D_NET *74 0.397559
*CONN
*P io_oeb[7] O
-*I *419:io_oeb[7] O *D user_proj_example
+*I *419:io_oeb[7] O *D wrapped_vga_clock
*CAP
-1 io_oeb[7] 0.00253818
-2 *419:io_oeb[7] 0.000490828
-3 *74:8 0.0508995
-4 *74:7 0.0488522
-5 io_oeb[7] *111:13 0.0238752
-6 *74:8 *90:8 0.0604907
-7 *74:8 *106:10 0.00033882
-8 *419:io_in[37] *74:8 0
-9 *10:16 *74:8 0.0158066
-10 *23:19 *74:8 0
-11 *62:8 *74:8 0.120173
+1 io_oeb[7] 0.000621435
+2 *419:io_oeb[7] 0.00116469
+3 *74:14 0.00724455
+4 *74:13 0.00662311
+5 *74:11 0.0757531
+6 *74:10 0.0757531
+7 *74:8 0.00265287
+8 *74:7 0.00381756
+9 *74:11 *112:13 0.0699371
+10 *74:14 *79:14 0.0809546
+11 *11:11 *74:8 0.0498985
+12 *71:8 *74:8 0.0231386
*RES
-1 *419:io_oeb[7] *74:7 8.685
-2 *74:7 *74:8 711.63
-3 *74:8 io_oeb[7] 49.635
+1 *419:io_oeb[7] *74:7 15.885
+2 *74:7 *74:8 73.17
+3 *74:8 *74:10 4.5
+4 *74:10 *74:11 779.49
+5 *74:11 *74:13 4.5
+6 *74:13 *74:14 118.71
+7 *74:14 io_oeb[7] 10.845
*END
-*D_NET *75 0.152063
+*D_NET *75 0.213002
*CONN
*P io_oeb[8] O
-*I *419:io_oeb[8] O *D user_proj_example
+*I *419:io_oeb[8] O *D wrapped_vga_clock
*CAP
1 io_oeb[8] 0.00010158
-2 *419:io_oeb[8] 0.00238831
-3 *75:12 0.0654529
-4 *75:11 0.0653513
-5 *75:9 0.00819008
-6 *75:7 0.0105784
-7 *13:12 *75:12 0
+2 *419:io_oeb[8] 0.000682717
+3 *75:17 0.0333774
+4 *75:16 0.0332758
+5 *75:14 0.0301742
+6 *75:13 0.0301742
+7 *75:11 0.0185225
+8 *75:10 0.0192052
+9 *75:11 *84:10 0.0139882
+10 *75:11 *86:14 0
+11 *75:11 *113:8 0.0258393
+12 *10:16 *75:10 6.21698e-05
+13 *33:9 *75:11 0.00126412
+14 *45:14 *75:10 0.000901462
+15 *47:11 *75:11 0.00428972
+16 *72:8 *75:11 0.00114392
*RES
-1 *419:io_oeb[8] *75:7 22.005
-2 *75:7 *75:9 81.18
-3 *75:9 *75:11 4.5
-4 *75:11 *75:12 709.83
-5 *75:12 io_oeb[8] 1.215
+1 *419:io_oeb[8] *75:10 14.895
+2 *75:10 *75:11 314.73
+3 *75:11 *75:13 4.5
+4 *75:13 *75:14 300.15
+5 *75:14 *75:16 4.5
+6 *75:16 *75:17 362.97
+7 *75:17 io_oeb[8] 1.215
*END
-*D_NET *76 0.164228
+*D_NET *76 0.193028
*CONN
*P io_oeb[9] O
-*I *419:io_oeb[9] O *D user_proj_example
+*I *419:io_oeb[9] O *D wrapped_vga_clock
*CAP
-1 io_oeb[9] 0.064805
-2 *419:io_oeb[9] 0.00261797
-3 *76:13 0.064805
-4 *76:11 0.0146912
-5 *76:9 0.0173092
-6 *76:9 *114:14 0
+1 io_oeb[9] 0.0305436
+2 *419:io_oeb[9] 0.0354635
+3 *76:10 0.0305436
+4 *76:8 0.0305068
+5 *76:7 0.0305068
+6 *76:5 0.0354635
*RES
-1 *419:io_oeb[9] *76:9 24.255
-2 *76:9 *76:11 145.98
-3 *76:11 *76:13 4.5
-4 *76:13 io_oeb[9] 704.385
+1 *419:io_oeb[9] *76:5 345.645
+2 *76:5 *76:7 4.5
+3 *76:7 *76:8 304.11
+4 *76:8 *76:10 4.5
+5 *76:10 io_oeb[9] 333.225
*END
-*D_NET *77 0.761989
+*D_NET *77 0.189791
*CONN
*P io_out[0] O
-*I *419:io_out[0] O *D user_proj_example
+*I *419:io_out[0] O *D wrapped_vga_clock
*CAP
1 io_out[0] 0.000332275
-2 *419:io_out[0] 0.000313186
-3 *77:15 0.0157572
-4 *77:14 0.0154249
-5 *77:12 0.0433316
-6 *77:11 0.0433316
-7 *77:9 0.0191987
-8 *77:8 0.0195119
-9 *77:9 *88:9 0.220268
-10 *77:9 *105:9 0
-11 *77:15 *302:16 0
-12 *33:15 *77:9 0
-13 *36:9 *77:9 0.38452
+2 *419:io_out[0] 0.0431193
+3 *77:11 0.0238301
+4 *77:10 0.0234978
+5 *77:8 0.0279462
+6 *77:7 0.0279462
+7 *77:5 0.0431193
*RES
-1 *419:io_out[0] *77:8 16.47
-2 *77:8 *77:9 604.53
-3 *77:9 *77:11 4.5
-4 *77:11 *77:12 430.65
-5 *77:12 *77:14 4.5
-6 *77:14 *77:15 163.17
-7 *77:15 io_out[0] 3.015
+1 *419:io_out[0] *77:5 421.245
+2 *77:5 *77:7 4.5
+3 *77:7 *77:8 278.73
+4 *77:8 *77:10 4.5
+5 *77:10 *77:11 257.67
+6 *77:11 io_out[0] 3.015
*END
-*D_NET *78 0.170837
+*D_NET *78 0.269199
*CONN
*P io_out[10] O
-*I *419:io_out[10] O *D user_proj_example
+*I *419:io_out[10] O *D wrapped_vga_clock
*CAP
1 io_out[10] 0.000332275
-2 *419:io_out[10] 0.00257912
-3 *78:14 0.0640895
-4 *78:13 0.0637573
-5 *78:11 0.0187497
-6 *78:9 0.0213288
-7 *40:10 *78:9 0
+2 *419:io_out[10] 0.000241929
+3 *78:14 0.00490958
+4 *78:13 0.00457731
+5 *78:11 0.0403274
+6 *78:10 0.0403274
+7 *78:8 0.0412168
+8 *78:7 0.0414587
+9 *78:8 *86:14 0
+10 *78:8 *89:8 0.00735578
+11 *78:8 *109:11 0.0481469
+12 *44:8 *78:8 0.00244792
+13 *73:8 *78:8 0.0378574
*RES
-1 *419:io_out[10] *78:9 23.535
-2 *78:9 *78:11 186.48
-3 *78:11 *78:13 4.5
-4 *78:13 *78:14 693.63
-5 *78:14 io_out[10] 3.015
+1 *419:io_out[10] *78:7 6.705
+2 *78:7 *78:8 651.51
+3 *78:8 *78:10 4.5
+4 *78:10 *78:11 402.57
+5 *78:11 *78:13 4.5
+6 *78:13 *78:14 49.77
+7 *78:14 io_out[10] 3.015
*END
-*D_NET *79 0.181952
+*D_NET *79 0.808062
*CONN
*P io_out[11] O
-*I *419:io_out[11] O *D user_proj_example
+*I *419:io_out[11] O *D wrapped_vga_clock
*CAP
-1 io_out[11] 0.000258912
-2 *419:io_out[11] 0.000111588
-3 *79:16 0.054998
-4 *79:15 0.0547391
-5 *79:13 0.00990568
-6 *79:12 0.00990568
-7 *79:10 0.00821087
-8 *79:9 0.00821087
-9 *79:7 0.0177496
-10 *79:5 0.0178612
+1 io_out[11] 0.000637361
+2 *419:io_out[11] 0.00278466
+3 *79:14 0.0324703
+4 *79:13 0.031833
+5 *79:11 0.0145285
+6 *79:10 0.0173131
+7 *79:11 *81:13 0.00105689
+8 *8:16 *79:11 0.447808
+9 *55:13 *79:11 0.00317066
+10 *71:11 *79:11 0.175505
+11 *74:14 *79:14 0.0809546
*RES
-1 *419:io_out[11] *79:5 1.125
-2 *79:5 *79:7 174.33
-3 *79:7 *79:9 4.5
-4 *79:9 *79:10 87.75
-5 *79:10 *79:12 4.5
-6 *79:12 *79:13 98.73
-7 *79:13 *79:15 4.5
-8 *79:15 *79:16 597.87
-9 *79:16 io_out[11] 2.475
+1 *419:io_out[11] *79:10 36.135
+2 *79:10 *79:11 768.33
+3 *79:11 *79:13 4.5
+4 *79:13 *79:14 370.53
+5 *79:14 io_out[11] 11.025
*END
-*D_NET *80 0.193063
+*D_NET *80 0.227987
*CONN
*P io_out[12] O
-*I *419:io_out[12] O *D user_proj_example
+*I *419:io_out[12] O *D wrapped_vga_clock
*CAP
1 io_out[12] 0.000191629
-2 *419:io_out[12] 5.8026e-05
-3 *80:10 0.0623366
-4 *80:9 0.062145
-5 *80:7 0.0341368
-6 *80:5 0.0341948
+2 *419:io_out[12] 0.0428997
+3 *80:11 0.019579
+4 *80:10 0.0193874
+5 *80:8 0.0515147
+6 *80:7 0.0515147
+7 *80:5 0.0428997
*RES
-1 *419:io_out[12] *80:5 0.585
-2 *80:5 *80:7 337.77
-3 *80:7 *80:9 4.5
-4 *80:9 *80:10 677.43
-5 *80:10 io_out[12] 1.935
+1 *419:io_out[12] *80:5 467.145
+2 *80:5 *80:7 4.5
+3 *80:7 *80:8 514.17
+4 *80:8 *80:10 4.5
+5 *80:10 *80:11 211.77
+6 *80:11 io_out[12] 1.935
*END
-*D_NET *81 0.20417
+*D_NET *81 0.312799
*CONN
*P io_out[13] O
-*I *419:io_out[13] O *D user_proj_example
+*I *419:io_out[13] O *D wrapped_vga_clock
*CAP
1 io_out[13] 0.000123625
-2 *419:io_out[13] 0.0406213
-3 *81:8 0.0614638
-4 *81:7 0.0613401
-5 *81:5 0.0406213
-6 *419:io_in[14] *81:5 0
+2 *419:io_out[13] 0.000356235
+3 *81:17 0.0709379
+4 *81:16 0.0708143
+5 *81:14 0.0499169
+6 *81:13 0.0500119
+7 *81:8 0.000705618
+8 *81:7 0.000966833
+9 *81:8 *87:8 0.0320995
+10 *81:8 *114:8 0.0320995
+11 *81:14 *111:12 0
+12 *8:16 *81:13 0.000663143
+13 *71:11 *81:13 0.00304632
+14 *79:11 *81:13 0.00105689
*RES
-1 *419:io_out[13] *81:5 402.525
-2 *81:5 *81:7 4.5
-3 *81:7 *81:8 669.33
-4 *81:8 io_out[13] 1.395
+1 *419:io_out[13] *81:7 7.785
+2 *81:7 *81:8 47.07
+3 *81:8 *81:13 13.41
+4 *81:13 *81:14 498.51
+5 *81:14 *81:16 4.5
+6 *81:16 *81:17 773.37
+7 *81:17 io_out[13] 1.395
*END
-*D_NET *82 0.25987
+*D_NET *82 0.325779
*CONN
*P io_out[14] O
-*I *419:io_out[14] O *D user_proj_example
+*I *419:io_out[14] O *D wrapped_vga_clock
*CAP
-1 io_out[14] 0.000271078
-2 *419:io_out[14] 0.00277105
-3 *82:17 0.0447839
-4 *82:16 0.0445129
-5 *82:14 0.0581028
-6 *82:13 0.0608739
-7 *82:14 *102:10 0
-8 *7:11 *82:13 0
-9 *17:11 *82:14 0.0485546
-10 *44:10 *82:13 0
+1 io_out[14] 0.00395544
+2 *419:io_out[14] 0.000324123
+3 *82:17 0.0589211
+4 *82:16 0.0549657
+5 *82:14 0.066237
+6 *82:13 0.066237
+7 *82:11 0.00516239
+8 *82:10 0.00548651
+9 *82:11 *109:11 0.0299862
+10 *45:14 *82:11 0.034504
*RES
-1 *419:io_out[14] *82:13 30.015
-2 *82:13 *82:14 661.59
-3 *82:14 *82:16 4.5
-4 *82:16 *82:17 444.51
-5 *82:17 io_out[14] 6.885
+1 *419:io_out[14] *82:10 12.735
+2 *82:10 *82:11 130.23
+3 *82:11 *82:13 4.5
+4 *82:13 *82:14 660.51
+5 *82:14 *82:16 4.5
+6 *82:16 *82:17 600.84
+7 *82:17 io_out[14] 43.245
*END
-*D_NET *83 0.439303
+*D_NET *83 0.239471
*CONN
*P io_out[15] O
-*I *419:io_out[15] O *D user_proj_example
+*I *419:io_out[15] O *D wrapped_vga_clock
*CAP
1 io_out[15] 0.000290594
-2 *419:io_out[15] 0.00180908
-3 *83:13 0.0488505
-4 *83:12 0.0485599
-5 *83:10 0.0393784
-6 *83:9 0.0411875
-7 *83:10 *85:10 0.25558
-8 *83:10 *91:10 0.00364729
-9 *83:10 *112:16 0
+2 *419:io_out[15] 0.0571613
+3 *83:8 0.0625743
+4 *83:7 0.0622837
+5 *83:5 0.0571613
*RES
-1 *419:io_out[15] *83:9 20.835
-2 *83:9 *83:10 599.13
-3 *83:10 *83:12 4.5
-4 *83:12 *83:13 484.47
-5 *83:13 io_out[15] 3.015
+1 *419:io_out[15] *83:5 622.485
+2 *83:5 *83:7 4.5
+3 *83:7 *83:8 621.81
+4 *83:8 io_out[15] 3.015
*END
-*D_NET *84 0.190551
+*D_NET *84 0.267977
*CONN
*P io_out[16] O
-*I *419:io_out[16] O *D user_proj_example
+*I *419:io_out[16] O *D wrapped_vga_clock
*CAP
1 io_out[16] 0.000104982
-2 *419:io_out[16] 0.000111588
-3 *84:13 0.043763
-4 *84:12 0.043658
-5 *84:10 0.0447105
-6 *84:9 0.0447105
-7 *84:7 0.0066902
-8 *84:5 0.00680179
+2 *419:io_out[16] 0.0012354
+3 *84:17 0.0686425
+4 *84:16 0.0685375
+5 *84:14 0.0505971
+6 *84:13 0.051946
+7 *84:10 0.00258423
+8 *84:10 *86:14 0
+9 *47:11 *84:10 0.00248679
+10 *72:8 *84:10 0.0078541
+11 *75:11 *84:10 0.0139882
*RES
-1 *419:io_out[16] *84:5 1.125
-2 *84:5 *84:7 63.63
-3 *84:7 *84:9 4.5
-4 *84:9 *84:10 486.09
-5 *84:10 *84:12 4.5
-6 *84:12 *84:13 435.87
-7 *84:13 io_out[16] 1.395
+1 *419:io_out[16] *84:10 48.375
+2 *84:10 *84:13 17.19
+3 *84:13 *84:14 495.81
+4 *84:14 *84:16 4.5
+5 *84:16 *84:17 684.27
+6 *84:17 io_out[16] 1.395
*END
-*D_NET *85 0.422189
+*D_NET *85 0.249124
*CONN
*P io_out[17] O
-*I *419:io_out[17] O *D user_proj_example
+*I *419:io_out[17] O *D wrapped_vga_clock
*CAP
-1 io_out[17] 0.000224243
-2 *419:io_out[17] 0.00175551
-3 *85:13 0.0487886
-4 *85:12 0.0485643
-5 *85:10 0.0149242
-6 *85:9 0.0166797
-7 *85:10 *91:10 0.0261734
-8 *85:10 *112:16 0
-9 *44:11 *85:9 0
-10 *49:10 *85:10 0.0094995
-11 *83:10 *85:10 0.25558
+1 io_out[17] 0.000649026
+2 *419:io_out[17] 0.0303307
+3 *85:11 0.00478877
+4 *85:10 0.00413975
+5 *85:8 0.0610124
+6 *85:7 0.0610124
+7 *85:5 0.0303307
+8 *9:8 *85:11 0.056388
+9 *46:8 io_out[17] 3.68254e-05
+10 *46:13 *85:11 0.000435189
*RES
-1 *419:io_out[17] *85:9 20.295
-2 *85:9 *85:10 369.99
-3 *85:10 *85:12 4.5
-4 *85:12 *85:13 484.29
-5 *85:13 io_out[17] 2.475
+1 *419:io_out[17] *85:5 329.445
+2 *85:5 *85:7 4.5
+3 *85:7 *85:8 609.03
+4 *85:8 *85:10 4.5
+5 *85:10 *85:11 81.63
+6 *85:11 io_out[17] 10.845
*END
-*D_NET *86 0.419666
+*D_NET *86 0.215459
*CONN
*P io_out[18] O
-*I *419:io_out[18] O *D user_proj_example
+*I *419:io_out[18] O *D wrapped_vga_clock
*CAP
-1 io_out[18] 0.00434651
-2 *419:io_out[18] 0.000602416
-3 *86:11 0.0496191
-4 *86:10 0.0452725
-5 *86:8 0.00308938
-6 *86:7 0.0036918
-7 *10:16 *86:8 0.177246
-8 *11:16 *86:8 0.125147
-9 *23:19 *86:8 0.0100715
-10 *25:13 *86:8 0.00058025
+1 io_out[18] 0.00434204
+2 *419:io_out[18] 0.00105257
+3 *86:17 0.0697319
+4 *86:16 0.0653899
+5 *86:14 0.0277043
+6 *86:13 0.0287569
+7 *86:13 *90:8 0.000306879
+8 *86:13 *108:7 0
+9 *25:19 *86:13 0.00221731
+10 *44:8 *86:14 0.0104942
+11 *45:13 *86:14 0
+12 *47:11 *86:14 0
+13 *53:8 *86:14 0.00333644
+14 *59:8 *86:13 0.00172827
+15 *63:8 *86:13 0.000397886
+16 *75:11 *86:14 0
+17 *78:8 *86:14 0
+18 *84:10 *86:14 0
*RES
-1 *419:io_out[18] *86:7 9.765
-2 *86:7 *86:8 256.59
-3 *86:8 *86:10 4.5
-4 *86:10 *86:11 451.26
-5 *86:11 io_out[18] 43.245
+1 *419:io_out[18] *86:13 33.885
+2 *86:13 *86:14 337.59
+3 *86:14 *86:16 4.5
+4 *86:16 *86:17 652.14
+5 *86:17 io_out[18] 43.245
*END
-*D_NET *87 0.161306
+*D_NET *87 0.406301
*CONN
*P io_out[19] O
-*I *419:io_out[19] O *D user_proj_example
+*I *419:io_out[19] O *D wrapped_vga_clock
*CAP
-1 io_out[19] 0.00065797
-2 *419:io_out[19] 0.00365166
-3 *87:20 0.00638019
-4 *87:19 0.00572222
-5 *87:17 0.0463433
-6 *87:16 0.0463433
-7 *87:14 0.00531621
-8 *87:13 0.00896788
-9 *87:14 *89:16 0.000559527
-10 *13:15 *87:13 0
-11 *32:11 *87:14 0
-12 *45:16 *87:20 0.037364
+1 io_out[19] 0.000659344
+2 *419:io_out[19] 0.00037216
+3 *87:17 0.0163588
+4 *87:16 0.0156994
+5 *87:14 0.0586533
+6 *87:13 0.0597674
+7 *87:8 0.00426673
+8 *87:7 0.00352487
+9 *87:8 *88:8 0.0117228
+10 *87:8 *109:10 0.0022709
+11 *87:8 *114:8 0.00366209
+12 *87:14 *112:12 0
+13 *87:17 io_out[21] 0.0146098
+14 io_oeb[21] *87:17 0
+15 *7:12 *87:13 0.0143612
+16 *9:8 *87:17 0.115698
+17 *14:10 *87:17 0
+18 *15:19 *87:8 0.0208064
+19 *48:11 *87:17 0.0317688
+20 *81:8 *87:8 0.0320995
*RES
-1 *419:io_out[19] *87:13 38.115
-2 *87:13 *87:14 58.05
-3 *87:14 *87:16 4.5
-4 *87:16 *87:17 461.97
-5 *87:17 *87:19 4.5
-6 *87:19 *87:20 86.49
-7 *87:20 io_out[19] 10.845
+1 *419:io_out[19] *87:7 7.965
+2 *87:7 *87:8 80.37
+3 *87:8 *87:13 29.79
+4 *87:13 *87:14 585.99
+5 *87:14 *87:16 4.5
+6 *87:16 *87:17 275.49
+7 *87:17 io_out[19] 10.845
*END
-*D_NET *88 0.410326
+*D_NET *88 0.205674
*CONN
*P io_out[1] O
-*I *419:io_out[1] O *D user_proj_example
+*I *419:io_out[1] O *D wrapped_vga_clock
*CAP
1 io_out[1] 0.000258912
-2 *419:io_out[1] 0.000283831
-3 *88:15 0.0418329
-4 *88:14 0.0415739
-5 *88:12 0.0371492
-6 *88:11 0.0371492
-7 *88:9 0.0157632
-8 *88:8 0.0160471
-9 *88:9 *105:9 0
-10 *88:12 *189:15 0
-11 *88:12 *253:13 0
-12 *33:15 *88:9 0
-13 *77:9 *88:9 0.220268
+2 *419:io_out[1] 0.000379173
+3 *88:11 0.071202
+4 *88:10 0.0709431
+5 *88:8 0.019431
+6 *88:7 0.0198101
+7 *88:8 *109:10 0.00462364
+8 *88:8 *114:8 0.00730371
+9 *87:8 *88:8 0.0117228
*RES
-1 *419:io_out[1] *88:8 16.29
-2 *88:8 *88:9 318.87
-3 *88:9 *88:11 4.5
-4 *88:11 *88:12 366.03
-5 *88:12 *88:14 4.5
-6 *88:14 *88:15 441.27
-7 *88:15 io_out[1] 2.475
+1 *419:io_out[1] *88:7 7.785
+2 *88:7 *88:8 213.75
+3 *88:8 *88:10 4.5
+4 *88:10 *88:11 777.69
+5 *88:11 io_out[1] 2.475
*END
-*D_NET *89 0.10716
+*D_NET *89 0.193819
*CONN
*P io_out[20] O
-*I *419:io_out[20] O *D user_proj_example
+*I *419:io_out[20] O *D wrapped_vga_clock
*CAP
-1 io_out[20] 0.00303197
-2 *419:io_out[20] 0.00363627
-3 *89:17 0.0494598
-4 *89:16 0.0500641
-5 *14:19 *89:17 0
-6 *32:11 *89:16 0.000407989
-7 *87:14 *89:16 0.000559527
+1 io_out[20] 0.000290594
+2 *419:io_out[20] 0.0001932
+3 *89:17 0.069461
+4 *89:16 0.0691704
+5 *89:14 0.00479522
+6 *89:13 0.00521114
+7 *89:8 0.00311859
+8 *89:7 0.00289587
+9 *89:8 *109:11 0.0145848
+10 *419:io_in[20] *89:14 0.00609185
+11 *22:11 *89:8 0.000335457
+12 *58:8 *89:8 0.00151268
+13 *73:8 *89:8 0.00880242
+14 *78:8 *89:8 0.00735578
*RES
-1 *419:io_out[20] *89:16 45.585
-2 *89:16 *89:17 462.33
-3 *89:17 io_out[20] 40.995
+1 *419:io_out[20] *89:7 6.345
+2 *89:7 *89:8 105.57
+3 *89:8 *89:13 12.87
+4 *89:13 *89:14 78.39
+5 *89:14 *89:16 4.5
+6 *89:16 *89:17 689.67
+7 *89:17 io_out[20] 3.015
*END
-*D_NET *90 0.170734
+*D_NET *90 0.250224
*CONN
*P io_out[21] O
-*I *419:io_out[21] O *D user_proj_example
+*I *419:io_out[21] O *D wrapped_vga_clock
*CAP
-1 io_out[21] 0.000104982
-2 *419:io_out[21] 0.000436614
-3 *90:11 0.0499327
-4 *90:10 0.0498277
-5 *90:8 0.00475218
-6 *90:7 0.0051888
-7 *90:11 *114:17 0
-8 *419:io_in[22] *90:7 0
-9 *40:10 *90:11 0
-10 *74:8 *90:8 0.0604907
+1 io_out[21] 0.00183833
+2 *419:io_out[21] 0.00119657
+3 *90:11 0.0667981
+4 *90:10 0.0649597
+5 *90:8 0.00119657
+6 *90:8 *113:8 0.0231893
+7 *90:11 *107:8 0.00716051
+8 *10:22 *90:8 0.00174075
+9 *55:8 *90:11 0.0483027
+10 *59:8 *90:8 0.0185888
+11 *63:8 *90:8 0.000335716
+12 *86:13 *90:8 0.000306879
+13 *87:17 io_out[21] 0.0146098
*RES
-1 *419:io_out[21] *90:7 8.505
-2 *90:7 *90:8 87.57
-3 *90:8 *90:10 4.5
-4 *90:10 *90:11 495.45
-5 *90:11 io_out[21] 1.395
+1 *419:io_out[21] *90:8 48.375
+2 *90:8 *90:10 4.5
+3 *90:10 *90:11 691.11
+4 *90:11 io_out[21] 36.675
*END
-*D_NET *91 0.266554
+*D_NET *91 0.145543
*CONN
*P io_out[22] O
-*I *419:io_out[22] O *D user_proj_example
+*I *419:io_out[22] O *D wrapped_vga_clock
*CAP
1 io_out[22] 0.000987786
-2 *419:io_out[22] 0.00189419
-3 *91:13 0.0486851
-4 *91:12 0.0476973
-5 *91:10 0.00909946
-6 *91:9 0.0109937
-7 *91:10 *112:10 0.0410941
-8 *49:10 *91:10 0.00248675
-9 *52:10 *91:10 0.0737954
-10 *53:16 io_out[22] 0
-11 *66:10 *91:10 0
-12 *83:10 *91:10 0.00364729
-13 *85:10 *91:10 0.0261734
+2 *419:io_out[22] 0.000554422
+3 *91:14 0.0591939
+4 *91:13 0.0599354
+5 *91:10 0.00228371
+6 *91:13 *92:11 0.0221946
+7 *3:16 *91:10 0
+8 *15:13 *91:10 0.000393572
+9 *53:16 io_out[22] 0
*RES
-1 *419:io_out[22] *91:9 20.475
-2 *91:9 *91:10 198.63
-3 *91:10 *91:12 4.5
-4 *91:12 *91:13 476.37
-5 *91:13 io_out[22] 18.675
+1 *419:io_out[22] *91:10 20.2774
+2 *91:10 *91:13 36.63
+3 *91:13 *91:14 581.85
+4 *91:14 io_out[22] 18.675
*END
-*D_NET *92 0.22799
+*D_NET *92 0.175355
*CONN
*P io_out[23] O
-*I *419:io_out[23] O *D user_proj_example
+*I *419:io_out[23] O *D wrapped_vga_clock
*CAP
-1 io_out[23] 0.00433039
-2 *419:io_out[23] 0.00125537
-3 *92:13 0.0488039
-4 *92:12 0.0444735
-5 *92:10 0.0248387
-6 *92:9 0.0260941
-7 *419:io_in[24] *92:9 0.000420424
-8 *29:19 *92:10 0
-9 *38:15 *92:10 0.0777741
+1 io_out[23] 0.000671366
+2 *419:io_out[23] 0.00070057
+3 *92:17 0.00619088
+4 *92:16 0.00551951
+5 *92:14 0.0583694
+6 *92:13 0.0583694
+7 *92:11 0.00866932
+8 *92:10 0.00936989
+9 *32:19 *92:11 0.000264222
+10 *51:16 *92:11 0.00503575
+11 *91:13 *92:11 0.0221946
*RES
-1 *419:io_out[23] *92:9 17.415
-2 *92:9 *92:10 316.35
-3 *92:10 *92:12 4.5
-4 *92:12 *92:13 444.24
-5 *92:13 io_out[23] 43.245
+1 *419:io_out[23] *92:10 20.0974
+2 *92:10 *92:11 110.97
+3 *92:11 *92:13 4.5
+4 *92:13 *92:14 583.29
+5 *92:14 *92:16 4.5
+6 *92:16 *92:17 60.21
+7 *92:17 io_out[23] 11.025
*END
-*D_NET *93 0.18078
+*D_NET *93 0.237667
*CONN
*P io_out[24] O
-*I *419:io_out[24] O *D user_proj_example
+*I *419:io_out[24] O *D wrapped_vga_clock
*CAP
1 io_out[24] 0.000215438
-2 *419:io_out[24] 0.00210569
-3 *93:16 0.016159
-4 *93:15 0.0159436
-5 *93:13 0.0444893
-6 *93:12 0.0444893
-7 *93:10 0.0134218
-8 *93:9 0.0155275
-9 *93:10 *103:10 0.0144288
-10 *419:io_in[13] *93:10 0.0139871
-11 *30:11 *93:10 0
-12 *66:10 *93:10 1.2434e-05
+2 *419:io_out[24] 0.00066151
+3 *93:17 0.00923593
+4 *93:16 0.00902049
+5 *93:14 0.0549872
+6 *93:13 0.0549872
+7 *93:11 0.00946995
+8 *93:10 0.0101315
+9 *419:io_in[14] *93:10 5.4397e-05
+10 *419:io_in[27] *93:11 0
+11 *419:io_in[30] *93:11 0
+12 *419:io_in[9] *93:11 0.000127448
+13 *6:12 *93:10 0.000868212
+14 *37:19 *93:11 0.00752255
+15 *52:13 *93:11 0
+16 *56:11 *93:11 0.0803856
*RES
-1 *419:io_out[24] *93:9 23.535
-2 *93:9 *93:10 202.23
-3 *93:10 *93:12 4.5
-4 *93:12 *93:13 444.33
-5 *93:13 *93:15 4.5
-6 *93:15 *93:16 173.61
-7 *93:16 io_out[24] 2.115
+1 *419:io_out[24] *93:10 22.9774
+2 *93:10 *93:11 157.41
+3 *93:11 *93:13 4.5
+4 *93:13 *93:14 549.45
+5 *93:14 *93:16 4.5
+6 *93:16 *93:17 98.01
+7 *93:17 io_out[24] 2.115
*END
-*D_NET *94 0.570308
+*D_NET *94 0.151475
*CONN
*P io_out[25] O
-*I *419:io_out[25] O *D user_proj_example
+*I *419:io_out[25] O *D wrapped_vga_clock
*CAP
-1 io_out[25] 0.000611329
-2 *419:io_out[25] 0.000585572
-3 *94:11 0.0266476
-4 *94:10 0.0260363
-5 *94:8 0.00643738
-6 *94:7 0.00702295
-7 *419:io_in[26] *94:7 0
-8 *10:16 *94:8 0.0400991
-9 *25:13 *94:8 0.0322763
-10 *30:8 *94:11 0.00975874
-11 *57:8 *94:8 0.261174
-12 *57:11 *94:11 0.0170829
-13 *58:13 *94:11 0.142576
+1 io_out[25] 0.00163658
+2 *419:io_out[25] 0.0159227
+3 *94:8 0.0598149
+4 *94:7 0.0581783
+5 *94:5 0.0159227
+6 *94:8 *313:13 0
*RES
-1 *419:io_out[25] *94:7 9.405
-2 *94:7 *94:8 378.45
-3 *94:8 *94:10 4.5
-4 *94:10 *94:11 389.97
-5 *94:11 io_out[25] 10.665
+1 *419:io_out[25] *94:5 171.765
+2 *94:5 *94:7 4.5
+3 *94:7 *94:8 580.95
+4 *94:8 io_out[25] 21.465
*END
-*D_NET *95 0.194237
+*D_NET *95 0.171554
*CONN
*P io_out[26] O
-*I *419:io_out[26] O *D user_proj_example
+*I *419:io_out[26] O *D wrapped_vga_clock
*CAP
1 io_out[26] 0.000280649
-2 *419:io_out[26] 0.00297936
-3 *95:16 0.0279168
-4 *95:15 0.0276361
-5 *95:13 0.0299438
-6 *95:12 0.0299438
-7 *95:10 0.00341125
-8 *95:9 0.00639061
-9 *95:10 *101:10 0.00313025
-10 *7:11 *95:13 0
-11 *20:19 *95:10 0.062605
-12 *57:7 *95:9 0
+2 *419:io_out[26] 0.000379581
+3 *95:14 0.0105789
+4 *95:13 0.0102983
+5 *95:11 0.0520932
+6 *95:10 0.0520932
+7 *95:8 0.0054738
+8 *95:7 0.00585338
+9 *95:8 *96:8 0.00746025
+10 *53:8 *95:8 0.0270431
+11 *63:8 *95:8 0
*RES
-1 *419:io_out[26] *95:9 31.815
-2 *95:9 *95:10 90.63
-3 *95:10 *95:12 4.5
-4 *95:12 *95:13 298.17
-5 *95:13 *95:15 4.5
-6 *95:15 *95:16 300.51
-7 *95:16 io_out[26] 2.655
+1 *419:io_out[26] *95:7 7.785
+2 *95:7 *95:8 93.15
+3 *95:8 *95:10 4.5
+4 *95:10 *95:11 519.75
+5 *95:11 *95:13 4.5
+6 *95:13 *95:14 111.51
+7 *95:14 io_out[26] 2.655
*END
-*D_NET *96 0.127212
+*D_NET *96 0.160215
*CONN
*P io_out[27] O
-*I *419:io_out[27] O *D user_proj_example
+*I *419:io_out[27] O *D wrapped_vga_clock
*CAP
1 io_out[27] 0.000145659
-2 *419:io_out[27] 0.00306749
-3 *96:16 0.0369004
-4 *96:15 0.0367547
-5 *96:13 0.0231095
-6 *96:12 0.026177
-7 *96:12 *97:13 0
-8 *96:12 *101:10 0.00105689
+2 *419:io_out[27] 0.000308516
+3 *96:14 0.00996161
+4 *96:13 0.00981595
+5 *96:11 0.0452794
+6 *96:10 0.0452794
+7 *96:8 0.00404306
+8 *96:7 0.00435158
+9 *22:11 *96:8 0.0162253
+10 *53:8 *96:8 0.00186498
+11 *58:8 *96:8 0.00298401
+12 *64:8 *96:8 0.0124956
+13 *95:8 *96:8 0.00746025
*RES
-1 *419:io_out[27] *96:12 38.205
-2 *96:12 *96:13 229.77
-3 *96:13 *96:15 4.5
-4 *96:15 *96:16 397.71
-5 *96:16 io_out[27] 1.575
+1 *419:io_out[27] *96:7 7.245
+2 *96:7 *96:8 85.59
+3 *96:8 *96:10 4.5
+4 *96:10 *96:11 451.71
+5 *96:11 *96:13 4.5
+6 *96:13 *96:14 106.11
+7 *96:14 io_out[27] 1.575
*END
-*D_NET *97 0.118615
+*D_NET *97 0.107268
*CONN
*P io_out[28] O
-*I *419:io_out[28] O *D user_proj_example
+*I *419:io_out[28] O *D wrapped_vga_clock
*CAP
-1 io_out[28] 0.0370721
-2 *419:io_out[28] 0.00149395
-3 *97:15 0.0370721
-4 *97:13 0.0180378
-5 *97:12 0.0195318
-6 *97:12 *109:10 0
-7 *419:io_in[29] *97:12 0.000371323
-8 *21:16 *97:13 0
-9 *29:19 *97:12 0.00503575
-10 *96:12 *97:13 0
+1 io_out[28] 0.0240675
+2 *419:io_out[28] 0.00168424
+3 *97:16 0.0240675
+4 *97:14 0.0278823
+5 *97:13 0.0295665
+6 *37:19 *97:13 0
*RES
-1 *419:io_out[28] *97:12 27.765
-2 *97:12 *97:13 178.47
-3 *97:13 *97:15 4.5
-4 *97:15 io_out[28] 400.365
+1 *419:io_out[28] *97:13 34.2274
+2 *97:13 *97:14 278.37
+3 *97:14 *97:16 4.5
+4 *97:16 io_out[28] 259.965
*END
-*D_NET *98 0.604697
+*D_NET *98 0.100649
*CONN
*P io_out[29] O
-*I *419:io_out[29] O *D user_proj_example
+*I *419:io_out[29] O *D wrapped_vga_clock
*CAP
-1 io_out[29] 0.000717761
-2 *419:io_out[29] 0.000501841
-3 *98:11 0.00655782
-4 *98:10 0.00584006
-5 *98:8 0.00459181
-6 *98:7 0.00509365
-7 io_oeb[30] *98:11 0.0055852
-8 *419:io_in[30] *98:7 0
-9 *10:16 *98:8 0.00348148
-10 *30:8 *98:11 2.45503e-05
-11 *57:8 *98:8 0.264407
-12 *57:11 *98:11 0.0263302
-13 *62:8 *98:8 0.281566
+1 io_out[29] 0.000215438
+2 *419:io_out[29] 0.0015994
+3 *98:17 0.021577
+4 *98:16 0.0213616
+5 *98:14 0.0209582
+6 *98:13 0.0225576
+7 *419:io_in[27] *98:13 6.52783e-05
+8 *419:io_in[30] *98:13 4.66274e-05
+9 *419:io_in[30] *98:14 0
+10 *49:13 *98:13 0.0121229
+11 *49:16 *98:13 6.13758e-05
+12 *52:13 *98:13 8.39292e-05
*RES
-1 *419:io_out[29] *98:7 9.045
-2 *98:7 *98:8 407.97
-3 *98:8 *98:10 4.5
-4 *98:10 *98:11 116.01
-5 *98:11 io_out[29] 11.385
+1 *419:io_out[29] *98:13 42.3274
+2 *98:13 *98:14 209.25
+3 *98:14 *98:16 4.5
+4 *98:16 *98:17 230.31
+5 *98:17 io_out[29] 2.115
*END
-*D_NET *99 0.519917
+*D_NET *99 0.170622
*CONN
*P io_out[2] O
-*I *419:io_out[2] O *D user_proj_example
+*I *419:io_out[2] O *D wrapped_vga_clock
*CAP
-1 io_out[2] 0.000191629
-2 *419:io_out[2] 9.52214e-05
-3 *99:14 0.0400074
-4 *99:13 0.0398158
-5 *99:11 0.0311121
-6 *99:10 0.0311121
-7 *99:8 0.0062397
-8 *99:7 0.00633492
-9 *99:11 *192:15 0
-10 *99:11 *256:13 0
-11 *99:14 *257:12 0
-12 *67:8 *99:8 0.170654
-13 *68:8 *99:8 0.175877
-14 *69:8 *99:8 0.00174075
-15 *72:8 *99:8 0.00733598
-16 *73:10 *99:8 0.00940003
+1 io_out[2] 0.00100159
+2 *419:io_out[2] 4.01718e-05
+3 *99:10 0.0743241
+4 *99:9 0.0733225
+5 *99:7 0.0109467
+6 *99:5 0.0109868
*RES
-1 *419:io_out[2] *99:7 5.265
-2 *99:7 *99:8 330.21
-3 *99:8 *99:10 4.5
-4 *99:10 *99:11 305.73
-5 *99:11 *99:13 4.5
-6 *99:13 *99:14 422.37
-7 *99:14 io_out[2] 1.935
+1 *419:io_out[2] *99:5 0.405
+2 *99:5 *99:7 108.81
+3 *99:7 *99:9 4.5
+4 *99:9 *99:10 720.99
+5 *99:10 io_out[2] 19.215
*END
-*D_NET *100 0.0895814
+*D_NET *100 0.134535
*CONN
*P io_out[30] O
-*I *419:io_out[30] O *D user_proj_example
+*I *419:io_out[30] O *D wrapped_vga_clock
*CAP
-1 io_out[30] 0.00133974
-2 *419:io_out[30] 0.00253788
-3 *100:14 0.0392006
-4 *100:13 0.0409131
-5 *100:9 0.00559011
-6 *47:10 *100:14 0
-7 *62:7 *100:9 0
+1 io_out[30] 0.00188969
+2 *419:io_out[30] 0.00160183
+3 *100:16 0.0153237
+4 *100:15 0.013434
+5 *100:13 0.0204696
+6 *100:12 0.0220714
+7 *100:13 *111:13 0.0597452
+8 *5:16 *100:12 0
*RES
-1 *419:io_out[30] *100:9 23.535
-2 *100:9 *100:13 34.38
-3 *100:13 *100:14 407.88
-4 *100:14 io_out[30] 13.365
+1 *419:io_out[30] *100:12 28.7257
+2 *100:12 *100:13 258.03
+3 *100:13 *100:15 4.5
+4 *100:15 *100:16 134.19
+5 *100:16 io_out[30] 24.165
*END
-*D_NET *101 0.119448
+*D_NET *101 0.220741
*CONN
*P io_out[31] O
-*I *419:io_out[31] O *D user_proj_example
+*I *419:io_out[31] O *D wrapped_vga_clock
*CAP
-1 io_out[31] 0.000280649
-2 *419:io_out[31] 0.00302165
-3 *101:16 0.0178453
-4 *101:15 0.0175646
-5 *101:13 0.00268155
-6 *101:12 0.00268155
-7 *101:10 0.0211262
-8 *101:9 0.0241479
-9 *101:13 *102:13 0.0011866
-10 *1:14 *101:13 0.000604551
-11 *2:11 *101:10 0
-12 *20:19 *101:10 0
-13 *45:13 *101:9 0
-14 *49:13 *101:9 0
-15 *58:10 *101:10 0
-16 *66:13 *101:13 0.0241207
-17 *95:10 *101:10 0.00313025
-18 *96:12 *101:10 0.00105689
+1 io_out[31] 0.000611329
+2 *419:io_out[31] 0.000188168
+3 *101:14 0.00849793
+4 *101:13 0.0078866
+5 *101:11 0.0189137
+6 *101:10 0.0189137
+7 *101:8 0.00339369
+8 *101:7 0.00358186
+9 *101:8 *314:11 0.0228931
+10 *8:16 *101:11 0.0732974
+11 *15:19 *101:11 0.00615481
+12 *17:8 *101:8 0.00366209
+13 *21:16 *101:8 0.00521694
+14 *40:12 *101:11 4.89586e-05
+15 *61:11 *101:11 0.000149208
+16 *66:8 *101:8 0.0413059
+17 *69:7 *101:11 0.00573516
+18 *70:11 *101:11 0
+19 *71:11 *101:11 0.000290125
*RES
-1 *419:io_out[31] *101:9 32.895
-2 *101:9 *101:10 239.31
-3 *101:10 *101:12 4.5
-4 *101:12 *101:13 45.99
-5 *101:13 *101:15 4.5
-6 *101:15 *101:16 189.63
-7 *101:16 io_out[31] 2.655
+1 *419:io_out[31] *101:7 6.345
+2 *101:7 *101:8 84.33
+3 *101:8 *101:10 4.5
+4 *101:10 *101:11 279.99
+5 *101:11 *101:13 4.5
+6 *101:13 *101:14 78.75
+7 *101:14 io_out[31] 10.665
*END
-*D_NET *102 0.233849
+*D_NET *102 0.0383944
*CONN
*P io_out[32] O
-*I *419:io_out[32] O *D user_proj_example
+*I *419:io_out[32] O *D wrapped_vga_clock
*CAP
-1 io_out[32] 0.000145659
-2 *419:io_out[32] 0.00240112
-3 *102:16 0.0177233
-4 *102:15 0.0175777
-5 *102:13 0.00157499
-6 *102:12 0.00157499
-7 *102:10 0.024418
-8 *102:9 0.0268192
-9 *102:13 *103:13 0.0702752
-10 *8:16 *102:10 0
-11 *15:16 *102:10 0
-12 *17:11 *102:10 0
-13 *18:21 *102:10 0
-14 *22:13 *102:10 0
-15 *66:13 *102:13 0.0701525
-16 *82:14 *102:10 0
-17 *101:13 *102:13 0.0011866
+1 io_out[32] 0.00342789
+2 *419:io_out[32] 0.0157693
+3 *102:5 0.0191972
*RES
-1 *419:io_out[32] *102:9 26.955
-2 *102:9 *102:10 247.05
-3 *102:10 *102:12 4.5
-4 *102:12 *102:13 108.09
-5 *102:13 *102:15 4.5
-6 *102:15 *102:16 189.99
-7 *102:16 io_out[32] 1.575
+1 *419:io_out[32] *102:5 169.065
+2 *102:5 io_out[32] 43.875
*END
-*D_NET *103 0.354329
+*D_NET *103 0.0363852
*CONN
*P io_out[33] O
-*I *419:io_out[33] O *D user_proj_example
+*I *419:io_out[33] O *D wrapped_vga_clock
*CAP
-1 io_out[33] 0.0175724
-2 *419:io_out[33] 0.00186371
-3 *103:15 0.0175724
-4 *103:13 0.0044099
-5 *103:12 0.0044099
-6 *103:10 0.00751222
-7 *103:9 0.00937593
-8 *39:7 *103:13 0.0151892
-9 *66:10 *103:10 0.176375
-10 *66:13 *103:13 0.0153439
-11 *93:10 *103:10 0.0144288
-12 *102:13 *103:13 0.0702752
+1 io_out[33] 0.00122119
+2 *419:io_out[33] 0.0169714
+3 *103:5 0.0181926
*RES
-1 *419:io_out[33] *103:9 21.915
-2 *103:9 *103:10 255.33
-3 *103:10 *103:12 4.5
-4 *103:12 *103:13 170.55
-5 *103:13 *103:15 4.5
-6 *103:15 io_out[33] 190.125
+1 *419:io_out[33] *103:5 182.025
+2 *103:5 io_out[33] 21.195
*END
-*D_NET *104 0.460372
+*D_NET *104 0.0494266
*CONN
*P io_out[34] O
-*I *419:io_out[34] O *D user_proj_example
+*I *419:io_out[34] O *D wrapped_vga_clock
*CAP
1 io_out[34] 0.000215438
-2 *419:io_out[34] 0.000150744
-3 *104:15 0.015648
-4 *104:14 0.0154326
-5 *104:12 0.02231
-6 *104:11 0.02231
-7 *104:9 0.00480456
-8 *104:8 0.00495531
-9 *104:9 *105:9 0.211191
-10 *104:12 *317:11 0.000306879
-11 *63:23 *104:9 0.00213967
-12 *63:27 *104:9 0.00243705
-13 *71:9 *104:9 0.158471
+2 *419:io_out[34] 0.00329621
+3 *104:10 0.0214171
+4 *104:9 0.0244978
*RES
-1 *419:io_out[34] *104:8 14.67
-2 *104:8 *104:9 305.73
-3 *104:9 *104:11 4.5
-4 *104:11 *104:12 221.85
-5 *104:12 *104:14 4.5
-6 *104:14 *104:15 146.97
-7 *104:15 io_out[34] 2.115
+1 *419:io_out[34] *104:9 36.675
+2 *104:9 *104:10 207.45
+3 *104:10 io_out[34] 2.115
*END
-*D_NET *105 0.477203
+*D_NET *105 0.0608946
*CONN
*P io_out[35] O
-*I *419:io_out[35] O *D user_proj_example
+*I *419:io_out[35] O *D wrapped_vga_clock
*CAP
-1 io_out[35] 0.00129702
-2 *419:io_out[35] 0.000165521
-3 *105:15 0.0137047
-4 *105:14 0.0124076
-5 *105:12 0.0291098
-6 *105:11 0.0291098
-7 *105:9 0.00643877
-8 *105:8 0.00660429
-9 *33:15 *105:9 0.165434
-10 *71:9 *105:9 0.00174075
-11 *77:9 *105:9 0
-12 *88:9 *105:9 0
-13 *104:9 *105:9 0.211191
+1 io_out[35] 0.00238169
+2 *419:io_out[35] 9.37343e-05
+3 *105:15 0.00465455
+4 *105:10 0.0202574
+5 *105:9 0.0179845
+6 *105:7 0.00771451
+7 *105:5 0.00780824
+8 *105:15 *314:5 0
+9 *29:13 *105:10 0
*RES
-1 *419:io_out[35] *105:8 14.85
-2 *105:8 *105:9 316.35
-3 *105:9 *105:11 4.5
-4 *105:11 *105:12 289.17
-5 *105:12 *105:14 4.5
-6 *105:14 *105:15 131.04
-7 *105:15 io_out[35] 13.365
+1 *419:io_out[35] *105:5 0.945
+2 *105:5 *105:7 76.41
+3 *105:7 *105:9 4.5
+4 *105:9 *105:10 195.93
+5 *105:10 *105:15 31.59
+6 *105:15 io_out[35] 25.065
*END
-*D_NET *106 0.225236
+*D_NET *106 0.0754244
*CONN
*P io_out[36] O
-*I *419:io_out[36] O *D user_proj_example
+*I *419:io_out[36] O *D wrapped_vga_clock
*CAP
-1 io_out[36] 0.000611329
-2 *419:io_out[36] 0.000855431
-3 *106:17 0.00743855
-4 *106:16 0.00682722
-5 *106:14 0.0460512
-6 *106:13 0.0460512
-7 *106:11 0.0278132
-8 *106:10 0.0286686
-9 *106:11 *107:7 0
-10 *419:io_in[37] *106:10 0.00503564
-11 *30:8 *106:17 0.055545
-12 *34:8 *106:11 0
-13 *74:8 *106:10 0.00033882
+1 io_out[36] 0.000280649
+2 *419:io_out[36] 0.00751146
+3 *106:11 0.0103258
+4 *106:10 0.0100452
+5 *106:8 0.0198749
+6 *106:7 0.0198749
+7 *106:5 0.00751146
*RES
-1 *419:io_out[36] *106:10 21.915
-2 *106:10 *106:11 258.21
-3 *106:11 *106:13 4.5
-4 *106:13 *106:14 471.33
-5 *106:14 *106:16 4.5
-6 *106:16 *106:17 104.31
-7 *106:17 io_out[36] 10.665
+1 *419:io_out[36] *106:5 79.965
+2 *106:5 *106:7 4.5
+3 *106:7 *106:8 198.27
+4 *106:8 *106:10 4.5
+5 *106:10 *106:11 108.81
+6 *106:11 io_out[36] 2.655
*END
-*D_NET *107 0.179835
+*D_NET *107 0.137536
*CONN
*P io_out[37] O
-*I *419:io_out[37] O *D user_proj_example
+*I *419:io_out[37] O *D wrapped_vga_clock
*CAP
-1 io_out[37] 0.000145659
-2 *419:io_out[37] 4.01718e-05
-3 *107:10 0.0439415
-4 *107:9 0.0437958
-5 *107:7 0.043519
-6 *107:5 0.0435592
-7 *107:7 *248:13 0
-8 *107:10 *115:8 0
-9 *107:10 *131:16 0
-10 *107:10 *141:16 0
-11 *107:10 *242:16 0
-12 *107:10 *247:16 0.00483367
-13 *107:10 *254:16 0
-14 *106:11 *107:7 0
+1 io_out[37] 0.000611329
+2 *419:io_out[37] 0.000439606
+3 *107:16 0.00414716
+4 *107:11 0.0293644
+5 *107:10 0.0258285
+6 *107:8 0.0233257
+7 *107:7 0.0237653
+8 *55:8 *107:8 0.0228931
+9 *90:11 *107:8 0.00716051
*RES
-1 *419:io_out[37] *107:5 0.405
-2 *107:5 *107:7 428.13
-3 *107:7 *107:9 4.5
-4 *107:9 *107:10 475.65
-5 *107:10 io_out[37] 1.575
+1 *419:io_out[37] *107:7 8.865
+2 *107:7 *107:8 259.65
+3 *107:8 *107:10 4.5
+4 *107:10 *107:11 282.51
+5 *107:11 *107:16 44.19
+6 *107:16 io_out[37] 6.165
*END
-*D_NET *108 0.473305
+*D_NET *108 0.143424
*CONN
*P io_out[3] O
-*I *419:io_out[3] O *D user_proj_example
+*I *419:io_out[3] O *D wrapped_vga_clock
*CAP
1 io_out[3] 0.000123625
-2 *419:io_out[3] 0.000703704
-3 *108:14 0.0352042
-4 *108:13 0.0350806
-5 *108:11 0.0251431
-6 *108:10 0.0251431
-7 *108:8 0.00823989
-8 *108:7 0.0089436
-9 *108:11 *256:13 0
-10 *108:14 *226:10 0.00975133
-11 *108:14 *232:10 0
-12 *108:14 *233:10 0
-13 *108:14 *293:16 0
-14 *23:19 *108:8 0.0132545
-15 *27:19 *108:8 0.153248
-16 *28:11 *108:8 0.15847
+2 *419:io_out[3] 0.00552949
+3 *108:10 0.0661827
+4 *108:9 0.0660591
+5 *108:7 0.00552949
+6 *86:13 *108:7 0
*RES
-1 *419:io_out[3] *108:7 10.845
-2 *108:7 *108:8 325.35
-3 *108:8 *108:10 4.5
-4 *108:10 *108:11 246.51
-5 *108:11 *108:13 4.5
-6 *108:13 *108:14 419.67
-7 *108:14 io_out[3] 1.395
+1 *419:io_out[3] *108:7 49.455
+2 *108:7 *108:9 4.5
+3 *108:9 *108:10 723.33
+4 *108:10 io_out[3] 1.395
*END
-*D_NET *109 0.319728
+*D_NET *109 0.235729
*CONN
*P io_out[4] O
-*I *419:io_out[4] O *D user_proj_example
+*I *419:io_out[4] O *D wrapped_vga_clock
*CAP
-1 io_out[4] 0.00396969
-2 *419:io_out[4] 0.00114993
-3 *109:16 0.0430942
-4 *109:15 0.0391245
-5 *109:13 0.0185328
-6 *109:12 0.0185328
-7 *109:10 0.00983816
-8 *109:9 0.0109881
-9 *53:10 *109:10 0.0169971
-10 *61:10 *109:10 0.00686353
-11 *65:8 *109:10 0.150637
-12 *97:12 *109:10 0
+1 io_out[4] 0.00248495
+2 *419:io_out[4] 0.00180316
+3 *109:11 0.0279821
+4 *109:10 0.0273003
+5 *45:14 *109:11 0.0762946
+6 *58:8 *109:11 0.000251762
+7 *78:8 *109:11 0.0481469
+8 *82:11 *109:11 0.0299862
+9 *87:8 *109:10 0.0022709
+10 *88:8 *109:10 0.00462364
+11 *89:8 *109:11 0.0145848
*RES
-1 *419:io_out[4] *109:9 14.895
-2 *109:9 *109:10 267.75
-3 *109:10 *109:12 4.5
-4 *109:12 *109:13 184.41
-5 *109:13 *109:15 4.5
-6 *109:15 *109:16 428.04
-7 *109:16 io_out[4] 43.245
+1 *419:io_out[4] *109:10 36.315
+2 *109:10 *109:11 771.57
+3 *109:11 io_out[4] 33.975
*END
-*D_NET *110 0.256021
+*D_NET *110 0.198925
*CONN
*P io_out[5] O
-*I *419:io_out[5] O *D user_proj_example
+*I *419:io_out[5] O *D wrapped_vga_clock
*CAP
-1 io_out[5] 0.000589585
-2 *419:io_out[5] 0.00472906
-3 *110:17 0.0057673
-4 *110:16 0.00517772
-5 *110:14 0.0668995
-6 *110:13 0.0716285
-7 *110:17 *111:13 0.0593503
-8 *2:8 *110:17 0.0102497
-9 *16:16 *110:14 0
-10 *70:15 *110:17 0.031629
-11 *72:7 *110:13 0
+1 io_out[5] 0.000332275
+2 *419:io_out[5] 0.000611305
+3 *110:17 0.0379026
+4 *110:16 0.0398618
+5 *110:13 0.00408854
+6 *110:10 0.00240841
+7 *32:19 *110:13 0.0230646
+8 *41:5 *110:17 0.0906558
*RES
-1 *419:io_out[5] *110:13 49.815
-2 *110:13 *110:14 725.49
-3 *110:14 *110:16 4.5
-4 *110:16 *110:17 154.17
-5 *110:17 io_out[5] 10.485
+1 *419:io_out[5] *110:10 19.1974
+2 *110:10 *110:13 37.89
+3 *110:13 *110:16 26.55
+4 *110:16 *110:17 668.07
+5 *110:17 io_out[5] 3.015
*END
-*D_NET *111 0.232937
+*D_NET *111 0.205394
*CONN
*P io_out[6] O
-*I *419:io_out[6] O *D user_proj_example
+*I *419:io_out[6] O *D wrapped_vga_clock
*CAP
-1 io_out[6] 0.000573659
-2 *419:io_out[6] 0.00478588
-3 *111:13 0.00387924
-4 *111:12 0.00330558
-5 *111:10 0.0661771
-6 *111:9 0.070963
-7 io_oeb[7] *111:13 0.0238752
-8 *16:16 *111:10 0
-9 *73:9 *111:9 2.68519e-05
-10 *110:17 *111:13 0.0593503
+1 io_out[6] 0.000258912
+2 *419:io_out[6] 0.00161168
+3 *111:19 0.0616348
+4 *111:18 0.0647837
+5 *111:13 0.00957803
+6 *111:12 0.00778195
+7 *81:14 *111:12 0
+8 *100:13 *111:13 0.0597452
*RES
-1 *419:io_out[6] *111:9 46.395
-2 *111:9 *111:10 717.57
-3 *111:10 *111:12 4.5
-4 *111:12 *111:13 87.03
-5 *111:13 io_out[6] 10.305
+1 *419:io_out[6] *111:12 28.9057
+2 *111:12 *111:13 103.95
+3 *111:13 *111:18 42.75
+4 *111:18 *111:19 668.07
+5 *111:19 io_out[6] 2.475
*END
-*D_NET *112 0.261831
+*D_NET *112 0.226107
*CONN
*P io_out[7] O
-*I *419:io_out[7] O *D user_proj_example
+*I *419:io_out[7] O *D wrapped_vga_clock
*CAP
1 io_out[7] 0.000191629
-2 *419:io_out[7] 0.00172636
-3 *112:16 0.0505202
-4 *112:15 0.0504829
-5 *112:10 0.00336084
-6 *112:9 0.00493289
-7 *49:10 *112:16 0.00954693
-8 *52:10 *112:16 0.00218216
-9 *66:10 *112:16 0.0977931
-10 *83:10 *112:16 0
-11 *85:10 *112:16 0
-12 *91:10 *112:10 0.0410941
+2 *419:io_out[7] 0.0018716
+3 *112:19 0.0602243
+4 *112:18 0.0600327
+5 *112:16 0.00959966
+6 *112:15 0.00959966
+7 *112:13 0.0063891
+8 *112:12 0.0082607
+9 *74:11 *112:13 0.0699371
+10 *87:14 *112:12 0
*RES
-1 *419:io_out[7] *112:9 20.295
-2 *112:9 *112:10 59.49
-3 *112:10 *112:15 10.35
-4 *112:15 *112:16 655.83
-5 *112:16 io_out[7] 1.935
+1 *419:io_out[7] *112:12 31.6057
+2 *112:12 *112:13 101.25
+3 *112:13 *112:15 4.5
+4 *112:15 *112:16 95.85
+5 *112:16 *112:18 4.5
+6 *112:18 *112:19 654.57
+7 *112:19 io_out[7] 1.935
*END
-*D_NET *113 0.147273
+*D_NET *113 0.250246
*CONN
*P io_out[8] O
-*I *419:io_out[8] O *D user_proj_example
+*I *419:io_out[8] O *D wrapped_vga_clock
*CAP
1 io_out[8] 0.000123625
-2 *419:io_out[8] 0.0083911
-3 *113:8 0.0652453
-4 *113:7 0.0651217
-5 *113:5 0.0083911
-6 *419:io_in[9] *113:5 0
+2 *419:io_out[8] 0.000648337
+3 *113:14 0.0361315
+4 *113:13 0.0360078
+5 *113:11 0.0281038
+6 *113:10 0.0281038
+7 *113:8 0.0163917
+8 *113:7 0.01704
+9 *63:8 *113:8 0.000308258
+10 *72:8 *113:8 0.0383588
+11 *75:11 *113:8 0.0258393
+12 *90:8 *113:8 0.0231893
*RES
-1 *419:io_out[8] *113:5 81.225
-2 *113:5 *113:7 4.5
-3 *113:7 *113:8 707.13
-4 *113:8 io_out[8] 1.395
+1 *419:io_out[8] *113:7 10.305
+2 *113:7 *113:8 315.09
+3 *113:8 *113:10 4.5
+4 *113:10 *113:11 279.27
+5 *113:11 *113:13 4.5
+6 *113:13 *113:14 392.67
+7 *113:14 io_out[8] 1.395
*END
-*D_NET *114 0.159546
+*D_NET *114 0.243096
*CONN
*P io_out[9] O
-*I *419:io_out[9] O *D user_proj_example
+*I *419:io_out[9] O *D wrapped_vga_clock
*CAP
-1 io_out[9] 0.00396967
-2 *419:io_out[9] 0.004372
-3 *114:20 0.0642542
-4 *114:19 0.0602845
-5 *114:17 0.011147
-6 *114:16 0.011147
-7 *114:14 0.004372
-8 *419:io_in[10] *114:14 0
-9 *76:9 *114:14 0
-10 *90:11 *114:17 0
+1 io_out[9] 0.00399814
+2 *419:io_out[9] 0.000326062
+3 *114:11 0.0714666
+4 *114:10 0.0674685
+5 *114:8 0.0282229
+6 *114:7 0.0285489
+7 *81:8 *114:8 0.0320995
+8 *87:8 *114:8 0.00366209
+9 *88:8 *114:8 0.00730371
*RES
-1 *419:io_out[9] *114:14 46.305
-2 *114:14 *114:16 4.5
-3 *114:16 *114:17 110.79
-4 *114:17 *114:19 4.5
-5 *114:19 *114:20 654.84
-6 *114:20 io_out[9] 43.245
+1 *419:io_out[9] *114:7 7.605
+2 *114:7 *114:8 312.75
+3 *114:8 *114:10 4.5
+4 *114:10 *114:11 734.58
+5 *114:11 io_out[9] 43.245
*END
-*D_NET *115 0.252151
-*CONN
-*P la_data_in[0] I
-*I *419:la_data_in[0] I *D user_proj_example
-*CAP
-1 la_data_in[0] 0.00378843
-2 *419:la_data_in[0] 0.00125105
-3 *115:11 0.0105662
-4 *115:10 0.00931519
-5 *115:8 0.00429878
-6 *115:7 0.00808721
-7 *419:la_data_in[0] *419:wbs_dat_i[31] 0
-8 *419:la_data_in[0] *126:11 0.000156508
-9 *419:la_data_in[0] *179:17 0
-10 *419:la_data_in[0] *372:19 0.000296905
-11 *419:la_data_in[0] *405:12 0.00111883
-12 *115:7 *188:15 0
-13 *115:8 *242:16 0.0185885
-14 *115:11 *419:wbs_dat_i[31] 0.0448657
-15 *115:11 *405:13 0.149818
-16 *107:10 *115:8 0
-*RES
-1 la_data_in[0] *115:7 40.365
-2 *115:7 *115:8 53.91
-3 *115:8 *115:10 4.5
-4 *115:10 *115:11 219.69
-5 *115:11 *419:la_data_in[0] 27.178
-*END
-
-*D_NET *116 0.132651
-*CONN
-*P la_data_in[10] I
-*I *419:la_data_in[10] I *D user_proj_example
-*CAP
-1 la_data_in[10] 0.0223521
-2 *419:la_data_in[10] 0.000960764
-3 *116:11 0.00573394
-4 *116:8 0.0119015
-5 *116:7 0.00712829
-6 *116:5 0.0223521
-7 *419:la_data_in[10] *419:la_data_in[12] 0.000435114
-8 *419:la_data_in[10] *419:la_oenb[3] 0.000419646
-9 *419:la_data_in[10] *419:la_oenb[9] 0
-10 *419:la_data_in[10] *180:7 0.000479882
-11 *419:la_data_in[10] *180:9 4.47532e-05
-12 *419:la_data_in[10] *265:11 0.000103572
-13 *419:la_data_in[10] *372:19 0
-14 *116:8 *182:14 0.0607397
-15 *116:11 *119:11 0
-16 *116:11 *183:5 0
-17 *116:11 *372:13 0
-*RES
-1 la_data_in[10] *116:5 219.645
-2 *116:5 *116:7 4.5
-3 *116:7 *116:8 109.53
-4 *116:8 *116:11 49.41
-5 *116:11 *419:la_data_in[10] 22.995
-*END
-
-*D_NET *117 0.329202
-*CONN
-*P la_data_in[11] I
-*I *419:la_data_in[11] I *D user_proj_example
-*CAP
-1 la_data_in[11] 0.000412634
-2 *419:la_data_in[11] 0.000752417
-3 *117:11 0.0153929
-4 *117:10 0.0146405
-5 *117:8 0.0049766
-6 *117:7 0.00538923
-7 *419:la_data_in[11] *419:la_oenb[10] 0.000655953
-8 *419:la_data_in[11] *181:7 0.000291535
-9 *117:7 la_data_out[11] 0
-10 *117:8 *159:8 0.042213
-11 *117:8 *251:8 0.0735462
-12 *117:11 *180:9 0.161848
-13 *117:11 *265:11 0
-14 *117:11 *370:11 0.00908361
-*RES
-1 la_data_in[11] *117:7 8.325
-2 *117:7 *117:8 125.37
-3 *117:8 *117:10 4.5
-4 *117:10 *117:11 258.93
-5 *117:11 *419:la_data_in[11] 20.1972
-*END
-
-*D_NET *118 0.136363
-*CONN
-*P la_data_in[12] I
-*I *419:la_data_in[12] I *D user_proj_example
-*CAP
-1 la_data_in[12] 0.000271935
-2 *419:la_data_in[12] 0.000723518
-3 *118:19 0.00366156
-4 *118:18 0.00293805
-5 *118:16 0.00847023
-6 *118:15 0.00847023
-7 *118:13 0.0220341
-8 *118:11 0.022306
-9 *419:la_data_in[12] *419:la_oenb[11] 0
-10 *419:la_data_in[12] *419:la_oenb[12] 0
-11 *419:la_data_in[12] *419:la_oenb[3] 0.000634086
-12 *419:la_data_in[12] *119:11 3.68254e-05
-13 *419:la_data_in[12] *182:10 0.00039012
-14 *118:13 *245:15 1.87963e-05
-15 *118:16 *262:12 0.0594963
-16 *118:19 *419:la_data_in[14] 0.000756968
-17 *118:19 *419:la_oenb[13] 0.00343704
-18 *118:19 *184:7 0
-19 *118:19 *247:19 0.00228241
-20 *419:la_data_in[10] *419:la_data_in[12] 0.000435114
-*RES
-1 la_data_in[12] *118:11 2.835
-2 *118:11 *118:13 216.81
-3 *118:13 *118:15 4.5
-4 *118:15 *118:16 123.03
-5 *118:16 *118:18 4.5
-6 *118:18 *118:19 48.15
-7 *118:19 *419:la_data_in[12] 19.935
-*END
-
-*D_NET *119 0.154945
-*CONN
-*P la_data_in[13] I
-*I *419:la_data_in[13] I *D user_proj_example
-*CAP
-1 la_data_in[13] 0.00157513
-2 *419:la_data_in[13] 0.000659385
-3 *119:11 0.0286786
-4 *119:10 0.0280192
-5 *119:8 0.00754969
-6 *119:7 0.00912482
-7 *419:la_data_in[13] *419:la_oenb[12] 0.00123774
-8 *419:la_data_in[13] *419:la_oenb[13] 0
-9 *419:la_data_in[13] *183:5 0
-10 *119:8 *212:12 0.00874512
-11 *119:8 *261:8 0.0693187
-12 *419:la_data_in[12] *119:11 3.68254e-05
-13 *116:11 *119:11 0
-*RES
-1 la_data_in[13] *119:7 19.125
-2 *119:7 *119:8 138.33
-3 *119:8 *119:10 4.5
-4 *119:10 *119:11 250.47
-5 *119:11 *419:la_data_in[13] 8.505
-*END
-
-*D_NET *120 0.451063
-*CONN
-*P la_data_in[14] I
-*I *419:la_data_in[14] I *D user_proj_example
-*CAP
-1 la_data_in[14] 0.00232097
-2 *419:la_data_in[14] 0.000764452
-3 *120:19 0.00407408
-4 *120:18 0.00330963
-5 *120:16 0.00768896
-6 *120:15 0.0100099
-7 *419:la_data_in[14] *419:la_oenb[13] 0.000483334
-8 *419:la_data_in[14] *184:7 0.00032836
-9 *120:15 la_data_out[14] 7.67196e-06
-10 *120:16 *270:16 0.0597446
-11 *120:16 *287:16 0.0392289
-12 *120:19 *183:5 0.157429
-13 *120:19 *372:13 0.164917
-14 *118:19 *419:la_data_in[14] 0.000756968
-*RES
-1 la_data_in[14] *120:15 26.685
-2 *120:15 *120:16 143.01
-3 *120:16 *120:18 4.5
-4 *120:18 *120:19 241.83
-5 *120:19 *419:la_data_in[14] 21.058
-*END
-
-*D_NET *121 0.123456
-*CONN
-*P la_data_in[15] I
-*I *419:la_data_in[15] I *D user_proj_example
-*CAP
-1 la_data_in[15] 0.0270387
-2 *419:la_data_in[15] 0.000406287
-3 *121:8 0.0124994
-4 *121:7 0.0120931
-5 *121:5 0.0270387
-6 *419:la_data_in[15] *419:la_oenb[14] 0.000431548
-7 *419:la_data_in[15] *122:19 0.000282328
-8 *419:la_data_in[15] *185:7 0.000479882
-9 *121:8 *419:la_data_in[19] 0.000352295
-10 *121:8 *419:la_oenb[57] 0.000683535
-11 *121:8 *150:16 0.00609255
-12 *121:8 *166:16 0.0265462
-13 *121:8 *238:14 0.00951187
-*RES
-1 la_data_in[15] *121:5 262.845
-2 *121:5 *121:7 4.5
-3 *121:7 *121:8 149.13
-4 *121:8 *419:la_data_in[15] 12.825
-*END
-
-*D_NET *122 0.320702
-*CONN
-*P la_data_in[16] I
-*I *419:la_data_in[16] I *D user_proj_example
-*CAP
-1 la_data_in[16] 0.00311369
-2 *419:la_data_in[16] 0.000685614
-3 *122:19 0.014599
-4 *122:18 0.0139134
-5 *122:16 0.00769301
-6 *122:15 0.0108067
-7 *419:la_data_in[16] *419:la_oenb[15] 0.000441905
-8 *419:la_data_in[16] *419:la_oenb[16] 0
-9 *419:la_data_in[16] *419:la_oenb[3] 0.000186509
-10 *419:la_data_in[16] *186:7 0
-11 *419:la_data_in[16] *248:24 3.62657e-05
-12 *419:la_data_in[16] *276:19 0.00014321
-13 *122:16 *123:16 0.106372
-14 *122:16 *240:8 0.000621697
-15 *122:16 *243:16 0.0112527
-16 *122:19 *185:9 0.150555
-17 *122:19 *276:19 0
-18 *419:la_data_in[15] *122:19 0.000282328
-*RES
-1 la_data_in[16] *122:15 34.425
-2 *122:15 *122:16 156.69
-3 *122:16 *122:18 4.5
-4 *122:18 *122:19 236.79
-5 *122:19 *419:la_data_in[16] 17.685
-*END
-
-*D_NET *123 0.348762
-*CONN
-*P la_data_in[17] I
-*I *419:la_data_in[17] I *D user_proj_example
-*CAP
-1 la_data_in[17] 0.00322552
-2 *419:la_data_in[17] 0.00103001
-3 *123:19 0.0144403
-4 *123:18 0.0134103
-5 *123:16 0.00431445
-6 *123:15 0.00753997
-7 *419:la_data_in[17] *419:la_oenb[16] 0.000918335
-8 *419:la_data_in[17] *419:la_oenb[17] 0
-9 *419:la_data_in[17] *187:11 0
-10 *419:la_data_in[17] *251:11 0.000199471
-11 *123:15 *250:11 1.87963e-05
-12 *123:16 *240:8 0.0522846
-13 *123:16 *302:16 0.0243083
-14 *123:19 *419:la_oenb[16] 0.000751853
-15 *123:19 *186:7 0.00272099
-16 *123:19 *250:19 0.0068127
-17 *123:19 *276:19 0
-18 *123:19 *373:13 0.110415
-19 *122:16 *123:16 0.106372
-*RES
-1 la_data_in[17] *123:15 35.325
-2 *123:15 *123:16 162.09
-3 *123:16 *123:18 4.5
-4 *123:18 *123:19 231.39
-5 *123:19 *419:la_data_in[17] 23.6172
-*END
-
-*D_NET *124 0.327838
-*CONN
-*P la_data_in[18] I
-*I *419:la_data_in[18] I *D user_proj_example
-*CAP
-1 la_data_in[18] 0.00441495
-2 *419:la_data_in[18] 0.0012105
-3 *124:19 0.00587567
-4 *124:18 0.00466518
-5 *124:16 0.00830204
-6 *124:15 0.012717
-7 *419:la_data_in[18] *419:la_oenb[17] 0.00117074
-8 *419:la_data_in[18] *419:la_oenb[18] 0
-9 *419:la_data_in[18] *187:11 0.000122752
-10 *419:la_data_in[18] *187:13 0.00247038
-11 *419:la_data_in[18] *188:7 0
-12 *419:la_data_in[18] *304:11 0.00597391
-13 *124:16 *244:16 0.0706867
-14 *124:16 *285:16 0.0597446
-15 *124:19 *187:13 0.135272
-16 *124:19 *304:11 0.0152112
-*RES
-1 la_data_in[18] *124:15 47.205
-2 *124:15 *124:16 169.83
-3 *124:16 *124:18 4.5
-4 *124:18 *124:19 198.36
-5 *124:19 *419:la_data_in[18] 33.615
-*END
-
-*D_NET *125 0.220409
-*CONN
-*P la_data_in[19] I
-*I *419:la_data_in[19] I *D user_proj_example
-*CAP
-1 la_data_in[19] 0.00508527
-2 *419:la_data_in[19] 0.000735607
-3 *125:19 0.0134146
-4 *125:18 0.012679
-5 *125:16 0.0130581
-6 *125:15 0.0130581
-7 *125:13 0.00508527
-8 *419:la_data_in[19] *419:la_oenb[18] 0.000614525
-9 *419:la_data_in[19] *419:la_oenb[19] 0
-10 *419:la_data_in[19] *189:7 0
-11 *419:la_data_in[19] *189:9 0
-12 *125:13 *189:15 7.67196e-06
-13 *125:16 *143:8 0.0913213
-14 *125:19 *188:7 0.00300741
-15 *125:19 *188:9 0.0413059
-16 *125:19 *252:26 0.0206836
-17 *125:19 *304:11 0
-18 *121:8 *419:la_data_in[19] 0.000352295
-*RES
-1 la_data_in[19] *125:13 49.185
-2 *125:13 *125:15 4.5
-3 *125:15 *125:16 175.41
-4 *125:16 *125:18 4.5
-5 *125:18 *125:19 216.45
-6 *125:19 *419:la_data_in[19] 19.125
-*END
-
-*D_NET *126 0.246766
-*CONN
-*P la_data_in[1] I
-*I *419:la_data_in[1] I *D user_proj_example
-*CAP
-1 la_data_in[1] 0.00130048
-2 *419:la_data_in[1] 0.000822663
-3 *126:11 0.0149669
-4 *126:10 0.0141443
-5 *126:8 0.00186653
-6 *126:7 0.00316701
-7 *419:la_data_in[1] *419:la_oenb[0] 0.00111883
-8 *419:la_data_in[1] *190:7 0.000383598
-9 *126:7 *258:11 0
-10 *126:8 *170:8 0.0048741
-11 *126:8 *187:16 0.000248679
-12 *126:8 *304:8 0.0092633
-13 *126:8 *405:16 0.0333852
-14 *126:11 wbs_dat_o[26] 0.0060762
-15 *126:11 *419:la_oenb[0] 0.000386667
-16 *126:11 *243:19 0.154605
-17 *126:11 *335:11 0
-18 *419:la_data_in[0] *126:11 0.000156508
-*RES
-1 la_data_in[1] *126:7 16.605
-2 *126:7 *126:8 60.57
-3 *126:8 *126:10 4.5
-4 *126:10 *126:11 247.95
-5 *126:11 *419:la_data_in[1] 22.545
-*END
-
-*D_NET *127 0.189114
-*CONN
-*P la_data_in[20] I
-*I *419:la_data_in[20] I *D user_proj_example
-*CAP
-1 la_data_in[20] 0.0062322
-2 *419:la_data_in[20] 0.00102417
-3 *127:11 0.0142766
-4 *127:10 0.0132524
-5 *127:8 0.0175454
-6 *127:7 0.0175454
-7 *127:5 0.0062322
-8 *419:la_data_in[20] *419:la_oenb[19] 0.000918335
-9 *419:la_data_in[20] *419:la_oenb[20] 0
-10 *419:la_data_in[20] *191:11 0
-11 *419:la_data_in[20] *255:11 0.000199471
-12 *127:11 *189:9 0.111888
-13 *31:13 *127:8 0
-*RES
-1 la_data_in[20] *127:5 54.765
-2 *127:5 *127:7 4.5
-3 *127:7 *127:8 183.69
-4 *127:8 *127:10 4.5
-5 *127:10 *127:11 204.57
-6 *127:11 *419:la_data_in[20] 23.6172
-*END
-
-*D_NET *128 0.306562
-*CONN
-*P la_data_in[21] I
-*I *419:la_data_in[21] I *D user_proj_example
-*CAP
-1 la_data_in[21] 0.00014502
-2 *419:la_data_in[21] 0.00120089
-3 *128:19 0.0100762
-4 *128:18 0.00887528
-5 *128:16 0.0121698
-6 *128:15 0.0121698
-7 *128:13 0.00542032
-8 *128:11 0.00556534
-9 *419:la_data_in[21] *419:la_oenb[20] 0.00127968
-10 *419:la_data_in[21] *419:la_oenb[21] 0
-11 *419:la_data_in[21] *182:11 0.00601483
-12 *419:la_data_in[21] *191:11 0.000122752
-13 *419:la_data_in[21] *191:13 0.00247037
-14 *419:la_data_in[21] *192:7 0
-15 *128:16 *147:16 0.0969223
-16 *128:19 la_data_out[0] 0.0146688
-17 *128:19 *182:11 0.00155357
-18 *128:19 *191:13 0.127907
-*RES
-1 la_data_in[21] *128:11 1.755
-2 *128:11 *128:13 52.29
-3 *128:13 *128:15 4.5
-4 *128:15 *128:16 188.73
-5 *128:16 *128:18 4.5
-6 *128:18 *128:19 187.56
-7 *128:19 *419:la_data_in[21] 33.615
-*END
-
-*D_NET *129 0.237172
-*CONN
-*P la_data_in[22] I
-*I *419:la_data_in[22] I *D user_proj_example
-*CAP
-1 la_data_in[22] 0.00484382
-2 *419:la_data_in[22] 0.00074291
-3 *129:19 0.0182888
-4 *129:18 0.0175459
-5 *129:16 0.0128439
-6 *129:15 0.0128439
-7 *129:13 0.00484382
-8 *419:la_data_in[22] *419:la_oenb[21] 0.000504048
-9 *419:la_data_in[22] *193:10 0
-10 *129:13 *256:11 1.87963e-05
-11 *129:16 *185:12 0.0933163
-12 *129:19 *182:11 0
-13 *129:19 *192:9 0.07138
-*RES
-1 la_data_in[22] *129:13 46.845
-2 *129:13 *129:15 4.5
-3 *129:15 *129:16 194.49
-4 *129:16 *129:18 4.5
-5 *129:18 *129:19 220.77
-6 *129:19 *419:la_data_in[22] 18.2172
-*END
-
-*D_NET *130 0.266044
-*CONN
-*P la_data_in[23] I
-*I *419:la_data_in[23] I *D user_proj_example
-*CAP
-1 la_data_in[23] 0.00412382
-2 *419:la_data_in[23] 0.00322903
-3 *130:19 0.0234575
-4 *130:18 0.0202285
-5 *130:16 0.00750841
-6 *130:15 0.0116322
-7 *419:la_data_in[23] *419:la_oenb[22] 0.00119683
-8 *419:la_data_in[23] *194:15 0
-9 *419:la_data_in[23] *258:11 0.000699683
-10 *130:16 *138:8 0.126763
-11 *130:16 *245:16 0.0672049
-*RES
-1 la_data_in[23] *130:15 44.505
-2 *130:15 *130:16 202.59
-3 *130:16 *130:18 4.5
-4 *130:18 *130:19 201.06
-5 *130:19 *419:la_data_in[23] 33.795
-*END
-
-*D_NET *131 0.430634
-*CONN
-*P la_data_in[24] I
-*I *419:la_data_in[24] I *D user_proj_example
-*CAP
-1 la_data_in[24] 0.00397602
-2 *419:la_data_in[24] 0.000949548
-3 *131:19 0.0129624
-4 *131:18 0.0120129
-5 *131:16 0.00674822
-6 *131:15 0.0107242
-7 *419:la_data_in[24] *419:la_oenb[23] 0.00102932
-8 *419:la_data_in[24] *419:la_oenb[24] 0
-9 *419:la_data_in[24] *195:10 0
-10 *131:15 *195:17 7.67196e-06
-11 *131:15 *258:7 0
-12 *131:16 *136:16 0.134348
-13 *131:16 *247:16 0.0782711
-14 *131:16 *254:16 0.00180292
-15 *131:19 *194:15 0.013073
-16 *131:19 *258:11 0.154728
-17 *107:10 *131:16 0
-*RES
-1 la_data_in[24] *131:15 40.185
-2 *131:15 *131:16 207.81
-3 *131:16 *131:18 4.5
-4 *131:18 *131:19 227.61
-5 *131:19 *419:la_data_in[24] 21.465
-*END
-
-*D_NET *132 0.200309
-*CONN
-*P la_data_in[25] I
-*I *419:la_data_in[25] I *D user_proj_example
-*CAP
-1 la_data_in[25] 0.0266649
-2 *419:la_data_in[25] 0.000813334
-3 *132:8 0.0144016
-4 *132:7 0.0135883
-5 *132:5 0.0266649
-6 *419:la_data_in[25] *419:la_oenb[24] 0
-7 *419:la_data_in[25] *419:la_oenb[25] 3.45239e-06
-8 *419:la_data_in[25] *196:11 0.00395055
-9 *132:8 *419:la_data_in[27] 0.000236245
-10 *132:8 *419:la_data_in[29] 0.000236245
-11 *132:8 *419:la_data_in[39] 0.000154129
-12 *132:8 *419:la_oenb[30] 0.000136773
-13 *132:8 *419:la_oenb[32] 0.000186509
-14 *132:8 *419:la_oenb[34] 0.000186509
-15 *132:8 *419:la_oenb[36] 0.000186509
-16 *132:8 *419:la_oenb[39] 0.000186509
-17 *132:8 *419:la_oenb[40] 0.000186509
-18 *132:8 *419:la_oenb[41] 0.000186509
-19 *132:8 *419:la_oenb[42] 0.000186509
-20 *132:8 *419:la_oenb[43] 0.000186509
-21 *132:8 *146:16 0.111967
-*RES
-1 la_data_in[25] *132:5 260.505
-2 *132:5 *132:7 4.5
-3 *132:7 *132:8 213.39
-4 *132:8 *419:la_data_in[25] 15.975
-*END
-
-*D_NET *133 0.213701
-*CONN
-*P la_data_in[26] I
-*I *419:la_data_in[26] I *D user_proj_example
-*CAP
-1 la_data_in[26] 0.00014502
-2 *419:la_data_in[26] 0.000498468
-3 *133:26 0.0041588
-4 *133:24 0.00492309
-5 *133:16 0.00858045
-6 *133:15 0.00731769
-7 *133:13 0.0263754
-8 *133:11 0.0265204
-9 *419:la_data_in[26] *419:la_oenb[25] 0
-10 *419:la_data_in[26] *197:17 0.000272738
-11 *133:13 *197:23 0
-12 *133:16 *139:16 0.00310848
-13 *133:16 *259:16 0.0866022
-14 *133:24 *419:la_data_in[56] 0.000306879
-15 *133:24 *419:la_oenb[49] 5.43985e-05
-16 *133:24 *419:la_oenb[54] 0.000310848
-17 *133:24 *419:la_oenb[55] 0.00020538
-18 *133:24 *142:21 0.000908361
-19 *133:24 *142:22 0.00337781
-20 *133:24 *230:7 0.000171852
-21 *133:26 *419:la_oenb[22] 0.000746036
-22 *133:26 *419:la_oenb[44] 0.00187752
-23 *133:26 *142:22 0.0302144
-24 *133:26 *193:12 0
-25 *133:26 *248:24 0.00690085
-26 *133:26 *269:24 0.000124339
-*RES
-1 la_data_in[26] *133:11 1.755
-2 *133:11 *133:13 258.03
-3 *133:13 *133:15 4.5
-4 *133:15 *133:16 138.87
-5 *133:16 *133:24 31.86
-6 *133:24 *133:26 65.34
-7 *133:26 *419:la_data_in[26] 10.305
-*END
-
-*D_NET *134 0.330138
-*CONN
-*P la_data_in[27] I
-*I *419:la_data_in[27] I *D user_proj_example
-*CAP
-1 la_data_in[27] 0.000388835
-2 *419:la_data_in[27] 0.000934354
-3 *134:11 0.016118
-4 *134:10 0.0151836
-5 *134:8 0.0158798
-6 *134:7 0.0162686
-7 *419:la_data_in[27] *419:la_oenb[26] 0.000537038
-8 *419:la_data_in[27] *419:la_oenb[27] 0
-9 *419:la_data_in[27] *198:11 0
-10 *419:la_data_in[27] *246:11 0.00132981
-11 *134:8 *251:8 0.0990357
-12 *134:11 *419:la_oenb[26] 0.000414286
-13 *134:11 *246:11 0
-14 *134:11 *261:11 0.163812
-15 *132:8 *419:la_data_in[27] 0.000236245
-*RES
-1 la_data_in[27] *134:7 7.965
-2 *134:7 *134:8 229.05
-3 *134:8 *134:10 4.5
-4 *134:10 *134:11 256.59
-5 *134:11 *419:la_data_in[27] 22.545
-*END
-
-*D_NET *135 0.232012
-*CONN
-*P la_data_in[28] I
-*I *419:la_data_in[28] I *D user_proj_example
-*CAP
-1 la_data_in[28] 0.000119863
-2 *419:la_data_in[28] 0.00243186
-3 *135:15 0.0168606
-4 *135:14 0.0144287
-5 *135:12 0.0149918
-6 *135:11 0.0151117
-7 *419:la_data_in[28] *419:la_oenb[27] 0.0015881
-8 *419:la_data_in[28] *136:19 0.000693546
-9 *419:la_data_in[28] *199:17 0
-10 *419:la_data_in[28] *262:17 0
-11 *135:12 *188:16 0.100902
-12 *135:15 la_data_out[2] 0.049295
-13 *135:15 *262:17 0.0155894
-*RES
-1 la_data_in[28] *135:11 5.805
-2 *135:11 *135:12 234.81
-3 *135:12 *135:14 4.5
-4 *135:14 *135:15 240.3
-5 *135:15 *419:la_data_in[28] 33.255
-*END
-
-*D_NET *136 0.243939
-*CONN
-*P la_data_in[29] I
-*I *419:la_data_in[29] I *D user_proj_example
-*CAP
-1 la_data_in[29] 0.00364017
-2 *419:la_data_in[29] 0.000956008
-3 *136:19 0.0215747
-4 *136:18 0.0206187
-5 *136:16 0.0146281
-6 *136:15 0.0182682
-7 *419:la_data_in[29] *419:la_oenb[28] 0.00111883
-8 *419:la_data_in[29] *419:la_oenb[29] 0
-9 *419:la_data_in[29] *200:7 0
-10 *136:15 *200:11 7.67196e-06
-11 *136:19 *419:la_oenb[28] 0.000414286
-12 *136:19 *263:21 0.0274349
-13 *419:la_data_in[28] *136:19 0.000693546
-14 *131:16 *136:16 0.134348
-15 *132:8 *419:la_data_in[29] 0.000236245
-*RES
-1 la_data_in[29] *136:15 40.005
-2 *136:15 *136:16 240.39
-3 *136:16 *136:18 4.5
-4 *136:18 *136:19 226.89
-5 *136:19 *419:la_data_in[29] 22.545
-*END
-
-*D_NET *137 0.202109
-*CONN
-*P la_data_in[2] I
-*I *419:la_data_in[2] I *D user_proj_example
-*CAP
-1 la_data_in[2] 0.000247279
-2 *419:la_data_in[2] 0.000711893
-3 *137:19 0.0039038
-4 *137:16 0.00958762
-5 *137:15 0.00639571
-6 *137:13 0.0154104
-7 *137:11 0.0156577
-8 *419:la_data_in[2] *419:la_oenb[1] 0
-9 *419:la_data_in[2] *201:11 0.000528215
-10 *419:la_data_in[2] *372:19 0
-11 *419:la_data_in[2] *401:10 0
-12 *137:13 *254:15 7.67196e-06
-13 *137:13 *260:11 0.146627
-14 *137:19 *419:la_data_in[3] 0.00100247
-15 *137:19 *148:15 0
-16 *137:19 *159:11 0
-17 *137:19 *201:11 0.00203
-*RES
-1 la_data_in[2] *137:11 2.655
-2 *137:11 *137:13 222.21
-3 *137:13 *137:15 4.5
-4 *137:15 *137:16 61.11
-5 *137:16 *137:19 46.71
-6 *137:19 *419:la_data_in[2] 17.775
-*END
-
-*D_NET *138 0.355374
-*CONN
-*P la_data_in[30] I
-*I *419:la_data_in[30] I *D user_proj_example
-*CAP
-1 la_data_in[30] 0.00398698
-2 *419:la_data_in[30] 0.00115028
-3 *138:11 0.00903739
-4 *138:10 0.00788711
-5 *138:8 0.0158099
-6 *138:7 0.0197969
-7 *419:la_data_in[30] *419:la_oenb[29] 0.0130815
-8 *419:la_data_in[30] *202:15 0
-9 *419:la_data_in[30] *248:19 0.00589207
-10 *419:la_data_in[30] *264:11 0.000821668
-11 *138:11 *148:9 0.00742646
-12 *138:11 *248:19 0.00648434
-13 *138:11 *264:11 0.137236
-14 *130:16 *138:8 0.126763
-*RES
-1 la_data_in[30] *138:7 43.065
-2 *138:7 *138:8 248.31
-3 *138:8 *138:10 4.5
-4 *138:10 *138:11 201.24
-5 *138:11 *419:la_data_in[30] 33.795
-*END
-
-*D_NET *139 0.348672
-*CONN
-*P la_data_in[31] I
-*I *419:la_data_in[31] I *D user_proj_example
-*CAP
-1 la_data_in[31] 0.00014502
-2 *419:la_data_in[31] 0.000889888
-3 *139:16 0.0079247
-4 *139:15 0.00703481
-5 *139:13 0.0262675
-6 *139:11 0.0264125
-7 *419:la_data_in[31] *419:la_oenb[30] 0.000447532
-8 *419:la_data_in[31] *419:la_oenb[31] 0
-9 *419:la_data_in[31] *195:13 0.00206632
-10 *419:la_data_in[31] *203:15 0
-11 *419:la_data_in[31] *267:19 8.28572e-05
-12 *139:16 *158:18 0.141063
-13 *139:16 *259:16 0.133229
-14 *133:16 *139:16 0.00310848
-*RES
-1 la_data_in[31] *139:11 1.755
-2 *139:11 *139:13 257.67
-3 *139:13 *139:15 4.5
-4 *139:15 *139:16 252.27
-5 *139:16 *419:la_data_in[31] 18.675
-*END
-
-*D_NET *140 0.361551
-*CONN
-*P la_data_in[32] I
-*I *419:la_data_in[32] I *D user_proj_example
-*CAP
-1 la_data_in[32] 0.000271935
-2 *419:la_data_in[32] 0.00103121
-3 *140:16 0.00836189
-4 *140:15 0.00733068
-5 *140:13 0.0259563
-6 *140:11 0.0262282
-7 *419:la_data_in[32] *419:la_oenb[31] 0.000400477
-8 *419:la_data_in[32] *257:15 0.00255732
-9 *419:la_data_in[32] *268:11 0.000181058
-10 *140:13 *267:11 1.87963e-05
-11 *140:16 *142:16 0.133603
-12 *140:16 *153:16 0.15561
-13 *23:16 *140:13 0
-*RES
-1 la_data_in[32] *140:11 2.835
-2 *140:11 *140:13 254.79
-3 *140:13 *140:15 4.5
-4 *140:15 *140:16 257.67
-5 *140:16 *419:la_data_in[32] 21.555
-*END
-
-*D_NET *141 0.270824
-*CONN
-*P la_data_in[33] I
-*I *419:la_data_in[33] I *D user_proj_example
-*CAP
-1 la_data_in[33] 0.00378052
-2 *419:la_data_in[33] 0.000951084
-3 *141:19 0.0132093
-4 *141:18 0.0122582
-5 *141:16 0.0232995
-6 *141:15 0.0270801
-7 *419:la_data_in[33] *419:la_oenb[32] 0.00254709
-8 *419:la_data_in[33] *204:9 4.47532e-06
-9 *419:la_data_in[33] *205:7 0
-10 *141:15 *205:11 0
-11 *141:16 *242:16 0.0335095
-12 *141:19 *204:9 0.00129784
-13 *141:19 *268:11 0.152887
-14 *107:10 *141:16 0
-*RES
-1 la_data_in[33] *141:15 41.625
-2 *141:15 *141:16 267.21
-3 *141:16 *141:18 4.5
-4 *141:18 *141:19 224.19
-5 *141:19 *419:la_data_in[33] 22.678
-*END
-
-*D_NET *142 0.283289
-*CONN
-*P la_data_in[34] I
-*I *419:la_data_in[34] I *D user_proj_example
-*CAP
-1 la_data_in[34] 0.000203572
-2 *419:la_data_in[34] 0.000447276
-3 *142:22 0.00146477
-4 *142:21 0.00172911
-5 *142:16 0.0118327
-6 *142:15 0.0111211
-7 *142:13 0.0259516
-8 *142:11 0.0261552
-9 *419:la_data_in[34] *419:la_oenb[33] 0.000403929
-10 *419:la_data_in[34] *206:9 0
-11 *142:11 *206:13 7.67196e-06
-12 *142:16 *153:16 0.00435188
-13 *142:21 *419:la_oenb[55] 0.000675133
-14 *142:21 *229:9 0.000365186
-15 *142:21 *230:7 0
-16 *142:22 *419:la_data_in[38] 0.0116258
-17 *142:22 *419:la_data_in[41] 0.000419633
-18 *142:22 *419:la_oenb[49] 0.000663069
-19 *142:22 *144:16 0
-20 *142:22 *207:10 0.000111905
-21 *142:22 *219:13 0.0153559
-22 *142:22 *269:24 0.00230028
-23 *133:24 *142:21 0.000908361
-24 *133:24 *142:22 0.00337781
-25 *133:26 *142:22 0.0302144
-26 *140:16 *142:16 0.133603
-*RES
-1 la_data_in[34] *142:11 2.295
-2 *142:11 *142:13 254.97
-3 *142:13 *142:15 4.5
-4 *142:15 *142:16 212.31
-5 *142:16 *142:21 19.71
-6 *142:21 *142:22 58.41
-7 *142:22 *419:la_data_in[34] 10.125
-*END
-
-*D_NET *143 0.323472
-*CONN
-*P la_data_in[35] I
-*I *419:la_data_in[35] I *D user_proj_example
-*CAP
-1 la_data_in[35] 0.0047788
-2 *419:la_data_in[35] 0.000967206
-3 *143:11 0.0122069
-4 *143:10 0.0112397
-5 *143:8 0.0238757
-6 *143:7 0.0238757
-7 *143:5 0.0047788
-8 *419:la_data_in[35] *419:la_oenb[34] 0.00254709
-9 *419:la_data_in[35] *419:la_oenb[35] 0
-10 *419:la_data_in[35] *206:9 4.47532e-06
-11 *419:la_data_in[35] *207:10 0
-12 *143:11 *206:9 0.00235402
-13 *143:11 *270:19 0.145522
-14 *125:16 *143:8 0.0913213
-*RES
-1 la_data_in[35] *143:5 46.665
-2 *143:5 *143:7 4.5
-3 *143:7 *143:8 280.71
-4 *143:8 *143:10 4.5
-5 *143:10 *143:11 213.39
-6 *143:11 *419:la_data_in[35] 22.678
-*END
-
-*D_NET *144 0.289666
-*CONN
-*P la_data_in[36] I
-*I *419:la_data_in[36] I *D user_proj_example
-*CAP
-1 la_data_in[36] 0.00014502
-2 *419:la_data_in[36] 0.000440451
-3 *144:16 0.00718842
-4 *144:15 0.00674797
-5 *144:13 0.0271678
-6 *144:11 0.0273128
-7 *419:la_data_in[36] *419:la_oenb[35] 0
-8 *419:la_data_in[36] *208:9 0.000150371
-9 *144:16 *419:la_data_in[38] 2.79764e-05
-10 *144:16 *419:la_data_in[41] 0.00269402
-11 *144:16 *419:la_data_in[47] 0.00136773
-12 *144:16 *419:la_oenb[50] 0.00553311
-13 *144:16 *419:la_oenb[53] 0.0055744
-14 *144:16 *193:12 0.00563664
-15 *144:16 *207:10 0.0012421
-16 *144:16 *217:13 0.00167847
-17 *144:16 *217:14 0.179111
-18 *144:16 *219:13 6.21698e-05
-19 *144:16 *238:13 0.00341934
-20 *144:16 *290:14 1.81328e-05
-21 *144:16 *294:16 0.00275412
-22 *144:16 *301:20 0.00340688
-23 *144:16 *310:8 0.00798725
-24 *142:22 *144:16 0
-*RES
-1 la_data_in[36] *144:11 1.755
-2 *144:11 *144:13 266.85
-3 *144:13 *144:15 4.5
-4 *144:15 *144:16 283.77
-5 *144:16 *419:la_data_in[36] 9.315
-*END
-
-*D_NET *145 0.284173
-*CONN
-*P la_data_in[37] I
-*I *419:la_data_in[37] I *D user_proj_example
-*CAP
-1 la_data_in[37] 0.000271935
-2 *419:la_data_in[37] 0.00128217
-3 *145:16 0.0171152
-4 *145:15 0.015833
-5 *145:13 0.0256498
-6 *145:11 0.0259217
-7 *419:la_data_in[37] *419:la_oenb[36] 0.00254709
-8 *419:la_data_in[37] *419:la_oenb[37] 0
-9 *419:la_data_in[37] *208:9 0.000756329
-10 *419:la_data_in[37] *209:11 0
-11 *145:13 *272:15 1.87963e-05
-12 *145:16 *149:8 0.194777
-*RES
-1 la_data_in[37] *145:11 2.835
-2 *145:11 *145:13 252.45
-3 *145:13 *145:15 4.5
-4 *145:15 *145:16 290.07
-5 *145:16 *419:la_data_in[37] 23.895
-*END
-
-*D_NET *146 0.375781
-*CONN
-*P la_data_in[38] I
-*I *419:la_data_in[38] I *D user_proj_example
-*CAP
-1 la_data_in[38] 8.61527e-05
-2 *419:la_data_in[38] 0.00125501
-3 *146:16 0.0104195
-4 *146:15 0.00916452
-5 *146:13 0.026448
-6 *146:11 0.0265342
-7 *419:la_data_in[38] *419:la_data_in[41] 0.000879442
-8 *419:la_data_in[38] *419:la_data_in[44] 0.000187196
-9 *419:la_data_in[38] *419:la_oenb[37] 0
-10 *419:la_data_in[38] *419:la_oenb[44] 0
-11 *419:la_data_in[38] *207:10 0.00167858
-12 *419:la_data_in[38] *210:13 0.000417739
-13 *419:la_data_in[38] *269:24 2.07143e-05
-14 *146:16 *419:la_oenb[45] 0.000310848
-15 *146:16 *219:14 0.174759
-16 *132:8 *146:16 0.111967
-17 *142:22 *419:la_data_in[38] 0.0116258
-18 *144:16 *419:la_data_in[38] 2.79764e-05
-*RES
-1 la_data_in[38] *146:11 1.215
-2 *146:11 *146:13 260.37
-3 *146:13 *146:15 4.5
-4 *146:15 *146:16 280.89
-5 *146:16 *419:la_data_in[38] 41.265
-*END
-
-*D_NET *147 0.318034
-*CONN
-*P la_data_in[39] I
-*I *419:la_data_in[39] I *D user_proj_example
-*CAP
-1 la_data_in[39] 0.000208583
-2 *419:la_data_in[39] 0.00101273
-3 *147:19 0.0122866
-4 *147:18 0.0112739
-5 *147:16 0.022855
-6 *147:15 0.022855
-7 *147:13 0.00492118
-8 *147:11 0.00512976
-9 *419:la_data_in[39] *419:la_oenb[38] 0.000876906
-10 *419:la_data_in[39] *275:11 9.20636e-06
-11 *147:11 *211:13 7.67196e-06
-12 *147:13 *158:13 0.000853122
-13 *147:13 *158:15 0
-14 *147:13 *274:7 0
-15 *147:19 *210:13 0.00603528
-16 *147:19 *269:24 0
-17 *147:19 *274:11 0.132633
-18 *128:16 *147:16 0.0969223
-19 *132:8 *419:la_data_in[39] 0.000154129
-*RES
-1 la_data_in[39] *147:11 2.295
-2 *147:11 *147:13 52.11
-3 *147:13 *147:15 4.5
-4 *147:15 *147:16 305.01
-5 *147:16 *147:18 4.5
-6 *147:18 *147:19 207.81
-7 *147:19 *419:la_data_in[39] 22.545
-*END
-
-*D_NET *148 0.0861221
-*CONN
-*P la_data_in[3] I
-*I *419:la_data_in[3] I *D user_proj_example
-*CAP
-1 la_data_in[3] 0.00362048
-2 *419:la_data_in[3] 0.00100172
-3 *148:15 0.0210724
-4 *148:14 0.0200707
-5 *148:12 0.00750009
-6 *148:11 0.00750009
-7 *148:9 0.00362048
-8 *419:la_data_in[3] *419:la_oenb[2] 0.00123774
-9 *419:la_data_in[3] *159:11 3.06879e-06
-10 *419:la_data_in[3] *201:11 0
-11 *419:la_data_in[3] *212:7 0
-12 *148:9 *264:11 0.00464001
-13 *148:15 *201:11 0.00742647
-14 *137:19 *419:la_data_in[3] 0.00100247
-15 *137:19 *148:15 0
-16 *138:11 *148:9 0.00742646
-*RES
-1 la_data_in[3] *148:9 49.725
-2 *148:9 *148:11 4.5
-3 *148:11 *148:12 73.35
-4 *148:12 *148:14 4.5
-5 *148:14 *148:15 210.69
-6 *148:15 *419:la_data_in[3] 22.545
-*END
-
-*D_NET *149 0.455499
-*CONN
-*P la_data_in[40] I
-*I *419:la_data_in[40] I *D user_proj_example
-*CAP
-1 la_data_in[40] 0.0256001
-2 *419:la_data_in[40] 0.00117811
-3 *149:8 0.00744273
-4 *149:7 0.00626462
-5 *149:5 0.0256001
-6 *419:la_data_in[40] *419:la_oenb[39] 0.00254709
-7 *419:la_data_in[40] *419:la_oenb[40] 0
-8 *419:la_data_in[40] *211:9 0.00077423
-9 *419:la_data_in[40] *213:15 0
-10 *419:la_data_in[40] *277:19 0.000266984
-11 *149:8 *163:16 0.191047
-12 *50:13 *149:5 0
-13 *145:16 *149:8 0.194777
-*RES
-1 la_data_in[40] *149:5 252.225
-2 *149:5 *149:7 4.5
-3 *149:7 *149:8 311.67
-4 *149:8 *419:la_data_in[40] 24.075
-*END
-
-*D_NET *150 0.290799
-*CONN
-*P la_data_in[41] I
-*I *419:la_data_in[41] I *D user_proj_example
-*CAP
-1 la_data_in[41] 0.00014502
-2 *419:la_data_in[41] 0.00115729
-3 *150:16 0.0170919
-4 *150:15 0.0159346
-5 *150:13 0.0267174
-6 *150:11 0.0268624
-7 *419:la_data_in[41] *419:la_data_in[46] 0.000113545
-8 *419:la_data_in[41] *419:la_oenb[40] 0
-9 *419:la_data_in[41] *419:la_oenb[46] 0
-10 *419:la_data_in[41] *214:13 0
-11 *419:la_data_in[41] *217:13 0.00167858
-12 *419:la_data_in[41] *219:13 0.000184127
-13 *150:16 *419:la_data_in[60] 0
-14 *150:16 *419:la_data_in[62] 0.000154129
-15 *150:16 *419:la_oenb[44] 0
-16 *150:16 *419:la_oenb[54] 0
-17 *150:16 *419:la_oenb[55] 0
-18 *150:16 *166:16 0.190674
-19 *150:16 *283:22 0
-20 *419:la_data_in[38] *419:la_data_in[41] 0.000879442
-21 *61:13 *150:13 0
-22 *121:8 *150:16 0.00609255
-23 *142:22 *419:la_data_in[41] 0.000419633
-24 *144:16 *419:la_data_in[41] 0.00269402
-*RES
-1 la_data_in[41] *150:11 1.755
-2 *150:11 *150:13 263.25
-3 *150:13 *150:15 4.5
-4 *150:15 *150:16 302.49
-5 *150:16 *419:la_data_in[41] 35.685
-*END
-
-*D_NET *151 0.369108
-*CONN
-*P la_data_in[42] I
-*I *419:la_data_in[42] I *D user_proj_example
-*CAP
-1 la_data_in[42] 0.000271935
-2 *419:la_data_in[42] 0.0013428
-3 *151:16 0.018228
-4 *151:15 0.0168852
-5 *151:13 0.0253087
-6 *151:11 0.0255806
-7 *419:la_data_in[42] *419:la_oenb[41] 0.00254709
-8 *419:la_data_in[42] *214:13 0.000944292
-9 *419:la_data_in[42] *279:11 0.00035291
-10 *151:13 *278:11 1.87963e-05
-11 *151:16 *152:16 0.220876
-12 *151:16 *249:16 0.056752
-*RES
-1 la_data_in[42] *151:11 2.835
-2 *151:11 *151:13 249.75
-3 *151:13 *151:15 4.5
-4 *151:15 *151:16 322.47
-5 *151:16 *419:la_data_in[42] 26.595
-*END
-
-*D_NET *152 0.50875
-*CONN
-*P la_data_in[43] I
-*I *419:la_data_in[43] I *D user_proj_example
-*CAP
-1 la_data_in[43] 8.61527e-05
-2 *419:la_data_in[43] 0.00136369
-3 *152:16 0.00982429
-4 *152:15 0.0084606
-5 *152:13 0.0252686
-6 *152:11 0.0253547
-7 *419:la_data_in[43] *419:la_oenb[42] 0.00254709
-8 *419:la_data_in[43] *215:13 0.000944292
-9 *419:la_data_in[43] *280:19 0.000359048
-10 *152:16 *156:16 0.213666
-11 *151:16 *152:16 0.220876
-*RES
-1 la_data_in[43] *152:11 1.215
-2 *152:11 *152:13 249.57
-3 *152:13 *152:15 4.5
-4 *152:15 *152:16 330.57
-5 *152:16 *419:la_data_in[43] 26.775
-*END
-
-*D_NET *153 0.260268
-*CONN
-*P la_data_in[44] I
-*I *419:la_data_in[44] I *D user_proj_example
-*CAP
-1 la_data_in[44] 0.000203572
-2 *419:la_data_in[44] 0.00105893
-3 *153:16 0.0225276
-4 *153:15 0.0214686
-5 *153:13 0.02578
-6 *153:11 0.0259836
-7 *419:la_data_in[44] *419:la_oenb[43] 0.00254709
-8 *419:la_data_in[44] *216:13 0.000541513
-9 *419:la_data_in[44] *217:13 0
-10 *153:11 *217:17 7.67196e-06
-11 *419:la_data_in[38] *419:la_data_in[44] 0.000187196
-12 *140:16 *153:16 0.15561
-13 *142:16 *153:16 0.00435188
-*RES
-1 la_data_in[44] *153:11 2.295
-2 *153:11 *153:13 254.61
-3 *153:13 *153:15 4.5
-4 *153:15 *153:16 335.97
-5 *153:16 *419:la_data_in[44] 21.735
-*END
-
-*D_NET *154 0.45144
-*CONN
-*P la_data_in[45] I
-*I *419:la_data_in[45] I *D user_proj_example
-*CAP
-1 la_data_in[45] 0.000699672
-2 *419:la_data_in[45] 0.000216663
-3 *154:14 0.0112337
-4 *154:13 0.011017
-5 *154:11 0.0265972
-6 *154:10 0.0272968
-7 *419:la_data_in[45] *419:la_oenb[44] 0.000224405
-8 *419:la_data_in[45] *218:9 0
-9 *154:10 *295:8 0.00105689
-10 *154:14 *168:16 0.212061
-11 *154:14 *193:12 0.00121229
-12 *154:14 *205:8 0.159824
-13 *154:14 *299:14 0
-*RES
-1 la_data_in[45] *154:10 16.515
-2 *154:10 *154:11 262.35
-3 *154:11 *154:13 4.5
-4 *154:13 *154:14 342.09
-5 *154:14 *419:la_data_in[45] 7.425
-*END
-
-*D_NET *155 0.388258
-*CONN
-*P la_data_in[46] I
-*I *419:la_data_in[46] I *D user_proj_example
-*CAP
-1 la_data_in[46] 0.00014763
-2 *419:la_data_in[46] 0.000943412
-3 *155:19 0.00474454
-4 *155:18 0.00380113
-5 *155:16 0.0305328
-6 *155:15 0.0305328
-7 *155:13 0.00553659
-8 *155:11 0.00568422
-9 *419:la_data_in[46] *419:la_oenb[45] 0.00254709
-10 *419:la_data_in[46] *218:9 4.47532e-06
-11 *419:la_data_in[46] *219:13 0
-12 *155:16 *248:16 0.0428347
-13 *155:19 *218:9 0.00201389
-14 *155:19 *218:11 0.115141
-15 *155:19 *282:11 0.143681
-16 *419:la_data_in[41] *419:la_data_in[46] 0.000113545
-*RES
-1 la_data_in[46] *155:11 1.755
-2 *155:11 *155:13 49.41
-3 *155:13 *155:15 4.5
-4 *155:15 *155:16 350.91
-5 *155:16 *155:18 4.5
-6 *155:18 *155:19 210.69
-7 *155:19 *419:la_data_in[46] 22.678
-*END
-
-*D_NET *156 0.516736
-*CONN
-*P la_data_in[47] I
-*I *419:la_data_in[47] I *D user_proj_example
-*CAP
-1 la_data_in[47] 0.000271935
-2 *419:la_data_in[47] 0.00193191
-3 *156:16 0.0116408
-4 *156:15 0.00970887
-5 *156:13 0.0252089
-6 *156:11 0.0254808
-7 *419:la_data_in[47] *419:la_data_in[51] 0.00192208
-8 *419:la_data_in[47] *419:la_oenb[46] 0.00111499
-9 *419:la_data_in[47] *419:la_oenb[49] 0.00064242
-10 *419:la_data_in[47] *419:la_oenb[50] 2.07232e-05
-11 *419:la_data_in[47] *219:13 0.000994715
-12 *419:la_data_in[47] *220:13 0
-13 *419:la_data_in[47] *224:9 0
-14 *419:la_data_in[47] *289:11 0
-15 *156:13 *283:11 1.87963e-05
-16 *156:16 *169:16 0.222745
-17 *144:16 *419:la_data_in[47] 0.00136773
-18 *152:16 *156:16 0.213666
-*RES
-1 la_data_in[47] *156:11 2.835
-2 *156:11 *156:13 249.39
-3 *156:13 *156:15 4.5
-4 *156:15 *156:16 344.43
-5 *156:16 *419:la_data_in[47] 45.405
-*END
-
-*D_NET *157 0.471186
-*CONN
-*P la_data_in[48] I
-*I *419:la_data_in[48] I *D user_proj_example
-*CAP
-1 la_data_in[48] 8.61527e-05
-2 *419:la_data_in[48] 0.00199631
-3 *157:16 0.0123293
-4 *157:15 0.010333
-5 *157:13 0.0249329
-6 *157:11 0.0250191
-7 *419:la_data_in[48] *419:la_oenb[47] 0.00144233
-8 *419:la_data_in[48] *220:13 4.02619e-05
-9 *419:la_data_in[48] *221:17 0.000240133
-10 *419:la_data_in[48] *285:19 0.000610688
-11 *157:13 *221:21 0
-12 *157:16 *162:16 0.24327
-13 *157:16 *204:10 0.150886
-*RES
-1 la_data_in[48] *157:11 1.215
-2 *157:11 *157:13 246.87
-3 *157:13 *157:15 4.5
-4 *157:15 *157:16 362.97
-5 *157:16 *419:la_data_in[48] 29.475
-*END
-
-*D_NET *158 0.422867
-*CONN
-*P la_data_in[49] I
-*I *419:la_data_in[49] I *D user_proj_example
-*CAP
-1 la_data_in[49] 0.000674064
-2 *419:la_data_in[49] 0.000830822
-3 *158:18 0.00804994
-4 *158:17 0.00721912
-5 *158:15 0.0228851
-6 *158:13 0.0250848
-7 *158:8 0.00731563
-8 *158:7 0.00579003
-9 *419:la_data_in[49] *419:la_oenb[48] 0.000571781
-10 *419:la_data_in[49] *221:17 0.000552382
-11 *419:la_data_in[49] *222:11 0
-12 *419:la_data_in[49] *283:22 0.00497143
-13 *158:7 *222:15 0.000234762
-14 *158:8 la_data_out[48] 0.000708712
-15 *158:8 *275:8 0.00615481
-16 *158:8 *289:8 0.0197283
-17 *158:13 *274:7 2.04586e-05
-18 *158:18 *297:16 0.170159
-19 *139:16 *158:18 0.141063
-20 *147:13 *158:13 0.000853122
-21 *147:13 *158:15 0
-*RES
-1 la_data_in[49] *158:7 11.385
-2 *158:7 *158:8 94.59
-3 *158:8 *158:13 29.97
-4 *158:13 *158:15 225.72
-5 *158:15 *158:17 4.5
-6 *158:17 *158:18 275.67
-7 *158:18 *419:la_data_in[49] 19.575
-*END
-
-*D_NET *159 0.245762
-*CONN
-*P la_data_in[4] I
-*I *419:la_data_in[4] I *D user_proj_example
-*CAP
-1 la_data_in[4] 0.000374224
-2 *419:la_data_in[4] 0.00127671
-3 *159:11 0.0160589
-4 *159:10 0.0147822
-5 *159:8 0.00512859
-6 *159:7 0.00550282
-7 *419:la_data_in[4] *419:la_oenb[3] 0.00131958
-8 *419:la_data_in[4] *170:11 3.06879e-06
-9 *419:la_data_in[4] *212:7 0
-10 *419:la_data_in[4] *223:17 0
-11 *159:7 la_data_out[4] 0.000136561
-12 *159:11 *212:7 0.00460318
-13 *159:11 *212:9 0.153808
-14 *159:11 *368:20 0.000552382
-15 *419:la_data_in[3] *159:11 3.06879e-06
-16 *117:8 *159:8 0.042213
-17 *137:19 *159:11 0
-*RES
-1 la_data_in[4] *159:7 8.505
-2 *159:7 *159:8 80.01
-3 *159:8 *159:10 4.5
-4 *159:10 *159:11 256.05
-5 *159:11 *419:la_data_in[4] 22.545
-*END
-
-*D_NET *160 0.578794
-*CONN
-*P la_data_in[50] I
-*I *419:la_data_in[50] I *D user_proj_example
-*CAP
-1 la_data_in[50] 0.000699672
-2 *419:la_data_in[50] 0.00198998
-3 *160:14 0.00621877
-4 *160:13 0.00422879
-5 *160:11 0.0240238
-6 *160:10 0.0247234
-7 *419:la_data_in[50] *419:la_oenb[49] 0.00119683
-8 *419:la_data_in[50] *222:11 0.00456227
-9 *419:la_data_in[50] *224:9 0.000242434
-10 *419:la_data_in[50] *281:21 0.000184127
-11 *419:la_data_in[50] *283:22 0
-12 *160:10 *295:8 0.00105689
-13 *160:14 *161:16 0.258191
-14 *160:14 *172:14 0.00435188
-15 *160:14 *221:18 0.247124
-*RES
-1 la_data_in[50] *160:10 16.515
-2 *160:10 *160:11 238.23
-3 *160:11 *160:13 4.5
-4 *160:13 *160:14 376.65
-5 *160:14 *419:la_data_in[50] 43.3272
-*END
-
-*D_NET *161 0.589119
-*CONN
-*P la_data_in[51] I
-*I *419:la_data_in[51] I *D user_proj_example
-*CAP
-1 la_data_in[51] 0.00014502
-2 *419:la_data_in[51] 0.00177186
-3 *161:16 0.00686936
-4 *161:15 0.0050975
-5 *161:13 0.024588
-6 *161:11 0.024733
-7 *419:la_data_in[51] *419:la_oenb[50] 0.00103316
-8 *419:la_data_in[51] *224:9 0.010618
-9 *419:la_data_in[51] *289:11 0.000187196
-10 *161:16 *167:16 0.25359
-11 *161:16 *172:14 0.000373018
-12 *419:la_data_in[47] *419:la_data_in[51] 0.00192208
-13 *160:14 *161:16 0.258191
-*RES
-1 la_data_in[51] *161:11 1.755
-2 *161:11 *161:13 243.99
-3 *161:13 *161:15 4.5
-4 *161:15 *161:16 383.31
-5 *161:16 *419:la_data_in[51] 43.288
-*END
-
-*D_NET *162 0.563232
-*CONN
-*P la_data_in[52] I
-*I *419:la_data_in[52] I *D user_proj_example
-*CAP
-1 la_data_in[52] 0.000271935
-2 *419:la_data_in[52] 0.00202838
-3 *162:16 0.00871635
-4 *162:15 0.00668797
-5 *162:13 0.0246523
-6 *162:11 0.0249243
-7 *419:la_data_in[52] *419:la_oenb[51] 0.00144233
-8 *419:la_data_in[52] *225:11 4.02779e-05
-9 *419:la_data_in[52] *226:7 0.000837779
-10 *162:13 *289:7 0.000500596
-11 *162:16 *173:16 0.24986
-12 *162:16 *253:16 0
-13 *157:16 *162:16 0.24327
-*RES
-1 la_data_in[52] *162:11 2.835
-2 *162:11 *162:13 246.69
-3 *162:13 *162:15 4.5
-4 *162:15 *162:16 387.27
-5 *162:16 *419:la_data_in[52] 29.655
-*END
-
-*D_NET *163 0.527703
-*CONN
-*P la_data_in[53] I
-*I *419:la_data_in[53] I *D user_proj_example
-*CAP
-1 la_data_in[53] 8.61527e-05
-2 *419:la_data_in[53] 0.00171198
-3 *163:16 0.0115489
-4 *163:15 0.00983687
-5 *163:13 0.0253918
-6 *163:11 0.0254779
-7 *419:la_data_in[53] *419:la_data_in[54] 0.000395873
-8 *419:la_data_in[53] *419:la_oenb[52] 0.00115591
-9 *419:la_data_in[53] *226:7 0
-10 *419:la_data_in[53] *227:5 0
-11 *163:16 *171:8 0.261051
-12 *149:8 *163:16 0.191047
-*RES
-1 la_data_in[53] *163:11 1.215
-2 *163:11 *163:13 252.09
-3 *163:13 *163:15 4.5
-4 *163:15 *163:16 395.37
-5 *163:16 *419:la_data_in[53] 24.255
-*END
-
-*D_NET *164 0.266836
-*CONN
-*P la_data_in[54] I
-*I *419:la_data_in[54] I *D user_proj_example
-*CAP
-1 la_data_in[54] 0.000203572
-2 *419:la_data_in[54] 0.00210117
-3 *164:16 0.0307942
-4 *164:15 0.0286931
-5 *164:13 0.02426
-6 *164:11 0.0244636
-7 *419:la_data_in[54] *419:la_oenb[53] 0.00107408
-8 *419:la_data_in[54] *227:5 0.00513511
-9 *419:la_data_in[54] *228:15 0
-10 *419:la_data_in[54] *288:25 0.000392805
-11 *419:la_data_in[54] *292:11 4.60318e-05
-12 *164:11 *228:19 7.67196e-06
-13 *164:16 *269:16 0.149269
-14 *419:la_data_in[53] *419:la_data_in[54] 0.000395873
-*RES
-1 la_data_in[54] *164:11 2.295
-2 *164:11 *164:13 241.11
-3 *164:13 *164:15 4.5
-4 *164:15 *164:16 402.39
-5 *164:16 *419:la_data_in[54] 46.3872
-*END
-
-*D_NET *165 0.26853
-*CONN
-*P la_data_in[55] I
-*I *419:la_data_in[55] I *D user_proj_example
-*CAP
-1 la_data_in[55] 0.0058005
-2 *419:la_data_in[55] 0.00090884
-3 *165:11 0.0114522
-4 *165:10 0.0105433
-5 *165:8 0.0387114
-6 *165:7 0.0387114
-7 *165:5 0.0058005
-8 *419:la_data_in[55] *419:la_oenb[54] 0.00144233
-9 *419:la_data_in[55] *219:13 0.000465433
-10 *419:la_data_in[55] *228:15 0
-11 *419:la_data_in[55] *229:9 0.000395873
-12 *165:5 *229:13 0
-13 *165:11 *228:15 0.0163873
-14 *165:11 *292:11 0.137911
-15 *31:13 *165:8 0
-*RES
-1 la_data_in[55] *165:5 57.465
-2 *165:5 *165:7 4.5
-3 *165:7 *165:8 410.31
-4 *165:8 *165:10 4.5
-5 *165:10 *165:11 202.23
-6 *165:11 *419:la_data_in[55] 23.038
-*END
-
-*D_NET *166 0.547779
-*CONN
-*P la_data_in[56] I
-*I *419:la_data_in[56] I *D user_proj_example
-*CAP
-1 la_data_in[56] 0.00014502
-2 *419:la_data_in[56] 0.000295836
-3 *166:16 0.0102094
-4 *166:15 0.0099136
-5 *166:13 0.0264588
-6 *166:11 0.0266038
-7 *419:la_data_in[56] *419:la_oenb[55] 0.000452263
-8 *419:la_data_in[56] *230:7 0.0011109
-9 *166:16 *238:14 0.00209305
-10 *166:16 *301:12 0.252969
-11 *121:8 *166:16 0.0265462
-12 *133:24 *419:la_data_in[56] 0.000306879
-13 *150:16 *166:16 0.190674
-*RES
-1 la_data_in[56] *166:11 1.755
-2 *166:11 *166:13 263.07
-3 *166:13 *166:15 4.5
-4 *166:15 *166:16 413.73
-5 *166:16 *419:la_data_in[56] 12.645
-*END
-
-*D_NET *167 0.37115
-*CONN
-*P la_data_in[57] I
-*I *419:la_data_in[57] I *D user_proj_example
-*CAP
-1 la_data_in[57] 0.000271935
-2 *419:la_data_in[57] 0.00169014
-3 *167:16 0.0257569
-4 *167:15 0.0240668
-5 *167:13 0.0244921
-6 *167:11 0.024764
-7 *419:la_data_in[57] *419:la_oenb[56] 0.00123774
-8 *419:la_data_in[57] *230:7 0.014546
-9 *419:la_data_in[57] *231:15 0
-10 *419:la_data_in[57] *293:19 0.000715027
-11 *167:13 *294:11 1.87963e-05
-12 *161:16 *167:16 0.25359
-*RES
-1 la_data_in[57] *167:11 2.835
-2 *167:11 *167:13 243.81
-3 *167:13 *167:15 4.5
-4 *167:15 *167:16 421.11
-5 *167:16 *419:la_data_in[57] 34.155
-*END
-
-*D_NET *168 0.322639
-*CONN
-*P la_data_in[58] I
-*I *419:la_data_in[58] I *D user_proj_example
-*CAP
-1 la_data_in[58] 8.61527e-05
-2 *419:la_data_in[58] 0.000215942
-3 *168:16 0.0206826
-4 *168:15 0.0204666
-5 *168:13 0.0269516
-6 *168:11 0.0270378
-7 *419:la_data_in[58] *419:la_oenb[57] 0
-8 *419:la_data_in[58] *232:7 0.000423492
-9 *168:16 *193:12 0.00781239
-10 *168:16 *217:14 0.00690085
-11 *168:16 *299:14 0
-12 *33:9 *168:16 0
-13 *154:14 *168:16 0.212061
-*RES
-1 la_data_in[58] *168:11 1.215
-2 *168:11 *168:13 268.11
-3 *168:13 *168:15 4.5
-4 *168:15 *168:16 427.23
-5 *168:16 *419:la_data_in[58] 7.605
-*END
-
-*D_NET *169 0.341336
-*CONN
-*P la_data_in[59] I
-*I *419:la_data_in[59] I *D user_proj_example
-*CAP
-1 la_data_in[59] 0.000203572
-2 *419:la_data_in[59] 0.00186839
-3 *169:16 0.0330558
-4 *169:15 0.0311874
-5 *169:13 0.0250169
-6 *169:11 0.0252205
-7 *419:la_data_in[59] *419:la_oenb[58] 0.00127866
-8 *419:la_data_in[59] *232:7 0
-9 *419:la_data_in[59] *233:7 0.000751853
-10 *169:11 *233:13 7.67196e-06
-11 *169:16 *186:8 0
-12 *156:16 *169:16 0.222745
-*RES
-1 la_data_in[59] *169:11 2.295
-2 *169:11 *169:13 249.21
-3 *169:13 *169:15 4.5
-4 *169:15 *169:16 433.17
-5 *169:16 *419:la_data_in[59] 27.135
-*END
-
-*D_NET *170 0.245124
-*CONN
-*P la_data_in[5] I
-*I *419:la_data_in[5] I *D user_proj_example
-*CAP
-1 la_data_in[5] 0.00125187
-2 *419:la_data_in[5] 0.000971078
-3 *170:11 0.015009
-4 *170:10 0.0140379
-5 *170:8 0.00488913
-6 *170:7 0.006141
-7 *419:la_data_in[5] *419:la_oenb[4] 0.00111883
-8 *419:la_data_in[5] *234:11 0
-9 *419:la_data_in[5] *298:11 8.28572e-05
-10 *170:8 *187:16 0.0353744
-11 *170:11 wbs_dat_o[27] 0.00084136
-12 *170:11 *419:la_oenb[4] 0.000400477
-13 *170:11 *287:19 0.160129
-14 *419:la_data_in[4] *170:11 3.06879e-06
-15 *126:8 *170:8 0.0048741
-*RES
-1 la_data_in[5] *170:7 16.065
-2 *170:7 *170:8 86.49
-3 *170:8 *170:10 4.5
-4 *170:10 *170:11 248.49
-5 *170:11 *419:la_data_in[5] 22.545
-*END
-
-*D_NET *171 0.375561
-*CONN
-*P la_data_in[60] I
-*I *419:la_data_in[60] I *D user_proj_example
-*CAP
-1 la_data_in[60] 0.0252958
-2 *419:la_data_in[60] 0.00109448
-3 *171:8 0.0265568
-4 *171:7 0.0254623
-5 *171:5 0.0252958
-6 *419:la_data_in[60] *419:la_oenb[59] 0.00153363
-7 *419:la_data_in[60] *233:7 0.00889948
-8 *419:la_data_in[60] *235:9 0.000217884
-9 *419:la_data_in[60] *296:16 0.000154129
-10 *171:5 *299:11 0
-11 *150:16 *419:la_data_in[60] 0
-12 *163:16 *171:8 0.261051
-*RES
-1 la_data_in[60] *171:5 251.865
-2 *171:5 *171:7 4.5
-3 *171:7 *171:8 442.71
-4 *171:8 *419:la_data_in[60] 35.055
-*END
-
-*D_NET *172 0.448373
-*CONN
-*P la_data_in[61] I
-*I *419:la_data_in[61] I *D user_proj_example
-*CAP
-1 la_data_in[61] 0.000753499
-2 *419:la_data_in[61] 0.00175155
-3 *172:14 0.0148771
-4 *172:13 0.0131255
-5 *172:11 0.0239735
-6 *172:10 0.0239735
-7 *172:8 0.00601946
-8 *172:7 0.00677296
-9 *419:la_data_in[61] *419:la_oenb[60] 0.000378484
-10 *419:la_data_in[61] *235:9 0.0149143
-11 *419:la_data_in[61] *236:11 0
-12 *419:la_data_in[61] *286:19 0.00073344
-13 *172:7 *236:19 0
-14 *172:8 la_data_out[55] 0.00317055
-15 *172:8 la_data_out[58] 0.00242462
-16 *172:8 user_irq[0] 0.000360562
-17 *172:8 *289:8 0.00976066
-18 *172:8 *292:8 0.00634127
-19 *172:8 *295:8 0.00319545
-20 *172:8 *299:10 0.000770645
-21 *172:11 la_data_out[50] 0
-22 *172:11 *224:13 0
-23 *172:14 *196:12 0.083867
-24 *172:14 *221:18 0.226484
-25 *160:14 *172:14 0.00435188
-26 *161:16 *172:14 0.000373018
-*RES
-1 la_data_in[61] *172:7 11.205
-2 *172:7 *172:8 99.81
-3 *172:8 *172:10 4.5
-4 *172:10 *172:11 237.87
-5 *172:11 *172:13 4.5
-6 *172:13 *172:14 349.47
-7 *172:14 *419:la_data_in[61] 33.435
-*END
-
-*D_NET *173 0.381441
-*CONN
-*P la_data_in[62] I
-*I *419:la_data_in[62] I *D user_proj_example
-*CAP
-1 la_data_in[62] 0.000271935
-2 *419:la_data_in[62] 0.000957605
-3 *173:16 0.0282017
-4 *173:15 0.0272441
-5 *173:13 0.0245473
-6 *173:11 0.0248192
-7 *419:la_data_in[62] *419:la_oenb[61] 0.000698442
-8 *419:la_data_in[62] *236:11 0
-9 *419:la_data_in[62] *236:13 0.0119683
-10 *419:la_data_in[62] *237:7 0.000248572
-11 *419:la_data_in[62] *296:16 0
-12 *419:la_data_in[62] *300:17 0.0119683
-13 *173:13 *300:13 0.000500596
-14 *173:16 *196:12 0
-15 *173:16 *253:16 0
-16 *150:16 *419:la_data_in[62] 0.000154129
-17 *162:16 *173:16 0.24986
-*RES
-1 la_data_in[62] *173:11 2.835
-2 *173:11 *173:13 246.51
-3 *173:13 *173:15 4.5
-4 *173:15 *173:16 453.51
-5 *173:16 *419:la_data_in[62] 40.455
-*END
-
-*D_NET *174 0.325687
-*CONN
-*P la_data_in[63] I
-*I *419:la_data_in[63] I *D user_proj_example
-*CAP
-1 la_data_in[63] 8.61527e-05
-2 *419:la_data_in[63] 0.000819548
-3 *174:16 0.0306359
-4 *174:15 0.0298163
-5 *174:13 0.0260563
-6 *174:11 0.0261425
-7 *419:la_data_in[63] *419:la_oenb[62] 0.00037631
-8 *419:la_data_in[63] *419:la_oenb[63] 0
-9 *419:la_data_in[63] *238:13 0.000348691
-10 *419:la_data_in[63] *291:23 0.000214815
-11 *174:16 *219:14 0.211191
-*RES
-1 la_data_in[63] *174:11 1.215
-2 *174:11 *174:13 260.01
-3 *174:13 *174:15 4.5
-4 *174:15 *174:16 459.63
-5 *174:16 *419:la_data_in[63] 15.705
-*END
-
-*D_NET *175 0.213859
-*CONN
-*P la_data_in[6] I
-*I *419:la_data_in[6] I *D user_proj_example
-*CAP
-1 la_data_in[6] 0.000125413
-2 *419:la_data_in[6] 0.00269857
-3 *175:19 0.0111893
-4 *175:18 0.00849073
-5 *175:16 0.00927325
-6 *175:15 0.00927325
-7 *175:13 0.00547588
-8 *175:11 0.0056013
-9 *419:la_data_in[6] *419:la_oenb[5] 0.00201517
-10 *419:la_data_in[6] *234:9 4.47532e-06
-11 *419:la_data_in[6] *234:11 0
-12 *419:la_data_in[6] *239:11 0
-13 *419:la_data_in[6] *239:13 0
-14 *419:la_data_in[6] *303:11 0.000687408
-15 *175:13 *275:11 0.0549313
-16 *175:19 *234:11 0.104093
-*RES
-1 la_data_in[6] *175:11 1.575
-2 *175:11 *175:13 87.21
-3 *175:13 *175:15 4.5
-4 *175:15 *175:16 91.71
-5 *175:16 *175:18 4.5
-6 *175:18 *175:19 152.64
-7 *175:19 *419:la_data_in[6] 33.435
-*END
-
-*D_NET *176 0.384917
-*CONN
-*P la_data_in[7] I
-*I *419:la_data_in[7] I *D user_proj_example
-*CAP
-1 la_data_in[7] 0.00186401
-2 *419:la_data_in[7] 0.000929509
-3 *176:11 0.00573594
-4 *176:10 0.00480643
-5 *176:8 0.00542807
-6 *176:7 0.00729208
-7 *419:la_data_in[7] *419:la_oenb[6] 0.00129412
-8 *419:la_data_in[7] *239:13 0
-9 *419:la_data_in[7] *240:5 0
-10 *419:la_data_in[7] *401:11 0.000211746
-11 *176:8 *177:8 0.0052429
-12 *176:8 *190:10 0.0326389
-13 *176:8 *268:8 0.0202052
-14 *176:11 *239:13 0.134106
-15 *176:11 *303:11 0.165162
-*RES
-1 la_data_in[7] *176:7 21.825
-2 *176:7 *176:8 99.27
-3 *176:8 *176:10 4.5
-4 *176:10 *176:11 242.19
-5 *176:11 *419:la_data_in[7] 23.218
-*END
-
-*D_NET *177 0.416254
-*CONN
-*P la_data_in[8] I
-*I *419:la_data_in[8] I *D user_proj_example
-*CAP
-1 la_data_in[8] 0.00195844
-2 *419:la_data_in[8] 0.000803717
-3 *177:11 0.00412007
-4 *177:10 0.00331635
-5 *177:8 0.00578674
-6 *177:7 0.00774518
-7 *419:la_data_in[8] *419:la_oenb[7] 0.00119683
-8 *419:la_data_in[8] *240:5 0
-9 *419:la_data_in[8] *305:11 8.28572e-05
-10 *419:la_data_in[8] *372:19 0.00105689
-11 *177:8 *190:10 0.0307738
-12 *177:8 *268:8 0.0265464
-13 *177:11 *240:5 0.160129
-14 *177:11 *401:11 0.167494
-15 *176:8 *177:8 0.0052429
-*RES
-1 la_data_in[8] *177:7 21.465
-2 *177:7 *177:8 105.75
-3 *177:8 *177:10 4.5
-4 *177:10 *177:11 245.61
-5 *177:11 *419:la_data_in[8] 19.845
-*END
-
-*D_NET *178 0.106189
-*CONN
-*P la_data_in[9] I
-*I *419:la_data_in[9] I *D user_proj_example
-*CAP
-1 la_data_in[9] 0.000203572
-2 *419:la_data_in[9] 0.00253293
-3 *178:16 0.0108678
-4 *178:15 0.00833492
-5 *178:13 0.0242469
-6 *178:11 0.0244505
-7 *419:la_data_in[9] *419:la_oenb[8] 0.00144233
-8 *419:la_data_in[9] *241:9 7.60804e-05
-9 *419:la_data_in[9] *241:11 0
-10 *419:la_data_in[9] *242:11 0
-11 *419:la_data_in[9] *242:13 0
-12 *419:la_data_in[9] *306:11 0.000604551
-13 *178:11 la_data_out[9] 7.67196e-06
-14 *178:13 *222:11 0.00497143
-15 *178:13 *283:22 0
-16 *178:13 *305:7 0
-17 *178:16 *194:16 0.000834078
-18 *178:16 *197:20 0.00144234
-19 *178:16 *202:16 0.00460055
-20 *178:16 *269:16 0.0215729
-*RES
-1 la_data_in[9] *178:11 2.295
-2 *178:11 *178:13 241.11
-3 *178:13 *178:15 4.5
-4 *178:15 *178:16 109.17
-5 *178:16 *419:la_data_in[9] 35.235
-*END
-
-*D_NET *179 0.187865
-*CONN
-*P la_data_out[0] O
-*I *419:la_data_out[0] O *D user_proj_example
-*CAP
-1 la_data_out[0] 0.00485609
-2 *419:la_data_out[0] 0.00185789
-3 *179:26 0.00485609
-4 *179:24 0.00566591
-5 *179:23 0.00566591
-6 *179:21 0.00386174
-7 *179:19 0.00389057
-8 *179:17 0.00188673
-9 la_data_out[0] *191:13 0.00491006
-10 la_data_out[0] *255:11 0.00336339
-11 *179:17 *419:la_oenb[0] 0.00231387
-12 *179:17 *243:19 0.00337567
-13 *179:17 *335:11 0.000268519
-14 *179:17 *372:19 0.000384877
-15 *179:21 *243:19 0.1133
-16 *179:21 *335:11 0.0127393
-17 *419:la_data_in[0] *179:17 0
-18 *128:19 la_data_out[0] 0.0146688
-*RES
-1 *419:la_data_out[0] *179:17 49.995
-2 *179:17 *179:19 0.27
-3 *179:19 *179:21 166.14
-4 *179:21 *179:23 4.5
-5 *179:23 *179:24 54.27
-6 *179:24 *179:26 4.5
-7 *179:26 la_data_out[0] 73.665
-*END
-
-*D_NET *180 0.421484
-*CONN
-*P la_data_out[10] O
-*I *419:la_data_out[10] O *D user_proj_example
-*CAP
-1 la_data_out[10] 0.00191518
-2 *419:la_data_out[10] 0.000209676
-3 *180:12 0.00846022
-4 *180:11 0.00654504
-5 *180:9 0.00301878
-6 *180:7 0.00322845
-7 la_data_out[10] *292:11 0.00435768
-8 *180:7 *419:la_oenb[10] 0.00144233
-9 *180:9 *419:la_oenb[10] 0.00341249
-10 *180:9 *244:19 0.135149
-11 *180:9 *265:11 0
-12 *180:9 *370:11 0.0108635
-13 *180:12 *181:10 0.0805093
-14 *419:la_data_in[10] *180:7 0.000479882
-15 *419:la_data_in[10] *180:9 4.47532e-05
-16 *117:11 *180:9 0.161848
-*RES
-1 *419:la_data_out[10] *180:7 6.615
-2 *180:7 *180:9 239.49
-3 *180:9 *180:11 4.5
-4 *180:11 *180:12 119.07
-5 *180:12 la_data_out[10] 29.925
-*END
-
-*D_NET *181 0.29831
-*CONN
-*P la_data_out[11] O
-*I *419:la_data_out[11] O *D user_proj_example
-*CAP
-1 la_data_out[11] 0.00220613
-2 *419:la_data_out[11] 4.01718e-05
-3 *181:10 0.00814167
-4 *181:9 0.00593554
-5 *181:7 0.0145605
-6 *181:5 0.0146007
-7 la_data_out[11] *295:11 0.013073
-8 *181:7 *419:la_oenb[11] 0.00312377
-9 *181:7 *245:19 0.136991
-10 *181:10 *284:8 0.0188371
-11 *419:la_data_in[11] *181:7 0.000291535
-12 *117:7 la_data_out[11] 0
-13 *180:12 *181:10 0.0805093
-*RES
-1 *419:la_data_out[11] *181:5 0.405
-2 *181:5 *181:7 245.97
-3 *181:7 *181:9 4.5
-4 *181:9 *181:10 124.47
-5 *181:10 la_data_out[11] 31.725
-*END
-
-*D_NET *182 0.280076
-*CONN
-*P la_data_out[12] O
-*I *419:la_data_out[12] O *D user_proj_example
-*CAP
-1 la_data_out[12] 0.013198
-2 *419:la_data_out[12] 0.00163308
-3 *182:16 0.013198
-4 *182:14 0.00606044
-5 *182:13 0.00606044
-6 *182:11 0.0029882
-7 *182:10 0.00462128
-8 la_data_out[12] *236:13 0.00190265
-9 la_data_out[12] *300:17 0.138157
-10 *182:10 *419:la_oenb[12] 0.00039012
-11 *182:10 *419:la_oenb[7] 0.0100093
-12 *182:10 *246:16 0.00186509
-13 *182:11 *192:7 0
-14 *182:11 *192:9 0
-15 *182:14 *227:8 0.0017822
-16 *182:14 *230:10 0.00951176
-17 *419:la_data_in[12] *182:10 0.00039012
-18 *419:la_data_in[21] *182:11 0.00601483
-19 *116:8 *182:14 0.0607397
-20 *128:19 *182:11 0.00155357
-21 *129:19 *182:11 0
-*RES
-1 *419:la_data_out[12] *182:10 36.675
-2 *182:10 *182:11 46.71
-3 *182:11 *182:13 4.5
-4 *182:13 *182:14 109.71
-5 *182:14 *182:16 4.5
-6 *182:16 la_data_out[12] 219.465
-*END
-
-*D_NET *183 0.417501
-*CONN
-*P la_data_out[13] O
-*I *419:la_data_out[13] O *D user_proj_example
-*CAP
-1 la_data_out[13] 0.00338483
-2 *419:la_data_out[13] 0.0034092
-3 *183:8 0.0116021
-4 *183:7 0.00821729
-5 *183:5 0.0034092
-6 *183:5 *419:la_oenb[13] 0.00712982
-7 *183:5 *247:19 0.140673
-8 *183:5 *372:13 0.000245503
-9 *183:8 *191:16 0.0820013
-10 *419:la_data_in[13] *183:5 0
-11 *116:11 *183:5 0
-12 *120:19 *183:5 0.157429
-*RES
-1 *419:la_data_out[13] *183:5 240.345
-2 *183:5 *183:7 4.5
-3 *183:7 *183:8 137.43
-4 *183:8 la_data_out[13] 36.945
-*END
-
-*D_NET *184 0.191568
-*CONN
-*P la_data_out[14] O
-*I *419:la_data_out[14] O *D user_proj_example
-*CAP
-1 la_data_out[14] 0.00265038
-2 *419:la_data_out[14] 4.34776e-05
-3 *184:10 0.00856979
-4 *184:9 0.00591941
-5 *184:7 0.0248621
-6 *184:5 0.0249056
-7 la_data_out[14] *248:13 2.5829e-05
-8 *184:7 *419:la_oenb[14] 0
-9 *184:10 *223:24 0.0354987
-10 *184:10 *234:14 0.00184437
-11 *184:10 *272:16 0.0578795
-12 *184:10 *276:18 0.0290331
-13 *419:la_data_in[14] *184:7 0.00032836
-14 *118:19 *184:7 0
-15 *120:15 la_data_out[14] 7.67196e-06
-*RES
-1 *419:la_data_out[14] *184:5 0.405
-2 *184:5 *184:7 248.49
-3 *184:7 *184:9 4.5
-4 *184:9 *184:10 143.19
-5 *184:10 la_data_out[14] 29.925
-*END
-
-*D_NET *185 0.299586
-*CONN
-*P la_data_out[15] O
-*I *419:la_data_out[15] O *D user_proj_example
-*CAP
-1 la_data_out[15] 0.00446336
-2 *419:la_data_out[15] 0.000230323
-3 *185:12 0.0133098
-4 *185:11 0.00884645
-5 *185:9 0.00857424
-6 *185:7 0.00880456
-7 la_data_out[15] *290:11 0.000510953
-8 *185:7 *419:la_oenb[15] 0.00144233
-9 *185:9 *419:la_oenb[15] 0.00203767
-10 *185:9 *276:19 0.00701524
-11 *419:la_data_in[15] *185:7 0.000479882
-12 *122:19 *185:9 0.150555
-13 *129:16 *185:12 0.0933163
-*RES
-1 *419:la_data_out[15] *185:7 6.615
-2 *185:7 *185:9 220.77
-3 *185:9 *185:11 4.5
-4 *185:11 *185:12 151.11
-5 *185:12 la_data_out[15] 49.185
-*END
-
-*D_NET *186 0.163872
-*CONN
-*P la_data_out[16] O
-*I *419:la_data_out[16] O *D user_proj_example
-*CAP
-1 la_data_out[16] 0.000187838
-2 *419:la_data_out[16] 0.000947304
-3 *186:11 0.0255468
-4 *186:10 0.0253589
-5 *186:8 0.0107483
-6 *186:7 0.0116956
-7 *186:7 *419:la_oenb[16] 0.0054113
-8 *186:7 *276:19 0
-9 *186:8 *195:14 0.0812554
-10 *419:la_data_in[16] *186:7 0
-11 *123:19 *186:7 0.00272099
-12 *169:16 *186:8 0
-*RES
-1 *419:la_data_out[16] *186:7 28.305
-2 *186:7 *186:8 156.33
-3 *186:8 *186:10 4.5
-4 *186:10 *186:11 247.41
-5 *186:11 la_data_out[16] 2.115
-*END
-
-*D_NET *187 0.493522
-*CONN
-*P la_data_out[17] O
-*I *419:la_data_out[17] O *D user_proj_example
-*CAP
-1 la_data_out[17] 0.00127197
-2 *419:la_data_out[17] 0.000457518
-3 *187:16 0.00759046
-4 *187:15 0.00631849
-5 *187:13 0.00414378
-6 *187:11 0.0046013
-7 *187:11 *419:la_oenb[17] 0.00332452
-8 *187:11 *251:11 4.91006e-05
-9 *187:13 *251:11 0.172527
-10 *187:13 *304:11 0.00100656
-11 *187:16 *279:8 0.0672048
-12 *187:16 *304:8 0.0515384
-13 *419:la_data_in[17] *187:11 0
-14 *419:la_data_in[18] *187:11 0.000122752
-15 *419:la_data_in[18] *187:13 0.00247038
-16 *124:19 *187:13 0.135272
-17 *126:8 *187:16 0.000248679
-18 *170:8 *187:16 0.0353744
-*RES
-1 *419:la_data_out[17] *187:11 7.335
-2 *187:11 *187:13 252.99
-3 *187:13 *187:15 4.5
-4 *187:15 *187:16 164.61
-5 *187:16 la_data_out[17] 16.245
-*END
-
-*D_NET *188 0.223945
-*CONN
-*P la_data_out[18] O
-*I *419:la_data_out[18] O *D user_proj_example
-*CAP
-1 la_data_out[18] 0.000101471
-2 *419:la_data_out[18] 0.000583433
-3 *188:16 0.00950469
-4 *188:15 0.0128749
-5 *188:9 0.017457
-6 *188:7 0.0145687
-7 *188:7 *419:la_oenb[18] 0.00277214
-8 *188:7 *304:11 0
-9 *188:9 *419:la_oenb[18] 0.000184127
-10 *188:9 *252:26 0.0206836
-11 *188:15 wbs_dat_o[31] 0
-12 *419:la_data_in[18] *188:7 0
-13 *115:7 *188:15 0
-14 *125:19 *188:7 0.00300741
-15 *125:19 *188:9 0.0413059
-16 *135:12 *188:16 0.100902
-*RES
-1 *419:la_data_out[18] *188:7 12.555
-2 *188:7 *188:9 227.16
-3 *188:9 *188:15 37.35
-4 *188:15 *188:16 169.83
-5 *188:16 la_data_out[18] 5.625
-*END
-
-*D_NET *189 0.192162
-*CONN
-*P la_data_out[19] O
-*I *419:la_data_out[19] O *D user_proj_example
-*CAP
-1 la_data_out[19] 0.000236116
-2 *419:la_data_out[19] 0.000418152
-3 *189:15 0.0100172
-4 *189:14 0.00978113
-5 *189:12 0.0186371
-6 *189:11 0.0186371
-7 *189:9 0.00896391
-8 *189:7 0.00938206
-9 la_data_out[19] *253:13 2.5829e-05
-10 *189:7 *419:la_oenb[19] 0.00144233
-11 *189:9 *419:la_oenb[19] 0.00272508
-12 *419:la_data_in[19] *189:7 0
-13 *419:la_data_in[19] *189:9 0
-14 *88:12 *189:15 0
-15 *125:13 *189:15 7.67196e-06
-16 *127:11 *189:9 0.111888
-*RES
-1 *419:la_data_out[19] *189:7 6.615
-2 *189:7 *189:9 169.65
-3 *189:9 *189:11 4.5
-4 *189:11 *189:12 175.41
-5 *189:12 *189:14 4.5
-6 *189:14 *189:15 95.31
-7 *189:15 la_data_out[19] 2.655
-*END
-
-*D_NET *190 0.245661
-*CONN
-*P la_data_out[1] O
-*I *419:la_data_out[1] O *D user_proj_example
-*CAP
-1 la_data_out[1] 0.0018237
-2 *419:la_data_out[1] 4.12737e-05
-3 *190:10 0.00386525
-4 *190:9 0.00204154
-5 *190:7 0.0150046
-6 *190:5 0.0150459
-7 la_data_out[1] *254:15 0
-8 la_data_out[1] *258:11 0
-9 *190:7 *419:la_oenb[0] 0
-10 *190:7 *419:la_oenb[1] 0.00312377
-11 *190:7 *254:19 0.140919
-12 *190:7 *335:11 0
-13 *419:la_data_in[1] *190:7 0.000383598
-14 *176:8 *190:10 0.0326389
-15 *177:8 *190:10 0.0307738
-*RES
-1 *419:la_data_out[1] *190:5 0.405
-2 *190:5 *190:7 254.07
-3 *190:7 *190:9 4.5
-4 *190:9 *190:10 60.93
-5 *190:10 la_data_out[1] 21.645
-*END
-
-*D_NET *191 0.502773
-*CONN
-*P la_data_out[20] O
-*I *419:la_data_out[20] O *D user_proj_example
-*CAP
-1 la_data_out[20] 0.00321373
-2 *419:la_data_out[20] 0.000451681
-3 *191:16 0.00994698
-4 *191:15 0.00673325
-5 *191:13 0.00306122
-6 *191:11 0.0035129
-7 *191:11 *419:la_oenb[20] 0.00332452
-8 *191:11 *255:11 4.91006e-05
-9 *191:13 *255:11 0.159638
-10 *191:16 *273:8 0.0954299
-11 la_data_out[0] *191:13 0.00491006
-12 *419:la_data_in[20] *191:11 0
-13 *419:la_data_in[21] *191:11 0.000122752
-14 *419:la_data_in[21] *191:13 0.00247037
-15 *128:19 *191:13 0.127907
-16 *183:8 *191:16 0.0820013
-*RES
-1 *419:la_data_out[20] *191:11 7.335
-2 *191:11 *191:13 234.09
-3 *191:13 *191:15 4.5
-4 *191:15 *191:16 183.87
-5 *191:16 la_data_out[20] 35.145
-*END
-
-*D_NET *192 0.164488
-*CONN
-*P la_data_out[21] O
-*I *419:la_data_out[21] O *D user_proj_example
-*CAP
-1 la_data_out[21] 0.000187838
-2 *419:la_data_out[21] 0.000415293
-3 *192:15 0.0164344
-4 *192:14 0.0162466
-5 *192:12 0.018061
-6 *192:11 0.018061
-7 *192:9 0.00430561
-8 *192:7 0.0047209
-9 *192:7 *419:la_oenb[21] 0.00144233
-10 *192:9 *419:la_oenb[21] 0.00341249
-11 *192:9 *256:21 0.00982012
-12 *419:la_data_in[21] *192:7 0
-13 *99:11 *192:15 0
-14 *129:19 *192:9 0.07138
-15 *182:11 *192:7 0
-16 *182:11 *192:9 0
-*RES
-1 *419:la_data_out[21] *192:7 6.615
-2 *192:7 *192:9 104.85
-3 *192:9 *192:11 4.5
-4 *192:11 *192:12 188.91
-5 *192:12 *192:14 4.5
-6 *192:14 *192:15 160.11
-7 *192:15 la_data_out[21] 2.115
-*END
-
-*D_NET *193 0.183382
-*CONN
-*P la_data_out[22] O
-*I *419:la_data_out[22] O *D user_proj_example
-*CAP
-1 la_data_out[22] 0.0274305
-2 *419:la_data_out[22] 0.000746113
-3 *193:14 0.0274305
-4 *193:12 0.0078876
-5 *193:10 0.00863371
-6 *193:10 *419:la_oenb[22] 0.000756647
-7 *193:10 *246:16 6.99409e-05
-8 *193:12 *419:la_oenb[22] 0
-9 *193:12 *195:10 0.00237479
-10 *193:12 *200:8 0
-11 *193:12 *205:8 0
-12 *193:12 *207:10 7.46038e-05
-13 *193:12 *217:14 0.0933163
-14 *193:12 *269:24 0
-15 *419:la_data_in[22] *193:10 0
-16 *133:26 *193:12 0
-17 *144:16 *193:12 0.00563664
-18 *154:14 *193:12 0.00121229
-19 *168:16 *193:12 0.00781239
-*RES
-1 *419:la_data_out[22] *193:10 14.625
-2 *193:10 *193:12 191.97
-3 *193:12 *193:14 4.5
-4 *193:14 la_data_out[22] 267.165
-*END
-
-*D_NET *194 0.224709
-*CONN
-*P la_data_out[23] O
-*I *419:la_data_out[23] O *D user_proj_example
-*CAP
-1 la_data_out[23] 0.000125413
-2 *419:la_data_out[23] 0.0018423
-3 *194:19 0.0247714
-4 *194:18 0.024646
-5 *194:16 0.0111309
-6 *194:15 0.0129732
-7 *194:15 *419:la_oenb[23] 0.00133748
-8 *194:16 *197:20 0.133975
-9 *419:la_data_in[23] *194:15 0
-10 *131:19 *194:15 0.013073
-11 *178:16 *194:16 0.000834078
-*RES
-1 *419:la_data_out[23] *194:15 34.605
-2 *194:15 *194:16 202.23
-3 *194:16 *194:18 4.5
-4 *194:18 *194:19 241.83
-5 *194:19 la_data_out[23] 1.575
-*END
-
-*D_NET *195 0.284686
-*CONN
-*P la_data_out[24] O
-*I *419:la_data_out[24] O *D user_proj_example
-*CAP
-1 la_data_out[24] 0.000236116
-2 *419:la_data_out[24] 0.000799389
-3 *195:17 0.0254656
-4 *195:16 0.0252295
-5 *195:14 0.00551467
-6 *195:13 0.00647075
-7 *195:10 0.00175546
-8 la_data_out[24] *259:13 2.5829e-05
-9 *195:10 *419:la_oenb[22] 0.00173162
-10 *195:10 *419:la_oenb[24] 0.00103316
-11 *195:13 *419:la_oenb[30] 0.00153439
-12 *195:13 *202:15 0.00105336
-13 *195:13 *267:19 0
-14 *195:14 *204:10 0.128131
-15 *419:la_data_in[24] *195:10 0
-16 *419:la_data_in[31] *195:13 0.00206632
-17 *131:15 *195:17 7.67196e-06
-18 *186:8 *195:14 0.0812554
-19 *193:12 *195:10 0.00237479
-*RES
-1 *419:la_data_out[24] *195:10 30.735
-2 *195:10 *195:13 24.03
-3 *195:13 *195:14 190.53
-4 *195:14 *195:16 4.5
-5 *195:16 *195:17 247.23
-6 *195:17 la_data_out[24] 2.655
-*END
-
-*D_NET *196 0.286847
-*CONN
-*P la_data_out[25] O
-*I *419:la_data_out[25] O *D user_proj_example
-*CAP
-1 la_data_out[25] 0.00335391
-2 *419:la_data_out[25] 0.0014771
-3 *196:15 0.0250017
-4 *196:14 0.0216478
-5 *196:12 0.00763669
-6 *196:11 0.0091138
-7 *196:11 *419:la_oenb[25] 0.00185966
-8 *196:11 *260:11 0.00963588
-9 *196:12 *221:18 0.00746021
-10 *196:12 *253:16 0.111843
-11 *419:la_data_in[25] *196:11 0.00395055
-12 *172:14 *196:12 0.083867
-13 *173:16 *196:12 0
-*RES
-1 *419:la_data_out[25] *196:11 31.365
-2 *196:11 *196:12 215.91
-3 *196:12 *196:14 4.5
-4 *196:14 *196:15 212.94
-5 *196:15 la_data_out[25] 32.265
-*END
-
-*D_NET *197 0.348127
-*CONN
-*P la_data_out[26] O
-*I *419:la_data_out[26] O *D user_proj_example
-*CAP
-1 la_data_out[26] 0.000995799
-2 *419:la_data_out[26] 0.00172621
-3 *197:23 0.0249528
-4 *197:22 0.023957
-5 *197:20 0.00353975
-6 *197:19 0.00353975
-7 *197:17 0.00172621
-8 la_data_out[26] *295:8 0.00391659
-9 *197:17 *419:la_oenb[26] 0.00231387
-10 *197:17 *246:11 0.000921915
-11 *197:17 *261:11 0.00210723
-12 *197:20 *202:16 0.142555
-13 *197:23 *260:7 0.000184127
-14 *419:la_data_in[26] *197:17 0.000272738
-15 *133:13 *197:23 0
-16 *178:16 *197:20 0.00144234
-17 *194:16 *197:20 0.133975
-*RES
-1 *419:la_data_out[26] *197:17 48.105
-2 *197:17 *197:19 4.5
-3 *197:19 *197:20 216.81
-4 *197:20 *197:22 4.5
-5 *197:22 *197:23 235.71
-6 *197:23 la_data_out[26] 20.655
-*END
-
-*D_NET *198 0.245204
-*CONN
-*P la_data_out[27] O
-*I *419:la_data_out[27] O *D user_proj_example
-*CAP
-1 la_data_out[27] 0.0243205
-2 *419:la_data_out[27] 0.00203097
-3 *198:14 0.0243205
-4 *198:12 0.0125999
-5 *198:11 0.0146309
-6 la_data_out[27] *310:11 0
-7 *198:11 *419:la_oenb[27] 0.00296445
-8 *198:11 *246:11 0
-9 *198:11 *262:17 0.00785609
-10 *198:12 *199:24 0.156481
-11 *419:la_data_in[27] *198:11 0
-*RES
-1 *419:la_data_out[27] *198:11 36.945
-2 *198:11 *198:12 229.41
-3 *198:12 *198:14 4.5
-4 *198:14 la_data_out[27] 239.085
-*END
-
-*D_NET *199 0.363549
-*CONN
-*P la_data_out[28] O
-*I *419:la_data_out[28] O *D user_proj_example
-*CAP
-1 la_data_out[28] 0.000125413
-2 *419:la_data_out[28] 0.00226709
-3 *199:27 0.0244092
-4 *199:26 0.0242838
-5 *199:24 0.00451316
-6 *199:23 0.00459889
-7 *199:17 0.00235283
-8 *199:17 *419:la_oenb[28] 0.00231387
-9 *199:17 *263:21 0.00251641
-10 *199:23 *263:21 0.000613757
-11 *199:24 *207:14 0.139073
-12 *419:la_data_in[28] *199:17 0
-13 *198:12 *199:24 0.156481
-*RES
-1 *419:la_data_out[28] *199:17 49.995
-2 *199:17 *199:23 5.67
-3 *199:23 *199:24 234.63
-4 *199:24 *199:26 4.5
-5 *199:26 *199:27 238.95
-6 *199:27 la_data_out[28] 1.575
-*END
-
-*D_NET *200 0.249
-*CONN
-*P la_data_out[29] O
-*I *419:la_data_out[29] O *D user_proj_example
-*CAP
-1 la_data_out[29] 0.000245505
-2 *419:la_data_out[29] 0.00015814
-3 *200:11 0.0277182
-4 *200:10 0.0274727
-5 *200:8 0.0111267
-6 *200:7 0.0112848
-7 *200:7 *419:la_oenb[29] 0.00058307
-8 *200:8 *205:8 0.158325
-9 *200:8 *299:14 0.0120783
-10 *419:la_data_in[29] *200:7 0
-11 *136:15 *200:11 7.67196e-06
-12 *193:12 *200:8 0
-*RES
-1 *419:la_data_out[29] *200:7 7.065
-2 *200:7 *200:8 240.03
-3 *200:8 *200:10 4.5
-4 *200:10 *200:11 268.65
-5 *200:11 la_data_out[29] 2.655
-*END
-
-*D_NET *201 0.117559
-*CONN
-*P la_data_out[2] O
-*I *419:la_data_out[2] O *D user_proj_example
-*CAP
-1 la_data_out[2] 0.0141292
-2 *419:la_data_out[2] 0.00132637
-3 *201:14 0.0141292
-4 *201:12 0.00706171
-5 *201:11 0.00838808
-6 la_data_out[2] *246:11 0
-7 la_data_out[2] *262:17 0.0128275
-8 *201:11 *419:la_oenb[2] 0.000417739
-9 *419:la_data_in[2] *201:11 0.000528215
-10 *419:la_data_in[3] *201:11 0
-11 *135:15 la_data_out[2] 0.049295
-12 *137:19 *201:11 0.00203
-13 *148:15 *201:11 0.00742647
-*RES
-1 *419:la_data_out[2] *201:11 40.365
-2 *201:11 *201:12 67.59
-3 *201:12 *201:14 4.5
-4 *201:14 la_data_out[2] 235.665
-*END
-
-*D_NET *202 0.377365
-*CONN
-*P la_data_out[30] O
-*I *419:la_data_out[30] O *D user_proj_example
-*CAP
-1 la_data_out[30] 0.00333642
-2 *419:la_data_out[30] 0.00152082
-3 *202:19 0.024587
-4 *202:18 0.0212506
-5 *202:16 0.00463592
-6 *202:15 0.00615674
-7 *202:15 *419:la_oenb[30] 0.0023957
-8 *202:15 *266:19 0.00754921
-9 *202:16 *269:16 0.157724
-10 *419:la_data_in[30] *202:15 0
-11 *178:16 *202:16 0.00460055
-12 *195:13 *202:15 0.00105336
-13 *197:20 *202:16 0.142555
-*RES
-1 *419:la_data_out[30] *202:15 35.145
-2 *202:15 *202:16 248.31
-3 *202:16 *202:18 4.5
-4 *202:18 *202:19 209.7
-5 *202:19 la_data_out[30] 32.265
-*END
-
-*D_NET *203 0.272522
-*CONN
-*P la_data_out[31] O
-*I *419:la_data_out[31] O *D user_proj_example
-*CAP
-1 la_data_out[31] 0.000187838
-2 *419:la_data_out[31] 0.00176272
-3 *203:19 0.0241932
-4 *203:18 0.0240054
-5 *203:16 0.0139799
-6 *203:15 0.0157426
-7 *203:15 *419:la_oenb[31] 0.00666336
-8 *203:15 *257:15 0.000804022
-9 *203:15 *267:19 0.0160191
-10 *203:16 *206:10 0.169163
-11 *203:16 *231:16 0
-12 *419:la_data_in[31] *203:15 0
-*RES
-1 *419:la_data_out[31] *203:15 40.005
-2 *203:15 *203:16 253.71
-3 *203:16 *203:18 4.5
-4 *203:18 *203:19 236.61
-5 *203:19 la_data_out[31] 2.115
-*END
-
-*D_NET *204 0.353292
-*CONN
-*P la_data_out[32] O
-*I *419:la_data_out[32] O *D user_proj_example
-*CAP
-1 la_data_out[32] 0.000699672
-2 *419:la_data_out[32] 0.00163298
-3 *204:13 0.0252293
-4 *204:12 0.0245296
-5 *204:10 0.00782225
-6 *204:9 0.00945523
-7 la_data_out[32] *295:8 0.00105689
-8 *204:9 *419:la_oenb[32] 0.00254709
-9 *419:la_data_in[33] *204:9 4.47532e-06
-10 *141:19 *204:9 0.00129784
-11 *157:16 *204:10 0.150886
-12 *195:14 *204:10 0.128131
-*RES
-1 *419:la_data_out[32] *204:9 29.295
-2 *204:9 *204:10 259.65
-3 *204:10 *204:12 4.5
-4 *204:12 *204:13 241.11
-5 *204:13 la_data_out[32] 16.515
-*END
-
-*D_NET *205 0.394974
-*CONN
-*P la_data_out[33] O
-*I *419:la_data_out[33] O *D user_proj_example
-*CAP
-1 la_data_out[33] 0.000919192
-2 *419:la_data_out[33] 0.000198808
-3 *205:11 0.0276032
-4 *205:10 0.0266841
-5 *205:8 0.00796025
-6 *205:7 0.00815906
-7 la_data_out[33] *269:13 0
-8 la_data_out[33] *295:8 0.00354368
-9 *205:7 *419:la_oenb[33] 0.000210596
-10 *205:8 *299:14 0.00116255
-11 *205:11 *268:7 0.000383598
-12 *419:la_data_in[33] *205:7 0
-13 *141:15 *205:11 0
-14 *154:14 *205:8 0.159824
-15 *193:12 *205:8 0
-16 *200:8 *205:8 0.158325
-*RES
-1 *419:la_data_out[33] *205:7 7.245
-2 *205:7 *205:8 262.89
-3 *205:8 *205:10 4.5
-4 *205:10 *205:11 262.53
-5 *205:11 la_data_out[33] 20.115
-*END
-
-*D_NET *206 0.415415
-*CONN
-*P la_data_out[34] O
-*I *419:la_data_out[34] O *D user_proj_example
-*CAP
-1 la_data_out[34] 0.000236116
-2 *419:la_data_out[34] 0.00241532
-3 *206:13 0.0242027
-4 *206:12 0.0239665
-5 *206:10 0.00479356
-6 *206:9 0.00720887
-7 la_data_out[34] *270:15 2.5829e-05
-8 *206:9 *419:la_oenb[34] 0.00254709
-9 *206:10 *211:10 0.178489
-10 *419:la_data_in[34] *206:9 0
-11 *419:la_data_in[35] *206:9 4.47532e-06
-12 *142:11 *206:13 7.67196e-06
-13 *143:11 *206:9 0.00235402
-14 *203:16 *206:10 0.169163
-*RES
-1 *419:la_data_out[34] *206:9 40.095
-2 *206:9 *206:10 271.89
-3 *206:10 *206:12 4.5
-4 *206:12 *206:13 236.43
-5 *206:13 la_data_out[34] 2.655
-*END
-
-*D_NET *207 0.398045
-*CONN
-*P la_data_out[35] O
-*I *419:la_data_out[35] O *D user_proj_example
-*CAP
-1 la_data_out[35] 0.00332477
-2 *419:la_data_out[35] 0.000750232
-3 *207:17 0.0242513
-4 *207:16 0.0209265
-5 *207:14 0.00568898
-6 *207:13 0.00801116
-7 *207:10 0.00307241
-8 *207:10 *419:la_oenb[35] 0.00115591
-9 *207:10 *269:24 0.00441406
-10 *207:13 *419:la_oenb[40] 0.000822435
-11 *207:13 *213:15 0.000730371
-12 *207:13 *278:19 0
-13 *207:14 *214:14 0.182716
-14 *419:la_data_in[35] *207:10 0
-15 *419:la_data_in[38] *207:10 0.00167858
-16 *142:22 *207:10 0.000111905
-17 *144:16 *207:10 0.0012421
-18 *193:12 *207:10 7.46038e-05
-19 *199:24 *207:14 0.139073
-*RES
-1 *419:la_data_out[35] *207:10 28.575
-2 *207:10 *207:13 31.95
-3 *207:13 *207:14 266.13
-4 *207:14 *207:16 4.5
-5 *207:16 *207:17 207
-6 *207:17 la_data_out[35] 32.265
-*END
-
-*D_NET *208 0.228348
-*CONN
-*P la_data_out[36] O
-*I *419:la_data_out[36] O *D user_proj_example
-*CAP
-1 la_data_out[36] 0.000187838
-2 *419:la_data_out[36] 0.00255198
-3 *208:17 0.00686514
-4 *208:16 0.0066773
-5 *208:14 0.025681
-6 *208:13 0.025681
-7 *208:11 0.00932257
-8 *208:9 0.0118745
-9 *208:9 *419:la_oenb[36] 0.00254709
-10 *208:9 *272:19 0.002175
-11 *208:9 *273:11 0
-12 *208:11 *272:19 0.1133
-13 *208:14 *241:14 0.0205782
-14 *419:la_data_in[36] *208:9 0.000150371
-15 *419:la_data_in[37] *208:9 0.000756329
-*RES
-1 *419:la_data_out[36] *208:9 41.175
-2 *208:9 *208:11 166.14
-3 *208:11 *208:13 4.5
-4 *208:13 *208:14 286.11
-5 *208:14 *208:16 4.5
-6 *208:16 *208:17 65.61
-7 *208:17 la_data_out[36] 2.115
-*END
-
-*D_NET *209 0.290924
-*CONN
-*P la_data_out[37] O
-*I *419:la_data_out[37] O *D user_proj_example
-*CAP
-1 la_data_out[37] 0.0236298
-2 *419:la_data_out[37] 0.00248474
-3 *209:14 0.0236298
-4 *209:12 0.0157266
-5 *209:11 0.0182114
-6 *209:11 *419:la_oenb[37] 0.00612325
-7 *209:12 *210:16 0.201119
-8 *419:la_data_in[37] *209:11 0
-*RES
-1 *419:la_data_out[37] *209:11 42.525
-2 *209:11 *209:12 294.21
-3 *209:12 *209:14 4.5
-4 *209:14 la_data_out[37] 233.505
-*END
-
-*D_NET *210 0.467462
-*CONN
-*P la_data_out[38] O
-*I *419:la_data_out[38] O *D user_proj_example
-*CAP
-1 la_data_out[38] 0.000125413
-2 *419:la_data_out[38] 0.00172833
-3 *210:19 0.0237186
-4 *210:18 0.0235932
-5 *210:16 0.00480799
-6 *210:15 0.00480799
-7 *210:13 0.00172833
-8 *210:13 *419:la_oenb[38] 0.0118148
-9 *210:13 *269:24 0
-10 *210:16 *283:16 0.187566
-11 *419:la_data_in[38] *210:13 0.000417739
-12 *147:19 *210:13 0.00603528
-13 *209:12 *210:16 0.201119
-*RES
-1 *419:la_data_out[38] *210:13 47.4907
-2 *210:13 *210:15 4.5
-3 *210:15 *210:16 299.25
-4 *210:16 *210:18 4.5
-5 *210:18 *210:19 233.37
-6 *210:19 la_data_out[38] 1.575
-*END
-
-*D_NET *211 0.443557
-*CONN
-*P la_data_out[39] O
-*I *419:la_data_out[39] O *D user_proj_example
-*CAP
-1 la_data_out[39] 0.000245505
-2 *419:la_data_out[39] 0.00224249
-3 *211:13 0.0241373
-4 *211:12 0.0238918
-5 *211:10 0.0056268
-6 *211:9 0.00786929
-7 *211:9 *419:la_oenb[39] 0.00254709
-8 *211:9 *275:11 0.00182976
-9 *211:9 *277:19 0
-10 *211:10 *215:14 0.00460055
-11 *211:10 *281:16 0.191296
-12 *419:la_data_in[40] *211:9 0.00077423
-13 *147:11 *211:13 7.67196e-06
-14 *206:10 *211:10 0.178489
-*RES
-1 *419:la_data_out[39] *211:9 40.275
-2 *211:9 *211:10 304.29
-3 *211:10 *211:12 4.5
-4 *211:12 *211:13 236.25
-5 *211:13 la_data_out[39] 2.655
-*END
-
-*D_NET *212 0.218542
-*CONN
-*P la_data_out[3] O
-*I *419:la_data_out[3] O *D user_proj_example
-*CAP
-1 la_data_out[3] 0.00153717
-2 *419:la_data_out[3] 0.00217097
-3 *212:12 0.00669164
-4 *212:11 0.00515447
-5 *212:9 0.0125978
-6 *212:7 0.0147688
-7 la_data_out[3] *276:15 0
-8 *212:7 *419:la_oenb[3] 0.000445358
-9 *212:12 *261:8 0.0080199
-10 *419:la_data_in[3] *212:7 0
-11 *419:la_data_in[4] *212:7 0
-12 *119:8 *212:12 0.00874512
-13 *159:11 *212:7 0.00460318
-14 *159:11 *212:9 0.153808
-*RES
-1 *419:la_data_out[3] *212:7 31.725
-2 *212:7 *212:9 225.54
-3 *212:9 *212:11 4.5
-4 *212:11 *212:12 73.71
-5 *212:12 la_data_out[3] 18.765
-*END
-
-*D_NET *213 0.322832
-*CONN
-*P la_data_out[40] O
-*I *419:la_data_out[40] O *D user_proj_example
-*CAP
-1 la_data_out[40] 0.00330144
-2 *419:la_data_out[40] 0.002178
-3 *213:19 0.0233903
-4 *213:18 0.0200888
-5 *213:16 0.0168921
-6 *213:15 0.0190701
-7 *213:15 *419:la_oenb[40] 0.00666336
-8 *213:15 *277:19 0.0198244
-9 *213:16 *216:14 0.210693
-10 *419:la_data_in[40] *213:15 0
-11 *207:13 *213:15 0.000730371
-*RES
-1 *419:la_data_out[40] *213:15 45.585
-2 *213:15 *213:16 313.11
-3 *213:16 *213:18 4.5
-4 *213:18 *213:19 199.26
-5 *213:19 la_data_out[40] 32.265
-*END
-
-*D_NET *214 0.453106
-*CONN
-*P la_data_out[41] O
-*I *419:la_data_out[41] O *D user_proj_example
-*CAP
-1 la_data_out[41] 0.000187838
-2 *419:la_data_out[41] 0.00194462
-3 *214:17 0.0243152
-4 *214:16 0.0241273
-5 *214:14 0.00762583
-6 *214:13 0.00957045
-7 *214:13 *419:la_oenb[41] 0.00254709
-8 *214:13 *278:19 0.00894935
-9 *214:14 *231:16 0.190177
-10 *419:la_data_in[41] *214:13 0
-11 *419:la_data_in[42] *214:13 0.000944292
-12 *207:14 *214:14 0.182716
-*RES
-1 *419:la_data_out[41] *214:13 38.655
-2 *214:13 *214:14 318.51
-3 *214:14 *214:16 4.5
-4 *214:16 *214:17 238.59
-5 *214:17 la_data_out[41] 2.115
-*END
-
-*D_NET *215 0.495861
-*CONN
-*P la_data_out[42] O
-*I *419:la_data_out[42] O *D user_proj_example
-*CAP
-1 la_data_out[42] 0.0238386
-2 *419:la_data_out[42] 0.00212026
-3 *215:16 0.0238386
-4 *215:14 0.00507003
-5 *215:13 0.00719029
-6 *215:13 *419:la_oenb[42] 0.00254709
-7 *215:13 *279:11 0.0107906
-8 *215:14 *228:16 0.203108
-9 *215:14 *281:16 0.211812
-10 *419:la_data_in[43] *215:13 0.000944292
-11 *211:10 *215:14 0.00460055
-*RES
-1 *419:la_data_out[42] *215:13 41.355
-2 *215:13 *215:14 326.61
-3 *215:14 *215:16 4.5
-4 *215:16 la_data_out[42] 235.845
-*END
-
-*D_NET *216 0.501955
-*CONN
-*P la_data_out[43] O
-*I *419:la_data_out[43] O *D user_proj_example
-*CAP
-1 la_data_out[43] 0.000125413
-2 *419:la_data_out[43] 0.00256679
-3 *216:17 0.0234278
-4 *216:16 0.0233024
-5 *216:14 0.006005
-6 *216:13 0.00857178
-7 *216:13 *419:la_oenb[43] 0.00254709
-8 *216:13 *280:19 0.0142277
-9 *216:14 *288:16 0.209947
-10 *419:la_data_in[44] *216:13 0.000541513
-11 *213:16 *216:14 0.210693
-*RES
-1 *419:la_data_out[43] *216:13 46.395
-2 *216:13 *216:14 332.01
-3 *216:14 *216:16 4.5
-4 *216:16 *216:17 230.85
-5 *216:17 la_data_out[43] 1.575
-*END
-
-*D_NET *217 0.407507
-*CONN
-*P la_data_out[44] O
-*I *419:la_data_out[44] O *D user_proj_example
-*CAP
-1 la_data_out[44] 0.000236116
-2 *419:la_data_out[44] 0.000445781
-3 *217:17 0.0273029
-4 *217:16 0.0270668
-5 *217:14 0.00874703
-6 *217:13 0.00919281
-7 la_data_out[44] *281:13 2.5829e-05
-8 *217:13 *419:la_oenb[44] 0.000348691
-9 *217:13 *218:9 3.45239e-05
-10 *217:14 *294:16 0
-11 *419:la_data_in[41] *217:13 0.00167858
-12 *419:la_data_in[44] *217:13 0
-13 *33:9 *217:14 0.0514144
-14 *144:16 *217:13 0.00167847
-15 *144:16 *217:14 0.179111
-16 *153:11 *217:17 7.67196e-06
-17 *168:16 *217:14 0.00690085
-18 *193:12 *217:14 0.0933163
-*RES
-1 *419:la_data_out[44] *217:13 20.925
-2 *217:13 *217:14 334.89
-3 *217:14 *217:16 4.5
-4 *217:16 *217:17 267.03
-5 *217:17 la_data_out[44] 2.655
-*END
-
-*D_NET *218 0.222872
-*CONN
-*P la_data_out[45] O
-*I *419:la_data_out[45] O *D user_proj_example
-*CAP
-1 la_data_out[45] 0.00325098
-2 *419:la_data_out[45] 0.00227556
-3 *218:19 0.00723673
-4 *218:14 0.0365055
-5 *218:13 0.0325198
-6 *218:11 0.00953376
-7 *218:9 0.0118093
-8 *218:9 *419:la_oenb[45] 0.00254709
-9 *419:la_data_in[45] *218:9 0
-10 *419:la_data_in[46] *218:9 4.47532e-06
-11 *155:19 *218:9 0.00201389
-12 *155:19 *218:11 0.115141
-13 *217:13 *218:9 3.45239e-05
-*RES
-1 *419:la_data_out[45] *218:9 32.715
-2 *218:9 *218:11 168.84
-3 *218:11 *218:13 4.5
-4 *218:13 *218:14 345.33
-5 *218:14 *218:19 44.19
-6 *218:19 la_data_out[45] 31.815
-*END
-
-*D_NET *219 0.483691
-*CONN
-*P la_data_out[46] O
-*I *419:la_data_out[46] O *D user_proj_example
-*CAP
-1 la_data_out[46] 0.000187838
-2 *419:la_data_out[46] 0.00113974
-3 *219:17 0.0265097
-4 *219:16 0.0263219
-5 *219:14 0.00764174
-6 *219:13 0.00878148
-7 *219:13 *419:la_oenb[46] 0
-8 *219:13 *419:la_oenb[49] 0.00913896
-9 *219:13 *419:la_oenb[54] 0.000225045
-10 *219:13 *228:15 0.00073344
-11 *419:la_data_in[41] *219:13 0.000184127
-12 *419:la_data_in[46] *219:13 0
-13 *419:la_data_in[47] *219:13 0.000994715
-14 *419:la_data_in[55] *219:13 0.000465433
-15 *142:22 *219:13 0.0153559
-16 *144:16 *219:13 6.21698e-05
-17 *146:16 *219:14 0.174759
-18 *174:16 *219:14 0.211191
-*RES
-1 *419:la_data_out[46] *219:13 46.845
-2 *219:13 *219:14 328.59
-3 *219:14 *219:16 4.5
-4 *219:16 *219:17 260.19
-5 *219:17 la_data_out[46] 2.115
-*END
-
-*D_NET *220 0.416704
-*CONN
-*P la_data_out[47] O
-*I *419:la_data_out[47] O *D user_proj_example
-*CAP
-1 la_data_out[47] 0.0229951
-2 *419:la_data_out[47] 0.00283722
-3 *220:16 0.0229951
-4 *220:14 0.0149188
-5 *220:13 0.0177561
-6 *220:13 *419:la_oenb[46] 0
-7 *220:13 *419:la_oenb[47] 0.00144233
-8 *220:13 *284:11 0.0248848
-9 *220:14 *224:10 0.242524
-10 *220:14 *252:16 0.0652158
-11 *419:la_data_in[47] *220:13 0
-12 *419:la_data_in[48] *220:13 4.02619e-05
-13 *39:10 *220:14 0.00109419
-*RES
-1 *419:la_data_out[47] *220:13 49.275
-2 *220:13 *220:14 359.01
-3 *220:14 *220:16 4.5
-4 *220:16 la_data_out[47] 228.105
-*END
-
-*D_NET *221 0.558419
-*CONN
-*P la_data_out[48] O
-*I *419:la_data_out[48] O *D user_proj_example
-*CAP
-1 la_data_out[48] 0.00114801
-2 *419:la_data_out[48] 0.00127573
-3 *221:21 0.0247748
-4 *221:20 0.0236268
-5 *221:18 0.00405017
-6 *221:17 0.00532589
-7 la_data_out[48] *285:15 0
-8 la_data_out[48] *310:14 0
-9 *221:17 *419:la_oenb[48] 0.000662325
-10 *221:17 *283:22 0.000448043
-11 *221:17 *285:19 0.0139323
-12 *221:21 *284:7 0.000604551
-13 *419:la_data_in[48] *221:17 0.000240133
-14 *419:la_data_in[49] *221:17 0.000552382
-15 *157:13 *221:21 0
-16 *158:8 la_data_out[48] 0.000708712
-17 *160:14 *221:18 0.247124
-18 *172:14 *221:18 0.226484
-19 *196:12 *221:18 0.00746021
-*RES
-1 *419:la_data_out[48] *221:17 32.715
-2 *221:17 *221:18 360.27
-3 *221:18 *221:20 4.5
-4 *221:20 *221:21 236.97
-5 *221:21 la_data_out[48] 21.555
-*END
-
-*D_NET *222 0.342919
-*CONN
-*P la_data_out[49] O
-*I *419:la_data_out[49] O *D user_proj_example
-*CAP
-1 la_data_out[49] 0.000236116
-2 *419:la_data_out[49] 0.00190293
-3 *222:15 0.0236357
-4 *222:14 0.0233996
-5 *222:12 0.0204576
-6 *222:11 0.0223605
-7 la_data_out[49] *286:15 2.5829e-05
-8 *222:11 *419:la_oenb[49] 0.000403929
-9 *222:11 *281:21 0.00205916
-10 *222:11 *283:22 0
-11 *222:12 *283:16 0.238669
-12 *419:la_data_in[49] *222:11 0
-13 *419:la_data_in[50] *222:11 0.00456227
-14 *158:7 *222:15 0.000234762
-15 *178:13 *222:11 0.00497143
-*RES
-1 *419:la_data_out[49] *222:11 43.065
-2 *222:11 *222:12 369.81
-3 *222:12 *222:14 4.5
-4 *222:14 *222:15 233.01
-5 *222:15 la_data_out[49] 2.655
-*END
-
-*D_NET *223 0.350223
-*CONN
-*P la_data_out[4] O
-*I *419:la_data_out[4] O *D user_proj_example
-*CAP
-1 la_data_out[4] 0.00258828
-2 *419:la_data_out[4] 0.00226562
-3 *223:24 0.00475721
-4 *223:23 0.00216893
-5 *223:21 0.00652495
-6 *223:19 0.00655379
-7 *223:17 0.00229446
-8 la_data_out[4] *287:15 1.87963e-05
-9 *223:17 *419:la_oenb[4] 0.00231387
-10 *223:17 *287:19 0.00251641
-11 *223:21 wbs_dat_o[27] 0.00210723
-12 *223:21 *287:19 0.148161
-13 *223:21 *400:17 0.0801567
-14 *223:24 *234:14 0.05216
-15 *419:la_data_in[4] *223:17 0
-16 *159:7 la_data_out[4] 0.000136561
-17 *184:10 *223:24 0.0354987
-*RES
-1 *419:la_data_out[4] *223:17 49.995
-2 *223:17 *223:19 0.27
-3 *223:19 *223:21 217.26
-4 *223:21 *223:23 4.5
-5 *223:23 *223:24 78.03
-6 *223:24 la_data_out[4] 29.745
-*END
-
-*D_NET *224 0.566525
-*CONN
-*P la_data_out[50] O
-*I *419:la_data_out[50] O *D user_proj_example
-*CAP
-1 la_data_out[50] 0.00328396
-2 *419:la_data_out[50] 0.00388316
-3 *224:13 0.0230052
-4 *224:12 0.0197212
-5 *224:10 0.00531124
-6 *224:9 0.0091944
-7 *224:9 *419:la_oenb[50] 0
-8 *224:9 *281:21 0
-9 *224:10 *235:10 0.242524
-10 *419:la_data_in[47] *224:9 0
-11 *419:la_data_in[50] *224:9 0.000242434
-12 *419:la_data_in[51] *224:9 0.010618
-13 *39:10 *224:10 0.00621689
-14 *172:11 la_data_out[50] 0
-15 *172:11 *224:13 0
-16 *220:14 *224:10 0.242524
-*RES
-1 *419:la_data_out[50] *224:9 48.195
-2 *224:9 *224:10 378.09
-3 *224:10 *224:12 4.5
-4 *224:12 *224:13 196.2
-5 *224:13 la_data_out[50] 32.265
-*END
-
-*D_NET *225 0.591146
-*CONN
-*P la_data_out[51] O
-*I *419:la_data_out[51] O *D user_proj_example
-*CAP
-1 la_data_out[51] 0.000187838
-2 *419:la_data_out[51] 0.00306997
-3 *225:17 0.0228362
-4 *225:16 0.0226484
-5 *225:14 0.00514428
-6 *225:13 0.00514428
-7 *225:11 0.00306997
-8 *225:11 *419:la_oenb[51] 0.00144233
-9 *225:11 *289:11 0.0269716
-10 *225:14 *233:10 0.249985
-11 *225:14 *256:16 0.00708727
-12 *225:14 *291:16 0.243519
-13 *419:la_data_in[52] *225:11 4.02779e-05
-*RES
-1 *419:la_data_out[51] *225:11 47.835
-2 *225:11 *225:13 4.5
-3 *225:13 *225:14 383.31
-4 *225:14 *225:16 4.5
-5 *225:16 *225:17 225.09
-6 *225:17 la_data_out[51] 2.115
-*END
-
-*D_NET *226 0.360733
-*CONN
-*P la_data_out[52] O
-*I *419:la_data_out[52] O *D user_proj_example
-*CAP
-1 la_data_out[52] 0.0223775
-2 *419:la_data_out[52] 0.00487001
-3 *226:12 0.0223775
-4 *226:10 0.0167396
-5 *226:9 0.0167396
-6 *226:7 0.00487001
-7 *226:7 *419:la_oenb[52] 0
-8 *226:10 *293:16 0.26217
-9 *419:la_data_in[52] *226:7 0.000837779
-10 *419:la_data_in[53] *226:7 0
-11 *108:14 *226:10 0.00975133
-*RES
-1 *419:la_data_out[52] *226:7 49.095
-2 *226:7 *226:9 4.5
-3 *226:9 *226:10 391.59
-4 *226:10 *226:12 4.5
-5 *226:12 la_data_out[52] 222.525
-*END
-
-*D_NET *227 0.371405
-*CONN
-*P la_data_out[53] O
-*I *419:la_data_out[53] O *D user_proj_example
-*CAP
-1 la_data_out[53] 0.000125413
-2 *419:la_data_out[53] 0.00324321
-3 *227:11 0.0221958
-4 *227:10 0.0220704
-5 *227:8 0.0208396
-6 *227:7 0.0208396
-7 *227:5 0.00324321
-8 *227:5 *419:la_oenb[53] 0.000341786
-9 *227:5 *288:25 0.00295294
-10 *227:8 *230:10 0.268635
-11 *419:la_data_in[53] *227:5 0
-12 *419:la_data_in[54] *227:5 0.00513511
-13 *182:14 *227:8 0.0017822
-*RES
-1 *419:la_data_out[53] *227:5 51.345
-2 *227:5 *227:7 4.5
-3 *227:7 *227:8 396.63
-4 *227:8 *227:10 4.5
-5 *227:10 *227:11 219.87
-6 *227:11 la_data_out[53] 1.575
-*END
-
-*D_NET *228 0.328166
-*CONN
-*P la_data_out[54] O
-*I *419:la_data_out[54] O *D user_proj_example
-*CAP
-1 la_data_out[54] 0.000245505
-2 *419:la_data_out[54] 0.00230855
-3 *228:19 0.0239438
-4 *228:18 0.0236983
-5 *228:16 0.0247529
-6 *228:15 0.0270615
-7 *228:15 *419:la_oenb[54] 0.000257394
-8 *228:15 *292:11 0.00130935
-9 *228:16 *281:16 0.00435188
-10 *419:la_data_in[54] *228:15 0
-11 *419:la_data_in[55] *228:15 0
-12 *164:11 *228:19 7.67196e-06
-13 *165:11 *228:15 0.0163873
-14 *215:14 *228:16 0.203108
-15 *219:13 *228:15 0.00073344
-*RES
-1 *419:la_data_out[54] *228:15 40.725
-2 *228:15 *228:16 402.03
-3 *228:16 *228:18 4.5
-4 *228:18 *228:19 235.71
-5 *228:19 la_data_out[54] 2.655
-*END
-
-*D_NET *229 0.591538
-*CONN
-*P la_data_out[55] O
-*I *419:la_data_out[55] O *D user_proj_example
-*CAP
-1 la_data_out[55] 0.00104047
-2 *419:la_data_out[55] 0.00441602
-3 *229:13 0.0235167
-4 *229:12 0.0224763
-5 *229:10 0.00705793
-6 *229:9 0.0114739
-7 *229:9 *419:la_oenb[55] 0
-8 *229:10 *288:16 0.253715
-9 *229:10 *309:10 0.263911
-10 *419:la_data_in[55] *229:9 0.000395873
-11 *142:21 *229:9 0.000365186
-12 *165:5 *229:13 0
-13 *172:8 la_data_out[55] 0.00317055
-*RES
-1 *419:la_data_out[55] *229:9 45.675
-2 *229:9 *229:10 406.35
-3 *229:10 *229:12 4.5
-4 *229:12 *229:13 223.65
-5 *229:13 la_data_out[55] 20.475
-*END
-
-*D_NET *230 0.634529
-*CONN
-*P la_data_out[56] O
-*I *419:la_data_out[56] O *D user_proj_example
-*CAP
-1 la_data_out[56] 0.000187838
-2 *419:la_data_out[56] 4.01718e-05
-3 *230:13 0.0222277
-4 *230:12 0.0220398
-5 *230:10 0.00573559
-6 *230:9 0.00573559
-7 *230:7 0.00422506
-8 *230:5 0.00426523
-9 *230:7 *419:la_oenb[56] 0
-10 *230:7 *293:19 0
-11 *230:10 *237:10 0.276096
-12 *419:la_data_in[56] *230:7 0.0011109
-13 *419:la_data_in[57] *230:7 0.014546
-14 *133:24 *230:7 0.000171852
-15 *142:21 *230:7 0
-16 *182:14 *230:10 0.00951176
-17 *227:8 *230:10 0.268635
-*RES
-1 *419:la_data_out[56] *230:5 0.405
-2 *230:5 *230:7 51.57
-3 *230:7 *230:9 4.5
-4 *230:9 *230:10 415.89
-5 *230:10 *230:12 4.5
-6 *230:12 *230:13 219.69
-7 *230:13 la_data_out[56] 2.115
-*END
-
-*D_NET *231 0.315635
-*CONN
-*P la_data_out[57] O
-*I *419:la_data_out[57] O *D user_proj_example
-*CAP
-1 la_data_out[57] 0.023945
-2 *419:la_data_out[57] 0.00249609
-3 *231:18 0.023945
-4 *231:16 0.0281608
-5 *231:15 0.0306569
-6 la_data_out[57] *232:13 0
-7 *231:15 *419:la_oenb[57] 0.00178194
-8 *231:15 *295:11 0.0144724
-9 *419:la_data_in[57] *231:15 0
-10 *203:16 *231:16 0
-11 *214:14 *231:16 0.190177
-*RES
-1 *419:la_data_out[57] *231:15 38.205
-2 *231:15 *231:16 423.81
-3 *231:16 *231:18 4.5
-4 *231:18 la_data_out[57] 238.365
-*END
-
-*D_NET *232 0.38685
-*CONN
-*P la_data_out[58] O
-*I *419:la_data_out[58] O *D user_proj_example
-*CAP
-1 la_data_out[58] 0.00106742
-2 *419:la_data_out[58] 0.00524529
-3 *232:13 0.0227293
-4 *232:12 0.0216619
-5 *232:10 0.0225903
-6 *232:9 0.0225903
-7 *232:7 0.00524529
-8 la_data_out[58] *295:8 0.00304632
-9 la_data_out[58] *296:13 0
-10 *232:7 *419:la_oenb[57] 0
-11 *232:7 *419:la_oenb[58] 0
-12 *232:10 *293:16 0.279826
-13 la_data_out[57] *232:13 0
-14 *419:la_data_in[58] *232:7 0.000423492
-15 *419:la_data_in[59] *232:7 0
-16 *108:14 *232:10 0
-17 *172:8 la_data_out[58] 0.00242462
-*RES
-1 *419:la_data_out[58] *232:7 49.455
-2 *232:7 *232:9 4.5
-3 *232:9 *232:10 419.85
-4 *232:10 *232:12 4.5
-5 *232:12 *232:13 215.91
-6 *232:13 la_data_out[58] 25.875
-*END
-
-*D_NET *233 0.368736
-*CONN
-*P la_data_out[59] O
-*I *419:la_data_out[59] O *D user_proj_example
-*CAP
-1 la_data_out[59] 0.000236116
-2 *419:la_data_out[59] 0.0039496
-3 *233:13 0.022799
-4 *233:12 0.0225629
-5 *233:10 0.0249848
-6 *233:9 0.0249848
-7 *233:7 0.0039496
-8 la_data_out[59] *297:13 2.5829e-05
-9 *233:7 *419:la_oenb[59] 0.000626544
-10 *233:10 *291:16 0.00497357
-11 *419:la_data_in[59] *233:7 0.000751853
-12 *419:la_data_in[60] *233:7 0.00889948
-13 *108:14 *233:10 0
-14 *169:11 *233:13 7.67196e-06
-15 *225:14 *233:10 0.249985
-*RES
-1 *419:la_data_out[59] *233:7 46.755
-2 *233:7 *233:9 4.5
-3 *233:9 *233:10 434.79
-4 *233:10 *233:12 4.5
-5 *233:12 *233:13 224.91
-6 *233:13 la_data_out[59] 2.655
-*END
-
-*D_NET *234 0.354569
-*CONN
-*P la_data_out[5] O
-*I *419:la_data_out[5] O *D user_proj_example
-*CAP
-1 la_data_out[5] 0.00238438
-2 *419:la_data_out[5] 0.000553466
-3 *234:14 0.00714188
-4 *234:13 0.0047575
-5 *234:11 0.00680686
-6 *234:9 0.00736032
-7 *234:9 *419:la_oenb[5] 0.00152417
-8 *234:11 *419:la_oenb[5] 7.36509e-05
-9 *234:11 *298:11 0.163689
-10 *234:14 *272:16 0.00217594
-11 *419:la_data_in[5] *234:11 0
-12 *419:la_data_in[6] *234:9 4.47532e-06
-13 *419:la_data_in[6] *234:11 0
-14 *175:19 *234:11 0.104093
-15 *184:10 *234:14 0.00184437
-16 *223:24 *234:14 0.05216
-*RES
-1 *419:la_data_out[5] *234:9 8.145
-2 *234:9 *234:11 242.19
-3 *234:11 *234:13 4.5
-4 *234:13 *234:14 86.67
-5 *234:14 la_data_out[5] 26.865
-*END
-
-*D_NET *235 0.634032
-*CONN
-*P la_data_out[60] O
-*I *419:la_data_out[60] O *D user_proj_example
-*CAP
-1 la_data_out[60] 0.00326646
-2 *419:la_data_out[60] 0.00373331
-3 *235:13 0.0229115
-4 *235:12 0.019645
-5 *235:10 0.00857449
-6 *235:9 0.0123078
-7 *235:9 *419:la_oenb[60] 0
-8 *235:9 *286:19 0
-9 *419:la_data_in[60] *235:9 0.000217884
-10 *419:la_data_in[61] *235:9 0.0149143
-11 *39:10 *235:10 0.305937
-12 *224:10 *235:10 0.242524
-*RES
-1 *419:la_data_out[60] *235:9 48.375
-2 *235:9 *235:10 442.89
-3 *235:10 *235:12 4.5
-4 *235:12 *235:13 196.02
-5 *235:13 la_data_out[60] 32.265
-*END
-
-*D_NET *236 0.241921
-*CONN
-*P la_data_out[61] O
-*I *419:la_data_out[61] O *D user_proj_example
-*CAP
-1 la_data_out[61] 0.000187838
-2 *419:la_data_out[61] 0.000542157
-3 *236:19 0.0219572
-4 *236:18 0.0217694
-5 *236:16 0.0363809
-6 *236:15 0.0363809
-7 *236:13 0.00317548
-8 *236:11 0.00371764
-9 *236:11 *419:la_oenb[61] 0.000695848
-10 *236:11 *286:19 0
-11 *236:11 *300:17 0.000184127
-12 *236:13 *300:17 0.00626033
-13 *236:16 *262:12 0.0967983
-14 *236:19 *300:13 0
-15 la_data_out[12] *236:13 0.00190265
-16 *419:la_data_in[61] *236:11 0
-17 *419:la_data_in[62] *236:11 0
-18 *419:la_data_in[62] *236:13 0.0119683
-19 *172:7 *236:19 0
-*RES
-1 *419:la_data_out[61] *236:11 7.155
-2 *236:11 *236:13 47.97
-3 *236:13 *236:15 4.5
-4 *236:15 *236:16 447.93
-5 *236:16 *236:18 4.5
-6 *236:18 *236:19 216.81
-7 *236:19 la_data_out[61] 2.115
-*END
-
-*D_NET *237 0.384244
-*CONN
-*P la_data_out[62] O
-*I *419:la_data_out[62] O *D user_proj_example
-*CAP
-1 la_data_out[62] 0.0220011
-2 *419:la_data_out[62] 4.01718e-05
-3 *237:12 0.0220011
-4 *237:10 0.0263466
-5 *237:9 0.0263466
-6 *237:7 0.00542669
-7 *237:5 0.00546686
-8 *237:7 *419:la_oenb[62] 0
-9 *237:7 *291:23 0.000270053
-10 *419:la_data_in[62] *237:7 0.000248572
-11 *230:10 *237:10 0.276096
-*RES
-1 *419:la_data_out[62] *237:5 0.405
-2 *237:5 *237:7 51.75
-3 *237:7 *237:9 4.5
-4 *237:9 *237:10 456.39
-5 *237:10 *237:12 4.5
-6 *237:12 la_data_out[62] 219.465
-*END
-
-*D_NET *238 0.414871
-*CONN
-*P la_data_out[63] O
-*I *419:la_data_out[63] O *D user_proj_example
-*CAP
-1 la_data_out[63] 0.000125413
-2 *419:la_data_out[63] 0.000707279
-3 *238:17 0.0264504
-4 *238:16 0.026325
-5 *238:14 0.0235718
-6 *238:13 0.024279
-7 *238:13 *419:la_oenb[63] 0.00103316
-8 *238:13 *301:20 0.00113978
-9 *238:13 *310:7 0
-10 *238:14 *301:12 0.295866
-11 *419:la_data_in[63] *238:13 0.000348691
-12 *121:8 *238:14 0.00951187
-13 *144:16 *238:13 0.00341934
-14 *166:16 *238:14 0.00209305
-*RES
-1 *419:la_data_out[63] *238:13 27.045
-2 *238:13 *238:14 456.57
-3 *238:14 *238:16 4.5
-4 *238:16 *238:17 262.71
-5 *238:17 la_data_out[63] 1.575
-*END
-
-*D_NET *239 0.191117
-*CONN
-*P la_data_out[6] O
-*I *419:la_data_out[6] O *D user_proj_example
-*CAP
-1 la_data_out[6] 0.000187838
-2 *419:la_data_out[6] 0.000484588
-3 *239:19 0.00678475
-4 *239:18 0.00659691
-5 *239:16 0.00920035
-6 *239:15 0.00920035
-7 *239:13 0.0113015
-8 *239:11 0.0117861
-9 *239:11 *419:la_oenb[6] 0.000686897
-10 *239:13 *419:la_oenb[6] 0.000699683
-11 *239:13 *303:11 8.18344e-05
-12 *419:la_data_in[6] *239:11 0
-13 *419:la_data_in[6] *239:13 0
-14 *419:la_data_in[7] *239:13 0
-15 *176:11 *239:13 0.134106
-*RES
-1 *419:la_data_out[6] *239:11 6.975
-2 *239:11 *239:13 202.05
-3 *239:13 *239:15 4.5
-4 *239:15 *239:16 91.53
-5 *239:16 *239:18 4.5
-6 *239:18 *239:19 62.91
-7 *239:19 la_data_out[6] 2.115
-*END
-
-*D_NET *240 0.261909
-*CONN
-*P la_data_out[7] O
-*I *419:la_data_out[7] O *D user_proj_example
-*CAP
-1 la_data_out[7] 0.00319092
-2 *419:la_data_out[7] 0.0137089
-3 *240:8 0.00871082
-4 *240:7 0.00551991
-5 *240:5 0.0137089
-6 *240:5 *419:la_oenb[7] 0.000403929
-7 *240:5 *401:11 0.000695592
-8 *240:8 *243:16 0.00293436
-9 *419:la_data_in[7] *240:5 0
-10 *419:la_data_in[8] *240:5 0
-11 *122:16 *240:8 0.000621697
-12 *123:16 *240:8 0.0522846
-13 *177:11 *240:5 0.160129
-*RES
-1 *419:la_data_out[7] *240:5 243.405
-2 *240:5 *240:7 4.5
-3 *240:7 *240:8 99.63
-4 *240:8 la_data_out[7] 32.265
-*END
-
-*D_NET *241 0.239274
-*CONN
-*P la_data_out[8] O
-*I *419:la_data_out[8] O *D user_proj_example
-*CAP
-1 la_data_out[8] 0.00010579
-2 *419:la_data_out[8] 0.000561158
-3 *241:17 0.00517772
-4 *241:16 0.00507193
-5 *241:14 0.0101926
-6 *241:13 0.0101926
-7 *241:11 0.0110611
-8 *241:9 0.0116223
-9 *241:9 *419:la_oenb[8] 0.00144233
-10 *241:9 *305:11 5.52382e-05
-11 *241:11 *305:11 0.135333
-12 *241:17 *284:11 0.0278032
-13 *419:la_data_in[9] *241:9 7.60804e-05
-14 *419:la_data_in[9] *241:11 0
-15 *208:14 *241:14 0.0205782
-*RES
-1 *419:la_data_out[8] *241:9 8.505
-2 *241:9 *241:11 198.45
-3 *241:11 *241:13 4.5
-4 *241:13 *241:14 105.39
-5 *241:14 *241:16 4.5
-6 *241:16 *241:17 65.79
-7 *241:17 la_data_out[8] 1.395
-*END
-
-*D_NET *242 0.257181
-*CONN
-*P la_data_out[9] O
-*I *419:la_data_out[9] O *D user_proj_example
-*CAP
-1 la_data_out[9] 0.00405805
-2 *419:la_data_out[9] 0.000822328
-3 *242:16 0.0116317
-4 *242:15 0.00757369
-5 *242:13 0.00900543
-6 *242:11 0.00982776
-7 *242:11 *419:la_oenb[9] 0.0026412
-8 *242:13 *419:la_oenb[9] 1.79013e-05
-9 *242:13 *265:11 0.00759218
-10 *242:13 *306:11 0.151905
-11 *419:la_data_in[9] *242:11 0
-12 *419:la_data_in[9] *242:13 0
-13 *107:10 *242:16 0
-14 *115:8 *242:16 0.0185885
-15 *141:16 *242:16 0.0335095
-16 *178:11 la_data_out[9] 7.67196e-06
-*RES
-1 *419:la_data_out[9] *242:11 13.095
-2 *242:11 *242:13 222.93
-3 *242:13 *242:15 4.5
-4 *242:15 *242:16 110.61
-5 *242:16 la_data_out[9] 43.245
-*END
-
-*D_NET *243 0.314811
-*CONN
-*P la_oenb[0] I
-*I *419:la_oenb[0] I *D user_proj_example
-*CAP
-1 la_oenb[0] 0.00311348
-2 *419:la_oenb[0] 0.000760027
-3 *243:19 0.00469748
-4 *243:18 0.00393745
-5 *243:16 0.00417767
-6 *243:15 0.00729115
-7 *243:19 *335:11 0.00154667
-8 *419:la_data_in[1] *419:la_oenb[0] 0.00111883
-9 *122:16 *243:16 0.0112527
-10 *126:11 *419:la_oenb[0] 0.000386667
-11 *126:11 *243:19 0.154605
-12 *179:17 *419:la_oenb[0] 0.00231387
-13 *179:17 *243:19 0.00337567
-14 *179:21 *243:19 0.1133
-15 *190:7 *419:la_oenb[0] 0
-16 *240:8 *243:16 0.00293436
-*RES
-1 la_oenb[0] *243:15 34.245
-2 *243:15 *243:16 56.61
-3 *243:16 *243:18 4.5
-4 *243:18 *243:19 226.71
-5 *243:19 *419:la_oenb[0] 17.505
-*END
-
-*D_NET *244 0.261803
-*CONN
-*P la_oenb[10] I
-*I *419:la_oenb[10] I *D user_proj_example
-*CAP
-1 la_oenb[10] 0.00488603
-2 *419:la_oenb[10] 0.00179682
-3 *244:19 0.0128521
-4 *244:18 0.0110552
-5 *244:16 0.00747962
-6 *244:15 0.0123656
-7 *244:16 *370:14 2.07232e-05
-8 *419:la_data_in[11] *419:la_oenb[10] 0.000655953
-9 *124:16 *244:16 0.0706867
-10 *180:7 *419:la_oenb[10] 0.00144233
-11 *180:9 *419:la_oenb[10] 0.00341249
-12 *180:9 *244:19 0.135149
-*RES
-1 la_oenb[10] *244:15 47.565
-2 *244:15 *244:16 121.23
-3 *244:16 *244:18 4.5
-4 *244:18 *244:19 198.18
-5 *244:19 *419:la_oenb[10] 32.535
-*END
-
-*D_NET *245 0.259262
-*CONN
-*P la_oenb[11] I
-*I *419:la_oenb[11] I *D user_proj_example
-*CAP
-1 la_oenb[11] 0.00433682
-2 *419:la_oenb[11] 0.00219515
-3 *245:19 0.0134042
-4 *245:18 0.0112091
-5 *245:16 0.00822103
-6 *245:15 0.0125579
-7 *419:la_data_in[12] *419:la_oenb[11] 0
-8 *118:13 *245:15 1.87963e-05
-9 *130:16 *245:16 0.0672049
-10 *181:7 *419:la_oenb[11] 0.00312377
-11 *181:7 *245:19 0.136991
-*RES
-1 la_oenb[11] *245:15 45.945
-2 *245:15 *245:16 126.81
-3 *245:16 *245:18 4.5
-4 *245:18 *245:19 200.88
-5 *245:19 *419:la_oenb[11] 32.715
-*END
-
-*D_NET *246 0.181347
-*CONN
-*P la_oenb[12] I
-*I *419:la_oenb[12] I *D user_proj_example
-*CAP
-1 la_oenb[12] 0.00101531
-2 *419:la_oenb[12] 0.000199423
-3 *246:16 0.00102936
-4 *246:11 0.0222134
-5 *246:10 0.0213835
-6 *246:8 0.00615912
-7 *246:7 0.00717443
-8 *246:8 *264:8 0.0617286
-9 *246:8 *265:8 0.00304577
-10 *246:8 *305:8 0.00055949
-11 *246:11 *419:la_oenb[26] 0.00255732
-12 *246:11 *261:11 0.00787144
-13 *246:11 *262:17 0
-14 *246:16 *419:la_oenb[22] 0.00752188
-15 *246:16 *419:la_oenb[3] 0.00124339
-16 *246:16 *419:la_oenb[7] 0.00938764
-17 *246:16 *248:24 0.0224426
-18 la_data_out[2] *246:11 0
-19 *419:la_data_in[12] *419:la_oenb[12] 0
-20 *419:la_data_in[13] *419:la_oenb[12] 0.00123774
-21 *419:la_data_in[27] *246:11 0.00132981
-22 *134:11 *246:11 0
-23 *182:10 *419:la_oenb[12] 0.00039012
-24 *182:10 *246:16 0.00186509
-25 *193:10 *246:16 6.99409e-05
-26 *197:17 *246:11 0.000921915
-27 *198:11 *246:11 0
-*RES
-1 la_oenb[12] *246:7 13.725
-2 *246:7 *246:8 96.21
-3 *246:8 *246:10 4.5
-4 *246:10 *246:11 256.59
-5 *246:11 *246:16 46.89
-6 *246:16 *419:la_oenb[12] 5.445
-*END
-
-*D_NET *247 0.284607
-*CONN
-*P la_oenb[13] I
-*I *419:la_oenb[13] I *D user_proj_example
-*CAP
-1 la_oenb[13] 0.0037109
-2 *419:la_oenb[13] 0.000813343
-3 *247:19 0.0115491
-4 *247:18 0.0107357
-5 *247:16 0.00542109
-6 *247:15 0.00913199
-7 *247:16 *254:16 0.00613407
-8 *419:la_data_in[13] *419:la_oenb[13] 0
-9 *419:la_data_in[14] *419:la_oenb[13] 0.000483334
-10 *107:10 *247:16 0.00483367
-11 *118:19 *419:la_oenb[13] 0.00343704
-12 *118:19 *247:19 0.00228241
-13 *131:16 *247:16 0.0782711
-14 *183:5 *419:la_oenb[13] 0.00712982
-15 *183:5 *247:19 0.140673
-*RES
-1 la_oenb[13] *247:15 40.005
-2 *247:15 *247:16 139.95
-3 *247:16 *247:18 4.5
-4 *247:18 *247:19 206.28
-5 *247:19 *419:la_oenb[13] 32.355
-*END
-
-*D_NET *248 0.155561
-*CONN
-*P la_oenb[14] I
-*I *419:la_oenb[14] I *D user_proj_example
-*CAP
-1 la_oenb[14] 0.000291782
-2 *419:la_oenb[14] 0.000406377
-3 *248:24 0.00220361
-4 *248:19 0.0195443
-5 *248:18 0.017747
-6 *248:16 0.00733989
-7 *248:15 0.00733989
-8 *248:13 0.00559122
-9 *248:11 0.005883
-10 *248:19 *266:19 0
-11 *248:24 *419:la_oenb[17] 0.000186509
-12 *248:24 *419:la_oenb[20] 0.000186509
-13 *248:24 *419:la_oenb[22] 0.00186509
-14 *248:24 *419:la_oenb[3] 0.00192726
-15 la_data_out[14] *248:13 2.5829e-05
-16 *419:la_data_in[15] *419:la_oenb[14] 0.000431548
-17 *419:la_data_in[16] *248:24 3.62657e-05
-18 *419:la_data_in[30] *248:19 0.00589207
-19 *107:7 *248:13 0
-20 *133:26 *248:24 0.00690085
-21 *138:11 *248:19 0.00648434
-22 *155:16 *248:16 0.0428347
-23 *184:7 *419:la_oenb[14] 0
-24 *246:16 *248:24 0.0224426
-*RES
-1 la_oenb[14] *248:11 3.015
-2 *248:11 *248:13 49.59
-3 *248:13 *248:15 4.5
-4 *248:15 *248:16 104.13
-5 *248:16 *248:18 4.5
-6 *248:18 *248:19 216.09
-7 *248:19 *248:24 49.59
-8 *248:24 *419:la_oenb[14] 5.625
-*END
-
-*D_NET *249 0.142973
-*CONN
-*P la_oenb[15] I
-*I *419:la_oenb[15] I *D user_proj_example
-*CAP
-1 la_oenb[15] 0.00010579
-2 *419:la_oenb[15] 0.000615613
-3 *249:16 0.0143431
-4 *249:15 0.0137275
-5 *249:13 0.0256388
-6 *249:11 0.0257445
-7 *419:la_oenb[15] *276:19 0.0021236
-8 *249:13 *290:11 0
-9 *419:la_data_in[16] *419:la_oenb[15] 0.000441905
-10 *151:16 *249:16 0.056752
-11 *185:7 *419:la_oenb[15] 0.00144233
-12 *185:9 *419:la_oenb[15] 0.00203767
-*RES
-1 la_oenb[15] *249:11 1.395
-2 *249:11 *249:13 249.93
-3 *249:13 *249:15 4.5
-4 *249:15 *249:16 153.27
-5 *249:16 *419:la_oenb[15] 26.415
-*END
-
-*D_NET *250 0.0932115
-*CONN
-*P la_oenb[16] I
-*I *419:la_oenb[16] I *D user_proj_example
-*CAP
-1 la_oenb[16] 0.000218295
-2 *419:la_oenb[16] 0.00165005
-3 *250:19 0.00476849
-4 *250:18 0.00311844
-5 *250:16 0.0153844
-6 *250:15 0.0153844
-7 *250:13 0.0192678
-8 *250:11 0.0194861
-9 *250:19 *373:13 2.04586e-05
-10 *419:la_data_in[16] *419:la_oenb[16] 0
-11 *419:la_data_in[17] *419:la_oenb[16] 0.000918335
-12 *123:15 *250:11 1.87963e-05
-13 *123:19 *419:la_oenb[16] 0.000751853
-14 *123:19 *250:19 0.0068127
-15 *186:7 *419:la_oenb[16] 0.0054113
-*RES
-1 la_oenb[16] *250:11 2.475
-2 *250:11 *250:13 189.81
-3 *250:13 *250:15 4.5
-4 *250:15 *250:16 158.85
-5 *250:16 *250:18 4.5
-6 *250:18 *250:19 50.04
-7 *250:19 *419:la_oenb[16] 32.355
-*END
-
-*D_NET *251 0.392735
-*CONN
-*P la_oenb[17] I
-*I *419:la_oenb[17] I *D user_proj_example
-*CAP
-1 la_oenb[17] 0.000388948
-2 *419:la_oenb[17] 0.000309168
-3 *251:11 0.015399
-4 *251:10 0.0150898
-5 *251:8 0.00555972
-6 *251:7 0.00594866
-7 *419:la_data_in[17] *419:la_oenb[17] 0
-8 *419:la_data_in[17] *251:11 0.000199471
-9 *419:la_data_in[18] *419:la_oenb[17] 0.00117074
-10 *117:8 *251:8 0.0735462
-11 *134:8 *251:8 0.0990357
-12 *187:11 *419:la_oenb[17] 0.00332452
-13 *187:11 *251:11 4.91006e-05
-14 *187:13 *251:11 0.172527
-15 *248:24 *419:la_oenb[17] 0.000186509
-*RES
-1 la_oenb[17] *251:7 8.145
-2 *251:7 *251:8 167.67
-3 *251:8 *251:10 4.5
-4 *251:10 *251:11 261.45
-5 *251:11 *419:la_oenb[17] 16.695
-*END
-
-*D_NET *252 0.18696
-*CONN
-*P la_oenb[18] I
-*I *419:la_oenb[18] I *D user_proj_example
-*CAP
-1 la_oenb[18] 0.000166523
-2 *419:la_oenb[18] 0.000568329
-3 *252:26 0.00101885
-4 *252:16 0.0105306
-5 *252:15 0.0100801
-6 *252:13 0.0232026
-7 *252:11 0.0233691
-8 *419:la_data_in[18] *419:la_oenb[18] 0
-9 *419:la_data_in[19] *419:la_oenb[18] 0.000614525
-10 *39:10 *252:16 0.00786962
-11 *125:19 *252:26 0.0206836
-12 *188:7 *419:la_oenb[18] 0.00277214
-13 *188:9 *419:la_oenb[18] 0.000184127
-14 *188:9 *252:26 0.0206836
-15 *220:14 *252:16 0.0652158
-*RES
-1 la_oenb[18] *252:11 1.935
-2 *252:11 *252:13 228.33
-3 *252:13 *252:15 4.5
-4 *252:15 *252:16 172.53
-5 *252:16 *252:26 44.55
-6 *252:26 *419:la_oenb[18] 13.095
-*END
-
-*D_NET *253 0.191539
-*CONN
-*P la_oenb[19] I
-*I *419:la_oenb[19] I *D user_proj_example
-*CAP
-1 la_oenb[19] 0.000291157
-2 *419:la_oenb[19] 0.00132496
-3 *253:16 0.0119674
-4 *253:15 0.0106424
-5 *253:13 0.0250337
-6 *253:11 0.0253249
-7 la_data_out[19] *253:13 2.5829e-05
-8 *419:la_data_in[19] *419:la_oenb[19] 0
-9 *419:la_data_in[20] *419:la_oenb[19] 0.000918335
-10 *88:12 *253:13 0
-11 *162:16 *253:16 0
-12 *173:16 *253:16 0
-13 *189:7 *419:la_oenb[19] 0.00144233
-14 *189:9 *419:la_oenb[19] 0.00272508
-15 *196:12 *253:16 0.111843
-*RES
-1 la_oenb[19] *253:11 3.015
-2 *253:11 *253:13 244.89
-3 *253:13 *253:15 4.5
-4 *253:15 *253:16 177.57
-5 *253:16 *419:la_oenb[19] 31.455
-*END
-
-*D_NET *254 0.197297
-*CONN
-*P la_oenb[1] I
-*I *419:la_oenb[1] I *D user_proj_example
-*CAP
-1 la_oenb[1] 0.00372571
-2 *419:la_oenb[1] 0.00236403
-3 *254:19 0.0138834
-4 *254:18 0.0115193
-5 *254:16 0.00504569
-6 *254:15 0.00877139
-7 la_data_out[1] *254:15 0
-8 *419:la_data_in[2] *419:la_oenb[1] 0
-9 *107:10 *254:16 0
-10 *131:16 *254:16 0.00180292
-11 *137:13 *254:15 7.67196e-06
-12 *190:7 *419:la_oenb[1] 0.00312377
-13 *190:7 *254:19 0.140919
-14 *247:16 *254:16 0.00613407
-*RES
-1 la_oenb[1] *254:15 40.185
-2 *254:15 *254:16 62.01
-3 *254:16 *254:18 4.5
-4 *254:18 *254:19 206.64
-5 *254:19 *419:la_oenb[1] 32.715
-*END
-
-*D_NET *255 0.342102
-*CONN
-*P la_oenb[20] I
-*I *419:la_oenb[20] I *D user_proj_example
-*CAP
-1 la_oenb[20] 0.000673267
-2 *419:la_oenb[20] 0.000301165
-3 *255:11 0.0150767
-4 *255:10 0.0147756
-5 *255:8 0.0100876
-6 *255:7 0.0107608
-7 *255:8 *289:8 0.000783338
-8 *255:8 *292:8 0.00186502
-9 *255:8 *295:8 0.0602419
-10 *255:8 *306:8 0.0594961
-11 la_data_out[0] *255:11 0.00336339
-12 *419:la_data_in[20] *419:la_oenb[20] 0
-13 *419:la_data_in[20] *255:11 0.000199471
-14 *419:la_data_in[21] *419:la_oenb[20] 0.00127968
-15 *191:11 *419:la_oenb[20] 0.00332452
-16 *191:11 *255:11 4.91006e-05
-17 *191:13 *255:11 0.159638
-18 *248:24 *419:la_oenb[20] 0.000186509
-*RES
-1 la_oenb[20] *255:7 10.485
-2 *255:7 *255:8 187.11
-3 *255:8 *255:10 4.5
-4 *255:10 *255:11 259.11
-5 *255:11 *419:la_oenb[20] 16.695
-*END
-
-*D_NET *256 0.156739
-*CONN
-*P la_oenb[21] I
-*I *419:la_oenb[21] I *D user_proj_example
-*CAP
-1 la_oenb[21] 0.000218295
-2 *419:la_oenb[21] 0.0018232
-3 *256:21 0.00267924
-4 *256:16 0.0147497
-5 *256:15 0.0138937
-6 *256:13 0.0228634
-7 *256:11 0.0230817
-8 *256:16 *291:16 0.0551445
-9 *419:la_data_in[21] *419:la_oenb[21] 0
-10 *419:la_data_in[22] *419:la_oenb[21] 0.000504048
-11 *99:11 *256:13 0
-12 *108:11 *256:13 0
-13 *129:13 *256:11 1.87963e-05
-14 *192:7 *419:la_oenb[21] 0.00144233
-15 *192:9 *419:la_oenb[21] 0.00341249
-16 *192:9 *256:21 0.00982012
-17 *225:14 *256:16 0.00708727
-*RES
-1 la_oenb[21] *256:11 2.475
-2 *256:11 *256:13 225.45
-3 *256:13 *256:15 4.5
-4 *256:15 *256:16 191.43
-5 *256:16 *256:21 19.35
-6 *256:21 *419:la_oenb[21] 32.085
-*END
-
-*D_NET *257 0.104856
-*CONN
-*P la_oenb[22] I
-*I *419:la_oenb[22] I *D user_proj_example
-*CAP
-1 la_oenb[22] 0.00334189
-2 *419:la_oenb[22] 0.00097066
-3 *257:15 0.0109377
-4 *257:14 0.00996706
-5 *257:12 0.0165047
-6 *257:11 0.0165047
-7 *257:9 0.0126549
-8 *257:7 0.0159967
-9 *257:15 *419:la_oenb[31] 0.000797884
-10 *257:15 *267:19 0
-11 *257:15 *268:11 0
-12 *419:la_data_in[23] *419:la_oenb[22] 0.00119683
-13 *419:la_data_in[32] *257:15 0.00255732
-14 *99:14 *257:12 0
-15 *133:26 *419:la_oenb[22] 0.000746036
-16 *193:10 *419:la_oenb[22] 0.000756647
-17 *193:12 *419:la_oenb[22] 0
-18 *195:10 *419:la_oenb[22] 0.00173162
-19 *203:15 *257:15 0.000804022
-20 *246:16 *419:la_oenb[22] 0.00752188
-21 *248:24 *419:la_oenb[22] 0.00186509
-*RES
-1 la_oenb[22] *257:7 32.085
-2 *257:7 *257:9 125.64
-3 *257:9 *257:11 4.5
-4 *257:11 *257:12 174.33
-5 *257:12 *257:14 4.5
-6 *257:14 *257:15 108.63
-7 *257:15 *419:la_oenb[22] 38.655
-*END
-
-*D_NET *258 0.352731
-*CONN
-*P la_oenb[23] I
-*I *419:la_oenb[23] I *D user_proj_example
-*CAP
-1 la_oenb[23] 0.000804702
-2 *419:la_oenb[23] 0.000549266
-3 *258:11 0.0158592
-4 *258:10 0.0153099
-5 *258:8 0.0111204
-6 *258:7 0.0119251
-7 *258:8 *260:8 0.138948
-8 *258:8 *264:8 0
-9 *258:8 *298:8 0.000419646
-10 *258:8 *305:8 0
-11 la_data_out[1] *258:11 0
-12 *419:la_data_in[23] *258:11 0.000699683
-13 *419:la_data_in[24] *419:la_oenb[23] 0.00102932
-14 *126:7 *258:11 0
-15 *131:15 *258:7 0
-16 *131:19 *258:11 0.154728
-17 *194:15 *419:la_oenb[23] 0.00133748
-*RES
-1 la_oenb[23] *258:7 11.925
-2 *258:7 *258:8 206.55
-3 *258:8 *258:10 4.5
-4 *258:10 *258:11 252.81
-5 *258:11 *419:la_oenb[23] 21.6607
-*END
-
-*D_NET *259 0.291161
-*CONN
-*P la_oenb[24] I
-*I *419:la_oenb[24] I *D user_proj_example
-*CAP
-1 la_oenb[24] 0.000291157
-2 *419:la_oenb[24] 0.001253
-3 *259:16 0.00847509
-4 *259:15 0.00722209
-5 *259:13 0.0263692
-6 *259:11 0.0266603
-7 la_data_out[24] *259:13 2.5829e-05
-8 *419:la_data_in[24] *419:la_oenb[24] 0
-9 *419:la_data_in[25] *419:la_oenb[24] 0
-10 *133:16 *259:16 0.0866022
-11 *139:16 *259:16 0.133229
-12 *195:10 *419:la_oenb[24] 0.00103316
-*RES
-1 la_oenb[24] *259:11 3.015
-2 *259:11 *259:13 257.85
-3 *259:13 *259:15 4.5
-4 *259:15 *259:16 209.97
-5 *259:16 *419:la_oenb[24] 18.495
-*END
-
-*D_NET *260 0.479559
-*CONN
-*P la_oenb[25] I
-*I *419:la_oenb[25] I *D user_proj_example
-*CAP
-1 la_oenb[25] 0.000729427
-2 *419:la_oenb[25] 0.001044
-3 *260:11 0.0191253
-4 *260:10 0.0180813
-5 *260:8 0.00344568
-6 *260:7 0.00417511
-7 *260:8 *264:8 0
-8 *260:8 *271:8 0.13298
-9 *260:8 *298:8 0.00271989
-10 *419:la_data_in[25] *419:la_oenb[25] 3.45239e-06
-11 *419:la_data_in[26] *419:la_oenb[25] 0
-12 *137:13 *260:11 0.146627
-13 *196:11 *419:la_oenb[25] 0.00185966
-14 *196:11 *260:11 0.00963588
-15 *197:23 *260:7 0.000184127
-16 *258:8 *260:8 0.138948
-*RES
-1 la_oenb[25] *260:7 11.745
-2 *260:7 *260:8 219.51
-3 *260:8 *260:10 4.5
-4 *260:10 *260:11 251.55
-5 *260:11 *419:la_oenb[25] 23.0615
-*END
-
-*D_NET *261 0.420004
-*CONN
-*P la_oenb[26] I
-*I *419:la_oenb[26] I *D user_proj_example
-*CAP
-1 la_oenb[26] 0.00152228
-2 *419:la_oenb[26] 0.000566526
-3 *261:11 0.0102271
-4 *261:10 0.00966056
-5 *261:8 0.00944163
-6 *261:7 0.0109639
-7 *261:8 *282:8 0.12067
-8 *419:la_data_in[27] *419:la_oenb[26] 0.000537038
-9 *119:8 *261:8 0.0693187
-10 *134:11 *419:la_oenb[26] 0.000414286
-11 *134:11 *261:11 0.163812
-12 *197:17 *419:la_oenb[26] 0.00231387
-13 *197:17 *261:11 0.00210723
-14 *212:12 *261:8 0.0080199
-15 *246:11 *419:la_oenb[26] 0.00255732
-16 *246:11 *261:11 0.00787144
-*RES
-1 la_oenb[26] *261:7 18.945
-2 *261:7 *261:8 225.81
-3 *261:8 *261:10 4.5
-4 *261:10 *261:11 240.21
-5 *261:11 *419:la_oenb[26] 17.865
-*END
-
-*D_NET *262 0.269756
-*CONN
-*P la_oenb[27] I
-*I *419:la_oenb[27] I *D user_proj_example
-*CAP
-1 la_oenb[27] 0.00332303
-2 *419:la_oenb[27] 0.000702498
-3 *262:17 0.00182638
-4 *262:12 0.013671
-5 *262:11 0.0125471
-6 *262:9 0.0186216
-7 *262:7 0.0219447
-8 la_data_out[2] *262:17 0.0128275
-9 *419:la_data_in[27] *419:la_oenb[27] 0
-10 *419:la_data_in[28] *419:la_oenb[27] 0.0015881
-11 *419:la_data_in[28] *262:17 0
-12 *118:16 *262:12 0.0594963
-13 *135:15 *262:17 0.0155894
-14 *198:11 *419:la_oenb[27] 0.00296445
-15 *198:11 *262:17 0.00785609
-16 *236:16 *262:12 0.0967983
-17 *246:11 *262:17 0
-*RES
-1 la_oenb[27] *262:7 32.085
-2 *262:7 *262:9 185.22
-3 *262:9 *262:11 4.5
-4 *262:11 *262:12 231.93
-5 *262:12 *262:17 38.61
-6 *262:17 *419:la_oenb[27] 21.285
-*END
-
-*D_NET *263 0.269365
-*CONN
-*P la_oenb[28] I
-*I *419:la_oenb[28] I *D user_proj_example
-*CAP
-1 la_oenb[28] 0.000166523
-2 *419:la_oenb[28] 0.000736492
-3 *263:21 0.00263866
-4 *263:16 0.014692
-5 *263:15 0.0127898
-6 *263:13 0.0216513
-7 *263:11 0.0218178
-8 *263:16 *266:16 0.16046
-9 *419:la_data_in[29] *419:la_oenb[28] 0.00111883
-10 *136:19 *419:la_oenb[28] 0.000414286
-11 *136:19 *263:21 0.0274349
-12 *199:17 *419:la_oenb[28] 0.00231387
-13 *199:17 *263:21 0.00251641
-14 *199:23 *263:21 0.000613757
-*RES
-1 la_oenb[28] *263:11 1.935
-2 *263:11 *263:13 214.47
-3 *263:13 *263:15 4.5
-4 *263:15 *263:16 237.51
-5 *263:16 *263:21 45.54
-6 *263:21 *419:la_oenb[28] 17.055
-*END
-
-*D_NET *264 0.33917
-*CONN
-*P la_oenb[29] I
-*I *419:la_oenb[29] I *D user_proj_example
-*CAP
-1 la_oenb[29] 0.000966934
-2 *419:la_oenb[29] 0.00124737
-3 *264:11 0.0153057
-4 *264:10 0.0140583
-5 *264:8 0.0182203
-6 *264:7 0.0191872
-7 *264:8 *305:8 0.0363659
-8 *264:8 *310:14 0.0157274
-9 *419:la_data_in[29] *419:la_oenb[29] 0
-10 *419:la_data_in[30] *419:la_oenb[29] 0.0130815
-11 *419:la_data_in[30] *264:11 0.000821668
-12 *138:11 *264:11 0.137236
-13 *148:9 *264:11 0.00464001
-14 *200:7 *419:la_oenb[29] 0.00058307
-15 *246:8 *264:8 0.0617286
-16 *258:8 *264:8 0
-17 *260:8 *264:8 0
-*RES
-1 la_oenb[29] *264:7 13.545
-2 *264:7 *264:8 245.43
-3 *264:8 *264:10 4.5
-4 *264:10 *264:11 241.56
-5 *264:11 *419:la_oenb[29] 22.095
-*END
-
-*D_NET *265 0.116989
-*CONN
-*P la_oenb[2] I
-*I *419:la_oenb[2] I *D user_proj_example
-*CAP
-1 la_oenb[2] 0.000990251
-2 *419:la_oenb[2] 0.00107028
-3 *265:11 0.0231172
-4 *265:10 0.0220469
-5 *265:8 0.00308448
-6 *265:7 0.00407473
-7 *419:la_oenb[2] *419:la_oenb[3] 0.00153352
-8 *419:la_oenb[2] *419:la_oenb[7] 0.00379236
-9 *419:la_oenb[2] *401:10 0.00851682
-10 *265:8 *305:8 0.0347489
-11 *265:11 *419:la_oenb[9] 0.00161623
-12 *265:11 *306:11 0
-13 *419:la_data_in[10] *265:11 0.000103572
-14 *419:la_data_in[3] *419:la_oenb[2] 0.00123774
-15 *117:11 *265:11 0
-16 *180:9 *265:11 0
-17 *201:11 *419:la_oenb[2] 0.000417739
-18 *242:13 *265:11 0.00759218
-19 *246:8 *265:8 0.00304577
-*RES
-1 la_oenb[2] *265:7 13.545
-2 *265:7 *265:8 50.31
-3 *265:8 *265:10 4.5
-4 *265:10 *265:11 256.77
-5 *265:11 *419:la_oenb[2] 33.435
-*END
-
-*D_NET *266 0.387232
-*CONN
-*P la_oenb[30] I
-*I *419:la_oenb[30] I *D user_proj_example
-*CAP
-1 la_oenb[30] 0.00010579
-2 *419:la_oenb[30] 0.00039485
-3 *266:19 0.00430625
-4 *266:18 0.0039114
-5 *266:16 0.00483386
-6 *266:15 0.00483386
-7 *266:13 0.0216084
-8 *266:11 0.0217142
-9 *266:16 *278:16 0.153
-10 *419:la_data_in[31] *419:la_oenb[30] 0.000447532
-11 *132:8 *419:la_oenb[30] 0.000136773
-12 *195:13 *419:la_oenb[30] 0.00153439
-13 *202:15 *419:la_oenb[30] 0.0023957
-14 *202:15 *266:19 0.00754921
-15 *248:19 *266:19 0
-16 *263:16 *266:16 0.16046
-*RES
-1 la_oenb[30] *266:11 1.395
-2 *266:11 *266:13 214.29
-3 *266:13 *266:15 4.5
-4 *266:15 *266:16 251.19
-5 *266:16 *266:18 4.5
-6 *266:18 *266:19 45.81
-7 *266:19 *419:la_oenb[30] 21.645
-*END
-
-*D_NET *267 0.124386
-*CONN
-*P la_oenb[31] I
-*I *419:la_oenb[31] I *D user_proj_example
-*CAP
-1 la_oenb[31] 0.000218295
-2 *419:la_oenb[31] 0.000460428
-3 *267:19 0.0170763
-4 *267:18 0.0166159
-5 *267:16 0.0242796
-6 *267:15 0.0242796
-7 *267:13 0.00862731
-8 *267:11 0.00884561
-9 *419:la_data_in[31] *419:la_oenb[31] 0
-10 *419:la_data_in[31] *267:19 8.28572e-05
-11 *419:la_data_in[32] *419:la_oenb[31] 0.000400477
-12 *140:13 *267:11 1.87963e-05
-13 *195:13 *267:19 0
-14 *203:15 *419:la_oenb[31] 0.00666336
-15 *203:15 *267:19 0.0160191
-16 *257:15 *419:la_oenb[31] 0.000797884
-17 *257:15 *267:19 0
-*RES
-1 la_oenb[31] *267:11 2.475
-2 *267:11 *267:13 84.51
-3 *267:13 *267:15 4.5
-4 *267:15 *267:16 256.59
-5 *267:16 *267:18 4.5
-6 *267:18 *267:19 175.59
-7 *267:19 *419:la_oenb[31] 21.9307
-*END
-
-*D_NET *268 0.396907
-*CONN
-*P la_oenb[32] I
-*I *419:la_oenb[32] I *D user_proj_example
-*CAP
-1 la_oenb[32] 0.00177507
-2 *419:la_oenb[32] 0.000352449
-3 *268:11 0.014949
-4 *268:10 0.0145966
-5 *268:8 0.0145489
-6 *268:7 0.0163239
-7 *268:8 *300:14 0.128877
-8 *419:la_data_in[32] *268:11 0.000181058
-9 *419:la_data_in[33] *419:la_oenb[32] 0.00254709
-10 *132:8 *419:la_oenb[32] 0.000186509
-11 *141:19 *268:11 0.152887
-12 *176:8 *268:8 0.0202052
-13 *177:8 *268:8 0.0265464
-14 *204:9 *419:la_oenb[32] 0.00254709
-15 *205:11 *268:7 0.000383598
-16 *257:15 *268:11 0
-*RES
-1 la_oenb[32] *268:7 21.645
-2 *268:7 *268:8 264.87
-3 *268:8 *268:10 4.5
-4 *268:10 *268:11 242.91
-5 *268:11 *419:la_oenb[32] 21.555
-*END
-
-*D_NET *269 0.402658
-*CONN
-*P la_oenb[33] I
-*I *419:la_oenb[33] I *D user_proj_example
-*CAP
-1 la_oenb[33] 0.000166523
-2 *419:la_oenb[33] 0.000329373
-3 *269:24 0.00236862
-4 *269:16 0.00663301
-5 *269:15 0.00459377
-6 *269:13 0.0244923
-7 *269:11 0.0246589
-8 *269:24 *419:la_oenb[37] 0.00337566
-9 *269:24 *274:11 0
-10 la_data_out[33] *269:13 0
-11 *419:la_data_in[34] *419:la_oenb[33] 0.000403929
-12 *419:la_data_in[38] *269:24 2.07143e-05
-13 *133:26 *269:24 0.000124339
-14 *142:22 *269:24 0.00230028
-15 *147:19 *269:24 0
-16 *164:16 *269:16 0.149269
-17 *178:16 *269:16 0.0215729
-18 *193:12 *269:24 0
-19 *202:16 *269:16 0.157724
-20 *205:7 *419:la_oenb[33] 0.000210596
-21 *207:10 *269:24 0.00441406
-22 *210:13 *269:24 0
-*RES
-1 la_oenb[33] *269:11 1.935
-2 *269:11 *269:13 241.29
-3 *269:13 *269:15 4.5
-4 *269:15 *269:16 258.03
-5 *269:16 *269:24 49.14
-6 *269:24 *419:la_oenb[33] 5.265
-*END
-
-*D_NET *270 0.291203
-*CONN
-*P la_oenb[34] I
-*I *419:la_oenb[34] I *D user_proj_example
-*CAP
-1 la_oenb[34] 0.00233542
-2 *419:la_oenb[34] 0.000368571
-3 *270:19 0.0152515
-4 *270:18 0.0148829
-5 *270:16 0.0225746
-6 *270:15 0.02491
-7 *270:19 *287:15 0.000306879
-8 la_data_out[34] *270:15 2.5829e-05
-9 *419:la_data_in[35] *419:la_oenb[34] 0.00254709
-10 *120:16 *270:16 0.0597446
-11 *132:8 *419:la_oenb[34] 0.000186509
-12 *143:11 *270:19 0.145522
-13 *206:9 *419:la_oenb[34] 0.00254709
-*RES
-1 la_oenb[34] *270:15 27.225
-2 *270:15 *270:16 275.49
-3 *270:16 *270:18 4.5
-4 *270:18 *270:19 240.39
-5 *270:19 *419:la_oenb[34] 21.555
-*END
-
-*D_NET *271 0.395395
-*CONN
-*P la_oenb[35] I
-*I *419:la_oenb[35] I *D user_proj_example
-*CAP
-1 la_oenb[35] 0.000751504
-2 *419:la_oenb[35] 0.00403545
-3 *271:11 0.0268337
-4 *271:10 0.0227982
-5 *271:8 0.00708574
-6 *271:7 0.00783724
-7 *271:8 *274:8 0.190798
-8 *271:8 *298:8 0.00111905
-9 *271:8 *310:14 0
-10 *419:la_data_in[35] *419:la_oenb[35] 0
-11 *419:la_data_in[36] *419:la_oenb[35] 0
-12 *207:10 *419:la_oenb[35] 0.00115591
-13 *260:8 *271:8 0.13298
-*RES
-1 la_oenb[35] *271:7 11.565
-2 *271:7 *271:8 284.31
-3 *271:8 *271:10 4.5
-4 *271:10 *271:11 224.64
-5 *271:11 *419:la_oenb[35] 40.995
-*END
-
-*D_NET *272 0.401576
-*CONN
-*P la_oenb[36] I
-*I *419:la_oenb[36] I *D user_proj_example
-*CAP
-1 la_oenb[36] 0.00276732
-2 *419:la_oenb[36] 0.000354746
-3 *272:19 0.0161455
-4 *272:18 0.0157908
-5 *272:16 0.0144632
-6 *272:15 0.0172305
-7 *272:16 *286:16 0.153994
-8 *419:la_data_in[37] *419:la_oenb[36] 0.00254709
-9 *132:8 *419:la_oenb[36] 0.000186509
-10 *145:13 *272:15 1.87963e-05
-11 *184:10 *272:16 0.0578795
-12 *208:9 *419:la_oenb[36] 0.00254709
-13 *208:9 *272:19 0.002175
-14 *208:11 *272:19 0.1133
-15 *234:14 *272:16 0.00217594
-*RES
-1 la_oenb[36] *272:15 29.565
-2 *272:15 *272:16 288.99
-3 *272:16 *272:18 4.5
-4 *272:18 *272:19 237.51
-5 *272:19 *419:la_oenb[36] 21.555
-*END
-
-*D_NET *273 0.20035
-*CONN
-*P la_oenb[37] I
-*I *419:la_oenb[37] I *D user_proj_example
-*CAP
-1 la_oenb[37] 0.00313757
-2 *419:la_oenb[37] 0.00183898
-3 *273:11 0.0221776
-4 *273:10 0.0203386
-5 *273:8 0.0223954
-6 *273:7 0.025533
-7 *419:la_data_in[37] *419:la_oenb[37] 0
-8 *419:la_data_in[38] *419:la_oenb[37] 0
-9 *191:16 *273:8 0.0954299
-10 *208:9 *273:11 0
-11 *209:11 *419:la_oenb[37] 0.00612325
-12 *269:24 *419:la_oenb[37] 0.00337566
-*RES
-1 la_oenb[37] *273:7 34.965
-2 *273:7 *273:8 297.27
-3 *273:8 *273:10 4.5
-4 *273:10 *273:11 201.24
-5 *273:11 *419:la_oenb[37] 40.995
-*END
-
-*D_NET *274 0.589318
-*CONN
-*P la_oenb[38] I
-*I *419:la_oenb[38] I *D user_proj_example
-*CAP
-1 la_oenb[38] 0.000724101
-2 *419:la_oenb[38] 0.00134881
-3 *274:11 0.0170946
-4 *274:10 0.0157458
-5 *274:8 0.00456685
-6 *274:7 0.00529095
-7 *274:8 *275:8 0.207957
-8 *274:8 *298:8 0.000186509
-9 *274:8 *303:8 0.000261113
-10 *419:la_data_in[39] *419:la_oenb[38] 0.000876906
-11 *147:13 *274:7 0
-12 *147:19 *274:11 0.132633
-13 *158:13 *274:7 2.04586e-05
-14 *210:13 *419:la_oenb[38] 0.0118148
-15 *269:24 *274:11 0
-16 *271:8 *274:8 0.190798
-*RES
-1 la_oenb[38] *274:7 11.385
-2 *274:7 *274:8 303.75
-3 *274:8 *274:10 4.5
-4 *274:10 *274:11 239.67
-5 *274:11 *419:la_oenb[38] 35.3015
-*END
-
-*D_NET *275 0.525633
-*CONN
-*P la_oenb[39] I
-*I *419:la_oenb[39] I *D user_proj_example
-*CAP
-1 la_oenb[39] 0.000704132
-2 *419:la_oenb[39] 0.000354746
-3 *275:11 0.0218169
-4 *275:10 0.0214622
-5 *275:8 0.00368224
-6 *275:7 0.00438637
-7 *275:8 *289:8 0.191917
-8 *275:8 *303:8 0.00167858
-9 *275:8 *306:8 0.00346902
-10 *419:la_data_in[39] *275:11 9.20636e-06
-11 *419:la_data_in[40] *419:la_oenb[39] 0.00254709
-12 *132:8 *419:la_oenb[39] 0.000186509
-13 *158:8 *275:8 0.00615481
-14 *175:13 *275:11 0.0549313
-15 *211:9 *419:la_oenb[39] 0.00254709
-16 *211:9 *275:11 0.00182976
-17 *274:8 *275:8 0.207957
-*RES
-1 la_oenb[39] *275:7 11.205
-2 *275:7 *275:8 310.23
-3 *275:8 *275:10 4.5
-4 *275:10 *275:11 253.35
-5 *275:11 *419:la_oenb[39] 21.555
-*END
-
-*D_NET *276 0.108617
-*CONN
-*P la_oenb[3] I
-*I *419:la_oenb[3] I *D user_proj_example
-*CAP
-1 la_oenb[3] 0.00261964
-2 *419:la_oenb[3] 0.00180851
-3 *276:19 0.02241
-4 *276:18 0.0228955
-5 *276:15 0.00491363
-6 *419:la_oenb[3] *419:la_oenb[7] 0.00110662
-7 *419:la_oenb[3] *419:la_oenb[8] 0.000186509
-8 *419:la_oenb[3] *401:10 0.00665184
-9 *276:19 *373:13 0
-10 la_data_out[3] *276:15 0
-11 *419:la_data_in[10] *419:la_oenb[3] 0.000419646
-12 *419:la_data_in[12] *419:la_oenb[3] 0.000634086
-13 *419:la_data_in[16] *419:la_oenb[3] 0.000186509
-14 *419:la_data_in[16] *276:19 0.00014321
-15 *419:la_data_in[4] *419:la_oenb[3] 0.00131958
-16 *419:la_oenb[15] *276:19 0.0021236
-17 *419:la_oenb[2] *419:la_oenb[3] 0.00153352
-18 *122:19 *276:19 0
-19 *123:19 *276:19 0
-20 *184:10 *276:18 0.0290331
-21 *185:9 *276:19 0.00701524
-22 *186:7 *276:19 0
-23 *212:7 *419:la_oenb[3] 0.000445358
-24 *246:16 *419:la_oenb[3] 0.00124339
-25 *248:24 *419:la_oenb[3] 0.00192726
-*RES
-1 la_oenb[3] *276:15 29.385
-2 *276:15 *276:18 46.53
-3 *276:18 *276:19 242.55
-4 *276:19 *419:la_oenb[3] 47.295
-*END
-
-*D_NET *277 0.138476
-*CONN
-*P la_oenb[40] I
-*I *419:la_oenb[40] I *D user_proj_example
-*CAP
-1 la_oenb[40] 0.00010579
-2 *419:la_oenb[40] 0.000597498
-3 *277:19 0.0180327
-4 *277:18 0.0174352
-5 *277:16 0.0297488
-6 *277:15 0.0297488
-7 *277:13 0.00746908
-8 *277:11 0.00757487
-9 *419:la_data_in[40] *419:la_oenb[40] 0
-10 *419:la_data_in[40] *277:19 0.000266984
-11 *419:la_data_in[41] *419:la_oenb[40] 0
-12 *132:8 *419:la_oenb[40] 0.000186509
-13 *207:13 *419:la_oenb[40] 0.000822435
-14 *211:9 *277:19 0
-15 *213:15 *419:la_oenb[40] 0.00666336
-16 *213:15 *277:19 0.0198244
-*RES
-1 la_oenb[40] *277:11 1.395
-2 *277:11 *277:13 73.71
-3 *277:13 *277:15 4.5
-4 *277:15 *277:16 315.99
-5 *277:16 *277:18 4.5
-6 *277:18 *277:19 186.39
-7 *277:19 *419:la_oenb[40] 21.735
-*END
-
-*D_NET *278 0.26147
-*CONN
-*P la_oenb[41] I
-*I *419:la_oenb[41] I *D user_proj_example
-*CAP
-1 la_oenb[41] 0.000218295
-2 *419:la_oenb[41] 0.000354746
-3 *278:19 0.00430649
-4 *278:18 0.00395175
-5 *278:16 0.0210474
-6 *278:15 0.0210474
-7 *278:13 0.0215388
-8 *278:11 0.0217571
-9 *419:la_data_in[42] *419:la_oenb[41] 0.00254709
-10 *132:8 *419:la_oenb[41] 0.000186509
-11 *151:13 *278:11 1.87963e-05
-12 *207:13 *278:19 0
-13 *214:13 *419:la_oenb[41] 0.00254709
-14 *214:13 *278:19 0.00894935
-15 *266:16 *278:16 0.153
-*RES
-1 la_oenb[41] *278:11 2.475
-2 *278:11 *278:13 214.11
-3 *278:13 *278:15 4.5
-4 *278:15 *278:16 321.39
-5 *278:16 *278:18 4.5
-6 *278:18 *278:19 45.99
-7 *278:19 *419:la_oenb[41] 21.555
-*END
-
-*D_NET *279 0.190023
-*CONN
-*P la_oenb[42] I
-*I *419:la_oenb[42] I *D user_proj_example
-*CAP
-1 la_oenb[42] 0.00130956
-2 *419:la_oenb[42] 0.000354746
-3 *279:11 0.0245512
-4 *279:10 0.0241965
-5 *279:8 0.027336
-6 *279:7 0.0286456
-7 *419:la_data_in[42] *279:11 0.00035291
-8 *419:la_data_in[43] *419:la_oenb[42] 0.00254709
-9 *132:8 *419:la_oenb[42] 0.000186509
-10 *187:16 *279:8 0.0672048
-11 *215:13 *419:la_oenb[42] 0.00254709
-12 *215:13 *279:11 0.0107906
-*RES
-1 la_oenb[42] *279:7 16.065
-2 *279:7 *279:8 329.67
-3 *279:8 *279:10 4.5
-4 *279:10 *279:11 248.49
-5 *279:11 *419:la_oenb[42] 21.555
-*END
-
-*D_NET *280 0.134112
-*CONN
-*P la_oenb[43] I
-*I *419:la_oenb[43] I *D user_proj_example
-*CAP
-1 la_oenb[43] 0.000166523
-2 *419:la_oenb[43] 0.000354746
-3 *280:19 0.019261
-4 *280:18 0.0189063
-5 *280:16 0.0315903
-6 *280:15 0.0315903
-7 *280:13 0.00610461
-8 *280:11 0.00627113
-9 *419:la_data_in[43] *280:19 0.000359048
-10 *419:la_data_in[44] *419:la_oenb[43] 0.00254709
-11 *132:8 *419:la_oenb[43] 0.000186509
-12 *216:13 *419:la_oenb[43] 0.00254709
-13 *216:13 *280:19 0.0142277
-*RES
-1 la_oenb[43] *280:11 1.935
-2 *280:11 *280:13 60.21
-3 *280:13 *280:15 4.5
-4 *280:15 *280:16 334.89
-5 *280:16 *280:18 4.5
-6 *280:18 *280:19 199.89
-7 *280:19 *419:la_oenb[43] 21.555
-*END
-
-*D_NET *281 0.481709
-*CONN
-*P la_oenb[44] I
-*I *419:la_oenb[44] I *D user_proj_example
-*CAP
-1 la_oenb[44] 0.000291157
-2 *419:la_oenb[44] 0.00116057
-3 *281:21 0.00334269
-4 *281:16 0.00776877
-5 *281:15 0.00558665
-6 *281:13 0.0238344
-7 *281:11 0.0241256
-8 *419:la_oenb[44] *283:22 0.00341934
-9 la_data_out[44] *281:13 2.5829e-05
-10 *419:la_data_in[38] *419:la_oenb[44] 0
-11 *419:la_data_in[45] *419:la_oenb[44] 0.000224405
-12 *419:la_data_in[50] *281:21 0.000184127
-13 *133:26 *419:la_oenb[44] 0.00187752
-14 *150:16 *419:la_oenb[44] 0
-15 *211:10 *281:16 0.191296
-16 *215:14 *281:16 0.211812
-17 *217:13 *419:la_oenb[44] 0.000348691
-18 *222:11 *281:21 0.00205916
-19 *224:9 *281:21 0
-20 *228:16 *281:16 0.00435188
-*RES
-1 la_oenb[44] *281:11 3.015
-2 *281:11 *281:13 236.07
-3 *281:13 *281:15 4.5
-4 *281:15 *281:16 325.53
-5 *281:16 *281:21 37.89
-6 *281:21 *419:la_oenb[44] 24.435
-*END
-
-*D_NET *282 0.35671
-*CONN
-*P la_oenb[45] I
-*I *419:la_oenb[45] I *D user_proj_example
-*CAP
-1 la_oenb[45] 0.00147528
-2 *419:la_oenb[45] 0.000390713
-3 *282:11 0.016088
-4 *282:10 0.0156973
-5 *282:8 0.0259136
-6 *282:7 0.0273889
-7 *419:la_data_in[46] *419:la_oenb[45] 0.00254709
-8 *146:16 *419:la_oenb[45] 0.000310848
-9 *155:19 *282:11 0.143681
-10 *218:9 *419:la_oenb[45] 0.00254709
-11 *261:8 *282:8 0.12067
-*RES
-1 la_oenb[45] *282:7 18.765
-2 *282:7 *282:8 349.11
-3 *282:8 *282:10 4.5
-4 *282:10 *282:11 245.79
-5 *282:11 *419:la_oenb[45] 21.555
-*END
-
-*D_NET *283 0.50516
-*CONN
-*P la_oenb[46] I
-*I *419:la_oenb[46] I *D user_proj_example
-*CAP
-1 la_oenb[46] 0.000218295
-2 *419:la_oenb[46] 0.000568408
-3 *283:22 0.00371505
-4 *283:16 0.0101576
-5 *283:15 0.00701094
-6 *283:13 0.0235218
-7 *283:11 0.0237401
-8 *419:la_oenb[46] *284:11 2.07143e-05
-9 *283:22 *285:19 0
-10 *419:la_data_in[41] *419:la_oenb[46] 0
-11 *419:la_data_in[47] *419:la_oenb[46] 0.00111499
-12 *419:la_data_in[49] *283:22 0.00497143
-13 *419:la_data_in[50] *283:22 0
-14 *419:la_oenb[44] *283:22 0.00341934
-15 *150:16 *283:22 0
-16 *156:13 *283:11 1.87963e-05
-17 *178:13 *283:22 0
-18 *210:16 *283:16 0.187566
-19 *219:13 *419:la_oenb[46] 0
-20 *220:13 *419:la_oenb[46] 0
-21 *221:17 *283:22 0.000448043
-22 *222:11 *283:22 0
-23 *222:12 *283:16 0.238669
-*RES
-1 la_oenb[46] *283:11 2.475
-2 *283:11 *283:13 233.19
-3 *283:13 *283:15 4.5
-4 *283:15 *283:16 347.13
-5 *283:16 *283:22 45.54
-6 *283:22 *419:la_oenb[46] 11.655
-*END
-
-*D_NET *284 0.368441
-*CONN
-*P la_oenb[47] I
-*I *419:la_oenb[47] I *D user_proj_example
-*CAP
-1 la_oenb[47] 0.00229207
-2 *419:la_oenb[47] 0.000346686
-3 *284:11 0.0213534
-4 *284:10 0.0210067
-5 *284:8 0.0208198
-6 *284:7 0.0231119
-7 *284:8 *290:8 0.204476
-8 *419:la_data_in[48] *419:la_oenb[47] 0.00144233
-9 *419:la_oenb[46] *284:11 2.07143e-05
-10 *181:10 *284:8 0.0188371
-11 *220:13 *419:la_oenb[47] 0.00144233
-12 *220:13 *284:11 0.0248848
-13 *221:21 *284:7 0.000604551
-14 *241:17 *284:11 0.0278032
-*RES
-1 la_oenb[47] *284:7 29.565
-2 *284:7 *284:8 362.07
-3 *284:8 *284:10 4.5
-4 *284:10 *284:11 239.85
-5 *284:11 *419:la_oenb[47] 16.9689
-*END
-
-*D_NET *285 0.190521
-*CONN
-*P la_oenb[48] I
-*I *419:la_oenb[48] I *D user_proj_example
-*CAP
-1 la_oenb[48] 0.00439232
-2 *419:la_oenb[48] 0.000445715
-3 *285:19 0.0219883
-4 *285:18 0.0215426
-5 *285:16 0.0311188
-6 *285:15 0.0355111
-7 la_data_out[48] *285:15 0
-8 *419:la_data_in[48] *285:19 0.000610688
-9 *419:la_data_in[49] *419:la_oenb[48] 0.000571781
-10 *124:16 *285:16 0.0597446
-11 *221:17 *419:la_oenb[48] 0.000662325
-12 *221:17 *285:19 0.0139323
-13 *283:22 *285:19 0
-*RES
-1 la_oenb[48] *285:15 47.745
-2 *285:15 *285:16 367.29
-3 *285:16 *285:18 4.5
-4 *285:18 *285:19 223.47
-5 *285:19 *419:la_oenb[48] 17.1215
-*END
-
-*D_NET *286 0.292352
-*CONN
-*P la_oenb[49] I
-*I *419:la_oenb[49] I *D user_proj_example
-*CAP
-1 la_oenb[49] 0.00257408
-2 *419:la_oenb[49] 0.000816741
-3 *286:19 0.0254965
-4 *286:18 0.0246798
-5 *286:16 0.023159
-6 *286:15 0.0257331
-7 *419:la_oenb[49] *419:la_oenb[50] 0.000534918
-8 *419:la_oenb[49] *419:la_oenb[55] 0
-9 *419:la_oenb[49] *290:14 0.0149825
-10 *419:la_oenb[49] *294:16 0.00752232
-11 *286:19 *300:17 0
-12 la_data_out[49] *286:15 2.5829e-05
-13 *419:la_data_in[47] *419:la_oenb[49] 0.00064242
-14 *419:la_data_in[50] *419:la_oenb[49] 0.00119683
-15 *419:la_data_in[61] *286:19 0.00073344
-16 *133:24 *419:la_oenb[49] 5.43985e-05
-17 *142:22 *419:la_oenb[49] 0.000663069
-18 *219:13 *419:la_oenb[49] 0.00913896
-19 *222:11 *419:la_oenb[49] 0.000403929
-20 *235:9 *286:19 0
-21 *236:11 *286:19 0
-22 *272:16 *286:16 0.153994
-*RES
-1 la_oenb[49] *286:15 29.925
-2 *286:15 *286:16 341.73
-3 *286:16 *286:18 4.5
-4 *286:18 *286:19 243.63
-5 *286:19 *419:la_oenb[49] 44.055
-*END
-
-*D_NET *287 0.377699
-*CONN
-*P la_oenb[4] I
-*I *419:la_oenb[4] I *D user_proj_example
-*CAP
-1 la_oenb[4] 0.00240104
-2 *419:la_oenb[4] 0.000783713
-3 *287:19 0.00368581
-4 *287:18 0.00290209
-5 *287:16 0.00549356
-6 *287:15 0.0078946
-7 *419:la_oenb[4] *298:11 0
-8 *287:19 wbs_dat_o[27] 0.000343704
-9 la_data_out[4] *287:15 1.87963e-05
-10 *419:la_data_in[5] *419:la_oenb[4] 0.00111883
-11 *120:16 *287:16 0.0392289
-12 *170:11 *419:la_oenb[4] 0.000400477
-13 *170:11 *287:19 0.160129
-14 *223:17 *419:la_oenb[4] 0.00231387
-15 *223:17 *287:19 0.00251641
-16 *223:21 *287:19 0.148161
-17 *270:19 *287:15 0.000306879
-*RES
-1 la_oenb[4] *287:15 27.405
-2 *287:15 *287:16 81.09
-3 *287:16 *287:18 4.5
-4 *287:18 *287:19 234.81
-5 *287:19 *419:la_oenb[4] 17.685
-*END
-
-*D_NET *288 0.541614
-*CONN
-*P la_oenb[50] I
-*I *419:la_oenb[50] I *D user_proj_example
-*CAP
-1 la_oenb[50] 0.00010579
-2 *419:la_oenb[50] 0.000474052
-3 *288:25 0.00309349
-4 *288:16 0.00965882
-5 *288:15 0.00703938
-6 *288:13 0.0232317
-7 *288:11 0.0233375
-8 *419:la_oenb[50] *290:14 0.000360584
-9 *288:25 *419:la_oenb[53] 0.000184127
-10 *288:25 *292:11 0
-11 *419:la_data_in[47] *419:la_oenb[50] 2.07232e-05
-12 *419:la_data_in[51] *419:la_oenb[50] 0.00103316
-13 *419:la_data_in[54] *288:25 0.000392805
-14 *419:la_oenb[49] *419:la_oenb[50] 0.000534918
-15 *144:16 *419:la_oenb[50] 0.00553311
-16 *216:14 *288:16 0.209947
-17 *224:9 *419:la_oenb[50] 0
-18 *227:5 *288:25 0.00295294
-19 *229:10 *288:16 0.253715
-*RES
-1 la_oenb[50] *288:11 1.395
-2 *288:11 *288:13 230.67
-3 *288:13 *288:15 4.5
-4 *288:15 *288:16 371.43
-5 *288:16 *288:25 45.45
-6 *288:25 *419:la_oenb[50] 17.055
-*END
-
-*D_NET *289 0.576735
-*CONN
-*P la_oenb[51] I
-*I *419:la_oenb[51] I *D user_proj_example
-*CAP
-1 la_oenb[51] 0.000469055
-2 *419:la_oenb[51] 0.000348149
-3 *289:11 0.0249639
-4 *289:10 0.0246157
-5 *289:8 0.0050796
-6 *289:7 0.00554866
-7 *289:8 *292:8 0.262417
-8 *289:8 *306:8 0.000559527
-9 *419:la_data_in[47] *289:11 0
-10 *419:la_data_in[51] *289:11 0.000187196
-11 *419:la_data_in[52] *419:la_oenb[51] 0.00144233
-12 *158:8 *289:8 0.0197283
-13 *162:13 *289:7 0.000500596
-14 *172:8 *289:8 0.00976066
-15 *225:11 *419:la_oenb[51] 0.00144233
-16 *225:11 *289:11 0.0269716
-17 *255:8 *289:8 0.000783338
-18 *275:8 *289:8 0.191917
-*RES
-1 la_oenb[51] *289:7 11.025
-2 *289:7 *289:8 387.99
-3 *289:8 *289:10 4.5
-4 *289:10 *289:11 258.39
-5 *289:11 *419:la_oenb[51] 16.9689
-*END
-
-*D_NET *290 0.356177
-*CONN
-*P la_oenb[52] I
-*I *419:la_oenb[52] I *D user_proj_example
-*CAP
-1 la_oenb[52] 0.00257317
-2 *419:la_oenb[52] 0.00034434
-3 *290:14 0.00117245
-4 *290:13 0.000828109
-5 *290:11 0.0245188
-6 *290:10 0.0245188
-7 *290:8 0.0200688
-8 *290:7 0.022642
-9 *290:14 *419:la_oenb[53] 0.0055744
-10 *290:14 *294:16 0.00246606
-11 *290:14 *301:20 0.0168479
-12 *290:14 *310:8 0.0131177
-13 la_data_out[15] *290:11 0.000510953
-14 *419:la_data_in[53] *419:la_oenb[52] 0.00115591
-15 *419:la_oenb[49] *290:14 0.0149825
-16 *419:la_oenb[50] *290:14 0.000360584
-17 *144:16 *290:14 1.81328e-05
-18 *226:7 *419:la_oenb[52] 0
-19 *249:13 *290:11 0
-20 *284:8 *290:8 0.204476
-*RES
-1 la_oenb[52] *290:7 29.745
-2 *290:7 *290:8 341.91
-3 *290:8 *290:10 4.5
-4 *290:10 *290:11 240.93
-5 *290:11 *290:13 4.5
-6 *290:13 *290:14 51.39
-7 *290:14 *419:la_oenb[52] 9.585
-*END
-
-*D_NET *291 0.405326
-*CONN
-*P la_oenb[53] I
-*I *419:la_oenb[53] I *D user_proj_example
-*CAP
-1 la_oenb[53] 0.000166523
-2 *419:la_oenb[53] 0.000684452
-3 *291:23 0.00499857
-4 *291:16 0.020644
-5 *291:15 0.0163298
-6 *291:13 0.0226408
-7 *291:11 0.0228073
-8 *291:23 *419:la_oenb[62] 0.000184127
-9 *291:23 *302:19 0
-10 *419:la_data_in[54] *419:la_oenb[53] 0.00107408
-11 *419:la_data_in[63] *291:23 0.000214815
-12 *144:16 *419:la_oenb[53] 0.0055744
-13 *225:14 *291:16 0.243519
-14 *227:5 *419:la_oenb[53] 0.000341786
-15 *233:10 *291:16 0.00497357
-16 *237:7 *291:23 0.000270053
-17 *256:16 *291:16 0.0551445
-18 *288:25 *419:la_oenb[53] 0.000184127
-19 *290:14 *419:la_oenb[53] 0.0055744
-*RES
-1 la_oenb[53] *291:11 1.935
-2 *291:11 *291:13 225.27
-3 *291:13 *291:15 4.5
-4 *291:15 *291:16 374.13
-5 *291:16 *291:23 46.17
-6 *291:23 *419:la_oenb[53] 37.935
-*END
-
-*D_NET *292 0.736984
-*CONN
-*P la_oenb[54] I
-*I *419:la_oenb[54] I *D user_proj_example
-*CAP
-1 la_oenb[54] 0.00071339
-2 *419:la_oenb[54] 0.000391578
-3 *292:11 0.0169028
-4 *292:10 0.0165113
-5 *292:8 0.00471127
-6 *292:7 0.00542467
-7 *292:8 *295:8 0.275846
-8 la_data_out[10] *292:11 0.00435768
-9 *419:la_data_in[54] *292:11 4.60318e-05
-10 *419:la_data_in[55] *419:la_oenb[54] 0.00144233
-11 *133:24 *419:la_oenb[54] 0.000310848
-12 *150:16 *419:la_oenb[54] 0
-13 *165:11 *292:11 0.137911
-14 *172:8 *292:8 0.00634127
-15 *219:13 *419:la_oenb[54] 0.000225045
-16 *228:15 *419:la_oenb[54] 0.000257394
-17 *228:15 *292:11 0.00130935
-18 *255:8 *292:8 0.00186502
-19 *288:25 *292:11 0
-20 *289:8 *292:8 0.262417
-*RES
-1 la_oenb[54] *292:7 10.845
-2 *292:7 *292:8 407.43
-3 *292:8 *292:10 4.5
-4 *292:10 *292:11 258.57
-5 *292:11 *419:la_oenb[54] 16.695
-*END
-
-*D_NET *293 0.610674
-*CONN
-*P la_oenb[55] I
-*I *419:la_oenb[55] I *D user_proj_example
-*CAP
-1 la_oenb[55] 0.00010579
-2 *419:la_oenb[55] 0.000773579
-3 *293:19 0.00502889
-4 *293:16 0.0101115
-5 *293:15 0.00585619
-6 *293:13 0.0223229
-7 *293:11 0.0224287
-8 *419:la_oenb[55] *294:16 3.10849e-06
-9 *293:19 *295:11 0
-10 *419:la_data_in[56] *419:la_oenb[55] 0.000452263
-11 *419:la_data_in[57] *293:19 0.000715027
-12 *419:la_oenb[49] *419:la_oenb[55] 0
-13 *108:14 *293:16 0
-14 *133:24 *419:la_oenb[55] 0.00020538
-15 *142:21 *419:la_oenb[55] 0.000675133
-16 *150:16 *419:la_oenb[55] 0
-17 *226:10 *293:16 0.26217
-18 *229:9 *419:la_oenb[55] 0
-19 *230:7 *293:19 0
-20 *232:10 *293:16 0.279826
-*RES
-1 la_oenb[55] *293:11 1.395
-2 *293:11 *293:13 222.39
-3 *293:13 *293:15 4.5
-4 *293:15 *293:16 409.23
-5 *293:16 *293:19 46.89
-6 *293:19 *419:la_oenb[55] 18.315
-*END
-
-*D_NET *294 0.470277
-*CONN
-*P la_oenb[56] I
-*I *419:la_oenb[56] I *D user_proj_example
-*CAP
-1 la_oenb[56] 0.000218295
-2 *419:la_oenb[56] 0.000376839
-3 *294:16 0.0118024
-4 *294:15 0.0114255
-5 *294:13 0.0267368
-6 *294:11 0.0269551
-7 *294:16 *296:16 0.284551
-8 *294:16 *310:8 0.0877215
-9 *419:la_data_in[57] *419:la_oenb[56] 0.00123774
-10 *419:la_oenb[49] *294:16 0.00752232
-11 *419:la_oenb[55] *294:16 3.10849e-06
-12 *33:9 *294:16 0.00648742
-13 *144:16 *294:16 0.00275412
-14 *167:13 *294:11 1.87963e-05
-15 *217:14 *294:16 0
-16 *230:7 *419:la_oenb[56] 0
-17 *290:14 *294:16 0.00246606
-*RES
-1 la_oenb[56] *294:11 2.475
-2 *294:11 *294:13 265.77
-3 *294:13 *294:15 4.5
-4 *294:15 *294:16 417.33
-5 *294:16 *419:la_oenb[56] 9.945
-*END
-
-*D_NET *295 0.476876
-*CONN
-*P la_oenb[57] I
-*I *419:la_oenb[57] I *D user_proj_example
-*CAP
-1 la_oenb[57] 0.000633074
-2 *419:la_oenb[57] 0.000761337
-3 *295:11 0.0277287
-4 *295:10 0.0269673
-5 *295:8 0.0185906
-6 *295:7 0.0192237
-7 la_data_out[11] *295:11 0.013073
-8 la_data_out[26] *295:8 0.00391659
-9 la_data_out[32] *295:8 0.00105689
-10 la_data_out[33] *295:8 0.00354368
-11 la_data_out[58] *295:8 0.00304632
-12 *419:la_data_in[58] *419:la_oenb[57] 0
-13 *121:8 *419:la_oenb[57] 0.000683535
-14 *154:10 *295:8 0.00105689
-15 *160:10 *295:8 0.00105689
-16 *172:8 *295:8 0.00319545
-17 *231:15 *419:la_oenb[57] 0.00178194
-18 *231:15 *295:11 0.0144724
-19 *232:7 *419:la_oenb[57] 0
-20 *255:8 *295:8 0.0602419
-21 *292:8 *295:8 0.275846
-22 *293:19 *295:11 0
-*RES
-1 la_oenb[57] *295:7 10.665
-2 *295:7 *295:8 426.87
-3 *295:8 *295:10 4.5
-4 *295:10 *295:11 256.59
-5 *295:11 *419:la_oenb[57] 18.945
-*END
-
-*D_NET *296 0.645735
-*CONN
-*P la_oenb[58] I
-*I *419:la_oenb[58] I *D user_proj_example
-*CAP
-1 la_oenb[58] 0.000167461
-2 *419:la_oenb[58] 0.000398924
-3 *296:16 0.0061703
-4 *296:15 0.00577138
-5 *296:13 0.0296584
-6 *296:11 0.0298258
-7 *296:16 *419:la_oenb[61] 9.97306e-05
-8 *296:16 *308:8 0.287659
-9 la_data_out[58] *296:13 0
-10 *419:la_data_in[59] *419:la_oenb[58] 0.00127866
-11 *419:la_data_in[60] *296:16 0.000154129
-12 *419:la_data_in[62] *296:16 0
-13 *33:9 *296:16 0
-14 *232:7 *419:la_oenb[58] 0
-15 *294:16 *296:16 0.284551
-*RES
-1 la_oenb[58] *296:11 1.935
-2 *296:11 *296:13 265.59
-3 *296:13 *296:15 4.5
-4 *296:15 *296:16 430.83
-5 *296:16 *419:la_oenb[58] 10.125
-*END
-
-*D_NET *297 0.28677
-*CONN
-*P la_oenb[59] I
-*I *419:la_oenb[59] I *D user_proj_example
-*CAP
-1 la_oenb[59] 0.000291157
-2 *419:la_oenb[59] 0.000862799
-3 *297:16 0.0310945
-4 *297:15 0.0302317
-5 *297:13 0.0258269
-6 *297:11 0.026118
-7 la_data_out[59] *297:13 2.5829e-05
-8 *419:la_data_in[60] *419:la_oenb[59] 0.00153363
-9 *158:18 *297:16 0.170159
-10 *233:7 *419:la_oenb[59] 0.000626544
-*RES
-1 la_oenb[59] *297:11 3.015
-2 *297:11 *297:13 257.31
-3 *297:13 *297:15 4.5
-4 *297:15 *297:16 436.77
-5 *297:16 *419:la_oenb[59] 19.035
-*END
-
-*D_NET *298 0.289203
-*CONN
-*P la_oenb[5] I
-*I *419:la_oenb[5] I *D user_proj_example
-*CAP
-1 la_oenb[5] 0.000703768
-2 *419:la_oenb[5] 0.00041151
-3 *298:11 0.0154172
-4 *298:10 0.0150057
-5 *298:8 0.00220081
-6 *298:7 0.00290458
-7 *298:8 *303:8 0.0602422
-8 *298:8 *337:15 0.000621697
-9 *298:8 *340:8 0.0198321
-10 *298:11 *336:10 3.37566e-05
-11 *419:la_data_in[5] *298:11 8.28572e-05
-12 *419:la_data_in[6] *419:la_oenb[5] 0.00201517
-13 *419:la_oenb[4] *298:11 0
-14 *234:9 *419:la_oenb[5] 0.00152417
-15 *234:11 *419:la_oenb[5] 7.36509e-05
-16 *234:11 *298:11 0.163689
-17 *258:8 *298:8 0.000419646
-18 *260:8 *298:8 0.00271989
-19 *271:8 *298:8 0.00111905
-20 *274:8 *298:8 0.000186509
-*RES
-1 la_oenb[5] *298:7 11.025
-2 *298:7 *298:8 89.91
-3 *298:8 *298:10 4.5
-4 *298:10 *298:11 255.87
-5 *298:11 *419:la_oenb[5] 19.4889
-*END
-
-*D_NET *299 0.147175
-*CONN
-*P la_oenb[60] I
-*I *419:la_oenb[60] I *D user_proj_example
-*CAP
-1 la_oenb[60] 0.00116776
-2 *419:la_oenb[60] 9.91926e-05
-3 *299:14 0.0387947
-4 *299:13 0.0386955
-5 *299:11 0.026338
-6 *299:10 0.0275058
-7 *299:10 *308:11 0.000184127
-8 *299:10 *310:14 0
-9 *419:la_data_in[61] *419:la_oenb[60] 0.000378484
-10 *154:14 *299:14 0
-11 *168:16 *299:14 0
-12 *171:5 *299:11 0
-13 *172:8 *299:10 0.000770645
-14 *200:8 *299:14 0.0120783
-15 *205:8 *299:14 0.00116255
-16 *235:9 *419:la_oenb[60] 0
-*RES
-1 la_oenb[60] *299:10 24.075
-2 *299:10 *299:11 262.17
-3 *299:11 *299:13 4.5
-4 *299:13 *299:14 437.49
-5 *299:14 *419:la_oenb[60] 6.165
-*END
-
-*D_NET *300 0.391517
-*CONN
-*P la_oenb[61] I
-*I *419:la_oenb[61] I *D user_proj_example
-*CAP
-1 la_oenb[61] 0.00178378
-2 *419:la_oenb[61] 0.000356512
-3 *300:17 0.0148878
-4 *300:16 0.0145313
-5 *300:14 0.0350244
-6 *300:13 0.0368082
-7 *300:13 user_irq[0] 0.000683829
-8 la_data_out[12] *300:17 0.138157
-9 *419:la_data_in[62] *419:la_oenb[61] 0.000698442
-10 *419:la_data_in[62] *300:17 0.0119683
-11 *173:13 *300:13 0.000500596
-12 *236:11 *419:la_oenb[61] 0.000695848
-13 *236:11 *300:17 0.000184127
-14 *236:13 *300:17 0.00626033
-15 *236:19 *300:13 0
-16 *268:8 *300:14 0.128877
-17 *286:19 *300:17 0
-18 *296:16 *419:la_oenb[61] 9.97306e-05
-*RES
-1 la_oenb[61] *300:13 33.525
-2 *300:13 *300:14 449.91
-3 *300:14 *300:16 4.5
-4 *300:16 *300:17 247.95
-5 *300:17 *419:la_oenb[61] 16.785
-*END
-
-*D_NET *301 0.641032
-*CONN
-*P la_oenb[62] I
-*I *419:la_oenb[62] I *D user_proj_example
-*CAP
-1 la_oenb[62] 0.00323696
-2 *419:la_oenb[62] 0.000372926
-3 *301:20 0.00125744
-4 *301:12 0.00775841
-5 *301:11 0.0068739
-6 *301:9 0.0231519
-7 *301:7 0.0263889
-8 *301:20 *310:8 0.00120195
-9 *419:la_data_in[63] *419:la_oenb[62] 0.00037631
-10 *144:16 *301:20 0.00340688
-11 *166:16 *301:12 0.252969
-12 *237:7 *419:la_oenb[62] 0
-13 *238:13 *301:20 0.00113978
-14 *238:14 *301:12 0.295866
-15 *290:14 *301:20 0.0168479
-16 *291:23 *419:la_oenb[62] 0.000184127
-*RES
-1 la_oenb[62] *301:7 32.085
-2 *301:7 *301:9 231.12
-3 *301:9 *301:11 4.5
-4 *301:11 *301:12 428.31
-5 *301:12 *301:20 46.62
-6 *301:20 *419:la_oenb[62] 4.905
-*END
-
-*D_NET *302 0.166635
-*CONN
-*P la_oenb[63] I
-*I *419:la_oenb[63] I *D user_proj_example
-*CAP
-1 la_oenb[63] 0.00296767
-2 *419:la_oenb[63] 0.00341248
-3 *302:19 0.0250251
-4 *302:18 0.0216126
-5 *302:16 0.0426542
-6 *302:15 0.0456218
-7 *419:la_oenb[63] *308:7 0
-8 *419:la_data_in[63] *419:la_oenb[63] 0
-9 *77:15 *302:16 0
-10 *123:16 *302:16 0.0243083
-11 *238:13 *419:la_oenb[63] 0.00103316
-12 *291:23 *302:19 0
-*RES
-1 la_oenb[63] *302:15 34.245
-2 *302:15 *302:16 464.49
-3 *302:16 *302:18 4.5
-4 *302:18 *302:19 212.04
-5 *302:19 *419:la_oenb[63] 32.895
-*END
-
-*D_NET *303 0.330489
-*CONN
-*P la_oenb[6] I
-*I *419:la_oenb[6] I *D user_proj_example
-*CAP
-1 la_oenb[6] 0.000680082
-2 *419:la_oenb[6] 0.000478609
-3 *303:11 0.014891
-4 *303:10 0.0144124
-5 *303:8 0.00114005
-6 *303:7 0.00182014
-7 *303:8 *306:8 0.0609882
-8 *303:8 *337:15 0.00528443
-9 *303:11 *336:10 0
-10 *419:la_data_in[6] *303:11 0.000687408
-11 *419:la_data_in[7] *419:la_oenb[6] 0.00129412
-12 *176:11 *303:11 0.165162
-13 *239:11 *419:la_oenb[6] 0.000686897
-14 *239:13 *419:la_oenb[6] 0.000699683
-15 *239:13 *303:11 8.18344e-05
-16 *274:8 *303:8 0.000261113
-17 *275:8 *303:8 0.00167858
-18 *298:8 *303:8 0.0602422
-*RES
-1 la_oenb[6] *303:7 10.845
-2 *303:7 *303:8 96.39
-3 *303:8 *303:10 4.5
-4 *303:10 *303:11 253.53
-5 *303:11 *419:la_oenb[6] 22.0207
-*END
-
-*D_NET *304 0.156223
-*CONN
-*P la_oenb[7] I
-*I *419:la_oenb[7] I *D user_proj_example
-*CAP
-1 la_oenb[7] 0.00129924
-2 *419:la_oenb[7] 0.00118481
-3 *304:11 0.018873
-4 *304:10 0.0176882
-5 *304:8 0.00348657
-6 *304:7 0.00478581
-7 *304:11 wbs_dat_o[31] 1.53439e-05
-8 *419:la_data_in[18] *304:11 0.00597391
-9 *419:la_data_in[8] *419:la_oenb[7] 0.00119683
-10 *419:la_oenb[2] *419:la_oenb[7] 0.00379236
-11 *419:la_oenb[3] *419:la_oenb[7] 0.00110662
-12 *124:19 *304:11 0.0152112
-13 *125:19 *304:11 0
-14 *126:8 *304:8 0.0092633
-15 *182:10 *419:la_oenb[7] 0.0100093
-16 *187:13 *304:11 0.00100656
-17 *187:16 *304:8 0.0515384
-18 *188:7 *304:11 0
-19 *240:5 *419:la_oenb[7] 0.000403929
-20 *246:16 *419:la_oenb[7] 0.00938764
-*RES
-1 la_oenb[7] *304:7 16.425
-2 *304:7 *304:8 74.61
-3 *304:8 *304:10 4.5
-4 *304:10 *304:11 254.07
-5 *304:11 *419:la_oenb[7] 41.355
-*END
-
-*D_NET *305 0.259978
-*CONN
-*P la_oenb[8] I
-*I *419:la_oenb[8] I *D user_proj_example
-*CAP
-1 la_oenb[8] 0.000966565
-2 *419:la_oenb[8] 0.000235988
-3 *305:11 0.0171015
-4 *305:10 0.0168655
-5 *305:8 0.00681213
-6 *305:7 0.0077787
-7 *305:8 *339:13 0
-8 *305:8 *402:20 0
-9 *419:la_data_in[8] *305:11 8.28572e-05
-10 *419:la_data_in[9] *419:la_oenb[8] 0.00144233
-11 *419:la_oenb[3] *419:la_oenb[8] 0.000186509
-12 *178:13 *305:7 0
-13 *241:9 *419:la_oenb[8] 0.00144233
-14 *241:9 *305:11 5.52382e-05
-15 *241:11 *305:11 0.135333
-16 *246:8 *305:8 0.00055949
-17 *258:8 *305:8 0
-18 *264:8 *305:8 0.0363659
-19 *265:8 *305:8 0.0347489
-*RES
-1 la_oenb[8] *305:7 13.365
-2 *305:7 *305:8 109.35
-3 *305:8 *305:10 4.5
-4 *305:10 *305:11 256.05
-5 *305:11 *419:la_oenb[8] 16.695
-*END
-
-*D_NET *306 0.319944
-*CONN
-*P la_oenb[9] I
-*I *419:la_oenb[9] I *D user_proj_example
-*CAP
-1 la_oenb[9] 0.000656396
-2 *419:la_oenb[9] 0.000644021
-3 *306:11 0.0159234
-4 *306:10 0.0152794
-5 *306:8 0.002737
-6 *306:7 0.00339339
-7 *306:11 *337:15 1.22751e-05
-8 *419:la_data_in[10] *419:la_oenb[9] 0
-9 *419:la_data_in[9] *306:11 0.000604551
-10 *242:11 *419:la_oenb[9] 0.0026412
-11 *242:13 *419:la_oenb[9] 1.79013e-05
-12 *242:13 *306:11 0.151905
-13 *255:8 *306:8 0.0594961
-14 *265:11 *419:la_oenb[9] 0.00161623
-15 *265:11 *306:11 0
-16 *275:8 *306:8 0.00346902
-17 *289:8 *306:8 0.000559527
-18 *303:8 *306:8 0.0609882
-*RES
-1 la_oenb[9] *306:7 10.665
-2 *306:7 *306:8 115.83
-3 *306:8 *306:10 4.5
-4 *306:10 *306:11 252.63
-5 *306:11 *419:la_oenb[9] 23.1007
-*END
-
-*D_NET *308 0.396119
-*CONN
-*P user_irq[0] O
-*I *419:irq[0] O *D user_proj_example
-*CAP
-1 user_irq[0] 0.00339766
-2 *419:irq[0] 0.000437504
-3 *308:11 0.0293714
-4 *308:10 0.0259737
-5 *308:8 0.0231042
-6 *308:7 0.0235417
-7 user_irq[0] *309:13 0.000613118
-8 *308:7 *309:9 0.000791747
-9 *419:la_oenb[63] *308:7 0
-10 *33:9 *308:8 0
-11 *172:8 user_irq[0] 0.000360562
-12 *296:16 *308:8 0.287659
-13 *299:10 *308:11 0.000184127
-14 *300:13 user_irq[0] 0.000683829
-*RES
-1 *419:irq[0] *308:7 10.305
-2 *308:7 *308:8 436.59
-3 *308:8 *308:10 4.5
-4 *308:10 *308:11 259.29
-5 *308:11 user_irq[0] 48.375
-*END
-
-*D_NET *309 0.376726
-*CONN
-*P user_irq[1] O
-*I *419:irq[1] O *D user_proj_example
-*CAP
-1 user_irq[1] 0.000291157
-2 *419:irq[1] 0.00434033
-3 *309:13 0.023162
-4 *309:12 0.0228708
-5 *309:10 0.0282027
-6 *309:9 0.032543
-7 *309:9 *310:7 0
-8 user_irq[0] *309:13 0.000613118
-9 *229:10 *309:10 0.263911
-10 *308:7 *309:9 0.000791747
-*RES
-1 *419:irq[1] *309:9 45.855
-2 *309:9 *309:10 469.89
-3 *309:10 *309:12 4.5
-4 *309:12 *309:13 230.31
-5 *309:13 user_irq[1] 3.015
-*END
-
-*D_NET *310 0.256525
-*CONN
-*P user_irq[2] O
-*I *419:irq[2] O *D user_proj_example
-*CAP
-1 user_irq[2] 0.000908262
-2 *419:irq[2] 0.000594117
-3 *310:14 0.0362163
-4 *310:13 0.035308
-5 *310:11 0.0262794
-6 *310:10 0.0262794
-7 *310:8 0.00229456
-8 *310:7 0.00288867
-9 la_data_out[27] *310:11 0
-10 la_data_out[48] *310:14 0
-11 *144:16 *310:8 0.00798725
-12 *238:13 *310:7 0
-13 *264:8 *310:14 0.0157274
-14 *271:8 *310:14 0
-15 *290:14 *310:8 0.0131177
-16 *294:16 *310:8 0.0877215
-17 *299:10 *310:14 0
-18 *301:20 *310:8 0.00120195
-19 *309:9 *310:7 0
-*RES
-1 *419:irq[2] *310:7 9.765
-2 *310:7 *310:8 126.99
-3 *310:8 *310:10 4.5
-4 *310:10 *310:11 257.13
-5 *310:11 *310:13 4.5
-6 *310:13 *310:14 347.13
-7 *310:14 user_irq[2] 13.365
-*END
-
-*D_NET *313 0.127298
+*D_NET *313 0.10389
*CONN
*P wb_clk_i I
-*I *419:wb_clk_i I *D user_proj_example
+*I *419:wb_clk_i I *D wrapped_vga_clock
*CAP
1 wb_clk_i 0.000291157
-2 *419:wb_clk_i 0.00232083
-3 *313:16 0.0181487
-4 *313:15 0.0158278
-5 *313:13 0.0236068
-6 *313:11 0.023898
-7 *419:wb_clk_i *314:11 0.0242434
-8 *313:16 *320:16 0.0189618
-9 *69:11 *313:13 0
+2 *419:wb_clk_i 0.0134678
+3 *313:15 0.0134678
+4 *313:13 0.0355052
+5 *313:11 0.0357963
+6 *64:14 *419:wb_clk_i 0.00536215
+7 *94:8 *313:13 0
*RES
1 wb_clk_i *313:11 3.015
-2 *313:11 *313:13 235.71
+2 *313:11 *313:13 354.33
3 *313:13 *313:15 4.5
-4 *313:15 *313:16 178.65
-5 *313:16 *419:wb_clk_i 40.995
+4 *313:15 *419:wb_clk_i 170.325
*END
-*D_NET *314 0.250946
+*D_NET *314 0.135663
*CONN
*P wb_rst_i I
-*I *419:wb_rst_i I *D user_proj_example
+*I *419:wb_rst_i I *D wrapped_vga_clock
*CAP
-1 wb_rst_i 0.00252754
-2 *419:wb_rst_i 0.000272069
-3 *314:11 0.0129759
-4 *314:10 0.0127039
-5 *314:8 0.0164332
-6 *314:7 0.0189607
-7 *314:11 *323:13 0.16283
-8 *419:wb_clk_i *314:11 0.0242434
+1 wb_rst_i 0.026316
+2 *419:wb_rst_i 0.000232589
+3 *314:11 0.00350075
+4 *314:10 0.00326817
+5 *314:8 0.0241334
+6 *314:7 0.0241334
+7 *314:5 0.026316
+8 *28:5 *314:8 0
+9 *66:8 *314:11 0.00486914
+10 *101:8 *314:11 0.0228931
+11 *105:15 *314:5 0
*RES
-1 wb_rst_i *314:7 29.565
-2 *314:7 *314:8 173.07
-3 *314:8 *314:10 4.5
-4 *314:10 *314:11 246.15
-5 *314:11 *419:wb_rst_i 11.115
-*END
-
-*D_NET *315 0.100448
-*CONN
-*P wbs_ack_o O
-*I *419:wbs_ack_o O *D user_proj_example
-*CAP
-1 wbs_ack_o 0.0032387
-2 *419:wbs_ack_o 0.00215583
-3 *315:15 0.0231176
-4 *315:14 0.0198789
-5 *315:12 0.0165186
-6 *315:11 0.0186744
-7 *315:11 *419:wbs_cyc_i 0.00270667
-8 *315:11 *419:wbs_stb_i 0.00840847
-9 *315:11 *356:13 0.00574886
-10 *68:11 *315:15 0
-*RES
-1 *419:wbs_ack_o *315:11 45.765
-2 *315:11 *315:12 173.07
-3 *315:12 *315:14 4.5
-4 *315:14 *315:15 198.54
-5 *315:15 wbs_ack_o 32.265
-*END
-
-*D_NET *316 0.171842
-*CONN
-*P wbs_adr_i[0] I
-*I *419:wbs_adr_i[0] I *D user_proj_example
-*CAP
-1 wbs_adr_i[0] 0.000220069
-2 *419:wbs_adr_i[0] 0.000458216
-3 *316:16 0.0105568
-4 *316:15 0.0100986
-5 *316:13 0.0291208
-6 *316:11 0.0293408
-7 *419:wbs_adr_i[0] *419:wbs_dat_i[0] 0.00102191
-8 *419:wbs_adr_i[0] *419:wbs_stb_i 0
-9 *419:wbs_adr_i[0] *419:wbs_we_i 0.00131958
-10 *316:11 *349:13 1.87963e-05
-11 *316:13 *418:10 0.000472977
-12 *316:16 *403:8 0.0892137
-13 *28:5 *316:16 0
-*RES
-1 wbs_adr_i[0] *316:11 2.475
-2 *316:11 *316:13 262.71
-3 *316:13 *316:15 4.5
-4 *316:15 *316:16 165.51
-5 *316:16 *419:wbs_adr_i[0] 13.635
-*END
-
-*D_NET *317 0.0926521
-*CONN
-*P wbs_adr_i[10] I
-*I *419:wbs_adr_i[10] I *D user_proj_example
-*CAP
-1 wbs_adr_i[10] 0.000967586
-2 *419:wbs_adr_i[10] 0.00190221
-3 *317:14 0.00919053
-4 *317:13 0.00728832
-5 *317:11 0.0233847
-6 *317:10 0.0243523
-7 *419:wbs_adr_i[10] wbs_dat_o[19] 0.00111704
-8 *419:wbs_adr_i[10] *419:wbs_dat_i[10] 0
-9 *419:wbs_adr_i[10] *419:wbs_dat_i[11] 0.00460318
-10 *419:wbs_adr_i[10] *419:wbs_dat_i[9] 0.00118072
-11 *419:wbs_adr_i[10] *382:9 0
-12 *419:wbs_adr_i[10] *412:12 0.000571817
-13 *317:10 *412:16 0.000317324
-14 *317:10 *413:8 0
-15 *317:11 wbs_dat_o[10] 0
-16 *317:14 *324:8 0.0174695
-17 *104:12 *317:11 0.000306879
-*RES
-1 wbs_adr_i[10] *317:10 19.575
-2 *317:10 *317:11 233.73
-3 *317:11 *317:13 4.5
-4 *317:13 *317:14 86.31
-5 *317:14 *419:wbs_adr_i[10] 35.955
-*END
-
-*D_NET *318 0.149293
-*CONN
-*P wbs_adr_i[11] I
-*I *419:wbs_adr_i[11] I *D user_proj_example
-*CAP
-1 wbs_adr_i[11] 0.00105029
-2 *419:wbs_adr_i[11] 0.000628996
-3 *318:14 0.00211491
-4 *318:13 0.00148592
-5 *318:11 0.0259341
-6 *318:10 0.0269844
-7 *419:wbs_adr_i[11] *419:wbs_dat_i[11] 0.000500596
-8 *419:wbs_adr_i[11] *382:9 0
-9 *419:wbs_adr_i[11] *383:9 0
-10 *318:10 *338:12 0.00702485
-11 *318:10 *351:13 0.000595217
-12 *318:11 *319:10 8.9762e-05
-13 *318:11 *352:7 0
-14 *318:11 *352:9 0
-15 *318:14 *319:14 0.0435808
-16 *318:14 *342:16 0.0363691
-17 *318:14 *389:12 0.00293441
-*RES
-1 wbs_adr_i[11] *318:10 25.155
-2 *318:10 *318:11 257.31
-3 *318:11 *318:13 4.5
-4 *318:13 *318:14 73.89
-5 *318:14 *419:wbs_adr_i[11] 12.465
-*END
-
-*D_NET *319 0.144221
-*CONN
-*P wbs_adr_i[12] I
-*I *419:wbs_adr_i[12] I *D user_proj_example
-*CAP
-1 wbs_adr_i[12] 0.00134328
-2 *419:wbs_adr_i[12] 0.000582501
-3 *319:14 0.00229191
-4 *319:13 0.00170941
-5 *319:11 0.0258711
-6 *319:10 0.0272143
-7 *419:wbs_adr_i[12] *419:wbs_dat_i[12] 0.000424643
-8 *419:wbs_adr_i[12] *383:9 0
-9 *419:wbs_adr_i[12] *393:11 0.000306879
-10 *319:10 *383:14 0.00814424
-11 *319:10 *413:8 0
-12 *319:11 wbs_dat_o[13] 0
-13 *319:11 *353:13 0
-14 *319:14 *322:14 0.0323901
-15 *319:14 *389:12 0.000271992
-16 *318:11 *319:10 8.9762e-05
-17 *318:14 *319:14 0.0435808
-*RES
-1 wbs_adr_i[12] *319:10 27.855
-2 *319:10 *319:11 256.41
-3 *319:11 *319:13 4.5
-4 *319:13 *319:14 65.79
-5 *319:14 *419:wbs_adr_i[12] 12.285
-*END
-
-*D_NET *320 0.130408
-*CONN
-*P wbs_adr_i[13] I
-*I *419:wbs_adr_i[13] I *D user_proj_example
-*CAP
-1 wbs_adr_i[13] 0.00014502
-2 *419:wbs_adr_i[13] 0.0035647
-3 *320:16 0.00639688
-4 *320:15 0.00283218
-5 *320:13 0.0236817
-6 *320:11 0.0238267
-7 *419:wbs_adr_i[13] *419:wbs_dat_i[12] 0
-8 *419:wbs_adr_i[13] *419:wbs_dat_i[13] 0
-9 *419:wbs_adr_i[13] *352:15 0.00270053
-10 *419:wbs_adr_i[13] *384:13 0.0013605
-11 *419:wbs_adr_i[13] *385:9 0
-12 *320:16 *353:16 0.0469379
-13 *313:16 *320:16 0.0189618
-*RES
-1 wbs_adr_i[13] *320:11 1.755
-2 *320:11 *320:13 235.89
-3 *320:13 *320:15 4.5
-4 *320:15 *320:16 70.65
-5 *320:16 *419:wbs_adr_i[13] 41.895
-*END
-
-*D_NET *321 0.132126
-*CONN
-*P wbs_adr_i[14] I
-*I *419:wbs_adr_i[14] I *D user_proj_example
-*CAP
-1 wbs_adr_i[14] 0.000271935
-2 *419:wbs_adr_i[14] 0.000761622
-3 *321:16 0.00298037
-4 *321:15 0.00221874
-5 *321:13 0.0262748
-6 *321:11 0.0265468
-7 *419:wbs_adr_i[14] *419:wbs_dat_i[14] 0.000936364
-8 *419:wbs_adr_i[14] *385:9 0
-9 *321:13 wbs_dat_o[13] 1.87963e-05
-10 *321:13 *414:21 0
-11 *321:16 *347:16 0.0369908
-12 *321:16 *387:8 0.0351256
-13 *29:16 *321:13 0
-*RES
-1 wbs_adr_i[14] *321:11 2.835
-2 *321:11 *321:13 260.37
-3 *321:13 *321:15 4.5
-4 *321:15 *321:16 67.05
-5 *321:16 *419:wbs_adr_i[14] 15.345
-*END
-
-*D_NET *322 0.128672
-*CONN
-*P wbs_adr_i[15] I
-*I *419:wbs_adr_i[15] I *D user_proj_example
-*CAP
-1 wbs_adr_i[15] 0.000789617
-2 *419:wbs_adr_i[15] 0.000577735
-3 *322:14 0.00163762
-4 *322:13 0.00105988
-5 *322:11 0.0259966
-6 *322:10 0.0267863
-7 *419:wbs_adr_i[15] *419:wbs_dat_i[15] 0.000583453
-8 *419:wbs_adr_i[15] *386:9 0
-9 *322:10 *338:12 0.00217594
-10 *322:11 *355:7 0.000920636
-11 *322:11 *387:11 0
-12 *322:14 *323:16 0.035125
-13 *322:14 *389:12 0.000629418
-14 *322:14 *418:14 0
-15 *12:14 *322:11 0
-16 *319:14 *322:14 0.0323901
-*RES
-1 wbs_adr_i[15] *322:10 18.135
-2 *322:10 *322:11 257.67
-3 *322:11 *322:13 4.5
-4 *322:13 *322:14 54.99
-5 *322:14 *419:wbs_adr_i[15] 12.105
-*END
-
-*D_NET *323 0.239962
-*CONN
-*P wbs_adr_i[16] I
-*I *419:wbs_adr_i[16] I *D user_proj_example
-*CAP
-1 wbs_adr_i[16] 0.00020706
-2 *419:wbs_adr_i[16] 0.00026907
-3 *323:16 0.00283071
-4 *323:15 0.00256164
-5 *323:13 0.0160755
-6 *323:11 0.0162825
-7 *419:wbs_adr_i[16] *419:wbs_dat_i[16] 0.000676028
-8 *419:wbs_adr_i[16] *387:7 0.000569644
-9 *323:16 *419:wbs_adr_i[19] 0
-10 *323:16 *419:wbs_dat_i[11] 0.000356699
-11 *323:16 *419:wbs_sel_i[0] 0.000216817
-12 *323:16 *419:wbs_stb_i 5.90613e-05
-13 *323:16 *384:13 0
-14 *323:16 *389:12 1.55425e-05
-15 *323:16 *394:10 0.000174852
-16 *323:16 *406:13 0.0010071
-17 *323:16 *408:10 0.00064242
-18 *323:16 *412:12 6.29468e-05
-19 *323:16 *416:14 0
-20 *323:16 *418:14 0
-21 *314:11 *323:13 0.16283
-22 *322:14 *323:16 0.035125
-*RES
-1 wbs_adr_i[16] *323:11 2.295
-2 *323:11 *323:13 263.79
-3 *323:13 *323:15 4.5
-4 *323:15 *323:16 53.55
-5 *323:16 *419:wbs_adr_i[16] 11.925
-*END
-
-*D_NET *324 0.223229
-*CONN
-*P wbs_adr_i[17] I
-*I *419:wbs_adr_i[17] I *D user_proj_example
-*CAP
-1 wbs_adr_i[17] 0.014408
-2 *419:wbs_adr_i[17] 0.00171729
-3 *324:8 0.00495893
-4 *324:5 0.0176496
-5 *419:wbs_adr_i[17] *419:wbs_dat_i[16] 0.00288466
-6 *419:wbs_adr_i[17] *419:wbs_dat_i[17] 0
-7 *419:wbs_adr_i[17] *357:17 0
-8 *419:wbs_adr_i[17] *361:11 0.000438836
-9 *419:wbs_adr_i[17] *388:12 0.00115463
-10 *419:wbs_adr_i[17] *388:13 0.0122138
-11 *419:wbs_adr_i[17] *389:9 0
-12 *324:5 *392:9 0.000208677
-13 *324:5 *392:11 0.150125
-14 *317:14 *324:8 0.0174695
-*RES
-1 wbs_adr_i[17] *324:5 241.245
-2 *324:5 *324:8 47.79
-3 *324:8 *419:wbs_adr_i[17] 45.675
-*END
-
-*D_NET *325 0.192443
-*CONN
-*P wbs_adr_i[18] I
-*I *419:wbs_adr_i[18] I *D user_proj_example
-*CAP
-1 wbs_adr_i[18] 0.00235195
-2 *419:wbs_adr_i[18] 0.00195159
-3 *325:17 0.0152283
-4 *325:16 0.0159844
-5 *325:13 0.00505962
-6 *419:wbs_adr_i[18] *419:wbs_dat_i[18] 0.000217884
-7 *419:wbs_adr_i[18] *357:17 0.00175381
-8 *419:wbs_adr_i[18] *359:13 0.00484868
-9 *419:wbs_adr_i[18] *389:9 0.000994799
-10 *419:wbs_adr_i[18] *390:11 0
-11 *325:13 *357:10 0.00192726
-12 *325:13 *358:10 6.13758e-05
-13 *325:13 *408:11 0.00939048
-14 *325:13 *410:14 0.00064242
-15 *325:16 *382:14 0.0105067
-16 *325:17 *357:17 0.121524
-17 *325:17 *362:11 0
-*RES
-1 wbs_adr_i[18] *325:13 44.325
-2 *325:13 *325:16 38.61
-3 *325:16 *325:17 211.86
-4 *325:17 *419:wbs_adr_i[18] 33.615
-*END
-
-*D_NET *326 0.0847193
-*CONN
-*P wbs_adr_i[19] I
-*I *419:wbs_adr_i[19] I *D user_proj_example
-*CAP
-1 wbs_adr_i[19] 0.000271935
-2 *419:wbs_adr_i[19] 0.00240214
-3 *326:13 0.0281318
-4 *326:11 0.0260016
-5 *419:wbs_adr_i[19] *419:wbs_dat_i[19] 0.000572806
-6 *419:wbs_adr_i[19] *384:13 0.00839248
-7 *419:wbs_adr_i[19] *390:9 0
-8 *419:wbs_adr_i[19] *393:10 0.0127444
-9 *419:wbs_adr_i[19] *409:8 0.000186509
-10 *419:wbs_adr_i[19] *411:8 0.000543985
-11 *326:13 wbs_dat_o[18] 0.000840847
-12 *326:13 *419:wbs_adr_i[6] 0.000273122
-13 *326:13 *419:wbs_dat_i[6] 0.00435768
-14 *323:16 *419:wbs_adr_i[19] 0
-*RES
-1 wbs_adr_i[19] *326:11 2.835
-2 *326:11 *326:13 265.41
-3 *326:13 *419:wbs_adr_i[19] 49.455
-*END
-
-*D_NET *327 0.129923
-*CONN
-*P wbs_adr_i[1] I
-*I *419:wbs_adr_i[1] I *D user_proj_example
-*CAP
-1 wbs_adr_i[1] 8.61527e-05
-2 *419:wbs_adr_i[1] 0.000628651
-3 *327:16 0.0121149
-4 *327:15 0.0114863
-5 *327:13 0.026068
-6 *327:11 0.0261541
-7 *419:wbs_adr_i[1] *419:wbs_dat_i[1] 0.000972167
-8 *419:wbs_adr_i[1] *419:wbs_sel_i[0] 0.000500596
-9 *419:wbs_adr_i[1] *381:5 0
-10 *327:13 *418:11 0
-11 *327:16 *347:16 0.0519118
-12 *327:16 *384:14 0
-*RES
-1 wbs_adr_i[1] *327:11 1.215
-2 *327:11 *327:13 260.01
-3 *327:13 *327:15 4.5
-4 *327:15 *327:16 156.15
-5 *327:16 *419:wbs_adr_i[1] 15.705
-*END
-
-*D_NET *328 0.199801
-*CONN
-*P wbs_adr_i[20] I
-*I *419:wbs_adr_i[20] I *D user_proj_example
-*CAP
-1 wbs_adr_i[20] 0.00265236
-2 *419:wbs_adr_i[20] 0.0010894
-3 *328:19 0.0137448
-4 *328:18 0.0151254
-5 *328:15 0.00512229
-6 *419:wbs_adr_i[20] *419:wbs_dat_i[20] 0
-7 *419:wbs_adr_i[20] *329:19 0
-8 *419:wbs_adr_i[20] *391:9 0.000918335
-9 *328:15 *358:11 0
-10 *328:19 *391:9 0.00138709
-11 *328:19 *395:11 0.159761
-*RES
-1 wbs_adr_i[20] *328:15 30.825
-2 *328:15 *328:18 29.07
-3 *328:18 *328:19 234.27
-4 *328:19 *419:wbs_adr_i[20] 23.398
-*END
-
-*D_NET *329 0.10192
-*CONN
-*P wbs_adr_i[21] I
-*I *419:wbs_adr_i[21] I *D user_proj_example
-*CAP
-1 wbs_adr_i[21] 0.00410607
-2 *419:wbs_adr_i[21] 0.000517273
-3 *329:19 0.0149092
-4 *329:18 0.0143919
-5 *329:16 0.00410607
-6 *419:wbs_adr_i[21] *419:wbs_adr_i[23] 0.000808207
-7 *419:wbs_adr_i[21] *419:wbs_dat_i[20] 0
-8 *419:wbs_adr_i[21] *419:wbs_dat_i[21] 0
-9 *419:wbs_adr_i[21] *331:13 9.20636e-06
-10 *419:wbs_adr_i[21] *393:10 0.00131493
-11 *419:wbs_adr_i[21] *395:10 0.00105689
-12 *329:16 *357:11 0
-13 *329:19 *419:wbs_dat_i[20] 0.00742646
-14 *329:19 *331:13 0.0532742
-15 *419:wbs_adr_i[20] *329:19 0
-*RES
-1 wbs_adr_i[21] *329:16 45.675
-2 *329:16 *329:18 4.5
-3 *329:18 *329:19 245.25
-4 *329:19 *419:wbs_adr_i[21] 17.505
-*END
-
-*D_NET *330 0.0902637
-*CONN
-*P wbs_adr_i[22] I
-*I *419:wbs_adr_i[22] I *D user_proj_example
-*CAP
-1 wbs_adr_i[22] 0.00274454
-2 *419:wbs_adr_i[22] 0.00303709
-3 *330:17 0.0158877
-4 *330:16 0.0155951
-5 *419:wbs_adr_i[22] *419:wbs_dat_i[22] 0
-6 *419:wbs_adr_i[22] *362:19 0
-7 *419:wbs_adr_i[22] *364:13 0
-8 *419:wbs_adr_i[22] *394:10 0.00189242
-9 *330:16 wbs_dat_o[18] 0
-10 *330:16 *331:13 0.00135155
-11 *330:16 *362:11 0
-12 *330:16 *364:13 0
-13 *330:17 *364:13 0.0497553
-*RES
-1 wbs_adr_i[22] *330:16 49.995
-2 *330:16 *330:17 218.88
-3 *330:17 *419:wbs_adr_i[22] 33.435
-*END
-
-*D_NET *331 0.0987657
-*CONN
-*P wbs_adr_i[23] I
-*I *419:wbs_adr_i[23] I *D user_proj_example
-*CAP
-1 wbs_adr_i[23] 8.61527e-05
-2 *419:wbs_adr_i[23] 0.000667921
-3 *331:13 0.0165587
-4 *331:11 0.0159769
-5 *419:wbs_adr_i[23] *419:wbs_dat_i[23] 0.000285014
-6 *419:wbs_adr_i[23] *363:14 0.000453321
-7 *419:wbs_adr_i[23] *393:10 0.000111905
-8 *419:wbs_adr_i[23] *395:10 0.00163344
-9 *331:13 *419:wbs_dat_i[20] 0.00754921
-10 *419:wbs_adr_i[21] *419:wbs_adr_i[23] 0.000808207
-11 *419:wbs_adr_i[21] *331:13 9.20636e-06
-12 *329:19 *331:13 0.0532742
-13 *330:16 *331:13 0.00135155
-*RES
-1 wbs_adr_i[23] *331:11 1.215
-2 *331:11 *331:13 265.05
-3 *331:13 *419:wbs_adr_i[23] 22.275
-*END
-
-*D_NET *332 0.202102
-*CONN
-*P wbs_adr_i[24] I
-*I *419:wbs_adr_i[24] I *D user_proj_example
-*CAP
-1 wbs_adr_i[24] 0.000962013
-2 *419:wbs_adr_i[24] 0.00153306
-3 *332:19 0.0152512
-4 *332:18 0.0146801
-5 *419:wbs_adr_i[24] *419:wbs_dat_i[24] 0
-6 *419:wbs_adr_i[24] *396:9 0.00165587
-7 *419:wbs_adr_i[24] *396:11 0
-8 *332:18 *396:11 3.45239e-05
-9 *332:19 *396:11 0.167985
-*RES
-1 wbs_adr_i[24] *332:18 18.495
-2 *332:18 *332:19 246.33
-3 *332:19 *419:wbs_adr_i[24] 30.0972
-*END
-
-*D_NET *333 0.061814
-*CONN
-*P wbs_adr_i[25] I
-*I *419:wbs_adr_i[25] I *D user_proj_example
-*CAP
-1 wbs_adr_i[25] 0.00111261
-2 *419:wbs_adr_i[25] 0.00040743
-3 *333:11 0.0267407
-4 *333:10 0.0274459
-5 *419:wbs_adr_i[25] *419:wbs_dat_i[24] 0.000435078
-6 *419:wbs_adr_i[25] *419:wbs_dat_i[25] 0.000486786
-7 *419:wbs_adr_i[25] *397:14 0.00181986
-8 *333:10 *419:wbs_dat_i[27] 0.000184127
-9 *333:10 *334:11 0.000116358
-10 *333:10 *336:10 0.000435189
-11 *333:10 *368:20 0.000186509
-12 *333:11 wbs_dat_o[24] 0
-13 *333:11 *365:5 0
-14 *333:11 *397:14 0.00244352
-15 *333:11 *399:11 0
-*RES
-1 wbs_adr_i[25] *333:10 21.015
-2 *333:10 *333:11 257.13
-3 *333:11 *419:wbs_adr_i[25] 17.775
-*END
-
-*D_NET *334 0.0684225
-*CONN
-*P wbs_adr_i[26] I
-*I *419:wbs_adr_i[26] I *D user_proj_example
-*CAP
-1 wbs_adr_i[26] 0.000916191
-2 *419:wbs_adr_i[26] 0.000615517
-3 *334:11 0.0179281
-4 *334:10 0.0182288
-5 *419:wbs_adr_i[26] *419:wbs_dat_i[25] 0.000262926
-6 *419:wbs_adr_i[26] *419:wbs_dat_i[26] 0.000445358
-7 *419:wbs_adr_i[26] *397:14 0.000306879
-8 *419:wbs_adr_i[26] *398:10 0.000761708
-9 *419:wbs_adr_i[26] *399:9 0
-10 *419:wbs_adr_i[26] *400:10 1.24339e-05
-11 *334:10 *337:15 0.000184127
-12 *334:10 *337:18 0.00478707
-13 *334:10 *339:20 0.00304632
-14 *334:10 *368:20 0.000142991
-15 *334:11 *419:wbs_adr_i[28] 0.000961554
-16 *334:11 *419:wbs_dat_i[27] 0.0197062
-17 *334:11 *366:13 0
-18 *333:10 *334:11 0.000116358
-*RES
-1 wbs_adr_i[26] *334:10 23.715
-2 *334:10 *334:11 258.03
-3 *334:11 *419:wbs_adr_i[26] 20.655
-*END
-
-*D_NET *335 0.0787499
-*CONN
-*P wbs_adr_i[27] I
-*I *419:wbs_adr_i[27] I *D user_proj_example
-*CAP
-1 wbs_adr_i[27] 0.000851661
-2 *419:wbs_adr_i[27] 0.000742326
-3 *335:19 0.00282804
-4 *335:11 0.019284
-5 *335:10 0.0180499
-6 *419:wbs_adr_i[27] *419:wbs_dat_i[27] 0
-7 *419:wbs_adr_i[27] *398:11 0.00969736
-8 *419:wbs_adr_i[27] *399:9 0.00438658
-9 *419:wbs_adr_i[27] *399:11 6.13757e-06
-10 *335:10 *336:10 0.00292198
-11 *335:10 *402:20 0.00292198
-12 *335:11 wbs_dat_o[26] 0.000469524
-13 *335:19 *398:11 0.000814508
-14 *335:19 *399:9 9.2064e-05
-15 *335:19 *399:11 0.00112931
-16 *126:11 *335:11 0
-17 *179:17 *335:11 0.000268519
-18 *179:21 *335:11 0.0127393
-19 *190:7 *335:11 0
-20 *243:19 *335:11 0.00154667
-*RES
-1 wbs_adr_i[27] *335:10 20.475
-2 *335:10 *335:11 235.17
-3 *335:11 *335:19 34.92
-4 *335:19 *419:wbs_adr_i[27] 22.005
-*END
-
-*D_NET *336 0.112156
-*CONN
-*P wbs_adr_i[28] I
-*I *419:wbs_adr_i[28] I *D user_proj_example
-*CAP
-1 wbs_adr_i[28] 0.00240383
-2 *419:wbs_adr_i[28] 0.00088921
-3 *336:11 0.0157515
-4 *336:10 0.0172661
-5 *419:wbs_adr_i[28] *419:wbs_dat_i[27] 0
-6 *419:wbs_adr_i[28] *419:wbs_dat_i[28] 0
-7 *419:wbs_adr_i[28] *366:13 0.000168783
-8 *419:wbs_adr_i[28] *369:15 0
-9 *419:wbs_adr_i[28] *400:10 0.00148325
-10 *336:10 *368:20 0.00882811
-11 *336:10 *402:20 0.00358512
-12 *336:11 *419:wbs_dat_i[27] 0.0574273
-13 *336:11 *398:11 0
-14 *298:11 *336:10 3.37566e-05
-15 *303:11 *336:10 0
-16 *333:10 *336:10 0.000435189
-17 *334:11 *419:wbs_adr_i[28] 0.000961554
-18 *335:10 *336:10 0.00292198
-*RES
-1 wbs_adr_i[28] *336:10 44.595
-2 *336:10 *336:11 252.63
-3 *336:11 *419:wbs_adr_i[28] 22.545
-*END
-
-*D_NET *337 0.280619
-*CONN
-*P wbs_adr_i[29] I
-*I *419:wbs_adr_i[29] I *D user_proj_example
-*CAP
-1 wbs_adr_i[29] 0.00129959
-2 *419:wbs_adr_i[29] 0.00109167
-3 *337:19 0.00476234
-4 *337:18 0.00377896
-5 *337:15 0.00140788
-6 *419:wbs_adr_i[29] *419:wbs_dat_i[29] 0
-7 *419:wbs_adr_i[29] *339:21 9.20636e-06
-8 *419:wbs_adr_i[29] *369:15 0.000196402
-9 *419:wbs_adr_i[29] *401:10 0.00127866
-10 *419:wbs_adr_i[29] *402:9 0
-11 *337:15 *339:20 0.00302559
-12 *337:15 *340:8 0.000136773
-13 *337:15 *368:20 0.00590613
-14 *337:15 *369:14 0.0143861
-15 *337:18 *339:20 4.14464e-05
-16 *337:18 *369:14 0.00155424
-17 *337:19 *366:13 0.173141
-18 *337:19 *369:15 0.0577137
-19 *298:8 *337:15 0.000621697
-20 *303:8 *337:15 0.00528443
-21 *306:11 *337:15 1.22751e-05
-22 *334:10 *337:15 0.000184127
-23 *334:10 *337:18 0.00478707
-*RES
-1 wbs_adr_i[29] *337:15 47.475
-2 *337:15 *337:18 11.61
-3 *337:18 *337:19 253.89
-4 *337:19 *419:wbs_adr_i[29] 22.858
-*END
-
-*D_NET *338 0.201119
-*CONN
-*P wbs_adr_i[2] I
-*I *419:wbs_adr_i[2] I *D user_proj_example
-*CAP
-1 wbs_adr_i[2] 0.00100319
-2 *419:wbs_adr_i[2] 0.00117375
-3 *338:15 0.029451
-4 *338:14 0.0282773
-5 *338:12 0.00543915
-6 *338:10 0.00644233
-7 *419:wbs_adr_i[2] *419:wbs_dat_i[2] 0.000238215
-8 *419:wbs_adr_i[2] *419:wbs_sel_i[1] 0.00037631
-9 *419:wbs_adr_i[2] *403:7 0
-10 *419:wbs_adr_i[2] *406:13 0
-11 *338:10 *371:10 0.00105689
-12 *338:10 *417:8 0.000417055
-13 *338:12 wbs_dat_o[2] 0.00254896
-14 *338:12 wbs_dat_o[4] 0.00615448
-15 *338:12 wbs_dat_o[6] 0.00105689
-16 *338:12 wbs_dat_o[8] 0.00317066
-17 *338:12 *341:8 0.0929433
-18 *338:12 *350:10 0.00192726
-19 *338:12 *379:10 0.00194798
-20 *338:12 *415:10 0.00789556
-21 *338:12 *417:8 0.000397886
-22 *318:10 *338:12 0.00702485
-23 *322:10 *338:12 0.00217594
-*RES
-1 wbs_adr_i[2] *338:10 16.515
-2 *338:10 *338:12 141.12
-3 *338:12 *338:14 4.5
-4 *338:14 *338:15 252.54
-5 *338:15 *419:wbs_adr_i[2] 12.825
-*END
-
-*D_NET *339 0.20706
-*CONN
-*P wbs_adr_i[30] I
-*I *419:wbs_adr_i[30] I *D user_proj_example
-*CAP
-1 wbs_adr_i[30] 0.00127533
-2 *419:wbs_adr_i[30] 0.000927145
-3 *339:21 0.0155342
-4 *339:20 0.0149424
-5 *339:13 0.00161069
-6 *419:wbs_adr_i[30] *419:wbs_dat_i[30] 0
-7 *419:wbs_adr_i[30] *340:11 0.000168783
-8 *419:wbs_adr_i[30] *400:11 0.00108431
-9 *419:wbs_adr_i[30] *402:9 0.000497144
-10 *419:wbs_adr_i[30] *404:9 0
-11 *339:13 *402:20 0.0121231
-12 *339:13 *404:14 0.0142368
-13 *339:20 *340:8 0.00924258
-14 *339:20 *367:10 0.00242462
-15 *339:20 *368:20 0.00593411
-16 *339:20 *369:14 2.71992e-05
-17 *339:20 *402:20 0.000235727
-18 *339:21 *398:17 0.0983853
-19 *339:21 *402:9 0.00201389
-20 *339:21 *402:11 0.0202745
-21 *419:wbs_adr_i[29] *339:21 9.20636e-06
-22 *305:8 *339:13 0
-23 *334:10 *339:20 0.00304632
-24 *337:15 *339:20 0.00302559
-25 *337:18 *339:20 4.14464e-05
-*RES
-1 wbs_adr_i[30] *339:13 41.805
-2 *339:13 *339:20 25.47
-3 *339:20 *339:21 253.71
-4 *339:21 *419:wbs_adr_i[30] 22.545
-*END
-
-*D_NET *340 0.153632
-*CONN
-*P wbs_adr_i[31] I
-*I *419:wbs_adr_i[31] I *D user_proj_example
-*CAP
-1 wbs_adr_i[31] 0.00071579
-2 *419:wbs_adr_i[31] 0.000558136
-3 *340:11 0.0158522
-4 *340:10 0.015294
-5 *340:8 0.000718576
-6 *340:7 0.00143437
-7 *419:wbs_adr_i[31] *419:wbs_dat_i[26] 0.000186509
-8 *419:wbs_adr_i[31] *419:wbs_dat_i[29] 0.000393741
-9 *419:wbs_adr_i[31] *419:wbs_dat_i[31] 0
-10 *419:wbs_adr_i[31] *367:11 0.00014321
-11 *419:wbs_adr_i[31] *401:10 3.62657e-05
-12 *419:wbs_adr_i[31] *404:9 0.000441905
-13 *340:7 *373:13 0
-14 *340:8 *367:10 0.00242462
-15 *340:8 *402:20 8.28929e-05
-16 *340:8 *404:14 0.0305253
-17 *340:11 *367:11 0
-18 *340:11 *400:11 0
-19 *340:11 *404:9 0.00249723
-20 *340:11 *404:11 0.0529468
-21 *419:wbs_adr_i[30] *340:11 0.000168783
-22 *298:8 *340:8 0.0198321
-23 *337:15 *340:8 0.000136773
-24 *339:20 *340:8 0.00924258
-*RES
-1 wbs_adr_i[31] *340:7 11.205
-2 *340:7 *340:8 47.61
-3 *340:8 *340:10 4.5
-4 *340:10 *340:11 258.21
-5 *340:11 *419:wbs_adr_i[31] 17.685
-*END
-
-*D_NET *341 0.24817
-*CONN
-*P wbs_adr_i[3] I
-*I *419:wbs_adr_i[3] I *D user_proj_example
-*CAP
-1 wbs_adr_i[3] 0.000662592
-2 *419:wbs_adr_i[3] 0.000853967
-3 *341:11 0.0161644
-4 *341:10 0.0153104
-5 *341:8 0.00166673
-6 *341:7 0.00232932
-7 *419:wbs_adr_i[3] *419:wbs_dat_i[3] 0.00147072
-8 *419:wbs_adr_i[3] *419:wbs_sel_i[2] 0.00185559
-9 *419:wbs_adr_i[3] *389:13 0.00804022
-10 *341:7 *374:13 0
-11 *341:8 *357:10 0.000476597
-12 *341:8 *410:14 0.0627289
-13 *341:8 *417:8 0.0105688
-14 *341:11 wbs_dat_o[17] 0.00253303
-15 *341:11 *419:wbs_sel_i[2] 0.00128889
-16 *341:11 *389:13 0.0292762
-17 *338:12 *341:8 0.0929433
-*RES
-1 wbs_adr_i[3] *341:7 10.845
-2 *341:7 *341:8 136.71
-3 *341:8 *341:10 4.5
-4 *341:10 *341:11 244.71
-5 *341:11 *419:wbs_adr_i[3] 30.8015
-*END
-
-*D_NET *342 0.190473
-*CONN
-*P wbs_adr_i[4] I
-*I *419:wbs_adr_i[4] I *D user_proj_example
-*CAP
-1 wbs_adr_i[4] 0.000271935
-2 *419:wbs_adr_i[4] 0.000597672
-3 *342:16 0.00514429
-4 *342:15 0.00454662
-5 *342:13 0.0261698
-6 *342:11 0.0264417
-7 *419:wbs_adr_i[4] *419:wbs_dat_i[3] 0.000269286
-8 *419:wbs_adr_i[4] *419:wbs_dat_i[4] 0.000362501
-9 *419:wbs_adr_i[4] *419:wbs_sel_i[3] 0.000362501
-10 *419:wbs_adr_i[4] *406:13 0.000306879
-11 *419:wbs_adr_i[4] *411:8 0.000559453
-12 *342:13 *415:11 0
-13 *342:13 *416:10 0.0010127
-14 *342:16 *389:12 0.000476634
-15 *342:16 *403:8 0.0873483
-16 *28:5 *342:16 0.000233137
-17 *318:14 *342:16 0.0363691
-*RES
-1 wbs_adr_i[4] *342:11 2.835
-2 *342:11 *342:13 263.07
-3 *342:13 *342:15 4.5
-4 *342:15 *342:16 129.51
-5 *342:16 *419:wbs_adr_i[4] 24.165
-*END
-
-*D_NET *343 0.149542
-*CONN
-*P wbs_adr_i[5] I
-*I *419:wbs_adr_i[5] I *D user_proj_example
-*CAP
-1 wbs_adr_i[5] 8.61527e-05
-2 *419:wbs_adr_i[5] 0.00108854
-3 *343:16 0.00807064
-4 *343:15 0.00698211
-5 *343:13 0.0258585
-6 *343:11 0.0259446
-7 *419:wbs_adr_i[5] *419:wbs_dat_i[4] 0
-8 *419:wbs_adr_i[5] *419:wbs_dat_i[5] 0
-9 *419:wbs_adr_i[5] *407:9 0.000421191
-10 *419:wbs_adr_i[5] *408:11 0.00157531
-11 *343:16 *344:16 0.079515
-12 *343:16 *356:16 0
-*RES
-1 wbs_adr_i[5] *343:11 1.215
-2 *343:11 *343:13 257.31
-3 *343:13 *343:15 4.5
-4 *343:15 *343:16 123.21
-5 *343:16 *419:wbs_adr_i[5] 19.035
-*END
-
-*D_NET *344 0.213605
-*CONN
-*P wbs_adr_i[6] I
-*I *419:wbs_adr_i[6] I *D user_proj_example
-*CAP
-1 wbs_adr_i[6] 0.000203572
-2 *419:wbs_adr_i[6] 0.00110784
-3 *344:16 0.00302558
-4 *344:15 0.00191774
-5 *344:13 0.0256695
-6 *344:11 0.025873
-7 *419:wbs_adr_i[6] *419:wbs_dat_i[5] 0
-8 *419:wbs_adr_i[6] *419:wbs_dat_i[6] 0
-9 *419:wbs_adr_i[6] *408:10 0.001606
-10 *344:11 *377:13 7.67196e-06
-11 *344:13 wbs_dat_o[5] 0.000486403
-12 *344:13 *407:13 0
-13 *344:16 *345:8 0.0739197
-14 *326:13 *419:wbs_adr_i[6] 0.000273122
-15 *343:16 *344:16 0.079515
-*RES
-1 wbs_adr_i[6] *344:11 2.295
-2 *344:11 *344:13 257.49
-3 *344:13 *344:15 4.5
-4 *344:15 *344:16 117.81
-5 *344:16 *419:wbs_adr_i[6] 18.855
-*END
-
-*D_NET *345 0.200812
-*CONN
-*P wbs_adr_i[7] I
-*I *419:wbs_adr_i[7] I *D user_proj_example
-*CAP
-1 wbs_adr_i[7] 0.0259227
-2 *419:wbs_adr_i[7] 0.00128267
-3 *345:8 0.00319801
-4 *345:7 0.00191534
-5 *345:5 0.0259227
-6 *419:wbs_adr_i[7] *419:wbs_dat_i[6] 0
-7 *419:wbs_adr_i[7] *419:wbs_dat_i[7] 0
-8 *419:wbs_adr_i[7] *409:7 0.00119683
-9 *419:wbs_adr_i[7] *410:9 0
-10 *345:5 *409:11 0
-11 *345:8 *346:14 0.067454
-12 *344:16 *345:8 0.0739197
-*RES
-1 wbs_adr_i[7] *345:5 257.625
-2 *345:5 *345:7 4.5
-3 *345:7 *345:8 109.71
-4 *345:8 *419:wbs_adr_i[7] 18.675
-*END
-
-*D_NET *346 0.179397
-*CONN
-*P wbs_adr_i[8] I
-*I *419:wbs_adr_i[8] I *D user_proj_example
-*CAP
-1 wbs_adr_i[8] 0.000938494
-2 *419:wbs_adr_i[8] 0.000928794
-3 *346:14 0.00332624
-4 *346:13 0.00239745
-5 *346:11 0.0252002
-6 *346:10 0.0261387
-7 *419:wbs_adr_i[8] *419:wbs_dat_i[8] 0
-8 *419:wbs_adr_i[8] *384:13 0.000242434
-9 *419:wbs_adr_i[8] *410:9 0.00102881
-10 *346:10 *410:14 0.000202829
-11 *346:10 *413:8 0
-12 *346:14 *351:16 0.0515385
-13 *345:8 *346:14 0.067454
-*RES
-1 wbs_adr_i[8] *346:10 19.035
-2 *346:10 *346:11 250.47
-3 *346:11 *346:13 4.5
-4 *346:13 *346:14 100.35
-5 *346:14 *419:wbs_adr_i[8] 18.495
-*END
-
-*D_NET *347 0.153672
-*CONN
-*P wbs_adr_i[9] I
-*I *419:wbs_adr_i[9] I *D user_proj_example
-*CAP
-1 wbs_adr_i[9] 0.000271935
-2 *419:wbs_adr_i[9] 0.0005771
-3 *347:16 0.00473954
-4 *347:15 0.00416244
-5 *347:13 0.0259896
-6 *347:11 0.0262616
-7 *419:wbs_adr_i[9] *419:wbs_dat_i[8] 0
-8 *419:wbs_adr_i[9] *419:wbs_dat_i[9] 0.000934701
-9 *419:wbs_adr_i[9] *411:7 0.00039012
-10 *419:wbs_adr_i[9] *412:13 0.000626032
-11 *347:13 wbs_dat_o[8] 0.000816297
-12 *321:16 *347:16 0.0369908
-13 *327:16 *347:16 0.0519118
-*RES
-1 wbs_adr_i[9] *347:11 2.835
-2 *347:11 *347:13 260.19
-3 *347:13 *347:15 4.5
-4 *347:15 *347:16 99.45
-5 *347:16 *419:wbs_adr_i[9] 15.525
-*END
-
-*D_NET *348 0.18673
-*CONN
-*P wbs_cyc_i I
-*I *419:wbs_cyc_i I *D user_proj_example
-*CAP
-1 wbs_cyc_i 0.00010579
-2 *419:wbs_cyc_i 0.00103184
-3 *348:16 0.010518
-4 *348:15 0.0094862
-5 *348:13 0.025505
-6 *348:11 0.0256108
-7 *419:wbs_cyc_i *419:wbs_stb_i 0.000490239
-8 *419:wbs_cyc_i *356:13 0.000675133
-9 *348:16 *349:16 0.1106
-10 *68:11 *348:13 0
-11 *315:11 *419:wbs_cyc_i 0.00270667
-*RES
-1 wbs_cyc_i *348:11 1.395
-2 *348:11 *348:13 254.61
-3 *348:13 *348:15 4.5
-4 *348:15 *348:16 170.91
-5 *348:16 *419:wbs_cyc_i 21.735
-*END
-
-*D_NET *349 0.267667
-*CONN
-*P wbs_dat_i[0] I
-*I *419:wbs_dat_i[0] I *D user_proj_example
-*CAP
-1 wbs_dat_i[0] 0.000271935
-2 *419:wbs_dat_i[0] 0.0011819
-3 *349:16 0.0039345
-4 *349:15 0.0027526
-5 *349:13 0.0255447
-6 *349:11 0.0258167
-7 *419:wbs_dat_i[0] *381:5 0
-8 *419:wbs_dat_i[0] *413:11 0.00681271
-9 *349:16 *406:14 0.0847374
-10 *349:16 *414:16 0.00497357
-11 *419:wbs_adr_i[0] *419:wbs_dat_i[0] 0.00102191
-12 *316:11 *349:13 1.87963e-05
-13 *348:16 *349:16 0.1106
-*RES
-1 wbs_dat_i[0] *349:11 2.835
-2 *349:11 *349:13 254.79
-3 *349:13 *349:15 4.5
-4 *349:15 *349:16 163.17
-5 *349:16 *419:wbs_dat_i[0] 22.275
-*END
-
-*D_NET *350 0.144962
-*CONN
-*P wbs_dat_i[10] I
-*I *419:wbs_dat_i[10] I *D user_proj_example
-*CAP
-1 wbs_dat_i[10] 0.000772387
-2 *419:wbs_dat_i[10] 0.00106381
-3 *350:14 0.00428783
-4 *350:13 0.00322403
-5 *350:11 0.0251106
-6 *350:10 0.025883
-7 *419:wbs_dat_i[10] *419:wbs_dat_i[11] 0
-8 *419:wbs_dat_i[10] *382:9 0.0027435
-9 *350:10 wbs_dat_o[10] 0
-10 *350:11 wbs_dat_o[10] 0
-11 *350:14 *354:8 0.0356231
-12 *350:14 *356:16 0.0240595
-13 *350:14 *406:14 0.00155424
-14 *350:14 *414:16 0.0187131
-15 *419:wbs_adr_i[10] *419:wbs_dat_i[10] 0
-16 *338:12 *350:10 0.00192726
-*RES
-1 wbs_dat_i[10] *350:10 17.775
-2 *350:10 *350:11 249.39
-3 *350:11 *350:13 4.5
-4 *350:13 *350:14 85.41
-5 *350:14 *419:wbs_dat_i[10] 20.745
-*END
-
-*D_NET *351 0.160319
-*CONN
-*P wbs_dat_i[11] I
-*I *419:wbs_dat_i[11] I *D user_proj_example
-*CAP
-1 wbs_dat_i[11] 0.000245505
-2 *419:wbs_dat_i[11] 0.000744755
-3 *351:16 0.00254973
-4 *351:15 0.00180497
-5 *351:13 0.0258248
-6 *351:11 0.0260703
-7 *419:wbs_dat_i[11] *383:9 0.00148325
-8 *419:wbs_dat_i[11] *384:13 0.000634131
-9 *351:16 *359:13 0.000407989
-10 *351:16 *384:14 0.0429591
-11 *419:wbs_adr_i[10] *419:wbs_dat_i[11] 0.00460318
-12 *419:wbs_adr_i[11] *419:wbs_dat_i[11] 0.000500596
-13 *419:wbs_dat_i[10] *419:wbs_dat_i[11] 0
-14 *318:10 *351:13 0.000595217
-15 *323:16 *419:wbs_dat_i[11] 0.000356699
-16 *346:14 *351:16 0.0515385
-*RES
-1 wbs_dat_i[11] *351:11 2.655
-2 *351:11 *351:13 258.03
-3 *351:13 *351:15 4.5
-4 *351:15 *351:16 79.65
-5 *351:16 *419:wbs_dat_i[11] 31.365
-*END
-
-*D_NET *352 0.143319
-*CONN
-*P wbs_dat_i[12] I
-*I *419:wbs_dat_i[12] I *D user_proj_example
-*CAP
-1 wbs_dat_i[12] 0.00330364
-2 *419:wbs_dat_i[12] 0.00030841
-3 *352:15 0.00793422
-4 *352:14 0.00762581
-5 *352:12 0.00735965
-6 *352:11 0.00735965
-7 *352:9 0.0117538
-8 *352:7 0.0150575
-9 *419:wbs_dat_i[12] *384:13 0.000459167
-10 *419:wbs_dat_i[12] *393:11 0.000163669
-11 *352:15 *393:11 0.0788678
-12 *419:wbs_adr_i[12] *419:wbs_dat_i[12] 0.000424643
-13 *419:wbs_adr_i[13] *419:wbs_dat_i[12] 0
-14 *419:wbs_adr_i[13] *352:15 0.00270053
-15 *67:11 *352:9 0
-16 *67:14 *352:12 0
-17 *318:11 *352:7 0
-18 *318:11 *352:9 0
-*RES
-1 wbs_dat_i[12] *352:7 32.265
-2 *352:7 *352:9 117.54
-3 *352:9 *352:11 4.5
-4 *352:11 *352:12 75.87
-5 *352:12 *352:14 4.5
-6 *352:14 *352:15 115.65
-7 *352:15 *419:wbs_dat_i[12] 6.615
-*END
-
-*D_NET *353 0.114641
-*CONN
-*P wbs_dat_i[13] I
-*I *419:wbs_dat_i[13] I *D user_proj_example
-*CAP
-1 wbs_dat_i[13] 0.000187838
-2 *419:wbs_dat_i[13] 0.00223675
-3 *353:16 0.00623746
-4 *353:15 0.00400071
-5 *353:13 0.0237097
-6 *353:11 0.0238976
-7 *419:wbs_dat_i[13] *385:9 0.00485482
-8 *419:wbs_dat_i[13] *385:11 0.00257778
-9 *419:wbs_adr_i[13] *419:wbs_dat_i[13] 0
-10 *319:11 *353:13 0
-11 *320:16 *353:16 0.0469379
-*RES
-1 wbs_dat_i[13] *353:11 2.115
-2 *353:11 *353:13 236.07
-3 *353:13 *353:15 4.5
-4 *353:15 *353:16 70.47
-5 *353:16 *419:wbs_dat_i[13] 40.005
-*END
-
-*D_NET *354 0.117504
-*CONN
-*P wbs_dat_i[14] I
-*I *419:wbs_dat_i[14] I *D user_proj_example
-*CAP
-1 wbs_dat_i[14] 0.025702
-2 *419:wbs_dat_i[14] 0.000806638
-3 *354:8 0.00328358
-4 *354:7 0.00247694
-5 *354:5 0.025702
-6 *419:wbs_dat_i[14] *386:9 0.00276805
-7 *354:8 *356:16 0.00248671
-8 *354:8 *406:14 0.0177184
-9 *419:wbs_adr_i[14] *419:wbs_dat_i[14] 0.000936364
-10 *350:14 *354:8 0.0356231
-*RES
-1 wbs_dat_i[14] *354:5 255.105
-2 *354:5 *354:7 4.5
-3 *354:7 *354:8 62.37
-4 *354:8 *419:wbs_dat_i[14] 20.925
-*END
-
-*D_NET *355 0.16236
-*CONN
-*P wbs_dat_i[15] I
-*I *419:wbs_dat_i[15] I *D user_proj_example
-*CAP
-1 wbs_dat_i[15] 0.000721044
-2 *419:wbs_dat_i[15] 0.0153497
-3 *355:10 0.0153497
-4 *355:8 0.00121075
-5 *355:7 0.0019318
-6 *419:wbs_dat_i[15] *387:7 0.000818215
-7 *419:wbs_dat_i[15] *394:11 0.0581229
-8 *355:7 *387:11 0
-9 *355:8 *361:10 0.000209823
-10 *355:8 *386:14 0.0368661
-11 *355:8 *388:16 0.030276
-12 *355:8 *413:8 0
-13 *419:wbs_adr_i[15] *419:wbs_dat_i[15] 0.000583453
-14 *322:11 *355:7 0.000920636
-*RES
-1 wbs_dat_i[15] *355:7 11.745
-2 *355:7 *355:8 56.07
-3 *355:8 *355:10 4.5
-4 *355:10 *419:wbs_dat_i[15] 263.925
-*END
-
-*D_NET *356 0.095816
-*CONN
-*P wbs_dat_i[16] I
-*I *419:wbs_dat_i[16] I *D user_proj_example
-*CAP
-1 wbs_dat_i[16] 0.000187838
-2 *419:wbs_dat_i[16] 0.000791386
-3 *356:16 0.00405504
-4 *356:15 0.00326365
-5 *356:13 0.0246573
-6 *356:11 0.0248451
-7 *419:wbs_dat_i[16] *387:7 0
-8 *419:wbs_dat_i[16] *388:12 0.00148478
-9 *356:16 *359:13 0
-10 *419:wbs_adr_i[16] *419:wbs_dat_i[16] 0.000676028
-11 *419:wbs_adr_i[17] *419:wbs_dat_i[16] 0.00288466
-12 *419:wbs_cyc_i *356:13 0.000675133
-13 *315:11 *356:13 0.00574886
-14 *343:16 *356:16 0
-15 *350:14 *356:16 0.0240595
-16 *354:8 *356:16 0.00248671
-*RES
-1 wbs_dat_i[16] *356:11 2.115
-2 *356:11 *356:13 255.51
-3 *356:13 *356:15 4.5
-4 *356:15 *356:16 51.21
-5 *356:16 *419:wbs_dat_i[16] 20.925
-*END
-
-*D_NET *357 0.184401
-*CONN
-*P wbs_dat_i[17] I
-*I *419:wbs_dat_i[17] I *D user_proj_example
-*CAP
-1 wbs_dat_i[17] 0.00234997
-2 *419:wbs_dat_i[17] 0.000412325
-3 *357:17 0.0120401
-4 *357:16 0.0128904
-5 *357:11 0.00720232
-6 *357:10 0.00828965
-7 *419:wbs_dat_i[17] *389:9 0.00144233
-8 *357:10 wbs_dat_o[18] 0.0124959
-9 *357:10 *358:10 0.000704589
-10 *357:10 *410:14 0.000596807
-11 *357:11 *385:11 0
-12 *357:11 *393:11 0
-13 *357:17 *361:11 0
-14 *357:17 *362:11 0
-15 *357:17 *389:9 0.000294603
-16 *419:wbs_adr_i[17] *419:wbs_dat_i[17] 0
-17 *419:wbs_adr_i[17] *357:17 0
-18 *419:wbs_adr_i[18] *357:17 0.00175381
-19 *325:13 *357:10 0.00192726
-20 *325:17 *357:17 0.121524
-21 *329:16 *357:11 0
-22 *341:8 *357:10 0.000476597
-*RES
-1 wbs_dat_i[17] *357:10 45.315
-2 *357:10 *357:11 55.71
-3 *357:11 *357:16 21.51
-4 *357:16 *357:17 203.31
-5 *357:17 *419:wbs_dat_i[17] 6.615
-*END
-
-*D_NET *358 0.095205
-*CONN
-*P wbs_dat_i[18] I
-*I *419:wbs_dat_i[18] I *D user_proj_example
-*CAP
-1 wbs_dat_i[18] 0.00082736
-2 *419:wbs_dat_i[18] 0.00206634
-3 *358:11 0.0197407
-4 *358:10 0.0185017
-5 *419:wbs_dat_i[18] *359:13 0.0131174
-6 *419:wbs_dat_i[18] *390:9 0.000554939
-7 *419:wbs_dat_i[18] *390:11 0.00558519
-8 *358:10 wbs_dat_o[18] 0.00876594
-9 *358:10 *383:14 0.000547093
-10 *358:10 *410:14 0.00466273
-11 *358:10 *412:16 0.0011605
-12 *358:11 *382:9 0.00243048
-13 *358:11 *382:11 0.0162607
-14 *358:11 *383:11 0
-15 *419:wbs_adr_i[18] *419:wbs_dat_i[18] 0.000217884
-16 *325:13 *358:10 6.13758e-05
-17 *328:15 *358:11 0
-18 *357:10 *358:10 0.000704589
-*RES
-1 wbs_dat_i[18] *358:10 31.095
-2 *358:10 *358:11 251.19
-3 *358:11 *419:wbs_dat_i[18] 43.605
-*END
-
-*D_NET *359 0.0790191
-*CONN
-*P wbs_dat_i[19] I
-*I *419:wbs_dat_i[19] I *D user_proj_example
-*CAP
-1 wbs_dat_i[19] 0.025549
-2 *419:wbs_dat_i[19] 0.000623942
-3 *359:13 0.00271166
-4 *359:5 0.0276367
-5 *419:wbs_dat_i[19] *391:9 0.00156508
-6 *419:wbs_dat_i[19] *393:10 0
-7 *419:wbs_dat_i[19] *394:10 0
-8 *419:wbs_dat_i[19] *395:10 0.000103616
-9 *419:wbs_dat_i[19] *395:11 0.000102293
-10 *359:5 *419:wbs_dat_i[8] 0.0017799
-11 *419:wbs_adr_i[18] *359:13 0.00484868
-12 *419:wbs_adr_i[19] *419:wbs_dat_i[19] 0.000572806
-13 *419:wbs_dat_i[18] *359:13 0.0131174
-14 *351:16 *359:13 0.000407989
-15 *356:16 *359:13 0
-*RES
-1 wbs_dat_i[19] *359:5 257.265
-2 *359:5 *359:13 46.26
-3 *359:13 *419:wbs_dat_i[19] 15.975
-*END
-
-*D_NET *360 0.164983
-*CONN
-*P wbs_dat_i[1] I
-*I *419:wbs_dat_i[1] I *D user_proj_example
-*CAP
-1 wbs_dat_i[1] 0.000125413
-2 *419:wbs_dat_i[1] 0.000988536
-3 *360:16 0.010166
-4 *360:15 0.00917747
-5 *360:13 0.0252537
-6 *360:11 0.0253791
-7 *419:wbs_dat_i[1] *392:9 0.00320995
-8 *360:16 *374:16 0.089711
-9 *419:wbs_adr_i[1] *419:wbs_dat_i[1] 0.000972167
-*RES
-1 wbs_dat_i[1] *360:11 1.575
-2 *360:11 *360:13 251.91
-3 *360:13 *360:15 4.5
-4 *360:15 *360:16 154.17
-5 *360:16 *419:wbs_dat_i[1] 24.165
-*END
-
-*D_NET *361 0.11471
-*CONN
-*P wbs_dat_i[20] I
-*I *419:wbs_dat_i[20] I *D user_proj_example
-*CAP
-1 wbs_dat_i[20] 0.00106237
-2 *419:wbs_dat_i[20] 0.00160564
-3 *361:11 0.0165375
-4 *361:10 0.0159942
-5 *419:wbs_dat_i[20] *393:10 0.000431548
-6 *361:10 wbs_dat_o[18] 0.00621676
-7 *361:10 *362:10 0.00304632
-8 *361:10 *386:14 0.000734347
-9 *361:10 *388:16 8.08207e-05
-10 *361:10 *393:11 0
-11 *361:11 *362:11 0.0533765
-12 *361:11 *388:13 0
-13 *419:wbs_adr_i[17] *361:11 0.000438836
-14 *419:wbs_adr_i[20] *419:wbs_dat_i[20] 0
-15 *419:wbs_adr_i[21] *419:wbs_dat_i[20] 0
-16 *329:19 *419:wbs_dat_i[20] 0.00742646
-17 *331:13 *419:wbs_dat_i[20] 0.00754921
-18 *355:8 *361:10 0.000209823
-19 *357:17 *361:11 0
-*RES
-1 wbs_dat_i[20] *361:10 28.935
-2 *361:10 *361:11 247.77
-3 *361:11 *419:wbs_dat_i[20] 36.135
-*END
-
-*D_NET *362 0.09907
-*CONN
-*P wbs_dat_i[21] I
-*I *419:wbs_dat_i[21] I *D user_proj_example
-*CAP
-1 wbs_dat_i[21] 0.00044692
-2 *419:wbs_dat_i[21] 0.00044271
-3 *362:19 0.00400012
-4 *362:11 0.017405
-5 *362:10 0.0142945
-6 *419:wbs_dat_i[21] *394:10 0.000486786
-7 *362:10 wbs_dat_o[18] 0.003295
-8 *362:10 *394:11 0.00140141
-9 *362:19 *364:13 0.000797884
-10 *362:19 *364:25 9.32547e-06
-11 *362:19 *394:10 6.75133e-05
-12 *419:wbs_adr_i[21] *419:wbs_dat_i[21] 0
-13 *419:wbs_adr_i[22] *362:19 0
-14 *325:17 *362:11 0
-15 *330:16 *362:11 0
-16 *357:17 *362:11 0
-17 *361:10 *362:10 0.00304632
-18 *361:11 *362:11 0.0533765
-*RES
-1 wbs_dat_i[21] *362:10 19.935
-2 *362:10 *362:11 234.99
-3 *362:11 *362:19 45.27
-4 *362:19 *419:wbs_dat_i[21] 6.345
-*END
-
-*D_NET *363 0.0950924
-*CONN
-*P wbs_dat_i[22] I
-*I *419:wbs_dat_i[22] I *D user_proj_example
-*CAP
-1 wbs_dat_i[22] 0.0143507
-2 *419:wbs_dat_i[22] 0.000379046
-3 *363:14 0.00279175
-4 *363:5 0.0167634
-5 *419:wbs_dat_i[22] *395:10 0.000417739
-6 *363:5 *390:11 0.0531514
-7 *363:14 *390:9 0.000184127
-8 *363:14 *390:11 0.00255988
-9 *363:14 *393:10 0.00404104
-10 *363:14 *395:11 0
-11 *419:wbs_adr_i[22] *419:wbs_dat_i[22] 0
-12 *419:wbs_adr_i[23] *363:14 0.000453321
-*RES
-1 wbs_dat_i[22] *363:5 239.715
-2 *363:5 *363:14 45.9
-3 *363:14 *419:wbs_dat_i[22] 5.445
-*END
-
-*D_NET *364 0.0902672
-*CONN
-*P wbs_dat_i[23] I
-*I *419:wbs_dat_i[23] I *D user_proj_example
-*CAP
-1 wbs_dat_i[23] 0.000187838
-2 *419:wbs_dat_i[23] 0.000582022
-3 *364:25 0.00274069
-4 *364:13 0.0173227
-5 *364:11 0.0153519
-6 *419:wbs_dat_i[23] *396:9 0.00231387
-7 *364:25 *396:11 0.000920637
-8 *419:wbs_adr_i[22] *364:13 0
-9 *419:wbs_adr_i[23] *419:wbs_dat_i[23] 0.000285014
-10 *330:16 *364:13 0
-11 *330:17 *364:13 0.0497553
-12 *362:19 *364:13 0.000797884
-13 *362:19 *364:25 9.32547e-06
-*RES
-1 wbs_dat_i[23] *364:11 2.115
-2 *364:11 *364:13 242.19
-3 *364:13 *364:25 46.89
-4 *364:25 *419:wbs_dat_i[23] 15.705
-*END
-
-*D_NET *365 0.061483
-*CONN
-*P wbs_dat_i[24] I
-*I *419:wbs_dat_i[24] I *D user_proj_example
-*CAP
-1 wbs_dat_i[24] 0.0294545
-2 *419:wbs_dat_i[24] 0.00070864
-3 *365:5 0.0301631
-4 *419:wbs_dat_i[24] *397:14 0.000721638
-5 *419:wbs_adr_i[24] *419:wbs_dat_i[24] 0
-6 *419:wbs_adr_i[25] *419:wbs_dat_i[24] 0.000435078
-7 *333:11 *365:5 0
-*RES
-1 wbs_dat_i[24] *365:5 264.105
-2 *365:5 *419:wbs_dat_i[24] 18.495
-*END
-
-*D_NET *366 0.21046
-*CONN
-*P wbs_dat_i[25] I
-*I *419:wbs_dat_i[25] I *D user_proj_example
-*CAP
-1 wbs_dat_i[25] 0.000125413
-2 *419:wbs_dat_i[25] 0.000538418
-3 *366:13 0.0155133
-4 *366:11 0.0151003
-5 *419:wbs_dat_i[25] *419:wbs_dat_i[26] 0.000708734
-6 *419:wbs_dat_i[25] *397:14 0.000207232
-7 *419:wbs_dat_i[25] *398:10 0.00241405
-8 *419:wbs_dat_i[25] *400:10 0.00105689
-9 *366:13 *369:15 0.000736509
-10 *419:wbs_adr_i[25] *419:wbs_dat_i[25] 0.000486786
-11 *419:wbs_adr_i[26] *419:wbs_dat_i[25] 0.000262926
-12 *419:wbs_adr_i[28] *366:13 0.000168783
-13 *334:11 *366:13 0
-14 *337:19 *366:13 0.173141
-*RES
-1 wbs_dat_i[25] *366:11 1.575
-2 *366:11 *366:13 264.87
-3 *366:13 *419:wbs_dat_i[25] 23.175
-*END
-
-*D_NET *367 0.103361
-*CONN
-*P wbs_dat_i[26] I
-*I *419:wbs_dat_i[26] I *D user_proj_example
-*CAP
-1 wbs_dat_i[26] 0.000504708
-2 *419:wbs_dat_i[26] 0.000694078
-3 *367:11 0.00888234
-4 *367:10 0.00869297
-5 *419:wbs_dat_i[26] *419:wbs_dat_i[29] 0.000104911
-6 *419:wbs_dat_i[26] *399:9 0.00131958
-7 *419:wbs_dat_i[26] *400:10 0.000398922
-8 *419:wbs_dat_i[26] *401:10 0.00379236
-9 *367:10 wbs_dat_o[26] 0.000479882
-10 *367:10 *368:20 2.68519e-05
-11 *367:11 *419:wbs_dat_i[31] 0
-12 *367:11 *370:15 0.0507578
-13 *367:11 *404:9 0.00351069
-14 *367:11 *404:11 0.0178626
-15 *367:11 *405:13 0
-16 *419:wbs_adr_i[26] *419:wbs_dat_i[26] 0.000445358
-17 *419:wbs_adr_i[31] *419:wbs_dat_i[26] 0.000186509
-18 *419:wbs_adr_i[31] *367:11 0.00014321
-19 *419:wbs_dat_i[25] *419:wbs_dat_i[26] 0.000708734
-20 *339:20 *367:10 0.00242462
-21 *340:8 *367:10 0.00242462
-22 *340:11 *367:11 0
-*RES
-1 wbs_dat_i[26] *367:10 19.035
-2 *367:10 *367:11 258.93
-3 *367:11 *419:wbs_dat_i[26] 26.595
-*END
-
-*D_NET *368 0.122709
-*CONN
-*P wbs_dat_i[27] I
-*I *419:wbs_dat_i[27] I *D user_proj_example
-*CAP
-1 wbs_dat_i[27] 0.00111434
-2 *419:wbs_dat_i[27] 0.00750078
-3 *368:20 0.00861512
-4 *419:wbs_dat_i[27] *398:11 0
-5 *419:wbs_dat_i[27] *400:10 0.000500596
-6 *368:20 wbs_dat_o[26] 0.000675133
-7 *368:20 *402:20 0.00540877
-8 *419:wbs_adr_i[27] *419:wbs_dat_i[27] 0
-9 *419:wbs_adr_i[28] *419:wbs_dat_i[27] 0
-10 *159:11 *368:20 0.000552382
-11 *333:10 *419:wbs_dat_i[27] 0.000184127
-12 *333:10 *368:20 0.000186509
-13 *334:10 *368:20 0.000142991
-14 *334:11 *419:wbs_dat_i[27] 0.0197062
-15 *336:10 *368:20 0.00882811
-16 *336:11 *419:wbs_dat_i[27] 0.0574273
-17 *337:15 *368:20 0.00590613
-18 *339:20 *368:20 0.00593411
-19 *367:10 *368:20 2.68519e-05
-*RES
-1 wbs_dat_i[27] *368:20 47.475
-2 *368:20 *419:wbs_dat_i[27] 264.105
-*END
-
-*D_NET *369 0.110894
-*CONN
-*P wbs_dat_i[28] I
-*I *419:wbs_dat_i[28] I *D user_proj_example
-*CAP
-1 wbs_dat_i[28] 0.00219533
-2 *419:wbs_dat_i[28] 0.000146375
-3 *369:15 0.0156839
-4 *369:14 0.0177328
-5 *419:wbs_dat_i[28] *401:10 0.000127738
-6 *369:14 *401:11 0
-7 *369:15 *401:10 0.000393828
-8 *419:wbs_adr_i[28] *419:wbs_dat_i[28] 0
-9 *419:wbs_adr_i[28] *369:15 0
-10 *419:wbs_adr_i[29] *369:15 0.000196402
-11 *337:15 *369:14 0.0143861
-12 *337:18 *369:14 0.00155424
-13 *337:19 *369:15 0.0577137
-14 *339:20 *369:14 2.71992e-05
-15 *366:13 *369:15 0.000736509
-*RES
-1 wbs_dat_i[28] *369:14 43.515
-2 *369:14 *369:15 263.88
-3 *369:15 *419:wbs_dat_i[28] 2.025
-*END
-
-*D_NET *370 0.113621
-*CONN
-*P wbs_dat_i[29] I
-*I *419:wbs_dat_i[29] I *D user_proj_example
-*CAP
-1 wbs_dat_i[29] 0.00270397
-2 *419:wbs_dat_i[29] 0.000706488
-3 *370:15 0.0104354
-4 *370:14 0.0129536
-5 *370:11 0.00592866
-6 *419:wbs_dat_i[29] *400:10 0.000683868
-7 *419:wbs_dat_i[29] *402:9 0.00152417
-8 *370:15 *419:wbs_dat_i[31] 0
-9 *370:15 *405:13 0.00746022
-10 *419:wbs_adr_i[29] *419:wbs_dat_i[29] 0
-11 *419:wbs_adr_i[31] *419:wbs_dat_i[29] 0.000393741
-12 *419:wbs_dat_i[26] *419:wbs_dat_i[29] 0.000104911
-13 *117:11 *370:11 0.00908361
-14 *180:9 *370:11 0.0108635
-15 *244:16 *370:14 2.07232e-05
-16 *367:11 *370:15 0.0507578
-*RES
-1 wbs_dat_i[29] *370:11 46.125
-2 *370:11 *370:14 35.73
-3 *370:14 *370:15 223.29
-4 *370:15 *419:wbs_dat_i[29] 19.755
-*END
-
-*D_NET *371 0.0827699
-*CONN
-*P wbs_dat_i[2] I
-*I *419:wbs_dat_i[2] I *D user_proj_example
-*CAP
-1 wbs_dat_i[2] 0.00066129
-2 *419:wbs_dat_i[2] 0.000134844
-3 *371:14 0.0135495
-4 *371:13 0.0134146
-5 *371:11 0.0263018
-6 *371:10 0.0269631
-7 *419:wbs_dat_i[2] *403:7 0.000238215
-8 *371:10 *417:8 0.000211377
-9 *371:11 wbs_dat_o[2] 0
-10 *371:14 *419:wbs_sel_i[1] 0
-11 *419:wbs_adr_i[2] *419:wbs_dat_i[2] 0.000238215
-12 *338:10 *371:10 0.00105689
-*RES
-1 wbs_dat_i[2] *371:10 16.695
-2 *371:10 *371:11 261.99
-3 *371:11 *371:13 4.5
-4 *371:13 *371:14 143.19
-5 *371:14 *419:wbs_dat_i[2] 7.605
-*END
-
-*D_NET *372 0.209046
-*CONN
-*P wbs_dat_i[30] I
-*I *419:wbs_dat_i[30] I *D user_proj_example
-*CAP
-1 wbs_dat_i[30] 0.000125413
-2 *419:wbs_dat_i[30] 0.000645876
-3 *372:19 0.00450359
-4 *372:13 0.0195722
-5 *372:11 0.0158399
-6 *419:wbs_dat_i[30] *401:10 0.000384675
-7 *419:wbs_dat_i[30] *404:9 0.00107408
-8 *419:la_data_in[0] *372:19 0.000296905
-9 *419:la_data_in[10] *372:19 0
-10 *419:la_data_in[2] *372:19 0
-11 *419:la_data_in[8] *372:19 0.00105689
-12 *419:wbs_adr_i[30] *419:wbs_dat_i[30] 0
-13 *116:11 *372:13 0
-14 *120:19 *372:13 0.164917
-15 *179:17 *372:19 0.000384877
-16 *183:5 *372:13 0.000245503
-*RES
-1 wbs_dat_i[30] *372:11 1.575
-2 *372:11 *372:13 262.71
-3 *372:13 *372:19 48.24
-4 *372:19 *419:wbs_dat_i[30] 18.675
-*END
-
-*D_NET *373 0.201261
-*CONN
-*P wbs_dat_i[31] I
-*I *419:wbs_dat_i[31] I *D user_proj_example
-*CAP
-1 wbs_dat_i[31] 0.000226282
-2 *419:wbs_dat_i[31] 0.0046476
-3 *373:18 0.0046476
-4 *373:16 0.0048035
-5 *373:15 0.0048035
-6 *373:13 0.0120271
-7 *373:11 0.0122534
-8 *419:wbs_dat_i[31] *405:12 0.00152826
-9 *419:wbs_dat_i[31] *405:13 0.00102293
-10 *419:la_data_in[0] *419:wbs_dat_i[31] 0
-11 *419:wbs_adr_i[31] *419:wbs_dat_i[31] 0
-12 *115:11 *419:wbs_dat_i[31] 0.0448657
-13 *123:19 *373:13 0.110415
-14 *250:19 *373:13 2.04586e-05
-15 *276:19 *373:13 0
-16 *340:7 *373:13 0
-17 *367:11 *419:wbs_dat_i[31] 0
-18 *370:15 *419:wbs_dat_i[31] 0
-*RES
-1 wbs_dat_i[31] *373:11 2.475
-2 *373:11 *373:13 189.81
-3 *373:13 *373:15 4.5
-4 *373:15 *373:16 45.81
-5 *373:16 *373:18 4.5
-6 *373:18 *419:wbs_dat_i[31] 81.405
-*END
-
-*D_NET *374 0.235046
-*CONN
-*P wbs_dat_i[3] I
-*I *419:wbs_dat_i[3] I *D user_proj_example
-*CAP
-1 wbs_dat_i[3] 0.00014502
-2 *419:wbs_dat_i[3] 0.00138585
-3 *374:16 0.00379628
-4 *374:15 0.00241043
-5 *374:13 0.0253011
-6 *374:11 0.0254461
-7 *419:wbs_dat_i[3] *406:13 0
-8 *374:16 *375:8 0.0851102
-9 *419:wbs_adr_i[3] *419:wbs_dat_i[3] 0.00147072
-10 *419:wbs_adr_i[4] *419:wbs_dat_i[3] 0.000269286
-11 *341:7 *374:13 0
-12 *360:16 *374:16 0.089711
-*RES
-1 wbs_dat_i[3] *374:11 1.755
-2 *374:11 *374:13 252.09
-3 *374:13 *374:15 4.5
-4 *374:15 *374:16 136.71
-5 *374:16 *419:wbs_dat_i[3] 24.255
-*END
-
-*D_NET *375 0.215703
-*CONN
-*P wbs_dat_i[4] I
-*I *419:wbs_dat_i[4] I *D user_proj_example
-*CAP
-1 wbs_dat_i[4] 0.0253316
-2 *419:wbs_dat_i[4] 0.00125744
-3 *375:8 0.00404579
-4 *375:7 0.00278835
-5 *375:5 0.0253316
-6 *419:wbs_dat_i[4] *419:wbs_sel_i[3] 0
-7 *419:wbs_dat_i[4] *407:9 0.00123774
-8 *419:wbs_dat_i[4] *408:11 0.000918335
-9 *375:5 *416:11 0
-10 *375:8 *378:12 0.0693191
-11 *419:wbs_adr_i[4] *419:wbs_dat_i[4] 0.000362501
-12 *419:wbs_adr_i[5] *419:wbs_dat_i[4] 0
-13 *374:16 *375:8 0.0851102
-*RES
-1 wbs_dat_i[4] *375:5 252.225
-2 *375:5 *375:7 4.5
-3 *375:7 *375:8 127.35
-4 *375:8 *419:wbs_dat_i[4] 23.445
-*END
-
-*D_NET *376 0.19637
-*CONN
-*P wbs_dat_i[5] I
-*I *419:wbs_dat_i[5] I *D user_proj_example
-*CAP
-1 wbs_dat_i[5] 0.0014798
-2 *419:wbs_dat_i[5] 0.00208127
-3 *376:14 0.00574002
-4 *376:13 0.00365874
-5 *376:11 0.0242971
-6 *376:10 0.0257769
-7 *419:wbs_dat_i[5] *408:10 0.000542025
-8 *419:wbs_dat_i[5] *408:11 0
-9 *376:10 *413:8 0
-10 *376:10 *417:8 0.00150448
-11 *376:14 *377:16 0.0759018
-12 *376:14 *379:14 0.0553874
-13 *419:wbs_adr_i[5] *419:wbs_dat_i[5] 0
-14 *419:wbs_adr_i[6] *419:wbs_dat_i[5] 0
-*RES
-1 wbs_dat_i[5] *376:10 27.135
-2 *376:10 *376:11 242.19
-3 *376:11 *376:13 4.5
-4 *376:13 *376:14 109.89
-5 *376:14 *419:wbs_dat_i[5] 26.325
-*END
-
-*D_NET *377 0.150055
-*CONN
-*P wbs_dat_i[6] I
-*I *419:wbs_dat_i[6] I *D user_proj_example
-*CAP
-1 wbs_dat_i[6] 0.000245505
-2 *419:wbs_dat_i[6] 0.00149941
-3 *377:16 0.00914297
-4 *377:15 0.00764357
-5 *377:13 0.0250134
-6 *377:11 0.0252589
-7 *419:wbs_dat_i[6] *409:7 0.000403929
-8 *377:16 *379:14 0.000580213
-9 *419:wbs_adr_i[6] *419:wbs_dat_i[6] 0
-10 *419:wbs_adr_i[7] *419:wbs_dat_i[6] 0
-11 *326:13 *419:wbs_dat_i[6] 0.00435768
-12 *344:11 *377:13 7.67196e-06
-13 *376:14 *377:16 0.0759018
-*RES
-1 wbs_dat_i[6] *377:11 2.655
-2 *377:11 *377:13 249.21
-3 *377:13 *377:15 4.5
-4 *377:15 *377:16 116.37
-5 *377:16 *419:wbs_dat_i[6] 26.865
-*END
-
-*D_NET *378 0.186056
-*CONN
-*P wbs_dat_i[7] I
-*I *419:wbs_dat_i[7] I *D user_proj_example
-*CAP
-1 wbs_dat_i[7] 0.00327812
-2 *419:wbs_dat_i[7] 0.00119726
-3 *378:12 0.00418063
-4 *378:11 0.00298337
-5 *378:9 0.0221373
-6 *378:7 0.0254154
-7 *419:wbs_dat_i[7] *410:9 0.00426562
-8 *378:12 *417:14 0.0532795
-9 *419:wbs_adr_i[7] *419:wbs_dat_i[7] 0
-10 *375:8 *378:12 0.0693191
-*RES
-1 wbs_dat_i[7] *378:7 32.265
-2 *378:7 *378:9 220.68
-3 *378:9 *378:11 4.5
-4 *378:11 *378:12 108.45
-5 *378:12 *419:wbs_dat_i[7] 23.265
-*END
-
-*D_NET *379 0.131442
-*CONN
-*P wbs_dat_i[8] I
-*I *419:wbs_dat_i[8] I *D user_proj_example
-*CAP
-1 wbs_dat_i[8] 0.00133042
-2 *419:wbs_dat_i[8] 0.00148295
-3 *379:14 0.00744711
-4 *379:13 0.00596416
-5 *379:11 0.0244579
-6 *379:10 0.0257883
-7 *419:wbs_dat_i[8] *384:13 0.00161623
-8 *419:wbs_dat_i[8] *411:7 0.00039012
-9 *379:10 wbs_dat_o[8] 0.00317066
-10 *379:11 wbs_dat_o[9] 9.8457e-05
-11 *419:wbs_adr_i[8] *419:wbs_dat_i[8] 0
-12 *419:wbs_adr_i[9] *419:wbs_dat_i[8] 0
-13 *338:12 *379:10 0.00194798
-14 *359:5 *419:wbs_dat_i[8] 0.0017799
-15 *376:14 *379:14 0.0553874
-16 *377:16 *379:14 0.000580213
-*RES
-1 wbs_dat_i[8] *379:10 27.855
-2 *379:10 *379:11 243.81
-3 *379:11 *379:13 4.5
-4 *379:13 *379:14 88.29
-5 *379:14 *419:wbs_dat_i[8] 26.145
-*END
-
-*D_NET *380 0.131081
-*CONN
-*P wbs_dat_i[9] I
-*I *419:wbs_dat_i[9] I *D user_proj_example
-*CAP
-1 wbs_dat_i[9] 0.0247693
-2 *419:wbs_dat_i[9] 0.000750533
-3 *380:8 0.00665073
-4 *380:7 0.00590019
-5 *380:5 0.0247693
-6 *419:wbs_dat_i[9] wbs_dat_o[19] 0.000593299
-7 *419:wbs_dat_i[9] *412:12 0.000662347
-8 *419:wbs_dat_i[9] *412:13 0.0123365
-9 *380:5 *411:11 0
-10 *380:8 *415:14 0.0525333
-11 *419:wbs_adr_i[10] *419:wbs_dat_i[9] 0.00118072
-12 *419:wbs_adr_i[9] *419:wbs_dat_i[9] 0.000934701
-*RES
-1 wbs_dat_i[9] *380:5 246.645
-2 *380:5 *380:7 4.5
-3 *380:7 *380:8 94.77
-4 *380:8 *419:wbs_dat_i[9] 30.375
-*END
-
-*D_NET *381 0.0852526
-*CONN
-*P wbs_dat_o[0] O
-*I *419:wbs_dat_o[0] O *D user_proj_example
-*CAP
-1 wbs_dat_o[0] 0.00119134
-2 *419:wbs_dat_o[0] 0.0260072
-3 *381:8 0.0163688
-4 *381:7 0.0151775
-5 *381:5 0.0260072
-6 *381:5 *419:wbs_sel_i[0] 0.000500596
-7 *381:5 *413:11 0
-8 *419:wbs_adr_i[1] *381:5 0
-9 *419:wbs_dat_i[0] *381:5 0
-*RES
-1 *419:wbs_dat_o[0] *381:5 259.605
-2 *381:5 *381:7 4.5
-3 *381:7 *381:8 159.57
-4 *381:8 wbs_dat_o[0] 16.065
-*END
-
-*D_NET *382 0.0861607
-*CONN
-*P wbs_dat_o[10] O
-*I *419:wbs_dat_o[10] O *D user_proj_example
-*CAP
-1 wbs_dat_o[10] 0.0030143
-2 *419:wbs_dat_o[10] 0.00203445
-3 *382:14 0.0107101
-4 *382:13 0.00769577
-5 *382:11 0.0143651
-6 *382:9 0.0163996
-7 *419:wbs_adr_i[10] *382:9 0
-8 *419:wbs_adr_i[11] *382:9 0
-9 *419:wbs_dat_i[10] *382:9 0.0027435
-10 *317:11 wbs_dat_o[10] 0
-11 *325:16 *382:14 0.0105067
-12 *350:10 wbs_dat_o[10] 0
-13 *350:11 wbs_dat_o[10] 0
-14 *358:11 *382:9 0.00243048
-15 *358:11 *382:11 0.0162607
-*RES
-1 *419:wbs_dat_o[10] *382:9 32.535
-2 *382:9 *382:11 212.04
-3 *382:11 *382:13 4.5
-4 *382:13 *382:14 86.85
-5 *382:14 wbs_dat_o[10] 34.245
-*END
-
-*D_NET *383 0.15384
-*CONN
-*P wbs_dat_o[11] O
-*I *419:wbs_dat_o[11] O *D user_proj_example
-*CAP
-1 wbs_dat_o[11] 0.000788076
-2 *419:wbs_dat_o[11] 0.00306965
-3 *383:14 0.00236147
-4 *383:13 0.00157339
-5 *383:11 0.0233517
-6 *383:9 0.0264214
-7 *383:14 wbs_dat_o[18] 0.000181328
-8 *383:14 *386:14 0.0353744
-9 *383:14 *412:16 0.0505437
-10 *419:wbs_adr_i[11] *383:9 0
-11 *419:wbs_adr_i[12] *383:9 0
-12 *419:wbs_dat_i[11] *383:9 0.00148325
-13 *319:10 *383:14 0.00814424
-14 *358:10 *383:14 0.000547093
-15 *358:11 *383:11 0
-*RES
-1 *419:wbs_dat_o[11] *383:9 32.535
-2 *383:9 *383:11 232.92
-3 *383:11 *383:13 4.5
-4 *383:13 *383:14 78.93
-5 *383:14 wbs_dat_o[11] 11.385
-*END
-
-*D_NET *384 0.117267
-*CONN
-*P wbs_dat_o[12] O
-*I *419:wbs_dat_o[12] O *D user_proj_example
-*CAP
-1 wbs_dat_o[12] 0.00010579
-2 *419:wbs_dat_o[12] 0.00111222
-3 *384:17 0.0261387
-4 *384:16 0.0260329
-5 *384:14 0.00349478
-6 *384:13 0.00460699
-7 *384:13 *412:12 0.000111905
-8 *419:wbs_adr_i[13] *384:13 0.0013605
-9 *419:wbs_adr_i[19] *384:13 0.00839248
-10 *419:wbs_adr_i[8] *384:13 0.000242434
-11 *419:wbs_dat_i[11] *384:13 0.000634131
-12 *419:wbs_dat_i[12] *384:13 0.000459167
-13 *419:wbs_dat_i[8] *384:13 0.00161623
-14 *67:11 *384:17 0
-15 *323:16 *384:13 0
-16 *327:16 *384:14 0
-17 *351:16 *384:14 0.0429591
-*RES
-1 *419:wbs_dat_o[12] *384:13 38.745
-2 *384:13 *384:14 62.19
-3 *384:14 *384:16 4.5
-4 *384:16 *384:17 258.21
-5 *384:17 wbs_dat_o[12] 1.395
-*END
-
-*D_NET *385 0.0730662
-*CONN
-*P wbs_dat_o[13] O
-*I *419:wbs_dat_o[13] O *D user_proj_example
-*CAP
-1 wbs_dat_o[13] 0.00252671
-2 *419:wbs_dat_o[13] 0.00211002
-3 *385:14 0.00910166
-4 *385:13 0.00657494
-5 *385:11 0.0215957
-6 *385:9 0.0237058
-7 *419:wbs_adr_i[13] *385:9 0
-8 *419:wbs_adr_i[14] *385:9 0
-9 *419:wbs_dat_i[13] *385:9 0.00485482
-10 *419:wbs_dat_i[13] *385:11 0.00257778
-11 *319:11 wbs_dat_o[13] 0
-12 *321:13 wbs_dat_o[13] 1.87963e-05
-13 *357:11 *385:11 0
-*RES
-1 *419:wbs_dat_o[13] *385:9 32.535
-2 *385:9 *385:11 217.44
-3 *385:11 *385:13 4.5
-4 *385:13 *385:14 67.95
-5 *385:14 wbs_dat_o[13] 29.385
-*END
-
-*D_NET *386 0.137355
-*CONN
-*P wbs_dat_o[14] O
-*I *419:wbs_dat_o[14] O *D user_proj_example
-*CAP
-1 wbs_dat_o[14] 0.000751504
-2 *419:wbs_dat_o[14] 0.00302336
-3 *386:14 0.00177444
-4 *386:13 0.00102293
-5 *386:11 0.0259768
-6 *386:9 0.0290001
-7 *386:14 wbs_dat_o[18] 6.29468e-05
-8 *386:14 *413:8 0
-9 *419:wbs_adr_i[15] *386:9 0
-10 *419:wbs_dat_i[14] *386:9 0.00276805
-11 *355:8 *386:14 0.0368661
-12 *361:10 *386:14 0.000734347
-13 *383:14 *386:14 0.0353744
-*RES
-1 *419:wbs_dat_o[14] *386:9 32.535
-2 *386:9 *386:11 232.74
-3 *386:11 *386:13 4.5
-4 *386:13 *386:14 59.31
-5 *386:14 wbs_dat_o[14] 11.565
-*END
-
-*D_NET *387 0.0974756
-*CONN
-*P wbs_dat_o[15] O
-*I *419:wbs_dat_o[15] O *D user_proj_example
-*CAP
-1 wbs_dat_o[15] 0.000166523
-2 *419:wbs_dat_o[15] 0.000516299
-3 *387:11 0.0264864
-4 *387:10 0.0263199
-5 *387:8 0.00347837
-6 *387:7 0.00399466
-7 *419:wbs_adr_i[16] *387:7 0.000569644
-8 *419:wbs_dat_i[15] *387:7 0.000818215
-9 *419:wbs_dat_i[16] *387:7 0
-10 *321:16 *387:8 0.0351256
-11 *322:11 *387:11 0
-12 *355:7 *387:11 0
-*RES
-1 *419:wbs_dat_o[15] *387:7 15.165
-2 *387:7 *387:8 55.35
-3 *387:8 *387:10 4.5
-4 *387:10 *387:11 260.55
-5 *387:11 wbs_dat_o[15] 1.935
-*END
-
-*D_NET *388 0.102042
-*CONN
-*P wbs_dat_o[16] O
-*I *419:wbs_dat_o[16] O *D user_proj_example
-*CAP
-1 wbs_dat_o[16] 0.000798876
-2 *419:wbs_dat_o[16] 0.000564881
-3 *388:16 0.00340385
-4 *388:15 0.00260497
-5 *388:13 0.0244471
-6 *388:12 0.025012
-7 *419:wbs_adr_i[17] *388:12 0.00115463
-8 *419:wbs_adr_i[17] *388:13 0.0122138
-9 *419:wbs_dat_i[16] *388:12 0.00148478
-10 *355:8 *388:16 0.030276
-11 *361:10 *388:16 8.08207e-05
-12 *361:11 *388:13 0
-*RES
-1 *419:wbs_dat_o[16] *388:12 22.7407
-2 *388:12 *388:13 251.73
-3 *388:13 *388:15 4.5
-4 *388:15 *388:16 46.17
-5 *388:16 wbs_dat_o[16] 11.925
-*END
-
-*D_NET *389 0.0951863
-*CONN
-*P wbs_dat_o[17] O
-*I *419:wbs_dat_o[17] O *D user_proj_example
-*CAP
-1 wbs_dat_o[17] 0.00237777
-2 *419:wbs_dat_o[17] 0.000297394
-3 *389:13 0.0162074
-4 *389:12 0.0165259
-5 *389:9 0.00299371
-6 *389:12 *394:10 0.00428972
-7 *389:13 *419:wbs_sel_i[2] 0.00558519
-8 *419:wbs_adr_i[17] *389:9 0
-9 *419:wbs_adr_i[18] *389:9 0.000994799
-10 *419:wbs_adr_i[3] *389:13 0.00804022
-11 *419:wbs_dat_i[17] *389:9 0.00144233
-12 *318:14 *389:12 0.00293441
-13 *319:14 *389:12 0.000271992
-14 *322:14 *389:12 0.000629418
-15 *323:16 *389:12 1.55425e-05
-16 *341:11 wbs_dat_o[17] 0.00253303
-17 *341:11 *389:13 0.0292762
-18 *342:16 *389:12 0.000476634
-19 *357:17 *389:9 0.000294603
-*RES
-1 *419:wbs_dat_o[17] *389:9 13.635
-2 *389:9 *389:12 45.27
-3 *389:12 *389:13 230.94
-4 *389:13 wbs_dat_o[17] 32.085
-*END
-
-*D_NET *390 0.128326
-*CONN
-*P wbs_dat_o[18] O
-*I *419:wbs_dat_o[18] O *D user_proj_example
-*CAP
-1 wbs_dat_o[18] 0.0016297
-2 *419:wbs_dat_o[18] 0.000484929
-3 *390:11 0.0167308
-4 *390:9 0.015586
-5 *419:wbs_adr_i[18] *390:11 0
-6 *419:wbs_adr_i[19] *390:9 0
-7 *419:wbs_dat_i[18] *390:9 0.000554939
-8 *419:wbs_dat_i[18] *390:11 0.00558519
-9 *326:13 wbs_dat_o[18] 0.000840847
-10 *330:16 wbs_dat_o[18] 0
-11 *357:10 wbs_dat_o[18] 0.0124959
-12 *358:10 wbs_dat_o[18] 0.00876594
-13 *361:10 wbs_dat_o[18] 0.00621676
-14 *362:10 wbs_dat_o[18] 0.003295
-15 *363:5 *390:11 0.0531514
-16 *363:14 *390:9 0.000184127
-17 *363:14 *390:11 0.00255988
-18 *383:14 wbs_dat_o[18] 0.000181328
-19 *386:14 wbs_dat_o[18] 6.29468e-05
-*RES
-1 *419:wbs_dat_o[18] *390:9 6.885
-2 *390:9 *390:11 259.65
-3 *390:11 wbs_dat_o[18] 48.735
-*END
-
-*D_NET *391 0.0780058
-*CONN
-*P wbs_dat_o[19] O
-*I *419:wbs_dat_o[19] O *D user_proj_example
-*CAP
-1 wbs_dat_o[19] 0.01544
-2 *419:wbs_dat_o[19] 0.00107293
-3 *391:12 0.0185306
-4 *391:9 0.00416352
-5 wbs_dat_o[19] *412:13 0.0327255
-6 *391:9 *395:11 0.000492285
-7 *419:wbs_adr_i[10] wbs_dat_o[19] 0.00111704
-8 *419:wbs_adr_i[20] *391:9 0.000918335
-9 *419:wbs_dat_i[19] *391:9 0.00156508
-10 *419:wbs_dat_i[9] wbs_dat_o[19] 0.000593299
-11 *328:19 *391:9 0.00138709
-*RES
-1 *419:wbs_dat_o[19] *391:9 27.135
-2 *391:9 *391:12 31.77
-3 *391:12 wbs_dat_o[19] 249.165
-*END
-
-*D_NET *392 0.21712
-*CONN
-*P wbs_dat_o[1] O
-*I *419:wbs_dat_o[1] O *D user_proj_example
-*CAP
-1 wbs_dat_o[1] 0.00217006
-2 *419:wbs_dat_o[1] 0.00227904
-3 *392:14 0.0166041
-4 *392:13 0.0144341
-5 *392:11 0.0122607
-6 *392:9 0.0145397
-7 *392:9 *419:wbs_sel_i[1] 0
-8 *392:9 *406:13 0.00128889
-9 *419:wbs_dat_i[1] *392:9 0.00320995
-10 *324:5 *392:9 0.000208677
-11 *324:5 *392:11 0.150125
-*RES
-1 *419:wbs_dat_o[1] *392:9 32.535
-2 *392:9 *392:11 220.14
-3 *392:11 *392:13 4.5
-4 *392:13 *392:14 151.65
-5 *392:14 wbs_dat_o[1] 26.145
-*END
-
-*D_NET *393 0.15021
-*CONN
-*P wbs_dat_o[20] O
-*I *419:wbs_dat_o[20] O *D user_proj_example
-*CAP
-1 wbs_dat_o[20] 0.000168297
-2 *419:wbs_dat_o[20] 0.00141362
-3 *393:11 0.0245883
-4 *393:10 0.0258336
-5 *393:10 *395:10 0.000223811
-6 *419:wbs_adr_i[12] *393:11 0.000306879
-7 *419:wbs_adr_i[19] *393:10 0.0127444
-8 *419:wbs_adr_i[21] *393:10 0.00131493
-9 *419:wbs_adr_i[23] *393:10 0.000111905
-10 *419:wbs_dat_i[12] *393:11 0.000163669
-11 *419:wbs_dat_i[19] *393:10 0
-12 *419:wbs_dat_i[20] *393:10 0.000431548
-13 *352:15 *393:11 0.0788678
-14 *357:11 *393:11 0
-15 *361:10 *393:11 0
-16 *363:14 *393:10 0.00404104
-*RES
-1 *419:wbs_dat_o[20] *393:10 37.575
-2 *393:10 *393:11 265.59
-3 *393:11 wbs_dat_o[20] 1.935
-*END
-
-*D_NET *394 0.101714
-*CONN
-*P wbs_dat_o[21] O
-*I *419:wbs_dat_o[21] O *D user_proj_example
-*CAP
-1 wbs_dat_o[21] 0.000291157
-2 *419:wbs_dat_o[21] 0.00175947
-3 *394:11 0.0158799
-4 *394:10 0.0173482
-5 *394:10 *395:10 0
-6 *419:wbs_adr_i[22] *394:10 0.00189242
-7 *419:wbs_dat_i[15] *394:11 0.0581229
-8 *419:wbs_dat_i[19] *394:10 0
-9 *419:wbs_dat_i[21] *394:10 0.000486786
-10 *323:16 *394:10 0.000174852
-11 *362:10 *394:11 0.00140141
-12 *362:19 *394:10 6.75133e-05
-13 *389:12 *394:10 0.00428972
-*RES
-1 *419:wbs_dat_o[21] *394:10 34.875
-2 *394:10 *394:11 262.89
-3 *394:11 wbs_dat_o[21] 3.015
-*END
-
-*D_NET *395 0.197679
-*CONN
-*P wbs_dat_o[22] O
-*I *419:wbs_dat_o[22] O *D user_proj_example
-*CAP
-1 wbs_dat_o[22] 0.00010579
-2 *419:wbs_dat_o[22] 0.000920416
-3 *395:11 0.0160235
-4 *395:10 0.0168381
-5 *419:wbs_adr_i[21] *395:10 0.00105689
-6 *419:wbs_adr_i[23] *395:10 0.00163344
-7 *419:wbs_dat_i[19] *395:10 0.000103616
-8 *419:wbs_dat_i[19] *395:11 0.000102293
-9 *419:wbs_dat_i[22] *395:10 0.000417739
-10 *328:19 *395:11 0.159761
-11 *363:14 *395:11 0
-12 *391:9 *395:11 0.000492285
-13 *393:10 *395:10 0.000223811
-14 *394:10 *395:10 0
-*RES
-1 *419:wbs_dat_o[22] *395:10 24.975
-2 *395:10 *395:11 264.69
-3 *395:11 wbs_dat_o[22] 1.395
-*END
-
-*D_NET *396 0.20344
-*CONN
-*P wbs_dat_o[23] O
-*I *419:wbs_dat_o[23] O *D user_proj_example
-*CAP
-1 wbs_dat_o[23] 0.000764887
-2 *419:wbs_dat_o[23] 0.000751205
-3 *396:11 0.0145135
-4 *396:9 0.0144998
-5 *419:wbs_adr_i[24] *396:9 0.00165587
-6 *419:wbs_adr_i[24] *396:11 0
-7 *419:wbs_dat_i[23] *396:9 0.00231387
-8 *332:18 *396:11 3.45239e-05
-9 *332:19 *396:11 0.167985
-10 *364:25 *396:11 0.000920637
-*RES
-1 *419:wbs_dat_o[23] *396:9 17.865
-2 *396:9 *396:11 248.49
-3 *396:11 wbs_dat_o[23] 6.975
-*END
-
-*D_NET *397 0.188888
-*CONN
-*P wbs_dat_o[24] O
-*I *419:wbs_dat_o[24] O *D user_proj_example
-*CAP
-1 wbs_dat_o[24] 0.0129003
-2 *419:wbs_dat_o[24] 0.00177658
-3 *397:16 0.0129003
-4 *397:14 0.00177658
-5 wbs_dat_o[24] *398:11 0.0030473
-6 wbs_dat_o[24] *399:11 0.149327
-7 *397:14 *398:10 0.000559528
-8 *397:14 *399:9 0
-9 *397:14 *399:11 0.00110093
-10 *419:wbs_adr_i[25] *397:14 0.00181986
-11 *419:wbs_adr_i[26] *397:14 0.000306879
-12 *419:wbs_dat_i[24] *397:14 0.000721638
-13 *419:wbs_dat_i[25] *397:14 0.000207232
-14 *333:11 wbs_dat_o[24] 0
-15 *333:11 *397:14 0.00244352
-*RES
-1 *419:wbs_dat_o[24] *397:14 49.455
-2 *397:14 *397:16 4.5
-3 *397:16 wbs_dat_o[24] 239.805
-*END
-
-*D_NET *398 0.238888
-*CONN
-*P wbs_dat_o[25] O
-*I *419:wbs_dat_o[25] O *D user_proj_example
-*CAP
-1 wbs_dat_o[25] 0.00014502
-2 *419:wbs_dat_o[25] 0.000309145
-3 *398:17 0.00246486
-4 *398:16 0.00306992
-5 *398:11 0.00988296
-6 *398:10 0.00944203
-7 *398:11 *399:11 0
-8 *398:17 *402:11 0.0978943
-9 wbs_dat_o[24] *398:11 0.0030473
-10 *419:wbs_adr_i[26] *398:10 0.000761708
-11 *419:wbs_adr_i[27] *398:11 0.00969736
-12 *419:wbs_dat_i[25] *398:10 0.00241405
-13 *419:wbs_dat_i[27] *398:11 0
-14 *335:19 *398:11 0.000814508
-15 *336:11 *398:11 0
-16 *339:21 *398:17 0.0983853
-17 *397:14 *398:10 0.000559528
-*RES
-1 *419:wbs_dat_o[25] *398:10 18.315
-2 *398:10 *398:11 114.21
-3 *398:11 *398:16 16.11
-4 *398:16 *398:17 150.57
-5 *398:17 wbs_dat_o[25] 1.755
-*END
-
-*D_NET *399 0.199003
-*CONN
-*P wbs_dat_o[26] O
-*I *419:wbs_dat_o[26] O *D user_proj_example
-*CAP
-1 wbs_dat_o[26] 0.00329027
-2 *419:wbs_dat_o[26] 0.00111438
-3 *399:11 0.015856
-4 *399:9 0.0136801
-5 wbs_dat_o[24] *399:11 0.149327
-6 *419:wbs_adr_i[26] *399:9 0
-7 *419:wbs_adr_i[27] *399:9 0.00438658
-8 *419:wbs_adr_i[27] *399:11 6.13757e-06
-9 *419:wbs_dat_i[26] *399:9 0.00131958
-10 *126:11 wbs_dat_o[26] 0.0060762
-11 *333:11 *399:11 0
-12 *335:11 wbs_dat_o[26] 0.000469524
-13 *335:19 *399:9 9.2064e-05
-14 *335:19 *399:11 0.00112931
-15 *367:10 wbs_dat_o[26] 0.000479882
-16 *368:20 wbs_dat_o[26] 0.000675133
-17 *397:14 *399:9 0
-18 *397:14 *399:11 0.00110093
-19 *398:11 *399:11 0
-*RES
-1 *419:wbs_dat_o[26] *399:9 21.825
-2 *399:9 *399:11 229.95
-3 *399:11 wbs_dat_o[26] 49.275
-*END
-
-*D_NET *400 0.137136
-*CONN
-*P wbs_dat_o[27] O
-*I *419:wbs_dat_o[27] O *D user_proj_example
-*CAP
-1 wbs_dat_o[27] 0.00252954
-2 *419:wbs_dat_o[27] 0.000505867
-3 *400:17 0.00909687
-4 *400:16 0.00853698
-5 *400:11 0.00945452
-6 *400:10 0.00799073
-7 *400:11 *402:9 0.00341249
-8 *400:11 *402:11 0.0069393
-9 *419:wbs_adr_i[26] *400:10 1.24339e-05
-10 *419:wbs_adr_i[28] *400:10 0.00148325
-11 *419:wbs_adr_i[30] *400:11 0.00108431
-12 *419:wbs_dat_i[25] *400:10 0.00105689
-13 *419:wbs_dat_i[26] *400:10 0.000398922
-14 *419:wbs_dat_i[27] *400:10 0.000500596
-15 *419:wbs_dat_i[29] *400:10 0.000683868
-16 *170:11 wbs_dat_o[27] 0.00084136
-17 *223:21 wbs_dat_o[27] 0.00210723
-18 *223:21 *400:17 0.0801567
-19 *287:19 wbs_dat_o[27] 0.000343704
-20 *340:11 *400:11 0
-*RES
-1 *419:wbs_dat_o[27] *400:10 21.015
-2 *400:10 *400:11 115.47
-3 *400:11 *400:16 27.27
-4 *400:16 *400:17 117.54
-5 *400:17 wbs_dat_o[27] 32.085
-*END
-
-*D_NET *401 0.224785
-*CONN
-*P wbs_dat_o[28] O
-*I *419:wbs_dat_o[28] O *D user_proj_example
-*CAP
-1 wbs_dat_o[28] 0.000226282
-2 *419:wbs_dat_o[28] 0.00175684
-3 *401:11 0.0158436
-4 *401:10 0.0173742
-5 *419:la_data_in[2] *401:10 0
-6 *419:la_data_in[7] *401:11 0.000211746
-7 *419:la_oenb[2] *401:10 0.00851682
-8 *419:la_oenb[3] *401:10 0.00665184
-9 *419:wbs_adr_i[29] *401:10 0.00127866
-10 *419:wbs_adr_i[31] *401:10 3.62657e-05
-11 *419:wbs_dat_i[26] *401:10 0.00379236
-12 *419:wbs_dat_i[28] *401:10 0.000127738
-13 *419:wbs_dat_i[30] *401:10 0.000384675
-14 *177:11 *401:11 0.167494
-15 *240:5 *401:11 0.000695592
-16 *369:14 *401:11 0
-17 *369:15 *401:10 0.000393828
-*RES
-1 *419:wbs_dat_o[28] *401:10 43.155
-2 *401:10 *401:11 265.59
-3 *401:11 wbs_dat_o[28] 2.475
-*END
-
-*D_NET *402 0.195579
-*CONN
-*P wbs_dat_o[29] O
-*I *419:wbs_dat_o[29] O *D user_proj_example
-*CAP
-1 wbs_dat_o[29] 0.000786848
-2 *419:wbs_dat_o[29] 0.0011306
-3 *402:20 0.00192496
-4 *402:11 0.0114469
-5 *402:9 0.0114394
-6 *402:20 *404:14 0.0119366
-7 *419:wbs_adr_i[29] *402:9 0
-8 *419:wbs_adr_i[30] *402:9 0.000497144
-9 *419:wbs_dat_i[29] *402:9 0.00152417
-10 *305:8 *402:20 0
-11 *335:10 *402:20 0.00292198
-12 *336:10 *402:20 0.00358512
-13 *339:13 *402:20 0.0121231
-14 *339:20 *402:20 0.000235727
-15 *339:21 *402:9 0.00201389
-16 *339:21 *402:11 0.0202745
-17 *340:8 *402:20 8.28929e-05
-18 *368:20 *402:20 0.00540877
-19 *398:17 *402:11 0.0978943
-20 *400:11 *402:9 0.00341249
-21 *400:11 *402:11 0.0069393
-*RES
-1 *419:wbs_dat_o[29] *402:9 32.535
-2 *402:9 *402:11 232.74
-3 *402:11 *402:20 47.07
-4 *402:20 wbs_dat_o[29] 7.245
-*END
-
-*D_NET *403 0.239793
-*CONN
-*P wbs_dat_o[2] O
-*I *419:wbs_dat_o[2] O *D user_proj_example
-*CAP
-1 wbs_dat_o[2] 0.000736551
-2 *419:wbs_dat_o[2] 0.000550074
-3 *403:11 0.0264941
-4 *403:10 0.0257575
-5 *403:8 0.00242655
-6 *403:7 0.00297662
-7 wbs_dat_o[2] *417:8 0.000849652
-8 *403:7 *419:wbs_sel_i[2] 0.000653012
-9 *419:wbs_adr_i[2] *403:7 0
-10 *419:wbs_dat_i[2] *403:7 0.000238215
-11 *28:5 *403:8 0
-12 *316:16 *403:8 0.0892137
-13 *338:12 wbs_dat_o[2] 0.00254896
-14 *342:16 *403:8 0.0873483
-15 *371:11 wbs_dat_o[2] 0
-*RES
-1 *419:wbs_dat_o[2] *403:7 12.825
-2 *403:7 *403:8 138.69
-3 *403:8 *403:10 4.5
-4 *403:10 *403:11 256.59
-5 *403:11 wbs_dat_o[2] 19.035
-*END
-
-*D_NET *404 0.152533
-*CONN
-*P wbs_dat_o[30] O
-*I *419:wbs_dat_o[30] O *D user_proj_example
-*CAP
-1 wbs_dat_o[30] 0.000739476
-2 *419:wbs_dat_o[30] 0.00103686
-3 *404:14 0.00154847
-4 *404:11 0.00697433
-5 *404:9 0.0072022
-6 *419:wbs_adr_i[30] *404:9 0
-7 *419:wbs_adr_i[31] *404:9 0.000441905
-8 *419:wbs_dat_i[30] *404:9 0.00107408
-9 *339:13 *404:14 0.0142368
-10 *340:8 *404:14 0.0305253
-11 *340:11 *404:9 0.00249723
-12 *340:11 *404:11 0.0529468
-13 *367:11 *404:9 0.00351069
-14 *367:11 *404:11 0.0178626
-15 *402:20 *404:14 0.0119366
-*RES
-1 *419:wbs_dat_o[30] *404:9 32.535
-2 *404:9 *404:11 232.92
-3 *404:11 *404:14 48.69
-4 *404:14 wbs_dat_o[30] 11.385
-*END
-
-*D_NET *405 0.226656
-*CONN
-*P wbs_dat_o[31] O
-*I *419:wbs_dat_o[31] O *D user_proj_example
-*CAP
-1 wbs_dat_o[31] 0.00131136
-2 *419:wbs_dat_o[31] 0.000481536
-3 *405:16 0.00420659
-4 *405:15 0.00289523
-5 *405:13 0.0114655
-6 *405:12 0.011947
-7 *419:la_data_in[0] *405:12 0.00111883
-8 *419:wbs_dat_i[31] *405:12 0.00152826
-9 *419:wbs_dat_i[31] *405:13 0.00102293
-10 *115:11 *405:13 0.149818
-11 *126:8 *405:16 0.0333852
-12 *188:15 wbs_dat_o[31] 0
-13 *304:11 wbs_dat_o[31] 1.53439e-05
-14 *367:11 *405:13 0
-15 *370:15 *405:13 0.00746022
-*RES
-1 *419:wbs_dat_o[31] *405:12 21.645
-2 *405:12 *405:13 247.77
-3 *405:13 *405:15 4.5
-4 *405:15 *405:16 51.03
-5 *405:16 wbs_dat_o[31] 16.785
-*END
-
-*D_NET *406 0.2315
-*CONN
-*P wbs_dat_o[3] O
-*I *419:wbs_dat_o[3] O *D user_proj_example
-*CAP
-1 wbs_dat_o[3] 0.000187838
-2 *419:wbs_dat_o[3] 0.00164154
-3 *406:17 0.0257965
-4 *406:16 0.0256086
-5 *406:14 0.00168444
-6 *406:13 0.00332598
-7 *406:13 *419:wbs_sel_i[3] 0.000431548
-8 *406:13 *416:14 0
-9 *406:14 *414:16 0.0662108
-10 *419:wbs_adr_i[2] *406:13 0
-11 *419:wbs_adr_i[4] *406:13 0.000306879
-12 *419:wbs_dat_i[3] *406:13 0
-13 *323:16 *406:13 0.0010071
-14 *349:16 *406:14 0.0847374
-15 *350:14 *406:14 0.00155424
-16 *354:8 *406:14 0.0177184
-17 *392:9 *406:13 0.00128889
-*RES
-1 *419:wbs_dat_o[3] *406:13 37.125
-2 *406:13 *406:14 128.25
-3 *406:14 *406:16 4.5
-4 *406:16 *406:17 254.97
-5 *406:17 wbs_dat_o[3] 2.115
-*END
-
-*D_NET *407 0.21866
-*CONN
-*P wbs_dat_o[4] O
-*I *419:wbs_dat_o[4] O *D user_proj_example
-*CAP
-1 wbs_dat_o[4] 0.0011973
-2 *419:wbs_dat_o[4] 0.000226904
-3 *407:13 0.0270005
-4 *407:12 0.0258032
-5 *407:10 0.00183295
-6 *407:9 0.00205986
-7 *407:10 *409:8 0.0724274
-8 *407:10 *416:14 0.0783958
-9 *407:13 wbs_dat_o[5] 0.00190265
-10 *419:wbs_adr_i[5] *407:9 0.000421191
-11 *419:wbs_dat_i[4] *407:9 0.00123774
-12 *338:12 wbs_dat_o[4] 0.00615448
-13 *344:13 *407:13 0
-*RES
-1 *419:wbs_dat_o[4] *407:9 10.575
-2 *407:9 *407:10 115.65
-3 *407:10 *407:12 4.5
-4 *407:12 *407:13 259.83
-5 *407:13 wbs_dat_o[4] 23.895
-*END
-
-*D_NET *408 0.0895384
-*CONN
-*P wbs_dat_o[5] O
-*I *419:wbs_dat_o[5] O *D user_proj_example
-*CAP
-1 wbs_dat_o[5] 0.000914306
-2 *419:wbs_dat_o[5] 0.000380094
-3 *408:14 0.0119782
-4 *408:13 0.0110639
-5 *408:11 0.0238791
-6 *408:10 0.0242592
-7 *408:10 *409:8 0
-8 *419:wbs_adr_i[5] *408:11 0.00157531
-9 *419:wbs_adr_i[6] *408:10 0.001606
-10 *419:wbs_dat_i[4] *408:11 0.000918335
-11 *419:wbs_dat_i[5] *408:10 0.000542025
-12 *419:wbs_dat_i[5] *408:11 0
-13 *323:16 *408:10 0.00064242
-14 *325:13 *408:11 0.00939048
-15 *344:13 wbs_dat_o[5] 0.000486403
-16 *407:13 wbs_dat_o[5] 0.00190265
-*RES
-1 *419:wbs_dat_o[5] *408:10 18.855
-2 *408:10 *408:11 249.93
-3 *408:11 *408:13 4.5
-4 *408:13 *408:14 115.83
-5 *408:14 wbs_dat_o[5] 18.765
-*END
-
-*D_NET *409 0.195728
-*CONN
-*P wbs_dat_o[6] O
-*I *419:wbs_dat_o[6] O *D user_proj_example
-*CAP
-1 wbs_dat_o[6] 0.000699672
-2 *419:wbs_dat_o[6] 0.00015545
-3 *409:11 0.026884
-4 *409:10 0.0261843
-5 *409:8 0.00238374
-6 *409:7 0.00253919
-7 *409:8 *411:8 0.0616098
-8 *419:wbs_adr_i[19] *409:8 0.000186509
-9 *419:wbs_adr_i[7] *409:7 0.00119683
-10 *419:wbs_dat_i[6] *409:7 0.000403929
-11 *338:12 wbs_dat_o[6] 0.00105689
-12 *345:5 *409:11 0
-13 *407:10 *409:8 0.0724274
-14 *408:10 *409:8 0
-*RES
-1 *419:wbs_dat_o[6] *409:7 9.765
-2 *409:7 *409:8 110.79
-3 *409:8 *409:10 4.5
-4 *409:10 *409:11 260.01
-5 *409:11 wbs_dat_o[6] 16.515
-*END
-
-*D_NET *410 0.190248
-*CONN
-*P wbs_dat_o[7] O
-*I *419:wbs_dat_o[7] O *D user_proj_example
-*CAP
-1 wbs_dat_o[7] 0.000680446
-2 *419:wbs_dat_o[7] 0.00216185
-3 *410:14 0.00259571
-4 *410:13 0.00191526
-5 *410:11 0.0233991
-6 *410:9 0.0255609
-7 *410:14 *412:16 0.0596204
-8 *410:14 *417:8 0.000186509
-9 *419:wbs_adr_i[7] *410:9 0
-10 *419:wbs_adr_i[8] *410:9 0.00102881
-11 *419:wbs_dat_i[7] *410:9 0.00426562
-12 *325:13 *410:14 0.00064242
-13 *341:8 *410:14 0.0627289
-14 *346:10 *410:14 0.000202829
-15 *357:10 *410:14 0.000596807
-16 *358:10 *410:14 0.00466273
-*RES
-1 *419:wbs_dat_o[7] *410:9 32.535
-2 *410:9 *410:11 233.28
-3 *410:11 *410:13 4.5
-4 *410:13 *410:14 104.67
-5 *410:14 wbs_dat_o[7] 11.025
-*END
-
-*D_NET *411 0.154784
-*CONN
-*P wbs_dat_o[8] O
-*I *419:wbs_dat_o[8] O *D user_proj_example
-*CAP
-1 wbs_dat_o[8] 0.000435426
-2 *419:wbs_dat_o[8] 0.000190262
-3 *411:11 0.0266756
-4 *411:10 0.0262402
-5 *411:8 0.00366813
-6 *411:7 0.00385839
-7 *411:8 *419:wbs_sel_i[1] 0.023065
-8 *419:wbs_adr_i[19] *411:8 0.000543985
-9 *419:wbs_adr_i[4] *411:8 0.000559453
-10 *419:wbs_adr_i[9] *411:7 0.00039012
-11 *419:wbs_dat_i[8] *411:7 0.00039012
-12 *338:12 wbs_dat_o[8] 0.00317066
-13 *347:13 wbs_dat_o[8] 0.000816297
-14 *379:10 wbs_dat_o[8] 0.00317066
-15 *380:5 *411:11 0
-16 *409:8 *411:8 0.0616098
-*RES
-1 *419:wbs_dat_o[8] *411:7 9.585
-2 *411:7 *411:8 94.59
-3 *411:8 *411:10 4.5
-4 *411:10 *411:11 260.19
-5 *411:11 wbs_dat_o[8] 19.575
-*END
-
-*D_NET *412 0.195863
-*CONN
-*P wbs_dat_o[9] O
-*I *419:wbs_dat_o[9] O *D user_proj_example
-*CAP
-1 wbs_dat_o[9] 0.000675064
-2 *419:wbs_dat_o[9] 0.000323938
-3 *412:16 0.00237693
-4 *412:15 0.00170187
-5 *412:13 0.0158118
-6 *412:12 0.0161357
-7 wbs_dat_o[19] *412:13 0.0327255
-8 *419:wbs_adr_i[10] *412:12 0.000571817
-9 *419:wbs_adr_i[9] *412:13 0.000626032
-10 *419:wbs_dat_i[9] *412:12 0.000662347
-11 *419:wbs_dat_i[9] *412:13 0.0123365
-12 *317:10 *412:16 0.000317324
-13 *323:16 *412:12 6.29468e-05
-14 *358:10 *412:16 0.0011605
-15 *379:11 wbs_dat_o[9] 9.8457e-05
-16 *383:14 *412:16 0.0505437
-17 *384:13 *412:12 0.000111905
-18 *410:14 *412:16 0.0596204
-*RES
-1 *419:wbs_dat_o[9] *412:12 16.965
-2 *412:12 *412:13 258.03
-3 *412:13 *412:15 4.5
-4 *412:15 *412:16 91.35
-5 *412:16 wbs_dat_o[9] 11.205
-*END
-
-*D_NET *413 0.0938673
-*CONN
-*P wbs_sel_i[0] I
-*I *419:wbs_sel_i[0] I *D user_proj_example
-*CAP
-1 wbs_sel_i[0] 0.000821577
-2 *419:wbs_sel_i[0] 0.000371289
-3 *413:11 0.0257362
-4 *413:10 0.0253649
-5 *413:8 0.0161134
-6 *413:7 0.016935
-7 *419:wbs_sel_i[0] *416:14 0.000216817
-8 *413:7 *418:11 0.00027747
-9 *413:8 *416:10 0
-10 *419:wbs_adr_i[1] *419:wbs_sel_i[0] 0.000500596
-11 *419:wbs_dat_i[0] *413:11 0.00681271
-12 *317:10 *413:8 0
-13 *319:10 *413:8 0
-14 *323:16 *419:wbs_sel_i[0] 0.000216817
-15 *346:10 *413:8 0
-16 *355:8 *413:8 0
-17 *376:10 *413:8 0
-18 *381:5 *419:wbs_sel_i[0] 0.000500596
-19 *381:5 *413:11 0
-20 *386:14 *413:8 0
-*RES
-1 wbs_sel_i[0] *413:7 13.365
-2 *413:7 *413:8 154.71
-3 *413:8 *413:10 4.5
-4 *413:10 *413:11 255.87
-5 *413:11 *419:wbs_sel_i[0] 18.315
-*END
-
-*D_NET *414 0.181941
-*CONN
-*P wbs_sel_i[1] I
-*I *419:wbs_sel_i[1] I *D user_proj_example
-*CAP
-1 wbs_sel_i[1] 0.00020706
-2 *419:wbs_sel_i[1] 0.00220472
-3 *414:21 0.00344014
-4 *414:16 0.00628637
-5 *414:15 0.00505095
-6 *414:13 0.0256032
-7 *414:11 0.0258102
-8 *419:wbs_adr_i[2] *419:wbs_sel_i[1] 0.00037631
-9 *321:13 *414:21 0
-10 *349:16 *414:16 0.00497357
-11 *350:14 *414:16 0.0187131
-12 *371:14 *419:wbs_sel_i[1] 0
-13 *392:9 *419:wbs_sel_i[1] 0
-14 *406:14 *414:16 0.0662108
-15 *411:8 *419:wbs_sel_i[1] 0.023065
-*RES
-1 wbs_sel_i[1] *414:11 2.295
-2 *414:11 *414:13 255.15
-3 *414:13 *414:15 4.5
-4 *414:15 *414:16 117.45
-5 *414:16 *414:21 20.25
-6 *414:21 *419:wbs_sel_i[1] 42.795
-*END
-
-*D_NET *415 0.14123
-*CONN
-*P wbs_sel_i[2] I
-*I *419:wbs_sel_i[2] I *D user_proj_example
-*CAP
-1 wbs_sel_i[2] 0.00120466
-2 *419:wbs_sel_i[2] 0.00121072
-3 *415:14 0.0103593
-4 *415:13 0.00914858
-5 *415:11 0.0240868
-6 *415:10 0.0252915
-7 *415:11 *416:10 0.000117381
-8 *419:wbs_adr_i[3] *419:wbs_sel_i[2] 0.00185559
-9 *338:12 *415:10 0.00789556
-10 *341:11 *419:wbs_sel_i[2] 0.00128889
-11 *342:13 *415:11 0
-12 *380:8 *415:14 0.0525333
-13 *389:13 *419:wbs_sel_i[2] 0.00558519
-14 *403:7 *419:wbs_sel_i[2] 0.000653012
-*RES
-1 wbs_sel_i[2] *415:10 26.415
-2 *415:10 *415:11 240.57
-3 *415:11 *415:13 4.5
-4 *415:13 *415:14 128.79
-5 *415:14 *419:wbs_sel_i[2] 29.925
-*END
-
-*D_NET *416 0.217826
-*CONN
-*P wbs_sel_i[3] I
-*I *419:wbs_sel_i[3] I *D user_proj_example
-*CAP
-1 wbs_sel_i[3] 0.000718811
-2 *419:wbs_sel_i[3] 0.000285019
-3 *416:14 0.00285398
-4 *416:13 0.00256896
-5 *416:11 0.0259532
-6 *416:10 0.026672
-7 *416:10 *417:8 0.000462387
-8 *416:14 *418:14 0.0777744
-9 *419:wbs_adr_i[4] *419:wbs_sel_i[3] 0.000362501
-10 *419:wbs_dat_i[4] *419:wbs_sel_i[3] 0
-11 *419:wbs_sel_i[0] *416:14 0.000216817
-12 *323:16 *416:14 0
-13 *342:13 *416:10 0.0010127
-14 *375:5 *416:11 0
-15 *406:13 *419:wbs_sel_i[3] 0.000431548
-16 *406:13 *416:14 0
-17 *407:10 *416:14 0.0783958
-18 *413:8 *416:10 0
-19 *415:11 *416:10 0.000117381
-*RES
-1 wbs_sel_i[3] *416:10 21.015
-2 *416:10 *416:11 258.21
-3 *416:11 *416:13 4.5
-4 *416:13 *416:14 126.99
-5 *416:14 *419:wbs_sel_i[3] 10.125
-*END
-
-*D_NET *417 0.151237
-*CONN
-*P wbs_stb_i I
-*I *419:wbs_stb_i I *D user_proj_example
-*CAP
-1 wbs_stb_i 0.000686636
-2 *419:wbs_stb_i 0.00146539
-3 *417:14 0.0056122
-4 *417:13 0.00414681
-5 *417:11 0.0247072
-6 *417:10 0.0247072
-7 *417:8 0.00517514
-8 *417:7 0.00586178
-9 *419:wbs_stb_i *419:wbs_we_i 0
-10 *419:wbs_stb_i *418:14 0.000236245
-11 *417:8 *418:10 0.00180285
-12 wbs_dat_o[2] *417:8 0.000849652
-13 *419:wbs_adr_i[0] *419:wbs_stb_i 0
-14 *419:wbs_cyc_i *419:wbs_stb_i 0.000490239
-15 *315:11 *419:wbs_stb_i 0.00840847
-16 *323:16 *419:wbs_stb_i 5.90613e-05
-17 *338:10 *417:8 0.000417055
-18 *338:12 *417:8 0.000397886
-19 *341:8 *417:8 0.0105688
-20 *371:10 *417:8 0.000211377
-21 *376:10 *417:8 0.00150448
-22 *378:12 *417:14 0.0532795
-23 *410:14 *417:8 0.000186509
-24 *416:10 *417:8 0.000462387
-*RES
-1 wbs_stb_i *417:7 11.205
-2 *417:7 *417:8 89.01
-3 *417:8 *417:10 4.5
-4 *417:10 *417:11 245.97
-5 *417:11 *417:13 4.5
-6 *417:13 *417:14 77.13
-7 *417:14 *419:wbs_stb_i 34.515
-*END
-
-*D_NET *418 0.156108
-*CONN
-*P wbs_we_i I
-*I *419:wbs_we_i I *D user_proj_example
-*CAP
-1 wbs_we_i 0.00130771
-2 *419:wbs_we_i 0.000386439
-3 *418:14 0.00989499
-4 *418:13 0.00950856
-5 *418:11 0.0259095
-6 *418:10 0.0272172
-7 *419:wbs_adr_i[0] *419:wbs_we_i 0.00131958
-8 *419:wbs_stb_i *419:wbs_we_i 0
-9 *419:wbs_stb_i *418:14 0.000236245
-10 *28:5 *418:14 0
-11 *316:13 *418:10 0.000472977
-12 *322:14 *418:14 0
-13 *323:16 *418:14 0
-14 *327:13 *418:11 0
-15 *413:7 *418:11 0.00027747
-16 *416:14 *418:14 0.0777744
-17 *417:8 *418:10 0.00180285
-*RES
-1 wbs_we_i *418:10 28.215
-2 *418:10 *418:11 259.29
-3 *418:11 *418:13 4.5
-4 *418:13 *418:14 153.09
-5 *418:14 *419:wbs_we_i 10.305
+1 wb_rst_i *314:5 262.665
+2 *314:5 *314:7 4.5
+3 *314:7 *314:8 262.53
+4 *314:8 *314:10 4.5
+5 *314:10 *314:11 54.99
+6 *314:11 *419:wb_rst_i 6.525
*END
diff --git a/spi/lvs/user_project_wrapper.spice b/spi/lvs/user_project_wrapper.spice
index df208e3..8e480df 100644
--- a/spi/lvs/user_project_wrapper.spice
+++ b/spi/lvs/user_project_wrapper.spice
@@ -1,7 +1,7 @@
* NGSPICE file created from user_project_wrapper.ext - technology: gf180mcuC
-* Black-box entry subcircuit for user_proj_example abstract view
-.subckt user_proj_example io_in[0] io_in[10] io_in[11] io_in[12] io_in[13] io_in[14]
+* Black-box entry subcircuit for wrapped_vga_clock abstract view
+.subckt wrapped_vga_clock io_in[0] io_in[10] io_in[11] io_in[12] io_in[13] io_in[14]
+ io_in[15] io_in[16] io_in[17] io_in[18] io_in[19] io_in[1] io_in[20] io_in[21] io_in[22]
+ io_in[23] io_in[24] io_in[25] io_in[26] io_in[27] io_in[28] io_in[29] io_in[2] io_in[30]
+ io_in[31] io_in[32] io_in[33] io_in[34] io_in[35] io_in[36] io_in[37] io_in[3] io_in[4]
@@ -15,55 +15,7 @@
+ io_out[22] io_out[23] io_out[24] io_out[25] io_out[26] io_out[27] io_out[28] io_out[29]
+ io_out[2] io_out[30] io_out[31] io_out[32] io_out[33] io_out[34] io_out[35] io_out[36]
+ io_out[37] io_out[3] io_out[4] io_out[5] io_out[6] io_out[7] io_out[8] io_out[9]
-+ irq[0] irq[1] irq[2] la_data_in[0] la_data_in[10] la_data_in[11] la_data_in[12]
-+ la_data_in[13] la_data_in[14] la_data_in[15] la_data_in[16] la_data_in[17] la_data_in[18]
-+ la_data_in[19] la_data_in[1] la_data_in[20] la_data_in[21] la_data_in[22] la_data_in[23]
-+ la_data_in[24] la_data_in[25] la_data_in[26] la_data_in[27] la_data_in[28] la_data_in[29]
-+ la_data_in[2] la_data_in[30] la_data_in[31] la_data_in[32] la_data_in[33] la_data_in[34]
-+ la_data_in[35] la_data_in[36] la_data_in[37] la_data_in[38] la_data_in[39] la_data_in[3]
-+ la_data_in[40] la_data_in[41] la_data_in[42] la_data_in[43] la_data_in[44] la_data_in[45]
-+ la_data_in[46] la_data_in[47] la_data_in[48] la_data_in[49] la_data_in[4] la_data_in[50]
-+ la_data_in[51] la_data_in[52] la_data_in[53] la_data_in[54] la_data_in[55] la_data_in[56]
-+ la_data_in[57] la_data_in[58] la_data_in[59] la_data_in[5] la_data_in[60] la_data_in[61]
-+ la_data_in[62] la_data_in[63] la_data_in[6] la_data_in[7] la_data_in[8] la_data_in[9]
-+ la_data_out[0] la_data_out[10] la_data_out[11] la_data_out[12] la_data_out[13] la_data_out[14]
-+ la_data_out[15] la_data_out[16] la_data_out[17] la_data_out[18] la_data_out[19]
-+ la_data_out[1] la_data_out[20] la_data_out[21] la_data_out[22] la_data_out[23] la_data_out[24]
-+ la_data_out[25] la_data_out[26] la_data_out[27] la_data_out[28] la_data_out[29]
-+ la_data_out[2] la_data_out[30] la_data_out[31] la_data_out[32] la_data_out[33] la_data_out[34]
-+ la_data_out[35] la_data_out[36] la_data_out[37] la_data_out[38] la_data_out[39]
-+ la_data_out[3] la_data_out[40] la_data_out[41] la_data_out[42] la_data_out[43] la_data_out[44]
-+ la_data_out[45] la_data_out[46] la_data_out[47] la_data_out[48] la_data_out[49]
-+ la_data_out[4] la_data_out[50] la_data_out[51] la_data_out[52] la_data_out[53] la_data_out[54]
-+ la_data_out[55] la_data_out[56] la_data_out[57] la_data_out[58] la_data_out[59]
-+ la_data_out[5] la_data_out[60] la_data_out[61] la_data_out[62] la_data_out[63] la_data_out[6]
-+ la_data_out[7] la_data_out[8] la_data_out[9] la_oenb[0] la_oenb[10] la_oenb[11]
-+ la_oenb[12] la_oenb[13] la_oenb[14] la_oenb[15] la_oenb[16] la_oenb[17] la_oenb[18]
-+ la_oenb[19] la_oenb[1] la_oenb[20] la_oenb[21] la_oenb[22] la_oenb[23] la_oenb[24]
-+ la_oenb[25] la_oenb[26] la_oenb[27] la_oenb[28] la_oenb[29] la_oenb[2] la_oenb[30]
-+ la_oenb[31] la_oenb[32] la_oenb[33] la_oenb[34] la_oenb[35] la_oenb[36] la_oenb[37]
-+ la_oenb[38] la_oenb[39] la_oenb[3] la_oenb[40] la_oenb[41] la_oenb[42] la_oenb[43]
-+ la_oenb[44] la_oenb[45] la_oenb[46] la_oenb[47] la_oenb[48] la_oenb[49] la_oenb[4]
-+ la_oenb[50] la_oenb[51] la_oenb[52] la_oenb[53] la_oenb[54] la_oenb[55] la_oenb[56]
-+ la_oenb[57] la_oenb[58] la_oenb[59] la_oenb[5] la_oenb[60] la_oenb[61] la_oenb[62]
-+ la_oenb[63] la_oenb[6] la_oenb[7] la_oenb[8] la_oenb[9] vdd vss wb_clk_i wb_rst_i
-+ wbs_ack_o wbs_adr_i[0] wbs_adr_i[10] wbs_adr_i[11] wbs_adr_i[12] wbs_adr_i[13] wbs_adr_i[14]
-+ wbs_adr_i[15] wbs_adr_i[16] wbs_adr_i[17] wbs_adr_i[18] wbs_adr_i[19] wbs_adr_i[1]
-+ wbs_adr_i[20] wbs_adr_i[21] wbs_adr_i[22] wbs_adr_i[23] wbs_adr_i[24] wbs_adr_i[25]
-+ wbs_adr_i[26] wbs_adr_i[27] wbs_adr_i[28] wbs_adr_i[29] wbs_adr_i[2] wbs_adr_i[30]
-+ wbs_adr_i[31] wbs_adr_i[3] wbs_adr_i[4] wbs_adr_i[5] wbs_adr_i[6] wbs_adr_i[7] wbs_adr_i[8]
-+ wbs_adr_i[9] wbs_cyc_i wbs_dat_i[0] wbs_dat_i[10] wbs_dat_i[11] wbs_dat_i[12] wbs_dat_i[13]
-+ wbs_dat_i[14] wbs_dat_i[15] wbs_dat_i[16] wbs_dat_i[17] wbs_dat_i[18] wbs_dat_i[19]
-+ wbs_dat_i[1] wbs_dat_i[20] wbs_dat_i[21] wbs_dat_i[22] wbs_dat_i[23] wbs_dat_i[24]
-+ wbs_dat_i[25] wbs_dat_i[26] wbs_dat_i[27] wbs_dat_i[28] wbs_dat_i[29] wbs_dat_i[2]
-+ wbs_dat_i[30] wbs_dat_i[31] wbs_dat_i[3] wbs_dat_i[4] wbs_dat_i[5] wbs_dat_i[6]
-+ wbs_dat_i[7] wbs_dat_i[8] wbs_dat_i[9] wbs_dat_o[0] wbs_dat_o[10] wbs_dat_o[11]
-+ wbs_dat_o[12] wbs_dat_o[13] wbs_dat_o[14] wbs_dat_o[15] wbs_dat_o[16] wbs_dat_o[17]
-+ wbs_dat_o[18] wbs_dat_o[19] wbs_dat_o[1] wbs_dat_o[20] wbs_dat_o[21] wbs_dat_o[22]
-+ wbs_dat_o[23] wbs_dat_o[24] wbs_dat_o[25] wbs_dat_o[26] wbs_dat_o[27] wbs_dat_o[28]
-+ wbs_dat_o[29] wbs_dat_o[2] wbs_dat_o[30] wbs_dat_o[31] wbs_dat_o[3] wbs_dat_o[4]
-+ wbs_dat_o[5] wbs_dat_o[6] wbs_dat_o[7] wbs_dat_o[8] wbs_dat_o[9] wbs_sel_i[0] wbs_sel_i[1]
-+ wbs_sel_i[2] wbs_sel_i[3] wbs_stb_i wbs_we_i
++ vdd vss wb_clk_i wb_rst_i
.ends
.subckt user_project_wrapper io_in[0] io_in[10] io_in[11] io_in[12] io_in[13] io_in[14]
@@ -129,11 +81,11 @@
+ wbs_dat_o[28] wbs_dat_o[29] wbs_dat_o[2] wbs_dat_o[30] wbs_dat_o[31] wbs_dat_o[3]
+ wbs_dat_o[4] wbs_dat_o[5] wbs_dat_o[6] wbs_dat_o[7] wbs_dat_o[8] wbs_dat_o[9] wbs_sel_i[0]
+ wbs_sel_i[1] wbs_sel_i[2] wbs_sel_i[3] wbs_stb_i wbs_we_i
-Xmprj io_in[0] io_in[10] io_in[11] io_in[12] io_in[13] io_in[14] io_in[15] io_in[16]
-+ io_in[17] io_in[18] io_in[19] io_in[1] io_in[20] io_in[21] io_in[22] io_in[23] io_in[24]
-+ io_in[25] io_in[26] io_in[27] io_in[28] io_in[29] io_in[2] io_in[30] io_in[31] io_in[32]
-+ io_in[33] io_in[34] io_in[35] io_in[36] io_in[37] io_in[3] io_in[4] io_in[5] io_in[6]
-+ io_in[7] io_in[8] io_in[9] io_oeb[0] io_oeb[10] io_oeb[11] io_oeb[12] io_oeb[13]
+Xwrapped_vga_clock io_in[0] io_in[10] io_in[11] io_in[12] io_in[13] io_in[14] io_in[15]
++ io_in[16] io_in[17] io_in[18] io_in[19] io_in[1] io_in[20] io_in[21] io_in[22] io_in[23]
++ io_in[24] io_in[25] io_in[26] io_in[27] io_in[28] io_in[29] io_in[2] io_in[30] io_in[31]
++ io_in[32] io_in[33] io_in[34] io_in[35] io_in[36] io_in[37] io_in[3] io_in[4] io_in[5]
++ io_in[6] io_in[7] io_in[8] io_in[9] io_oeb[0] io_oeb[10] io_oeb[11] io_oeb[12] io_oeb[13]
+ io_oeb[14] io_oeb[15] io_oeb[16] io_oeb[17] io_oeb[18] io_oeb[19] io_oeb[1] io_oeb[20]
+ io_oeb[21] io_oeb[22] io_oeb[23] io_oeb[24] io_oeb[25] io_oeb[26] io_oeb[27] io_oeb[28]
+ io_oeb[29] io_oeb[2] io_oeb[30] io_oeb[31] io_oeb[32] io_oeb[33] io_oeb[34] io_oeb[35]
@@ -142,55 +94,7 @@
+ io_out[16] io_out[17] io_out[18] io_out[19] io_out[1] io_out[20] io_out[21] io_out[22]
+ io_out[23] io_out[24] io_out[25] io_out[26] io_out[27] io_out[28] io_out[29] io_out[2]
+ io_out[30] io_out[31] io_out[32] io_out[33] io_out[34] io_out[35] io_out[36] io_out[37]
-+ io_out[3] io_out[4] io_out[5] io_out[6] io_out[7] io_out[8] io_out[9] user_irq[0]
-+ user_irq[1] user_irq[2] la_data_in[0] la_data_in[10] la_data_in[11] la_data_in[12]
-+ la_data_in[13] la_data_in[14] la_data_in[15] la_data_in[16] la_data_in[17] la_data_in[18]
-+ la_data_in[19] la_data_in[1] la_data_in[20] la_data_in[21] la_data_in[22] la_data_in[23]
-+ la_data_in[24] la_data_in[25] la_data_in[26] la_data_in[27] la_data_in[28] la_data_in[29]
-+ la_data_in[2] la_data_in[30] la_data_in[31] la_data_in[32] la_data_in[33] la_data_in[34]
-+ la_data_in[35] la_data_in[36] la_data_in[37] la_data_in[38] la_data_in[39] la_data_in[3]
-+ la_data_in[40] la_data_in[41] la_data_in[42] la_data_in[43] la_data_in[44] la_data_in[45]
-+ la_data_in[46] la_data_in[47] la_data_in[48] la_data_in[49] la_data_in[4] la_data_in[50]
-+ la_data_in[51] la_data_in[52] la_data_in[53] la_data_in[54] la_data_in[55] la_data_in[56]
-+ la_data_in[57] la_data_in[58] la_data_in[59] la_data_in[5] la_data_in[60] la_data_in[61]
-+ la_data_in[62] la_data_in[63] la_data_in[6] la_data_in[7] la_data_in[8] la_data_in[9]
-+ la_data_out[0] la_data_out[10] la_data_out[11] la_data_out[12] la_data_out[13] la_data_out[14]
-+ la_data_out[15] la_data_out[16] la_data_out[17] la_data_out[18] la_data_out[19]
-+ la_data_out[1] la_data_out[20] la_data_out[21] la_data_out[22] la_data_out[23] la_data_out[24]
-+ la_data_out[25] la_data_out[26] la_data_out[27] la_data_out[28] la_data_out[29]
-+ la_data_out[2] la_data_out[30] la_data_out[31] la_data_out[32] la_data_out[33] la_data_out[34]
-+ la_data_out[35] la_data_out[36] la_data_out[37] la_data_out[38] la_data_out[39]
-+ la_data_out[3] la_data_out[40] la_data_out[41] la_data_out[42] la_data_out[43] la_data_out[44]
-+ la_data_out[45] la_data_out[46] la_data_out[47] la_data_out[48] la_data_out[49]
-+ la_data_out[4] la_data_out[50] la_data_out[51] la_data_out[52] la_data_out[53] la_data_out[54]
-+ la_data_out[55] la_data_out[56] la_data_out[57] la_data_out[58] la_data_out[59]
-+ la_data_out[5] la_data_out[60] la_data_out[61] la_data_out[62] la_data_out[63] la_data_out[6]
-+ la_data_out[7] la_data_out[8] la_data_out[9] la_oenb[0] la_oenb[10] la_oenb[11]
-+ la_oenb[12] la_oenb[13] la_oenb[14] la_oenb[15] la_oenb[16] la_oenb[17] la_oenb[18]
-+ la_oenb[19] la_oenb[1] la_oenb[20] la_oenb[21] la_oenb[22] la_oenb[23] la_oenb[24]
-+ la_oenb[25] la_oenb[26] la_oenb[27] la_oenb[28] la_oenb[29] la_oenb[2] la_oenb[30]
-+ la_oenb[31] la_oenb[32] la_oenb[33] la_oenb[34] la_oenb[35] la_oenb[36] la_oenb[37]
-+ la_oenb[38] la_oenb[39] la_oenb[3] la_oenb[40] la_oenb[41] la_oenb[42] la_oenb[43]
-+ la_oenb[44] la_oenb[45] la_oenb[46] la_oenb[47] la_oenb[48] la_oenb[49] la_oenb[4]
-+ la_oenb[50] la_oenb[51] la_oenb[52] la_oenb[53] la_oenb[54] la_oenb[55] la_oenb[56]
-+ la_oenb[57] la_oenb[58] la_oenb[59] la_oenb[5] la_oenb[60] la_oenb[61] la_oenb[62]
-+ la_oenb[63] la_oenb[6] la_oenb[7] la_oenb[8] la_oenb[9] vdd vss wb_clk_i wb_rst_i
-+ wbs_ack_o wbs_adr_i[0] wbs_adr_i[10] wbs_adr_i[11] wbs_adr_i[12] wbs_adr_i[13] wbs_adr_i[14]
-+ wbs_adr_i[15] wbs_adr_i[16] wbs_adr_i[17] wbs_adr_i[18] wbs_adr_i[19] wbs_adr_i[1]
-+ wbs_adr_i[20] wbs_adr_i[21] wbs_adr_i[22] wbs_adr_i[23] wbs_adr_i[24] wbs_adr_i[25]
-+ wbs_adr_i[26] wbs_adr_i[27] wbs_adr_i[28] wbs_adr_i[29] wbs_adr_i[2] wbs_adr_i[30]
-+ wbs_adr_i[31] wbs_adr_i[3] wbs_adr_i[4] wbs_adr_i[5] wbs_adr_i[6] wbs_adr_i[7] wbs_adr_i[8]
-+ wbs_adr_i[9] wbs_cyc_i wbs_dat_i[0] wbs_dat_i[10] wbs_dat_i[11] wbs_dat_i[12] wbs_dat_i[13]
-+ wbs_dat_i[14] wbs_dat_i[15] wbs_dat_i[16] wbs_dat_i[17] wbs_dat_i[18] wbs_dat_i[19]
-+ wbs_dat_i[1] wbs_dat_i[20] wbs_dat_i[21] wbs_dat_i[22] wbs_dat_i[23] wbs_dat_i[24]
-+ wbs_dat_i[25] wbs_dat_i[26] wbs_dat_i[27] wbs_dat_i[28] wbs_dat_i[29] wbs_dat_i[2]
-+ wbs_dat_i[30] wbs_dat_i[31] wbs_dat_i[3] wbs_dat_i[4] wbs_dat_i[5] wbs_dat_i[6]
-+ wbs_dat_i[7] wbs_dat_i[8] wbs_dat_i[9] wbs_dat_o[0] wbs_dat_o[10] wbs_dat_o[11]
-+ wbs_dat_o[12] wbs_dat_o[13] wbs_dat_o[14] wbs_dat_o[15] wbs_dat_o[16] wbs_dat_o[17]
-+ wbs_dat_o[18] wbs_dat_o[19] wbs_dat_o[1] wbs_dat_o[20] wbs_dat_o[21] wbs_dat_o[22]
-+ wbs_dat_o[23] wbs_dat_o[24] wbs_dat_o[25] wbs_dat_o[26] wbs_dat_o[27] wbs_dat_o[28]
-+ wbs_dat_o[29] wbs_dat_o[2] wbs_dat_o[30] wbs_dat_o[31] wbs_dat_o[3] wbs_dat_o[4]
-+ wbs_dat_o[5] wbs_dat_o[6] wbs_dat_o[7] wbs_dat_o[8] wbs_dat_o[9] wbs_sel_i[0] wbs_sel_i[1]
-+ wbs_sel_i[2] wbs_sel_i[3] wbs_stb_i wbs_we_i user_proj_example
++ io_out[3] io_out[4] io_out[5] io_out[6] io_out[7] io_out[8] io_out[9] vdd vss wb_clk_i
++ wb_rst_i wrapped_vga_clock
.ends
diff --git a/verilog/gl/user_project_wrapper.v b/verilog/gl/user_project_wrapper.v
index c47bee1..19e3e48 100644
--- a/verilog/gl/user_project_wrapper.v
+++ b/verilog/gl/user_project_wrapper.v
@@ -40,14 +40,10 @@
input [3:0] wbs_sel_i;
- user_proj_example mprj (.vdd(vdd),
+ wrapped_vga_clock wrapped_vga_clock (.vdd(vdd),
.vss(vss),
.wb_clk_i(wb_clk_i),
.wb_rst_i(wb_rst_i),
- .wbs_ack_o(wbs_ack_o),
- .wbs_cyc_i(wbs_cyc_i),
- .wbs_stb_i(wbs_stb_i),
- .wbs_we_i(wbs_we_i),
.io_in({io_in[37],
io_in[36],
io_in[35],
@@ -161,300 +157,5 @@
io_out[3],
io_out[2],
io_out[1],
- io_out[0]}),
- .irq({user_irq[2],
- user_irq[1],
- user_irq[0]}),
- .la_data_in({la_data_in[63],
- la_data_in[62],
- la_data_in[61],
- la_data_in[60],
- la_data_in[59],
- la_data_in[58],
- la_data_in[57],
- la_data_in[56],
- la_data_in[55],
- la_data_in[54],
- la_data_in[53],
- la_data_in[52],
- la_data_in[51],
- la_data_in[50],
- la_data_in[49],
- la_data_in[48],
- la_data_in[47],
- la_data_in[46],
- la_data_in[45],
- la_data_in[44],
- la_data_in[43],
- la_data_in[42],
- la_data_in[41],
- la_data_in[40],
- la_data_in[39],
- la_data_in[38],
- la_data_in[37],
- la_data_in[36],
- la_data_in[35],
- la_data_in[34],
- la_data_in[33],
- la_data_in[32],
- la_data_in[31],
- la_data_in[30],
- la_data_in[29],
- la_data_in[28],
- la_data_in[27],
- la_data_in[26],
- la_data_in[25],
- la_data_in[24],
- la_data_in[23],
- la_data_in[22],
- la_data_in[21],
- la_data_in[20],
- la_data_in[19],
- la_data_in[18],
- la_data_in[17],
- la_data_in[16],
- la_data_in[15],
- la_data_in[14],
- la_data_in[13],
- la_data_in[12],
- la_data_in[11],
- la_data_in[10],
- la_data_in[9],
- la_data_in[8],
- la_data_in[7],
- la_data_in[6],
- la_data_in[5],
- la_data_in[4],
- la_data_in[3],
- la_data_in[2],
- la_data_in[1],
- la_data_in[0]}),
- .la_data_out({la_data_out[63],
- la_data_out[62],
- la_data_out[61],
- la_data_out[60],
- la_data_out[59],
- la_data_out[58],
- la_data_out[57],
- la_data_out[56],
- la_data_out[55],
- la_data_out[54],
- la_data_out[53],
- la_data_out[52],
- la_data_out[51],
- la_data_out[50],
- la_data_out[49],
- la_data_out[48],
- la_data_out[47],
- la_data_out[46],
- la_data_out[45],
- la_data_out[44],
- la_data_out[43],
- la_data_out[42],
- la_data_out[41],
- la_data_out[40],
- la_data_out[39],
- la_data_out[38],
- la_data_out[37],
- la_data_out[36],
- la_data_out[35],
- la_data_out[34],
- la_data_out[33],
- la_data_out[32],
- la_data_out[31],
- la_data_out[30],
- la_data_out[29],
- la_data_out[28],
- la_data_out[27],
- la_data_out[26],
- la_data_out[25],
- la_data_out[24],
- la_data_out[23],
- la_data_out[22],
- la_data_out[21],
- la_data_out[20],
- la_data_out[19],
- la_data_out[18],
- la_data_out[17],
- la_data_out[16],
- la_data_out[15],
- la_data_out[14],
- la_data_out[13],
- la_data_out[12],
- la_data_out[11],
- la_data_out[10],
- la_data_out[9],
- la_data_out[8],
- la_data_out[7],
- la_data_out[6],
- la_data_out[5],
- la_data_out[4],
- la_data_out[3],
- la_data_out[2],
- la_data_out[1],
- la_data_out[0]}),
- .la_oenb({la_oenb[63],
- la_oenb[62],
- la_oenb[61],
- la_oenb[60],
- la_oenb[59],
- la_oenb[58],
- la_oenb[57],
- la_oenb[56],
- la_oenb[55],
- la_oenb[54],
- la_oenb[53],
- la_oenb[52],
- la_oenb[51],
- la_oenb[50],
- la_oenb[49],
- la_oenb[48],
- la_oenb[47],
- la_oenb[46],
- la_oenb[45],
- la_oenb[44],
- la_oenb[43],
- la_oenb[42],
- la_oenb[41],
- la_oenb[40],
- la_oenb[39],
- la_oenb[38],
- la_oenb[37],
- la_oenb[36],
- la_oenb[35],
- la_oenb[34],
- la_oenb[33],
- la_oenb[32],
- la_oenb[31],
- la_oenb[30],
- la_oenb[29],
- la_oenb[28],
- la_oenb[27],
- la_oenb[26],
- la_oenb[25],
- la_oenb[24],
- la_oenb[23],
- la_oenb[22],
- la_oenb[21],
- la_oenb[20],
- la_oenb[19],
- la_oenb[18],
- la_oenb[17],
- la_oenb[16],
- la_oenb[15],
- la_oenb[14],
- la_oenb[13],
- la_oenb[12],
- la_oenb[11],
- la_oenb[10],
- la_oenb[9],
- la_oenb[8],
- la_oenb[7],
- la_oenb[6],
- la_oenb[5],
- la_oenb[4],
- la_oenb[3],
- la_oenb[2],
- la_oenb[1],
- la_oenb[0]}),
- .wbs_adr_i({wbs_adr_i[31],
- wbs_adr_i[30],
- wbs_adr_i[29],
- wbs_adr_i[28],
- wbs_adr_i[27],
- wbs_adr_i[26],
- wbs_adr_i[25],
- wbs_adr_i[24],
- wbs_adr_i[23],
- wbs_adr_i[22],
- wbs_adr_i[21],
- wbs_adr_i[20],
- wbs_adr_i[19],
- wbs_adr_i[18],
- wbs_adr_i[17],
- wbs_adr_i[16],
- wbs_adr_i[15],
- wbs_adr_i[14],
- wbs_adr_i[13],
- wbs_adr_i[12],
- wbs_adr_i[11],
- wbs_adr_i[10],
- wbs_adr_i[9],
- wbs_adr_i[8],
- wbs_adr_i[7],
- wbs_adr_i[6],
- wbs_adr_i[5],
- wbs_adr_i[4],
- wbs_adr_i[3],
- wbs_adr_i[2],
- wbs_adr_i[1],
- wbs_adr_i[0]}),
- .wbs_dat_i({wbs_dat_i[31],
- wbs_dat_i[30],
- wbs_dat_i[29],
- wbs_dat_i[28],
- wbs_dat_i[27],
- wbs_dat_i[26],
- wbs_dat_i[25],
- wbs_dat_i[24],
- wbs_dat_i[23],
- wbs_dat_i[22],
- wbs_dat_i[21],
- wbs_dat_i[20],
- wbs_dat_i[19],
- wbs_dat_i[18],
- wbs_dat_i[17],
- wbs_dat_i[16],
- wbs_dat_i[15],
- wbs_dat_i[14],
- wbs_dat_i[13],
- wbs_dat_i[12],
- wbs_dat_i[11],
- wbs_dat_i[10],
- wbs_dat_i[9],
- wbs_dat_i[8],
- wbs_dat_i[7],
- wbs_dat_i[6],
- wbs_dat_i[5],
- wbs_dat_i[4],
- wbs_dat_i[3],
- wbs_dat_i[2],
- wbs_dat_i[1],
- wbs_dat_i[0]}),
- .wbs_dat_o({wbs_dat_o[31],
- wbs_dat_o[30],
- wbs_dat_o[29],
- wbs_dat_o[28],
- wbs_dat_o[27],
- wbs_dat_o[26],
- wbs_dat_o[25],
- wbs_dat_o[24],
- wbs_dat_o[23],
- wbs_dat_o[22],
- wbs_dat_o[21],
- wbs_dat_o[20],
- wbs_dat_o[19],
- wbs_dat_o[18],
- wbs_dat_o[17],
- wbs_dat_o[16],
- wbs_dat_o[15],
- wbs_dat_o[14],
- wbs_dat_o[13],
- wbs_dat_o[12],
- wbs_dat_o[11],
- wbs_dat_o[10],
- wbs_dat_o[9],
- wbs_dat_o[8],
- wbs_dat_o[7],
- wbs_dat_o[6],
- wbs_dat_o[5],
- wbs_dat_o[4],
- wbs_dat_o[3],
- wbs_dat_o[2],
- wbs_dat_o[1],
- wbs_dat_o[0]}),
- .wbs_sel_i({wbs_sel_i[3],
- wbs_sel_i[2],
- wbs_sel_i[1],
- wbs_sel_i[0]}));
+ io_out[0]}));
endmodule
diff --git a/verilog/gl/wrapped_vga_clock.v b/verilog/gl/wrapped_vga_clock.v
new file mode 100644
index 0000000..dd6f277
--- /dev/null
+++ b/verilog/gl/wrapped_vga_clock.v
@@ -0,0 +1,15997 @@
+module wrapped_vga_clock (wb_clk_i,
+ wb_rst_i,
+ vdd,
+ vss,
+ io_in,
+ io_oeb,
+ io_out);
+ input wb_clk_i;
+ input wb_rst_i;
+ input vdd;
+ input vss;
+ input [37:0] io_in;
+ output [37:0] io_oeb;
+ output [37:0] io_out;
+
+ wire _0000_;
+ wire _0001_;
+ wire _0002_;
+ wire _0003_;
+ wire _0004_;
+ wire _0005_;
+ wire _0006_;
+ wire _0007_;
+ wire _0008_;
+ wire _0009_;
+ wire _0010_;
+ wire _0011_;
+ wire _0012_;
+ wire _0013_;
+ wire _0014_;
+ wire _0015_;
+ wire _0016_;
+ wire _0017_;
+ wire _0018_;
+ wire _0019_;
+ wire _0020_;
+ wire _0021_;
+ wire _0022_;
+ wire _0023_;
+ wire _0024_;
+ wire _0025_;
+ wire _0026_;
+ wire _0027_;
+ wire _0028_;
+ wire _0029_;
+ wire _0030_;
+ wire _0031_;
+ wire _0032_;
+ wire _0033_;
+ wire _0034_;
+ wire _0035_;
+ wire _0036_;
+ wire _0037_;
+ wire _0038_;
+ wire _0039_;
+ wire _0040_;
+ wire _0041_;
+ wire _0042_;
+ wire _0043_;
+ wire _0044_;
+ wire _0045_;
+ wire _0046_;
+ wire _0047_;
+ wire _0048_;
+ wire _0049_;
+ wire _0050_;
+ wire _0051_;
+ wire _0052_;
+ wire _0053_;
+ wire _0054_;
+ wire _0055_;
+ wire _0056_;
+ wire _0057_;
+ wire _0058_;
+ wire _0059_;
+ wire _0060_;
+ wire _0061_;
+ wire _0062_;
+ wire _0063_;
+ wire _0064_;
+ wire _0065_;
+ wire _0066_;
+ wire _0067_;
+ wire _0068_;
+ wire _0069_;
+ wire _0070_;
+ wire _0071_;
+ wire _0072_;
+ wire _0073_;
+ wire _0074_;
+ wire _0075_;
+ wire _0076_;
+ wire _0077_;
+ wire _0078_;
+ wire _0079_;
+ wire _0080_;
+ wire _0081_;
+ wire _0082_;
+ wire _0083_;
+ wire _0084_;
+ wire _0085_;
+ wire _0086_;
+ wire _0087_;
+ wire _0088_;
+ wire _0089_;
+ wire _0090_;
+ wire _0091_;
+ wire _0092_;
+ wire _0093_;
+ wire _0094_;
+ wire _0095_;
+ wire _0096_;
+ wire _0097_;
+ wire _0098_;
+ wire _0099_;
+ wire _0100_;
+ wire _0101_;
+ wire _0102_;
+ wire _0103_;
+ wire _0104_;
+ wire _0105_;
+ wire _0106_;
+ wire _0107_;
+ wire _0108_;
+ wire _0109_;
+ wire _0110_;
+ wire _0111_;
+ wire _0112_;
+ wire _0113_;
+ wire _0114_;
+ wire _0115_;
+ wire _0116_;
+ wire _0117_;
+ wire _0118_;
+ wire _0119_;
+ wire _0120_;
+ wire _0121_;
+ wire _0122_;
+ wire _0123_;
+ wire _0124_;
+ wire _0125_;
+ wire _0126_;
+ wire _0127_;
+ wire _0128_;
+ wire _0129_;
+ wire _0130_;
+ wire _0131_;
+ wire _0132_;
+ wire _0133_;
+ wire _0134_;
+ wire _0135_;
+ wire _0136_;
+ wire _0137_;
+ wire _0138_;
+ wire _0139_;
+ wire _0140_;
+ wire _0141_;
+ wire _0142_;
+ wire _0143_;
+ wire _0144_;
+ wire _0145_;
+ wire _0146_;
+ wire _0147_;
+ wire _0148_;
+ wire _0149_;
+ wire _0150_;
+ wire _0151_;
+ wire _0152_;
+ wire _0153_;
+ wire _0154_;
+ wire _0155_;
+ wire _0156_;
+ wire _0157_;
+ wire _0158_;
+ wire _0159_;
+ wire _0160_;
+ wire _0161_;
+ wire _0162_;
+ wire _0163_;
+ wire _0164_;
+ wire _0165_;
+ wire _0166_;
+ wire _0167_;
+ wire _0168_;
+ wire _0169_;
+ wire _0170_;
+ wire _0171_;
+ wire _0172_;
+ wire _0173_;
+ wire _0174_;
+ wire _0175_;
+ wire _0176_;
+ wire _0177_;
+ wire _0178_;
+ wire _0179_;
+ wire _0180_;
+ wire _0181_;
+ wire _0182_;
+ wire _0183_;
+ wire _0184_;
+ wire _0185_;
+ wire _0186_;
+ wire _0187_;
+ wire _0188_;
+ wire _0189_;
+ wire _0190_;
+ wire _0191_;
+ wire _0192_;
+ wire _0193_;
+ wire _0194_;
+ wire _0195_;
+ wire _0196_;
+ wire _0197_;
+ wire _0198_;
+ wire _0199_;
+ wire _0200_;
+ wire _0201_;
+ wire _0202_;
+ wire _0203_;
+ wire _0204_;
+ wire _0205_;
+ wire _0206_;
+ wire _0207_;
+ wire _0208_;
+ wire _0209_;
+ wire _0210_;
+ wire _0211_;
+ wire _0212_;
+ wire _0213_;
+ wire _0214_;
+ wire _0215_;
+ wire _0216_;
+ wire _0217_;
+ wire _0218_;
+ wire _0219_;
+ wire _0220_;
+ wire _0221_;
+ wire _0222_;
+ wire _0223_;
+ wire _0224_;
+ wire _0225_;
+ wire _0226_;
+ wire _0227_;
+ wire _0228_;
+ wire _0229_;
+ wire _0230_;
+ wire _0231_;
+ wire _0232_;
+ wire _0233_;
+ wire _0234_;
+ wire _0235_;
+ wire _0236_;
+ wire _0237_;
+ wire _0238_;
+ wire _0239_;
+ wire _0240_;
+ wire _0241_;
+ wire _0242_;
+ wire _0243_;
+ wire _0244_;
+ wire _0245_;
+ wire _0246_;
+ wire _0247_;
+ wire _0248_;
+ wire _0249_;
+ wire _0250_;
+ wire _0251_;
+ wire _0252_;
+ wire _0253_;
+ wire _0254_;
+ wire _0255_;
+ wire _0256_;
+ wire _0257_;
+ wire _0258_;
+ wire _0259_;
+ wire _0260_;
+ wire _0261_;
+ wire _0262_;
+ wire _0263_;
+ wire _0264_;
+ wire _0265_;
+ wire _0266_;
+ wire _0267_;
+ wire _0268_;
+ wire _0269_;
+ wire _0270_;
+ wire _0271_;
+ wire _0272_;
+ wire _0273_;
+ wire _0274_;
+ wire _0275_;
+ wire _0276_;
+ wire _0277_;
+ wire _0278_;
+ wire _0279_;
+ wire _0280_;
+ wire _0281_;
+ wire _0282_;
+ wire _0283_;
+ wire _0284_;
+ wire _0285_;
+ wire _0286_;
+ wire _0287_;
+ wire _0288_;
+ wire _0289_;
+ wire _0290_;
+ wire _0291_;
+ wire _0292_;
+ wire _0293_;
+ wire _0294_;
+ wire _0295_;
+ wire _0296_;
+ wire _0297_;
+ wire _0298_;
+ wire _0299_;
+ wire _0300_;
+ wire _0301_;
+ wire _0302_;
+ wire _0303_;
+ wire _0304_;
+ wire _0305_;
+ wire _0306_;
+ wire _0307_;
+ wire _0308_;
+ wire _0309_;
+ wire _0310_;
+ wire _0311_;
+ wire _0312_;
+ wire _0313_;
+ wire _0314_;
+ wire _0315_;
+ wire _0316_;
+ wire _0317_;
+ wire _0318_;
+ wire _0319_;
+ wire _0320_;
+ wire _0321_;
+ wire _0322_;
+ wire _0323_;
+ wire _0324_;
+ wire _0325_;
+ wire _0326_;
+ wire _0327_;
+ wire _0328_;
+ wire _0329_;
+ wire _0330_;
+ wire _0331_;
+ wire _0332_;
+ wire _0333_;
+ wire _0334_;
+ wire _0335_;
+ wire _0336_;
+ wire _0337_;
+ wire _0338_;
+ wire _0339_;
+ wire _0340_;
+ wire _0341_;
+ wire _0342_;
+ wire _0343_;
+ wire _0344_;
+ wire _0345_;
+ wire _0346_;
+ wire _0347_;
+ wire _0348_;
+ wire _0349_;
+ wire _0350_;
+ wire _0351_;
+ wire _0352_;
+ wire _0353_;
+ wire _0354_;
+ wire _0355_;
+ wire _0356_;
+ wire _0357_;
+ wire _0358_;
+ wire _0359_;
+ wire _0360_;
+ wire _0361_;
+ wire _0362_;
+ wire _0363_;
+ wire _0364_;
+ wire _0365_;
+ wire _0366_;
+ wire _0367_;
+ wire _0368_;
+ wire _0369_;
+ wire _0370_;
+ wire _0371_;
+ wire _0372_;
+ wire _0373_;
+ wire _0374_;
+ wire _0375_;
+ wire _0376_;
+ wire _0377_;
+ wire _0378_;
+ wire _0379_;
+ wire _0380_;
+ wire _0381_;
+ wire _0382_;
+ wire _0383_;
+ wire _0384_;
+ wire _0385_;
+ wire _0386_;
+ wire _0387_;
+ wire _0388_;
+ wire _0389_;
+ wire _0390_;
+ wire _0391_;
+ wire _0392_;
+ wire _0393_;
+ wire _0394_;
+ wire _0395_;
+ wire _0396_;
+ wire _0397_;
+ wire _0398_;
+ wire _0399_;
+ wire _0400_;
+ wire _0401_;
+ wire _0402_;
+ wire _0403_;
+ wire _0404_;
+ wire _0405_;
+ wire _0406_;
+ wire _0407_;
+ wire _0408_;
+ wire _0409_;
+ wire _0410_;
+ wire _0411_;
+ wire _0412_;
+ wire _0413_;
+ wire _0414_;
+ wire _0415_;
+ wire _0416_;
+ wire _0417_;
+ wire _0418_;
+ wire _0419_;
+ wire _0420_;
+ wire _0421_;
+ wire _0422_;
+ wire _0423_;
+ wire _0424_;
+ wire _0425_;
+ wire _0426_;
+ wire _0427_;
+ wire _0428_;
+ wire _0429_;
+ wire _0430_;
+ wire _0431_;
+ wire _0432_;
+ wire _0433_;
+ wire _0434_;
+ wire _0435_;
+ wire _0436_;
+ wire _0437_;
+ wire _0438_;
+ wire _0439_;
+ wire _0440_;
+ wire _0441_;
+ wire _0442_;
+ wire _0443_;
+ wire _0444_;
+ wire _0445_;
+ wire _0446_;
+ wire _0447_;
+ wire _0448_;
+ wire _0449_;
+ wire _0450_;
+ wire _0451_;
+ wire _0452_;
+ wire _0453_;
+ wire _0454_;
+ wire _0455_;
+ wire _0456_;
+ wire _0457_;
+ wire _0458_;
+ wire _0459_;
+ wire _0460_;
+ wire _0461_;
+ wire _0462_;
+ wire _0463_;
+ wire _0464_;
+ wire _0465_;
+ wire _0466_;
+ wire _0467_;
+ wire _0468_;
+ wire _0469_;
+ wire _0470_;
+ wire _0471_;
+ wire _0472_;
+ wire _0473_;
+ wire _0474_;
+ wire _0475_;
+ wire _0476_;
+ wire _0477_;
+ wire _0478_;
+ wire _0479_;
+ wire _0480_;
+ wire _0481_;
+ wire _0482_;
+ wire _0483_;
+ wire _0484_;
+ wire _0485_;
+ wire _0486_;
+ wire _0487_;
+ wire _0488_;
+ wire _0489_;
+ wire _0490_;
+ wire _0491_;
+ wire _0492_;
+ wire _0493_;
+ wire _0494_;
+ wire _0495_;
+ wire _0496_;
+ wire _0497_;
+ wire _0498_;
+ wire _0499_;
+ wire _0500_;
+ wire _0501_;
+ wire _0502_;
+ wire _0503_;
+ wire _0504_;
+ wire _0505_;
+ wire _0506_;
+ wire _0507_;
+ wire _0508_;
+ wire _0509_;
+ wire _0510_;
+ wire _0511_;
+ wire _0512_;
+ wire _0513_;
+ wire _0514_;
+ wire _0515_;
+ wire _0516_;
+ wire _0517_;
+ wire _0518_;
+ wire _0519_;
+ wire _0520_;
+ wire _0521_;
+ wire _0522_;
+ wire _0523_;
+ wire _0524_;
+ wire _0525_;
+ wire _0526_;
+ wire _0527_;
+ wire _0528_;
+ wire _0529_;
+ wire _0530_;
+ wire _0531_;
+ wire _0532_;
+ wire _0533_;
+ wire _0534_;
+ wire _0535_;
+ wire _0536_;
+ wire _0537_;
+ wire _0538_;
+ wire _0539_;
+ wire _0540_;
+ wire _0541_;
+ wire _0542_;
+ wire _0543_;
+ wire _0544_;
+ wire _0545_;
+ wire _0546_;
+ wire _0547_;
+ wire _0548_;
+ wire _0549_;
+ wire _0550_;
+ wire _0551_;
+ wire _0552_;
+ wire _0553_;
+ wire _0554_;
+ wire _0555_;
+ wire _0556_;
+ wire _0557_;
+ wire _0558_;
+ wire _0559_;
+ wire _0560_;
+ wire _0561_;
+ wire _0562_;
+ wire _0563_;
+ wire _0564_;
+ wire _0565_;
+ wire _0566_;
+ wire _0567_;
+ wire _0568_;
+ wire _0569_;
+ wire _0570_;
+ wire _0571_;
+ wire _0572_;
+ wire _0573_;
+ wire _0574_;
+ wire _0575_;
+ wire _0576_;
+ wire _0577_;
+ wire _0578_;
+ wire _0579_;
+ wire _0580_;
+ wire _0581_;
+ wire _0582_;
+ wire _0583_;
+ wire _0584_;
+ wire _0585_;
+ wire _0586_;
+ wire _0587_;
+ wire _0588_;
+ wire _0589_;
+ wire _0590_;
+ wire _0591_;
+ wire _0592_;
+ wire _0593_;
+ wire _0594_;
+ wire _0595_;
+ wire _0596_;
+ wire _0597_;
+ wire _0598_;
+ wire _0599_;
+ wire _0600_;
+ wire _0601_;
+ wire _0602_;
+ wire _0603_;
+ wire _0604_;
+ wire _0605_;
+ wire _0606_;
+ wire _0607_;
+ wire _0608_;
+ wire _0609_;
+ wire _0610_;
+ wire _0611_;
+ wire _0612_;
+ wire _0613_;
+ wire _0614_;
+ wire _0615_;
+ wire _0616_;
+ wire _0617_;
+ wire _0618_;
+ wire _0619_;
+ wire _0620_;
+ wire _0621_;
+ wire _0622_;
+ wire _0623_;
+ wire _0624_;
+ wire _0625_;
+ wire _0626_;
+ wire _0627_;
+ wire _0628_;
+ wire _0629_;
+ wire _0630_;
+ wire _0631_;
+ wire _0632_;
+ wire _0633_;
+ wire _0634_;
+ wire _0635_;
+ wire _0636_;
+ wire _0637_;
+ wire _0638_;
+ wire _0639_;
+ wire _0640_;
+ wire _0641_;
+ wire _0642_;
+ wire _0643_;
+ wire _0644_;
+ wire _0645_;
+ wire _0646_;
+ wire _0647_;
+ wire _0648_;
+ wire _0649_;
+ wire _0650_;
+ wire _0651_;
+ wire _0652_;
+ wire _0653_;
+ wire _0654_;
+ wire _0655_;
+ wire _0656_;
+ wire _0657_;
+ wire _0658_;
+ wire _0659_;
+ wire _0660_;
+ wire _0661_;
+ wire _0662_;
+ wire _0663_;
+ wire _0664_;
+ wire _0665_;
+ wire _0666_;
+ wire _0667_;
+ wire _0668_;
+ wire _0669_;
+ wire _0670_;
+ wire _0671_;
+ wire net14;
+ wire net24;
+ wire net25;
+ wire net26;
+ wire net27;
+ wire net28;
+ wire net29;
+ wire net30;
+ wire net31;
+ wire net32;
+ wire net33;
+ wire net15;
+ wire net34;
+ wire net35;
+ wire net36;
+ wire net37;
+ wire net38;
+ wire net39;
+ wire net40;
+ wire net41;
+ wire net42;
+ wire net43;
+ wire net16;
+ wire net44;
+ wire net45;
+ wire net46;
+ wire net47;
+ wire net48;
+ wire net49;
+ wire net50;
+ wire net51;
+ wire net17;
+ wire net18;
+ wire net19;
+ wire net20;
+ wire net21;
+ wire net22;
+ wire net23;
+ wire net52;
+ wire net62;
+ wire net63;
+ wire net53;
+ wire net64;
+ wire net65;
+ wire net66;
+ wire net67;
+ wire net68;
+ wire net69;
+ wire net70;
+ wire net71;
+ wire net72;
+ wire net73;
+ wire net54;
+ wire net74;
+ wire net75;
+ wire net76;
+ wire net77;
+ wire net78;
+ wire net79;
+ wire net80;
+ wire clknet_0_wb_clk_i;
+ wire net55;
+ wire net56;
+ wire net57;
+ wire net58;
+ wire net59;
+ wire net60;
+ wire net61;
+ wire \vga_clock.col_index[0] ;
+ wire \vga_clock.col_index[1] ;
+ wire \vga_clock.col_index_q[0] ;
+ wire \vga_clock.col_index_q[1] ;
+ wire \vga_clock.color[0] ;
+ wire \vga_clock.color[1] ;
+ wire \vga_clock.color[2] ;
+ wire \vga_clock.color[3] ;
+ wire \vga_clock.color[4] ;
+ wire \vga_clock.color[5] ;
+ wire \vga_clock.color_offset[0] ;
+ wire \vga_clock.color_offset[1] ;
+ wire \vga_clock.color_offset[2] ;
+ wire \vga_clock.digit_0.char[0] ;
+ wire \vga_clock.digit_0.char[1] ;
+ wire \vga_clock.digit_0.char[2] ;
+ wire \vga_clock.digit_0.char[3] ;
+ wire \vga_clock.digit_0.digit_index[0] ;
+ wire \vga_clock.digit_0.digit_index[1] ;
+ wire \vga_clock.digit_0.digit_index[2] ;
+ wire \vga_clock.digit_0.digit_index[3] ;
+ wire \vga_clock.digit_0.digit_index[4] ;
+ wire \vga_clock.digit_0.digit_index[5] ;
+ wire \vga_clock.digit_0.number[0] ;
+ wire \vga_clock.digit_0.number[1] ;
+ wire \vga_clock.digit_0.x_block[0] ;
+ wire \vga_clock.digit_0.x_block[1] ;
+ wire \vga_clock.draw ;
+ wire \vga_clock.font_0.dout[1] ;
+ wire \vga_clock.font_0.dout[2] ;
+ wire \vga_clock.font_0.dout[3] ;
+ wire \vga_clock.hrs_d[0] ;
+ wire \vga_clock.hrs_d[1] ;
+ wire \vga_clock.hrs_u[0] ;
+ wire \vga_clock.hrs_u[1] ;
+ wire \vga_clock.hrs_u[2] ;
+ wire \vga_clock.hrs_u[3] ;
+ wire \vga_clock.min_d[0] ;
+ wire \vga_clock.min_d[1] ;
+ wire \vga_clock.min_d[2] ;
+ wire \vga_clock.min_u[0] ;
+ wire \vga_clock.min_u[1] ;
+ wire \vga_clock.min_u[2] ;
+ wire \vga_clock.min_u[3] ;
+ wire \vga_clock.pulse_hrs.comp[0] ;
+ wire \vga_clock.pulse_hrs.comp[1] ;
+ wire \vga_clock.pulse_hrs.comp[2] ;
+ wire \vga_clock.pulse_hrs.comp[3] ;
+ wire \vga_clock.pulse_hrs.comp[4] ;
+ wire \vga_clock.pulse_hrs.count[0] ;
+ wire \vga_clock.pulse_hrs.count[1] ;
+ wire \vga_clock.pulse_hrs.count[2] ;
+ wire \vga_clock.pulse_hrs.count[3] ;
+ wire \vga_clock.pulse_hrs.count[4] ;
+ wire \vga_clock.pulse_min.comp[0] ;
+ wire \vga_clock.pulse_min.comp[1] ;
+ wire \vga_clock.pulse_min.comp[2] ;
+ wire \vga_clock.pulse_min.comp[3] ;
+ wire \vga_clock.pulse_min.comp[4] ;
+ wire \vga_clock.pulse_min.count[0] ;
+ wire \vga_clock.pulse_min.count[1] ;
+ wire \vga_clock.pulse_min.count[2] ;
+ wire \vga_clock.pulse_min.count[3] ;
+ wire \vga_clock.pulse_min.count[4] ;
+ wire \vga_clock.pulse_sec.comp[0] ;
+ wire \vga_clock.pulse_sec.comp[1] ;
+ wire \vga_clock.pulse_sec.comp[2] ;
+ wire \vga_clock.pulse_sec.comp[3] ;
+ wire \vga_clock.pulse_sec.comp[4] ;
+ wire \vga_clock.pulse_sec.count[0] ;
+ wire \vga_clock.pulse_sec.count[1] ;
+ wire \vga_clock.pulse_sec.count[2] ;
+ wire \vga_clock.pulse_sec.count[3] ;
+ wire \vga_clock.pulse_sec.count[4] ;
+ wire \vga_clock.sec_counter[0] ;
+ wire \vga_clock.sec_counter[10] ;
+ wire \vga_clock.sec_counter[11] ;
+ wire \vga_clock.sec_counter[12] ;
+ wire \vga_clock.sec_counter[13] ;
+ wire \vga_clock.sec_counter[14] ;
+ wire \vga_clock.sec_counter[15] ;
+ wire \vga_clock.sec_counter[16] ;
+ wire \vga_clock.sec_counter[17] ;
+ wire \vga_clock.sec_counter[18] ;
+ wire \vga_clock.sec_counter[19] ;
+ wire \vga_clock.sec_counter[1] ;
+ wire \vga_clock.sec_counter[20] ;
+ wire \vga_clock.sec_counter[21] ;
+ wire \vga_clock.sec_counter[22] ;
+ wire \vga_clock.sec_counter[23] ;
+ wire \vga_clock.sec_counter[24] ;
+ wire \vga_clock.sec_counter[25] ;
+ wire \vga_clock.sec_counter[2] ;
+ wire \vga_clock.sec_counter[3] ;
+ wire \vga_clock.sec_counter[4] ;
+ wire \vga_clock.sec_counter[5] ;
+ wire \vga_clock.sec_counter[6] ;
+ wire \vga_clock.sec_counter[7] ;
+ wire \vga_clock.sec_counter[8] ;
+ wire \vga_clock.sec_counter[9] ;
+ wire \vga_clock.sec_d[0] ;
+ wire \vga_clock.sec_d[1] ;
+ wire \vga_clock.sec_d[2] ;
+ wire \vga_clock.sec_u[0] ;
+ wire \vga_clock.sec_u[1] ;
+ wire \vga_clock.sec_u[2] ;
+ wire \vga_clock.sec_u[3] ;
+ wire \vga_clock.vga_0.hc[0] ;
+ wire \vga_clock.vga_0.hc[1] ;
+ wire \vga_clock.vga_0.hc[2] ;
+ wire \vga_clock.vga_0.hc[3] ;
+ wire \vga_clock.vga_0.hc[4] ;
+ wire \vga_clock.vga_0.hc[5] ;
+ wire \vga_clock.vga_0.hc[6] ;
+ wire \vga_clock.vga_0.hc[7] ;
+ wire \vga_clock.vga_0.hc[8] ;
+ wire \vga_clock.vga_0.hc[9] ;
+ wire \vga_clock.vga_0.vc[0] ;
+ wire \vga_clock.vga_0.vc[1] ;
+ wire \vga_clock.vga_0.vc[2] ;
+ wire \vga_clock.vga_0.vc[3] ;
+ wire \vga_clock.vga_0.vc[4] ;
+ wire \vga_clock.vga_0.vc[5] ;
+ wire \vga_clock.vga_0.vc[6] ;
+ wire \vga_clock.vga_0.vc[7] ;
+ wire \vga_clock.vga_0.vc[8] ;
+ wire \vga_clock.vga_0.vc[9] ;
+ wire \vga_clock.vga_0.x_px[0] ;
+ wire \vga_clock.vga_0.x_px[1] ;
+ wire \vga_clock.vga_0.x_px[2] ;
+ wire \vga_clock.vga_0.x_px[3] ;
+ wire \vga_clock.vga_0.x_px[6] ;
+ wire \vga_clock.vga_0.x_px[7] ;
+ wire \vga_clock.vga_0.x_px[8] ;
+ wire \vga_clock.vga_0.x_px[9] ;
+ wire \vga_clock.vga_0.y_px[0] ;
+ wire \vga_clock.vga_0.y_px[1] ;
+ wire \vga_clock.vga_0.y_px[2] ;
+ wire \vga_clock.vga_0.y_px[3] ;
+ wire \vga_clock.vga_0.y_px[4] ;
+ wire \vga_clock.vga_0.y_px[5] ;
+ wire \vga_clock.vga_0.y_px[6] ;
+ wire \vga_clock.vga_0.y_px[7] ;
+ wire \vga_clock.vga_0.y_px[8] ;
+ wire \vga_clock.vga_0.y_px[9] ;
+ wire \vga_clock.x_block_q[0] ;
+ wire \vga_clock.x_block_q[1] ;
+ wire \vga_clock.x_block_q[2] ;
+ wire \vga_clock.x_block_q[3] ;
+ wire \vga_clock.x_block_q[4] ;
+ wire \vga_clock.x_block_q[5] ;
+ wire \vga_clock.y_block[0] ;
+ wire \vga_clock.y_block[1] ;
+ wire \vga_clock.y_block[2] ;
+ wire \vga_clock.y_block[3] ;
+ wire \vga_clock.y_block[4] ;
+ wire \vga_clock.y_block[5] ;
+ wire \vga_clock.y_block_q[0] ;
+ wire \vga_clock.y_block_q[1] ;
+ wire \vga_clock.y_block_q[2] ;
+ wire \vga_clock.y_block_q[3] ;
+ wire \vga_clock.y_block_q[4] ;
+ wire \vga_clock.y_block_q[5] ;
+ wire net1;
+ wire net2;
+ wire net3;
+ wire net4;
+ wire net5;
+ wire net6;
+ wire net7;
+ wire net8;
+ wire net9;
+ wire net10;
+ wire net11;
+ wire net12;
+ wire net13;
+ wire clknet_4_0_0_wb_clk_i;
+ wire clknet_4_1_0_wb_clk_i;
+ wire clknet_4_2_0_wb_clk_i;
+ wire clknet_4_3_0_wb_clk_i;
+ wire clknet_4_4_0_wb_clk_i;
+ wire clknet_4_5_0_wb_clk_i;
+ wire clknet_4_6_0_wb_clk_i;
+ wire clknet_4_7_0_wb_clk_i;
+ wire clknet_4_8_0_wb_clk_i;
+ wire clknet_4_9_0_wb_clk_i;
+ wire clknet_4_10_0_wb_clk_i;
+ wire clknet_4_11_0_wb_clk_i;
+ wire clknet_4_12_0_wb_clk_i;
+ wire clknet_4_13_0_wb_clk_i;
+ wire clknet_4_14_0_wb_clk_i;
+ wire clknet_4_15_0_wb_clk_i;
+
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _0672_ (.I(\vga_clock.vga_0.x_px[6] ),
+ .ZN(\vga_clock.digit_0.char[0] ),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__xor2_1 _0673_ (.A1(\vga_clock.digit_0.char[0] ),
+ .A2(\vga_clock.vga_0.x_px[7] ),
+ .Z(_0135_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__clkbuf_2 _0674_ (.I(_0135_),
+ .Z(\vga_clock.digit_0.char[1] ),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__xor2_1 _0675_ (.A1(\vga_clock.color_offset[1] ),
+ .A2(\vga_clock.digit_0.char[1] ),
+ .Z(_0136_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _0676_ (.I(\vga_clock.color_offset[0] ),
+ .ZN(_0137_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__buf_2 _0677_ (.I(\vga_clock.vga_0.x_px[6] ),
+ .Z(_0138_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__xor2_1 _0678_ (.A1(_0137_),
+ .A2(_0138_),
+ .Z(_0139_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_1 _0679_ (.A1(_0136_),
+ .A2(_0139_),
+ .ZN(_0140_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_1 _0680_ (.A1(_0137_),
+ .A2(_0138_),
+ .ZN(_0141_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__xor2_1 _0681_ (.A1(_0136_),
+ .A2(_0141_),
+ .Z(_0142_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_1 _0682_ (.A1(\vga_clock.color_offset[1] ),
+ .A2(\vga_clock.digit_0.char[1] ),
+ .ZN(_0143_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_1 _0683_ (.A1(_0136_),
+ .A2(_0141_),
+ .ZN(_0144_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_1 _0684_ (.A1(_0143_),
+ .A2(_0144_),
+ .ZN(_0145_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _0685_ (.A1(\vga_clock.vga_0.x_px[6] ),
+ .A2(\vga_clock.vga_0.x_px[7] ),
+ .ZN(_0146_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__xor2_1 _0686_ (.A1(\vga_clock.vga_0.x_px[8] ),
+ .A2(_0146_),
+ .Z(_0147_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__buf_2 _0687_ (.I(_0147_),
+ .Z(\vga_clock.digit_0.char[2] ),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__xor3_2 _0688_ (.A1(\vga_clock.color_offset[2] ),
+ .A2(_0145_),
+ .A3(\vga_clock.digit_0.char[2] ),
+ .Z(_0148_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_2 _0689_ (.I0(_0140_),
+ .I1(_0142_),
+ .S(_0148_),
+ .Z(_0149_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__clkbuf_1 _0690_ (.I(_0149_),
+ .Z(_0000_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_2 _0691_ (.I0(_0140_),
+ .I1(_0139_),
+ .S(_0148_),
+ .Z(_0150_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__clkbuf_1 _0692_ (.I(_0150_),
+ .Z(_0001_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__or3_2 _0693_ (.A1(\vga_clock.vga_0.y_px[3] ),
+ .A2(\vga_clock.vga_0.y_px[4] ),
+ .A3(\vga_clock.vga_0.y_px[5] ),
+ .Z(_0151_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__nand3_1 _0694_ (.A1(\vga_clock.vga_0.y_px[7] ),
+ .A2(\vga_clock.vga_0.y_px[6] ),
+ .A3(_0151_),
+ .ZN(_0152_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__xor2_1 _0695_ (.A1(\vga_clock.vga_0.y_px[8] ),
+ .A2(_0152_),
+ .Z(_0153_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__clkbuf_1 _0696_ (.I(_0153_),
+ .Z(\vga_clock.y_block[4] ),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__xnor2_1 _0697_ (.A1(\vga_clock.digit_0.digit_index[4] ),
+ .A2(\vga_clock.y_block[4] ),
+ .ZN(_0154_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__xor2_1 _0698_ (.A1(\vga_clock.vga_0.y_px[6] ),
+ .A2(_0151_),
+ .Z(_0155_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__clkbuf_1 _0699_ (.I(_0155_),
+ .Z(\vga_clock.y_block[2] ),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_1 _0700_ (.A1(\vga_clock.digit_0.digit_index[2] ),
+ .A2(\vga_clock.y_block[2] ),
+ .ZN(_0156_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_1 _0701_ (.A1(\vga_clock.vga_0.y_px[3] ),
+ .A2(\vga_clock.vga_0.y_px[4] ),
+ .ZN(_0157_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__xor3_2 _0702_ (.A1(\vga_clock.vga_0.y_px[5] ),
+ .A2(\vga_clock.digit_0.digit_index[1] ),
+ .A3(_0157_),
+ .Z(_0158_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__xnor2_1 _0703_ (.A1(\vga_clock.vga_0.y_px[3] ),
+ .A2(\vga_clock.vga_0.y_px[4] ),
+ .ZN(_0159_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__clkbuf_1 _0704_ (.I(_0159_),
+ .Z(\vga_clock.y_block[0] ),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__and2_1 _0705_ (.A1(\vga_clock.digit_0.digit_index[0] ),
+ .A2(\vga_clock.y_block[0] ),
+ .Z(_0160_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_1 _0706_ (.A1(\vga_clock.vga_0.y_px[3] ),
+ .A2(\vga_clock.vga_0.y_px[4] ),
+ .B(\vga_clock.vga_0.y_px[5] ),
+ .ZN(_0161_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _0707_ (.I(\vga_clock.digit_0.digit_index[1] ),
+ .ZN(_0162_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__aoi21_1 _0708_ (.A1(_0151_),
+ .A2(_0161_),
+ .B(_0162_),
+ .ZN(_0163_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__aoi221_2 _0709_ (.A1(\vga_clock.digit_0.digit_index[2] ),
+ .A2(\vga_clock.y_block[2] ),
+ .B1(_0158_),
+ .B2(_0160_),
+ .C(_0163_),
+ .ZN(_0164_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__oai31_1 _0710_ (.A1(\vga_clock.vga_0.y_px[3] ),
+ .A2(\vga_clock.vga_0.y_px[4] ),
+ .A3(\vga_clock.vga_0.y_px[5] ),
+ .B(\vga_clock.vga_0.y_px[6] ),
+ .ZN(_0165_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__xnor2_1 _0711_ (.A1(\vga_clock.vga_0.y_px[7] ),
+ .A2(_0165_),
+ .ZN(_0166_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__clkbuf_1 _0712_ (.I(_0166_),
+ .Z(\vga_clock.y_block[3] ),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_1 _0713_ (.A1(\vga_clock.digit_0.digit_index[3] ),
+ .A2(\vga_clock.y_block[3] ),
+ .ZN(_0167_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_1 _0714_ (.A1(\vga_clock.digit_0.digit_index[3] ),
+ .A2(\vga_clock.y_block[3] ),
+ .ZN(_0168_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__oai31_1 _0715_ (.A1(_0156_),
+ .A2(_0164_),
+ .A3(_0167_),
+ .B(_0168_),
+ .ZN(_0169_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _0716_ (.I(_0169_),
+ .ZN(_0170_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_1 _0717_ (.A1(\vga_clock.digit_0.digit_index[4] ),
+ .A2(\vga_clock.y_block[4] ),
+ .ZN(_0171_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_1 _0718_ (.A1(_0154_),
+ .A2(_0170_),
+ .B(_0171_),
+ .ZN(_0172_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _0719_ (.I(\vga_clock.vga_0.y_px[8] ),
+ .ZN(_0173_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_1 _0720_ (.A1(_0173_),
+ .A2(_0152_),
+ .ZN(_0174_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__xnor2_1 _0721_ (.A1(\vga_clock.vga_0.y_px[9] ),
+ .A2(_0174_),
+ .ZN(_0175_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__clkbuf_1 _0722_ (.I(_0175_),
+ .Z(\vga_clock.y_block[5] ),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__xor3_2 _0723_ (.A1(\vga_clock.digit_0.digit_index[5] ),
+ .A2(_0172_),
+ .A3(\vga_clock.y_block[5] ),
+ .Z(_0176_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__xnor2_1 _0724_ (.A1(_0158_),
+ .A2(_0160_),
+ .ZN(_0177_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_1 _0725_ (.A1(_0156_),
+ .A2(_0164_),
+ .ZN(_0178_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__xor3_1 _0726_ (.A1(\vga_clock.digit_0.digit_index[3] ),
+ .A2(\vga_clock.y_block[3] ),
+ .A3(_0178_),
+ .Z(_0179_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__buf_2 _0727_ (.I(_0179_),
+ .Z(_0180_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__xor2_2 _0728_ (.A1(\vga_clock.digit_0.digit_index[0] ),
+ .A2(\vga_clock.y_block[0] ),
+ .Z(_0181_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__aoi21_1 _0729_ (.A1(_0158_),
+ .A2(_0160_),
+ .B(_0163_),
+ .ZN(_0182_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__xor3_1 _0730_ (.A1(\vga_clock.digit_0.digit_index[2] ),
+ .A2(\vga_clock.y_block[2] ),
+ .A3(_0182_),
+ .Z(_0183_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__buf_2 _0731_ (.I(_0183_),
+ .Z(_0184_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_1 _0732_ (.A1(_0181_),
+ .A2(_0184_),
+ .ZN(_0185_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_1 _0733_ (.A1(_0180_),
+ .A2(_0185_),
+ .ZN(_0186_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__xor2_2 _0734_ (.A1(_0154_),
+ .A2(_0169_),
+ .Z(_0187_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _0735_ (.I(_0187_),
+ .ZN(_0188_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_1 _0736_ (.A1(_0177_),
+ .A2(_0186_),
+ .B(_0188_),
+ .ZN(_0189_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_1 _0737_ (.A1(_0187_),
+ .A2(_0180_),
+ .ZN(_0190_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__nand4_1 _0738_ (.A1(_0177_),
+ .A2(_0184_),
+ .A3(_0176_),
+ .A4(_0190_),
+ .ZN(_0191_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__xor2_1 _0739_ (.A1(_0158_),
+ .A2(_0160_),
+ .Z(_0192_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_1 _0740_ (.A1(_0192_),
+ .A2(_0181_),
+ .ZN(_0193_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__or2_1 _0741_ (.A1(_0184_),
+ .A2(_0180_),
+ .Z(_0194_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _0742_ (.I(_0181_),
+ .ZN(_0195_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_1 _0743_ (.A1(_0158_),
+ .A2(_0195_),
+ .ZN(_0196_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_1 _0744_ (.A1(_0192_),
+ .A2(_0181_),
+ .B(_0184_),
+ .ZN(_0197_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__oai211_1 _0745_ (.A1(_0184_),
+ .A2(_0196_),
+ .B(_0197_),
+ .C(_0180_),
+ .ZN(_0198_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__oai221_1 _0746_ (.A1(_0193_),
+ .A2(_0194_),
+ .B1(_0176_),
+ .B2(_0198_),
+ .C(_0187_),
+ .ZN(_0199_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__oai211_1 _0747_ (.A1(_0176_),
+ .A2(_0189_),
+ .B(_0191_),
+ .C(_0199_),
+ .ZN(_0005_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_1 _0748_ (.A1(_0183_),
+ .A2(_0196_),
+ .ZN(_0200_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__and2_1 _0749_ (.A1(_0184_),
+ .A2(_0196_),
+ .Z(_0201_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__nor3_1 _0750_ (.A1(_0177_),
+ .A2(_0181_),
+ .A3(_0184_),
+ .ZN(_0202_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__oai32_1 _0751_ (.A1(_0180_),
+ .A2(_0200_),
+ .A3(_0201_),
+ .B1(_0202_),
+ .B2(_0186_),
+ .ZN(_0203_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_1 _0752_ (.A1(_0158_),
+ .A2(_0181_),
+ .ZN(_0204_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__aoi21_1 _0753_ (.A1(_0184_),
+ .A2(_0204_),
+ .B(_0200_),
+ .ZN(_0205_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__aoi22_1 _0754_ (.A1(_0187_),
+ .A2(_0203_),
+ .B1(_0205_),
+ .B2(_0190_),
+ .ZN(_0206_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_1 _0755_ (.A1(_0190_),
+ .A2(_0202_),
+ .ZN(_0207_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_1 _0756_ (.A1(_0180_),
+ .A2(_0196_),
+ .ZN(_0208_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_1 _0757_ (.A1(_0185_),
+ .A2(_0208_),
+ .ZN(_0209_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_1 _0758_ (.A1(_0180_),
+ .A2(_0197_),
+ .ZN(_0210_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__aoi211_1 _0759_ (.A1(_0180_),
+ .A2(_0205_),
+ .B(_0210_),
+ .C(_0188_),
+ .ZN(_0211_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__aoi211_1 _0760_ (.A1(_0188_),
+ .A2(_0209_),
+ .B(_0211_),
+ .C(_0176_),
+ .ZN(_0212_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__aoi22_1 _0761_ (.A1(_0176_),
+ .A2(_0206_),
+ .B1(_0207_),
+ .B2(_0212_),
+ .ZN(_0006_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__and2_1 _0762_ (.A1(_0193_),
+ .A2(_0179_),
+ .Z(_0213_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _0763_ (.I(_0204_),
+ .ZN(_0214_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_1 _0764_ (.A1(_0183_),
+ .A2(_0214_),
+ .ZN(_0215_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__aoi211_1 _0765_ (.A1(_0181_),
+ .A2(_0184_),
+ .B(_0180_),
+ .C(_0215_),
+ .ZN(_0216_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__or3_1 _0766_ (.A1(_0187_),
+ .A2(_0213_),
+ .A3(_0216_),
+ .Z(_0217_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__oai211_1 _0767_ (.A1(_0193_),
+ .A2(_0214_),
+ .B(_0180_),
+ .C(_0184_),
+ .ZN(_0218_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__oai211_1 _0768_ (.A1(_0177_),
+ .A2(_0194_),
+ .B(_0218_),
+ .C(_0187_),
+ .ZN(_0219_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__and2_1 _0769_ (.A1(_0217_),
+ .A2(_0219_),
+ .Z(_0220_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__oai211_1 _0770_ (.A1(_0192_),
+ .A2(_0194_),
+ .B(_0176_),
+ .C(_0187_),
+ .ZN(_0221_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_1 _0771_ (.A1(_0176_),
+ .A2(_0220_),
+ .B(_0221_),
+ .ZN(_0007_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__oai31_1 _0772_ (.A1(\vga_clock.vga_0.x_px[6] ),
+ .A2(\vga_clock.vga_0.x_px[7] ),
+ .A3(\vga_clock.vga_0.x_px[8] ),
+ .B(\vga_clock.vga_0.x_px[9] ),
+ .ZN(_0222_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_1 _0773_ (.A1(\vga_clock.vga_0.x_px[9] ),
+ .A2(\vga_clock.vga_0.x_px[8] ),
+ .ZN(_0223_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_1 _0774_ (.A1(_0146_),
+ .A2(_0223_),
+ .ZN(_0224_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_1 _0775_ (.A1(_0222_),
+ .A2(_0224_),
+ .ZN(_0225_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__buf_1 _0776_ (.I(_0225_),
+ .Z(\vga_clock.digit_0.char[3] ),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_4 _0777_ (.A1(\vga_clock.vga_0.x_px[9] ),
+ .A2(\vga_clock.digit_0.char[2] ),
+ .ZN(_0226_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _0778_ (.I(\vga_clock.vga_0.x_px[7] ),
+ .ZN(_0227_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_1 _0779_ (.A1(_0138_),
+ .A2(_0227_),
+ .ZN(_0228_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_1 _0780_ (.A1(\vga_clock.digit_0.char[2] ),
+ .A2(_0228_),
+ .ZN(_0229_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_1 _0781_ (.A1(\vga_clock.digit_0.char[1] ),
+ .A2(\vga_clock.digit_0.char[2] ),
+ .ZN(_0230_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_1 _0782_ (.A1(_0138_),
+ .A2(\vga_clock.vga_0.x_px[8] ),
+ .ZN(_0231_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__oai22_1 _0783_ (.A1(\vga_clock.sec_u[0] ),
+ .A2(_0138_),
+ .B1(_0231_),
+ .B2(\vga_clock.sec_d[0] ),
+ .ZN(_0232_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_1 _0784_ (.A1(_0230_),
+ .A2(_0232_),
+ .ZN(_0233_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__aoi211_2 _0785_ (.A1(\vga_clock.min_u[0] ),
+ .A2(_0229_),
+ .B(_0233_),
+ .C(\vga_clock.digit_0.char[3] ),
+ .ZN(_0234_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__nand3_1 _0786_ (.A1(\vga_clock.min_d[0] ),
+ .A2(_0146_),
+ .A3(_0226_),
+ .ZN(_0235_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__buf_2 _0787_ (.I(\vga_clock.hrs_u[0] ),
+ .Z(_0236_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__nor3_4 _0788_ (.A1(\vga_clock.vga_0.x_px[9] ),
+ .A2(\vga_clock.vga_0.x_px[8] ),
+ .A3(\vga_clock.digit_0.char[1] ),
+ .ZN(_0237_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_1 _0789_ (.A1(_0236_),
+ .A2(_0237_),
+ .ZN(_0238_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__oai211_1 _0790_ (.A1(_0226_),
+ .A2(_0234_),
+ .B(_0235_),
+ .C(_0238_),
+ .ZN(_0239_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__nand3_2 _0791_ (.A1(_0138_),
+ .A2(_0227_),
+ .A3(_0223_),
+ .ZN(_0240_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__mux2_2 _0792_ (.I0(\vga_clock.hrs_d[0] ),
+ .I1(_0239_),
+ .S(_0240_),
+ .Z(_0241_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__clkbuf_1 _0793_ (.I(_0241_),
+ .Z(\vga_clock.digit_0.number[0] ),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _0794_ (.I(\vga_clock.hrs_d[1] ),
+ .ZN(_0242_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__and2_1 _0795_ (.A1(\vga_clock.digit_0.char[2] ),
+ .A2(_0228_),
+ .Z(_0243_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_1 _0796_ (.A1(\vga_clock.min_u[1] ),
+ .A2(_0243_),
+ .ZN(_0244_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__aoi221_1 _0797_ (.A1(\vga_clock.sec_d[1] ),
+ .A2(_0138_),
+ .B1(_0231_),
+ .B2(\vga_clock.sec_u[1] ),
+ .C(_0230_),
+ .ZN(_0245_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _0798_ (.A1(\vga_clock.digit_0.char[3] ),
+ .A2(_0226_),
+ .ZN(_0246_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_1 _0799_ (.A1(_0244_),
+ .A2(_0245_),
+ .B(_0246_),
+ .ZN(_0247_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _0800_ (.I(\vga_clock.min_d[1] ),
+ .ZN(_0248_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__nand3_1 _0801_ (.A1(_0248_),
+ .A2(_0146_),
+ .A3(_0226_),
+ .ZN(_0249_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _0802_ (.I(\vga_clock.hrs_u[1] ),
+ .ZN(_0250_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_1 _0803_ (.A1(_0250_),
+ .A2(_0138_),
+ .B(_0237_),
+ .ZN(_0251_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__nand3_1 _0804_ (.A1(_0247_),
+ .A2(_0249_),
+ .A3(_0251_),
+ .ZN(_0252_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_1 _0805_ (.A1(_0242_),
+ .A2(_0240_),
+ .B(_0252_),
+ .ZN(_0253_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__clkbuf_1 _0806_ (.I(_0253_),
+ .Z(\vga_clock.digit_0.number[1] ),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__oai22_1 _0807_ (.A1(\vga_clock.sec_u[2] ),
+ .A2(_0138_),
+ .B1(_0231_),
+ .B2(\vga_clock.sec_d[2] ),
+ .ZN(_0254_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_1 _0808_ (.A1(\vga_clock.min_u[2] ),
+ .A2(_0229_),
+ .ZN(_0255_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_1 _0809_ (.A1(_0230_),
+ .A2(_0254_),
+ .B(_0255_),
+ .ZN(_0256_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__nand3_1 _0810_ (.A1(\vga_clock.hrs_u[2] ),
+ .A2(\vga_clock.digit_0.char[0] ),
+ .A3(_0237_),
+ .ZN(_0257_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__nand3_1 _0811_ (.A1(\vga_clock.min_d[2] ),
+ .A2(_0146_),
+ .A3(_0226_),
+ .ZN(_0258_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_1 _0812_ (.A1(_0257_),
+ .A2(_0258_),
+ .ZN(_0259_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__aoi21_2 _0813_ (.A1(_0246_),
+ .A2(_0256_),
+ .B(_0259_),
+ .ZN(_0260_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _0814_ (.I(\vga_clock.sec_u[3] ),
+ .ZN(_0261_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_1 _0815_ (.A1(_0261_),
+ .A2(_0138_),
+ .ZN(_0262_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__oai22_2 _0816_ (.A1(\vga_clock.min_u[3] ),
+ .A2(_0243_),
+ .B1(_0262_),
+ .B2(_0230_),
+ .ZN(_0263_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__inv_1 _0817_ (.I(\vga_clock.hrs_u[3] ),
+ .ZN(_0264_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__aoi222_4 _0818_ (.A1(\vga_clock.vga_0.x_px[8] ),
+ .A2(_0226_),
+ .B1(_0246_),
+ .B2(_0263_),
+ .C1(_0237_),
+ .C2(_0264_),
+ .ZN(_0265_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_1 _0819_ (.A1(_0260_),
+ .A2(_0265_),
+ .ZN(_0266_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__xor2_1 _0820_ (.A1(\vga_clock.digit_0.number[0] ),
+ .A2(_0266_),
+ .Z(_0267_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__clkbuf_1 _0821_ (.I(_0267_),
+ .Z(_0002_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_1 _0822_ (.A1(_0226_),
+ .A2(_0234_),
+ .ZN(_0268_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_1 _0823_ (.A1(_0235_),
+ .A2(_0238_),
+ .ZN(_0269_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_1 _0824_ (.A1(_0268_),
+ .A2(_0269_),
+ .ZN(_0270_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_1 _0825_ (.A1(_0240_),
+ .A2(_0265_),
+ .ZN(_0271_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_1 _0826_ (.A1(_0270_),
+ .A2(_0260_),
+ .B(_0271_),
+ .ZN(_0272_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__xor2_1 _0827_ (.A1(\vga_clock.digit_0.number[1] ),
+ .A2(_0272_),
+ .Z(_0273_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__clkbuf_1 _0828_ (.I(_0273_),
+ .Z(_0003_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__aoi211_1 _0829_ (.A1(\vga_clock.digit_0.number[0] ),
+ .A2(\vga_clock.digit_0.number[1] ),
+ .B(_0260_),
+ .C(_0265_),
+ .ZN(_0274_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _0830_ (.I(_0265_),
+ .ZN(_0275_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_1 _0831_ (.A1(_0252_),
+ .A2(_0275_),
+ .ZN(_0276_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__or2_1 _0832_ (.A1(_0274_),
+ .A2(_0276_),
+ .Z(_0277_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__clkbuf_1 _0833_ (.I(_0277_),
+ .Z(_0004_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_1 _0834_ (.A1(\vga_clock.vga_0.hc[7] ),
+ .A2(\vga_clock.vga_0.hc[6] ),
+ .ZN(_0278_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_1 _0835_ (.A1(\vga_clock.vga_0.hc[8] ),
+ .A2(\vga_clock.vga_0.hc[9] ),
+ .ZN(_0279_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _0836_ (.I(\vga_clock.vga_0.vc[4] ),
+ .ZN(_0280_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _0837_ (.I(\vga_clock.vga_0.vc[3] ),
+ .ZN(_0281_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_1 _0838_ (.A1(_0280_),
+ .A2(_0281_),
+ .ZN(_0282_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__and2_1 _0839_ (.A1(\vga_clock.vga_0.vc[5] ),
+ .A2(_0282_),
+ .Z(_0283_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__or2_1 _0840_ (.A1(\vga_clock.vga_0.vc[6] ),
+ .A2(_0283_),
+ .Z(_0284_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__or2_1 _0841_ (.A1(\vga_clock.vga_0.vc[7] ),
+ .A2(_0284_),
+ .Z(_0285_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__or2_1 _0842_ (.A1(\vga_clock.vga_0.vc[8] ),
+ .A2(_0285_),
+ .Z(_0286_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_1 _0843_ (.A1(\vga_clock.vga_0.vc[9] ),
+ .A2(_0286_),
+ .B(\vga_clock.draw ),
+ .ZN(_0287_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__aoi21_2 _0844_ (.A1(_0278_),
+ .A2(_0279_),
+ .B(_0287_),
+ .ZN(_0288_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__and2_1 _0845_ (.A1(\vga_clock.color[0] ),
+ .A2(_0288_),
+ .Z(_0289_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__clkbuf_1 _0846_ (.I(_0289_),
+ .Z(net7),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__and2_1 _0847_ (.A1(\vga_clock.color[1] ),
+ .A2(_0288_),
+ .Z(_0290_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__clkbuf_1 _0848_ (.I(_0290_),
+ .Z(net8),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__and2_1 _0849_ (.A1(\vga_clock.color[2] ),
+ .A2(_0288_),
+ .Z(_0291_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__clkbuf_1 _0850_ (.I(_0291_),
+ .Z(net9),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__and2_1 _0851_ (.A1(\vga_clock.color[3] ),
+ .A2(_0288_),
+ .Z(_0292_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__clkbuf_1 _0852_ (.I(_0292_),
+ .Z(net10),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__and2_1 _0853_ (.A1(\vga_clock.color[4] ),
+ .A2(_0288_),
+ .Z(_0293_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__clkbuf_1 _0854_ (.I(_0293_),
+ .Z(net11),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__and2_1 _0855_ (.A1(\vga_clock.color[5] ),
+ .A2(_0288_),
+ .Z(_0294_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__clkbuf_1 _0856_ (.I(_0294_),
+ .Z(net12),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__and2_1 _0857_ (.A1(\vga_clock.vga_0.hc[3] ),
+ .A2(\vga_clock.vga_0.hc[4] ),
+ .Z(_0295_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_1 _0858_ (.A1(\vga_clock.vga_0.hc[7] ),
+ .A2(\vga_clock.vga_0.hc[6] ),
+ .ZN(_0296_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__oai211_1 _0859_ (.A1(\vga_clock.vga_0.hc[5] ),
+ .A2(_0295_),
+ .B(_0296_),
+ .C(_0279_),
+ .ZN(net5),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__or3_1 _0860_ (.A1(\vga_clock.vga_0.vc[8] ),
+ .A2(\vga_clock.vga_0.vc[7] ),
+ .A3(\vga_clock.vga_0.vc[5] ),
+ .Z(_0297_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__nor3_1 _0861_ (.A1(\vga_clock.vga_0.vc[6] ),
+ .A2(\vga_clock.vga_0.vc[4] ),
+ .A3(_0297_),
+ .ZN(_0298_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_1 _0862_ (.A1(\vga_clock.vga_0.vc[1] ),
+ .A2(\vga_clock.vga_0.vc[0] ),
+ .B(\vga_clock.vga_0.vc[3] ),
+ .ZN(_0299_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__aoi221_1 _0863_ (.A1(\vga_clock.vga_0.vc[3] ),
+ .A2(\vga_clock.vga_0.vc[2] ),
+ .B1(_0299_),
+ .B2(_0280_),
+ .C(\vga_clock.vga_0.vc[9] ),
+ .ZN(_0300_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_1 _0864_ (.A1(_0298_),
+ .A2(_0300_),
+ .ZN(net6),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_1 _0865_ (.A1(_0151_),
+ .A2(_0161_),
+ .ZN(\vga_clock.y_block[1] ),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_1 _0866_ (.A1(_0139_),
+ .A2(_0142_),
+ .ZN(_0301_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_1 _0867_ (.A1(_0148_),
+ .A2(_0301_),
+ .ZN(_0008_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_1 _0868_ (.A1(\vga_clock.digit_0.number[0] ),
+ .A2(\vga_clock.digit_0.number[1] ),
+ .ZN(_0302_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_1 _0869_ (.A1(_0260_),
+ .A2(_0302_),
+ .B(_0271_),
+ .ZN(_0009_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__and2_1 _0870_ (.A1(_0140_),
+ .A2(_0148_),
+ .Z(_0303_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__clkbuf_1 _0871_ (.I(_0303_),
+ .Z(_0010_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__and2_1 _0872_ (.A1(_0148_),
+ .A2(_0301_),
+ .Z(_0304_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__clkbuf_1 _0873_ (.I(_0304_),
+ .Z(_0011_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__or2_1 _0874_ (.A1(\vga_clock.digit_0.x_block[1] ),
+ .A2(\vga_clock.digit_0.char[3] ),
+ .Z(_0305_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__clkbuf_1 _0875_ (.I(_0305_),
+ .Z(_0012_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__or2_1 _0876_ (.A1(\vga_clock.digit_0.x_block[0] ),
+ .A2(\vga_clock.digit_0.char[3] ),
+ .Z(_0306_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__clkbuf_1 _0877_ (.I(_0306_),
+ .Z(_0013_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__buf_2 _0878_ (.I(net4),
+ .Z(_0307_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_2 _0879_ (.I(_0307_),
+ .ZN(_0308_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__and3_1 _0880_ (.A1(\vga_clock.vga_0.hc[1] ),
+ .A2(\vga_clock.vga_0.hc[0] ),
+ .A3(\vga_clock.vga_0.hc[2] ),
+ .Z(_0309_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__and2_1 _0881_ (.A1(_0295_),
+ .A2(_0309_),
+ .Z(_0310_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_1 _0882_ (.A1(\vga_clock.vga_0.hc[5] ),
+ .A2(_0310_),
+ .ZN(_0311_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_1 _0883_ (.A1(_0296_),
+ .A2(_0311_),
+ .ZN(_0312_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__nand3_4 _0884_ (.A1(\vga_clock.vga_0.hc[8] ),
+ .A2(\vga_clock.vga_0.hc[9] ),
+ .A3(_0312_),
+ .ZN(_0313_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_1 _0885_ (.A1(_0308_),
+ .A2(_0313_),
+ .ZN(_0314_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__buf_2 _0886_ (.I(_0314_),
+ .Z(_0315_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_1 _0887_ (.A1(\vga_clock.vga_0.hc[0] ),
+ .A2(_0315_),
+ .ZN(_0014_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__and3_1 _0888_ (.A1(\vga_clock.vga_0.hc[8] ),
+ .A2(\vga_clock.vga_0.hc[9] ),
+ .A3(_0312_),
+ .Z(_0316_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_1 _0889_ (.A1(_0307_),
+ .A2(_0316_),
+ .ZN(_0317_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_1 _0890_ (.A1(\vga_clock.vga_0.hc[1] ),
+ .A2(\vga_clock.vga_0.hc[0] ),
+ .B(_0317_),
+ .ZN(_0318_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__aoi21_1 _0891_ (.A1(\vga_clock.vga_0.hc[1] ),
+ .A2(\vga_clock.vga_0.hc[0] ),
+ .B(_0318_),
+ .ZN(_0015_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__aoi21_1 _0892_ (.A1(\vga_clock.vga_0.hc[1] ),
+ .A2(\vga_clock.vga_0.hc[0] ),
+ .B(\vga_clock.vga_0.hc[2] ),
+ .ZN(_0319_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__nor3_1 _0893_ (.A1(_0309_),
+ .A2(_0315_),
+ .A3(_0319_),
+ .ZN(_0016_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__and2_1 _0894_ (.A1(\vga_clock.vga_0.hc[3] ),
+ .A2(_0309_),
+ .Z(_0320_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_1 _0895_ (.A1(\vga_clock.vga_0.hc[3] ),
+ .A2(_0309_),
+ .ZN(_0321_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__nor3_1 _0896_ (.A1(_0320_),
+ .A2(_0315_),
+ .A3(_0321_),
+ .ZN(_0017_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_1 _0897_ (.A1(\vga_clock.vga_0.hc[4] ),
+ .A2(_0320_),
+ .ZN(_0322_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__nor3_1 _0898_ (.A1(_0310_),
+ .A2(_0315_),
+ .A3(_0322_),
+ .ZN(_0018_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__and2_1 _0899_ (.A1(\vga_clock.vga_0.hc[5] ),
+ .A2(_0310_),
+ .Z(_0323_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_1 _0900_ (.A1(\vga_clock.vga_0.hc[5] ),
+ .A2(_0310_),
+ .ZN(_0324_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__nor3_1 _0901_ (.A1(_0323_),
+ .A2(_0315_),
+ .A3(_0324_),
+ .ZN(_0019_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_1 _0902_ (.A1(\vga_clock.vga_0.hc[6] ),
+ .A2(_0323_),
+ .B(_0317_),
+ .ZN(_0325_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__aoi21_1 _0903_ (.A1(\vga_clock.vga_0.hc[6] ),
+ .A2(_0323_),
+ .B(_0325_),
+ .ZN(_0020_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_1 _0904_ (.A1(_0278_),
+ .A2(_0311_),
+ .ZN(_0326_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__aoi21_1 _0905_ (.A1(\vga_clock.vga_0.hc[6] ),
+ .A2(_0323_),
+ .B(\vga_clock.vga_0.hc[7] ),
+ .ZN(_0327_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__nor3_1 _0906_ (.A1(_0315_),
+ .A2(_0326_),
+ .A3(_0327_),
+ .ZN(_0021_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_1 _0907_ (.A1(\vga_clock.vga_0.hc[8] ),
+ .A2(_0326_),
+ .B(_0317_),
+ .ZN(_0328_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__aoi21_1 _0908_ (.A1(\vga_clock.vga_0.hc[8] ),
+ .A2(_0326_),
+ .B(_0328_),
+ .ZN(_0022_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__aoi21_1 _0909_ (.A1(\vga_clock.vga_0.hc[8] ),
+ .A2(_0326_),
+ .B(\vga_clock.vga_0.hc[9] ),
+ .ZN(_0329_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_1 _0910_ (.A1(_0315_),
+ .A2(_0329_),
+ .ZN(_0023_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_1 _0911_ (.A1(\vga_clock.sec_counter[4] ),
+ .A2(\vga_clock.sec_counter[8] ),
+ .ZN(_0330_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _0912_ (.I(\vga_clock.sec_counter[15] ),
+ .ZN(_0331_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _0913_ (.I(\vga_clock.sec_counter[21] ),
+ .ZN(_0332_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__or4_1 _0914_ (.A1(\vga_clock.sec_counter[19] ),
+ .A2(\vga_clock.sec_counter[18] ),
+ .A3(\vga_clock.sec_counter[20] ),
+ .A4(_0332_),
+ .Z(_0333_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__nor3_1 _0915_ (.A1(_0331_),
+ .A2(\vga_clock.sec_counter[16] ),
+ .A3(_0333_),
+ .ZN(_0334_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _0916_ (.I(\vga_clock.sec_counter[25] ),
+ .ZN(_0335_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__nand4_1 _0917_ (.A1(\vga_clock.sec_counter[23] ),
+ .A2(\vga_clock.sec_counter[22] ),
+ .A3(_0335_),
+ .A4(\vga_clock.sec_counter[24] ),
+ .ZN(_0336_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__nor3_1 _0918_ (.A1(\vga_clock.sec_counter[14] ),
+ .A2(\vga_clock.sec_counter[17] ),
+ .A3(_0336_),
+ .ZN(_0337_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_1 _0919_ (.A1(\vga_clock.sec_counter[0] ),
+ .A2(\vga_clock.sec_counter[1] ),
+ .ZN(_0338_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_1 _0920_ (.A1(\vga_clock.sec_counter[3] ),
+ .A2(\vga_clock.sec_counter[2] ),
+ .ZN(_0339_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__and2_1 _0921_ (.A1(\vga_clock.sec_counter[7] ),
+ .A2(\vga_clock.sec_counter[6] ),
+ .Z(_0340_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__nand3_1 _0922_ (.A1(_0338_),
+ .A2(_0339_),
+ .A3(_0340_),
+ .ZN(_0341_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__inv_1 _0923_ (.I(\vga_clock.sec_counter[11] ),
+ .ZN(_0342_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__inv_1 _0924_ (.I(\vga_clock.sec_counter[12] ),
+ .ZN(_0343_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__nand4_1 _0925_ (.A1(_0342_),
+ .A2(\vga_clock.sec_counter[10] ),
+ .A3(_0343_),
+ .A4(\vga_clock.sec_counter[13] ),
+ .ZN(_0344_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_1 _0926_ (.A1(\vga_clock.sec_counter[5] ),
+ .A2(\vga_clock.sec_counter[9] ),
+ .ZN(_0345_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__nor3_1 _0927_ (.A1(_0341_),
+ .A2(_0344_),
+ .A3(_0345_),
+ .ZN(_0346_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__nand4_1 _0928_ (.A1(_0330_),
+ .A2(_0334_),
+ .A3(_0337_),
+ .A4(_0346_),
+ .ZN(_0347_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_1 _0929_ (.A1(_0308_),
+ .A2(_0347_),
+ .ZN(_0348_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__buf_2 _0930_ (.I(_0348_),
+ .Z(_0349_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_1 _0931_ (.A1(\vga_clock.sec_counter[0] ),
+ .A2(_0349_),
+ .ZN(_0024_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__and2_1 _0932_ (.A1(\vga_clock.sec_counter[0] ),
+ .A2(\vga_clock.sec_counter[1] ),
+ .Z(_0350_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__nor3_1 _0933_ (.A1(_0338_),
+ .A2(_0349_),
+ .A3(_0350_),
+ .ZN(_0025_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__and2_1 _0934_ (.A1(\vga_clock.sec_counter[2] ),
+ .A2(_0350_),
+ .Z(_0351_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_1 _0935_ (.A1(\vga_clock.sec_counter[2] ),
+ .A2(_0350_),
+ .ZN(_0352_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__nor3_1 _0936_ (.A1(_0349_),
+ .A2(_0351_),
+ .A3(_0352_),
+ .ZN(_0026_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__and4_1 _0937_ (.A1(\vga_clock.sec_counter[0] ),
+ .A2(\vga_clock.sec_counter[1] ),
+ .A3(\vga_clock.sec_counter[3] ),
+ .A4(\vga_clock.sec_counter[2] ),
+ .Z(_0353_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_1 _0938_ (.A1(\vga_clock.sec_counter[3] ),
+ .A2(_0351_),
+ .ZN(_0354_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__nor3_1 _0939_ (.A1(_0349_),
+ .A2(_0353_),
+ .A3(_0354_),
+ .ZN(_0027_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__and2_1 _0940_ (.A1(\vga_clock.sec_counter[4] ),
+ .A2(_0353_),
+ .Z(_0355_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_1 _0941_ (.A1(\vga_clock.sec_counter[4] ),
+ .A2(_0353_),
+ .ZN(_0356_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__nor3_1 _0942_ (.A1(_0349_),
+ .A2(_0355_),
+ .A3(_0356_),
+ .ZN(_0028_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__and2_1 _0943_ (.A1(\vga_clock.sec_counter[5] ),
+ .A2(_0355_),
+ .Z(_0357_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_1 _0944_ (.A1(\vga_clock.sec_counter[5] ),
+ .A2(_0355_),
+ .ZN(_0358_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__nor3_1 _0945_ (.A1(_0349_),
+ .A2(_0357_),
+ .A3(_0358_),
+ .ZN(_0029_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__xnor2_1 _0946_ (.A1(\vga_clock.sec_counter[6] ),
+ .A2(_0357_),
+ .ZN(_0359_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_1 _0947_ (.A1(_0349_),
+ .A2(_0359_),
+ .ZN(_0030_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__aoi21_1 _0948_ (.A1(\vga_clock.sec_counter[6] ),
+ .A2(_0357_),
+ .B(\vga_clock.sec_counter[7] ),
+ .ZN(_0360_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__and4_1 _0949_ (.A1(\vga_clock.sec_counter[4] ),
+ .A2(\vga_clock.sec_counter[5] ),
+ .A3(_0340_),
+ .A4(_0353_),
+ .Z(_0361_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__nor3_1 _0950_ (.A1(_0349_),
+ .A2(_0360_),
+ .A3(_0361_),
+ .ZN(_0031_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__buf_2 _0951_ (.I(_0348_),
+ .Z(_0362_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_1 _0952_ (.A1(\vga_clock.sec_counter[8] ),
+ .A2(_0361_),
+ .ZN(_0363_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__and2_1 _0953_ (.A1(\vga_clock.sec_counter[8] ),
+ .A2(_0361_),
+ .Z(_0364_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__nor3_1 _0954_ (.A1(_0362_),
+ .A2(_0363_),
+ .A3(_0364_),
+ .ZN(_0032_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_1 _0955_ (.A1(\vga_clock.sec_counter[9] ),
+ .A2(_0364_),
+ .ZN(_0365_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__and2_1 _0956_ (.A1(\vga_clock.sec_counter[9] ),
+ .A2(_0364_),
+ .Z(_0366_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__nor3_1 _0957_ (.A1(_0362_),
+ .A2(_0365_),
+ .A3(_0366_),
+ .ZN(_0033_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_1 _0958_ (.A1(\vga_clock.sec_counter[10] ),
+ .A2(_0366_),
+ .ZN(_0367_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__and2_1 _0959_ (.A1(\vga_clock.sec_counter[10] ),
+ .A2(_0366_),
+ .Z(_0368_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__nor3_1 _0960_ (.A1(_0362_),
+ .A2(_0367_),
+ .A3(_0368_),
+ .ZN(_0034_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_1 _0961_ (.A1(\vga_clock.sec_counter[11] ),
+ .A2(_0368_),
+ .ZN(_0369_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__nand4_4 _0962_ (.A1(\vga_clock.sec_counter[8] ),
+ .A2(\vga_clock.sec_counter[9] ),
+ .A3(\vga_clock.sec_counter[10] ),
+ .A4(_0361_),
+ .ZN(_0370_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_1 _0963_ (.A1(_0342_),
+ .A2(_0370_),
+ .ZN(_0371_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__nor3_1 _0964_ (.A1(_0362_),
+ .A2(_0369_),
+ .A3(_0371_),
+ .ZN(_0035_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__xor2_1 _0965_ (.A1(_0343_),
+ .A2(_0371_),
+ .Z(_0372_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_1 _0966_ (.A1(_0349_),
+ .A2(_0372_),
+ .ZN(_0036_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__aoi21_1 _0967_ (.A1(\vga_clock.sec_counter[12] ),
+ .A2(_0371_),
+ .B(\vga_clock.sec_counter[13] ),
+ .ZN(_0373_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _0968_ (.I(\vga_clock.sec_counter[13] ),
+ .ZN(_0374_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__nor4_4 _0969_ (.A1(_0342_),
+ .A2(_0343_),
+ .A3(_0374_),
+ .A4(_0370_),
+ .ZN(_0375_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__nor3_1 _0970_ (.A1(_0362_),
+ .A2(_0373_),
+ .A3(_0375_),
+ .ZN(_0037_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_1 _0971_ (.A1(\vga_clock.sec_counter[14] ),
+ .A2(_0375_),
+ .ZN(_0376_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__and2_1 _0972_ (.A1(\vga_clock.sec_counter[14] ),
+ .A2(_0375_),
+ .Z(_0377_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__nor3_1 _0973_ (.A1(_0362_),
+ .A2(_0376_),
+ .A3(_0377_),
+ .ZN(_0038_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_1 _0974_ (.A1(\vga_clock.sec_counter[15] ),
+ .A2(_0377_),
+ .ZN(_0378_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__aoi211_1 _0975_ (.A1(\vga_clock.sec_counter[15] ),
+ .A2(_0377_),
+ .B(_0378_),
+ .C(_0348_),
+ .ZN(_0039_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__aoi21_1 _0976_ (.A1(\vga_clock.sec_counter[15] ),
+ .A2(_0377_),
+ .B(\vga_clock.sec_counter[16] ),
+ .ZN(_0379_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__and4_1 _0977_ (.A1(\vga_clock.sec_counter[14] ),
+ .A2(\vga_clock.sec_counter[15] ),
+ .A3(\vga_clock.sec_counter[16] ),
+ .A4(_0375_),
+ .Z(_0380_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__nor3_1 _0978_ (.A1(_0362_),
+ .A2(_0379_),
+ .A3(_0380_),
+ .ZN(_0040_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_1 _0979_ (.A1(\vga_clock.sec_counter[17] ),
+ .A2(_0380_),
+ .ZN(_0381_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__and2_1 _0980_ (.A1(\vga_clock.sec_counter[17] ),
+ .A2(_0380_),
+ .Z(_0382_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__nor3_1 _0981_ (.A1(_0362_),
+ .A2(_0381_),
+ .A3(_0382_),
+ .ZN(_0041_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__aoi21_1 _0982_ (.A1(\vga_clock.sec_counter[18] ),
+ .A2(_0382_),
+ .B(_0348_),
+ .ZN(_0383_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_1 _0983_ (.A1(\vga_clock.sec_counter[18] ),
+ .A2(_0382_),
+ .B(_0383_),
+ .ZN(_0384_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _0984_ (.I(_0384_),
+ .ZN(_0042_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__aoi21_1 _0985_ (.A1(\vga_clock.sec_counter[18] ),
+ .A2(_0382_),
+ .B(\vga_clock.sec_counter[19] ),
+ .ZN(_0385_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__and4_1 _0986_ (.A1(\vga_clock.sec_counter[17] ),
+ .A2(\vga_clock.sec_counter[19] ),
+ .A3(\vga_clock.sec_counter[18] ),
+ .A4(_0380_),
+ .Z(_0386_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__nor3_1 _0987_ (.A1(_0362_),
+ .A2(_0385_),
+ .A3(_0386_),
+ .ZN(_0043_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__and2_1 _0988_ (.A1(\vga_clock.sec_counter[20] ),
+ .A2(_0386_),
+ .Z(_0387_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _0989_ (.I(_0348_),
+ .ZN(_0388_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_1 _0990_ (.A1(\vga_clock.sec_counter[20] ),
+ .A2(_0386_),
+ .B(_0388_),
+ .ZN(_0389_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_1 _0991_ (.A1(_0387_),
+ .A2(_0389_),
+ .ZN(_0044_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_1 _0992_ (.A1(\vga_clock.sec_counter[21] ),
+ .A2(_0387_),
+ .B(_0388_),
+ .ZN(_0390_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__aoi21_1 _0993_ (.A1(\vga_clock.sec_counter[21] ),
+ .A2(_0387_),
+ .B(_0390_),
+ .ZN(_0045_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__aoi21_1 _0994_ (.A1(\vga_clock.sec_counter[21] ),
+ .A2(_0387_),
+ .B(\vga_clock.sec_counter[22] ),
+ .ZN(_0391_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__and4_1 _0995_ (.A1(\vga_clock.sec_counter[20] ),
+ .A2(\vga_clock.sec_counter[21] ),
+ .A3(\vga_clock.sec_counter[22] ),
+ .A4(_0386_),
+ .Z(_0392_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__nor3_1 _0996_ (.A1(_0362_),
+ .A2(_0391_),
+ .A3(_0392_),
+ .ZN(_0046_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _0997_ (.I(\vga_clock.sec_counter[23] ),
+ .ZN(_0393_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__nand4_2 _0998_ (.A1(\vga_clock.sec_counter[20] ),
+ .A2(\vga_clock.sec_counter[21] ),
+ .A3(\vga_clock.sec_counter[22] ),
+ .A4(_0386_),
+ .ZN(_0394_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_1 _0999_ (.A1(_0393_),
+ .A2(_0394_),
+ .ZN(_0395_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_1 _1000_ (.A1(\vga_clock.sec_counter[23] ),
+ .A2(_0392_),
+ .ZN(_0396_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__and3_1 _1001_ (.A1(_0388_),
+ .A2(_0395_),
+ .A3(_0396_),
+ .Z(_0397_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__clkbuf_1 _1002_ (.I(_0397_),
+ .Z(_0047_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _1003_ (.I(\vga_clock.sec_counter[24] ),
+ .ZN(_0398_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__oai31_1 _1004_ (.A1(_0393_),
+ .A2(_0398_),
+ .A3(_0394_),
+ .B(_0388_),
+ .ZN(_0399_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__aoi21_1 _1005_ (.A1(_0398_),
+ .A2(_0396_),
+ .B(_0399_),
+ .ZN(_0048_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__nand4_1 _1006_ (.A1(\vga_clock.sec_counter[23] ),
+ .A2(_0335_),
+ .A3(\vga_clock.sec_counter[24] ),
+ .A4(_0392_),
+ .ZN(_0400_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__oai31_1 _1007_ (.A1(_0393_),
+ .A2(_0398_),
+ .A3(_0394_),
+ .B(\vga_clock.sec_counter[25] ),
+ .ZN(_0401_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__aoi21_1 _1008_ (.A1(_0400_),
+ .A2(_0401_),
+ .B(_0349_),
+ .ZN(_0049_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__buf_2 _1009_ (.I(_0308_),
+ .Z(_0402_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__and2_1 _1010_ (.A1(\vga_clock.vga_0.hc[0] ),
+ .A2(_0402_),
+ .Z(_0403_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__clkbuf_1 _1011_ (.I(_0403_),
+ .Z(_0050_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__and2_1 _1012_ (.A1(\vga_clock.vga_0.hc[1] ),
+ .A2(_0402_),
+ .Z(_0404_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__clkbuf_1 _1013_ (.I(_0404_),
+ .Z(_0051_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__and2_1 _1014_ (.A1(\vga_clock.vga_0.hc[2] ),
+ .A2(_0402_),
+ .Z(_0405_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__clkbuf_1 _1015_ (.I(_0405_),
+ .Z(_0052_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__and2_1 _1016_ (.A1(\vga_clock.vga_0.hc[3] ),
+ .A2(_0402_),
+ .Z(_0406_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__clkbuf_1 _1017_ (.I(_0406_),
+ .Z(_0053_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__buf_2 _1018_ (.I(_0308_),
+ .Z(_0407_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__and2_1 _1019_ (.A1(\vga_clock.vga_0.hc[4] ),
+ .A2(_0407_),
+ .Z(_0408_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__clkbuf_1 _1020_ (.I(_0408_),
+ .Z(_0054_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__and2_1 _1021_ (.A1(\vga_clock.vga_0.hc[5] ),
+ .A2(_0407_),
+ .Z(_0409_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__clkbuf_1 _1022_ (.I(_0409_),
+ .Z(_0055_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__buf_2 _1023_ (.I(_0307_),
+ .Z(_0410_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__buf_2 _1024_ (.I(_0410_),
+ .Z(_0411_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_1 _1025_ (.A1(\vga_clock.vga_0.hc[6] ),
+ .A2(_0411_),
+ .ZN(_0056_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_1 _1026_ (.A1(_0407_),
+ .A2(_0278_),
+ .ZN(_0412_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_1 _1027_ (.A1(_0296_),
+ .A2(_0412_),
+ .ZN(_0057_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _1028_ (.I(\vga_clock.vga_0.hc[8] ),
+ .ZN(_0413_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_1 _1029_ (.A1(_0413_),
+ .A2(_0278_),
+ .ZN(_0414_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__nand3_1 _1030_ (.A1(\vga_clock.vga_0.hc[8] ),
+ .A2(\vga_clock.vga_0.hc[7] ),
+ .A3(\vga_clock.vga_0.hc[6] ),
+ .ZN(_0415_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__buf_2 _1031_ (.I(_0410_),
+ .Z(_0416_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__aoi21_1 _1032_ (.A1(_0414_),
+ .A2(_0415_),
+ .B(_0416_),
+ .ZN(_0058_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__xor2_1 _1033_ (.A1(\vga_clock.vga_0.hc[9] ),
+ .A2(_0414_),
+ .Z(_0417_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_1 _1034_ (.A1(_0411_),
+ .A2(_0417_),
+ .ZN(_0059_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _1035_ (.I(\vga_clock.vga_0.vc[0] ),
+ .ZN(_0418_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_1 _1036_ (.A1(_0418_),
+ .A2(_0411_),
+ .ZN(_0060_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__inv_1 _1037_ (.I(\vga_clock.vga_0.vc[1] ),
+ .ZN(_0419_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_1 _1038_ (.A1(_0419_),
+ .A2(_0411_),
+ .ZN(_0061_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _1039_ (.I(\vga_clock.vga_0.vc[2] ),
+ .ZN(_0420_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_1 _1040_ (.A1(_0420_),
+ .A2(_0411_),
+ .ZN(_0062_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_1 _1041_ (.A1(\vga_clock.vga_0.vc[3] ),
+ .A2(_0411_),
+ .ZN(_0063_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_1 _1042_ (.A1(\vga_clock.vga_0.vc[4] ),
+ .A2(\vga_clock.vga_0.vc[3] ),
+ .ZN(_0421_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__aoi21_1 _1043_ (.A1(_0282_),
+ .A2(_0421_),
+ .B(_0416_),
+ .ZN(_0064_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__buf_2 _1044_ (.I(_0307_),
+ .Z(_0422_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_1 _1045_ (.A1(\vga_clock.vga_0.vc[5] ),
+ .A2(_0282_),
+ .ZN(_0423_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__nor3_1 _1046_ (.A1(_0422_),
+ .A2(_0283_),
+ .A3(_0423_),
+ .ZN(_0065_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_1 _1047_ (.A1(\vga_clock.vga_0.vc[6] ),
+ .A2(_0283_),
+ .ZN(_0424_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__aoi21_1 _1048_ (.A1(_0284_),
+ .A2(_0424_),
+ .B(_0416_),
+ .ZN(_0066_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_1 _1049_ (.A1(\vga_clock.vga_0.vc[7] ),
+ .A2(_0284_),
+ .ZN(_0425_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__aoi21_1 _1050_ (.A1(_0285_),
+ .A2(_0425_),
+ .B(_0416_),
+ .ZN(_0067_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_1 _1051_ (.A1(\vga_clock.vga_0.vc[8] ),
+ .A2(_0285_),
+ .ZN(_0426_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__aoi21_1 _1052_ (.A1(_0286_),
+ .A2(_0426_),
+ .B(_0422_),
+ .ZN(_0068_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__xor2_1 _1053_ (.A1(\vga_clock.vga_0.vc[9] ),
+ .A2(_0286_),
+ .Z(_0427_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_1 _1054_ (.A1(_0411_),
+ .A2(_0427_),
+ .ZN(_0069_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_1 _1055_ (.A1(_0419_),
+ .A2(_0418_),
+ .ZN(_0428_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__aoi21_1 _1056_ (.A1(\vga_clock.vga_0.vc[2] ),
+ .A2(_0428_),
+ .B(\vga_clock.vga_0.vc[3] ),
+ .ZN(_0429_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_1 _1057_ (.A1(_0298_),
+ .A2(_0429_),
+ .ZN(_0430_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_1 _1058_ (.A1(\vga_clock.vga_0.vc[9] ),
+ .A2(_0430_),
+ .ZN(_0431_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _1059_ (.I(_0431_),
+ .ZN(_0432_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _1060_ (.A1(_0313_),
+ .A2(_0432_),
+ .ZN(_0433_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_1 _1061_ (.A1(\vga_clock.vga_0.vc[0] ),
+ .A2(_0433_),
+ .ZN(_0434_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__buf_2 _1062_ (.I(_0307_),
+ .Z(_0435_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__aoi211_1 _1063_ (.A1(\vga_clock.vga_0.vc[0] ),
+ .A2(_0316_),
+ .B(_0434_),
+ .C(_0435_),
+ .ZN(_0070_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_1 _1064_ (.A1(\vga_clock.vga_0.vc[1] ),
+ .A2(\vga_clock.vga_0.vc[0] ),
+ .ZN(_0436_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_1 _1065_ (.A1(_0308_),
+ .A2(_0433_),
+ .ZN(_0437_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__oai32_1 _1066_ (.A1(_0436_),
+ .A2(_0428_),
+ .A3(_0437_),
+ .B1(_0315_),
+ .B2(_0419_),
+ .ZN(_0071_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__xor2_1 _1067_ (.A1(\vga_clock.vga_0.vc[2] ),
+ .A2(_0428_),
+ .Z(_0438_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__aoi22_1 _1068_ (.A1(\vga_clock.vga_0.vc[2] ),
+ .A2(_0313_),
+ .B1(_0433_),
+ .B2(_0438_),
+ .ZN(_0439_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_1 _1069_ (.A1(_0411_),
+ .A2(_0439_),
+ .ZN(_0072_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__nor4_2 _1070_ (.A1(_0281_),
+ .A2(_0420_),
+ .A3(_0419_),
+ .A4(_0418_),
+ .ZN(_0440_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__oai32_1 _1071_ (.A1(_0429_),
+ .A2(_0437_),
+ .A3(_0440_),
+ .B1(_0315_),
+ .B2(_0281_),
+ .ZN(_0073_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_1 _1072_ (.A1(\vga_clock.vga_0.vc[4] ),
+ .A2(_0440_),
+ .ZN(_0441_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__and2_1 _1073_ (.A1(\vga_clock.vga_0.vc[4] ),
+ .A2(_0440_),
+ .Z(_0442_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__oai32_1 _1074_ (.A1(_0437_),
+ .A2(_0441_),
+ .A3(_0442_),
+ .B1(_0315_),
+ .B2(_0280_),
+ .ZN(_0074_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__xor2_1 _1075_ (.A1(\vga_clock.vga_0.vc[5] ),
+ .A2(_0442_),
+ .Z(_0443_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__aoi22_1 _1076_ (.A1(\vga_clock.vga_0.vc[5] ),
+ .A2(_0313_),
+ .B1(_0433_),
+ .B2(_0443_),
+ .ZN(_0444_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_1 _1077_ (.A1(_0411_),
+ .A2(_0444_),
+ .ZN(_0075_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_1 _1078_ (.A1(\vga_clock.vga_0.vc[5] ),
+ .A2(_0442_),
+ .ZN(_0445_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__xnor2_1 _1079_ (.A1(\vga_clock.vga_0.vc[6] ),
+ .A2(_0445_),
+ .ZN(_0446_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__aoi22_1 _1080_ (.A1(\vga_clock.vga_0.vc[6] ),
+ .A2(_0313_),
+ .B1(_0433_),
+ .B2(_0446_),
+ .ZN(_0447_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_1 _1081_ (.A1(_0411_),
+ .A2(_0447_),
+ .ZN(_0076_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _1082_ (.I(\vga_clock.vga_0.vc[7] ),
+ .ZN(_0448_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__nand3_1 _1083_ (.A1(\vga_clock.vga_0.vc[6] ),
+ .A2(\vga_clock.vga_0.vc[5] ),
+ .A3(_0442_),
+ .ZN(_0449_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__xor2_1 _1084_ (.A1(_0448_),
+ .A2(_0449_),
+ .Z(_0450_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__aoi22_1 _1085_ (.A1(\vga_clock.vga_0.vc[7] ),
+ .A2(_0313_),
+ .B1(_0433_),
+ .B2(_0450_),
+ .ZN(_0451_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_1 _1086_ (.A1(_0416_),
+ .A2(_0451_),
+ .ZN(_0077_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_1 _1087_ (.A1(_0448_),
+ .A2(_0449_),
+ .ZN(_0452_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__xor2_1 _1088_ (.A1(\vga_clock.vga_0.vc[8] ),
+ .A2(_0452_),
+ .Z(_0453_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__aoi22_1 _1089_ (.A1(\vga_clock.vga_0.vc[8] ),
+ .A2(_0313_),
+ .B1(_0433_),
+ .B2(_0453_),
+ .ZN(_0454_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_1 _1090_ (.A1(_0416_),
+ .A2(_0454_),
+ .ZN(_0078_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__nand3_1 _1091_ (.A1(\vga_clock.vga_0.vc[8] ),
+ .A2(_0316_),
+ .A3(_0452_),
+ .ZN(_0455_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _1092_ (.I(\vga_clock.vga_0.vc[9] ),
+ .ZN(_0456_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__aoi221_1 _1093_ (.A1(_0316_),
+ .A2(_0432_),
+ .B1(_0455_),
+ .B2(_0456_),
+ .C(_0410_),
+ .ZN(_0079_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _1094_ (.I(_0142_),
+ .ZN(_0457_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__nor3_1 _1095_ (.A1(_0139_),
+ .A2(_0148_),
+ .A3(_0457_),
+ .ZN(_0080_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__or2_1 _1096_ (.A1(\vga_clock.pulse_hrs.count[1] ),
+ .A2(\vga_clock.pulse_hrs.count[0] ),
+ .Z(_0458_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__nor4_4 _1097_ (.A1(\vga_clock.pulse_hrs.count[4] ),
+ .A2(\vga_clock.pulse_hrs.count[3] ),
+ .A3(\vga_clock.pulse_hrs.count[2] ),
+ .A4(_0458_),
+ .ZN(_0459_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__oai31_1 _1098_ (.A1(\vga_clock.pulse_hrs.comp[4] ),
+ .A2(\vga_clock.pulse_hrs.comp[3] ),
+ .A3(\vga_clock.pulse_hrs.comp[2] ),
+ .B(_0459_),
+ .ZN(_0460_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_1 _1099_ (.A1(net2),
+ .A2(_0460_),
+ .ZN(_0461_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__nor3_1 _1100_ (.A1(\vga_clock.vga_0.x_px[2] ),
+ .A2(\vga_clock.digit_0.x_block[1] ),
+ .A3(\vga_clock.digit_0.x_block[0] ),
+ .ZN(_0462_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__nor4_1 _1101_ (.A1(\vga_clock.vga_0.y_px[8] ),
+ .A2(\vga_clock.vga_0.x_px[1] ),
+ .A3(\vga_clock.vga_0.x_px[0] ),
+ .A4(\vga_clock.vga_0.x_px[3] ),
+ .ZN(_0463_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_1 _1102_ (.A1(_0462_),
+ .A2(_0463_),
+ .ZN(_0464_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_1 _1103_ (.A1(\vga_clock.vga_0.y_px[1] ),
+ .A2(\vga_clock.vga_0.y_px[0] ),
+ .ZN(_0465_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__nor4_1 _1104_ (.A1(\vga_clock.vga_0.y_px[2] ),
+ .A2(\vga_clock.vga_0.y_px[7] ),
+ .A3(\vga_clock.vga_0.y_px[6] ),
+ .A4(\vga_clock.vga_0.y_px[9] ),
+ .ZN(_0466_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_1 _1105_ (.A1(_0465_),
+ .A2(_0466_),
+ .ZN(_0467_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__nor4_4 _1106_ (.A1(_0151_),
+ .A2(_0224_),
+ .A3(_0464_),
+ .A4(_0467_),
+ .ZN(_0468_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__buf_2 _1107_ (.I(_0468_),
+ .Z(_0469_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_1 _1108_ (.A1(_0461_),
+ .A2(_0469_),
+ .ZN(_0470_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__nand3_1 _1109_ (.A1(net2),
+ .A2(_0461_),
+ .A3(_0469_),
+ .ZN(_0471_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_1 _1110_ (.A1(\vga_clock.pulse_hrs.comp[0] ),
+ .A2(_0471_),
+ .ZN(_0472_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__oai211_1 _1111_ (.A1(\vga_clock.pulse_hrs.comp[0] ),
+ .A2(_0470_),
+ .B(_0472_),
+ .C(_0402_),
+ .ZN(_0081_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_1 _1112_ (.A1(\vga_clock.pulse_hrs.comp[0] ),
+ .A2(_0470_),
+ .B(\vga_clock.pulse_hrs.comp[1] ),
+ .ZN(_0473_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__or2_1 _1113_ (.A1(\vga_clock.pulse_hrs.comp[1] ),
+ .A2(\vga_clock.pulse_hrs.comp[0] ),
+ .Z(_0474_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__aoi21_1 _1114_ (.A1(net2),
+ .A2(_0474_),
+ .B(_0470_),
+ .ZN(_0475_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_1 _1115_ (.A1(_0435_),
+ .A2(_0475_),
+ .ZN(_0476_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_1 _1116_ (.A1(_0473_),
+ .A2(_0476_),
+ .ZN(_0082_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _1117_ (.I(\vga_clock.pulse_hrs.comp[2] ),
+ .ZN(_0477_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__or2_1 _1118_ (.A1(_0477_),
+ .A2(_0474_),
+ .Z(_0478_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__oai22_1 _1119_ (.A1(\vga_clock.pulse_hrs.comp[2] ),
+ .A2(_0475_),
+ .B1(_0478_),
+ .B2(_0471_),
+ .ZN(_0479_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_1 _1120_ (.A1(_0402_),
+ .A2(_0479_),
+ .ZN(_0083_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _1121_ (.I(\vga_clock.pulse_hrs.comp[3] ),
+ .ZN(_0480_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__nor3_1 _1122_ (.A1(\vga_clock.pulse_hrs.comp[2] ),
+ .A2(_0470_),
+ .A3(_0474_),
+ .ZN(_0481_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_1 _1123_ (.A1(\vga_clock.pulse_hrs.comp[3] ),
+ .A2(\vga_clock.pulse_hrs.comp[2] ),
+ .B(net2),
+ .ZN(_0482_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__aoi21_1 _1124_ (.A1(_0475_),
+ .A2(_0482_),
+ .B(_0410_),
+ .ZN(_0483_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_1 _1125_ (.A1(_0480_),
+ .A2(_0481_),
+ .B(_0483_),
+ .ZN(_0084_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__and2_1 _1126_ (.A1(\vga_clock.pulse_hrs.comp[4] ),
+ .A2(_0483_),
+ .Z(_0484_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__clkbuf_1 _1127_ (.I(_0484_),
+ .Z(_0085_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _1128_ (.I(\vga_clock.pulse_hrs.count[0] ),
+ .ZN(_0485_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__xor2_1 _1129_ (.A1(\vga_clock.pulse_hrs.count[3] ),
+ .A2(\vga_clock.pulse_hrs.comp[3] ),
+ .Z(_0486_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__aoi221_2 _1130_ (.A1(\vga_clock.pulse_hrs.count[2] ),
+ .A2(_0477_),
+ .B1(\vga_clock.pulse_hrs.comp[0] ),
+ .B2(_0485_),
+ .C(_0486_),
+ .ZN(_0487_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__xor2_1 _1131_ (.A1(\vga_clock.pulse_hrs.count[1] ),
+ .A2(\vga_clock.pulse_hrs.comp[1] ),
+ .Z(_0488_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__oai22_1 _1132_ (.A1(\vga_clock.pulse_hrs.count[2] ),
+ .A2(_0477_),
+ .B1(\vga_clock.pulse_hrs.comp[0] ),
+ .B2(_0485_),
+ .ZN(_0489_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__xor2_1 _1133_ (.A1(\vga_clock.pulse_hrs.count[4] ),
+ .A2(\vga_clock.pulse_hrs.comp[4] ),
+ .Z(_0490_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__nor3_1 _1134_ (.A1(_0488_),
+ .A2(_0489_),
+ .A3(_0490_),
+ .ZN(_0491_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_1 _1135_ (.A1(net2),
+ .A2(_0468_),
+ .ZN(_0492_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__aoi21_2 _1136_ (.A1(_0487_),
+ .A2(_0491_),
+ .B(_0492_),
+ .ZN(_0493_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_1 _1137_ (.A1(\vga_clock.pulse_hrs.count[0] ),
+ .A2(_0493_),
+ .B(_0407_),
+ .ZN(_0494_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__aoi21_1 _1138_ (.A1(\vga_clock.pulse_hrs.count[0] ),
+ .A2(_0469_),
+ .B(_0494_),
+ .ZN(_0086_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__inv_2 _1139_ (.I(_0469_),
+ .ZN(_0495_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_1 _1140_ (.A1(\vga_clock.pulse_hrs.count[1] ),
+ .A2(_0495_),
+ .ZN(_0496_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_1 _1141_ (.A1(\vga_clock.pulse_hrs.count[1] ),
+ .A2(\vga_clock.pulse_hrs.count[0] ),
+ .ZN(_0497_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__nand3_1 _1142_ (.A1(_0458_),
+ .A2(_0493_),
+ .A3(_0497_),
+ .ZN(_0498_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__aoi21_1 _1143_ (.A1(_0496_),
+ .A2(_0498_),
+ .B(_0422_),
+ .ZN(_0087_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _1144_ (.I(\vga_clock.pulse_hrs.count[2] ),
+ .ZN(_0499_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__nand3_1 _1145_ (.A1(\vga_clock.pulse_hrs.count[2] ),
+ .A2(\vga_clock.pulse_hrs.count[1] ),
+ .A3(\vga_clock.pulse_hrs.count[0] ),
+ .ZN(_0500_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__aoi22_1 _1146_ (.A1(\vga_clock.pulse_hrs.count[2] ),
+ .A2(_0495_),
+ .B1(_0493_),
+ .B2(_0500_),
+ .ZN(_0501_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__aoi211_1 _1147_ (.A1(_0499_),
+ .A2(_0497_),
+ .B(_0501_),
+ .C(_0435_),
+ .ZN(_0088_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_1 _1148_ (.A1(_0499_),
+ .A2(_0497_),
+ .ZN(_0502_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__aoi21_1 _1149_ (.A1(_0493_),
+ .A2(_0502_),
+ .B(\vga_clock.pulse_hrs.count[3] ),
+ .ZN(_0503_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_1 _1150_ (.A1(\vga_clock.pulse_hrs.count[3] ),
+ .A2(_0502_),
+ .ZN(_0504_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__aoi21_1 _1151_ (.A1(_0493_),
+ .A2(_0504_),
+ .B(_0495_),
+ .ZN(_0505_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__nor3_1 _1152_ (.A1(_0422_),
+ .A2(_0503_),
+ .A3(_0505_),
+ .ZN(_0089_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__and2_1 _1153_ (.A1(\vga_clock.pulse_hrs.count[3] ),
+ .A2(_0502_),
+ .Z(_0506_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__aoi21_1 _1154_ (.A1(_0493_),
+ .A2(_0506_),
+ .B(\vga_clock.pulse_hrs.count[4] ),
+ .ZN(_0507_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__aoi211_1 _1155_ (.A1(\vga_clock.pulse_hrs.count[4] ),
+ .A2(_0505_),
+ .B(_0507_),
+ .C(_0435_),
+ .ZN(_0090_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__or3_1 _1156_ (.A1(\vga_clock.pulse_min.count[3] ),
+ .A2(\vga_clock.pulse_min.count[1] ),
+ .A3(\vga_clock.pulse_min.count[0] ),
+ .Z(_0508_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__nor3_2 _1157_ (.A1(\vga_clock.pulse_min.count[4] ),
+ .A2(\vga_clock.pulse_min.count[2] ),
+ .A3(_0508_),
+ .ZN(_0509_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__oai31_1 _1158_ (.A1(\vga_clock.pulse_min.comp[4] ),
+ .A2(\vga_clock.pulse_min.comp[3] ),
+ .A3(\vga_clock.pulse_min.comp[2] ),
+ .B(_0509_),
+ .ZN(_0510_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_1 _1159_ (.A1(net3),
+ .A2(_0510_),
+ .ZN(_0511_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_1 _1160_ (.A1(_0469_),
+ .A2(_0511_),
+ .ZN(_0512_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__nand3_1 _1161_ (.A1(net3),
+ .A2(_0469_),
+ .A3(_0511_),
+ .ZN(_0513_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_1 _1162_ (.A1(\vga_clock.pulse_min.comp[0] ),
+ .A2(_0513_),
+ .ZN(_0514_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__oai211_1 _1163_ (.A1(\vga_clock.pulse_min.comp[0] ),
+ .A2(_0512_),
+ .B(_0514_),
+ .C(_0402_),
+ .ZN(_0091_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_1 _1164_ (.A1(\vga_clock.pulse_min.comp[0] ),
+ .A2(_0512_),
+ .B(\vga_clock.pulse_min.comp[1] ),
+ .ZN(_0515_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _1165_ (.I(\vga_clock.pulse_min.comp[1] ),
+ .ZN(_0516_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__inv_1 _1166_ (.I(\vga_clock.pulse_min.comp[0] ),
+ .ZN(_0517_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_1 _1167_ (.A1(_0516_),
+ .A2(_0517_),
+ .ZN(_0518_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__aoi21_1 _1168_ (.A1(net3),
+ .A2(_0518_),
+ .B(_0512_),
+ .ZN(_0519_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_1 _1169_ (.A1(_0410_),
+ .A2(_0519_),
+ .ZN(_0520_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_1 _1170_ (.A1(_0515_),
+ .A2(_0520_),
+ .ZN(_0092_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__nand3_1 _1171_ (.A1(\vga_clock.pulse_min.comp[2] ),
+ .A2(_0516_),
+ .A3(_0517_),
+ .ZN(_0521_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__oai22_1 _1172_ (.A1(\vga_clock.pulse_min.comp[2] ),
+ .A2(_0519_),
+ .B1(_0521_),
+ .B2(_0513_),
+ .ZN(_0522_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_1 _1173_ (.A1(_0402_),
+ .A2(_0522_),
+ .ZN(_0093_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _1174_ (.I(\vga_clock.pulse_min.comp[3] ),
+ .ZN(_0523_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__nor3_1 _1175_ (.A1(\vga_clock.pulse_min.comp[2] ),
+ .A2(_0512_),
+ .A3(_0518_),
+ .ZN(_0524_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_1 _1176_ (.A1(\vga_clock.pulse_min.comp[3] ),
+ .A2(\vga_clock.pulse_min.comp[2] ),
+ .B(net3),
+ .ZN(_0525_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__aoi21_1 _1177_ (.A1(_0519_),
+ .A2(_0525_),
+ .B(_0307_),
+ .ZN(_0526_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_1 _1178_ (.A1(_0523_),
+ .A2(_0524_),
+ .B(_0526_),
+ .ZN(_0094_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__and2_1 _1179_ (.A1(\vga_clock.pulse_min.comp[4] ),
+ .A2(_0526_),
+ .Z(_0527_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__clkbuf_1 _1180_ (.I(_0527_),
+ .Z(_0095_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _1181_ (.I(\vga_clock.pulse_min.comp[4] ),
+ .ZN(_0528_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _1182_ (.I(\vga_clock.pulse_min.count[1] ),
+ .ZN(_0529_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__xor2_1 _1183_ (.A1(\vga_clock.pulse_min.count[3] ),
+ .A2(\vga_clock.pulse_min.comp[3] ),
+ .Z(_0530_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__aoi221_2 _1184_ (.A1(\vga_clock.pulse_min.count[4] ),
+ .A2(_0528_),
+ .B1(\vga_clock.pulse_min.comp[1] ),
+ .B2(_0529_),
+ .C(_0530_),
+ .ZN(_0531_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__xnor2_1 _1185_ (.A1(\vga_clock.pulse_min.count[2] ),
+ .A2(\vga_clock.pulse_min.comp[2] ),
+ .ZN(_0532_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__oai221_2 _1186_ (.A1(\vga_clock.pulse_min.count[4] ),
+ .A2(_0528_),
+ .B1(_0517_),
+ .B2(\vga_clock.pulse_min.count[0] ),
+ .C(_0532_),
+ .ZN(_0533_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__aoi221_2 _1187_ (.A1(\vga_clock.pulse_min.count[1] ),
+ .A2(_0516_),
+ .B1(_0517_),
+ .B2(\vga_clock.pulse_min.count[0] ),
+ .C(_0533_),
+ .ZN(_0534_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_1 _1188_ (.A1(net3),
+ .A2(_0468_),
+ .ZN(_0535_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__aoi21_2 _1189_ (.A1(_0531_),
+ .A2(_0534_),
+ .B(_0535_),
+ .ZN(_0536_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_1 _1190_ (.A1(\vga_clock.pulse_min.count[0] ),
+ .A2(_0536_),
+ .B(_0407_),
+ .ZN(_0537_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__aoi21_1 _1191_ (.A1(\vga_clock.pulse_min.count[0] ),
+ .A2(_0469_),
+ .B(_0537_),
+ .ZN(_0096_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__xor2_1 _1192_ (.A1(\vga_clock.pulse_min.count[1] ),
+ .A2(\vga_clock.pulse_min.count[0] ),
+ .Z(_0538_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__aoi22_1 _1193_ (.A1(\vga_clock.pulse_min.count[1] ),
+ .A2(_0495_),
+ .B1(_0536_),
+ .B2(_0538_),
+ .ZN(_0539_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_1 _1194_ (.A1(_0416_),
+ .A2(_0539_),
+ .ZN(_0097_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__and3_1 _1195_ (.A1(\vga_clock.pulse_min.count[2] ),
+ .A2(\vga_clock.pulse_min.count[1] ),
+ .A3(\vga_clock.pulse_min.count[0] ),
+ .Z(_0540_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__aoi21_1 _1196_ (.A1(\vga_clock.pulse_min.count[1] ),
+ .A2(\vga_clock.pulse_min.count[0] ),
+ .B(\vga_clock.pulse_min.count[2] ),
+ .ZN(_0541_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_1 _1197_ (.A1(_0540_),
+ .A2(_0541_),
+ .ZN(_0542_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__aoi22_1 _1198_ (.A1(\vga_clock.pulse_min.count[2] ),
+ .A2(_0495_),
+ .B1(_0536_),
+ .B2(_0542_),
+ .ZN(_0543_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_1 _1199_ (.A1(_0416_),
+ .A2(_0543_),
+ .ZN(_0098_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__aoi21_1 _1200_ (.A1(_0536_),
+ .A2(_0540_),
+ .B(\vga_clock.pulse_min.count[3] ),
+ .ZN(_0544_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_1 _1201_ (.A1(\vga_clock.pulse_min.count[3] ),
+ .A2(_0540_),
+ .ZN(_0545_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__aoi21_1 _1202_ (.A1(_0536_),
+ .A2(_0545_),
+ .B(_0495_),
+ .ZN(_0546_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__nor3_1 _1203_ (.A1(_0422_),
+ .A2(_0544_),
+ .A3(_0546_),
+ .ZN(_0099_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__and2_1 _1204_ (.A1(\vga_clock.pulse_min.count[3] ),
+ .A2(_0540_),
+ .Z(_0547_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__aoi21_1 _1205_ (.A1(_0536_),
+ .A2(_0547_),
+ .B(\vga_clock.pulse_min.count[4] ),
+ .ZN(_0548_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__aoi211_1 _1206_ (.A1(\vga_clock.pulse_min.count[4] ),
+ .A2(_0546_),
+ .B(_0548_),
+ .C(_0435_),
+ .ZN(_0100_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__or2_1 _1207_ (.A1(\vga_clock.pulse_sec.count[1] ),
+ .A2(\vga_clock.pulse_sec.count[0] ),
+ .Z(_0549_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__nor4_2 _1208_ (.A1(\vga_clock.pulse_sec.count[4] ),
+ .A2(\vga_clock.pulse_sec.count[3] ),
+ .A3(\vga_clock.pulse_sec.count[2] ),
+ .A4(_0549_),
+ .ZN(_0550_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__oai31_1 _1209_ (.A1(\vga_clock.pulse_sec.comp[4] ),
+ .A2(\vga_clock.pulse_sec.comp[3] ),
+ .A3(\vga_clock.pulse_sec.comp[2] ),
+ .B(_0550_),
+ .ZN(_0551_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_1 _1210_ (.A1(net1),
+ .A2(_0551_),
+ .ZN(_0552_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_1 _1211_ (.A1(_0468_),
+ .A2(_0552_),
+ .ZN(_0553_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__nand3_1 _1212_ (.A1(net1),
+ .A2(_0469_),
+ .A3(_0552_),
+ .ZN(_0554_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_1 _1213_ (.A1(\vga_clock.pulse_sec.comp[0] ),
+ .A2(_0554_),
+ .ZN(_0555_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__oai211_1 _1214_ (.A1(\vga_clock.pulse_sec.comp[0] ),
+ .A2(_0553_),
+ .B(_0555_),
+ .C(_0402_),
+ .ZN(_0101_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_1 _1215_ (.A1(\vga_clock.pulse_sec.comp[0] ),
+ .A2(_0553_),
+ .B(\vga_clock.pulse_sec.comp[1] ),
+ .ZN(_0556_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__or2_1 _1216_ (.A1(\vga_clock.pulse_sec.comp[1] ),
+ .A2(\vga_clock.pulse_sec.comp[0] ),
+ .Z(_0557_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__aoi21_1 _1217_ (.A1(net1),
+ .A2(_0557_),
+ .B(_0553_),
+ .ZN(_0558_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_1 _1218_ (.A1(_0410_),
+ .A2(_0558_),
+ .ZN(_0559_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_1 _1219_ (.A1(_0556_),
+ .A2(_0559_),
+ .ZN(_0102_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_1 _1220_ (.A1(\vga_clock.pulse_sec.comp[1] ),
+ .A2(\vga_clock.pulse_sec.comp[0] ),
+ .ZN(_0560_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_1 _1221_ (.A1(\vga_clock.pulse_sec.comp[2] ),
+ .A2(_0560_),
+ .ZN(_0561_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__oai22_1 _1222_ (.A1(\vga_clock.pulse_sec.comp[2] ),
+ .A2(_0558_),
+ .B1(_0561_),
+ .B2(_0554_),
+ .ZN(_0562_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_1 _1223_ (.A1(_0402_),
+ .A2(_0562_),
+ .ZN(_0103_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _1224_ (.I(\vga_clock.pulse_sec.comp[3] ),
+ .ZN(_0563_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__nor3_1 _1225_ (.A1(\vga_clock.pulse_sec.comp[2] ),
+ .A2(_0553_),
+ .A3(_0557_),
+ .ZN(_0564_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_1 _1226_ (.A1(\vga_clock.pulse_sec.comp[3] ),
+ .A2(\vga_clock.pulse_sec.comp[2] ),
+ .B(net1),
+ .ZN(_0565_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__aoi21_1 _1227_ (.A1(_0558_),
+ .A2(_0565_),
+ .B(_0307_),
+ .ZN(_0566_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_1 _1228_ (.A1(_0563_),
+ .A2(_0564_),
+ .B(_0566_),
+ .ZN(_0104_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__and2_1 _1229_ (.A1(\vga_clock.pulse_sec.comp[4] ),
+ .A2(_0566_),
+ .Z(_0567_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__clkbuf_1 _1230_ (.I(_0567_),
+ .Z(_0105_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _1231_ (.I(\vga_clock.pulse_sec.count[2] ),
+ .ZN(_0568_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__aoi22_1 _1232_ (.A1(\vga_clock.pulse_sec.count[3] ),
+ .A2(_0563_),
+ .B1(\vga_clock.pulse_sec.comp[2] ),
+ .B2(_0568_),
+ .ZN(_0569_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _1233_ (.I(\vga_clock.pulse_sec.comp[1] ),
+ .ZN(_0570_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _1234_ (.I(\vga_clock.pulse_sec.count[0] ),
+ .ZN(_0571_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__aoi22_1 _1235_ (.A1(\vga_clock.pulse_sec.count[1] ),
+ .A2(_0570_),
+ .B1(\vga_clock.pulse_sec.comp[0] ),
+ .B2(_0571_),
+ .ZN(_0572_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__xor2_1 _1236_ (.A1(\vga_clock.pulse_sec.count[4] ),
+ .A2(\vga_clock.pulse_sec.comp[4] ),
+ .Z(_0573_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__oai22_1 _1237_ (.A1(\vga_clock.pulse_sec.count[3] ),
+ .A2(_0563_),
+ .B1(\vga_clock.pulse_sec.comp[0] ),
+ .B2(_0571_),
+ .ZN(_0574_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__oai22_1 _1238_ (.A1(_0568_),
+ .A2(\vga_clock.pulse_sec.comp[2] ),
+ .B1(_0570_),
+ .B2(\vga_clock.pulse_sec.count[1] ),
+ .ZN(_0575_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__nor3_1 _1239_ (.A1(_0573_),
+ .A2(_0574_),
+ .A3(_0575_),
+ .ZN(_0576_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__nand3_1 _1240_ (.A1(_0569_),
+ .A2(_0572_),
+ .A3(_0576_),
+ .ZN(_0577_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__and3_1 _1241_ (.A1(net1),
+ .A2(_0469_),
+ .A3(_0577_),
+ .Z(_0578_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_1 _1242_ (.A1(\vga_clock.pulse_sec.count[0] ),
+ .A2(_0578_),
+ .B(_0407_),
+ .ZN(_0579_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__aoi21_1 _1243_ (.A1(\vga_clock.pulse_sec.count[0] ),
+ .A2(_0469_),
+ .B(_0579_),
+ .ZN(_0106_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_1 _1244_ (.A1(\vga_clock.pulse_sec.count[1] ),
+ .A2(_0495_),
+ .ZN(_0580_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_1 _1245_ (.A1(\vga_clock.pulse_sec.count[1] ),
+ .A2(\vga_clock.pulse_sec.count[0] ),
+ .ZN(_0581_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__nand3_1 _1246_ (.A1(_0549_),
+ .A2(_0578_),
+ .A3(_0581_),
+ .ZN(_0582_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__aoi21_1 _1247_ (.A1(_0580_),
+ .A2(_0582_),
+ .B(_0422_),
+ .ZN(_0107_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__nand3_1 _1248_ (.A1(\vga_clock.pulse_sec.count[2] ),
+ .A2(\vga_clock.pulse_sec.count[1] ),
+ .A3(\vga_clock.pulse_sec.count[0] ),
+ .ZN(_0583_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__aoi22_1 _1249_ (.A1(\vga_clock.pulse_sec.count[2] ),
+ .A2(_0495_),
+ .B1(_0578_),
+ .B2(_0583_),
+ .ZN(_0584_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__aoi211_1 _1250_ (.A1(_0568_),
+ .A2(_0581_),
+ .B(_0584_),
+ .C(_0435_),
+ .ZN(_0108_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_1 _1251_ (.A1(_0568_),
+ .A2(_0581_),
+ .ZN(_0585_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__aoi21_1 _1252_ (.A1(_0578_),
+ .A2(_0585_),
+ .B(\vga_clock.pulse_sec.count[3] ),
+ .ZN(_0586_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_1 _1253_ (.A1(\vga_clock.pulse_sec.count[3] ),
+ .A2(_0585_),
+ .ZN(_0587_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__aoi21_1 _1254_ (.A1(_0578_),
+ .A2(_0587_),
+ .B(_0495_),
+ .ZN(_0588_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__nor3_1 _1255_ (.A1(_0422_),
+ .A2(_0586_),
+ .A3(_0588_),
+ .ZN(_0109_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__and2_1 _1256_ (.A1(\vga_clock.pulse_sec.count[3] ),
+ .A2(_0585_),
+ .Z(_0589_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__aoi21_1 _1257_ (.A1(_0578_),
+ .A2(_0589_),
+ .B(\vga_clock.pulse_sec.count[4] ),
+ .ZN(_0590_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__aoi211_1 _1258_ (.A1(\vga_clock.pulse_sec.count[4] ),
+ .A2(_0588_),
+ .B(_0590_),
+ .C(_0435_),
+ .ZN(_0110_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_2 _1259_ (.A1(\vga_clock.min_d[2] ),
+ .A2(\vga_clock.min_d[1] ),
+ .ZN(_0591_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_1 _1260_ (.A1(\vga_clock.hrs_u[1] ),
+ .A2(_0236_),
+ .ZN(_0592_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__nand3_1 _1261_ (.A1(_0264_),
+ .A2(\vga_clock.hrs_u[2] ),
+ .A3(_0592_),
+ .ZN(_0593_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__nor3_2 _1262_ (.A1(_0242_),
+ .A2(\vga_clock.hrs_d[0] ),
+ .A3(_0593_),
+ .ZN(_0594_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_1 _1263_ (.A1(\vga_clock.hrs_u[3] ),
+ .A2(\vga_clock.hrs_u[1] ),
+ .ZN(_0595_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__nor3_4 _1264_ (.A1(\vga_clock.hrs_u[2] ),
+ .A2(_0236_),
+ .A3(_0595_),
+ .ZN(_0596_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_2 _1265_ (.A1(_0594_),
+ .A2(_0596_),
+ .ZN(_0597_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__nand3_4 _1266_ (.A1(net2),
+ .A2(_0459_),
+ .A3(_0468_),
+ .ZN(_0598_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__oai211_4 _1267_ (.A1(\vga_clock.min_d[0] ),
+ .A2(_0591_),
+ .B(_0597_),
+ .C(_0598_),
+ .ZN(_0599_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_1 _1268_ (.A1(\vga_clock.min_d[0] ),
+ .A2(_0591_),
+ .ZN(_0600_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__aoi21_1 _1269_ (.A1(_0600_),
+ .A2(_0597_),
+ .B(_0236_),
+ .ZN(_0601_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__aoi221_1 _1270_ (.A1(_0236_),
+ .A2(_0599_),
+ .B1(_0601_),
+ .B2(_0598_),
+ .C(_0410_),
+ .ZN(_0111_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_1 _1271_ (.A1(_0236_),
+ .A2(_0599_),
+ .ZN(_0602_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_1 _1272_ (.A1(_0598_),
+ .A2(_0596_),
+ .ZN(_0603_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__nand3_1 _1273_ (.A1(\vga_clock.hrs_u[1] ),
+ .A2(_0236_),
+ .A3(_0599_),
+ .ZN(_0604_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__nand3_1 _1274_ (.A1(_0407_),
+ .A2(_0603_),
+ .A3(_0604_),
+ .ZN(_0605_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__aoi21_1 _1275_ (.A1(_0250_),
+ .A2(_0602_),
+ .B(_0605_),
+ .ZN(_0112_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__xor2_1 _1276_ (.A1(\vga_clock.hrs_u[2] ),
+ .A2(_0604_),
+ .Z(_0606_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__aoi211_1 _1277_ (.A1(_0598_),
+ .A2(_0594_),
+ .B(_0606_),
+ .C(_0435_),
+ .ZN(_0113_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__nand4_1 _1278_ (.A1(\vga_clock.hrs_u[2] ),
+ .A2(\vga_clock.hrs_u[1] ),
+ .A3(_0236_),
+ .A4(_0599_),
+ .ZN(_0607_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_1 _1279_ (.A1(\vga_clock.hrs_u[2] ),
+ .A2(_0236_),
+ .ZN(_0608_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_1 _1280_ (.A1(_0595_),
+ .A2(_0608_),
+ .B(_0603_),
+ .ZN(_0609_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__aoi221_1 _1281_ (.A1(_0264_),
+ .A2(_0607_),
+ .B1(_0609_),
+ .B2(_0599_),
+ .C(_0410_),
+ .ZN(_0114_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_1 _1282_ (.A1(\vga_clock.min_d[0] ),
+ .A2(_0591_),
+ .B(_0308_),
+ .ZN(_0610_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_1 _1283_ (.A1(\vga_clock.min_u[3] ),
+ .A2(\vga_clock.min_u[1] ),
+ .ZN(_0611_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__nor3_4 _1284_ (.A1(\vga_clock.min_u[2] ),
+ .A2(\vga_clock.min_u[0] ),
+ .A3(_0611_),
+ .ZN(_0612_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__xnor2_1 _1285_ (.A1(\vga_clock.min_d[0] ),
+ .A2(_0612_),
+ .ZN(_0613_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_1 _1286_ (.A1(_0610_),
+ .A2(_0613_),
+ .ZN(_0115_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__nand3_1 _1287_ (.A1(\vga_clock.min_d[1] ),
+ .A2(\vga_clock.min_d[0] ),
+ .A3(_0612_),
+ .ZN(_0614_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_1 _1288_ (.A1(\vga_clock.min_d[0] ),
+ .A2(_0612_),
+ .ZN(_0615_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__aoi21_1 _1289_ (.A1(_0248_),
+ .A2(_0615_),
+ .B(_0610_),
+ .ZN(_0616_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__and2_1 _1290_ (.A1(_0614_),
+ .A2(_0616_),
+ .Z(_0617_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__clkbuf_1 _1291_ (.I(_0617_),
+ .Z(_0116_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__xor2_1 _1292_ (.A1(\vga_clock.min_d[2] ),
+ .A2(_0614_),
+ .Z(_0618_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_1 _1293_ (.A1(_0610_),
+ .A2(_0618_),
+ .ZN(_0117_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_1 _1294_ (.A1(\vga_clock.sec_d[2] ),
+ .A2(\vga_clock.sec_d[1] ),
+ .ZN(_0619_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__nand3_2 _1295_ (.A1(net3),
+ .A2(_0468_),
+ .A3(_0509_),
+ .ZN(_0620_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_2 _1296_ (.A1(\vga_clock.sec_d[0] ),
+ .A2(_0619_),
+ .B(_0620_),
+ .ZN(_0621_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__nor3_1 _1297_ (.A1(\vga_clock.min_u[0] ),
+ .A2(_0612_),
+ .A3(_0621_),
+ .ZN(_0622_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__and2_1 _1298_ (.A1(\vga_clock.min_u[0] ),
+ .A2(_0621_),
+ .Z(_0623_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__and2_1 _1299_ (.A1(_0612_),
+ .A2(_0620_),
+ .Z(_0624_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__nor4_1 _1300_ (.A1(_0435_),
+ .A2(_0622_),
+ .A3(_0623_),
+ .A4(_0624_),
+ .ZN(_0625_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__clkbuf_1 _1301_ (.I(_0625_),
+ .Z(_0118_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_1 _1302_ (.A1(_0612_),
+ .A2(_0620_),
+ .ZN(_0626_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__aoi21_1 _1303_ (.A1(\vga_clock.min_u[1] ),
+ .A2(_0626_),
+ .B(_0623_),
+ .ZN(_0627_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__aoi211_1 _1304_ (.A1(\vga_clock.min_u[1] ),
+ .A2(_0623_),
+ .B(_0627_),
+ .C(_0435_),
+ .ZN(_0119_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__aoi21_1 _1305_ (.A1(\vga_clock.min_u[1] ),
+ .A2(_0623_),
+ .B(\vga_clock.min_u[2] ),
+ .ZN(_0628_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__and3_1 _1306_ (.A1(\vga_clock.min_u[2] ),
+ .A2(\vga_clock.min_u[1] ),
+ .A3(_0623_),
+ .Z(_0629_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__nor3_1 _1307_ (.A1(_0422_),
+ .A2(_0628_),
+ .A3(_0629_),
+ .ZN(_0120_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__xnor2_1 _1308_ (.A1(\vga_clock.min_u[3] ),
+ .A2(_0629_),
+ .ZN(_0630_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__nor3_1 _1309_ (.A1(_0422_),
+ .A2(_0624_),
+ .A3(_0630_),
+ .ZN(_0121_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_1 _1310_ (.A1(\vga_clock.sec_d[0] ),
+ .A2(_0619_),
+ .B(_0308_),
+ .ZN(_0631_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_1 _1311_ (.A1(\vga_clock.sec_u[3] ),
+ .A2(\vga_clock.sec_u[1] ),
+ .ZN(_0632_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__nor3_2 _1312_ (.A1(\vga_clock.sec_u[2] ),
+ .A2(\vga_clock.sec_u[0] ),
+ .A3(_0632_),
+ .ZN(_0633_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _1313_ (.I(_0633_),
+ .ZN(_0634_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__xor2_1 _1314_ (.A1(\vga_clock.sec_d[0] ),
+ .A2(_0634_),
+ .Z(_0635_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_1 _1315_ (.A1(_0631_),
+ .A2(_0635_),
+ .ZN(_0122_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__nand3_1 _1316_ (.A1(\vga_clock.sec_d[1] ),
+ .A2(\vga_clock.sec_d[0] ),
+ .A3(_0633_),
+ .ZN(_0636_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__aoi21_1 _1317_ (.A1(\vga_clock.sec_d[0] ),
+ .A2(_0633_),
+ .B(\vga_clock.sec_d[1] ),
+ .ZN(_0637_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_1 _1318_ (.A1(_0631_),
+ .A2(_0637_),
+ .ZN(_0638_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__and2_1 _1319_ (.A1(_0636_),
+ .A2(_0638_),
+ .Z(_0639_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__clkbuf_1 _1320_ (.I(_0639_),
+ .Z(_0123_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__xor2_1 _1321_ (.A1(\vga_clock.sec_d[2] ),
+ .A2(_0636_),
+ .Z(_0640_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_1 _1322_ (.A1(_0631_),
+ .A2(_0640_),
+ .ZN(_0124_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__nand3_1 _1323_ (.A1(net1),
+ .A2(_0468_),
+ .A3(_0550_),
+ .ZN(_0641_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__and2_1 _1324_ (.A1(_0347_),
+ .A2(_0641_),
+ .Z(_0642_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__xor2_1 _1325_ (.A1(\vga_clock.sec_u[0] ),
+ .A2(_0642_),
+ .Z(_0643_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_1 _1326_ (.A1(_0416_),
+ .A2(_0643_),
+ .ZN(_0125_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_1 _1327_ (.A1(\vga_clock.sec_u[0] ),
+ .A2(_0642_),
+ .ZN(_0644_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__aoi21_1 _1328_ (.A1(_0634_),
+ .A2(_0642_),
+ .B(_0644_),
+ .ZN(_0645_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_1 _1329_ (.A1(\vga_clock.sec_u[1] ),
+ .A2(_0645_),
+ .B(_0407_),
+ .ZN(_0646_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__aoi21_1 _1330_ (.A1(\vga_clock.sec_u[1] ),
+ .A2(_0645_),
+ .B(_0646_),
+ .ZN(_0126_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_1 _1331_ (.A1(_0634_),
+ .A2(_0642_),
+ .ZN(_0647_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__nand3_1 _1332_ (.A1(\vga_clock.sec_u[1] ),
+ .A2(\vga_clock.sec_u[0] ),
+ .A3(_0647_),
+ .ZN(_0648_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__xor2_1 _1333_ (.A1(\vga_clock.sec_u[2] ),
+ .A2(_0648_),
+ .Z(_0649_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_1 _1334_ (.A1(_0416_),
+ .A2(_0649_),
+ .ZN(_0127_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__nand3_1 _1335_ (.A1(\vga_clock.sec_u[2] ),
+ .A2(\vga_clock.sec_u[1] ),
+ .A3(\vga_clock.sec_u[0] ),
+ .ZN(_0650_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__xor2_1 _1336_ (.A1(\vga_clock.sec_u[3] ),
+ .A2(_0650_),
+ .Z(_0651_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__oai22_1 _1337_ (.A1(_0261_),
+ .A2(_0647_),
+ .B1(_0651_),
+ .B2(_0642_),
+ .ZN(_0652_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__and2_1 _1338_ (.A1(_0407_),
+ .A2(_0652_),
+ .Z(_0653_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__clkbuf_1 _1339_ (.I(_0653_),
+ .Z(_0128_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__aoi21_1 _1340_ (.A1(\vga_clock.color_offset[0] ),
+ .A2(_0621_),
+ .B(_0410_),
+ .ZN(_0654_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_1 _1341_ (.A1(\vga_clock.color_offset[0] ),
+ .A2(_0621_),
+ .B(_0654_),
+ .ZN(_0655_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _1342_ (.I(_0655_),
+ .ZN(_0129_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__aoi21_1 _1343_ (.A1(\vga_clock.color_offset[0] ),
+ .A2(_0621_),
+ .B(\vga_clock.color_offset[1] ),
+ .ZN(_0656_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__and3_1 _1344_ (.A1(\vga_clock.color_offset[1] ),
+ .A2(\vga_clock.color_offset[0] ),
+ .A3(_0621_),
+ .Z(_0657_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__nor3_1 _1345_ (.A1(_0422_),
+ .A2(_0656_),
+ .A3(_0657_),
+ .ZN(_0130_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__xor2_1 _1346_ (.A1(\vga_clock.color_offset[2] ),
+ .A2(_0657_),
+ .Z(_0658_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__and2_1 _1347_ (.A1(_0407_),
+ .A2(_0658_),
+ .Z(_0659_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__clkbuf_1 _1348_ (.I(_0659_),
+ .Z(_0131_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__or2_1 _1349_ (.A1(_0410_),
+ .A2(_0594_),
+ .Z(_0660_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__xnor2_1 _1350_ (.A1(\vga_clock.hrs_d[0] ),
+ .A2(_0596_),
+ .ZN(_0661_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_1 _1351_ (.A1(_0660_),
+ .A2(_0661_),
+ .ZN(_0132_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__nand2_1 _1352_ (.A1(\vga_clock.hrs_d[0] ),
+ .A2(_0596_),
+ .ZN(_0662_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__xor2_1 _1353_ (.A1(\vga_clock.hrs_d[1] ),
+ .A2(_0662_),
+ .Z(_0663_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_1 _1354_ (.A1(_0660_),
+ .A2(_0663_),
+ .ZN(_0133_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__nor4_1 _1355_ (.A1(\vga_clock.x_block_q[5] ),
+ .A2(\vga_clock.y_block_q[4] ),
+ .A3(\vga_clock.y_block_q[3] ),
+ .A4(\vga_clock.y_block_q[5] ),
+ .ZN(_0664_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__oai21_1 _1356_ (.A1(\vga_clock.y_block_q[1] ),
+ .A2(\vga_clock.y_block_q[0] ),
+ .B(\vga_clock.y_block_q[2] ),
+ .ZN(_0665_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__clkinv_1 _1357_ (.I(\vga_clock.col_index_q[0] ),
+ .ZN(_0666_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_1 _1358_ (.A1(\vga_clock.font_0.dout[2] ),
+ .A2(_0666_),
+ .ZN(_0667_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__nor2_1 _1359_ (.A1(\vga_clock.font_0.dout[3] ),
+ .A2(\vga_clock.col_index_q[0] ),
+ .ZN(_0668_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__nand3_1 _1360_ (.A1(_0666_),
+ .A2(\vga_clock.font_0.dout[1] ),
+ .A3(\vga_clock.col_index_q[1] ),
+ .ZN(_0669_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__oai31_1 _1361_ (.A1(\vga_clock.col_index_q[1] ),
+ .A2(_0667_),
+ .A3(_0668_),
+ .B(_0669_),
+ .ZN(_0670_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__and3_1 _1362_ (.A1(_0664_),
+ .A2(_0665_),
+ .A3(_0670_),
+ .Z(_0671_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__clkbuf_1 _1363_ (.I(_0671_),
+ .Z(_0134_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__dffq_1 _1364_ (.D(_0008_),
+ .CLK(clknet_4_10_0_wb_clk_i),
+ .Q(\vga_clock.color[3] ),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__dffq_1 _1365_ (.D(_0000_),
+ .CLK(clknet_4_11_0_wb_clk_i),
+ .Q(\vga_clock.color[4] ),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__dffq_1 _1366_ (.D(_0001_),
+ .CLK(clknet_4_2_0_wb_clk_i),
+ .Q(\vga_clock.color[5] ),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__dffq_1 _1367_ (.D(_0009_),
+ .CLK(clknet_4_9_0_wb_clk_i),
+ .Q(\vga_clock.digit_0.digit_index[5] ),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__dffq_1 _1368_ (.D(_0010_),
+ .CLK(clknet_4_0_0_wb_clk_i),
+ .Q(\vga_clock.color[1] ),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__dffq_1 _1369_ (.D(_0005_),
+ .CLK(clknet_4_10_0_wb_clk_i),
+ .Q(\vga_clock.font_0.dout[1] ),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__dffq_1 _1370_ (.D(_0006_),
+ .CLK(clknet_4_10_0_wb_clk_i),
+ .Q(\vga_clock.font_0.dout[2] ),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__dffq_1 _1371_ (.D(_0007_),
+ .CLK(clknet_4_10_0_wb_clk_i),
+ .Q(\vga_clock.font_0.dout[3] ),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__dffq_1 _1372_ (.D(_0011_),
+ .CLK(clknet_4_6_0_wb_clk_i),
+ .Q(\vga_clock.color[0] ),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__dffq_1 _1373_ (.D(_0012_),
+ .CLK(clknet_4_11_0_wb_clk_i),
+ .Q(\vga_clock.col_index[1] ),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__dffq_1 _1374_ (.D(_0013_),
+ .CLK(clknet_4_11_0_wb_clk_i),
+ .Q(\vga_clock.col_index[0] ),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__dffq_1 _1375_ (.D(_0014_),
+ .CLK(clknet_4_3_0_wb_clk_i),
+ .Q(\vga_clock.vga_0.hc[0] ),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__dffq_1 _1376_ (.D(_0015_),
+ .CLK(clknet_4_3_0_wb_clk_i),
+ .Q(\vga_clock.vga_0.hc[1] ),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__dffq_1 _1377_ (.D(_0016_),
+ .CLK(clknet_4_3_0_wb_clk_i),
+ .Q(\vga_clock.vga_0.hc[2] ),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__dffq_1 _1378_ (.D(_0017_),
+ .CLK(clknet_4_1_0_wb_clk_i),
+ .Q(\vga_clock.vga_0.hc[3] ),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__dffq_1 _1379_ (.D(_0018_),
+ .CLK(clknet_4_1_0_wb_clk_i),
+ .Q(\vga_clock.vga_0.hc[4] ),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__dffq_1 _1380_ (.D(_0019_),
+ .CLK(clknet_4_1_0_wb_clk_i),
+ .Q(\vga_clock.vga_0.hc[5] ),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__dffq_1 _1381_ (.D(_0020_),
+ .CLK(clknet_4_1_0_wb_clk_i),
+ .Q(\vga_clock.vga_0.hc[6] ),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__dffq_1 _1382_ (.D(_0021_),
+ .CLK(clknet_4_0_0_wb_clk_i),
+ .Q(\vga_clock.vga_0.hc[7] ),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__dffq_2 _1383_ (.D(_0022_),
+ .CLK(clknet_4_0_0_wb_clk_i),
+ .Q(\vga_clock.vga_0.hc[8] ),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__dffq_2 _1384_ (.D(_0023_),
+ .CLK(clknet_4_2_0_wb_clk_i),
+ .Q(\vga_clock.vga_0.hc[9] ),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__dffq_1 _1385_ (.D(_0024_),
+ .CLK(clknet_4_0_0_wb_clk_i),
+ .Q(\vga_clock.sec_counter[0] ),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__dffq_1 _1386_ (.D(_0025_),
+ .CLK(clknet_4_1_0_wb_clk_i),
+ .Q(\vga_clock.sec_counter[1] ),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__dffq_1 _1387_ (.D(_0026_),
+ .CLK(clknet_4_0_0_wb_clk_i),
+ .Q(\vga_clock.sec_counter[2] ),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__dffq_1 _1388_ (.D(_0027_),
+ .CLK(clknet_4_0_0_wb_clk_i),
+ .Q(\vga_clock.sec_counter[3] ),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__dffq_1 _1389_ (.D(_0028_),
+ .CLK(clknet_4_0_0_wb_clk_i),
+ .Q(\vga_clock.sec_counter[4] ),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__dffq_1 _1390_ (.D(_0029_),
+ .CLK(clknet_4_0_0_wb_clk_i),
+ .Q(\vga_clock.sec_counter[5] ),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__dffq_1 _1391_ (.D(_0030_),
+ .CLK(clknet_4_0_0_wb_clk_i),
+ .Q(\vga_clock.sec_counter[6] ),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__dffq_1 _1392_ (.D(_0031_),
+ .CLK(clknet_4_1_0_wb_clk_i),
+ .Q(\vga_clock.sec_counter[7] ),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__dffq_1 _1393_ (.D(_0032_),
+ .CLK(clknet_4_1_0_wb_clk_i),
+ .Q(\vga_clock.sec_counter[8] ),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__dffq_1 _1394_ (.D(_0033_),
+ .CLK(clknet_4_1_0_wb_clk_i),
+ .Q(\vga_clock.sec_counter[9] ),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__dffq_1 _1395_ (.D(_0034_),
+ .CLK(clknet_4_1_0_wb_clk_i),
+ .Q(\vga_clock.sec_counter[10] ),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__dffq_1 _1396_ (.D(_0035_),
+ .CLK(clknet_4_1_0_wb_clk_i),
+ .Q(\vga_clock.sec_counter[11] ),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__dffq_1 _1397_ (.D(_0036_),
+ .CLK(clknet_4_4_0_wb_clk_i),
+ .Q(\vga_clock.sec_counter[12] ),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__dffq_1 _1398_ (.D(_0037_),
+ .CLK(clknet_4_4_0_wb_clk_i),
+ .Q(\vga_clock.sec_counter[13] ),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__dffq_1 _1399_ (.D(_0038_),
+ .CLK(clknet_4_4_0_wb_clk_i),
+ .Q(\vga_clock.sec_counter[14] ),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__dffq_1 _1400_ (.D(_0039_),
+ .CLK(clknet_4_4_0_wb_clk_i),
+ .Q(\vga_clock.sec_counter[15] ),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__dffq_1 _1401_ (.D(_0040_),
+ .CLK(clknet_4_4_0_wb_clk_i),
+ .Q(\vga_clock.sec_counter[16] ),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__dffq_1 _1402_ (.D(_0041_),
+ .CLK(clknet_4_5_0_wb_clk_i),
+ .Q(\vga_clock.sec_counter[17] ),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__dffq_1 _1403_ (.D(_0042_),
+ .CLK(clknet_4_5_0_wb_clk_i),
+ .Q(\vga_clock.sec_counter[18] ),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__dffq_1 _1404_ (.D(_0043_),
+ .CLK(clknet_4_5_0_wb_clk_i),
+ .Q(\vga_clock.sec_counter[19] ),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__dffq_1 _1405_ (.D(_0044_),
+ .CLK(clknet_4_5_0_wb_clk_i),
+ .Q(\vga_clock.sec_counter[20] ),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__dffq_1 _1406_ (.D(_0045_),
+ .CLK(clknet_4_5_0_wb_clk_i),
+ .Q(\vga_clock.sec_counter[21] ),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__dffq_1 _1407_ (.D(_0046_),
+ .CLK(clknet_4_5_0_wb_clk_i),
+ .Q(\vga_clock.sec_counter[22] ),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__dffq_1 _1408_ (.D(_0047_),
+ .CLK(clknet_4_4_0_wb_clk_i),
+ .Q(\vga_clock.sec_counter[23] ),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__dffq_1 _1409_ (.D(_0048_),
+ .CLK(clknet_4_4_0_wb_clk_i),
+ .Q(\vga_clock.sec_counter[24] ),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__dffq_1 _1410_ (.D(_0049_),
+ .CLK(clknet_4_4_0_wb_clk_i),
+ .Q(\vga_clock.sec_counter[25] ),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__dffq_1 _1411_ (.D(_0050_),
+ .CLK(clknet_4_3_0_wb_clk_i),
+ .Q(\vga_clock.vga_0.x_px[0] ),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__dffq_1 _1412_ (.D(_0051_),
+ .CLK(clknet_4_3_0_wb_clk_i),
+ .Q(\vga_clock.vga_0.x_px[1] ),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__dffq_1 _1413_ (.D(_0052_),
+ .CLK(clknet_4_6_0_wb_clk_i),
+ .Q(\vga_clock.vga_0.x_px[2] ),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__dffq_1 _1414_ (.D(_0053_),
+ .CLK(clknet_4_3_0_wb_clk_i),
+ .Q(\vga_clock.vga_0.x_px[3] ),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__dffq_1 _1415_ (.D(_0054_),
+ .CLK(clknet_4_3_0_wb_clk_i),
+ .Q(\vga_clock.digit_0.x_block[0] ),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__dffq_1 _1416_ (.D(_0055_),
+ .CLK(clknet_4_9_0_wb_clk_i),
+ .Q(\vga_clock.digit_0.x_block[1] ),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__dffq_1 _1417_ (.D(_0056_),
+ .CLK(clknet_4_6_0_wb_clk_i),
+ .Q(\vga_clock.vga_0.x_px[6] ),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__dffq_1 _1418_ (.D(_0057_),
+ .CLK(clknet_4_6_0_wb_clk_i),
+ .Q(\vga_clock.vga_0.x_px[7] ),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__dffq_2 _1419_ (.D(_0058_),
+ .CLK(clknet_4_3_0_wb_clk_i),
+ .Q(\vga_clock.vga_0.x_px[8] ),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__dffq_2 _1420_ (.D(_0059_),
+ .CLK(clknet_4_6_0_wb_clk_i),
+ .Q(\vga_clock.vga_0.x_px[9] ),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__dffq_1 _1421_ (.D(_0060_),
+ .CLK(clknet_4_8_0_wb_clk_i),
+ .Q(\vga_clock.vga_0.y_px[0] ),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__dffq_1 _1422_ (.D(_0061_),
+ .CLK(clknet_4_8_0_wb_clk_i),
+ .Q(\vga_clock.vga_0.y_px[1] ),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__dffq_1 _1423_ (.D(_0062_),
+ .CLK(clknet_4_8_0_wb_clk_i),
+ .Q(\vga_clock.vga_0.y_px[2] ),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__dffq_1 _1424_ (.D(_0063_),
+ .CLK(clknet_4_8_0_wb_clk_i),
+ .Q(\vga_clock.vga_0.y_px[3] ),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__dffq_1 _1425_ (.D(_0064_),
+ .CLK(clknet_4_8_0_wb_clk_i),
+ .Q(\vga_clock.vga_0.y_px[4] ),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__dffq_1 _1426_ (.D(_0065_),
+ .CLK(clknet_4_8_0_wb_clk_i),
+ .Q(\vga_clock.vga_0.y_px[5] ),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__dffq_1 _1427_ (.D(_0066_),
+ .CLK(clknet_4_8_0_wb_clk_i),
+ .Q(\vga_clock.vga_0.y_px[6] ),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__dffq_1 _1428_ (.D(_0067_),
+ .CLK(clknet_4_8_0_wb_clk_i),
+ .Q(\vga_clock.vga_0.y_px[7] ),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__dffq_1 _1429_ (.D(_0068_),
+ .CLK(clknet_4_8_0_wb_clk_i),
+ .Q(\vga_clock.vga_0.y_px[8] ),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__dffq_1 _1430_ (.D(_0069_),
+ .CLK(clknet_4_8_0_wb_clk_i),
+ .Q(\vga_clock.vga_0.y_px[9] ),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__dffq_1 _1431_ (.D(_0070_),
+ .CLK(clknet_4_2_0_wb_clk_i),
+ .Q(\vga_clock.vga_0.vc[0] ),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__dffq_1 _1432_ (.D(_0071_),
+ .CLK(clknet_4_2_0_wb_clk_i),
+ .Q(\vga_clock.vga_0.vc[1] ),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__dffq_1 _1433_ (.D(_0072_),
+ .CLK(clknet_4_2_0_wb_clk_i),
+ .Q(\vga_clock.vga_0.vc[2] ),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__dffq_1 _1434_ (.D(_0073_),
+ .CLK(clknet_4_2_0_wb_clk_i),
+ .Q(\vga_clock.vga_0.vc[3] ),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__dffq_1 _1435_ (.D(_0074_),
+ .CLK(clknet_4_2_0_wb_clk_i),
+ .Q(\vga_clock.vga_0.vc[4] ),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__dffq_1 _1436_ (.D(_0075_),
+ .CLK(clknet_4_2_0_wb_clk_i),
+ .Q(\vga_clock.vga_0.vc[5] ),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__dffq_1 _1437_ (.D(_0076_),
+ .CLK(clknet_4_2_0_wb_clk_i),
+ .Q(\vga_clock.vga_0.vc[6] ),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__dffq_1 _1438_ (.D(_0077_),
+ .CLK(clknet_4_2_0_wb_clk_i),
+ .Q(\vga_clock.vga_0.vc[7] ),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__dffq_1 _1439_ (.D(_0078_),
+ .CLK(clknet_4_3_0_wb_clk_i),
+ .Q(\vga_clock.vga_0.vc[8] ),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__dffq_1 _1440_ (.D(_0079_),
+ .CLK(clknet_4_3_0_wb_clk_i),
+ .Q(\vga_clock.vga_0.vc[9] ),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__dffq_1 _1441_ (.D(_0080_),
+ .CLK(clknet_4_11_0_wb_clk_i),
+ .Q(\vga_clock.color[2] ),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__dffq_1 _1442_ (.D(_0081_),
+ .CLK(clknet_4_13_0_wb_clk_i),
+ .Q(\vga_clock.pulse_hrs.comp[0] ),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__dffq_1 _1443_ (.D(_0082_),
+ .CLK(clknet_4_15_0_wb_clk_i),
+ .Q(\vga_clock.pulse_hrs.comp[1] ),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__dffq_1 _1444_ (.D(_0083_),
+ .CLK(clknet_4_13_0_wb_clk_i),
+ .Q(\vga_clock.pulse_hrs.comp[2] ),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__dffq_1 _1445_ (.D(_0084_),
+ .CLK(clknet_4_13_0_wb_clk_i),
+ .Q(\vga_clock.pulse_hrs.comp[3] ),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__dffq_1 _1446_ (.D(_0085_),
+ .CLK(clknet_4_13_0_wb_clk_i),
+ .Q(\vga_clock.pulse_hrs.comp[4] ),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__dffq_1 _1447_ (.D(_0086_),
+ .CLK(clknet_4_12_0_wb_clk_i),
+ .Q(\vga_clock.pulse_hrs.count[0] ),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__dffq_1 _1448_ (.D(_0087_),
+ .CLK(clknet_4_15_0_wb_clk_i),
+ .Q(\vga_clock.pulse_hrs.count[1] ),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__dffq_2 _1449_ (.D(_0088_),
+ .CLK(clknet_4_15_0_wb_clk_i),
+ .Q(\vga_clock.pulse_hrs.count[2] ),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__dffq_1 _1450_ (.D(_0089_),
+ .CLK(clknet_4_13_0_wb_clk_i),
+ .Q(\vga_clock.pulse_hrs.count[3] ),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__dffq_1 _1451_ (.D(_0090_),
+ .CLK(clknet_4_13_0_wb_clk_i),
+ .Q(\vga_clock.pulse_hrs.count[4] ),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__dffq_1 _1452_ (.D(_0091_),
+ .CLK(clknet_4_15_0_wb_clk_i),
+ .Q(\vga_clock.pulse_min.comp[0] ),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__dffq_1 _1453_ (.D(_0092_),
+ .CLK(clknet_4_15_0_wb_clk_i),
+ .Q(\vga_clock.pulse_min.comp[1] ),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__dffq_1 _1454_ (.D(_0093_),
+ .CLK(clknet_4_15_0_wb_clk_i),
+ .Q(\vga_clock.pulse_min.comp[2] ),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__dffq_1 _1455_ (.D(_0094_),
+ .CLK(clknet_4_15_0_wb_clk_i),
+ .Q(\vga_clock.pulse_min.comp[3] ),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__dffq_1 _1456_ (.D(_0095_),
+ .CLK(clknet_4_15_0_wb_clk_i),
+ .Q(\vga_clock.pulse_min.comp[4] ),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__dffq_2 _1457_ (.D(_0096_),
+ .CLK(clknet_4_15_0_wb_clk_i),
+ .Q(\vga_clock.pulse_min.count[0] ),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__dffq_2 _1458_ (.D(_0097_),
+ .CLK(clknet_4_15_0_wb_clk_i),
+ .Q(\vga_clock.pulse_min.count[1] ),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__dffq_1 _1459_ (.D(_0098_),
+ .CLK(clknet_4_15_0_wb_clk_i),
+ .Q(\vga_clock.pulse_min.count[2] ),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__dffq_1 _1460_ (.D(_0099_),
+ .CLK(clknet_4_15_0_wb_clk_i),
+ .Q(\vga_clock.pulse_min.count[3] ),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__dffq_1 _1461_ (.D(_0100_),
+ .CLK(clknet_4_15_0_wb_clk_i),
+ .Q(\vga_clock.pulse_min.count[4] ),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__dffq_1 _1462_ (.D(\vga_clock.digit_0.number[0] ),
+ .CLK(clknet_4_9_0_wb_clk_i),
+ .Q(\vga_clock.digit_0.digit_index[0] ),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__dffq_1 _1463_ (.D(\vga_clock.digit_0.number[1] ),
+ .CLK(clknet_4_9_0_wb_clk_i),
+ .Q(\vga_clock.digit_0.digit_index[1] ),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__dffq_1 _1464_ (.D(_0002_),
+ .CLK(clknet_4_8_0_wb_clk_i),
+ .Q(\vga_clock.digit_0.digit_index[2] ),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__dffq_1 _1465_ (.D(_0003_),
+ .CLK(clknet_4_9_0_wb_clk_i),
+ .Q(\vga_clock.digit_0.digit_index[3] ),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__dffq_1 _1466_ (.D(_0004_),
+ .CLK(clknet_4_9_0_wb_clk_i),
+ .Q(\vga_clock.digit_0.digit_index[4] ),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__dffq_1 _1467_ (.D(_0101_),
+ .CLK(clknet_4_11_0_wb_clk_i),
+ .Q(\vga_clock.pulse_sec.comp[0] ),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__dffq_1 _1468_ (.D(_0102_),
+ .CLK(clknet_4_14_0_wb_clk_i),
+ .Q(\vga_clock.pulse_sec.comp[1] ),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__dffq_1 _1469_ (.D(_0103_),
+ .CLK(clknet_4_11_0_wb_clk_i),
+ .Q(\vga_clock.pulse_sec.comp[2] ),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__dffq_1 _1470_ (.D(_0104_),
+ .CLK(clknet_4_14_0_wb_clk_i),
+ .Q(\vga_clock.pulse_sec.comp[3] ),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__dffq_1 _1471_ (.D(_0105_),
+ .CLK(clknet_4_14_0_wb_clk_i),
+ .Q(\vga_clock.pulse_sec.comp[4] ),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__dffq_1 _1472_ (.D(_0106_),
+ .CLK(clknet_4_12_0_wb_clk_i),
+ .Q(\vga_clock.pulse_sec.count[0] ),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__dffq_1 _1473_ (.D(_0107_),
+ .CLK(clknet_4_14_0_wb_clk_i),
+ .Q(\vga_clock.pulse_sec.count[1] ),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__dffq_1 _1474_ (.D(_0108_),
+ .CLK(clknet_4_14_0_wb_clk_i),
+ .Q(\vga_clock.pulse_sec.count[2] ),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__dffq_1 _1475_ (.D(_0109_),
+ .CLK(clknet_4_14_0_wb_clk_i),
+ .Q(\vga_clock.pulse_sec.count[3] ),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__dffq_1 _1476_ (.D(_0110_),
+ .CLK(clknet_4_14_0_wb_clk_i),
+ .Q(\vga_clock.pulse_sec.count[4] ),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__dffq_1 _1477_ (.D(_0111_),
+ .CLK(clknet_4_13_0_wb_clk_i),
+ .Q(\vga_clock.hrs_u[0] ),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__dffq_1 _1478_ (.D(_0112_),
+ .CLK(clknet_4_12_0_wb_clk_i),
+ .Q(\vga_clock.hrs_u[1] ),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__dffq_2 _1479_ (.D(_0113_),
+ .CLK(clknet_4_14_0_wb_clk_i),
+ .Q(\vga_clock.hrs_u[2] ),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__dffq_1 _1480_ (.D(_0114_),
+ .CLK(clknet_4_12_0_wb_clk_i),
+ .Q(\vga_clock.hrs_u[3] ),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__dffq_2 _1481_ (.D(_0115_),
+ .CLK(clknet_4_12_0_wb_clk_i),
+ .Q(\vga_clock.min_d[0] ),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__dffq_1 _1482_ (.D(_0116_),
+ .CLK(clknet_4_13_0_wb_clk_i),
+ .Q(\vga_clock.min_d[1] ),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__dffq_1 _1483_ (.D(_0117_),
+ .CLK(clknet_4_12_0_wb_clk_i),
+ .Q(\vga_clock.min_d[2] ),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__dffq_1 _1484_ (.D(_0118_),
+ .CLK(clknet_4_7_0_wb_clk_i),
+ .Q(\vga_clock.min_u[0] ),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__dffq_1 _1485_ (.D(_0119_),
+ .CLK(clknet_4_13_0_wb_clk_i),
+ .Q(\vga_clock.min_u[1] ),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__dffq_1 _1486_ (.D(_0120_),
+ .CLK(clknet_4_7_0_wb_clk_i),
+ .Q(\vga_clock.min_u[2] ),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__dffq_1 _1487_ (.D(_0121_),
+ .CLK(clknet_4_7_0_wb_clk_i),
+ .Q(\vga_clock.min_u[3] ),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__dffq_1 _1488_ (.D(_0122_),
+ .CLK(clknet_4_7_0_wb_clk_i),
+ .Q(\vga_clock.sec_d[0] ),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__dffq_1 _1489_ (.D(_0123_),
+ .CLK(clknet_4_7_0_wb_clk_i),
+ .Q(\vga_clock.sec_d[1] ),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__dffq_1 _1490_ (.D(_0124_),
+ .CLK(clknet_4_7_0_wb_clk_i),
+ .Q(\vga_clock.sec_d[2] ),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__dffq_1 _1491_ (.D(_0125_),
+ .CLK(clknet_4_7_0_wb_clk_i),
+ .Q(\vga_clock.sec_u[0] ),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__dffq_1 _1492_ (.D(_0126_),
+ .CLK(clknet_4_5_0_wb_clk_i),
+ .Q(\vga_clock.sec_u[1] ),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__dffq_1 _1493_ (.D(_0127_),
+ .CLK(clknet_4_7_0_wb_clk_i),
+ .Q(\vga_clock.sec_u[2] ),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__dffq_1 _1494_ (.D(_0128_),
+ .CLK(clknet_4_5_0_wb_clk_i),
+ .Q(\vga_clock.sec_u[3] ),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__dffq_1 _1495_ (.D(_0129_),
+ .CLK(clknet_4_6_0_wb_clk_i),
+ .Q(\vga_clock.color_offset[0] ),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__dffq_1 _1496_ (.D(_0130_),
+ .CLK(clknet_4_6_0_wb_clk_i),
+ .Q(\vga_clock.color_offset[1] ),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__dffq_1 _1497_ (.D(_0131_),
+ .CLK(clknet_4_7_0_wb_clk_i),
+ .Q(\vga_clock.color_offset[2] ),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__dffq_1 _1498_ (.D(\vga_clock.col_index[0] ),
+ .CLK(clknet_4_11_0_wb_clk_i),
+ .Q(\vga_clock.col_index_q[0] ),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__dffq_1 _1499_ (.D(\vga_clock.col_index[1] ),
+ .CLK(clknet_4_11_0_wb_clk_i),
+ .Q(\vga_clock.col_index_q[1] ),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__dffq_1 _1500_ (.D(\vga_clock.y_block[0] ),
+ .CLK(clknet_4_10_0_wb_clk_i),
+ .Q(\vga_clock.y_block_q[0] ),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__dffq_1 _1501_ (.D(\vga_clock.y_block[1] ),
+ .CLK(clknet_4_8_0_wb_clk_i),
+ .Q(\vga_clock.y_block_q[1] ),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__dffq_1 _1502_ (.D(\vga_clock.y_block[2] ),
+ .CLK(clknet_4_10_0_wb_clk_i),
+ .Q(\vga_clock.y_block_q[2] ),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__dffq_1 _1503_ (.D(\vga_clock.y_block[3] ),
+ .CLK(clknet_4_10_0_wb_clk_i),
+ .Q(\vga_clock.y_block_q[3] ),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__dffq_1 _1504_ (.D(\vga_clock.y_block[4] ),
+ .CLK(clknet_4_9_0_wb_clk_i),
+ .Q(\vga_clock.y_block_q[4] ),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__dffq_1 _1505_ (.D(\vga_clock.y_block[5] ),
+ .CLK(clknet_4_10_0_wb_clk_i),
+ .Q(\vga_clock.y_block_q[5] ),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__dffq_1 _1506_ (.D(\vga_clock.digit_0.x_block[0] ),
+ .CLK(clknet_4_11_0_wb_clk_i),
+ .Q(\vga_clock.x_block_q[0] ),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__dffq_1 _1507_ (.D(\vga_clock.digit_0.x_block[1] ),
+ .CLK(clknet_4_11_0_wb_clk_i),
+ .Q(\vga_clock.x_block_q[1] ),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__dffq_1 _1508_ (.D(\vga_clock.digit_0.char[0] ),
+ .CLK(clknet_4_12_0_wb_clk_i),
+ .Q(\vga_clock.x_block_q[2] ),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__dffq_1 _1509_ (.D(\vga_clock.digit_0.char[1] ),
+ .CLK(clknet_4_6_0_wb_clk_i),
+ .Q(\vga_clock.x_block_q[3] ),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__dffq_1 _1510_ (.D(\vga_clock.digit_0.char[2] ),
+ .CLK(clknet_4_6_0_wb_clk_i),
+ .Q(\vga_clock.x_block_q[4] ),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__dffq_1 _1511_ (.D(\vga_clock.digit_0.char[3] ),
+ .CLK(clknet_4_11_0_wb_clk_i),
+ .Q(\vga_clock.x_block_q[5] ),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__dffq_1 _1512_ (.D(_0132_),
+ .CLK(clknet_4_9_0_wb_clk_i),
+ .Q(\vga_clock.hrs_d[0] ),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__dffq_1 _1513_ (.D(_0133_),
+ .CLK(clknet_4_14_0_wb_clk_i),
+ .Q(\vga_clock.hrs_d[1] ),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__dffq_1 _1514_ (.D(_0134_),
+ .CLK(clknet_4_8_0_wb_clk_i),
+ .Q(\vga_clock.draw ),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__tiel wrapped_vga_clock_14 (.ZN(net14),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__tiel wrapped_vga_clock_15 (.ZN(net15),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__tiel wrapped_vga_clock_16 (.ZN(net16),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__tiel wrapped_vga_clock_17 (.ZN(net17),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__tiel wrapped_vga_clock_18 (.ZN(net18),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__tiel wrapped_vga_clock_19 (.ZN(net19),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__tiel wrapped_vga_clock_20 (.ZN(net20),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__tiel wrapped_vga_clock_21 (.ZN(net21),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__tiel wrapped_vga_clock_22 (.ZN(net22),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__tiel wrapped_vga_clock_23 (.ZN(net23),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__tiel wrapped_vga_clock_24 (.ZN(net24),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__tiel wrapped_vga_clock_25 (.ZN(net25),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__tiel wrapped_vga_clock_26 (.ZN(net26),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__tiel wrapped_vga_clock_27 (.ZN(net27),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__tiel wrapped_vga_clock_28 (.ZN(net28),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__tiel wrapped_vga_clock_29 (.ZN(net29),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__tiel wrapped_vga_clock_30 (.ZN(net30),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__tiel wrapped_vga_clock_31 (.ZN(net31),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__tiel wrapped_vga_clock_32 (.ZN(net32),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__tiel wrapped_vga_clock_33 (.ZN(net33),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__tiel wrapped_vga_clock_34 (.ZN(net34),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__tiel wrapped_vga_clock_35 (.ZN(net35),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__tiel wrapped_vga_clock_36 (.ZN(net36),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__tiel wrapped_vga_clock_37 (.ZN(net37),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__tiel wrapped_vga_clock_38 (.ZN(net38),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__tiel wrapped_vga_clock_39 (.ZN(net39),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__tiel wrapped_vga_clock_40 (.ZN(net40),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__tiel wrapped_vga_clock_41 (.ZN(net41),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__tiel wrapped_vga_clock_42 (.ZN(net42),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__tiel wrapped_vga_clock_43 (.ZN(net43),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__tiel wrapped_vga_clock_44 (.ZN(net44),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__tiel wrapped_vga_clock_45 (.ZN(net45),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__tiel wrapped_vga_clock_46 (.ZN(net46),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__tiel wrapped_vga_clock_47 (.ZN(net47),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__tiel wrapped_vga_clock_48 (.ZN(net48),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__tiel wrapped_vga_clock_49 (.ZN(net49),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__tiel wrapped_vga_clock_50 (.ZN(net50),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__tiel wrapped_vga_clock_51 (.ZN(net51),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__tiel wrapped_vga_clock_52 (.ZN(net52),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__tiel wrapped_vga_clock_53 (.ZN(net53),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__tiel wrapped_vga_clock_54 (.ZN(net54),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__tiel wrapped_vga_clock_55 (.ZN(net55),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__tiel wrapped_vga_clock_56 (.ZN(net56),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__tiel wrapped_vga_clock_57 (.ZN(net57),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__tiel wrapped_vga_clock_58 (.ZN(net58),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__tiel wrapped_vga_clock_59 (.ZN(net59),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__tiel wrapped_vga_clock_60 (.ZN(net60),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__tiel wrapped_vga_clock_61 (.ZN(net61),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__tiel wrapped_vga_clock_62 (.ZN(net62),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__tiel wrapped_vga_clock_63 (.ZN(net63),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__tiel wrapped_vga_clock_64 (.ZN(net64),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__tiel wrapped_vga_clock_65 (.ZN(net65),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__tiel wrapped_vga_clock_66 (.ZN(net66),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__tiel wrapped_vga_clock_67 (.ZN(net67),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__tiel wrapped_vga_clock_68 (.ZN(net68),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__tiel wrapped_vga_clock_69 (.ZN(net69),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__tiel wrapped_vga_clock_70 (.ZN(net70),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__tiel wrapped_vga_clock_71 (.ZN(net71),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__tiel wrapped_vga_clock_72 (.ZN(net72),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__tiel wrapped_vga_clock_73 (.ZN(net73),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__tiel wrapped_vga_clock_74 (.ZN(net74),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__tiel wrapped_vga_clock_75 (.ZN(net75),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__tiel wrapped_vga_clock_76 (.ZN(net76),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__tiel wrapped_vga_clock_77 (.ZN(net77),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__tiel wrapped_vga_clock_78 (.ZN(net78),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__tiel wrapped_vga_clock_79 (.ZN(net79),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__tiel wrapped_vga_clock_80 (.ZN(net80),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__clkbuf_16 clkbuf_0_wb_clk_i (.I(wb_clk_i),
+ .Z(clknet_0_wb_clk_i),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__endcap PHY_0 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__endcap PHY_1 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__endcap PHY_2 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__endcap PHY_3 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__endcap PHY_4 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__endcap PHY_5 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__endcap PHY_6 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__endcap PHY_7 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__endcap PHY_8 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__endcap PHY_9 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__endcap PHY_10 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__endcap PHY_11 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__endcap PHY_12 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__endcap PHY_13 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__endcap PHY_14 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__endcap PHY_15 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__endcap PHY_16 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__endcap PHY_17 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__endcap PHY_18 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__endcap PHY_19 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__endcap PHY_20 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__endcap PHY_21 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__endcap PHY_22 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__endcap PHY_23 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__endcap PHY_24 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__endcap PHY_25 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__endcap PHY_26 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__endcap PHY_27 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__endcap PHY_28 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__endcap PHY_29 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__endcap PHY_30 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__endcap PHY_31 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__endcap PHY_32 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__endcap PHY_33 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__endcap PHY_34 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__endcap PHY_35 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__endcap PHY_36 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__endcap PHY_37 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__endcap PHY_38 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__endcap PHY_39 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__endcap PHY_40 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__endcap PHY_41 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__endcap PHY_42 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__endcap PHY_43 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__endcap PHY_44 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__endcap PHY_45 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__endcap PHY_46 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__endcap PHY_47 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__endcap PHY_48 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__endcap PHY_49 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__endcap PHY_50 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__endcap PHY_51 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__endcap PHY_52 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__endcap PHY_53 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__endcap PHY_54 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__endcap PHY_55 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__endcap PHY_56 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__endcap PHY_57 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__endcap PHY_58 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__endcap PHY_59 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__endcap PHY_60 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__endcap PHY_61 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__endcap PHY_62 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__endcap PHY_63 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__endcap PHY_64 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__endcap PHY_65 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__endcap PHY_66 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__endcap PHY_67 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__endcap PHY_68 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__endcap PHY_69 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__endcap PHY_70 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__endcap PHY_71 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__endcap PHY_72 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__endcap PHY_73 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__endcap PHY_74 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__endcap PHY_75 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__endcap PHY_76 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__endcap PHY_77 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__endcap PHY_78 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__endcap PHY_79 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__endcap PHY_80 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__endcap PHY_81 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__endcap PHY_82 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__endcap PHY_83 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__endcap PHY_84 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__endcap PHY_85 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__endcap PHY_86 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__endcap PHY_87 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__endcap PHY_88 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__endcap PHY_89 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__endcap PHY_90 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__endcap PHY_91 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__endcap PHY_92 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__endcap PHY_93 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__endcap PHY_94 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__endcap PHY_95 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__endcap PHY_96 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__endcap PHY_97 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__endcap PHY_98 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__endcap PHY_99 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__endcap PHY_100 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__endcap PHY_101 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__endcap PHY_102 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__endcap PHY_103 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__endcap PHY_104 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__endcap PHY_105 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__endcap PHY_106 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__endcap PHY_107 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__endcap PHY_108 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__endcap PHY_109 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__endcap PHY_110 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__endcap PHY_111 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__endcap PHY_112 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__endcap PHY_113 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__endcap PHY_114 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__endcap PHY_115 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__endcap PHY_116 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__endcap PHY_117 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__endcap PHY_118 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__endcap PHY_119 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__endcap PHY_120 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__endcap PHY_121 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__endcap PHY_122 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__endcap PHY_123 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__endcap PHY_124 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__endcap PHY_125 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__endcap PHY_126 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__endcap PHY_127 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__endcap PHY_128 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__endcap PHY_129 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__endcap PHY_130 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__endcap PHY_131 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__endcap PHY_132 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__endcap PHY_133 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__endcap PHY_134 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__endcap PHY_135 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_136 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_137 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_138 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_139 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_140 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_141 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_142 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_143 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_144 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_145 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_146 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_147 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_148 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_149 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_150 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_151 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_152 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_153 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_154 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_155 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_156 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_157 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_158 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_159 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_160 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_161 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_162 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_163 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_164 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_165 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_166 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_167 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_168 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_169 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_170 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_171 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_172 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_173 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_174 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_175 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_176 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_177 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_178 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_179 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_180 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_181 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_182 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_183 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_184 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_185 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_186 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_187 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_188 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_189 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_190 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_191 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_192 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_193 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_194 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_195 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_196 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_197 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_198 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_199 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_200 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_201 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_202 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_203 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_204 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_205 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_206 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_207 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_208 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_209 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_210 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_211 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_212 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_213 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_214 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_215 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_216 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_217 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_218 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_219 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_220 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_221 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_222 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_223 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_224 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_225 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_226 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_227 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_228 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_229 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_230 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_231 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_232 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_233 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_234 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_235 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_236 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_237 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_238 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_239 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_240 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_241 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_242 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_243 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_244 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_245 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_246 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_247 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_248 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_249 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_250 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_251 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_252 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_253 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_254 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_255 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_256 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_257 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_258 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_259 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_260 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_261 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_262 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_263 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_264 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_265 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_266 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_267 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_268 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_269 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_270 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_271 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_272 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_273 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_274 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_275 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_276 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_277 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_278 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_279 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_280 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_281 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_282 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_283 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_284 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_285 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_286 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_287 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_288 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_289 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_290 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_291 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_292 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_293 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_294 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_295 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_296 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_297 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_298 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_299 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_300 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_301 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_302 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_303 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_304 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_305 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_306 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_307 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_308 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_309 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_310 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_311 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_312 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_313 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_314 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_315 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_316 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_317 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_318 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_319 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_320 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_321 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_322 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_323 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_324 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_325 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_326 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_327 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_328 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_329 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_330 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_331 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_332 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_333 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_334 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_335 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_336 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_337 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_338 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_339 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_340 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_341 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_342 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_343 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_344 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_345 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_346 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_347 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_348 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_349 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_350 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_351 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_352 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_353 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_354 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_355 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_356 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_357 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_358 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_359 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_360 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_361 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_362 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_363 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_364 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_365 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_366 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_367 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_368 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_369 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_370 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_371 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_372 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_373 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_374 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_375 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_376 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_377 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_378 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_379 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_380 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_381 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_382 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_383 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_384 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_385 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_386 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_387 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_388 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_389 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_390 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_391 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_392 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_393 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_394 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_395 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_396 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_397 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_398 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_399 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_400 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_401 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_402 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_403 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_404 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_405 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_406 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_407 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_408 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_409 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_410 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_411 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_412 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_413 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_414 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_415 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_416 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_417 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_418 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_419 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_420 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_421 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_422 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_423 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_424 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_425 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_426 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_427 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_428 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_429 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_430 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_431 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_432 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_433 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_434 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_435 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_436 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_437 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_438 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_439 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_440 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_441 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_442 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_443 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_444 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_445 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_446 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_447 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_448 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_449 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_450 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_451 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_452 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_453 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_454 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_455 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_456 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_457 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_458 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_459 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_460 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_461 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_462 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_463 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_464 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_465 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_466 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_467 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_468 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_469 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_470 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_471 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_472 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_473 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_474 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_475 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_476 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_477 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_478 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_479 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_480 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_481 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_482 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_483 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_484 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_485 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_486 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_487 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_488 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_489 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_490 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_491 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_492 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_493 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_494 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_495 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_496 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_497 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_498 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_499 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_500 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_501 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_502 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_503 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_504 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_505 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_506 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_507 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_508 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_509 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_510 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_511 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_512 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_513 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_514 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_515 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_516 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_517 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_518 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_519 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_520 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_521 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_522 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_523 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_524 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_525 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_526 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_527 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_528 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_529 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_530 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_531 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_532 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_533 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_534 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_535 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_536 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_537 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_538 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_539 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_540 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_541 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_542 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_543 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_544 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_545 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_546 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_547 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_548 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_549 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_550 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_551 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_552 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_553 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_554 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_555 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_556 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_557 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_558 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_559 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_560 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_561 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_562 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_563 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_564 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_565 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_566 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_567 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_568 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_569 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_570 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_571 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_572 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_573 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_574 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_575 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_576 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_577 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_578 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_579 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_580 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_581 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_582 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_583 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_584 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_585 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_586 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_587 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_588 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_589 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_590 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_591 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_592 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_593 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_594 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_595 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_596 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_597 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_598 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_599 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_600 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_601 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_602 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_603 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_604 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_605 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_606 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_607 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_608 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_609 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_610 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_611 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_612 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_613 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_614 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_615 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_616 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_617 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_618 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_619 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_620 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_621 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_622 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_623 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_624 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__filltie TAP_625 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__buf_1 input1 (.I(io_in[10]),
+ .Z(net1),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__buf_2 input2 (.I(io_in[8]),
+ .Z(net2),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__clkbuf_2 input3 (.I(io_in[9]),
+ .Z(net3),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__clkbuf_1 input4 (.I(wb_rst_i),
+ .Z(net4),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__clkbuf_4 output5 (.I(net5),
+ .Z(io_out[11]),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__clkbuf_4 output6 (.I(net6),
+ .Z(io_out[12]),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__clkbuf_4 output7 (.I(net7),
+ .Z(io_out[13]),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__clkbuf_4 output8 (.I(net8),
+ .Z(io_out[14]),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__clkbuf_4 output9 (.I(net9),
+ .Z(io_out[15]),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__clkbuf_4 output10 (.I(net10),
+ .Z(io_out[16]),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__clkbuf_4 output11 (.I(net11),
+ .Z(io_out[17]),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__clkbuf_4 output12 (.I(net12),
+ .Z(io_out[18]),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__tiel wrapped_vga_clock_13 (.ZN(net13),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__clkbuf_8 clkbuf_4_0_0_wb_clk_i (.I(clknet_0_wb_clk_i),
+ .Z(clknet_4_0_0_wb_clk_i),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__clkbuf_8 clkbuf_4_1_0_wb_clk_i (.I(clknet_0_wb_clk_i),
+ .Z(clknet_4_1_0_wb_clk_i),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__clkbuf_8 clkbuf_4_2_0_wb_clk_i (.I(clknet_0_wb_clk_i),
+ .Z(clknet_4_2_0_wb_clk_i),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__clkbuf_8 clkbuf_4_3_0_wb_clk_i (.I(clknet_0_wb_clk_i),
+ .Z(clknet_4_3_0_wb_clk_i),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__clkbuf_8 clkbuf_4_4_0_wb_clk_i (.I(clknet_0_wb_clk_i),
+ .Z(clknet_4_4_0_wb_clk_i),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__clkbuf_8 clkbuf_4_5_0_wb_clk_i (.I(clknet_0_wb_clk_i),
+ .Z(clknet_4_5_0_wb_clk_i),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__clkbuf_8 clkbuf_4_6_0_wb_clk_i (.I(clknet_0_wb_clk_i),
+ .Z(clknet_4_6_0_wb_clk_i),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__clkbuf_8 clkbuf_4_7_0_wb_clk_i (.I(clknet_0_wb_clk_i),
+ .Z(clknet_4_7_0_wb_clk_i),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__clkbuf_8 clkbuf_4_8_0_wb_clk_i (.I(clknet_0_wb_clk_i),
+ .Z(clknet_4_8_0_wb_clk_i),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__clkbuf_8 clkbuf_4_9_0_wb_clk_i (.I(clknet_0_wb_clk_i),
+ .Z(clknet_4_9_0_wb_clk_i),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__clkbuf_8 clkbuf_4_10_0_wb_clk_i (.I(clknet_0_wb_clk_i),
+ .Z(clknet_4_10_0_wb_clk_i),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__clkbuf_8 clkbuf_4_11_0_wb_clk_i (.I(clknet_0_wb_clk_i),
+ .Z(clknet_4_11_0_wb_clk_i),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__clkbuf_8 clkbuf_4_12_0_wb_clk_i (.I(clknet_0_wb_clk_i),
+ .Z(clknet_4_12_0_wb_clk_i),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__clkbuf_8 clkbuf_4_13_0_wb_clk_i (.I(clknet_0_wb_clk_i),
+ .Z(clknet_4_13_0_wb_clk_i),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__clkbuf_8 clkbuf_4_14_0_wb_clk_i (.I(clknet_0_wb_clk_i),
+ .Z(clknet_4_14_0_wb_clk_i),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__clkbuf_8 clkbuf_4_15_0_wb_clk_i (.I(clknet_0_wb_clk_i),
+ .Z(clknet_4_15_0_wb_clk_i),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1364__D (.I(_0008_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1368__D (.I(_0010_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1441__D (.I(_0080_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__0815__A2 (.I(_0138_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__0807__A2 (.I(_0138_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__0803__A2 (.I(_0138_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__0797__A2 (.I(_0138_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__0791__A1 (.I(_0138_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__0783__A2 (.I(_0138_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__0782__A1 (.I(_0138_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__0779__A1 (.I(_0138_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__0680__A2 (.I(_0138_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__0678__A2 (.I(_0138_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__0811__A2 (.I(_0146_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__0801__A2 (.I(_0146_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__0786__A2 (.I(_0146_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__0774__A1 (.I(_0146_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__0686__A2 (.I(_0146_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__0690__I (.I(_0149_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__0692__I (.I(_0150_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1106__A1 (.I(_0151_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__0865__A1 (.I(_0151_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__0708__A1 (.I(_0151_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__0698__A2 (.I(_0151_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__0694__A3 (.I(_0151_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__0771__A1 (.I(_0176_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__0770__B (.I(_0176_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__0761__A1 (.I(_0176_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__0760__C (.I(_0176_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__0747__A1 (.I(_0176_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__0746__B1 (.I(_0176_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__0738__A3 (.I(_0176_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__0768__A1 (.I(_0177_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__0750__A1 (.I(_0177_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__0738__A1 (.I(_0177_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__0736__A1 (.I(_0177_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__0767__B (.I(_0180_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__0765__B (.I(_0180_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__0759__A1 (.I(_0180_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__0758__A1 (.I(_0180_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__0756__A1 (.I(_0180_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__0751__A1 (.I(_0180_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__0745__C (.I(_0180_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__0741__A2 (.I(_0180_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__0737__A2 (.I(_0180_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__0733__A1 (.I(_0180_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__0765__A1 (.I(_0181_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__0752__A2 (.I(_0181_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__0750__A2 (.I(_0181_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__0744__A2 (.I(_0181_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__0742__I (.I(_0181_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__0740__A2 (.I(_0181_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__0732__A1 (.I(_0181_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__0767__C (.I(_0184_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__0765__A2 (.I(_0184_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__0753__A1 (.I(_0184_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__0750__A3 (.I(_0184_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__0749__A1 (.I(_0184_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__0745__A1 (.I(_0184_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__0744__B (.I(_0184_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__0741__A1 (.I(_0184_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__0738__A2 (.I(_0184_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__0732__A2 (.I(_0184_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__0770__C (.I(_0187_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__0768__C (.I(_0187_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__0766__A1 (.I(_0187_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__0754__A1 (.I(_0187_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__0746__C (.I(_0187_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__0737__A1 (.I(_0187_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__0735__I (.I(_0187_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1106__A2 (.I(_0224_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__0775__A2 (.I(_0224_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1279__A2 (.I(_0236_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1278__A3 (.I(_0236_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1273__A2 (.I(_0236_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1271__A1 (.I(_0236_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1270__A1 (.I(_0236_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1269__B (.I(_0236_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1264__A2 (.I(_0236_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1260__A2 (.I(_0236_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__0789__A1 (.I(_0236_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__0869__A1 (.I(_0260_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__0829__B (.I(_0260_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__0826__A2 (.I(_0260_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__0819__A1 (.I(_0260_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__0830__I (.I(_0265_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__0829__C (.I(_0265_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__0825__A2 (.I(_0265_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__0819__A2 (.I(_0265_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__0855__A2 (.I(_0288_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__0853__A2 (.I(_0288_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__0851__A2 (.I(_0288_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__0849__A2 (.I(_0288_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__0847__A2 (.I(_0288_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__0845__A2 (.I(_0288_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__0850__I (.I(_0291_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__0871__I (.I(_0303_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1227__B (.I(_0307_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1177__B (.I(_0307_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1062__I (.I(_0307_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1044__I (.I(_0307_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1023__I (.I(_0307_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__0889__A1 (.I(_0307_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__0879__I (.I(_0307_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1310__B (.I(_0308_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1282__B (.I(_0308_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1065__A1 (.I(_0308_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1018__I (.I(_0308_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1009__I (.I(_0308_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__0929__A1 (.I(_0308_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__0885__A1 (.I(_0308_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1089__A2 (.I(_0313_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1085__A2 (.I(_0313_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1080__A2 (.I(_0313_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1076__A2 (.I(_0313_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1068__A2 (.I(_0313_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1060__A1 (.I(_0313_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__0885__A2 (.I(_0313_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1074__B1 (.I(_0315_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1071__B1 (.I(_0315_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1066__B1 (.I(_0315_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__0910__A1 (.I(_0315_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__0906__A1 (.I(_0315_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__0901__A2 (.I(_0315_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__0898__A2 (.I(_0315_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__0896__A2 (.I(_0315_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__0893__A2 (.I(_0315_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__0887__A2 (.I(_0315_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__0907__B (.I(_0317_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__0902__B (.I(_0317_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__0890__B (.I(_0317_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__0928__A1 (.I(_0330_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__0928__A4 (.I(_0346_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1324__A1 (.I(_0347_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__0929__A2 (.I(_0347_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__0989__I (.I(_0348_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__0982__B (.I(_0348_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__0975__C (.I(_0348_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__0951__I (.I(_0348_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__0930__I (.I(_0348_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1008__B (.I(_0349_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__0966__A1 (.I(_0349_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__0950__A1 (.I(_0349_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__0947__A1 (.I(_0349_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__0945__A1 (.I(_0349_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__0942__A1 (.I(_0349_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__0939__A1 (.I(_0349_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__0936__A1 (.I(_0349_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__0933__A2 (.I(_0349_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__0931__A2 (.I(_0349_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__0996__A1 (.I(_0362_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__0987__A1 (.I(_0362_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__0981__A1 (.I(_0362_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__0978__A1 (.I(_0362_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__0973__A1 (.I(_0362_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__0970__A1 (.I(_0362_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__0964__A1 (.I(_0362_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__0960__A1 (.I(_0362_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__0957__A1 (.I(_0362_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__0954__A1 (.I(_0362_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1223__A1 (.I(_0402_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1214__C (.I(_0402_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1173__A1 (.I(_0402_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1163__C (.I(_0402_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1120__A1 (.I(_0402_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1111__C (.I(_0402_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1016__A2 (.I(_0402_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1014__A2 (.I(_0402_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1012__A2 (.I(_0402_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1010__A2 (.I(_0402_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1347__A1 (.I(_0407_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1338__A1 (.I(_0407_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1329__B (.I(_0407_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1274__A1 (.I(_0407_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1242__B (.I(_0407_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1190__B (.I(_0407_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1137__B (.I(_0407_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1026__A1 (.I(_0407_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1021__A2 (.I(_0407_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1019__A2 (.I(_0407_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1349__A1 (.I(_0410_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1340__B (.I(_0410_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1281__C (.I(_0410_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1270__C (.I(_0410_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1218__A1 (.I(_0410_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1169__A1 (.I(_0410_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1124__B (.I(_0410_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1093__C (.I(_0410_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1031__I (.I(_0410_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1024__I (.I(_0410_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1081__A1 (.I(_0411_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1077__A1 (.I(_0411_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1069__A1 (.I(_0411_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1054__A1 (.I(_0411_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1041__A2 (.I(_0411_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1040__A2 (.I(_0411_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1038__A2 (.I(_0411_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1036__A2 (.I(_0411_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1034__A1 (.I(_0411_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1025__A2 (.I(_0411_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1334__A1 (.I(_0416_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1326__A1 (.I(_0416_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1199__A1 (.I(_0416_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1194__A1 (.I(_0416_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1090__A1 (.I(_0416_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1086__A1 (.I(_0416_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1050__B (.I(_0416_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1048__B (.I(_0416_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1043__B (.I(_0416_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1032__B (.I(_0416_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1070__A3 (.I(_0419_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1066__B2 (.I(_0419_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1055__A1 (.I(_0419_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1038__A1 (.I(_0419_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1345__A1 (.I(_0422_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1309__A1 (.I(_0422_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1307__A1 (.I(_0422_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1255__A1 (.I(_0422_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1247__B (.I(_0422_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1203__A1 (.I(_0422_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1152__A1 (.I(_0422_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1143__B (.I(_0422_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1052__B (.I(_0422_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1046__A1 (.I(_0422_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1089__B1 (.I(_0433_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1085__B1 (.I(_0433_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1080__B1 (.I(_0433_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1076__B1 (.I(_0433_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1068__B1 (.I(_0433_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1065__A2 (.I(_0433_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1061__A2 (.I(_0433_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1304__C (.I(_0435_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1300__A1 (.I(_0435_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1277__C (.I(_0435_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1258__C (.I(_0435_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1250__C (.I(_0435_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1206__C (.I(_0435_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1155__C (.I(_0435_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1147__C (.I(_0435_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1115__A1 (.I(_0435_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1063__C (.I(_0435_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1323__A2 (.I(_0468_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1295__A2 (.I(_0468_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1266__A3 (.I(_0468_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1211__A1 (.I(_0468_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1188__A2 (.I(_0468_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1135__A2 (.I(_0468_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1107__I (.I(_0468_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1243__A2 (.I(_0469_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1241__A2 (.I(_0469_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1212__A2 (.I(_0469_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1191__A2 (.I(_0469_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1161__A2 (.I(_0469_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1160__A1 (.I(_0469_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1139__I (.I(_0469_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1138__A2 (.I(_0469_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1109__A3 (.I(_0469_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1108__A2 (.I(_0469_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1154__A1 (.I(_0493_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1151__A1 (.I(_0493_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1149__A1 (.I(_0493_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1146__B1 (.I(_0493_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1142__A2 (.I(_0493_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1137__A2 (.I(_0493_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1254__B (.I(_0495_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1249__A2 (.I(_0495_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1244__A2 (.I(_0495_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1202__B (.I(_0495_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1198__A2 (.I(_0495_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1193__A2 (.I(_0495_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1151__B (.I(_0495_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1146__A2 (.I(_0495_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1140__A2 (.I(_0495_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1295__A3 (.I(_0509_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1158__B (.I(_0509_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1205__A1 (.I(_0536_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1202__A1 (.I(_0536_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1200__A1 (.I(_0536_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1198__B1 (.I(_0536_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1193__B1 (.I(_0536_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1190__A2 (.I(_0536_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1227__A1 (.I(_0558_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1222__A2 (.I(_0558_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1218__A2 (.I(_0558_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1257__A1 (.I(_0578_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1254__A1 (.I(_0578_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1252__A1 (.I(_0578_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1249__B1 (.I(_0578_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1246__A2 (.I(_0578_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1242__A2 (.I(_0578_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1277__A1 (.I(_0598_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1272__A1 (.I(_0598_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1270__B2 (.I(_0598_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1267__C (.I(_0598_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1281__B2 (.I(_0599_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1278__A4 (.I(_0599_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1273__A3 (.I(_0599_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1271__A2 (.I(_0599_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1270__A2 (.I(_0599_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1302__A1 (.I(_0612_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1299__A1 (.I(_0612_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1297__A2 (.I(_0612_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1288__A2 (.I(_0612_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1287__A3 (.I(_0612_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1285__A2 (.I(_0612_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1302__A2 (.I(_0620_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1299__A2 (.I(_0620_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1296__B (.I(_0620_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1344__A3 (.I(_0621_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1343__A2 (.I(_0621_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1341__A2 (.I(_0621_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1340__A2 (.I(_0621_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1298__A2 (.I(_0621_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1297__A3 (.I(_0621_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1324__A2 (.I(_0641_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1362__A2 (.I(_0665_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1363__I (.I(_0671_),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA_input1_I (.I(io_in[10]),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA_input2_I (.I(io_in[8]),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA_input3_I (.I(io_in[9]),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA_clkbuf_4_15_0_wb_clk_i_I (.I(clknet_0_wb_clk_i),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA_clkbuf_4_14_0_wb_clk_i_I (.I(clknet_0_wb_clk_i),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA_clkbuf_4_13_0_wb_clk_i_I (.I(clknet_0_wb_clk_i),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA_clkbuf_4_12_0_wb_clk_i_I (.I(clknet_0_wb_clk_i),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA_clkbuf_4_11_0_wb_clk_i_I (.I(clknet_0_wb_clk_i),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA_clkbuf_4_10_0_wb_clk_i_I (.I(clknet_0_wb_clk_i),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA_clkbuf_4_9_0_wb_clk_i_I (.I(clknet_0_wb_clk_i),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA_clkbuf_4_8_0_wb_clk_i_I (.I(clknet_0_wb_clk_i),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA_clkbuf_4_7_0_wb_clk_i_I (.I(clknet_0_wb_clk_i),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA_clkbuf_4_6_0_wb_clk_i_I (.I(clknet_0_wb_clk_i),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA_clkbuf_4_5_0_wb_clk_i_I (.I(clknet_0_wb_clk_i),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA_clkbuf_4_4_0_wb_clk_i_I (.I(clknet_0_wb_clk_i),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA_clkbuf_4_3_0_wb_clk_i_I (.I(clknet_0_wb_clk_i),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA_clkbuf_4_2_0_wb_clk_i_I (.I(clknet_0_wb_clk_i),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA_clkbuf_4_1_0_wb_clk_i_I (.I(clknet_0_wb_clk_i),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA_clkbuf_4_0_0_wb_clk_i_I (.I(clknet_0_wb_clk_i),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__0845__A1 (.I(\vga_clock.color[0] ),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__0847__A1 (.I(\vga_clock.color[1] ),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__0855__A1 (.I(\vga_clock.color[5] ),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1509__D (.I(\vga_clock.digit_0.char[1] ),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__0788__A3 (.I(\vga_clock.digit_0.char[1] ),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__0781__A1 (.I(\vga_clock.digit_0.char[1] ),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__0682__A2 (.I(\vga_clock.digit_0.char[1] ),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__0675__A2 (.I(\vga_clock.digit_0.char[1] ),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1510__D (.I(\vga_clock.digit_0.char[2] ),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__0795__A1 (.I(\vga_clock.digit_0.char[2] ),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__0781__A2 (.I(\vga_clock.digit_0.char[2] ),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__0780__A1 (.I(\vga_clock.digit_0.char[2] ),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__0777__A2 (.I(\vga_clock.digit_0.char[2] ),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__0688__A3 (.I(\vga_clock.digit_0.char[2] ),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1511__D (.I(\vga_clock.digit_0.char[3] ),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__0876__A2 (.I(\vga_clock.digit_0.char[3] ),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__0874__A2 (.I(\vga_clock.digit_0.char[3] ),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__0798__A1 (.I(\vga_clock.digit_0.char[3] ),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__0785__C (.I(\vga_clock.digit_0.char[3] ),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__0728__A1 (.I(\vga_clock.digit_0.digit_index[0] ),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__0705__A1 (.I(\vga_clock.digit_0.digit_index[0] ),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__0707__I (.I(\vga_clock.digit_0.digit_index[1] ),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__0702__A2 (.I(\vga_clock.digit_0.digit_index[1] ),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1462__D (.I(\vga_clock.digit_0.number[0] ),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__0868__A1 (.I(\vga_clock.digit_0.number[0] ),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__0829__A1 (.I(\vga_clock.digit_0.number[0] ),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__0820__A1 (.I(\vga_clock.digit_0.number[0] ),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1506__D (.I(\vga_clock.digit_0.x_block[0] ),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1100__A3 (.I(\vga_clock.digit_0.x_block[0] ),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__0876__A1 (.I(\vga_clock.digit_0.x_block[0] ),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1507__D (.I(\vga_clock.digit_0.x_block[1] ),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1100__A2 (.I(\vga_clock.digit_0.x_block[1] ),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__0874__A1 (.I(\vga_clock.digit_0.x_block[1] ),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1352__A1 (.I(\vga_clock.hrs_d[0] ),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1350__A1 (.I(\vga_clock.hrs_d[0] ),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1262__A2 (.I(\vga_clock.hrs_d[0] ),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__0792__I0 (.I(\vga_clock.hrs_d[0] ),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1279__A1 (.I(\vga_clock.hrs_u[2] ),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1278__A1 (.I(\vga_clock.hrs_u[2] ),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1276__A1 (.I(\vga_clock.hrs_u[2] ),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1264__A1 (.I(\vga_clock.hrs_u[2] ),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1261__A2 (.I(\vga_clock.hrs_u[2] ),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__0810__A1 (.I(\vga_clock.hrs_u[2] ),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1288__A1 (.I(\vga_clock.min_d[0] ),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1287__A2 (.I(\vga_clock.min_d[0] ),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1285__A1 (.I(\vga_clock.min_d[0] ),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1282__A1 (.I(\vga_clock.min_d[0] ),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1268__A1 (.I(\vga_clock.min_d[0] ),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1267__A1 (.I(\vga_clock.min_d[0] ),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__0786__A1 (.I(\vga_clock.min_d[0] ),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1306__A2 (.I(\vga_clock.min_u[1] ),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1305__A1 (.I(\vga_clock.min_u[1] ),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1304__A1 (.I(\vga_clock.min_u[1] ),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1303__A1 (.I(\vga_clock.min_u[1] ),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1283__A2 (.I(\vga_clock.min_u[1] ),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__0796__A1 (.I(\vga_clock.min_u[1] ),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1306__A1 (.I(\vga_clock.min_u[2] ),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1305__B (.I(\vga_clock.min_u[2] ),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1284__A1 (.I(\vga_clock.min_u[2] ),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__0808__A1 (.I(\vga_clock.min_u[2] ),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1308__A1 (.I(\vga_clock.min_u[3] ),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1283__A1 (.I(\vga_clock.min_u[3] ),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__0816__A1 (.I(\vga_clock.min_u[3] ),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1196__A1 (.I(\vga_clock.pulse_min.count[1] ),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1195__A2 (.I(\vga_clock.pulse_min.count[1] ),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1193__A1 (.I(\vga_clock.pulse_min.count[1] ),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1192__A1 (.I(\vga_clock.pulse_min.count[1] ),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1187__A1 (.I(\vga_clock.pulse_min.count[1] ),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1182__I (.I(\vga_clock.pulse_min.count[1] ),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1156__A2 (.I(\vga_clock.pulse_min.count[1] ),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1204__A1 (.I(\vga_clock.pulse_min.count[3] ),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1201__A1 (.I(\vga_clock.pulse_min.count[3] ),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1200__B (.I(\vga_clock.pulse_min.count[3] ),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1183__A1 (.I(\vga_clock.pulse_min.count[3] ),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1156__A1 (.I(\vga_clock.pulse_min.count[3] ),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1237__B1 (.I(\vga_clock.pulse_sec.comp[0] ),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1235__B1 (.I(\vga_clock.pulse_sec.comp[0] ),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1220__A2 (.I(\vga_clock.pulse_sec.comp[0] ),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1216__A2 (.I(\vga_clock.pulse_sec.comp[0] ),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1215__A1 (.I(\vga_clock.pulse_sec.comp[0] ),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1214__A1 (.I(\vga_clock.pulse_sec.comp[0] ),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1213__A1 (.I(\vga_clock.pulse_sec.comp[0] ),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1248__A2 (.I(\vga_clock.pulse_sec.count[1] ),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1245__A1 (.I(\vga_clock.pulse_sec.count[1] ),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1244__A1 (.I(\vga_clock.pulse_sec.count[1] ),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1238__B2 (.I(\vga_clock.pulse_sec.count[1] ),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1235__A1 (.I(\vga_clock.pulse_sec.count[1] ),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1207__A1 (.I(\vga_clock.pulse_sec.count[1] ),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__0977__A1 (.I(\vga_clock.sec_counter[14] ),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__0972__A1 (.I(\vga_clock.sec_counter[14] ),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__0971__A1 (.I(\vga_clock.sec_counter[14] ),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__0918__A1 (.I(\vga_clock.sec_counter[14] ),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__0962__A2 (.I(\vga_clock.sec_counter[9] ),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__0956__A1 (.I(\vga_clock.sec_counter[9] ),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__0955__A1 (.I(\vga_clock.sec_counter[9] ),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__0926__A2 (.I(\vga_clock.sec_counter[9] ),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1317__A1 (.I(\vga_clock.sec_d[0] ),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1316__A2 (.I(\vga_clock.sec_d[0] ),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1314__A1 (.I(\vga_clock.sec_d[0] ),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1310__A1 (.I(\vga_clock.sec_d[0] ),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1296__A1 (.I(\vga_clock.sec_d[0] ),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__0783__B2 (.I(\vga_clock.sec_d[0] ),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1317__B (.I(\vga_clock.sec_d[1] ),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1316__A1 (.I(\vga_clock.sec_d[1] ),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1294__A2 (.I(\vga_clock.sec_d[1] ),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__0797__A1 (.I(\vga_clock.sec_d[1] ),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1335__A3 (.I(\vga_clock.sec_u[0] ),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1332__A2 (.I(\vga_clock.sec_u[0] ),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1327__A1 (.I(\vga_clock.sec_u[0] ),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1325__A1 (.I(\vga_clock.sec_u[0] ),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1312__A2 (.I(\vga_clock.sec_u[0] ),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__0783__A1 (.I(\vga_clock.sec_u[0] ),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1335__A2 (.I(\vga_clock.sec_u[1] ),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1332__A1 (.I(\vga_clock.sec_u[1] ),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1330__A1 (.I(\vga_clock.sec_u[1] ),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1329__A1 (.I(\vga_clock.sec_u[1] ),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1311__A2 (.I(\vga_clock.sec_u[1] ),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__0797__B2 (.I(\vga_clock.sec_u[1] ),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1016__A1 (.I(\vga_clock.vga_0.hc[3] ),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__0895__A1 (.I(\vga_clock.vga_0.hc[3] ),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__0894__A1 (.I(\vga_clock.vga_0.hc[3] ),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__0857__A1 (.I(\vga_clock.vga_0.hc[3] ),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1021__A1 (.I(\vga_clock.vga_0.hc[5] ),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__0900__A1 (.I(\vga_clock.vga_0.hc[5] ),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__0899__A1 (.I(\vga_clock.vga_0.hc[5] ),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__0882__A1 (.I(\vga_clock.vga_0.hc[5] ),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__0859__A1 (.I(\vga_clock.vga_0.hc[5] ),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1033__A1 (.I(\vga_clock.vga_0.hc[9] ),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__0909__B (.I(\vga_clock.vga_0.hc[9] ),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__0888__A2 (.I(\vga_clock.vga_0.hc[9] ),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__0884__A2 (.I(\vga_clock.vga_0.hc[9] ),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__0835__A2 (.I(\vga_clock.vga_0.hc[9] ),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1064__A2 (.I(\vga_clock.vga_0.vc[0] ),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1063__A1 (.I(\vga_clock.vga_0.vc[0] ),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1061__A1 (.I(\vga_clock.vga_0.vc[0] ),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1035__I (.I(\vga_clock.vga_0.vc[0] ),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__0862__A2 (.I(\vga_clock.vga_0.vc[0] ),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1083__A2 (.I(\vga_clock.vga_0.vc[5] ),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1078__A1 (.I(\vga_clock.vga_0.vc[5] ),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1076__A1 (.I(\vga_clock.vga_0.vc[5] ),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1075__A1 (.I(\vga_clock.vga_0.vc[5] ),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1045__A1 (.I(\vga_clock.vga_0.vc[5] ),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__0860__A3 (.I(\vga_clock.vga_0.vc[5] ),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__0839__A1 (.I(\vga_clock.vga_0.vc[5] ),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1083__A1 (.I(\vga_clock.vga_0.vc[6] ),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1080__A1 (.I(\vga_clock.vga_0.vc[6] ),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1079__A1 (.I(\vga_clock.vga_0.vc[6] ),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1047__A1 (.I(\vga_clock.vga_0.vc[6] ),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__0861__A1 (.I(\vga_clock.vga_0.vc[6] ),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__0840__A1 (.I(\vga_clock.vga_0.vc[6] ),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1085__A1 (.I(\vga_clock.vga_0.vc[7] ),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1082__I (.I(\vga_clock.vga_0.vc[7] ),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1049__A1 (.I(\vga_clock.vga_0.vc[7] ),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__0860__A2 (.I(\vga_clock.vga_0.vc[7] ),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__0841__A1 (.I(\vga_clock.vga_0.vc[7] ),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1091__A1 (.I(\vga_clock.vga_0.vc[8] ),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1089__A1 (.I(\vga_clock.vga_0.vc[8] ),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1088__A1 (.I(\vga_clock.vga_0.vc[8] ),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1051__A1 (.I(\vga_clock.vga_0.vc[8] ),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__0860__A1 (.I(\vga_clock.vga_0.vc[8] ),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__0842__A1 (.I(\vga_clock.vga_0.vc[8] ),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1092__I (.I(\vga_clock.vga_0.vc[9] ),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1058__A1 (.I(\vga_clock.vga_0.vc[9] ),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1053__A1 (.I(\vga_clock.vga_0.vc[9] ),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__0863__C (.I(\vga_clock.vga_0.vc[9] ),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__0843__A1 (.I(\vga_clock.vga_0.vc[9] ),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__0818__A1 (.I(\vga_clock.vga_0.x_px[8] ),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__0788__A2 (.I(\vga_clock.vga_0.x_px[8] ),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__0782__A2 (.I(\vga_clock.vga_0.x_px[8] ),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__0773__A2 (.I(\vga_clock.vga_0.x_px[8] ),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__0772__A3 (.I(\vga_clock.vga_0.x_px[8] ),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__0686__A1 (.I(\vga_clock.vga_0.x_px[8] ),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA_clkbuf_0_wb_clk_i_I (.I(wb_clk_i),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA_input4_I (.I(wb_rst_i),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1323__A1 (.I(net1),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1241__A1 (.I(net1),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1226__B (.I(net1),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1217__A1 (.I(net1),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1212__A1 (.I(net1),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1210__A1 (.I(net1),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1266__A1 (.I(net2),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1135__A1 (.I(net2),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1123__B (.I(net2),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1114__A1 (.I(net2),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1109__A1 (.I(net2),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1099__A1 (.I(net2),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1295__A1 (.I(net3),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1188__A1 (.I(net3),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1176__B (.I(net3),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1168__A1 (.I(net3),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1161__A1 (.I(net3),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1159__A1 (.I(net3),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA_output5_I (.I(net5),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA_output6_I (.I(net6),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA_output11_I (.I(net11),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1368__CLK (.I(clknet_4_0_0_wb_clk_i),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1382__CLK (.I(clknet_4_0_0_wb_clk_i),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1383__CLK (.I(clknet_4_0_0_wb_clk_i),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1385__CLK (.I(clknet_4_0_0_wb_clk_i),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1387__CLK (.I(clknet_4_0_0_wb_clk_i),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1388__CLK (.I(clknet_4_0_0_wb_clk_i),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1389__CLK (.I(clknet_4_0_0_wb_clk_i),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1390__CLK (.I(clknet_4_0_0_wb_clk_i),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1391__CLK (.I(clknet_4_0_0_wb_clk_i),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1378__CLK (.I(clknet_4_1_0_wb_clk_i),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1379__CLK (.I(clknet_4_1_0_wb_clk_i),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1380__CLK (.I(clknet_4_1_0_wb_clk_i),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1381__CLK (.I(clknet_4_1_0_wb_clk_i),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1386__CLK (.I(clknet_4_1_0_wb_clk_i),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1392__CLK (.I(clknet_4_1_0_wb_clk_i),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1393__CLK (.I(clknet_4_1_0_wb_clk_i),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1394__CLK (.I(clknet_4_1_0_wb_clk_i),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1395__CLK (.I(clknet_4_1_0_wb_clk_i),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1396__CLK (.I(clknet_4_1_0_wb_clk_i),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1366__CLK (.I(clknet_4_2_0_wb_clk_i),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1384__CLK (.I(clknet_4_2_0_wb_clk_i),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1431__CLK (.I(clknet_4_2_0_wb_clk_i),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1432__CLK (.I(clknet_4_2_0_wb_clk_i),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1433__CLK (.I(clknet_4_2_0_wb_clk_i),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1434__CLK (.I(clknet_4_2_0_wb_clk_i),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1435__CLK (.I(clknet_4_2_0_wb_clk_i),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1436__CLK (.I(clknet_4_2_0_wb_clk_i),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1437__CLK (.I(clknet_4_2_0_wb_clk_i),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1438__CLK (.I(clknet_4_2_0_wb_clk_i),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1375__CLK (.I(clknet_4_3_0_wb_clk_i),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1376__CLK (.I(clknet_4_3_0_wb_clk_i),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1377__CLK (.I(clknet_4_3_0_wb_clk_i),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1411__CLK (.I(clknet_4_3_0_wb_clk_i),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1412__CLK (.I(clknet_4_3_0_wb_clk_i),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1414__CLK (.I(clknet_4_3_0_wb_clk_i),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1415__CLK (.I(clknet_4_3_0_wb_clk_i),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1419__CLK (.I(clknet_4_3_0_wb_clk_i),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1439__CLK (.I(clknet_4_3_0_wb_clk_i),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1440__CLK (.I(clknet_4_3_0_wb_clk_i),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1397__CLK (.I(clknet_4_4_0_wb_clk_i),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1398__CLK (.I(clknet_4_4_0_wb_clk_i),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1399__CLK (.I(clknet_4_4_0_wb_clk_i),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1400__CLK (.I(clknet_4_4_0_wb_clk_i),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1401__CLK (.I(clknet_4_4_0_wb_clk_i),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1408__CLK (.I(clknet_4_4_0_wb_clk_i),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1409__CLK (.I(clknet_4_4_0_wb_clk_i),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1410__CLK (.I(clknet_4_4_0_wb_clk_i),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1402__CLK (.I(clknet_4_5_0_wb_clk_i),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1403__CLK (.I(clknet_4_5_0_wb_clk_i),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1404__CLK (.I(clknet_4_5_0_wb_clk_i),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1405__CLK (.I(clknet_4_5_0_wb_clk_i),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1406__CLK (.I(clknet_4_5_0_wb_clk_i),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1407__CLK (.I(clknet_4_5_0_wb_clk_i),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1492__CLK (.I(clknet_4_5_0_wb_clk_i),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1494__CLK (.I(clknet_4_5_0_wb_clk_i),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1372__CLK (.I(clknet_4_6_0_wb_clk_i),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1413__CLK (.I(clknet_4_6_0_wb_clk_i),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1417__CLK (.I(clknet_4_6_0_wb_clk_i),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1418__CLK (.I(clknet_4_6_0_wb_clk_i),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1420__CLK (.I(clknet_4_6_0_wb_clk_i),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1495__CLK (.I(clknet_4_6_0_wb_clk_i),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1496__CLK (.I(clknet_4_6_0_wb_clk_i),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1509__CLK (.I(clknet_4_6_0_wb_clk_i),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1510__CLK (.I(clknet_4_6_0_wb_clk_i),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1484__CLK (.I(clknet_4_7_0_wb_clk_i),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1486__CLK (.I(clknet_4_7_0_wb_clk_i),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1487__CLK (.I(clknet_4_7_0_wb_clk_i),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1488__CLK (.I(clknet_4_7_0_wb_clk_i),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1489__CLK (.I(clknet_4_7_0_wb_clk_i),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1490__CLK (.I(clknet_4_7_0_wb_clk_i),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1491__CLK (.I(clknet_4_7_0_wb_clk_i),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1493__CLK (.I(clknet_4_7_0_wb_clk_i),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1497__CLK (.I(clknet_4_7_0_wb_clk_i),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1421__CLK (.I(clknet_4_8_0_wb_clk_i),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1422__CLK (.I(clknet_4_8_0_wb_clk_i),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1423__CLK (.I(clknet_4_8_0_wb_clk_i),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1424__CLK (.I(clknet_4_8_0_wb_clk_i),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1425__CLK (.I(clknet_4_8_0_wb_clk_i),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1426__CLK (.I(clknet_4_8_0_wb_clk_i),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1427__CLK (.I(clknet_4_8_0_wb_clk_i),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1428__CLK (.I(clknet_4_8_0_wb_clk_i),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1429__CLK (.I(clknet_4_8_0_wb_clk_i),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1430__CLK (.I(clknet_4_8_0_wb_clk_i),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1464__CLK (.I(clknet_4_8_0_wb_clk_i),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1501__CLK (.I(clknet_4_8_0_wb_clk_i),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1514__CLK (.I(clknet_4_8_0_wb_clk_i),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1367__CLK (.I(clknet_4_9_0_wb_clk_i),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1416__CLK (.I(clknet_4_9_0_wb_clk_i),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1462__CLK (.I(clknet_4_9_0_wb_clk_i),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1463__CLK (.I(clknet_4_9_0_wb_clk_i),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1465__CLK (.I(clknet_4_9_0_wb_clk_i),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1466__CLK (.I(clknet_4_9_0_wb_clk_i),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1504__CLK (.I(clknet_4_9_0_wb_clk_i),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1512__CLK (.I(clknet_4_9_0_wb_clk_i),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1364__CLK (.I(clknet_4_10_0_wb_clk_i),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1369__CLK (.I(clknet_4_10_0_wb_clk_i),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1370__CLK (.I(clknet_4_10_0_wb_clk_i),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1371__CLK (.I(clknet_4_10_0_wb_clk_i),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1500__CLK (.I(clknet_4_10_0_wb_clk_i),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1502__CLK (.I(clknet_4_10_0_wb_clk_i),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1503__CLK (.I(clknet_4_10_0_wb_clk_i),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1505__CLK (.I(clknet_4_10_0_wb_clk_i),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1365__CLK (.I(clknet_4_11_0_wb_clk_i),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1373__CLK (.I(clknet_4_11_0_wb_clk_i),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1374__CLK (.I(clknet_4_11_0_wb_clk_i),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1441__CLK (.I(clknet_4_11_0_wb_clk_i),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1467__CLK (.I(clknet_4_11_0_wb_clk_i),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1469__CLK (.I(clknet_4_11_0_wb_clk_i),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1498__CLK (.I(clknet_4_11_0_wb_clk_i),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1499__CLK (.I(clknet_4_11_0_wb_clk_i),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1506__CLK (.I(clknet_4_11_0_wb_clk_i),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1507__CLK (.I(clknet_4_11_0_wb_clk_i),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1511__CLK (.I(clknet_4_11_0_wb_clk_i),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1447__CLK (.I(clknet_4_12_0_wb_clk_i),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1472__CLK (.I(clknet_4_12_0_wb_clk_i),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1478__CLK (.I(clknet_4_12_0_wb_clk_i),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1480__CLK (.I(clknet_4_12_0_wb_clk_i),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1481__CLK (.I(clknet_4_12_0_wb_clk_i),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1483__CLK (.I(clknet_4_12_0_wb_clk_i),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1508__CLK (.I(clknet_4_12_0_wb_clk_i),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1442__CLK (.I(clknet_4_13_0_wb_clk_i),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1444__CLK (.I(clknet_4_13_0_wb_clk_i),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1445__CLK (.I(clknet_4_13_0_wb_clk_i),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1446__CLK (.I(clknet_4_13_0_wb_clk_i),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1450__CLK (.I(clknet_4_13_0_wb_clk_i),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1451__CLK (.I(clknet_4_13_0_wb_clk_i),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1477__CLK (.I(clknet_4_13_0_wb_clk_i),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1482__CLK (.I(clknet_4_13_0_wb_clk_i),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1485__CLK (.I(clknet_4_13_0_wb_clk_i),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1468__CLK (.I(clknet_4_14_0_wb_clk_i),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1470__CLK (.I(clknet_4_14_0_wb_clk_i),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1471__CLK (.I(clknet_4_14_0_wb_clk_i),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1473__CLK (.I(clknet_4_14_0_wb_clk_i),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1474__CLK (.I(clknet_4_14_0_wb_clk_i),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1475__CLK (.I(clknet_4_14_0_wb_clk_i),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1476__CLK (.I(clknet_4_14_0_wb_clk_i),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1479__CLK (.I(clknet_4_14_0_wb_clk_i),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1513__CLK (.I(clknet_4_14_0_wb_clk_i),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1443__CLK (.I(clknet_4_15_0_wb_clk_i),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1448__CLK (.I(clknet_4_15_0_wb_clk_i),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1449__CLK (.I(clknet_4_15_0_wb_clk_i),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1452__CLK (.I(clknet_4_15_0_wb_clk_i),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1453__CLK (.I(clknet_4_15_0_wb_clk_i),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1454__CLK (.I(clknet_4_15_0_wb_clk_i),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1455__CLK (.I(clknet_4_15_0_wb_clk_i),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1456__CLK (.I(clknet_4_15_0_wb_clk_i),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1457__CLK (.I(clknet_4_15_0_wb_clk_i),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1458__CLK (.I(clknet_4_15_0_wb_clk_i),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1459__CLK (.I(clknet_4_15_0_wb_clk_i),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1460__CLK (.I(clknet_4_15_0_wb_clk_i),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__antenna ANTENNA__1461__CLK (.I(clknet_4_15_0_wb_clk_i),
+ .VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_0_2 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_0_17 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_0_23 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_0_29 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_0_33 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_0_37 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_0_41 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_8 FILLER_0_47 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_0_55 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_0_59 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_0_65 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_0_69 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_0_72 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_0_76 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_0_78 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_8 FILLER_0_83 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_0_91 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_0_95 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_0_101 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_32 FILLER_0_107 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_0_139 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_8 FILLER_0_142 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_0_150 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_16 FILLER_0_155 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_0_171 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_0_177 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_16 FILLER_0_182 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_8 FILLER_0_198 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_0_206 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_0_212 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_8 FILLER_0_217 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_0_225 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_8 FILLER_0_233 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_0_241 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_0_247 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_8 FILLER_0_252 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_0_260 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_0_264 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_0_279 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_0_282 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_8 FILLER_0_287 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_0_295 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_0_299 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_8 FILLER_0_305 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_0_313 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_16 FILLER_0_317 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_0_333 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_8 FILLER_0_341 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_0_349 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_8 FILLER_0_352 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_0_360 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_8 FILLER_0_365 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_0_373 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_0_377 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_0_383 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_8 FILLER_0_387 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_0_395 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_8 FILLER_0_401 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_0_409 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_0_413 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_0_419 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_8 FILLER_0_422 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_0_430 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_0_432 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_16 FILLER_0_437 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_0_453 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_0_457 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_0_472 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_8 FILLER_0_478 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_0_486 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_0_492 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_0_497 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_0_501 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_0_503 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_0_508 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_1_2 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_1_6 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_1_14 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_32 FILLER_1_20 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_16 FILLER_1_52 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_1_68 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_1_70 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_64 FILLER_1_73 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_1_137 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_1_141 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_64 FILLER_1_144 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_1_208 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_1_212 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_32 FILLER_1_215 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_8 FILLER_1_247 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_1_255 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_16 FILLER_1_262 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_1_278 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_1_282 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_64 FILLER_1_286 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_1_350 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_1_354 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_64 FILLER_1_357 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_1_421 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_1_425 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_8 FILLER_1_428 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_1_436 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_1_440 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_32 FILLER_1_448 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_16 FILLER_1_480 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_1_496 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_1_499 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_1_503 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_1_508 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_2_2 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_2_7 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_2_19 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_2_23 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_8 FILLER_2_27 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_64 FILLER_2_37 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_2_101 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_2_105 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_64 FILLER_2_108 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_2_172 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_2_176 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_32 FILLER_2_179 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_16 FILLER_2_211 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_8 FILLER_2_227 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_2_235 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_2_239 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_2_243 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_2_247 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_2_250 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_32 FILLER_2_259 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_16 FILLER_2_291 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_8 FILLER_2_307 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_2_315 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_64 FILLER_2_321 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_2_385 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_2_389 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_32 FILLER_2_392 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_2_424 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_2_428 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_2_432 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_16 FILLER_2_442 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_2_458 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_2_460 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_32 FILLER_2_463 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_8 FILLER_2_495 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_2_503 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_2_507 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_64 FILLER_3_2 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_3_66 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_3_70 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_64 FILLER_3_73 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_3_137 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_3_141 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_64 FILLER_3_144 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_3_208 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_3_212 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_64 FILLER_3_215 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_3_279 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_3_283 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_64 FILLER_3_286 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_3_350 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_3_354 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_64 FILLER_3_357 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_3_421 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_3_425 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_64 FILLER_3_428 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_3_492 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_3_496 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_8 FILLER_3_499 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_3_507 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_32 FILLER_4_2 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_4_34 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_64 FILLER_4_37 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_4_101 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_4_105 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_64 FILLER_4_108 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_4_172 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_4_176 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_64 FILLER_4_179 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_4_243 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_4_247 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_64 FILLER_4_250 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_4_314 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_4_318 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_64 FILLER_4_321 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_4_385 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_4_389 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_64 FILLER_4_392 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_4_456 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_4_460 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_32 FILLER_4_463 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_8 FILLER_4_495 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_4_503 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_4_507 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_64 FILLER_5_2 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_5_66 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_5_70 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_64 FILLER_5_73 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_5_137 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_5_141 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_64 FILLER_5_144 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_5_208 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_5_212 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_64 FILLER_5_215 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_5_279 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_5_283 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_64 FILLER_5_286 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_5_350 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_5_354 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_64 FILLER_5_357 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_5_421 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_5_425 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_64 FILLER_5_428 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_5_492 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_5_496 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_8 FILLER_5_499 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_5_507 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_32 FILLER_6_2 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_6_34 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_64 FILLER_6_37 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_6_101 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_6_105 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_64 FILLER_6_108 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_6_172 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_6_176 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_32 FILLER_6_179 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_6_211 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_6_213 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_8 FILLER_6_216 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_6_224 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_8 FILLER_6_230 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_6_238 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_6_240 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_6_245 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_6_247 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_6_250 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_32 FILLER_6_253 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_6_285 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_6_318 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_6_321 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_64 FILLER_6_324 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_6_388 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_64 FILLER_6_392 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_6_456 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_6_460 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_32 FILLER_6_463 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_8 FILLER_6_495 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_6_503 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_6_508 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_64 FILLER_7_2 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_7_66 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_7_70 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_16 FILLER_7_73 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_7_89 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_7_91 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_7_121 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_7_125 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_8 FILLER_7_129 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_7_137 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_7_141 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_16 FILLER_7_144 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_8 FILLER_7_160 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_7_168 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_7_199 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_7_203 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_7_207 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_7_209 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_7_212 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_7_215 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_7_245 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_7_247 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_7_250 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_7_281 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_7_283 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_7_286 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_7_316 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_16 FILLER_7_324 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_8 FILLER_7_340 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_7_348 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_7_352 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_7_354 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_16 FILLER_7_357 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_7_373 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_7_379 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_7_410 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_8 FILLER_7_414 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_7_422 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_64 FILLER_7_428 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_7_492 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_7_496 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_8 FILLER_7_499 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_7_507 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_32 FILLER_8_2 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_8_34 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_64 FILLER_8_37 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_8_101 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_8_105 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_32 FILLER_8_108 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_16 FILLER_8_140 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_8 FILLER_8_156 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_8_164 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_8_168 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_8_175 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_8_179 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_8_182 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_8_215 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_8_219 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_8_222 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_8_228 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_8_242 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_8_246 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_8_250 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_8_252 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_8_271 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_8_277 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_8_281 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_8_289 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_8_297 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_8_301 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_8 FILLER_8_305 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_8_313 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_8_315 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_8_318 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_64 FILLER_8_321 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_8_385 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_8_389 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_64 FILLER_8_392 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_8_456 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_8_460 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_16 FILLER_8_463 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_8 FILLER_8_479 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_8_487 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_8_489 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_8_492 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_8_508 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_64 FILLER_9_2 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_9_66 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_9_70 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_64 FILLER_9_73 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_9_137 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_9_141 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_32 FILLER_9_144 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_16 FILLER_9_176 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_9_194 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_9_202 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_9_206 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_9_210 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_9_212 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_9_215 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_9_228 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_9_236 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_9_244 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_9_258 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_9_268 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_9_278 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_9_282 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_9_286 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_9_293 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_16 FILLER_9_297 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_9_313 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_9_317 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_9_319 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_9_349 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_9_353 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_64 FILLER_9_357 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_9_421 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_9_425 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_64 FILLER_9_428 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_9_492 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_9_496 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_8 FILLER_9_499 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_9_507 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_32 FILLER_10_2 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_10_34 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_64 FILLER_10_37 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_10_101 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_10_105 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_64 FILLER_10_108 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_10_172 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_10_176 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_10_179 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_10_182 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_10_190 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_10_194 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_10_197 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_10_201 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_10_205 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_10_207 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_10_217 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_8 FILLER_10_221 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_10_229 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_10_233 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_10_235 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_10_238 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_10_242 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_10_246 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_10_250 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_10_258 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_10_271 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_10_278 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_10_280 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_10_287 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_10_318 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_10_321 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_16 FILLER_10_324 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_8 FILLER_10_340 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_10_348 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_10_350 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_10_364 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_10_368 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_8 FILLER_10_375 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_10_383 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_10_387 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_10_389 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_10_392 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_10_422 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_32 FILLER_10_426 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_10_458 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_10_460 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_32 FILLER_10_463 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_8 FILLER_10_495 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_10_503 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_10_507 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_64 FILLER_11_2 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_11_66 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_11_70 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_64 FILLER_11_73 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_11_137 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_11_141 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_16 FILLER_11_144 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_11_160 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_11_164 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_11_166 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_11_196 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_11_207 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_11_211 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_11_215 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_11_218 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_8 FILLER_11_222 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_11_230 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_11_234 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_11_237 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_11_251 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_11_257 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_11_261 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_11_267 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_11_274 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_11_278 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_11_282 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_16 FILLER_11_286 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_8 FILLER_11_302 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_11_310 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_11_340 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_8 FILLER_11_344 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_11_354 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_11_357 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_16 FILLER_11_390 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_11_406 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_8 FILLER_11_416 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_11_424 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_64 FILLER_11_428 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_11_492 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_11_496 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_8 FILLER_11_499 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_11_507 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_12_2 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_16 FILLER_12_7 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_8 FILLER_12_23 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_12_31 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_64 FILLER_12_37 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_12_101 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_12_105 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_64 FILLER_12_108 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_12_172 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_12_176 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_12_179 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_12_185 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_12_189 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_12_203 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_12_205 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_12_208 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_12_212 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_12_243 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_12_247 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_12_250 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_12_257 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_12_261 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_12_267 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_12_279 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_12_283 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_32 FILLER_12_287 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_8 FILLER_12_321 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_12_329 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_8 FILLER_12_332 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_12_352 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_12_356 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_12_363 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_16 FILLER_12_367 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_12_383 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_12_387 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_12_389 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_64 FILLER_12_392 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_12_456 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_12_460 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_32 FILLER_12_463 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_8 FILLER_12_495 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_12_503 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_12_508 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_64 FILLER_13_2 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_13_66 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_13_70 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_64 FILLER_13_73 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_13_137 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_13_141 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_8 FILLER_13_144 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_13_152 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_13_156 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_13_187 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_13_202 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_13_209 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_13_215 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_13_217 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_13_225 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_13_229 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_13_233 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_13_237 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_13_247 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_13_249 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_13_255 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_13_265 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_13_275 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_13_283 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_13_286 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_13_295 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_13_299 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_13_330 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_13_345 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_13_347 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_13_354 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_13_357 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_8 FILLER_13_366 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_13_376 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_13_380 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_13_411 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_8 FILLER_13_415 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_13_423 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_13_425 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_13_428 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_13_433 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_8 FILLER_13_437 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_13_447 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_13_451 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_32 FILLER_13_455 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_8 FILLER_13_487 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_13_495 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_8 FILLER_13_499 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_13_507 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_14_2 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_16 FILLER_14_7 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_8 FILLER_14_23 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_14_31 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_16 FILLER_14_37 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_8 FILLER_14_53 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_14_61 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_14_65 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_14_67 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_14_97 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_14_101 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_14_105 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_64 FILLER_14_108 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_14_172 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_14_176 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_14_179 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_14_181 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_14_188 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_14_199 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_14_207 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_14_211 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_14_214 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_14_218 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_14_228 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_14_232 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_14_236 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_14_240 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_14_243 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_14_247 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_14_250 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_14_256 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_14_262 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_14_269 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_8 FILLER_14_279 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_14_316 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_14_318 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_14_321 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_16 FILLER_14_324 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_14_340 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_14_344 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_14_374 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_14_378 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_14_387 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_14_389 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_14_392 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_14_401 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_8 FILLER_14_405 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_14_413 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_14_415 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_14_429 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_14_437 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_14_441 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_14_445 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_14_448 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_14_452 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_14_458 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_14_460 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_14_463 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_32 FILLER_14_466 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_14_500 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_14_508 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_16 FILLER_15_2 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_8 FILLER_15_18 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_15_26 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_15_57 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_8 FILLER_15_61 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_15_69 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_15_73 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_15_75 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_15_78 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_15_86 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_15_90 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_15_120 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_16 FILLER_15_124 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_15_140 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_32 FILLER_15_144 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_15_176 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_15_180 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_15_184 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_15_212 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_15_215 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_15_229 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_15_235 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_15_239 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_15_242 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_15_248 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_15_260 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_15_264 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_15_268 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_15_271 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_15_283 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_15_286 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_32 FILLER_15_289 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_16 FILLER_15_321 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_8 FILLER_15_337 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_15_345 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_15_348 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_15_354 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_15_357 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_15_366 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_15_368 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_15_392 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_15_412 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_15_414 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_15_417 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_15_421 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_15_425 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_15_428 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_15_434 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_15_444 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_15_446 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_15_455 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_15_465 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_15_469 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_16 FILLER_15_473 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_8 FILLER_15_489 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_8 FILLER_15_499 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_15_507 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_32 FILLER_16_2 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_16_34 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_16_37 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_16_47 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_16_51 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_16_55 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_16_85 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_16 FILLER_16_89 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_16_105 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_64 FILLER_16_108 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_16_172 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_16_176 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_16_179 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_16_182 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_16_186 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_16_217 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_16_219 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_16_226 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_16_240 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_16_247 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_16_250 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_16_255 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_8 FILLER_16_259 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_16_269 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_16_279 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_16_286 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_16_290 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_16 FILLER_16_294 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_8 FILLER_16_310 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_16_318 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_16_321 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_16_327 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_16_331 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_16_333 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_16_346 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_16_350 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_16_354 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_32 FILLER_16_358 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_16_392 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_8 FILLER_16_395 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_16_403 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_16_412 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_16_426 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_16_436 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_16_446 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_16_460 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_16_463 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_16_469 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_16_476 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_16 FILLER_16_480 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_8 FILLER_16_496 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_16_504 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_16_508 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_17_2 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_32 FILLER_17_7 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_17_39 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_17_43 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_17_52 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_17_60 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_17_70 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_17_73 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_8 FILLER_17_76 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_17_84 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_17_88 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_17_98 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_17_126 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_8 FILLER_17_130 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_17_138 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_17_144 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_17_179 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_8 FILLER_17_191 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_17_199 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_17_203 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_17_209 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_17_215 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_17_219 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_17_223 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_17_227 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_17_231 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_8 FILLER_17_262 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_17_270 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_17_274 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_17_283 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_17_286 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_17_319 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_17_331 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_8 FILLER_17_346 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_17_354 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_17_357 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_17_364 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_17_374 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_8 FILLER_17_399 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_17_407 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_17_411 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_17_414 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_17_422 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_17_428 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_17_439 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_17_443 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_17_447 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_17_451 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_17_459 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_17_466 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_17_470 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_16 FILLER_17_474 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_17_490 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_17_494 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_17_496 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_17_499 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_17_503 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_17_508 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_18_2 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_16 FILLER_18_7 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_8 FILLER_18_23 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_18_31 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_18_34 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_18_37 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_18_44 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_16 FILLER_18_48 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_18_64 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_18_66 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_18_75 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_8 FILLER_18_83 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_18_91 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_18_95 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_18_105 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_18_108 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_8 FILLER_18_115 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_18_123 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_18_127 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_18_131 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_18_164 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_18_172 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_18_176 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_18_179 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_18_188 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_18_192 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_18_196 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_18_200 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_18_207 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_18_211 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_18_222 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_18_226 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_18_230 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_18_232 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_18_235 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_18_243 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_18_247 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_16 FILLER_18_250 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_18_266 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_18_270 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_18_277 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_18_281 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_18_283 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_18_290 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_16 FILLER_18_294 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_8 FILLER_18_310 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_18_318 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_18_321 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_18_324 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_18_328 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_18_336 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_8 FILLER_18_340 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_18_348 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_8 FILLER_18_355 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_18_363 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_8 FILLER_18_376 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_18_384 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_18_388 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_8 FILLER_18_392 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_18_400 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_18_402 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_18_405 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_18_417 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_18_425 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_18_431 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_18_435 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_18_439 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_18_443 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_18_447 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_18_451 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_18_455 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_18_457 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_18_460 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_18_463 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_32 FILLER_18_474 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_18_506 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_18_508 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_19_2 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_19_32 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_16 FILLER_19_47 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_8 FILLER_19_63 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_16 FILLER_19_73 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_19_89 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_19_95 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_19_105 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_19_136 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_19_140 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_16 FILLER_19_144 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_19_160 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_19_163 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_19_173 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_19_179 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_19_207 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_19_211 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_19_215 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_19_228 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_19_232 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_19_236 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_19_247 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_19_251 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_8 FILLER_19_255 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_19_263 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_19_265 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_19_268 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_19_278 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_19_282 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_19_286 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_19_290 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_19_292 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_19_322 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_16 FILLER_19_326 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_8 FILLER_19_342 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_19_350 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_19_354 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_19_357 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_19_361 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_19_368 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_19_393 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_19_397 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_19_399 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_19_408 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_19_418 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_19_422 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_19_428 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_19_439 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_19_443 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_19_447 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_19_458 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_19_470 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_19_477 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_19_483 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_8 FILLER_19_487 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_19_495 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_8 FILLER_19_499 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_19_507 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_32 FILLER_20_2 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_20_34 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_20_37 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_20_39 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_20_48 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_20_58 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_16 FILLER_20_62 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_20_78 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_20_82 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_20_90 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_20_103 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_20_105 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_20_108 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_20_115 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_20_123 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_20_125 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_20_128 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_20_159 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_20_169 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_20_173 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_8 FILLER_20_179 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_20_187 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_20_220 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_20_224 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_20_233 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_20_237 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_20_239 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_20_242 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_20_246 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_20_250 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_20_255 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_8 FILLER_20_259 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_20_269 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_20_283 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_20_293 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_16 FILLER_20_297 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_20_313 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_20_317 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_8 FILLER_20_321 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_20_329 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_20_362 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_20_369 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_20_373 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_8 FILLER_20_380 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_20_388 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_8 FILLER_20_392 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_20_402 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_20_414 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_20_416 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_20_425 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_20_439 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_20_443 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_20_447 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_20_460 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_20_463 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_20_473 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_20_481 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_20_485 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_16 FILLER_20_489 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_20_505 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_8 FILLER_21_2 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_21_10 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_21_14 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_21_45 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_21_55 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_21_70 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_21_73 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_21_77 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_21_86 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_21_96 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_21_124 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_8 FILLER_21_128 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_21_136 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_21_140 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_16 FILLER_21_144 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_21_160 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_21_169 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_21_175 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_21_179 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_21_191 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_21_193 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_21_207 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_21_211 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_21_215 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_21_219 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_21_222 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_21_226 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_21_228 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_21_240 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_21_271 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_21_281 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_21_283 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_21_286 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_21_316 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_21_320 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_21_327 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_21_342 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_21_348 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_21_352 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_21_354 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_21_357 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_21_362 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_8 FILLER_21_366 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_21_374 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_21_407 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_21_411 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_21_415 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_21_425 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_21_428 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_21_439 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_21_443 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_21_447 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_21_461 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_21_471 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_21_475 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_16 FILLER_21_479 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_21_495 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_8 FILLER_21_499 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_21_507 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_32 FILLER_22_2 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_22_34 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_8 FILLER_22_37 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_8 FILLER_22_47 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_22_55 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_8 FILLER_22_58 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_22_66 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_22_72 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_8 FILLER_22_76 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_22_84 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_22_90 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_22_100 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_22_104 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_22_108 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_22_111 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_32 FILLER_22_115 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_22_147 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_22_151 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_22_160 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_22_164 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_22_168 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_22_170 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_22_176 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_22_179 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_22_181 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_22_188 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_22_190 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_22_195 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_22_223 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_22_227 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_22_231 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_22_239 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_22_243 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_22_247 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_16 FILLER_22_250 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_22_266 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_22_270 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_32 FILLER_22_273 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_8 FILLER_22_305 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_22_313 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_22_317 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_22_321 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_22_325 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_22_329 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_22_337 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_22_365 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_22_385 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_22_389 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_22_392 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_22_396 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_22_400 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_22_428 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_22_440 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_22_444 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_22_448 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_22_452 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_22_456 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_22_460 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_22_463 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_16 FILLER_22_493 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_23_2 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_16 FILLER_23_7 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_23_23 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_23_27 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_23_37 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_23_41 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_23_45 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_23_47 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_23_56 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_23_64 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_23_68 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_23_70 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_23_73 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_23_77 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_23_108 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_23_139 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_23_141 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_23_144 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_23_150 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_23_160 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_23_164 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_23_167 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_23_169 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_23_176 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_23_185 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_23_189 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_23_202 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_23_209 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_23_215 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_8 FILLER_23_218 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_23_226 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_23_235 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_23_239 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_23_251 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_16 FILLER_23_255 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_8 FILLER_23_271 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_23_281 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_23_283 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_16 FILLER_23_286 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_23_331 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_23_335 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_23_339 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_23_349 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_23_353 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_23_357 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_23_366 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_23_368 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_16 FILLER_23_398 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_8 FILLER_23_414 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_23_422 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_23_425 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_23_428 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_23_437 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_23_441 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_23_444 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_16 FILLER_23_475 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_23_491 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_23_495 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_8 FILLER_23_499 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_23_507 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_24_2 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_24_32 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_24_34 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_24_37 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_24_44 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_24_75 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_24_85 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_8 FILLER_24_93 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_24_101 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_24_105 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_24_108 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_24_115 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_16 FILLER_24_119 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_24_135 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_24_145 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_24_155 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_24_165 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_24_169 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_24_176 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_24_179 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_24_181 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_24_184 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_24_194 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_24_202 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_24_210 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_24_216 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_24_247 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_8 FILLER_24_250 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_24_258 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_8 FILLER_24_262 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_24_276 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_24_280 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_8 FILLER_24_310 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_24_318 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_24_321 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_24_328 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_24_342 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_24_350 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_24_354 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_24_369 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_8 FILLER_24_379 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_24_387 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_24_389 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_8 FILLER_24_392 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_24_400 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_24_404 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_24_415 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_8 FILLER_24_419 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_24_427 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_24_437 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_16 FILLER_24_441 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_24_457 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_32 FILLER_24_463 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_8 FILLER_24_495 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_24_503 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_24_507 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_25_2 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_16 FILLER_25_7 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_25_23 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_25_35 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_25_39 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_25_43 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_25_47 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_8 FILLER_25_56 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_25_64 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_25_70 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_25_73 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_32 FILLER_25_106 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_25_138 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_25_144 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_25_148 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_25_158 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_25_164 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_25_168 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_25_170 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_25_176 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_8 FILLER_25_183 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_25_191 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_25_193 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_25_196 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_25_200 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_25_204 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_25_208 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_25_212 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_25_215 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_25_222 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_25_224 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_16 FILLER_25_233 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_25_249 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_25_252 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_25_283 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_16 FILLER_25_286 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_25_302 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_25_314 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_25_318 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_25_322 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_25_324 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_25_354 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_25_357 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_16 FILLER_25_360 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_8 FILLER_25_376 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_25_413 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_25_425 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_25_428 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_8 FILLER_25_458 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_25_466 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_16 FILLER_25_477 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_25_493 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_25_499 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_25_503 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_25_508 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_16 FILLER_26_2 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_8 FILLER_26_18 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_26_26 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_26_34 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_26_37 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_26_46 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_26_50 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_26_52 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_16 FILLER_26_55 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_26_71 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_26_82 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_26_88 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_26_92 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_26_102 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_26_108 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_26_112 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_26_114 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_26_117 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_26_148 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_26_150 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_26_153 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_26_161 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_26_169 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_26_175 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_26_179 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_26_182 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_26_186 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_26_188 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_26_194 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_26_198 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_26_202 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_26_233 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_8 FILLER_26_237 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_26_245 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_26_247 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_26_250 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_26_260 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_26_270 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_26_278 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_26_309 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_26_311 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_26_317 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_26_321 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_26_359 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_16 FILLER_26_363 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_8 FILLER_26_379 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_26_387 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_26_389 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_16 FILLER_26_392 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_26_408 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_26_412 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_8 FILLER_26_415 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_26_423 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_32 FILLER_26_429 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_26_463 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_26_467 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_26_469 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_26_481 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_16 FILLER_26_489 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_26_505 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_27_2 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_27_32 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_27_42 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_27_44 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_27_53 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_27_57 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_27_62 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_27_70 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_27_73 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_16 FILLER_27_114 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_8 FILLER_27_130 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_27_138 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_27_144 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_27_148 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_27_158 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_27_166 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_27_176 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_27_188 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_27_190 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_8 FILLER_27_197 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_27_205 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_27_209 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_27_212 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_27_215 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_27_224 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_27_236 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_27_238 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_27_241 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_27_245 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_27_255 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_27_263 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_27_267 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_27_269 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_27_272 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_27_276 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_27_280 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_32 FILLER_27_286 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_8 FILLER_27_318 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_16 FILLER_27_332 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_27_348 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_27_354 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_27_357 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_27_359 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_27_389 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_16 FILLER_27_393 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_8 FILLER_27_409 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_27_417 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_27_421 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_27_424 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_27_428 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_27_431 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_27_433 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_27_436 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_27_467 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_27_471 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_27_479 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_8 FILLER_27_485 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_27_493 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_8 FILLER_27_499 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_27_507 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_28_2 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_16 FILLER_28_7 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_8 FILLER_28_23 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_28_31 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_28_34 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_28_37 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_28_67 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_28_81 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_28_85 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_8 FILLER_28_95 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_28_103 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_28_105 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_8 FILLER_28_108 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_28_118 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_28_149 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_28_153 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_28_163 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_28_173 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_28_179 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_28_188 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_28_192 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_8 FILLER_28_202 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_28_210 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_28_214 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_28_245 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_28_247 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_28_250 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_28_252 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_28_261 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_28_265 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_28_273 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_28_277 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_28_281 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_8 FILLER_28_291 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_28_299 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_28_303 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_28_305 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_28_318 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_28_321 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_28_324 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_28_328 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_28_330 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_28_360 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_28_364 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_28_368 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_28_370 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_28_373 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_28_377 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_28_387 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_28_389 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_28_392 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_28_422 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_8 FILLER_28_453 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_32 FILLER_28_463 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_8 FILLER_28_495 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_28_503 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_28_507 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_32 FILLER_29_2 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_8 FILLER_29_34 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_29_42 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_29_44 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_16 FILLER_29_51 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_29_69 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_29_73 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_29_80 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_29_88 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_29_121 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_8 FILLER_29_125 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_29_133 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_29_137 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_29_141 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_29_144 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_29_174 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_29_176 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_29_179 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_29_212 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_29_215 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_29_218 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_29_222 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_29_224 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_8 FILLER_29_233 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_29_241 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_29_244 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_8 FILLER_29_275 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_29_283 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_29_286 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_29_316 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_29_347 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_29_351 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_29_357 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_29_387 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_29_393 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_29_397 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_29_425 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_29_428 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_16 FILLER_29_431 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_29_449 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_16 FILLER_29_480 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_29_496 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_8 FILLER_29_499 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_29_507 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_30_2 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_16 FILLER_30_7 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_8 FILLER_30_23 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_30_31 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_16 FILLER_30_37 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_8 FILLER_30_53 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_30_90 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_30_94 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_30_98 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_30_102 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_30_108 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_32 FILLER_30_138 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_30_170 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_30_174 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_30_176 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_32 FILLER_30_179 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_16 FILLER_30_211 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_8 FILLER_30_227 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_30_235 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_30_239 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_30_247 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_30_250 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_30_252 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_30_261 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_30_271 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_30_302 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_30_314 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_30_318 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_30_321 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_8 FILLER_30_324 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_30_332 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_30_334 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_30_337 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_16 FILLER_30_365 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_30_381 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_30_385 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_30_389 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_30_392 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_30_401 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_30_405 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_30_409 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_30_416 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_30_424 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_30_455 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_30_459 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_32 FILLER_30_463 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_8 FILLER_30_495 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_30_503 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_30_507 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_16 FILLER_31_2 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_31_18 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_31_22 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_31_53 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_8 FILLER_31_57 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_31_65 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_31_69 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_16 FILLER_31_73 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_31_89 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_31_91 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_31_100 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_31_110 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_31_118 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_16 FILLER_31_122 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_31_138 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_16 FILLER_31_144 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_31_160 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_31_162 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_31_171 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_31_175 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_31_177 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_16 FILLER_31_184 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_8 FILLER_31_200 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_31_208 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_31_212 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_31_215 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_32 FILLER_31_218 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_8 FILLER_31_250 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_31_258 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_31_260 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_31_263 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_31_267 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_8 FILLER_31_273 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_31_281 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_31_283 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_16 FILLER_31_286 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_31_302 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_31_305 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_8 FILLER_31_309 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_31_317 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_31_323 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_31_327 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_8 FILLER_31_334 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_31_342 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_31_346 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_31_350 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_31_354 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_31_357 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_31_388 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_31_419 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_31_423 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_31_425 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_8 FILLER_31_428 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_31_436 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_31_448 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_16 FILLER_31_479 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_31_495 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_8 FILLER_31_499 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_31_507 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_32 FILLER_32_2 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_32_34 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_32_37 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_32_47 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_8 FILLER_32_51 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_32_59 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_32_61 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_32_91 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_32_95 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_32_99 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_32_102 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_32 FILLER_32_108 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_8 FILLER_32_140 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_32_148 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_32_152 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_32_155 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_32_159 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_32_176 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_32_179 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_32_183 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_32_214 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_32_247 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_32_250 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_32_261 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_32_269 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_32_276 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_16 FILLER_32_280 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_32_296 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_32_299 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_32_303 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_32_305 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_32_314 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_32_318 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_32_321 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_8 FILLER_32_335 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_32_343 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_32_373 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_8 FILLER_32_377 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_32_385 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_32_389 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_32_392 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_16 FILLER_32_395 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_32_411 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_32_442 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_32_446 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_32_448 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_32_451 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_32_455 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_32_459 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_32 FILLER_32_463 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_32_495 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_32_505 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_33_2 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_33_7 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_33_9 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_33_18 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_33_22 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_16 FILLER_33_26 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_33_42 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_16 FILLER_33_47 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_8 FILLER_33_63 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_33_73 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_33_82 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_33_84 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_33_87 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_33_97 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_33_101 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_33_105 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_16 FILLER_33_113 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_33_129 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_33_133 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_33_141 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_33_144 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_33_153 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_33_157 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_33_166 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_33_183 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_16 FILLER_33_191 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_33_207 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_33_211 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_33_215 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_16 FILLER_33_218 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_8 FILLER_33_234 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_33_242 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_33_246 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_33_249 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_33_262 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_33_272 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_33_279 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_33_283 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_33_286 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_33_293 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_33_295 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_33_301 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_33_305 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_33_317 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_33_327 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_33_335 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_33_339 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_8 FILLER_33_343 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_33_351 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_16 FILLER_33_357 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_33_373 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_33_403 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_33_407 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_33_411 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_33_415 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_33_421 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_33_425 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_8 FILLER_33_428 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_33_436 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_33_440 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_33_443 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_33_451 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_8 FILLER_33_482 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_33_490 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_33_494 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_33_496 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_33_499 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_33_501 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_33_508 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_34_2 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_34_32 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_34_34 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_34_37 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_34_40 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_34_53 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_8 FILLER_34_59 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_34_67 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_34_71 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_34_75 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_34_85 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_34_98 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_34_102 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_34_108 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_34_119 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_34_123 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_34_125 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_34_155 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_8 FILLER_34_159 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_34_167 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_34_169 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_34_175 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_34_179 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_34_183 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_34_193 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_34_195 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_34_198 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_34_229 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_34_239 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_34_243 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_34_247 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_34_250 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_34_301 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_34_311 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_34_318 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_34_321 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_34_324 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_34_328 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_34_358 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_16 FILLER_34_362 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_8 FILLER_34_378 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_34_386 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_34_392 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_34_398 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_34_405 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_34_409 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_34_423 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_16 FILLER_34_427 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_8 FILLER_34_443 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_8 FILLER_34_453 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_16 FILLER_34_463 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_34_479 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_34_483 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_8 FILLER_34_493 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_34_501 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_34_505 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_34_508 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_35_2 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_35_6 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_8 FILLER_35_14 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_35_22 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_35_26 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_35_31 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_35_42 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_35_55 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_35_65 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_35_69 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_35_73 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_35_85 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_35_91 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_35_95 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_35_97 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_35_100 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_8 FILLER_35_131 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_35_139 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_35_141 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_8 FILLER_35_144 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_35_152 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_35_156 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_35_160 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_35_164 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_35_177 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_8 FILLER_35_183 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_35_191 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_35_205 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_35_209 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_35_215 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_8 FILLER_35_218 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_35_226 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_35_230 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_35_243 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_35_249 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_35_251 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_35_256 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_35_262 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_35_277 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_35_281 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_35_283 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_35_286 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_35_302 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_35_310 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_35_318 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_8 FILLER_35_322 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_35_330 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_35_334 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_35_336 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_35_343 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_8 FILLER_35_347 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_32 FILLER_35_357 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_35_389 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_35_392 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_35_404 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_35_408 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_35_418 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_35_425 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_35_428 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_35_431 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_35_433 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_32 FILLER_35_436 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_8 FILLER_35_468 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_35_476 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_35_480 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_35_483 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_35_493 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_8 FILLER_35_499 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_35_507 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_36_2 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_8 FILLER_36_17 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_36_25 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_36_34 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_36_37 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_36_41 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_36_53 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_8 FILLER_36_60 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_36_68 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_36_72 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_36_76 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_36_87 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_36_97 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_36_105 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_16 FILLER_36_108 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_36_124 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_36_126 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_36_156 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_36_158 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_36_161 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_36_175 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_36_179 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_36_185 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_36_191 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_36_199 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_36_230 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_36_234 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_36_244 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_36_250 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_36_256 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_32 FILLER_36_260 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_36_292 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_36_296 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_36_306 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_36_312 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_36_316 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_36_318 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_8 FILLER_36_321 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_36_329 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_36_335 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_36_345 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_36_376 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_36_380 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_36_382 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_36_389 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_36_392 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_36_395 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_36_399 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_36_407 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_36_411 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_36_415 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_36_424 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_36_434 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_36_444 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_36_448 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_8 FILLER_36_452 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_36_460 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_32 FILLER_36_463 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_36_495 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_36_503 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_36_507 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_37_2 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_37_32 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_37_36 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_37_40 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_8 FILLER_37_50 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_37_58 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_37_62 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_37_66 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_37_70 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_37_73 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_37_77 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_37_89 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_37_117 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_37_121 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_37_125 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_37_128 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_37_135 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_37_139 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_37_141 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_8 FILLER_37_144 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_37_152 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_37_158 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_37_189 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_37_193 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_37_195 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_37_204 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_37_210 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_37_212 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_37_215 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_16 FILLER_37_218 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_37_234 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_37_238 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_37_242 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_37_252 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_37_283 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_37_286 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_16 FILLER_37_289 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_8 FILLER_37_305 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_37_313 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_37_331 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_37_346 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_37_354 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_37_357 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_37_363 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_37_367 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_37_400 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_37_410 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_37_417 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_37_421 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_37_425 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_37_428 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_37_438 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_37_448 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_16 FILLER_37_481 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_8 FILLER_37_499 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_37_507 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_38_2 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_38_6 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_38_8 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_16 FILLER_38_15 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_38_31 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_38_37 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_38_41 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_38_53 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_38_57 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_38_59 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_38_64 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_38_66 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_38_75 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_38_88 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_38_92 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_38_95 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_38_105 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_38_108 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_38_138 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_16 FILLER_38_142 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_38_158 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_38_165 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_38_172 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_38_176 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_38_179 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_38_181 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_38_208 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_8 FILLER_38_212 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_38_224 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_38_226 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_38_229 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_38_233 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_38_247 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_38_250 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_16 FILLER_38_269 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_38_285 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_38_318 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_38_321 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_38_326 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_38_330 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_8 FILLER_38_333 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_38_353 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_16 FILLER_38_357 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_8 FILLER_38_373 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_38_381 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_38_383 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_38_389 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_38_392 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_38_396 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_38_400 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_38_407 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_38_411 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_8 FILLER_38_415 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_38_423 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_38_427 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_38_429 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_38_441 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_38_451 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_38_455 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_38_459 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_38_463 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_32 FILLER_38_472 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_38_504 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_38_508 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_39_2 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_39_35 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_39_39 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_39_43 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_39_45 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_39_62 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_39_68 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_39_70 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_39_73 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_8 FILLER_39_86 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_39_120 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_39_124 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_39_126 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_39_129 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_39_133 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_39_141 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_39_144 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_39_153 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_32 FILLER_39_157 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_39_189 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_39_193 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_39_205 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_39_209 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_39_212 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_39_215 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_39_245 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_39_273 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_39_283 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_39_286 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_8 FILLER_39_297 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_39_305 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_39_316 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_39_320 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_39_322 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_39_328 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_39_332 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_8 FILLER_39_336 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_39_344 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_39_348 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_39_352 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_39_354 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_32 FILLER_39_357 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_8 FILLER_39_389 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_39_397 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_39_401 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_39_403 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_39_406 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_39_412 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_39_423 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_39_425 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_39_428 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_39_438 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_39_444 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_39_448 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_39_456 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_8 FILLER_39_487 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_39_495 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_8 FILLER_39_499 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_39_507 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_32 FILLER_40_2 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_40_34 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_40_37 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_40_46 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_16 FILLER_40_50 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_40_66 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_40_70 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_40_80 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_16 FILLER_40_90 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_40_108 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_40_117 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_40_127 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_40_158 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_40_172 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_40_176 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_40_179 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_40_209 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_40_213 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_40_217 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_40_227 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_40_237 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_40_243 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_40_247 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_40_250 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_40_298 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_40_302 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_40_313 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_40_315 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_40_318 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_40_321 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_40_324 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_40_334 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_40_346 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_40_379 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_40_383 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_40_389 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_40_392 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_40_400 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_40_404 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_40_410 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_40_414 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_40_416 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_40_427 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_40_439 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_40_449 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_40_453 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_40_455 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_40_458 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_40_460 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_32 FILLER_40_463 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_8 FILLER_40_495 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_40_503 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_40_507 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_32 FILLER_41_2 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_41_34 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_41_36 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_41_45 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_41_47 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_8 FILLER_41_56 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_41_64 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_41_68 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_41_70 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_41_73 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_41_77 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_41_79 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_8 FILLER_41_82 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_41_90 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_41_94 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_41_96 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_41_126 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_8 FILLER_41_130 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_41_138 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_41_141 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_41_144 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_41_146 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_41_155 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_41_157 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_41_160 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_41_164 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_41_197 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_41_207 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_41_211 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_41_215 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_8 FILLER_41_218 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_41_226 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_8 FILLER_41_229 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_41_237 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_41_243 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_41_247 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_41_251 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_41_265 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_41_274 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_41_283 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_41_286 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_41_293 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_41_300 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_41_302 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_41_314 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_41_318 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_41_320 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_41_326 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_41_354 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_41_357 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_41_360 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_41_364 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_41_397 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_41_409 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_41_411 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_41_416 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_41_425 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_41_428 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_41_431 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_41_435 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_8 FILLER_41_449 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_41_457 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_41_461 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_32 FILLER_41_464 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_41_496 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_41_499 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_41_503 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_41_508 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_16 FILLER_42_2 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_8 FILLER_42_18 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_42_34 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_42_37 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_42_39 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_42_48 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_42_58 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_42_66 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_42_97 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_42_101 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_42_105 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_42_108 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_32 FILLER_42_113 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_8 FILLER_42_145 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_42_153 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_42_157 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_42_171 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_42_175 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_42_179 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_42_186 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_42_190 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_42_194 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_42_196 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_16 FILLER_42_199 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_42_220 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_42_224 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_42_228 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_42_232 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_42_242 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_42_246 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_42_250 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_42_254 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_42_269 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_42_273 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_42_284 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_42_288 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_42_292 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_42_296 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_42_300 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_42_304 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_42_312 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_42_316 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_42_318 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_42_321 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_42_324 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_42_326 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_42_337 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_42_351 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_42_355 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_42_359 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_42_363 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_42_365 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_16 FILLER_42_368 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_42_384 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_42_386 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_42_389 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_42_392 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_42_401 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_42_405 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_42_409 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_42_413 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_42_419 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_42_423 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_42_427 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_8 FILLER_42_437 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_42_445 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_42_447 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_42_450 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_42_460 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_42_463 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_16 FILLER_42_493 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_8 FILLER_43_2 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_43_39 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_43_70 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_43_73 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_32 FILLER_43_76 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_16 FILLER_43_108 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_43_124 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_43_128 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_43_136 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_43_140 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_43_144 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_43_153 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_43_157 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_43_161 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_43_163 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_32 FILLER_43_166 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_43_200 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_43_204 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_43_208 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_43_212 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_43_215 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_43_222 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_43_229 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_43_233 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_43_239 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_43_258 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_43_262 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_43_271 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_43_283 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_43_286 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_43_294 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_43_298 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_43_308 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_43_314 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_43_318 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_43_324 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_43_333 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_43_342 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_43_349 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_43_353 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_43_357 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_16 FILLER_43_360 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_43_376 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_43_380 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_43_383 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_8 FILLER_43_393 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_43_401 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_43_404 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_43_408 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_43_419 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_43_425 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_43_428 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_43_447 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_43_449 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_43_452 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_32 FILLER_43_464 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_43_496 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_43_499 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_43_503 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_43_508 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_32 FILLER_44_2 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_44_34 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_44_37 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_64 FILLER_44_41 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_44_105 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_8 FILLER_44_108 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_44_116 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_44_119 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_44_150 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_44_154 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_44_165 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_44_171 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_44_175 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_44_179 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_44_206 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_44_218 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_44_224 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_44_226 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_44_246 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_44_250 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_44_259 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_44_268 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_44_270 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_44_273 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_44_282 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_44_286 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_44_288 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_44_318 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_44_321 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_44_324 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_44_328 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_44_362 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_16 FILLER_44_366 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_8 FILLER_44_382 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_44_392 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_44_396 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_44_399 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_44_408 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_8 FILLER_44_436 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_44_452 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_44_456 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_44_460 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_32 FILLER_44_463 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_8 FILLER_44_495 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_44_503 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_44_507 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_64 FILLER_45_2 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_45_66 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_45_70 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_64 FILLER_45_73 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_45_137 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_45_141 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_8 FILLER_45_144 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_45_164 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_45_173 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_45_189 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_45_195 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_45_199 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_45_212 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_45_215 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_45_226 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_45_236 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_45_246 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_45_250 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_16 FILLER_45_254 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_45_270 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_45_277 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_45_279 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_45_282 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_45_286 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_45_290 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_45_293 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_45_297 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_45_299 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_45_305 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_45_309 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_45_313 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_45_323 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_45_351 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_45_357 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_45_360 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_45_362 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_45_371 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_45_375 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_45_408 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_45_410 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_45_421 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_45_425 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_45_428 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_45_437 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_45_441 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_45_451 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_8 FILLER_45_482 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_45_490 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_45_494 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_45_496 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_8 FILLER_45_499 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_45_507 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_46_2 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_16 FILLER_46_7 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_8 FILLER_46_23 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_46_31 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_64 FILLER_46_37 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_46_101 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_46_105 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_32 FILLER_46_108 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_46_140 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_46_144 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_46_146 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_46_149 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_46_153 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_46_160 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_46_176 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_46_179 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_46_182 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_46_213 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_46_217 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_46_219 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_46_226 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_46_230 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_46_234 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_46_241 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_46_245 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_46_247 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_46_250 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_46_280 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_46_291 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_46_301 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_46_305 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_46_309 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_46_311 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_46_314 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_46_318 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_46_321 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_46_328 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_46_341 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_46_372 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_8 FILLER_46_382 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_16 FILLER_46_392 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_46_410 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_46_414 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_46_418 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_46_426 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_46_430 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_46_434 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_46_441 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_46_443 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_46_446 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_46_456 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_46_460 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_32 FILLER_46_463 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_8 FILLER_46_495 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_46_503 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_46_508 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_64 FILLER_47_2 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_47_66 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_47_70 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_64 FILLER_47_73 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_47_137 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_47_141 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_47_144 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_47_153 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_47_163 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_47_170 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_8 FILLER_47_179 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_47_193 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_16 FILLER_47_197 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_47_215 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_47_218 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_47_222 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_47_226 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_47_233 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_47_261 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_47_277 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_47_283 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_47_286 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_8 FILLER_47_290 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_47_298 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_47_330 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_47_334 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_47_338 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_47_342 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_47_346 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_47_350 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_47_354 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_47_357 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_47_360 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_47_364 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_47_366 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_47_369 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_47_377 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_47_387 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_16 FILLER_47_391 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_47_407 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_47_411 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_47_414 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_47_418 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_47_425 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_47_428 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_47_437 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_47_441 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_47_445 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_47_448 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_47_452 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_32 FILLER_47_461 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_47_493 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_8 FILLER_47_499 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_47_507 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_32 FILLER_48_2 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_48_34 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_64 FILLER_48_37 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_48_101 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_48_105 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_48_108 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_48_112 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_48_116 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_48_147 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_48_151 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_48_160 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_48_162 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_48_165 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_48_169 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_48_172 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_48_176 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_16 FILLER_48_179 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_48_195 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_8 FILLER_48_198 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_48_206 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_48_210 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_48_214 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_16 FILLER_48_218 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_48_234 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_8 FILLER_48_237 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_48_245 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_48_247 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_48_250 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_48_257 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_48_263 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_48_267 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_48_277 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_48_287 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_48_289 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_48_303 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_8 FILLER_48_311 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_48_321 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_48_351 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_48_382 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_48_386 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_48_392 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_48_395 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_48_403 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_48_407 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_48_437 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_8 FILLER_48_441 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_48_449 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_8 FILLER_48_453 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_32 FILLER_48_463 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_8 FILLER_48_495 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_48_503 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_48_507 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_64 FILLER_49_2 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_49_66 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_49_70 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_64 FILLER_49_73 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_49_137 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_49_141 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_49_144 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_49_153 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_49_157 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_49_161 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_49_166 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_8 FILLER_49_170 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_49_178 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_49_182 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_49_212 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_49_215 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_49_217 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_16 FILLER_49_247 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_49_263 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_49_267 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_49_271 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_49_280 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_49_286 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_8 FILLER_49_289 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_49_297 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_49_301 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_16 FILLER_49_305 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_49_321 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_49_323 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_49_326 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_49_354 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_49_357 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_49_366 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_49_370 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_8 FILLER_49_374 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_49_382 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_49_415 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_49_419 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_49_425 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_49_428 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_49_432 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_32 FILLER_49_463 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_49_495 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_49_499 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_49_503 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_49_508 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_32 FILLER_50_2 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_50_34 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_64 FILLER_50_37 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_50_101 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_50_105 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_32 FILLER_50_108 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_8 FILLER_50_140 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_50_148 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_50_152 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_50_165 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_50_169 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_50_173 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_50_176 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_50_179 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_50_181 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_50_194 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_50_206 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_50_213 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_50_217 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_50_221 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_50_225 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_50_232 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_50_244 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_50_250 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_8 FILLER_50_253 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_50_261 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_50_271 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_50_275 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_50_282 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_50_286 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_16 FILLER_50_290 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_50_306 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_50_310 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_50_316 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_50_318 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_50_321 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_50_324 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_50_328 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_50_330 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_50_339 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_50_349 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_50_358 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_50_365 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_50_369 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_50_373 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_50_377 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_50_381 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_50_385 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_50_389 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_50_392 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_50_402 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_50_430 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_50_440 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_50_448 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_50_452 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_50_456 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_50_460 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_50_463 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_16 FILLER_50_472 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_50_488 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_50_492 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_50_495 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_50_503 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_50_507 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_64 FILLER_51_2 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_51_66 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_51_70 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_64 FILLER_51_73 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_51_137 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_51_141 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_8 FILLER_51_144 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_51_152 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_51_159 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_51_167 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_51_177 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_51_186 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_51_188 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_51_195 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_51_212 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_51_215 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_51_218 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_51_224 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_51_228 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_51_232 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_51_242 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_51_252 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_51_283 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_51_286 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_51_316 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_51_326 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_51_330 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_51_340 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_51_350 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_51_354 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_51_357 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_51_368 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_51_372 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_51_376 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_51_408 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_51_422 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_51_428 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_51_431 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_51_442 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_51_450 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_51_454 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_8 FILLER_51_485 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_51_493 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_8 FILLER_51_499 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_51_507 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_52_2 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_52_17 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_8 FILLER_52_21 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_52_29 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_52_33 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_64 FILLER_52_37 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_52_101 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_52_105 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_16 FILLER_52_108 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_8 FILLER_52_124 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_52_132 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_52_136 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_52_166 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_52_170 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_52_176 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_52_179 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_52_188 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_52_192 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_52_194 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_52_197 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_52_230 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_52_240 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_52_244 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_52_247 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_52_250 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_52_257 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_52_261 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_16 FILLER_52_265 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_52_281 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_8 FILLER_52_285 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_52_293 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_52_305 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_52_315 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_52_321 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_52_324 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_52_326 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_52_353 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_52_388 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_52_392 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_52_401 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_52_405 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_52_409 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_52_413 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_52_417 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_52_419 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_52_422 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_52_426 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_52_438 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_52_442 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_52_444 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_52_450 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_52_460 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_52_463 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_52_472 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_52_476 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_8 FILLER_52_480 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_52_488 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_52_492 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_52_508 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_64 FILLER_53_2 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_53_66 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_53_70 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_64 FILLER_53_73 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_53_137 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_53_141 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_16 FILLER_53_144 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_53_160 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_53_164 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_8 FILLER_53_168 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_16 FILLER_53_182 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_53_198 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_8 FILLER_53_201 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_53_209 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_53_215 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_53_217 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_53_220 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_53_230 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_53_236 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_53_246 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_53_248 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_53_251 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_53_261 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_53_265 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_8 FILLER_53_269 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_53_277 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_53_281 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_53_283 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_8 FILLER_53_286 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_53_294 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_53_298 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_53_302 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_53_304 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_53_313 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_53_354 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_53_357 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_53_367 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_53_371 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_53_375 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_53_381 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_53_385 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_53_395 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_53_399 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_16 FILLER_53_403 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_53_419 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_53_425 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_53_428 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_53_440 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_53_444 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_53_450 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_53_454 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_53_463 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_53_473 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_53_477 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_16 FILLER_53_481 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_8 FILLER_53_499 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_53_507 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_32 FILLER_54_2 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_54_34 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_64 FILLER_54_37 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_54_101 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_54_105 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_64 FILLER_54_108 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_54_172 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_54_176 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_54_179 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_54_209 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_8 FILLER_54_213 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_54_234 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_54_246 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_54_250 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_54_252 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_54_263 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_54_267 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_54_300 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_54_312 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_54_314 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_54_317 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_54_321 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_54_330 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_54_332 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_54_337 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_54_344 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_54_353 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_54_359 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_54_363 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_54_367 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_54_371 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_54_375 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_8 FILLER_54_378 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_54_386 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_54_392 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_54_395 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_54_399 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_54_414 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_54_439 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_54_455 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_54_459 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_54_463 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_54_474 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_16 FILLER_54_478 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_8 FILLER_54_494 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_54_502 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_54_508 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_64 FILLER_55_2 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_55_66 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_55_70 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_64 FILLER_55_73 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_55_137 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_55_141 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_64 FILLER_55_144 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_55_208 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_55_212 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_8 FILLER_55_215 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_55_223 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_55_227 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_55_231 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_55_241 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_55_247 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_55_278 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_55_282 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_16 FILLER_55_286 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_55_302 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_55_304 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_55_307 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_55_321 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_55_327 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_55_334 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_55_349 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_55_353 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_55_357 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_55_360 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_55_362 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_55_376 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_55_378 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_55_387 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_55_391 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_55_400 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_55_425 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_55_428 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_55_442 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_55_446 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_55_450 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_55_452 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_55_455 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_8 FILLER_55_486 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_55_494 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_55_496 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_55_499 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_55_503 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_55_505 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_55_508 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_32 FILLER_56_2 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_56_34 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_64 FILLER_56_37 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_56_101 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_56_105 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_64 FILLER_56_108 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_56_172 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_56_176 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_32 FILLER_56_179 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_16 FILLER_56_211 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_8 FILLER_56_227 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_56_235 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_56_239 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_56_243 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_56_247 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_56_250 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_56_253 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_32 FILLER_56_257 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_8 FILLER_56_289 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_56_297 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_56_301 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_56_315 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_56_321 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_56_330 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_56_355 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_16 FILLER_56_371 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_56_387 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_56_389 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_56_392 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_8 FILLER_56_395 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_56_403 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_56_406 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_56_412 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_56_437 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_56_451 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_56_455 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_56_459 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_16 FILLER_56_463 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_8 FILLER_56_479 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_56_487 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_56_491 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_56_493 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_56_508 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_57_2 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_64 FILLER_57_7 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_64 FILLER_57_73 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_57_137 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_57_141 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_64 FILLER_57_144 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_57_208 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_57_212 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_57_215 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_57_219 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_57_222 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_16 FILLER_57_253 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_57_269 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_57_273 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_57_280 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_57_286 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_57_290 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_57_292 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_16 FILLER_57_295 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_8 FILLER_57_311 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_57_319 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_57_322 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_57_326 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_57_329 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_8 FILLER_57_343 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_57_351 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_16 FILLER_57_357 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_57_373 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_57_403 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_57_407 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_57_409 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_57_414 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_57_418 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_57_420 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_57_425 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_57_428 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_57_443 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_8 FILLER_57_447 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_57_455 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_57_459 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_57_461 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_16 FILLER_57_468 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_8 FILLER_57_484 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_57_492 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_57_496 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_8 FILLER_57_499 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_57_507 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_32 FILLER_58_2 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_58_34 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_64 FILLER_58_37 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_58_101 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_58_105 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_64 FILLER_58_108 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_58_172 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_58_176 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_64 FILLER_58_179 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_58_243 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_58_247 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_8 FILLER_58_250 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_58_258 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_58_262 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_58_293 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_58_303 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_58_318 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_58_321 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_58_327 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_58_334 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_58_338 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_58_342 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_58_350 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_58_354 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_16 FILLER_58_364 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_58_380 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_58_389 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_58_392 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_58_399 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_58_403 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_58_408 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_58_412 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_8 FILLER_58_421 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_58_429 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_58_435 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_58_439 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_8 FILLER_58_443 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_58_451 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_58_460 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_58_463 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_16 FILLER_58_493 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_64 FILLER_59_2 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_59_66 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_59_70 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_64 FILLER_59_73 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_59_137 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_59_141 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_64 FILLER_59_144 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_59_208 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_59_212 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_64 FILLER_59_215 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_59_279 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_59_283 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_59_286 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_59_290 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_59_292 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_59_301 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_59_303 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_59_312 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_59_322 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_59_326 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_59_338 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_59_344 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_59_354 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_59_357 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_59_387 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_59_391 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_59_393 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_59_402 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_59_411 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_59_420 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_59_424 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_59_428 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_59_431 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_59_443 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_59_453 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_59_457 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_59_461 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_32 FILLER_59_464 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_59_496 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_8 FILLER_59_499 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_59_507 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_60_2 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_16 FILLER_60_7 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_8 FILLER_60_23 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_60_31 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_64 FILLER_60_37 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_60_101 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_60_105 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_64 FILLER_60_108 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_60_172 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_60_176 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_64 FILLER_60_179 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_60_243 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_60_247 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_16 FILLER_60_250 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_8 FILLER_60_266 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_60_274 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_60_305 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_60_311 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_60_315 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_60_321 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_60_324 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_60_326 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_60_335 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_60_345 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_60_354 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_60_361 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_60_365 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_16 FILLER_60_369 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_60_385 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_60_389 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_60_392 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_60_403 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_60_407 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_60_409 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_60_420 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_60_422 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_60_431 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_60_441 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_60_453 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_60_459 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_32 FILLER_60_463 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_8 FILLER_60_495 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_60_503 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_60_508 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_64 FILLER_61_2 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_61_66 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_61_70 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_64 FILLER_61_73 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_61_137 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_61_141 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_64 FILLER_61_144 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_61_208 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_61_212 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_64 FILLER_61_215 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_61_279 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_61_283 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_8 FILLER_61_286 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_61_294 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_61_296 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_61_326 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_61_338 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_61_342 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_61_353 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_61_357 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_8 FILLER_61_360 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_61_368 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_61_372 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_61_402 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_61_409 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_61_413 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_61_419 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_61_423 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_61_425 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_61_428 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_8 FILLER_61_431 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_61_441 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_16 FILLER_61_472 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_8 FILLER_61_488 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_61_496 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_8 FILLER_61_499 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_61_507 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_32 FILLER_62_2 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_62_34 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_64 FILLER_62_37 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_62_101 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_62_105 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_64 FILLER_62_108 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_62_172 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_62_176 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_64 FILLER_62_179 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_62_243 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_62_247 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_32 FILLER_62_250 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_16 FILLER_62_282 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_8 FILLER_62_298 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_62_308 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_62_315 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_62_321 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_62_325 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_62_328 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_62_332 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_62_334 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_62_340 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_16 FILLER_62_371 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_62_387 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_62_389 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_62_392 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_62_396 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_62_403 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_62_407 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_62_440 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_16 FILLER_62_444 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_62_460 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_32 FILLER_62_463 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_8 FILLER_62_495 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_62_503 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_62_508 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_64 FILLER_63_2 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_63_66 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_63_70 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_64 FILLER_63_73 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_63_137 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_63_141 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_64 FILLER_63_144 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_63_208 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_63_212 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_64 FILLER_63_215 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_63_279 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_63_283 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_32 FILLER_63_286 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_16 FILLER_63_318 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_63_334 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_63_338 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_8 FILLER_63_342 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_63_350 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_63_354 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_64 FILLER_63_357 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_63_421 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_63_425 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_64 FILLER_63_428 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_63_492 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_63_496 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_8 FILLER_63_499 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_63_507 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_32 FILLER_64_2 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_64_34 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_64 FILLER_64_37 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_64_101 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_64_105 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_64 FILLER_64_108 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_64_172 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_64_176 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_64 FILLER_64_179 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_64_243 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_64_247 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_64 FILLER_64_250 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_64_314 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_64_318 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_64 FILLER_64_321 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_64_385 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_64_389 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_64 FILLER_64_392 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_64_456 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_64_460 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_32 FILLER_64_463 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_8 FILLER_64_495 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_64_503 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_64_507 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_64 FILLER_65_2 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_65_66 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_65_70 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_64 FILLER_65_73 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_65_137 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_65_141 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_64 FILLER_65_144 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_65_208 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_65_212 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_64 FILLER_65_215 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_65_279 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_65_283 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_64 FILLER_65_286 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_65_350 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_65_354 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_64 FILLER_65_357 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_65_421 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_65_425 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_64 FILLER_65_428 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_65_492 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_65_496 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_8 FILLER_65_499 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_65_507 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_66_2 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_16 FILLER_66_7 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_8 FILLER_66_23 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_66_31 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_64 FILLER_66_37 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_66_101 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_66_105 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_64 FILLER_66_108 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_66_172 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_66_176 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_64 FILLER_66_179 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_66_243 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_66_247 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_64 FILLER_66_250 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_66_314 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_66_318 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_64 FILLER_66_321 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_66_385 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_66_389 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_64 FILLER_66_392 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_66_456 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_66_460 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_32 FILLER_66_463 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_8 FILLER_66_495 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_66_503 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_66_508 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_67_2 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_67_6 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_67_11 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_8 FILLER_67_17 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_67_29 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_67_33 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_16 FILLER_67_37 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_8 FILLER_67_53 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_67_65 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_67_69 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_67_72 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_67_76 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_67_78 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_8 FILLER_67_83 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_67_91 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_67_95 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_67_101 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_8 FILLER_67_107 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_8 FILLER_67_119 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_67_127 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_67_131 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_67_137 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_67_139 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_32 FILLER_67_142 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_67_174 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_16 FILLER_67_177 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_8 FILLER_67_197 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_67_205 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_67_209 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_67_212 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_16 FILLER_67_217 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_8 FILLER_67_233 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_67_241 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_16 FILLER_67_247 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_67_263 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_8 FILLER_67_269 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_67_277 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_67_279 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_8 FILLER_67_282 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_67_290 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_67_294 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_67_296 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_67_299 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_67_309 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_67_313 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_67_317 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_8 FILLER_67_323 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_67_331 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_67_335 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_67_345 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_67_349 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_8 FILLER_67_352 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_67_360 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_16 FILLER_67_365 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_67_381 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_8 FILLER_67_387 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_67_395 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_8 FILLER_67_401 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_67_409 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_67_413 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_67_419 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_8 FILLER_67_422 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_67_430 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_67_432 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_16 FILLER_67_437 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_67_453 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_32 FILLER_67_457 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_67_489 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_67_492 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fillcap_4 FILLER_67_497 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_2 FILLER_67_501 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_67_503 (.VDD(vdd),
+ .VSS(vss));
+ gf180mcu_fd_sc_mcu7t5v0__fill_1 FILLER_67_508 (.VDD(vdd),
+ .VSS(vss));
+ assign io_oeb[0] = net13;
+ assign io_oeb[10] = net23;
+ assign io_oeb[11] = net24;
+ assign io_oeb[12] = net25;
+ assign io_oeb[13] = net26;
+ assign io_oeb[14] = net27;
+ assign io_oeb[15] = net28;
+ assign io_oeb[16] = net29;
+ assign io_oeb[17] = net30;
+ assign io_oeb[18] = net31;
+ assign io_oeb[19] = net32;
+ assign io_oeb[1] = net14;
+ assign io_oeb[20] = net33;
+ assign io_oeb[21] = net34;
+ assign io_oeb[22] = net35;
+ assign io_oeb[23] = net36;
+ assign io_oeb[24] = net37;
+ assign io_oeb[25] = net38;
+ assign io_oeb[26] = net39;
+ assign io_oeb[27] = net40;
+ assign io_oeb[28] = net41;
+ assign io_oeb[29] = net42;
+ assign io_oeb[2] = net15;
+ assign io_oeb[30] = net43;
+ assign io_oeb[31] = net44;
+ assign io_oeb[32] = net45;
+ assign io_oeb[33] = net46;
+ assign io_oeb[34] = net47;
+ assign io_oeb[35] = net48;
+ assign io_oeb[36] = net49;
+ assign io_oeb[37] = net50;
+ assign io_oeb[3] = net16;
+ assign io_oeb[4] = net17;
+ assign io_oeb[5] = net18;
+ assign io_oeb[6] = net19;
+ assign io_oeb[7] = net20;
+ assign io_oeb[8] = net21;
+ assign io_oeb[9] = net22;
+ assign io_out[0] = net51;
+ assign io_out[10] = net61;
+ assign io_out[19] = net62;
+ assign io_out[1] = net52;
+ assign io_out[20] = net63;
+ assign io_out[21] = net64;
+ assign io_out[22] = net65;
+ assign io_out[23] = net66;
+ assign io_out[24] = net67;
+ assign io_out[25] = net68;
+ assign io_out[26] = net69;
+ assign io_out[27] = net70;
+ assign io_out[28] = net71;
+ assign io_out[29] = net72;
+ assign io_out[2] = net53;
+ assign io_out[30] = net73;
+ assign io_out[31] = net74;
+ assign io_out[32] = net75;
+ assign io_out[33] = net76;
+ assign io_out[34] = net77;
+ assign io_out[35] = net78;
+ assign io_out[36] = net79;
+ assign io_out[37] = net80;
+ assign io_out[3] = net54;
+ assign io_out[4] = net55;
+ assign io_out[5] = net56;
+ assign io_out[6] = net57;
+ assign io_out[7] = net58;
+ assign io_out[8] = net59;
+ assign io_out[9] = net60;
+endmodule
diff --git a/verilog/includes/includes.rtl.caravel_user_project b/verilog/includes/includes.rtl.caravel_user_project
index 31ab09b..6e31100 100644
--- a/verilog/includes/includes.rtl.caravel_user_project
+++ b/verilog/includes/includes.rtl.caravel_user_project
@@ -1,5 +1,5 @@
# Caravel user project includes
-v $(USER_PROJECT_VERILOG)/rtl/user_project_wrapper.v
--v $(USER_PROJECT_VERILOG)/rtl/user_proj_example.v
+-v $(USER_PROJECT_VERILOG)/rtl/wrapped_vga_clock.v
-
\ No newline at end of file
+
diff --git a/verilog/rtl/user_project_wrapper.v b/verilog/rtl/user_project_wrapper.v
index 146877d..7ab691e 100644
--- a/verilog/rtl/user_project_wrapper.v
+++ b/verilog/rtl/user_project_wrapper.v
@@ -69,7 +69,7 @@
/*--------------------------------------*/
/* User project is instantiated here */
/*--------------------------------------*/
-
+/*
user_proj_example mprj (
`ifdef USE_POWER_PINS
.vdd(vdd), // User area 1 1.8V power
@@ -105,7 +105,23 @@
// IRQ
.irq(user_irq)
);
+*/
+wrapped_vga_clock wrapped_vga_clock (
+`ifdef USE_POWER_PINS
+ .vdd(vdd), // User area 1 1.8V power
+ .vss(vss), // User area 1 digital ground
+`endif
+
+ .wb_clk_i(wb_clk_i),
+ .wb_rst_i(wb_rst_i),
+
+ .io_in (io_in),
+ .io_out(io_out),
+ .io_oeb(io_oeb),
+
+);
endmodule // user_project_wrapper
+
`default_nettype wire
diff --git a/verilog/rtl/vga-clock b/verilog/rtl/vga-clock
new file mode 160000
index 0000000..94d7b8b
--- /dev/null
+++ b/verilog/rtl/vga-clock
@@ -0,0 +1 @@
+Subproject commit 94d7b8b5b98ed4509907fc7daea14dee0f13da8e
diff --git a/verilog/rtl/wrapped_vga_clock.v b/verilog/rtl/wrapped_vga_clock.v
new file mode 100644
index 0000000..83d2a6e
--- /dev/null
+++ b/verilog/rtl/wrapped_vga_clock.v
@@ -0,0 +1,38 @@
+`default_nettype none
+// update this to the name of your module
+module wrapped_vga_clock(
+`ifdef USE_POWER_PINS
+ inout vdd, // User area 1 1.8V supply
+ inout vss, // User area 1 digital ground
+`endif
+ // interface as user_proj_example.v
+ input wire wb_clk_i,
+ input wire wb_rst_i,
+
+ // Logic Analyzer Signals
+ // only provide first 32 bits to reduce wiring congestion
+
+ input wire [`MPRJ_IO_PADS-1:0] io_in,
+ output wire [`MPRJ_IO_PADS-1:0] io_out,
+ output wire [`MPRJ_IO_PADS-1:0] io_oeb,
+
+);
+
+ // permanently set oeb so that outputs are always enabled: 0 is output, 1 is high-impedance
+ assign io_oeb = {`MPRJ_IO_PADS{1'b0}};
+
+ wire reset = ! wb_rst_i;
+
+ vga_clock vga_clock(
+ .clk(wb_clk_i),
+ .reset_n(reset),
+ .adj_hrs(io_in[8]),
+ .adj_min(io_in[9]),
+ .adj_sec(io_in[10]),
+ .hsync(io_out[11]),
+ .vsync(io_out[12]),
+ .rrggbb(io_out[18:13])
+ );
+
+endmodule
+`default_nettype wire
