commit | 1aa6a9678d0e5e2b74ba1705010204aef011ccbf | [log] [tgz] |
---|---|---|
author | Jeff DiCorpo <jeffdi@efabless.com> | Mon Jan 02 13:21:36 2023 -0800 |
committer | Jeff DiCorpo <jeffdi@efabless.com> | Mon Jan 02 13:21:36 2023 -0800 |
tree | 58b6173fd43160c68b93eed9eb3622e9fc6fbe6f | |
parent | 2311ae57c4d661cf5405a7f6e352b278b4f3f94b [diff] |
update repo
An award winning CPU design fit into the GF180 MPW0 Shuttle.
To keep the design simple this project places a Serv CPU with a scan-chain around it connecting it's wishbone bus which is a combination of data and instructions out via I/O pins.
Another I/O pin is responsible for handling clock and reset. Operation will run as follows:
In this manner we should be able to implement external peripherals like UARTs, timers, and GPIOs. The external controller can be a microcontroller, FPGA, or the caravel harness SoC.