)]}'
{
  "commit": "dde4a146ec4b0cf129b247202d7eab979fb0f6e4",
  "tree": "dae07a889221fa4e4b85d87fce47ca5b5701c4fe",
  "parents": [
    "04b51ee3d3e8f1258dc60caf4ece37037c4e2965"
  ],
  "author": {
    "name": "Greg Davill",
    "email": "greg.davill@gmail.com",
    "time": "Tue Dec 06 00:53:13 2022 +1030"
  },
  "committer": {
    "name": "Greg Davill",
    "email": "greg.davill@gmail.com",
    "time": "Tue Dec 06 00:53:13 2022 +1030"
  },
  "message": "rtl: Adjust rf_ram_if for single port memory\n\nBump up macro serv_0 size to assist with routing\n",
  "tree_diff": [
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      "new_mode": 33188,
      "new_path": "openlane/serv_0/config.tcl"
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      "old_mode": 33188,
      "old_path": "verilog/rtl/serv_rf_ram_gf180.v",
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      "new_mode": 33188,
      "new_path": "verilog/rtl/serv_rf_ram_gf180.v"
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    {
      "type": "add",
      "old_id": "0000000000000000000000000000000000000000",
      "old_mode": 0,
      "old_path": "/dev/null",
      "new_id": "a23805eef014ef3795a48af4135c1dfb9763dfb9",
      "new_mode": 33188,
      "new_path": "verilog/rtl/serv_rf_spram_if.v"
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}