commit | da29cfe0e6732275435aceb348881a2ff8339034 | [log] [tgz] |
---|---|---|
author | tinybot <bot@tinytapeout.com> | Mon Dec 05 10:03:43 2022 +0000 |
committer | tinybot <bot@tinytapeout.com> | Mon Dec 05 10:03:43 2022 +0000 |
tree | c82183c1c49e2df3597eda655153aae888b0cc5c | |
parent | 3a830709c02b2965ad3822677212a58c79684e70 [diff] |
harden project [skip ci]
An award winning CPU design fit into the GF180 MPW0 Shuttle.
To keep the design simple this project places a Serv CPU with a scan-chain around it connecting it's wishbone bus which is a combination of data and instructions out via I/O pins.
Another I/O pin is responsible for handling clock and reset. Operation will run as follows:
In this manner we should be able to implement external peripherals like UARTs, timers, and GPIOs. The external controller can be a microcontroller, FPGA, or the caravel harness SoC.