| commit | c72fc44389b3d8d0b075e76c391be4e6be84536f | [log] [tgz] |
|---|---|---|
| author | Greg Davill <greg.davill@gmail.com> | Sun Dec 04 18:56:30 2022 +1030 |
| committer | Greg Davill <greg.davill@gmail.com> | Sun Dec 04 18:56:30 2022 +1030 |
| tree | 6fc041bc8aaa84232f71f38d26b5b3b826767d53 | |
| parent | 40ced4acffb548d2cb16d0d549cf83d3be5827bf [diff] |
ci: Create layout image with klayout
An award winning CPU design fit into the GF180 MPW0 Shuttle.
To keep the design simple this project places a Serv CPU with a scan-chain around it connecting it's wishbone bus which is a combination of data and instructions out via I/O pins.
Another I/O pin is responsible for handling clock and reset. Operation will run as follows:
In this manner we should be able to implement external peripherals like UARTs, timers, and GPIOs. The external controller can be a microcontroller, FPGA, or the caravel harness SoC.