commit | 91ddd78fc81e904b4ff1f63cd234433312043c27 | [log] [tgz] |
---|---|---|
author | tinybot <bot@tinytapeout.com> | Sun Dec 04 23:12:50 2022 +0000 |
committer | tinybot <bot@tinytapeout.com> | Sun Dec 04 23:12:50 2022 +0000 |
tree | 8d5057f149fc06fb25ca44e96a31d5672a1c1a0b | |
parent | eb4c6c5d9aff2d1e03df37bd463746a53de7b6eb [diff] |
harden project [skip ci]
An award winning CPU design fit into the GF180 MPW0 Shuttle.
To keep the design simple this project places a Serv CPU with a scan-chain around it connecting it's wishbone bus which is a combination of data and instructions out via I/O pins.
Another I/O pin is responsible for handling clock and reset. Operation will run as follows:
In this manner we should be able to implement external peripherals like UARTs, timers, and GPIOs. The external controller can be a microcontroller, FPGA, or the caravel harness SoC.