commit | 796f1870650384b57af0c0c266233ec291965e20 | [log] [tgz] |
---|---|---|
author | tinybot <bot@tinytapeout.com> | Sat Dec 03 01:34:44 2022 +0000 |
committer | tinybot <bot@tinytapeout.com> | Sat Dec 03 01:34:44 2022 +0000 |
tree | 0690e1e98c953859d440e2a866ba5505ac3901f1 | |
parent | 1412d26fd88984d20607aca7ee0c0dacc272f593 [diff] |
harden project [skip ci]
An award winning CPU design fit into the GF180 MPW0 Shuttle.
To keep the design simple this project places a Serv CPU with a scan-chain around it connecting it's wishbone bus which is a combination of data and instructions out via I/O pins.
Another I/O pin is responsible for handling clock and reset. Operation will run as follows:
In this manner we should be able to implement external peripherals like UARTs, timers, and GPIOs. The external controller can be a microcontroller, FPGA, or the caravel harness SoC.