commit | 33dfe5c116d7b01cea0c5ece22e5bde5abcc7324 | [log] [tgz] |
---|---|---|
author | tinybot <bot@tinytapeout.com> | Sun Dec 04 14:12:25 2022 +0000 |
committer | tinybot <bot@tinytapeout.com> | Sun Dec 04 14:12:25 2022 +0000 |
tree | 841b2bb60d8279e745fa44f01b284fb2d7257925 | |
parent | f06d601d17b65642d71ac79395c9ed1557db0704 [diff] |
harden project [skip ci]
An award winning CPU design fit into the GF180 MPW0 Shuttle.
To keep the design simple this project places a Serv CPU with a scan-chain around it connecting it's wishbone bus which is a combination of data and instructions out via I/O pins.
Another I/O pin is responsible for handling clock and reset. Operation will run as follows:
In this manner we should be able to implement external peripherals like UARTs, timers, and GPIOs. The external controller can be a microcontroller, FPGA, or the caravel harness SoC.