commit | 2311ae57c4d661cf5405a7f6e352b278b4f3f94b | [log] [tgz] |
---|---|---|
author | Jeff DiCorpo <jeffdi@efabless.com> | Wed Dec 14 22:22:04 2022 -0800 |
committer | Jeff DiCorpo <jeffdi@efabless.com> | Wed Dec 14 22:22:04 2022 -0800 |
tree | 7b51a1d5982c309f81061feddbc9c2f2ba57a307 | |
parent | f3ef131fcc93a278b2a00c57028037ebdc8d7c0d [diff] |
update repo
An award winning CPU design fit into the GF180 MPW0 Shuttle.
To keep the design simple this project places a Serv CPU with a scan-chain around it connecting it's wishbone bus which is a combination of data and instructions out via I/O pins.
Another I/O pin is responsible for handling clock and reset. Operation will run as follows:
In this manner we should be able to implement external peripherals like UARTs, timers, and GPIOs. The external controller can be a microcontroller, FPGA, or the caravel harness SoC.