commit | 1412d26fd88984d20607aca7ee0c0dacc272f593 | [log] [tgz] |
---|---|---|
author | Greg Davill <greg.davill@gmail.com> | Sat Dec 03 11:03:49 2022 +1030 |
committer | Greg Davill <greg.davill@gmail.com> | Sat Dec 03 11:03:49 2022 +1030 |
tree | e15d2ee57668bc0c29ad12bead0ae0ec8f7e6872 | |
parent | c608abe9a28a708f3f5003f549af3818aadb229e [diff] |
docs: Update README
An award winning CPU design fit into the GF180 MPW0 Shuttle.
To keep the design simple this project places a Serv CPU with a scan-chain around it connecting it's wishbone bus which is a combination of data and instructions out via I/O pins.
Another I/O pin is responsible for handling clock and reset. Operation will run as follows:
In this manner we should be able to implement external peripherals like UARTs, timers, and GPIOs. The external controller can be a microcontroller, FPGA, or the caravel harness SoC.