- 4d3fdb4 Replace SYNTH_DRIVING_CELL with size 2 inverters by Mohamed Gaber · 3 years, 5 months ago
- 2abf58b Remove buf_1 from the cts buffer list by manarabdelaty · 3 years, 5 months ago
- 50b373b Update synth drving cell and cap load for all std cell variants by manarabdelaty · 3 years, 6 months ago
- 3c55b38 Add default_max_tran by manarabdelaty · 3 years, 6 months ago
- 2ecac4f Added carry select adder mapping files by manarabdelaty · 4 years, 1 month ago
- 1f42245 update the rest of the std cell libraries openlane configs to a working state by agorararmard · 4 years, 1 month ago
- 716d1cd Update the exclude lists to match the new mapping of muxes to size 1 by agorararmard · 4 years, 1 month ago
- 4424e1f Map to the smallest mux by default, by agorararmard · 4 years, 1 month ago
- 2ca4602 Revised the exclude lists used in openlane by agorararmard · 4 years, 2 months ago
- 07a866e Added adder mapping files for yosys by manarabdelaty · 4 years, 2 months ago
- 6eaca1c Add yosys mux mapping. by agorararmard · 4 years, 2 months ago
- 0708640 [openlane] add pointer to no synth list -- first step to design specific lists by agorararmard · 4 years, 2 months ago
- 3267bbb [openlane] set default cell pad to 4 by agorararmard · 4 years, 2 months ago
- f2abe53 Added tribuff_map to all standard cells by manarabdelaty · 4 years, 4 months ago
- 4ddcc61 openlane config updates (PR #30 and #31): by agorararmard · 4 years, 6 months ago
- b1a1842 Corrected capacitor extraction (needed type "csubcircuit" and not by Tim Edwards · 4 years, 6 months ago
- 6f4d304 openlane support for latch mapping in synthesis by Ahmed Ghazy · 4 years, 6 months ago 1.0.42
- 29113fc renamed variables to follow the conventions by agorararmard · 4 years, 7 months ago
- 93f1168 openlane configs updates by agorararmard · 4 years, 7 months ago
- ad2e60d Renamed some variables to more meaningful names by Ahmed Ghazy · 4 years, 8 months ago
- 8e84e5c OpenLane support for other sky130 variants by Ahmed Ghazy · 4 years, 8 months ago
