diff --git a/VERSION b/VERSION
index 3a55179..95bf089 100644
--- a/VERSION
+++ b/VERSION
@@ -1 +1 @@
-1.0.442
+1.0.443
diff --git a/sky130/custom/sky130_fd_io/gds/sky130_ef_io__analog.gds b/sky130/custom/sky130_fd_io/gds/sky130_ef_io__analog.gds
index d37d552..ff0e5cc 100644
--- a/sky130/custom/sky130_fd_io/gds/sky130_ef_io__analog.gds
+++ b/sky130/custom/sky130_fd_io/gds/sky130_ef_io__analog.gds
Binary files differ
diff --git a/sky130/custom/sky130_fd_io/lef/sky130_ef_io__analog_esd_pad.lef b/sky130/custom/sky130_fd_io/lef/sky130_ef_io__analog_esd_pad.lef
new file mode 100644
index 0000000..2e032cd
--- /dev/null
+++ b/sky130/custom/sky130_fd_io/lef/sky130_ef_io__analog_esd_pad.lef
@@ -0,0 +1,345 @@
+VERSION 5.7 ;
+  NOWIREEXTENSIONATPIN ON ;
+  DIVIDERCHAR "/" ;
+  BUSBITCHARS "[]" ;
+MACRO sky130_ef_io__analog_esd_pad
+  CLASS PAD ;
+  FOREIGN sky130_ef_io__analog_esd_pad ;
+  ORIGIN 0.000 0.000 ;
+  SIZE 75.000 BY 200.000 ;
+  PIN P_CORE
+    PORT
+      LAYER met3 ;
+        RECT 24.720 0.000 49.720 82.350 ;
+    END
+  END P_CORE
+  PIN VSSA
+    PORT
+      LAYER met4 ;
+        RECT 0.000 36.735 1.270 40.185 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 0.000 56.405 75.000 56.735 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 0.000 47.735 75.000 48.065 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 0.000 51.645 1.270 52.825 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 73.730 36.735 75.000 40.185 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 73.730 56.405 75.000 56.735 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 73.730 47.735 75.000 48.065 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 73.730 51.645 75.000 52.825 ;
+    END
+    PORT
+      LAYER met5 ;
+        RECT 73.730 36.840 75.000 40.085 ;
+    END
+    PORT
+      LAYER met5 ;
+        RECT 0.000 47.735 1.270 56.735 ;
+    END
+    PORT
+      LAYER met5 ;
+        RECT 0.000 36.840 1.270 40.085 ;
+    END
+    PORT
+      LAYER met5 ;
+        RECT 73.730 47.735 75.000 56.735 ;
+    END
+  END VSSA
+  PIN VSSD
+    PORT
+      LAYER met4 ;
+        RECT 0.000 41.585 1.270 46.235 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 73.730 41.585 75.000 46.235 ;
+    END
+    PORT
+      LAYER met5 ;
+        RECT 0.000 41.685 1.270 46.135 ;
+    END
+    PORT
+      LAYER met5 ;
+        RECT 73.730 41.685 75.000 46.135 ;
+    END
+  END VSSD
+  PIN AMUXBUS_B
+    PORT
+      LAYER met4 ;
+        RECT 0.000 48.365 75.000 51.345 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 73.730 48.365 75.000 51.345 ;
+    END
+  END AMUXBUS_B
+  PIN AMUXBUS_A
+    PORT
+      LAYER met4 ;
+        RECT 0.000 53.125 75.000 56.105 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 73.730 53.125 75.000 56.105 ;
+    END
+  END AMUXBUS_A
+  PIN VDDIO_Q
+    PORT
+      LAYER met4 ;
+        RECT 0.000 64.085 1.270 68.535 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 73.730 64.085 75.000 68.535 ;
+    END
+    PORT
+      LAYER met5 ;
+        RECT 73.730 64.185 75.000 68.435 ;
+    END
+    PORT
+      LAYER met5 ;
+        RECT 0.000 64.185 1.270 68.435 ;
+    END
+  END VDDIO_Q
+  PIN VDDIO
+    PORT
+      LAYER met4 ;
+        RECT 0.000 70.035 1.270 95.000 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 0.000 19.785 1.270 24.435 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 73.730 70.035 75.000 95.000 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 73.730 19.785 75.000 24.435 ;
+    END
+    PORT
+      LAYER met5 ;
+        RECT 0.000 19.885 1.270 24.335 ;
+    END
+    PORT
+      LAYER met5 ;
+        RECT 0.000 70.035 1.270 94.985 ;
+    END
+    PORT
+      LAYER met5 ;
+        RECT 73.730 19.885 75.000 24.335 ;
+    END
+    PORT
+      LAYER met5 ;
+        RECT 73.730 70.035 75.000 94.985 ;
+    END
+  END VDDIO
+  PIN VSWITCH
+    PORT
+      LAYER met4 ;
+        RECT 0.000 31.885 1.270 35.335 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 73.730 31.885 75.000 35.335 ;
+    END
+    PORT
+      LAYER met5 ;
+        RECT 73.730 31.985 75.000 35.235 ;
+    END
+    PORT
+      LAYER met5 ;
+        RECT 0.000 31.985 1.270 35.235 ;
+    END
+  END VSWITCH
+  PIN VSSIO
+    PORT
+      LAYER met4 ;
+        RECT 0.000 25.835 1.270 30.485 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 73.730 25.835 75.000 30.485 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 0.000 175.785 1.270 200.000 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 0.630 191.600 0.640 191.610 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 73.730 175.785 75.000 200.000 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 74.360 191.600 74.370 191.610 ;
+    END
+    PORT
+      LAYER met5 ;
+        RECT 73.730 25.935 75.000 30.385 ;
+    END
+    PORT
+      LAYER met5 ;
+        RECT 73.730 175.785 75.000 200.000 ;
+    END
+    PORT
+      LAYER met5 ;
+        RECT 0.000 175.785 1.270 200.000 ;
+    END
+    PORT
+      LAYER met5 ;
+        RECT 0.000 25.935 1.270 30.385 ;
+    END
+  END VSSIO
+  PIN VDDA
+    PORT
+      LAYER met4 ;
+        RECT 0.000 14.935 0.965 18.385 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 74.035 14.935 75.000 18.385 ;
+    END
+    PORT
+      LAYER met5 ;
+        RECT 0.000 15.035 0.965 18.285 ;
+    END
+    PORT
+      LAYER met5 ;
+        RECT 74.035 15.035 75.000 18.285 ;
+    END
+  END VDDA
+  PIN VCCD
+    PORT
+      LAYER met4 ;
+        RECT 0.000 8.885 1.270 13.535 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 73.730 8.885 75.000 13.535 ;
+    END
+    PORT
+      LAYER met5 ;
+        RECT 0.000 8.985 1.270 13.435 ;
+    END
+    PORT
+      LAYER met5 ;
+        RECT 73.730 8.985 75.000 13.435 ;
+    END
+  END VCCD
+  PIN VCCHIB
+    PORT
+      LAYER met4 ;
+        RECT 0.000 2.035 1.270 7.485 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 73.730 2.035 75.000 7.485 ;
+    END
+    PORT
+      LAYER met5 ;
+        RECT 0.000 2.135 1.270 7.385 ;
+    END
+    PORT
+      LAYER met5 ;
+        RECT 73.730 2.135 75.000 7.385 ;
+    END
+  END VCCHIB
+  PIN VSSIO_Q
+    PORT
+      LAYER met4 ;
+        RECT 0.000 58.235 1.270 62.685 ;
+    END
+    PORT
+      LAYER met4 ;
+        RECT 73.730 58.235 75.000 62.685 ;
+    END
+    PORT
+      LAYER met5 ;
+        RECT 73.730 58.335 75.000 62.585 ;
+    END
+    PORT
+      LAYER met5 ;
+        RECT 0.000 58.335 1.270 62.585 ;
+    END
+  END VSSIO_Q
+  PIN P_PAD
+    PORT
+      LAYER met5 ;
+        RECT 7.050 105.120 67.890 165.945 ;
+    END
+  END P_PAD
+  OBS
+      LAYER li1 ;
+        RECT 2.905 48.265 72.045 181.100 ;
+      LAYER met1 ;
+        RECT 4.250 46.255 70.440 48.855 ;
+      LAYER met2 ;
+        RECT 4.250 46.255 70.440 48.855 ;
+      LAYER met3 ;
+        RECT 0.455 82.750 74.250 173.315 ;
+        RECT 0.455 14.905 24.320 82.750 ;
+        RECT 50.120 14.905 74.250 82.750 ;
+      LAYER met4 ;
+        RECT 1.670 175.385 73.330 200.000 ;
+        RECT 0.965 95.400 74.035 175.385 ;
+        RECT 1.670 69.635 73.330 95.400 ;
+        RECT 0.965 68.935 74.035 69.635 ;
+        RECT 1.670 63.685 73.330 68.935 ;
+        RECT 0.965 63.085 74.035 63.685 ;
+        RECT 1.670 57.835 73.330 63.085 ;
+        RECT 0.965 57.135 74.035 57.835 ;
+        RECT 1.670 51.745 73.330 52.725 ;
+        RECT 0.965 46.635 74.035 47.335 ;
+        RECT 1.670 41.185 73.330 46.635 ;
+        RECT 0.965 40.585 74.035 41.185 ;
+        RECT 1.670 36.335 73.330 40.585 ;
+        RECT 0.965 35.735 74.035 36.335 ;
+        RECT 1.670 31.485 73.330 35.735 ;
+        RECT 0.965 30.885 74.035 31.485 ;
+        RECT 1.670 25.435 73.330 30.885 ;
+        RECT 0.965 24.835 74.035 25.435 ;
+        RECT 1.670 19.385 73.330 24.835 ;
+        RECT 0.965 18.785 74.035 19.385 ;
+        RECT 1.365 14.535 73.635 18.785 ;
+        RECT 0.965 13.935 74.035 14.535 ;
+        RECT 1.670 8.485 73.330 13.935 ;
+        RECT 0.965 7.885 74.035 8.485 ;
+        RECT 1.670 2.035 73.330 7.885 ;
+      LAYER met5 ;
+        RECT 2.870 174.185 72.130 200.000 ;
+        RECT 0.000 167.545 75.000 174.185 ;
+        RECT 0.000 103.520 5.450 167.545 ;
+        RECT 69.490 103.520 75.000 167.545 ;
+        RECT 0.000 96.585 75.000 103.520 ;
+        RECT 2.870 36.840 72.130 96.585 ;
+        RECT 0.000 36.835 75.000 36.840 ;
+        RECT 2.870 18.285 72.130 36.835 ;
+        RECT 2.565 15.035 72.435 18.285 ;
+        RECT 2.870 2.135 72.130 15.035 ;
+  END
+END sky130_ef_io__analog_pad
+END LIBRARY
+
diff --git a/sky130/custom/sky130_fd_io/lef/sky130_ef_io__analog_pad.lef b/sky130/custom/sky130_fd_io/lef/sky130_ef_io__analog_pad.lef
index fb2f3ee..cf7c9a2 100644
--- a/sky130/custom/sky130_fd_io/lef/sky130_ef_io__analog_pad.lef
+++ b/sky130/custom/sky130_fd_io/lef/sky130_ef_io__analog_pad.lef
@@ -340,6 +340,6 @@
         RECT 2.565 15.035 72.435 18.285 ;
         RECT 2.870 2.135 72.130 15.035 ;
   END
-END sky130_ef_io__analog_pad
+END sky130_ef_io__analog_noesd_pad
 END LIBRARY
 
diff --git a/sky130/custom/sky130_fd_io/mag/sky130_ef_io__analog_esd_pad.mag b/sky130/custom/sky130_fd_io/mag/sky130_ef_io__analog_esd_pad.mag
new file mode 100644
index 0000000..1f5112e
--- /dev/null
+++ b/sky130/custom/sky130_fd_io/mag/sky130_ef_io__analog_esd_pad.mag
@@ -0,0 +1,203 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1681336083
+<< checkpaint >>
+rect -1260 -853 16260 41260
+<< metal3 >>
+rect 5078 0 9858 391
+<< metal4 >>
+rect 0 35157 254 40000
+rect 14746 35157 15000 40000
+rect 0 14007 254 19000
+rect 14746 14007 15000 19000
+rect 0 12817 254 13707
+rect 14746 12817 15000 13707
+rect 0 11647 254 12537
+rect 14746 11647 15000 12537
+rect 0 11281 254 11347
+rect 14746 11281 15000 11347
+rect 0 10625 254 11221
+rect 14746 10625 15000 11221
+rect 0 10329 254 10565
+rect 14746 10329 15000 10565
+rect 0 9673 254 10269
+rect 14746 9673 15000 10269
+rect 0 9547 254 9613
+rect 14746 9547 15000 9613
+rect 0 8317 254 9247
+rect 14746 8317 15000 9247
+rect 0 7347 254 8037
+rect 14746 7347 15000 8037
+rect 0 6377 254 7067
+rect 14746 6377 15000 7067
+rect 0 5167 254 6097
+rect 14746 5167 15000 6097
+rect 0 3957 254 4887
+rect 14746 3957 15000 4887
+rect 0 2987 193 3677
+rect 14807 2987 15000 3677
+rect 0 1777 254 2707
+rect 14746 1777 15000 2707
+rect 0 407 254 1497
+rect 14746 407 15000 1497
+<< metal5 >>
+rect 0 35157 254 40000
+rect 14746 35157 15000 40000
+rect 2000 20574 12990 33596
+rect 0 14007 254 18997
+rect 14746 14007 15000 18997
+rect 0 12837 254 13687
+rect 14746 12837 15000 13687
+rect 0 11667 254 12517
+rect 14746 11667 15000 12517
+rect 0 9547 254 11347
+rect 14746 9547 15000 11347
+rect 0 8337 254 9227
+rect 14746 8337 15000 9227
+rect 0 7368 254 8017
+rect 14746 7368 15000 8017
+rect 0 6397 254 7047
+rect 14746 6397 15000 7047
+rect 0 5187 254 6077
+rect 14746 5187 15000 6077
+rect 0 3977 254 4867
+rect 14746 3977 15000 4867
+rect 0 3007 193 3657
+rect 14807 3007 15000 3657
+rect 0 1797 254 2687
+rect 14746 1797 15000 2687
+rect 0 427 254 1477
+rect 14746 427 15000 1477
+use sky130_ef_io__esd_pad_and_busses  sky130_ef_io__esd_pad_and_busses_0
+timestamp 1681336083
+transform 1 0 -8 0 1 -1
+box 8 1 15008 40001
+<< labels >>
+flabel metal3 s 5078 0 9858 391 0 FreeSans 3125 0 0 0 P_CORE
+port 1 nsew
+flabel metal4 s 0 7347 254 8037 3 FreeSans 812 0 0 0 VSSA
+port 2 nsew
+flabel metal4 s 0 11281 254 11347 3 FreeSans 812 0 0 0 VSSA
+port 2 nsew
+flabel metal4 s 0 9547 254 9613 3 FreeSans 812 0 0 0 VSSA
+port 2 nsew
+flabel metal4 s 0 10329 254 10565 3 FreeSans 812 0 0 0 VSSA
+port 2 nsew
+flabel metal4 s 14746 7347 15000 8037 3 FreeSans 812 180 0 0 VSSA
+port 2 nsew
+flabel metal4 s 14746 11281 15000 11347 3 FreeSans 812 180 0 0 VSSA
+port 2 nsew
+flabel metal4 s 14746 9547 15000 9613 3 FreeSans 812 180 0 0 VSSA
+port 2 nsew
+flabel metal4 s 14746 10329 15000 10565 3 FreeSans 812 180 0 0 VSSA
+port 2 nsew
+flabel metal5 s 14746 7368 15000 8017 3 FreeSans 812 180 0 0 VSSA
+port 2 nsew
+flabel metal5 s 0 9547 254 11347 3 FreeSans 812 0 0 0 VSSA
+port 2 nsew
+flabel metal5 s 0 7368 254 8017 3 FreeSans 812 0 0 0 VSSA
+port 2 nsew
+flabel metal5 s 14746 9547 15000 11347 3 FreeSans 812 180 0 0 VSSA
+port 2 nsew
+flabel metal4 s 0 8317 254 9247 3 FreeSans 812 0 0 0 VSSD
+port 3 nsew
+flabel metal4 s 14746 8317 15000 9247 3 FreeSans 812 180 0 0 VSSD
+port 3 nsew
+flabel metal5 s 0 8337 254 9227 3 FreeSans 812 0 0 0 VSSD
+port 3 nsew
+flabel metal5 s 14746 8337 15000 9227 3 FreeSans 812 180 0 0 VSSD
+port 3 nsew
+flabel metal4 s 0 9673 254 10269 3 FreeSans 812 0 0 0 AMUXBUS_B
+port 4 nsew
+flabel metal4 s 14746 9673 15000 10269 3 FreeSans 812 180 0 0 AMUXBUS_B
+port 4 nsew
+flabel metal4 s 0 10625 254 11221 3 FreeSans 812 0 0 0 AMUXBUS_A
+port 5 nsew
+flabel metal4 s 14746 10625 15000 11221 3 FreeSans 812 180 0 0 AMUXBUS_A
+port 5 nsew
+flabel metal4 s 0 12817 254 13707 3 FreeSans 812 0 0 0 VDDIO_Q
+port 6 nsew
+flabel metal4 s 14746 12817 15000 13707 3 FreeSans 812 180 0 0 VDDIO_Q
+port 6 nsew
+flabel metal5 s 14746 12837 15000 13687 3 FreeSans 812 180 0 0 VDDIO_Q
+port 6 nsew
+flabel metal5 s 0 12837 254 13687 3 FreeSans 812 0 0 0 VDDIO_Q
+port 6 nsew
+flabel metal4 s 0 14007 254 19000 3 FreeSans 812 0 0 0 VDDIO
+port 7 nsew
+flabel metal4 s 0 3957 254 4887 3 FreeSans 812 0 0 0 VDDIO
+port 7 nsew
+flabel metal4 s 14746 14007 15000 19000 3 FreeSans 812 180 0 0 VDDIO
+port 7 nsew
+flabel metal4 s 14746 3957 15000 4887 3 FreeSans 812 180 0 0 VDDIO
+port 7 nsew
+flabel metal5 s 0 3977 254 4867 3 FreeSans 812 0 0 0 VDDIO
+port 7 nsew
+flabel metal5 s 0 14007 254 18997 3 FreeSans 812 0 0 0 VDDIO
+port 7 nsew
+flabel metal5 s 14746 3977 15000 4867 3 FreeSans 812 180 0 0 VDDIO
+port 7 nsew
+flabel metal5 s 14746 14007 15000 18997 3 FreeSans 812 180 0 0 VDDIO
+port 7 nsew
+flabel metal4 s 0 6377 254 7067 3 FreeSans 812 0 0 0 VSWITCH
+port 8 nsew
+flabel metal4 s 14746 6377 15000 7067 3 FreeSans 812 180 0 0 VSWITCH
+port 8 nsew
+flabel metal5 s 14746 6397 15000 7047 3 FreeSans 812 180 0 0 VSWITCH
+port 8 nsew
+flabel metal5 s 0 6397 254 7047 3 FreeSans 812 0 0 0 VSWITCH
+port 8 nsew
+flabel metal4 s 0 5167 254 6097 3 FreeSans 812 0 0 0 VSSIO
+port 9 nsew
+flabel metal4 s 14746 5167 15000 6097 3 FreeSans 812 180 0 0 VSSIO
+port 9 nsew
+flabel metal4 s 0 35157 254 40000 3 FreeSans 812 0 0 0 VSSIO
+port 9 nsew
+flabel metal4 s 127 38321 127 38321 3 FreeSans 812 0 0 0 VSSIO
+flabel metal4 s 14746 35157 15000 40000 3 FreeSans 812 180 0 0 VSSIO
+port 9 nsew
+flabel metal4 s 14873 38321 14873 38321 3 FreeSans 812 180 0 0 VSSIO
+flabel metal5 s 14746 5187 15000 6077 3 FreeSans 812 180 0 0 VSSIO
+port 9 nsew
+flabel metal5 s 14746 35157 15000 40000 3 FreeSans 812 180 0 0 VSSIO
+port 9 nsew
+flabel metal5 s 0 35157 254 40000 3 FreeSans 812 0 0 0 VSSIO
+port 9 nsew
+flabel metal5 s 0 5187 254 6077 3 FreeSans 812 0 0 0 VSSIO
+port 9 nsew
+flabel metal4 s 0 2987 193 3677 3 FreeSans 812 0 0 0 VDDA
+port 10 nsew
+flabel metal4 s 14807 2987 15000 3677 3 FreeSans 812 180 0 0 VDDA
+port 10 nsew
+flabel metal5 s 0 3007 193 3657 3 FreeSans 812 0 0 0 VDDA
+port 10 nsew
+flabel metal5 s 14807 3007 15000 3657 3 FreeSans 812 180 0 0 VDDA
+port 10 nsew
+flabel metal4 s 0 1777 254 2707 3 FreeSans 812 0 0 0 VCCD
+port 11 nsew
+flabel metal4 s 14746 1777 15000 2707 3 FreeSans 812 180 0 0 VCCD
+port 11 nsew
+flabel metal5 s 0 1797 254 2687 3 FreeSans 812 0 0 0 VCCD
+port 11 nsew
+flabel metal5 s 14746 1797 15000 2687 3 FreeSans 812 180 0 0 VCCD
+port 11 nsew
+flabel metal4 s 0 407 254 1497 3 FreeSans 812 0 0 0 VCCHIB
+port 12 nsew
+flabel metal4 s 14746 407 15000 1497 3 FreeSans 812 180 0 0 VCCHIB
+port 12 nsew
+flabel metal5 s 0 427 254 1477 3 FreeSans 812 0 0 0 VCCHIB
+port 12 nsew
+flabel metal5 s 14746 427 15000 1477 3 FreeSans 812 180 0 0 VCCHIB
+port 12 nsew
+flabel metal4 s 0 11647 254 12537 3 FreeSans 812 0 0 0 VSSIO_Q
+port 13 nsew
+flabel metal4 s 14746 11647 15000 12537 3 FreeSans 812 180 0 0 VSSIO_Q
+port 13 nsew
+flabel metal5 s 14746 11667 15000 12517 3 FreeSans 812 180 0 0 VSSIO_Q
+port 13 nsew
+flabel metal5 s 0 11667 254 12517 3 FreeSans 812 0 0 0 VSSIO_Q
+port 13 nsew
+flabel metal5 s 2000 20574 12990 33596 0 FreeSans 3125 0 0 0 P_PAD
+port 14 nsew
+<< end >>
diff --git a/sky130/custom/sky130_fd_io/mag/sky130_ef_io__analog_pad.mag b/sky130/custom/sky130_fd_io/mag/sky130_ef_io__analog_pad.mag
index 1f5112e..c492e5e 100644
--- a/sky130/custom/sky130_fd_io/mag/sky130_ef_io__analog_pad.mag
+++ b/sky130/custom/sky130_fd_io/mag/sky130_ef_io__analog_pad.mag
@@ -1,11 +1,11 @@
 magic
 tech sky130A
 magscale 1 2
-timestamp 1681336083
+timestamp 1681335912
 << checkpaint >>
 rect -1260 -853 16260 41260
 << metal3 >>
-rect 5078 0 9858 391
+rect 5544 0 9344 391
 << metal4 >>
 rect 0 35157 254 40000
 rect 14746 35157 15000 40000
@@ -69,12 +69,12 @@
 rect 14746 1797 15000 2687
 rect 0 427 254 1477
 rect 14746 427 15000 1477
-use sky130_ef_io__esd_pad_and_busses  sky130_ef_io__esd_pad_and_busses_0
-timestamp 1681336083
+use sky130_ef_io__simple_pad_and_busses  sky130_ef_io__simple_pad_and_busses_0
+timestamp 1681335912
 transform 1 0 -8 0 1 -1
 box 8 1 15008 40001
 << labels >>
-flabel metal3 s 5078 0 9858 391 0 FreeSans 3125 0 0 0 P_CORE
+flabel metal3 s 5544 0 9344 391 0 FreeSans 3125 0 0 0 P_CORE
 port 1 nsew
 flabel metal4 s 0 7347 254 8037 3 FreeSans 812 0 0 0 VSSA
 port 2 nsew
diff --git a/sky130/custom/sky130_fd_io/spice/sky130_ef_io__analog.spice b/sky130/custom/sky130_fd_io/spice/sky130_ef_io__analog.spice
index 22e944a..0162b74 100644
--- a/sky130/custom/sky130_fd_io/spice/sky130_ef_io__analog.spice
+++ b/sky130/custom/sky130_fd_io/spice/sky130_ef_io__analog.spice
@@ -17,11 +17,23 @@
 *---------------------------------------------------------------------------
 * sky130_ef_io__analog_pad:
 *---------------------------------------------------------------------------
+* This is just a copy of sky130_ef_io__analog_noesd_pad.
+*---------------------------------------------------------------------------
+
+.subckt sky130_ef_io__analog_pad P_CORE VSSA VSSD AMUXBUS_B AMUXBUS_A
++ VDDIO_Q VDDIO VSWITCH VSSIO VDDA VCCD VCCHIB VSSIO_Q P_PAD
+
+R0 P_PAD P_CORE sky130_fd_pr__res_generic_m5 w=253 l=0.1
+.ends
+
+*---------------------------------------------------------------------------
+* sky130_ef_io__analog_esd_pad:
+*---------------------------------------------------------------------------
 * Simple pad, straight through, with ESD diodes (5 each P and N).
 *---------------------------------------------------------------------------
 
-.subckt sky130_ef_io__analog_pad P_CORE VSSA VSSD AMUXBUS_B AMUXBUS_A VDDIO_Q VDDIO
-+ VSWITCH VSSIO VDDA VCCD VCCHIB VSSIO_Q P_PAD
+.subckt sky130_ef_io__analog_esd_pad P_CORE VSSA VSSD AMUXBUS_B AMUXBUS_A VDDIO_Q
++ VDDIO VSWITCH VSSIO VDDA VCCD VCCHIB VSSIO_Q P_PAD
 R0 P_PAD P_CORE sky130_fd_pr__res_generic_m5 w=253 l=0.1
 
 D0 VSSIO P_CORE sky130_fd_pr__diode_pw2nd_11v0 pj=1.02e+08 area=5e+13
diff --git a/sky130/custom/sky130_fd_io/verilog/sky130_ef_io__analog_esd_pad.v b/sky130/custom/sky130_fd_io/verilog/sky130_ef_io__analog_esd_pad.v
new file mode 100644
index 0000000..832931f
--- /dev/null
+++ b/sky130/custom/sky130_fd_io/verilog/sky130_ef_io__analog_esd_pad.v
@@ -0,0 +1,210 @@
+/**
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+`ifndef SKY130_EF_IO__ANALOG_ESD_PAD_V
+`define SKY130_EF_IO__ANALOG_ESD_PAD_V
+
+/**
+ * analog_esd_pad: Analog PAD.
+ *
+ * Verilog top module.
+ *
+ * WARNING: This file is autogenerated, do not modify directly!
+ */
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+`ifdef USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+module sky130_ef_io__analog_esd_pad (AMUXBUS_A, AMUXBUS_B, P_PAD, P_CORE
+                                 ,VCCD, VCCHIB, VDDA, VDDIO, VDDIO_Q, VSSA, VSSD, VSSIO, VSSIO_Q, VSWITCH
+                                );
+inout AMUXBUS_A;
+inout AMUXBUS_B;
+inout P_PAD;
+inout P_CORE;
+inout VCCD;
+inout VCCHIB;
+inout VDDA;
+inout VDDIO;
+inout VDDIO_Q;
+inout VSSA;
+inout VSSD;
+inout VSSIO;
+inout VSSIO_Q;
+inout VSWITCH;
+wire pwr_good = VDDIO===1 && VSSIO===0;
+wire pad_sw = pwr_good===1 ? 1'b1 : 1'bx;
+tranif1 x_pad (P_PAD, P_CORE, pad_sw);
+endmodule
+
+`else  // FUNCTIONAL
+
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+module sky130_ef_io__analog_esd_pad (AMUXBUS_A, AMUXBUS_B, P_PAD, P_CORE
+                                 ,VCCD, VCCHIB, VDDA, VDDIO, VDDIO_Q, VSSA, VSSD, VSSIO, VSSIO_Q, VSWITCH
+                                );
+inout AMUXBUS_A;
+inout AMUXBUS_B;
+inout P_PAD;
+inout P_CORE;
+inout VCCD;
+inout VCCHIB;
+inout VDDA;
+inout VDDIO;
+inout VDDIO_Q;
+inout VSSA;
+inout VSSD;
+inout VSSIO;
+inout VSSIO_Q;
+inout VSWITCH;
+wire pwr_good = VDDIO===1 && VSSIO===0;
+wire pad_sw = pwr_good===1 ? 1'b1 : 1'bx;
+tranif1 x_pad (P_PAD, P_CORE, pad_sw);
+endmodule
+
+`endif // FUNCTIONAL
+
+`else  // USE_POWER_PINS
+
+`ifdef FUNCTIONAL
+
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+module sky130_ef_io__analog_esd_pad (AMUXBUS_A, AMUXBUS_B, P_PAD, P_CORE
+                                );
+inout AMUXBUS_A;
+inout AMUXBUS_B;
+inout P_PAD;
+inout P_CORE;
+supply1 VCCD;
+supply1 VCCHIB;
+supply1 VDDA;
+supply1 VDDIO;
+supply1 VDDIO_Q;
+supply0 VSSA;
+supply0 VSSD;
+supply0 VSSIO;
+supply0 VSSIO_Q;
+supply1 VSWITCH;
+wire pwr_good = 1;
+wire pad_sw = pwr_good===1 ? 1'b1 : 1'bx;
+tranif1 x_pad (P_PAD, P_CORE, pad_sw);
+endmodule
+
+`else  // FUNCTIONAL
+
+/*
+ * Copyright 2020 The SkyWater PDK Authors
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     https://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+*/
+
+module sky130_ef_io__analog_esd_pad (AMUXBUS_A, AMUXBUS_B, P_PAD, P_CORE
+                                );
+inout AMUXBUS_A;
+inout AMUXBUS_B;
+inout P_PAD;
+inout P_CORE;
+supply1 VCCD;
+supply1 VCCHIB;
+supply1 VDDA;
+supply1 VDDIO;
+supply1 VDDIO_Q;
+supply0 VSSA;
+supply0 VSSD;
+supply0 VSSIO;
+supply0 VSSIO_Q;
+supply1 VSWITCH;
+wire pwr_good = 1;
+wire pad_sw = pwr_good===1 ? 1'b1 : 1'bx;
+tranif1 x_pad (P_PAD, P_CORE, pad_sw);
+endmodule
+
+`endif // FUNCTIONAL
+
+`endif // USE_POWER_PINS
+
+`default_nettype wire
+`endif  // SKY130_EF_IO__ANALOG_ESD_PAD_V
diff --git a/sky130/custom/sky130_fd_io/verilog/sky130_ef_io__analog_pad.v b/sky130/custom/sky130_fd_io/verilog/sky130_ef_io__analog_pad.v
index f172cd5..1449c18 100644
--- a/sky130/custom/sky130_fd_io/verilog/sky130_ef_io__analog_pad.v
+++ b/sky130/custom/sky130_fd_io/verilog/sky130_ef_io__analog_pad.v
@@ -20,7 +20,7 @@
 `define SKY130_EF_IO__ANALOG_PAD_V
 
 /**
- * analog_pad: Analog PAD.
+ * analog_pad: Analog PAD, without ESD structures.
  *
  * Verilog top module.
  *