diff --git a/gf180mcu/Makefile.in b/gf180mcu/Makefile.in
index f2f6a79..865f3e5 100644
--- a/gf180mcu/Makefile.in
+++ b/gf180mcu/Makefile.in
@@ -999,7 +999,7 @@
 		-lef cells/*/*.lef annotate compile-only \
 			filter=custom/scripts/fix_digital_lef.py \
 		-verilog models/*/*.v compile-only rename=primitives \
-		-verilog cells/*/*.v exclude=*.*.v,primitives.v stub \
+		-verilog cells/*/*.v exclude=*.*.v,primitives.v \
 			compile-only filter=custom/scripts/inc_verilog.py \
 		-library digital gf180mcu_fd_sc_mcu9t5v0 2>&1 | \
 		tee -a ${GF180MCU$*}_make.log
@@ -1083,7 +1083,7 @@
 		-lef cells/*/*.lef annotate compile-only \
 			filter=custom/scripts/fix_digital_lef.py \
 		-verilog models/*/*.v compile-only rename=primitives \
-		-verilog cells/*/*.v exclude=*.*.v,primitives.v stub \
+		-verilog cells/*/*.v exclude=*.*.v,primitives.v \
 			compile-only filter=custom/scripts/inc_verilog.py \
 		-library digital gf180mcu_fd_sc_mcu7t5v0 2>&1 | \
 		tee -a ${GF180MCU$*}_make.log