diff --git a/VERSION b/VERSION
index 7bf92ee..8bbd18b 100644
--- a/VERSION
+++ b/VERSION
@@ -1 +1 @@
-1.0.420
+1.0.421
diff --git a/common/foundry_install.py b/common/foundry_install.py
index bcb17e6..f8738e6 100755
--- a/common/foundry_install.py
+++ b/common/foundry_install.py
@@ -167,6 +167,10 @@
 #		    specified for installation:  Do parasitic extraction
 #		    (NOTE:  Only does parasitic capacitance extraction).
 #
+#	noextract: Used with "-gds".  Do not extract the layout into a
+#		    netlist (implies that the layout uses the "device
+#		    primitive" property).
+#
 #	options:   Followed by "=" and the name of a script.  Behavior
 #		    is dependent on the mode;  if applied to "-gds",
 #		    then the script is inserted before the GDS read
@@ -1257,6 +1261,7 @@
     no_gds_convert = False
     no_lef_convert = False
     do_parasitics = False
+    no_extract = False
     cdl_compile_only = False
     lef_compile = False
     lef_compile_only = False
@@ -1302,6 +1307,10 @@
             if option[0] == 'gds':
                 do_parasitics = True
 
+        if 'noextract' in option:
+            if option[0] == 'gds':
+                no_extract = True
+
         # Option 'privileged' is a standalone keyword.
         if 'priv' in option or 'privileged' in option or 'private' in option:
             if option[0] == 'cdl':
@@ -2150,7 +2159,7 @@
                 print('Running (in ' + destlibdir + '): ' + ' '.join(procopts))
                 subprocess_run('cdl2spi.py', procopts, cwd = destlibdir)
 
-    elif have_gds and not no_gds_convert:
+    elif have_gds and not no_gds_convert and not no_extract:
         # If neither SPICE nor CDL formats is available in the source, then
         # read GDS;  if the result has no ports, then read the corresponding
         # LEF library to get port information.  Then write out a SPICE netlist
diff --git a/common/port_order.py b/common/port_order.py
new file mode 100755
index 0000000..2a6c8b3
--- /dev/null
+++ b/common/port_order.py
@@ -0,0 +1,136 @@
+#!/usr/bin/env python3
+#
+# port_order.py:  For the given install path, library name, and cellname,
+# find the Magic layout of the cell, and set the indexes of the ports to
+# match the order of the specified ports.  The names of the ports must
+# match and must be a complete set;  otherwise different ports may end up
+# with the same index.
+# The port indexes are changed in the layout in both the mag/ (full) and maglef/
+# (abstract) directories.  Option "-maglef" or "-mag" will restrict the
+# use to only the view indicated by the option.
+# 
+# e.g.:
+#
+# port_order.py /path/to/sky130A \
+#	sky130_fd_sc_hd sky130_fd_sc_hd__inv_1 A VGND VNB VPB VPWR Y
+
+import os
+import re
+import sys
+
+def order_ports(filename, portnames):
+    with open(filename, 'r') as ifile:
+        magtext = ifile.read().splitlines() 
+
+    labrex = re.compile('<< labels >>')
+
+    in_labs = False
+    portidx = 0
+
+    with open(filename, 'w') as ofile:
+        for line in magtext:
+            lmatch = labrex.match(line)
+            if lmatch:
+                in_labs = True
+                print(line, file=ofile)
+            elif in_labs:
+                linetok = line.split()
+                if linetok[0] == 'port':
+                    if portidx > 0:
+                        print(linetok[0] + ' ' + str(portidx) + ' ' + linetok[2], file=ofile)
+                    else:
+                        print(line, file=ofile)
+                    portidx = 0
+                elif linetok[0] == 'flabel':
+                    portlab = linetok[-1]
+                    try:
+                        portidx = portnames.index(portlab) + 1
+                    except:
+                        print('Error: Port order list does not contain "' + portlab + '"')
+                        portidx = 0
+                    print(line, file=ofile)
+                else:
+                    print(line, file=ofile)
+            else:
+                print(line, file=ofile)
+
+def usage():
+    print("port_order.py <path_to_pdk> <libname> <cellname> <port_name> ... [option]")
+    print("  options:")
+    print("   -mag      do only for the view in the mag/ directory")
+    print("   -maglef   do only for the view in the maglef/ directory")
+    return 0
+
+if __name__ == '__main__':
+
+    options = []
+    arguments = []
+    for item in sys.argv[1:]:
+        if item.find('-', 0) == 0:
+            options.append(item)
+        else:
+            arguments.append(item)
+
+    if len(arguments) < 4:
+        print('Not enough options given to port_order.py.')
+        usage()
+        sys.exit(0)
+
+    source = arguments[0]
+    libname = arguments[1]
+    cellname = arguments[2]
+    portnames = arguments[3:]
+
+    # Diagnostic
+    print('port_order.py:')
+    print('   source     = ' + source)
+    print('   library    = ' + libname)
+    print('   cell       = ' + cellname)
+    print('   port names = ' + ' '.join(portnames))
+
+    fail = 0
+
+    efformat = True if '-ef_format' in options else False
+
+    domag = True
+    domaglef = True
+    if '-mag' in options and '-maglef' not in options:
+        domaglef = False
+    if '-maglef' in options and '-mag' not in options:
+        domag = False
+
+    if domag:
+        if efformat:
+            filename = source + '/libs.ref/mag/' + libname + '/' + cellname + '.mag'
+        else:
+            filename = source + '/libs.ref/' + libname + '/mag/' + cellname + '.mag'
+
+        if os.path.isfile(filename):
+            order_ports(filename, portnames)
+        else:
+            fail += 1
+    else:
+        fail += 1
+
+    if domaglef:
+        if efformat:
+            filename = source + '/libs.ref/maglef/' + libname + '/' + cellname + '.mag'
+        else:
+            filename = source + '/libs.ref/' + libname + '/maglef/' + cellname + '.mag'
+
+        if os.path.isfile(filename):
+            order_ports(filename, portnames)
+        else:
+            fail += 1
+    else:
+        fail += 1
+
+    if fail == 2:
+        print('Error:  No layout file in either mag/ or maglef/', file=sys.stderr)
+        if efformat:
+            print('(' + source + '/libs.ref/mag[lef]/' + libname +
+		    '/' + cellname + '.mag)', file=sys.stderr)
+        else:
+            print('(' + source + '/libs.ref/' + libname + '/mag[lef]/'
+		    + cellname + '.mag)', file=sys.stderr)
+
diff --git a/gf180mcu/Makefile.in b/gf180mcu/Makefile.in
index 2842a03..86a650d 100644
--- a/gf180mcu/Makefile.in
+++ b/gf180mcu/Makefile.in
@@ -428,6 +428,10 @@
 INSTALL = ${SCRIPTSDIR}/common/staging_install.py ${EF_FORMAT}
 endif
 
+# The script(s) below are used for custom changes to the vendor PDK files
+PORTORDER = ../common/port_order.py ${EF_FORMAT}
+ADDPROP = ../common/insert_property.py ${EF_FORMAT}
+
 # List the EDA tools to install local setup files for
 TOOLS =
 
@@ -659,7 +663,7 @@
 	rm -f ${MAGIC_STAGING_$*}/${GF180MCU$*}-BindKeys
 	rm -f ${MAGIC_STAGING_$*}/magicrc
 	if test "${EF_STYLE}" == "1" ; then \
-            (cd ${MAGICTOP_STAGING_$*} ; ln -s ${REV_DIR} current) ; \
+            (cd ${MAGICTOP_STAGING_$*} ; ln -f -s ${REV_DIR} current) ; \
 	fi
 
 	${CPP} ${GF180MCU$*_DEFS} magic/${TECH}.tech \
@@ -682,7 +686,7 @@
 	rm -f ${NETGEN_STAGING_$*}/setup.tcl
 	${CPP} ${GF180MCU$*_DEFS} netgen/${TECH}_setup.tcl \
 		${NETGEN_STAGING_$*}/${GF180MCU$*}_setup.tcl
-	(cd ${NETGEN_STAGING_$*} ; ln -s ${GF180MCU$*}_setup.tcl setup.tcl)
+	(cd ${NETGEN_STAGING_$*} ; ln -f -s ${GF180MCU$*}_setup.tcl setup.tcl)
 
 qflow-%: qflow/${TECH}.sh qflow/${TECH}.par
 	mkdir -p ${QFLOWTOP_STAGING_$*}
@@ -845,6 +849,55 @@
 		-ngspice models/ngspice/*.ngspice \
 		-xyce models/xyce/*.xyce \
 		2>&1 | tee -a ${GF180MCU$*}_make.log
+	# Install primitive device fixed layout cells from GDS
+	${STAGE} -source ${GF180MCU_PR_PATH} \
+		-target ${STAGING_PATH}/${GF180MCU$*} \
+		-gds cells/klayout/pymacros/cells/*/*.gds noextract \
+		-library primitive gf180mcu_fd_pr \
+		2>&1 | tee -a ${GF180MCU$*}_make.log
+	# The klayout GUI prefers that drc/ and lvs/ exist under tech/,
+	# so make symbolic links.
+	(cd ${STAGING_PATH}/${GF180MCU$*}/libs.tech/klayout/tech ; \
+		ln -f -s ../lvs ; ln -f -s ../drc)
+	# Add "device primitive" property to the bipolar devices and
+	# order the ports correctly to match the subcircuit model.  This
+	# ensures that the bipolar layouts extract correctly.
+	${ADDPROP} ${STAGING_PATH}/${GF180MCU$*} gf180mcu_fd_pr \
+		npn_00p54x02p00 "device primitive"
+	${PORTORDER} ${STAGING_PATH}/${GF180MCU$*} gf180mcu_fd_pr \
+		npn_00p54x02p00 I1_default_C I1_default_B I1_default_E I1_default_S
+	${ADDPROP} ${STAGING_PATH}/${GF180MCU$*} gf180mcu_fd_pr \
+		npn_00p54x04p00 "device primitive"
+	${PORTORDER} ${STAGING_PATH}/${GF180MCU$*} gf180mcu_fd_pr \
+		npn_00p54x04p00 I1_default_C I1_default_B I1_default_E I1_default_S
+	${ADDPROP} ${STAGING_PATH}/${GF180MCU$*} gf180mcu_fd_pr \
+		npn_00p54x08p00 "device primitive"
+	${PORTORDER} ${STAGING_PATH}/${GF180MCU$*} gf180mcu_fd_pr \
+		npn_00p54x08p00 I1_default_C I1_default_B I1_default_E I1_default_S
+	${ADDPROP} ${STAGING_PATH}/${GF180MCU$*} gf180mcu_fd_pr \
+		npn_00p54x16p00 "device primitive"
+	${PORTORDER} ${STAGING_PATH}/${GF180MCU$*} gf180mcu_fd_pr \
+		npn_00p54x16p00 I1_default_C I1_default_B I1_default_E I1_default_S
+	${ADDPROP} ${STAGING_PATH}/${GF180MCU$*} gf180mcu_fd_pr \
+		npn_05p00x05p00 "device primitive"
+	${PORTORDER} ${STAGING_PATH}/${GF180MCU$*} gf180mcu_fd_pr \
+		npn_05p00x05p00 I1_default_C I1_default_B I1_default_E I1_default_S
+	${ADDPROP} ${STAGING_PATH}/${GF180MCU$*} gf180mcu_fd_pr \
+		npn_10p00x10p00 "device primitive"
+	${PORTORDER} ${STAGING_PATH}/${GF180MCU$*} gf180mcu_fd_pr \
+		npn_10p00x10p00 I1_default_C I1_default_B I1_default_E I1_default_S
+	${ADDPROP} ${STAGING_PATH}/${GF180MCU$*} gf180mcu_fd_pr \
+		pnp_05p00x00p42 "device primitive"
+	${PORTORDER} ${STAGING_PATH}/${GF180MCU$*} gf180mcu_fd_pr \
+		pnp_05p00x00p42 I1_default_C I1_default_B I1_default_E
+	${ADDPROP} ${STAGING_PATH}/${GF180MCU$*} gf180mcu_fd_pr \
+		pnp_05p00x05p00 "device primitive"
+	${PORTORDER} ${STAGING_PATH}/${GF180MCU$*} gf180mcu_fd_pr \
+		pnp_05p00x05p00 I1_default_C I1_default_B I1_default_E
+	${ADDPROP} ${STAGING_PATH}/${GF180MCU$*} gf180mcu_fd_pr \
+		pnp_10p00x10p00 "device primitive"
+	${PORTORDER} ${STAGING_PATH}/${GF180MCU$*} gf180mcu_fd_pr \
+		pnp_10p00x10p00 I1_default_C I1_default_B I1_default_E
 
 digital-9t5v0-%:
         # Install 5V 9-track digital standard cells from vendor files
diff --git a/gf180mcu/magic/gf180mcu.tcl b/gf180mcu/magic/gf180mcu.tcl
index dd15fa9..9702501 100644
--- a/gf180mcu/magic/gf180mcu.tcl
+++ b/gf180mcu/magic/gf180mcu.tcl
@@ -103,7 +103,7 @@
    magic::add_toolkit_command $layoutframe "pn_3p3 - p-diode" "magic::gencell gf180mcu::pn_3p3" pdk1
 
    magic::add_toolkit_separator	$layoutframe pdk1
-   magic::add_toolkit_command $layoutframe "vnpn_5x5     (3.3V) - 5.0um^2 " "magic::gencell gf180mcu::vnpn_2x2" pdk1
+   magic::add_toolkit_command $layoutframe "XXX_5x5     (3.3V) - 5.0um^2 " "magic::gencell gf180mcu::vnpn_2x2" pdk1
    magic::add_toolkit_command $layoutframe "vnpn_5x0p42  (3.3V) - 5.0um x 0.42um " "magic::gencell gf180mcu::vnpn_5x0p42" pdk1
    magic::add_toolkit_command $layoutframe "vnpn_10x10   (3.3V) - 10.0um^2 " "magic::gencell gf180mcu::vnpn_5x5" pdk1
    magic::add_toolkit_command $layoutframe "vnpn_10x0p42 (3.3V) - 10.0um x 0.42um " "magic::gencell gf180mcu::vnpn_10x0p42" pdk1
diff --git a/gf180mcu/magic/gf180mcu.tech b/gf180mcu/magic/gf180mcu.tech
index c902ded..1f7433c 100644
--- a/gf180mcu/magic/gf180mcu.tech
+++ b/gf180mcu/magic/gf180mcu.tech
@@ -66,6 +66,8 @@
  -well obswell
 # Well resistors
   well rnw,rnwell
+  well pbase,npn
+  well nbase,pnp
 
 # Transistors
   active nmos,ntransistor,nfet
@@ -111,6 +113,7 @@
   active ppolyres,ppres,rpp
   active npolysilicide,nsresistor,nspres,rnps
   active ppolysilicide,psresistor,pspres,rpps
+  active efuse
 #ifdef HRPOLY1K
   active nhighres,nhires,hires
   active mvnhighres,mvnhires,mvhires
@@ -284,9 +287,9 @@
 
 aliases
 
-  allnwell	   nwell,rnwell
+  allnwell	   nwell,rnwell,nbase
 
-  allpsub	   space/w,pwell
+  allpsub	   space/w,pwell,pbase
 
   # Similar to allpsub* but does not include space-on-well-plane
   allpwell	   pwell
@@ -432,6 +435,9 @@
   ncap      ntransistor    ntransistor_stripes
   pcap      ptransistor    ptransistor_stripes
 
+  nbase	    nwell ntransistor_stripes
+  pbase	    pwell ptransistor_stripes
+
   mvndiff     ndiffusion     hvndiff_mask
   mvpdiff     pdiffusion     hvpdiff_mask
   mvnsd       ndiff_in_nwell hvndiff_mask
@@ -452,6 +458,7 @@
   pc        polysilicon    metal1  contact_X'es
   npolyres  polysilicon    silicide_block nselect2
   ppolyres  polysilicon    silicide_block pselect2
+  efuse	    polysilicon	   electrode
 
   pdiode    pdiffusion     pselect2
   ndiode    ndiffusion     nselect2
@@ -632,8 +639,8 @@
 #-----------------------------------------------------
 
 connect
-  nwell,*nsd,*mvnsd nwell,*nsd,*mvnsd
-  pwell,*psd,*mvpsd,isosub  pwell,*psd,*mvpsd,isosub
+  nwell,*nsd,*mvnsd,nbase,dnwell nwell,*nsd,*mvnsd,nbase,dnwell
+  pwell,*psd,*mvpsd,pbase,isosub  pwell,*psd,*mvpsd,pbase,isosub
   *psd,*mvpsd  *psd,*mvpsd
   *m1	*m1
   *m2	*m2
@@ -701,12 +708,12 @@
 #-----------------------------------------------------
 # PWELL (LVPWELL)
 #-----------------------------------------------------
- layer PWELL 	pwell
- 	labels 	pwell noport
+ layer PWELL 	allpwell
+ 	labels 	allpwell noport
  	calma 	204 0
 
  layer PWELLTXT
-	labels  pwell port
+	labels  allpwell port
 	calma	204 10
 
 #-----------------------------------------------------
@@ -721,6 +728,20 @@
 	calma	22 4
 
 #-----------------------------------------------------
+# Bipolar ID markers
+#-----------------------------------------------------
+
+ layer BJTDRC nbase
+	grow 580
+	bloat-all pbase dnwell
+	grow 20
+
+ layer BJTLVS nbase
+	grow 580
+	bloat-all pbase dnwell
+	grow 20
+
+#-----------------------------------------------------
 # PPLUS, NPLUS
 #-----------------------------------------------------
 
@@ -883,6 +904,13 @@
 	labels	fillpoly
 	calma	30 4
 
+ layer PLFUSE	efuse
+	calma	125 5
+
+ layer EFUSE	efuse
+	bloat-all efuse *poly
+	calma	80 5
+
 #-----------------------------------------------------
 # CONT
 #-----------------------------------------------------
@@ -1588,18 +1616,31 @@
 
  options ignore-unknown-layer-labels options no-reconnect-labels 
 
- ignore BJTDEF
  ignore SRAMDEF
  ignore FET5VDEF
  ignore CAPDEF
+ ignore EFUSE
+ ignore SOURCE
  ignore VTEXT
  ignore FILLOBS
 
  layer pwell PWELL,PWELLTXT
+ and-not BJTDEF,BJTDRC
+ labels PWELL
+ labels PWELLTXT port
+
+ layer pbase PWELL,PWELLTXT
+ and BJTDEF,BJTDRC
  labels PWELL
  labels PWELLTXT port
 
  layer nwell NWELL,NWELLTXT
+ and-not BJTDEF,BJTDRC
+ labels NWELL
+ labels NWELLTXT port
+
+ layer nbase NWELL,NWELLTXT
+ and BJTDEF,BJTDRC
  labels NWELL
  labels NWELLTXT port
 
@@ -1609,9 +1650,15 @@
  layer isosub SUBCUT
  labels SUBCUT
 
+ # Implicit nwell defined by DNWELL outside of PWELL
+ templayer nwelldef DNWELL
+ shrink 500
+ and-not PWELL
+ or NWELL
+
  templayer ndiffarea DIFF
  and-not POLY
- and-not NWELL
+ and-not nwelldef
  and-not PPLUS
  and-not SBLK
  and-not DUALGATE
@@ -1630,7 +1677,7 @@
 
  templayer mvndiffarea DIFF
  and-not POLY
- and-not NWELL
+ and-not nwelldef
  and-not PPLUS
  and-not SBLK
  and DUALGATE
@@ -1647,7 +1694,7 @@
  layer ndiode DIFF
  and NPLUS
  and DIODE
- and-not NWELL
+ and-not nwelldef
  and-not POLY
  and-not PPLUS
  and-not DUALGATE
@@ -1657,7 +1704,7 @@
  layer nndiode DIFF
  and NPLUS
  and DIODE
- and-not NWELL
+ and-not nwelldef
  and-not POLY
  and-not PPLUS
  and-not DUALGATE
@@ -1666,7 +1713,7 @@
 
  templayer ndiodearea DIODE
  and NPLUS
- and-not NWELL
+ and-not nwelldef
  and-not DUALGATE
  copyup DIODE,NPLUS
 
@@ -1679,7 +1726,7 @@
 
  templayer pdiffarea DIFF
  and-not POLY
- and NWELL
+ and nwelldef
  and-not NPLUS
  and-not SBLK
  and-not DIODE
@@ -1710,7 +1757,7 @@
 
  templayer mvndiodearea DIODE
  and NPLUS
- and-not NWELL
+ and-not nwelldef
  and DUALGATE
  copyup DIODE,NPLUS
 
@@ -1723,7 +1770,7 @@
 
  templayer mvpdiffarea DIFF
  and-not POLY
- and NWELL
+ and nwelldef
  and-not NPLUS
  and-not SBLK
  and-not DIODE
@@ -1815,14 +1862,14 @@
  and-not DUALGATE
  and-not NPLUS
  and-not POLY
- and NWELL
+ and nwelldef
  and pfetexpand
  labels DIFF
 
  layer pdiffres DIFF
  and-not POLY
  and PPLUS
- and NWELL
+ and nwelldef
  and SBLK
  labels DIFF
 
@@ -1830,7 +1877,7 @@
  and POLY
  and-not PPLUS
  and-not DUALGATE
- and-not NWELL
+ and-not nwelldef
  and NPLUS
  and-not NAT
  and-not MOSCAP
@@ -1840,7 +1887,7 @@
  and POLY
  and-not PPLUS
  and-not DUALGATE
- and-not NWELL
+ and-not nwelldef
  and NPLUS
  and-not NAT
  and MOSCAP
@@ -1850,14 +1897,14 @@
  and POLY
  and-not PPLUS
  and-not DUALGATE
- and-not NWELL
+ and-not nwelldef
  and NPLUS
  and NAT
  labels DIFF
 
  templayer nsdarea DIFF
  and NPLUS
- and NWELL
+ and nwelldef
  and-not POLY
  and-not PPLUS
  and-not DUALGATE
@@ -1875,7 +1922,7 @@
  templayer psdarea DIFF
  and PPLUS
  and-not DUALGATE
- and-not NWELL
+ and-not nwelldef
  and-not POLY
  and-not NPLUS
  and-not pfetexpand
@@ -1890,7 +1937,7 @@
  layer mvpdiff DIFF
  and-not NPLUS
  and-not POLY
- and NWELL
+ and nwelldef
  and DUALGATE
  and mvpfetexpand
  labels DIFF
@@ -1907,7 +1954,7 @@
  and-not PPLUS
  and NPLUS
  and-not NAT
- and-not NWELL
+ and-not nwelldef
  and DUALGATE
  and-not MOSCAP
  labels DIFF
@@ -1917,7 +1964,7 @@
  and-not PPLUS
  and NPLUS
  and-not NAT
- and-not NWELL
+ and-not nwelldef
  and DUALGATE
  and MOSCAP
  labels DIFF
@@ -1927,7 +1974,7 @@
  and-not PPLUS
  and NPLUS
  and NAT
- and-not NWELL
+ and-not nwelldef
  and DUALGATE
  labels DIFF
 
@@ -1935,7 +1982,7 @@
  and NPLUS
  and-not POLY
  and-not PPLUS
- and NWELL
+ and nwelldef
  and DUALGATE
  copyup mvnsubcheck
 
@@ -1951,7 +1998,7 @@
 
  templayer mvpsdarea DIFF
  and PPLUS
- and-not NWELL
+ and-not nwelldef
  and-not POLY
  and-not NPLUS
  and DUALGATE
@@ -1983,7 +2030,7 @@
  and-not PPLUS
  and-not NPLUS
  and-not POLY
- and NWELL
+ and nwelldef
  and-not DUALGATE
  and nsdexpand
 
@@ -1991,7 +2038,7 @@
  and-not PPLUS
  and-not NPLUS
  and-not POLY
- and-not NWELL
+ and-not nwelldef
  and DUALGATE
  and-not mvpfetexpand
  and mvpsdexpand
@@ -2000,13 +2047,14 @@
  and-not PPLUS
  and-not NPLUS
  and-not POLY
- and NWELL
+ and nwelldef
  and DUALGATE
  and mvnsdexpand
 
  templayer polyarea POLY
  and-not DIFF
  and-not SBLK
+ and-not PLFUSE
 #ifdef HRPOLY1K
  and-not HRES
 #endif (HRPOLY1K)
@@ -2054,6 +2102,11 @@
  and-not RESDEF
  labels POLY
 
+ layer efuse POLY
+ and-not DIFF
+ and PLFUSE
+ labels POLY
+
  layer rnp POLY
  and SBLK
  and NPLUS
@@ -2088,7 +2141,7 @@
  layer ndc CONT
  and DIFF
  and NPLUS
- and-not NWELL
+ and-not nwelldef
  and MET1
  and-not DUALGATE
  and-not DIODE
@@ -2098,7 +2151,7 @@
  layer nsc CONT
  and DIFF
  and NPLUS
- and NWELL
+ and nwelldef
  and MET1
  and-not DUALGATE
  and-not DIODE
@@ -2108,7 +2161,7 @@
  layer pdc CONT
  and DIFF
  and PPLUS
- and NWELL
+ and nwelldef
  and MET1
  and-not DUALGATE
  and-not DIODE
@@ -2128,7 +2181,7 @@
  layer psc CONT
  and DIFF
  and PPLUS
- and-not NWELL
+ and-not nwelldef
  and MET1
  and-not DUALGATE
  and-not DIODE
@@ -2178,7 +2231,7 @@
  layer mvndc CONT
  and DIFF
  and NPLUS
- and-not NWELL
+ and-not nwelldef
  and MET1
  and DUALGATE
  and-not DIODE
@@ -2190,7 +2243,7 @@
  and NPLUS
  and MET1
  and DUALGATE
- and NWELL
+ and nwelldef
  and-not DIODE
  grow 145
  shrink 140
@@ -2200,7 +2253,7 @@
  and PPLUS
  and MET1
  and DUALGATE
- and NWELL
+ and nwelldef
  and-not DIODE
  grow 145
  shrink 140
@@ -2218,7 +2271,7 @@
  layer mvpsc CONT
  and DIFF
  and PPLUS
- and-not NWELL
+ and-not nwelldef
  and MET1
  and DUALGATE
  and-not DIODE
@@ -2608,28 +2661,28 @@
  layer nvar POLY
  and DIFF
  and NPLUS
- and NWELL
+ and nwelldef
  and-not DUALGATE
  labels POLY
 
  layer mvnvar POLY
  and DIFF
  and NPLUS
- and NWELL
+ and nwelldef
  and DUALGATE
  labels POLY
 
  layer pvar POLY
  and DIFF
  and PPLUS
- and-not NWELL
+ and-not nwelldef
  and-not DUALGATE
  labels POLY
 
  layer mvpvar POLY
  and DIFF
  and PPLUS
- and-not NWELL
+ and-not nwelldef
  and DUALGATE
  labels POLY
 
@@ -2694,6 +2747,9 @@
 #ifdef HRPOLY1K
  calma HRES 62 0
 #endif (HRPOLY1K)
+ calma EFUSE 80 5
+ calma PLFUSE 125 5
+ calma SOURCE 100 8
  calma NAT 5 0
 #ifdef MIM
  calma CAPM 75 0
@@ -2702,6 +2758,7 @@
  calma DIODE  115 5
  calma CAPDEF 117 5
  calma BJTDEF 118 5
+ calma BJTDRC 127 5
  calma MOSCAP 166 5
  calma BOUND 0 0
  calma PRBOUND 63 0
@@ -4675,6 +4732,8 @@
 #  cap_pmos_06v0_b	mosfet   (p-varactor, high voltage)
 #
 #  cap_mim_2f0_mXmY_noshield	capacitor (MiM)*,**
+#
+#  efuse		fuse
 
 #
 # *Note that there are multiple mutually exclusive process options for the
@@ -4711,6 +4770,8 @@
  device subcircuit cap_pmos_06v0 mvpcap mvpdiff,mvpdc l=c_length w=c_width
  device subcircuit cap_nmos_06v0 mvncap mvndiff,mvndc l=c_length w=c_width
 
+ device rsubcircuit efuse efuse *poly
+
  device rsubcircuit rm1 rm1 *m1 l=r_length w=r_width
  device rsubcircuit rm2 rm2 *m2 l=r_length w=r_width
 #ifdef METALS4 || METALS5 || METALS6
diff --git a/gf180mcu/magic/gf180mcu_make_torture.tcl b/gf180mcu/magic/gf180mcu_make_torture.tcl
index 7a28a6e..dc1d3aa 100644
--- a/gf180mcu/magic/gf180mcu_make_torture.tcl
+++ b/gf180mcu/magic/gf180mcu_make_torture.tcl
@@ -43,7 +43,7 @@
          if {[rand] > 0.5} {set gt 1} else {set gt 0}
          if {[rand] > 0.5} {set gb 1} else {set gb 0}
 
-         magic::gencell efgf013::${devname} ${devname}_$i w $w l $l m $m nf $nf diffcov $dcov polycov $pcov rlcov $rlcov poverlap $pov doverlap $dov topc $tc botc $bc full_metal $fm glc $gl grc $gr gbc $gb gtc $gt
+         magic::gencell gf180mcu::${devname} ${devname}_$i w $w l $l m $m nf $nf diffcov $dcov polycov $pcov rlcov $rlcov poverlap $pov doverlap $dov topc $tc botc $bc full_metal $fm glc $gl grc $gr gbc $gb gtc $gt
          select cell ${devname}_$i
          set bh [box height]
          set bh [+ $bh 124]
@@ -85,7 +85,7 @@
          if {[rand] > 0.5} {set gt 1} else {set gt 0}
          if {[rand] > 0.5} {set gb 1} else {set gb 0}
 
-         magic::gencell efgf013::${devname} ${devname}_$i w $w l $l m $m nx $nx endcov $ecov roverlap $rov snake $sn full_metal $fm glc $gl grc $gr gbc $gb gtc $gt
+         magic::gencell gf180mcu::${devname} ${devname}_$i w $w l $l m $m nx $nx endcov $ecov roverlap $rov snake $sn full_metal $fm glc $gl grc $gr gbc $gb gtc $gt
          select cell ${devname}_$i
          set bh [box height]
          set bh [+ $bh 124]
@@ -127,7 +127,7 @@
          if {[rand] > 0.5} {set gt 1} else {set gt 0}
          if {[rand] > 0.5} {set gb 1} else {set gb 0}
 
-         magic::gencell efgf013::${devname} ${devname}_$i w $w l $l nx $nx ny $ny doverlap $dov full_metal $fm elc $el erc $er etc $et ebc $eb glc $gl grc $gr gbc $gb gtc $gt
+         magic::gencell gf180mcu::${devname} ${devname}_$i w $w l $l nx $nx ny $ny doverlap $dov full_metal $fm elc $el erc $er etc $et ebc $eb glc $gl grc $gr gbc $gb gtc $gt
          select cell ${devname}_$i
          set bh [box height]
          set bh [+ $bh 124]
@@ -161,7 +161,7 @@
          if {[rand] > 0.5} {set bc 1} else {set bc 0}
          if {[rand] > 0.5} {set tc 1} else {set tc 0}
 
-         magic::gencell efgf013::${devname} ${devname}_$i w $w l $l nx $nx ny $ny bconnect $bc tconnect $tc
+         magic::gencell gf180mcu::${devname} ${devname}_$i w $w l $l nx $nx ny $ny bconnect $bc tconnect $tc
          select cell ${devname}_$i
          set bh [box height]
          set bh [+ $bh 160]
@@ -195,7 +195,7 @@
          # set r [int [* [rand] 10]]
          set deltay [/ $r 10.0]
 
-         magic::gencell efgf013::${devname} ${devname}_$i nx $nx ny $ny deltax $deltax deltay $deltay
+         magic::gencell gf180mcu::${devname} ${devname}_$i nx $nx ny $ny deltax $deltax deltay $deltay
          select cell ${devname}_$i
          set bh [box height]
          set bh [* $bh [+ $ny 1]]
@@ -225,16 +225,16 @@
 #
 
 
-mos_array 6 nmos_1p2 0 0
-mos_array 6 pmos_1p2 0 75000
-mos_array 6 nmos_3p3 0 150000 
-mos_array 6 pmos_3p3 0 225000
-mos_array 6 pmos_1p2_lvt 0 300000
-mos_array 6 pmos_1p2_hvt 0 375000
-mos_array 6 nmos_1p2_lvt 0 450000
-mos_array 6 nmos_1p2_hvt 0 525000
-mos_array 6 nmos_1p2_nat 0 600000
-mos_array 6 nmos_3p3_nat 0 675000
+mos_array 6 nmos_3p3 0 0
+mos_array 6 pmos_3p3 0 75000
+mos_array 6 nmos_6p0 0 150000 
+mos_array 6 pmos_6p0 0 225000
+mos_array 6 pmos_3p3_lvt 0 300000
+mos_array 6 pmos_3p3_hvt 0 375000
+mos_array 6 nmos_3p3_lvt 0 450000
+mos_array 6 nmos_3p3_hvt 0 525000
+mos_array 6 nmos_3p3_nat 0 600000
+mos_array 6 nmos_6p0_nat 0 675000
 
 res_array 6 nplus_u 100000 0 
 res_array 6 pplus_u 100000 180000
diff --git a/gf180mcu/netgen/gf180mcu_setup.tcl b/gf180mcu/netgen/gf180mcu_setup.tcl
index 137e376..6248733 100644
--- a/gf180mcu/netgen/gf180mcu_setup.tcl
+++ b/gf180mcu/netgen/gf180mcu_setup.tcl
@@ -466,4 +466,17 @@
     }
 }
 
+# Allow parallel reduction of fillcap (decap fill) cells
+
+foreach cell $cells1 {
+    if {[regexp {.*gf180mcu_fd_sc_.*__fillcap_[[:digit:]]+} $cell match]} {
+	property "-circuit1 $cell" parallel enable
+    }
+}
+
+foreach cell $cells2 {
+    if {[regexp {gf180mcu_fd_sc_.*__fillcap_[[:digit:]]+} $cell match]} {
+	property "-circuit2 $cell" parallel enable
+    }
+}
 #---------------------------------------------------------------