tree 7cd41309deca93360b2ea24d7b5785e37ddf32ad
parent 0059588eebfc704681dc2368bd1d33d96281d10f
author Tim Edwards <tim@opencircuitdesign.com> 1666897132 -0400
committer Tim Edwards <tim@opencircuitdesign.com> 1666897132 -0400

A number of changes in support of correctly reading and extracting the
SkyWater I/O cells.  This set of patches has been a long time in coming!
(1) Corrected the vendor cells for the VDDIO and VSSIO pads such that
the metal3 area under VDDIO_Q and VSSIO_Q, respectively, is separated
by metal resistors.  This allows the overlay cell to contact the
domains while keeping the net names separate.  Changed the SPICE and
CDL netlists to add the metal resistor devices.  (2) Corrected an
issue in the magic tech file that caused some high voltage transistors
in the I/O to get split.  (3) Corrected the netlist for the hvsbt_nor
cell, which had an incorrect count of pFET transistors (each device
has M=2, not M=1).  (4) Modified the netgen entries for metal resistors
to allow a very large tolerance for L and W, based on the assumption
that these are net-splitters, not devices.  This avoids the need to
track down each one and ensure its W and L is correct.  (5) Created an
import Tcl script for the vendor GPIO library that flattens specific
cells to ensure that devices are correctly generated.  (6) Corrected
the units for diodes created by magic's extractor to match the
(bizarre) model units.  (7) Corrected a couple of port ordering issues
in the netlists for the Efabless combined overlay I/O cells.  The
bottom line is that it is now possible to read in the I/O cell library
and extract an LVS clean netlist from a layout using the SkyWater I/O
pads.