diff --git a/.gitignore b/.gitignore
index 7fe9b79..20d39f4 100644
--- a/.gitignore
+++ b/.gitignore
@@ -9,6 +9,7 @@
 # script artifacts
 *_install.log
 *_migrate.log
+make.log
 
 # autotools artifacts
 **/Makefile
diff --git a/VERSION b/VERSION
index 0a897c0..e4882a8 100644
--- a/VERSION
+++ b/VERSION
@@ -1 +1 @@
-1.0.321
+1.0.322
diff --git a/common/foundry_install.py b/common/foundry_install.py
index 250635c..99123b4 100755
--- a/common/foundry_install.py
+++ b/common/foundry_install.py
@@ -2225,17 +2225,25 @@
                     print('ext2spice cthresh 0.1', file=ofile)
 
                 if os.path.isfile(allgdslibname):
-                    print('select top cell', file=ofile)
-                    print('set glist [cellname list children]', file=ofile)
-                    print('foreach cell $glist {', file=ofile)
+                    # Do not depend absolutely on the library having a top
+                    # level cell, but query for it from inside magic
+                    print('if {[cellname list exists ' + allgdslibname + ']} {',
+				file=ofile)
+                    print('   select top cell', file=ofile)
+                    print('   set glist [cellname list children]', file=ofile)
+                    print('} else {', file=ofile)
+                    print('   set glist [cellname list top]', file=ofile)
+                    print('}', file=ofile)
                 else:
-                    print('foreach cell [cellname list top] {', file=ofile)
+                    print('set glist [cellname list top]', file=ofile)
 
+                print('foreach cell $glist {', file=ofile)
                 print('    load $cell', file=ofile)
                 print('    puts stdout "Extracting cell $cell"', file=ofile)
                 print('    extract all', file=ofile)
                 print('    ext2spice', file=ofile)
                 print('}', file=ofile)
+
                 print('puts stdout "Done."', file=ofile)
                 print('quit -noprompt', file=ofile)
 
diff --git a/common/save_commit_refs.py b/common/save_commit_refs.py
index 3987db1..c226313 100755
--- a/common/save_commit_refs.py
+++ b/common/save_commit_refs.py
@@ -12,7 +12,7 @@
 # section is fixed and is not modified by replacement like the
 # rest of the JSON file.  It is the duty of the PDK developer to
 # update the references section periodically by running "make
-# distribution".
+# reference".
 #
 #--------------------------------------------------------------------
 # Usage:
@@ -41,7 +41,7 @@
 # contents.
 #
 # Example:
-#	sky130.json has an entry in "distribution":
+#	sky130.json has an entry in "reference":
 #		"magic": "fe2eb6d3906ed15ade0e7a51daea80dd4e3846e2"
 #	reflecting the git commit number of the program "magic" at
 #	the time the developer last ran save_commit_refs.py.
@@ -49,7 +49,7 @@
 #		"magic": "MAGIC_COMMIT"
 #	If save_commit_refs.py is called as:
 #		save_commit_refs.py sky130.json -DMAGIC_COMMIT=abcdef
-#	then the line in "distribution" will be changed to:
+#	then the line in "reference" will be changed to:
 #		"magic": "abcdef"
 #
 #--------------------------------------------------------------------
@@ -92,7 +92,7 @@
         newline = line
 
         if indist == False:
-            if '"distribution":' in line:
+            if '"reference":' in line:
                 indist = True
             else:
                 # Find values matching keywords
diff --git a/gf180mcu/.gitignore b/gf180mcu/.gitignore
new file mode 100644
index 0000000..1848907
--- /dev/null
+++ b/gf180mcu/.gitignore
@@ -0,0 +1,5 @@
+*.log
+gf180mcuA
+gf180mcuB
+gf180mcuC
+/Makefile
\ No newline at end of file
diff --git a/gf180mcu/Makefile.in b/gf180mcu/Makefile.in
new file mode 100644
index 0000000..8f78f7a
--- /dev/null
+++ b/gf180mcu/Makefile.in
@@ -0,0 +1,931 @@
+# Makefile for Efabless design kits for gf180mcu:
+#
+# This file supports all the process options including 2 to 6 metals,
+# and multiple thicknesses of the top metal.  The three PDKs generated by
+# the Makefile represent the three backend options for which the I/O library
+# has layout, which are, namely, 3-, 4-, and 5- metal options.
+#
+# Important note about the process:  GF180MCU uses the same base process as
+# other GF180 processes.  However, instead of a thin oxide gate, the base
+# oxide is a thick oxide, and the thick oxide mask defines a thicker oxide.
+# The process DRC rules then follow the rule sets for thick oxide devices,
+# so the minimum length transistor is 280nm, making this much more like a
+# 0.28um process than a 0.18um process.
+#
+# Notes about definitions:
+# METALSN means N layers of metal, where N can be 2 to 6.
+# THICKMET3P0 means that the top metal is 3.0um thick
+# THICKMET1P1 means that the top metal is 1.1um thick
+# THICKMET0P9 means that the top metal is 0.9um thick
+# Otherwise, the top metal is 0.6um thick
+# Always use exactly one "METALSN" option (N = 4 to 6).
+#
+# NOTE:  Using "METALSN" instead of "METALN" because "METALN" are the preferred
+# layer names in the technology LEF file.
+#
+# MIM means that the MiM cap is defined between top metal and the one below.
+# The process defines a "MIM OPT A" with the MiM cap between metals 3 and 2.
+# Because this option is only available with METALS4 (For METALS3 options A
+# and B are the same), it is not being implemented.
+#
+# MIM caps are mutually-exclusive-selectable 1fF, 1.5fF, or 2fF per um^2.
+# For simplicity, this file assumes the 2fF per um^2 value.
+#
+# HRPOLY1K defines the 1K high sheet rho poly resistor.
+#
+# Not all combinations of options are valid.  Global Foundries defines the
+# following combinations as valid (adjusting for the decision not to
+# implement MIM OPT A):
+#
+# METALS2 + THICKMET3P0
+#
+# METALS3 + MIM
+# METALS3 + MIM + THICKMET0P9
+# METALS3 + MIM + THICKMET1P1
+# METALS3 + MIM + THICKMET3P0
+#
+# METALS4 + MIM + THICKMET0P9
+# METALS4 + MIM + THICKMET1P1
+# METALS4 + MIM + THICKMET3P0
+#
+# METALS5 + MIM + THICKMET0P9
+# METALS5 + MIM + THICKMET1P1
+#
+# METALS6 + MIM + THICKMET0P9
+#
+#------------------------------------------------------------------------------
+#
+# The defined options per PDK in this file are:
+#
+#  gf180mcuA   =  METALS3 | MIM | THICKMET3P0 | HRPOLY1K
+#  gf180mcuB   =  METALS4 | MIM | THICKMET1P1 | HRPOLY1K
+#  gf180mcuC   =  METALS5 | MIM | THICKMET0P9 | HRPOLY1K
+#
+# Written by Tim Edwards April 2022
+# Efabless, Inc.
+#
+#--------------------------------------------------------------------
+# This Makefile contains bash-isms
+SHELL := /bin/bash
+export SHELL
+# We use pipes to save output to files, without pipefail they will always be
+# seen by make as having succeeded.
+SHELLOPTS := pipefail
+export SHELLOPTS
+MV = mv
+PATCH = patch
+SED = @SED@
+
+prefix = @prefix@
+datarootdir = @datarootdir@
+datadir = @datadir@
+
+# Find path to open_pdks (even though this directory may be a symbolic link)
+SCRIPTSDIR = $(patsubst %/gf180mcu,%,$(PWD))
+
+# Use git revision if this is a cloned repo;  otherwise get the revision
+# from the VERSION file in the directory above.
+GITREV = $(shell git describe --long)
+ifeq (${GITREV},)
+    REVISION = $(shell cat ${SCRIPTSDIR}/VERSION)
+else
+    REVISION = ${GITREV}
+endif
+TECH = gf180mcu
+
+# The run-time environment uses PDKPATH to override the PDK location,
+# so prevent that from happening during PDK install.  This will also
+# happen with PDK_ROOT, so avoid that as well.
+unexport PDKPATH
+unexport PDK_ROOT
+
+# If EF_STYLE is set to 1, then efabless naming conventions are
+# used, otherwise the generic naming conventions are used.
+# Mainly this has to do with where the technology LEF files are
+# put (libs.tech/lef/ vs. libs.ref/techLEF).
+
+# EF_STYLE = 0 | 1
+EF_STYLE = @EF_STYLE@
+
+# Normally it's fine to keep the staging path in a local directory,
+# although /tmp or a dedicated staging area are also fine, as long
+# as the install process can write to the path.
+
+STAGING_PATH = $(shell pwd)
+
+SHARED_PDKS_PATH ?= $(datadir)/pdk
+
+# If LINK_TARGETS is set to "none", then files are copied
+# from the SkyWater sources to the target.  If set to "source",
+# symbolic links are made in the target directories pointing
+# back to the SkyWater sources.  If set to the name of another
+# PDK (e.g, "sky130A"), then symbolic links are made to the
+# same files in that PDK, where they exist, and are copied
+# from source, where they don't.
+#
+# Behavior is to let the link targets for variant A follow the
+# configuration option.  Link targets for variant B will always
+# be the files of variant A (which may end up being symbolic
+# links to symbolic links if "source" was chosen for link-targets
+# in the configuration).
+
+# LINK_TARGETS = source | none | gf180mcuA
+LINK_TARGETS_A = @GF180MCU_LINK_TARGETS@
+LINK_TARGETS_B = gf180mcuA
+LINK_TARGETS_C = gf180mcuA
+
+# ENABLED_VARIANTS = all | A | B | C
+ENABLED_VARIANTS = @GF180MCU_ENABLED_VARIANTS@
+ifeq (${ENABLED_VARIANTS},)
+	VARIANTS += A B C
+else
+    ifeq (${ENABLED_VARIANTS}, all)
+	VARIANTS += A B C
+    else
+	VARIANTS += ${ENABLED_VARIANTS}
+    endif
+endif
+
+# Paths:
+
+# Path to GF180MCU open PDK sources.  If this is specified, then all
+# library repositories must be subdirectories of this path.
+GF180MCU_PR_PATH = @GF180MCU_FD_PR_PATH@
+GF180MCU_IO_PATH = @GF180MCU_FD_IO_PATH@
+GF180MCU_SC_7T5V0_PATH = @GF180MCU_FD_SC_MCU7T5V0_PATH@
+GF180MCU_SC_9T5V0_PATH = @GF180MCU_FD_SC_MCU9T5V0_PATH@
+GF180MCU_SRAM_PATH = @GF180MCU_FD_IP_SRAM_PATH@
+
+# Path to GF180MCU library sources
+PDK_URL = https://github.com/google
+
+# Names of library repositories
+PDK_LIB_PR =       ${PDK_URL}/globalfoundries-pdk-libs-gf180mcu_fd_pr
+PDK_LIB_IO =       ${PDK_URL}/globalfoundries-pdk-libs-gf180mcu_fd_io
+PDK_LIB_SC_7T5V0 = ${PDK_URL}/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0
+PDK_LIB_SC_9T5V0 = ${PDK_URL}/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0
+PDK_LIB_SRAM =     ${PDK_URL}/globalfoundries-pdk-ip-gf180mcu_fd_ip_sram
+
+# NOTE:  Install destination is the git repository of the technology platform.
+# Once updated in git, the git project can be distributed to all hosts.
+#
+ifeq (${EF_STYLE}, 1)
+    CONFIG_DIR = .ef-config
+    REV_DIR = ${REVISION}
+else
+    CONFIG_DIR = .config
+    REV_DIR = .
+endif
+
+# Process nodes created from the master sources
+GF180MCUA = gf180mcuA
+GF180MCUB = gf180mcuB
+GF180MCUC = gf180mcuC
+
+DIST_LINK_TARGETS_A = ${LINK_TARGETS_A}
+DIST_LINK_TARGETS_B = ${SHARED_PDKS_PATH}/${LINK_TARGETS_B}
+DIST_LINK_TARGETS_C = ${SHARED_PDKS_PATH}/${LINK_TARGETS_C}
+
+# Basic definitions for each process node
+GF180MCUA_DEFS = -DTECHNAME=gf180mcuA -DREVISION=${REVISION}
+GF180MCUB_DEFS = -DTECHNAME=gf180mcuB -DREVISION=${REVISION}
+GF180MCUC_DEFS = -DTECHNAME=gf180mcuC -DREVISION=${REVISION}
+
+# Module definitions for each process node (see top)
+GF180MCUA_DEFS += -DMETALS3 -DMIM -DTHICKMET3P0 -DHRPOLY1K
+GF180MCUB_DEFS += -DMETALS4 -DMIM -DTHICKMET1P1 -DHRPOLY1K
+GF180MCUC_DEFS += -DMETALS5 -DMIM -DTHICKMET0P9 -DHRPOLY1K
+
+# Add staging path
+GF180MCUA_DEFS += -DSTAGING_PATH=${STAGING_PATH}
+GF180MCUB_DEFS += -DSTAGING_PATH=${STAGING_PATH}
+GF180MCUC_DEFS += -DSTAGING_PATH=${STAGING_PATH}
+
+# Get the timestamp of the open_pdks commit to use for stamping layouts.
+OPEN_PDKS_TIMESTAMP = $(shell git log -1 --format="%ad" --date=raw | cut -d' ' -f1)
+TIMESTAMP_OPT = -timestamp ${OPEN_PDKS_TIMESTAMP}
+
+# Record commit numbers for the nodeinfo.json file
+OPEN_PDKS_COMMIT = $(shell git rev-parse HEAD)
+ifeq (${OPEN_PDKS_COMMIT},)
+    COMMIT_DEFS = -DOPEN_PDKS_COMMIT=${REVISION}
+else
+    COMMIT_DEFS = -DOPEN_PDKS_COMMIT=${OPEN_PDKS_COMMIT}
+endif
+
+ifeq (${GF180MCU_SC_9T5V0_PATH},)
+    COMMIT_DEFS += -DFD_SC_MCU9T5V0_COMMIT="unknown"
+else
+    COMMIT_DEFS += -DFD_SC_MCU9T5V0_COMMIT=$(shell cd ${GF180MCU_SC_9T5V0_PATH} ; git rev-parse HEAD)
+endif
+ifeq (${GF180MCU_SC_7T5V0_PATH},)
+    COMMIT_DEFS += -DFD_SC_MCU7T5V0_COMMIT="unknown"
+else
+    COMMIT_DEFS += -DFD_SC_MCU7T5V0_COMMIT=$(shell cd ${GF180MCU_SC_7T5V0_PATH} ; git rev-parse HEAD)
+endif
+ifeq (${GF180MCU_PR_PATH},)
+    COMMIT_DEFS += -DFD_PR_COMMIT="unknown"
+else
+    COMMIT_DEFS += -DFD_PR_COMMIT=$(shell cd ${GF180MCU_PR_PATH} ; git rev-parse HEAD)
+endif
+ifeq (${GF180MCU_IO_PATH},)
+    COMMIT_DEFS += -DFD_IO_COMMIT="unknown"
+else
+    COMMIT_DEFS += -DFD_IO_COMMIT=$(shell cd ${GF180MCU_IO_PATH} ; git rev-parse HEAD)
+endif
+ifeq (${GF180MCU_SRAM_PATH},)
+    COMMIT_DEFS += -DFD_IP_SRAM_COMMIT="unknown"
+else
+    COMMIT_DEFS += -DFD_IP_SRAM_COMMIT=$(shell cd ${GF180MCU_SRAM_PATH} ; git rev-parse HEAD)
+endif
+
+COMMIT_DEFS += -DMAGIC_COMMIT=$(shell magic -dnull -noconsole --commit)
+COMMIT_DEFS += -DMAGIC_VERSION=$(shell magic -dnull -noconsole --version)
+COMMIT_DEFS += -DOPEN_PDKS_VERSION=$(shell cat ${SCRIPTSDIR}/VERSION)
+
+ifeq (${EF_STYLE}, 1)
+    EF_FORMAT = -ef_format
+    GF180MCUA_DEFS += -DEF_FORMAT
+    GF180MCUB_DEFS += -DEF_FORMAT
+    GF180MCUC_DEFS += -DEF_FORMAT
+else
+    EF_FORMAT = -std_format
+endif
+
+MAGICTOP = libs.tech/magic
+NETGENTOP = libs.tech/netgen
+QFLOWTOP = libs.tech/qflow
+IRSIMTOP = libs.tech/irsim
+KLAYOUTTOP = libs.tech/klayout
+OPENLANETOP = libs.tech/openlane
+XSCHEMTOP = libs.tech/xschem
+XCIRCUITTOP = libs.tech/xcircuit
+NGSPICETOP = libs.tech/ngspice
+
+ifeq (${EF_STYLE}, 1)
+    MAGICPATH = ${MAGICTOP}/${REVISION}
+    MAGIC_CURRENT = ${MAGICTOP}/current
+else
+    MAGICPATH = ${MAGICTOP}
+    MAGIC_CURRENT = ${MAGICTOP}
+endif
+
+NETGENPATH = ${NETGENTOP}
+IRSIMPATH = ${IRSIMTOP}
+QFLOWPATH = ${QFLOWTOP}
+KLAYOUTPATH = ${KLAYOUTTOP}
+OPENLANEPATH = ${OPENLANETOP}
+XSCHEMPATH = ${XSCHEMTOP}
+XCIRCUITPATH = ${XCIRCUITTOP}
+NGSPICEPATH = ${NGSPICETOP}
+
+MAGICTOP_STAGING_A = ${STAGING_PATH}/${GF180MCUA}/${MAGICTOP}
+NETGENTOP_STAGING_A = ${STAGING_PATH}/${GF180MCUA}/${NETGENTOP}
+IRSIMTOP_STAGING_A = ${STAGING_PATH}/${GF180MCUA}/${IRSIMTOP}
+QFLOWTOP_STAGING_A = ${STAGING_PATH}/${GF180MCUA}/${QFLOWTOP}
+KLAYOUTTOP_STAGING_A = ${STAGING_PATH}/${GF180MCUA}/${KLAYOUTTOP}
+OPENLANETOP_STAGING_A = ${STAGING_PATH}/${GF180MCUA}/${OPENLANETOP}
+XSCHEMTOP_STAGING_A = ${STAGING_PATH}/${GF180MCUA}/${XSCHEMTOP}
+XCIRCUITTOP_STAGING_A = ${STAGING_PATH}/${GF180MCUA}/${XCIRCUITTOP}
+NGSPICETOP_STAGING_A = ${STAGING_PATH}/${GF180MCUA}/${NGSPICETOP}
+
+MAGIC_STAGING_A = ${STAGING_PATH}/${GF180MCUA}/${MAGICPATH}
+NETGEN_STAGING_A = ${STAGING_PATH}/${GF180MCUA}/${NETGENPATH}
+IRSIM_STAGING_A = ${STAGING_PATH}/${GF180MCUA}/${IRSIMPATH}
+QFLOW_STAGING_A = ${STAGING_PATH}/${GF180MCUA}/${QFLOWPATH}
+KLAYOUT_STAGING_A = ${STAGING_PATH}/${GF180MCUA}/${KLAYOUTPATH}
+OPENLANE_STAGING_A = ${STAGING_PATH}/${GF180MCUA}/${OPENLANEPATH}
+XSCHEM_STAGING_A = ${STAGING_PATH}/${GF180MCUA}/${XSCHEMPATH}
+XCIRCUIT_STAGING_A = ${STAGING_PATH}/${GF180MCUA}/${XCIRCUITPATH}
+NGSPICE_STAGING_A = ${STAGING_PATH}/${GF180MCUA}/${NGSPICEPATH}
+
+MAGICTOP_STAGING_B = ${STAGING_PATH}/${GF180MCUB}/${MAGICTOP}
+NETGENTOP_STAGING_B = ${STAGING_PATH}/${GF180MCUB}/${NETGENTOP}
+IRSIMTOP_STAGING_B = ${STAGING_PATH}/${GF180MCUB}/${IRSIMTOP}
+QFLOWTOP_STAGING_B = ${STAGING_PATH}/${GF180MCUB}/${QFLOWTOP}
+KLAYOUTTOP_STAGING_B = ${STAGING_PATH}/${GF180MCUB}/${KLAYOUTTOP}
+OPENLANETOP_STAGING_B = ${STAGING_PATH}/${GF180MCUB}/${OPENLANETOP}
+XSCHEMTOP_STAGING_B = ${STAGING_PATH}/${GF180MCUB}/${XSCHEMTOP}
+XCIRCUITTOP_STAGING_B = ${STAGING_PATH}/${GF180MCUB}/${XCIRCUITTOP}
+NGSPICETOP_STAGING_B = ${STAGING_PATH}/${GF180MCUB}/${NGSPICETOP}
+
+MAGIC_STAGING_B = ${STAGING_PATH}/${GF180MCUB}/${MAGICPATH}
+NETGEN_STAGING_B = ${STAGING_PATH}/${GF180MCUB}/${NETGENPATH}
+IRSIM_STAGING_B = ${STAGING_PATH}/${GF180MCUB}/${IRSIMPATH}
+QFLOW_STAGING_B = ${STAGING_PATH}/${GF180MCUB}/${QFLOWPATH}
+KLAYOUT_STAGING_B = ${STAGING_PATH}/${GF180MCUB}/${KLAYOUTPATH}
+OPENLANE_STAGING_B = ${STAGING_PATH}/${GF180MCUB}/${OPENLANEPATH}
+XSCHEM_STAGING_B = ${STAGING_PATH}/${GF180MCUB}/${XSCHEMPATH}
+XCIRCUIT_STAGING_B = ${STAGING_PATH}/${GF180MCUB}/${XCIRCUITPATH}
+NGSPICE_STAGING_B = ${STAGING_PATH}/${GF180MCUB}/${NGSPICEPATH}
+
+MAGICTOP_STAGING_C = ${STAGING_PATH}/${GF180MCUC}/${MAGICTOP}
+NETGENTOP_STAGING_C = ${STAGING_PATH}/${GF180MCUC}/${NETGENTOP}
+IRSIMTOP_STAGING_C = ${STAGING_PATH}/${GF180MCUC}/${IRSIMTOP}
+QFLOWTOP_STAGING_C = ${STAGING_PATH}/${GF180MCUC}/${QFLOWTOP}
+KLAYOUTTOP_STAGING_C = ${STAGING_PATH}/${GF180MCUC}/${KLAYOUTTOP}
+OPENLANETOP_STAGING_C = ${STAGING_PATH}/${GF180MCUC}/${OPENLANETOP}
+XSCHEMTOP_STAGING_C = ${STAGING_PATH}/${GF180MCUC}/${XSCHEMTOP}
+XCIRCUITTOP_STAGING_C = ${STAGING_PATH}/${GF180MCUC}/${XCIRCUITTOP}
+NGSPICETOP_STAGING_C = ${STAGING_PATH}/${GF180MCUC}/${NGSPICETOP}
+
+MAGIC_STAGING_C = ${STAGING_PATH}/${GF180MCUC}/${MAGICPATH}
+NETGEN_STAGING_C = ${STAGING_PATH}/${GF180MCUC}/${NETGENPATH}
+IRSIM_STAGING_C = ${STAGING_PATH}/${GF180MCUC}/${IRSIMPATH}
+QFLOW_STAGING_C = ${STAGING_PATH}/${GF180MCUC}/${QFLOWPATH}
+KLAYOUT_STAGING_C = ${STAGING_PATH}/${GF180MCUC}/${KLAYOUTPATH}
+OPENLANE_STAGING_C = ${STAGING_PATH}/${GF180MCUC}/${OPENLANEPATH}
+XSCHEM_STAGING_C = ${STAGING_PATH}/${GF180MCUC}/${XSCHEMPATH}
+XCIRCUIT_STAGING_C = ${STAGING_PATH}/${GF180MCUC}/${XCIRCUITPATH}
+NGSPICE_STAGING_C = ${STAGING_PATH}/${GF180MCUC}/${NGSPICEPATH}
+
+GF180MCUA_DEFS += -DMAGIC_CURRENT=${MAGIC_CURRENT}
+GF180MCUB_DEFS += -DMAGIC_CURRENT=${MAGIC_CURRENT}
+GF180MCUC_DEFS += -DMAGIC_CURRENT=${MAGIC_CURRENT}
+
+# These definitions are used by the build recipes
+A_STACK = 3lm
+B_STACK = 4lm
+C_STACK = 5lm
+
+# These definitions are used by the build recipes for the tech LEF
+A_FULLSTACK = 3LM_1TM_30K
+B_FULLSTACK = 4LM_1TM_11K
+C_FULLSTACK = 5LM_1TM_9K
+
+# Openlane has a number of files that are common to all digital
+# standard cell libraries, so these are collected in one definition
+# here:
+OPENLANE_COMMON = config.tcl tracks.info no_synth.cells drc_exclude.cells
+
+# Where cpp syntax is followed, this is equivalent to cpp, but it does not
+# mangle non-C source files under the belief that they are actually C code.
+CPP   = ${SCRIPTSDIR}/common/preproc.py
+
+# The following script in the ${SCRIPTSDIR}/common directory does most of the work of
+# copying or linking the foundry vendor files to the target directory.
+STAGE = set -f ; ${SCRIPTSDIR}/common/foundry_install.py ${EF_FORMAT} ${TIMESTAMP_OPT}
+ifneq ($(DESTDIR), )
+INSTALL = ${SCRIPTSDIR}/common/staging_install.py -writeto $(DESTDIR) ${EF_FORMAT}
+else
+INSTALL = ${SCRIPTSDIR}/common/staging_install.py ${EF_FORMAT}
+endif
+
+# List the EDA tools to install local setup files for
+TOOLS =
+
+# KLAYOUT_DISABLED = 0 | 1
+KLAYOUT_DISABLED = @KLAYOUT_DISABLED@
+ifneq (${KLAYOUT_DISABLED}, 1)
+        TOOLS += klayout
+endif
+
+# OPENLANE_DISABLED = 0 | 1
+OPENLANE_DISABLED = @OPENLANE_DISABLED@
+ifneq (${OPENLANE_DISABLED}, 1)
+        TOOLS += openlane
+endif
+
+# QFLOW_DISABLED = 0 | 1
+QFLOW_DISABLED = @QFLOW_DISABLED@
+ifneq (${QFLOW_DISABLED}, 1)
+        TOOLS += qflow
+endif
+
+# MAGIC_DISABLED = 0 | 1
+MAGIC_DISABLED = @MAGIC_DISABLED@
+ifneq (${MAGIC_DISABLED}, 1)
+        TOOLS += magic
+endif
+
+# NETGEN_DISABLED = 0 | 1
+NETGEN_DISABLED = @NETGEN_DISABLED@
+ifneq (${NETGEN_DISABLED}, 1)
+        TOOLS += netgen
+endif
+
+# IRSIM_DISABLED = 0 | 1
+IRSIM_DISABLED = @IRSIM_DISABLED@
+ifneq (${IRSIM_DISABLED}, 1)
+        TOOLS += irsim
+endif
+
+# XSCHEM_DISABLED = 0 | 1
+XSCHEM_DISABLED = @XSCHEM_DISABLED@
+ifneq (${XSCHEM_DISABLED}, 1)
+        TOOLS += xschem
+endif
+
+# XCIRCUIT_DISABLED = 0 | 1
+XCIRCUIT_DISABLED = @XCIRCUIT_DISABLED@
+ifneq (${XCIRCUIT_DISABLED}, 1)
+        TOOLS += xcircuit
+endif
+
+reference: ${TECH}.json
+	# Rewrite the ${TECH}.json file to change the commit values in
+	# "reference" to reflect the state of the system when  "make
+	# reference" was run.  This is then committed to the open_pdks
+	# repository to create a known reference configuration of all
+	# tools.
+	../common/save_commit_refs.py ${COMMIT_DEFS} ${TECH}.json
+
+all: $(foreach var, ${VARIANTS}, all-$(var))
+
+# Handle prerequisites
+prerequisites: pr-repo io-repo sc-7t-repo sc-9t-repo sram-repo
+
+pr-repo:
+	if test "x${GF180MCU_PR_PATH}" != "x" ; then \
+		if test -d "${GF180MCU_PR_PATH}" ; then \
+			echo "Using existing installation of primitive library from ${GF180MCU_PR_PATH}" ; \
+		else \
+			echo "Downloading primitive library from ${GF180MCU_PR_PATH}" ; \
+			../scripts/download.sh ${PDK_LIB_PR} ${GF180MCU_PR_PATH} ; \
+		fi ; \
+	fi
+
+io-repo:
+	if test "x${GF180MCU_IO_PATH}" != "x" ; then \
+		if test -d "${GF180MCU_IO_PATH}" ; then \
+			echo "Using existing installation of I/O library from ${GF180MCU_IO_PATH}" ; \
+		else \
+			echo "Downloading I/O library from ${GF180MCU_IO_PATH}" ; \
+			../scripts/download.sh ${PDK_LIB_IO} ${GF180MCU_IO_PATH} ; \
+		fi ; \
+	fi
+
+sc-7t-repo:
+	if test "x${GF180MCU_SC_7T5V0_PATH}" != "x" ; then \
+		if test -d "${GF180MCU_SC_7T5V0_PATH}" ; then \
+			echo "Using existing installation of 7-track standard cell library from ${GF180MCU_SC_7T5V0_PATH}" ; \
+		else \
+			echo "Downloading 7-track standard cell library from ${GF180MCU_SC_7T5V0_PATH}" ; \
+			../scripts/download.sh ${PDK_LIB_SC_7T5V0} ${GF180MCU_SC_7T5V0_PATH} ; \
+		fi ; \
+	fi
+
+sc-9t-repo:
+	if test "x${GF180MCU_SC_9T5V0_PATH}" != "x" ; then \
+		if test -d "${GF180MCU_SC_9T5V0_PATH}" ; then \
+			echo "Using existing installation of 9-track standard cell library from ${GF180MCU_SC_9T5V0_PATH}" ; \
+		else \
+			echo "Downloading 9-track standard cell library from ${GF180MCU_SC_9T5V0_PATH}" ; \
+			../scripts/download.sh ${PDK_LIB_SC_9T5V0} ${GF180MCU_SC_9T5V0_PATH} ; \
+		fi ; \
+	fi
+
+sram-repo:
+	if test "x${GF180MCU_SRAM_PATH}" != "x" ; then \
+		if test -d "${GF180MCU_SRAM_PATH}" ; then \
+			echo "Using existing installation of primitive library from ${GF180MCU_SRAM_PATH}" ; \
+		else \
+			echo "Downloading primitive library from ${GF180MCU_SRAM_PATH}" ; \
+			../scripts/download.sh ${PDK_LIB_SRAM} ${GF180MCU_SRAM_PATH} ; \
+		fi ; \
+	fi
+
+# Update prerequisites
+update: update-pr-repo update-io-repo update-sc-7t-repo update-sc-9t-repo update-ream-repo
+
+update-pr-repo:
+	if test "x${GF180MCU_PR_PATH}" != "x" ; then \
+		echo "Updating GF180MCU primitive library from ${PDK_LIB_PR}" ; \
+		custom/scripts/pdk_update.sh ${GF180MCU_PR_PATH} ; \
+	fi
+
+update-io-repo:
+	if test "x${GF180MCU_IO_PATH}" != "x" ; then \
+		echo "Updating GF180MCU I/O library from ${PDK_LIB_IO}" ; \
+		custom/scripts/pdk_update.sh ${GF180MCU_IO_PATH} ; \
+	fi
+
+update-sc-7t-repo:
+	if test "x${GF180MCU_SC_7T5V0_PATH}" != "x" ; then \
+		echo "Updating GF180MCU 7-track standard cell library from ${PDK_LIB_SC_7T5V0}" ; \
+		custom/scripts/pdk_update.sh ${GF180MCU_SC_7T5V0_PATH} ; \
+	fi
+
+update-sc-9t-repo:
+	if test "x${GF180MCU_SC_9T5V0_PATH}" != "x" ; then \
+		echo "Updating GF180MCU 9-track standard cell library from ${PDK_LIB_SC_9T5V0}" ; \
+		custom/scripts/pdk_update.sh ${GF180MCU_SC_9T5V0_PATH} ; \
+	fi
+
+update-sram-repo:
+	if test "x${GF180MCU_SRAM_PATH}" != "x" ; then \
+		echo "Updating GF180MCU SRAM macro library from ${PDK_LIB_SRAM}" ; \
+		custom/scripts/pdk_update.sh ${GF180MCU_SRAM_PATH} ; \
+	fi
+
+all-%: prerequisites
+	echo "Starting gf180mcu$* PDK staging on "`date` > ${GF180MCU$*}_make.log
+	${MAKE} general-$*
+	${MAKE} tools-$*
+	${MAKE} vendor-$*
+	echo "Ended gf180mcu$* PDK staging on "`date` >> ${GF180MCU$*}_make.log
+
+general-%: ${TECH}.json
+	mkdir -p ${STAGING_PATH}/${GF180MCU$*}/${CONFIG_DIR}
+	rm -f ${STAGING_PATH}/${GF180MCU$*}/${CONFIG_DIR}/nodeinfo.json
+	${CPP} ${GF180MCU$*_DEFS} ${COMMIT_DEFS} ${TECH}.json \
+		${STAGING_PATH}/${GF180MCU$*}/${CONFIG_DIR}/nodeinfo.json
+
+tools-A: $(addsuffix -A, $(TOOLS))
+
+tools-B: $(addsuffix -B, $(TOOLS))
+
+tools-C: $(addsuffix -C, $(TOOLS))
+
+magic-%: magic/${TECH}.tech magic/${TECH}gds.tech magic/${TECH}.magicrc magic/${TECH}.tcl
+	mkdir -p ${MAGICTOP_STAGING_$*}
+	mkdir -p ${MAGIC_STAGING_$*}
+	rm -f ${MAGICTOP_STAGING_$*}/current
+	rm -f ${MAGIC_STAGING_$*}/${GF180MCU$*}.tech
+	rm -f ${MAGIC_STAGING_$*}/${GF180MCU$*}-GDS.tech
+	rm -f ${MAGIC_STAGING_$*}/${GF180MCU$*}.tcl
+	rm -f ${MAGIC_STAGING_$*}/${GF180MCU$*}-BindKeys
+	rm -f ${MAGIC_STAGING_$*}/magicrc
+	if test "${EF_STYLE}" == "1" ; then \
+            (cd ${MAGICTOP_STAGING_$*} ; ln -s ${REV_DIR} current) ; \
+	fi
+
+	${CPP} ${GF180MCU$*_DEFS} magic/${TECH}.tech \
+		${MAGIC_STAGING_$*}/${GF180MCU$*}.tech
+	${CPP} ${GF180MCU$*_DEFS} magic/${TECH}gds.tech \
+		${MAGIC_STAGING_$*}/${GF180MCU$*}-GDS.tech
+	${CPP} ${GF180MCU$*_DEFS} magic/${TECH}.magicrc \
+		${MAGIC_STAGING_$*}/${GF180MCU$*}.magicrc
+	${CPP} ${GF180MCU$*_DEFS} ${SCRIPTSDIR}/common/pdk.bindkeys \
+		${MAGIC_STAGING_$*}/${GF180MCU$*}-BindKeys
+	${CPP} ${GF180MCU$*_DEFS} magic/${TECH}.tcl \
+		${MAGIC_STAGING_$*}/${GF180MCU$*}.tcl
+	${CPP} ${GF180MCU$*_DEFS} ${SCRIPTSDIR}/common/pdk.tcl >> \
+		${MAGIC_STAGING_$*}/${GF180MCU$*}.tcl
+
+netgen-%: netgen/${TECH}_setup.tcl
+	mkdir -p ${NETGENTOP_STAGING_$*}
+	mkdir -p ${NETGEN_STAGING_$*}
+	rm -f ${NETGEN_STAGING_$*}/${GF180MCU$*}_setup.tcl
+	rm -f ${NETGEN_STAGING_$*}/setup.tcl
+	${CPP} ${GF180MCU$*_DEFS} netgen/${TECH}_setup.tcl \
+		${NETGEN_STAGING_$*}/${GF180MCU$*}_setup.tcl
+	(cd ${NETGEN_STAGING_$*} ; ln -s ${GF180MCU$*}_setup.tcl setup.tcl)
+
+qflow-%: qflow/${TECH}.sh qflow/${TECH}.par
+	mkdir -p ${QFLOWTOP_STAGING_$*}
+	mkdir -p ${QFLOW_STAGING_$*}
+	rm -f ${QFLOW_STAGING_$*}/gf180mcu_fd_sc_mcu7t5v0.sh
+	rm -f ${QFLOW_STAGING_$*}/gf180mcu_fd_sc_mcu7t5v0.par
+	rm -f ${QFLOW_STAGING_$*}/gf180mcu_fd_sc_mcu9t5v0.sh
+	rm -f ${QFLOW_STAGING_$*}/gf180mcu_fd_sc_mcu9t5v0.par
+	${CPP} ${GF180MCU$*_DEFS} -DLIBRARY=gf180mcu_fd_sc_mcu7t5v0 \
+		qflow/${TECH}.sh ${QFLOW_STAGING_$*}/gf180mcu_fd_sc_mcu7t5v0.sh
+	${CPP} ${GF180MCU$*_DEFS} -DLIBRARY=gf180mcu_fd_sc_mcu9t5v0 \
+		qflow/${TECH}.sh ${QFLOW_STAGING_$*}/gf180mcu_fd_sc_mcu9t5v0.sh
+	${CPP} ${GF180MCU$*_DEFS} qflow/${TECH}.par \
+		 ${QFLOW_STAGING_$*}/gf180mcu_fd_sc_mcu7t5v0.par
+	${CPP} ${GF180MCU$*_DEFS} qflow/${TECH}.par \
+		 ${QFLOW_STAGING_$*}/gf180mcu_fd_sc_mcu9t5v0.par
+
+irsim-%:
+	mkdir -p ${IRSIMTOP_STAGING_$*}
+	mkdir -p ${IRSIM_STAGING_$*}
+
+klayout-%: ${GF180MCU_PR_PATH}
+	mkdir -p ${KLAYOUTTOP_STAGING_$*}
+	mkdir -p ${KLAYOUT_STAGING_$*}
+	rm -rf ${KLAYOUT_STAGING_$*}/drc
+	rm -rf ${KLAYOUT_STAGING_$*}/lvs
+	rm -rf ${KLAYOUT_STAGING_$*}/tech
+	rm -rf ${KLAYOUT_STAGING_$*}/pymacros
+	mkdir ${KLAYOUT_STAGING_$*}/drc
+	mkdir ${KLAYOUT_STAGING_$*}/lvs
+	mkdir ${KLAYOUT_STAGING_$*}/tech
+	mkdir ${KLAYOUT_STAGING_$*}/pymacros
+
+	cp -rp ${GF180MCU_PR_PATH}/rules/klayout/drc/* \
+		${KLAYOUT_STAGING_$*}/drc
+	cp -rp ${GF180MCU_PR_PATH}/rules/klayout/lvs/* \
+		${KLAYOUT_STAGING_$*}/lvs
+	cp -rp ${GF180MCU_PR_PATH}/cells/klayout/pymacros/cells/* \
+		${KLAYOUT_STAGING_$*}/pymacros
+	cp -rp ${GF180MCU_PR_PATH}/tech/klayout/* \
+		${KLAYOUT_STAGING_$*}/tech
+	cp -rp ${GF180MCU_PR_PATH}/cells/klayout/pymacros/*.lym \
+		${KLAYOUT_STAGING_$*}/tech
+
+xcircuit-%:
+	rm -rf ${XCIRCUIT_STAGING_$*}
+	mkdir -p ${XCIRCUITTOP_STAGING_$*}
+	mkdir -p ${XCIRCUIT_STAGING_$*}
+
+xschem-%: ${GF180MCU_PR_PATH}
+	rm -rf ${XSCHEM_STAGING_$*}
+	mkdir -p ${XSCHEMTOP_STAGING_$*}
+	mkdir -p ${XSCHEM_STAGING_$*}
+	cp -rp ${GF180MCU_PR_PATH}/cells/xschem/symbols ${XSCHEM_STAGING_$*}
+	cp -rp ${GF180MCU_PR_PATH}/cells/xschem/tests ${XSCHEM_STAGING_$*}
+	cp -rp ${GF180MCU_PR_PATH}/cells/xschem/xschemrc ${XSCHEM_STAGING_$*}
+
+openlane-%: openlane/config.tcl openlane/gf180mcu_fd_sc_mcu7t5v0/config.tcl openlane/gf180mcu_fd_sc_mcu9t5v0/config.tcl
+	mkdir -p ${OPENLANETOP_STAGING_$*}
+	mkdir -p ${OPENLANE_STAGING_$*}
+	rm -rf ${OPENLANE_STAGING_$*}/gf180mcu_fd_sc_mcu7t5v0
+	rm -rf ${OPENLANE_STAGING_$*}/gf180mcu_fd_sc_mcu9t5v0
+	mkdir ${OPENLANE_STAGING_$*}/gf180mcu_fd_sc_mcu7t5v0
+	mkdir ${OPENLANE_STAGING_$*}/gf180mcu_fd_sc_mcu9t5v0
+	for file in ${OPENLANE_COMMON} ; do \
+		rm -f ${OPENLANE_STAGING_$*}/gf180mcu_fd_sc_mcu7t5v0/$$file ; \
+	done
+	for file in ${OPENLANE_COMMON} ; do \
+		rm -f ${OPENLANE_STAGING_$*}/gf180mcu_fd_sc_mcu9t5v0/$$file ; \
+	done
+	${CPP} ${GF180MCU$*_DEFS} openlane/config.tcl ${OPENLANE_STAGING_$*}/config.tcl
+
+	for file in ${OPENLANE_COMMON} ; do \
+		${CPP} -quiet ${GF180MCU$*_DEFS} openlane/gf180mcu_fd_sc_mcu7t5v0/$$file \
+			${OPENLANE_STAGING_$*}/gf180mcu_fd_sc_mcu7t5v0/$$file ; \
+	done
+	for file in ${OPENLANE_COMMON} ; do \
+		${CPP} -quiet ${GF180MCU$*_DEFS} openlane/gf180mcu_fd_sc_mcu9t5v0/$$file \
+			${OPENLANE_STAGING_$*}/gf180mcu_fd_sc_mcu9t5v0/$$file ; \
+	done
+
+	rm -f ${OPENLANE_STAGING_$*}/rules.openrcx.gf180mcu$*.min.magic
+	rm -f ${OPENLANE_STAGING_$*}/rules.openrcx.gf180mcu$*.nom.magic
+	rm -f ${OPENLANE_STAGING_$*}/rules.openrcx.gf180mcu$*.max.magic
+
+	if test -f openlane/rules.openrcx.gf180mcu$*.min.magic ; then \
+		${CPP} ${GF180MCU$*_DEFS} openlane/rules.openrcx.gf180mcu$*.min.magic \
+		${OPENLANE_STAGING_$*}/rules.openrcx.gf180mcu$*.min.magic ;\
+	fi
+	if test -f openlane/rules.openrcx.gf180mcu$*.nom.magic ; then \
+		${CPP} ${GF180MCU$*_DEFS} openlane/rules.openrcx.gf180mcu$*.nom.magic \
+		${OPENLANE_STAGING_$*}/rules.openrcx.gf180mcu$*.nom.magic ;\
+	fi
+	if test -f openlane/rules.openrcx.gf180mcu$*.max.magic ; then \
+		${CPP} ${GF180MCU$*_DEFS} openlane/rules.openrcx.gf180mcu$*.max.magic \
+		${OPENLANE_STAGING_$*}/rules.openrcx.gf180mcu$*.max.magic ;\
+	fi
+
+vendor-A: primitive-build-A digital-7t5v0-build-A digital-9t5v0-build-A io-build-A sram-build-A
+
+vendor-B: primitive-build-B digital-7t5v0-build-B digital-9t5v0-build-B io-build-B sram-build-B
+
+vendor-C: primitive-build-C digital-7t5v0-build-C digital-9t5v0-build-C io-build-C sram-build-C
+
+primitive-build-%:
+	if test -d ${GF180MCU_PR_PATH} ; then \
+		echo "Building primitives library and simulation models" ;\
+		make primitive-$* ;\
+	fi
+
+io-build-%:
+	if test -d ${GF180MCU_IO_PATH} ; then \
+		echo "Building padframe I/O libraries" ;\
+		make io-$* ;\
+	fi
+
+digital-9t5v0-build-%:
+	if test -d ${GF180MCU_SC_9T5V0_PATH} ; then \
+		echo "Building 5V 9-track digital standard cell libraries" ;\
+		make digital-9t5v0-$* ;\
+	fi
+
+digital-7t5v0-build-%:
+	if test -d ${GF180MCU_SC_7T5V0_PATH} ; then \
+		echo "Building 5V 7-track digital standard cell libraries" ;\
+		make digital-7t5v0-$* ;\
+	fi
+
+sram-build-%:
+	if test -d ${GF180MCU_SRAM_PATH} ; then \
+		echo "Building SRAM libraries" ;\
+		make sram-$* ;\
+	fi
+
+primitive-%:
+        # Install tech LEF and primitive devices from vendor files
+	${STAGE} -source ${GF180MCU_PR_PATH} \
+		-target ${STAGING_PATH}/${GF180MCU$*} \
+		-ngspice models/ngspice/*.ngspice \
+		-xyce models/xyce/*.xyce \
+		2>&1 | tee -a ${GF180MCU$*}_make.log
+
+digital-9t5v0-%:
+        # Install 5V 9-track digital standard cells from vendor files
+	${STAGE} -source ${GF180MCU_SC_9T5V0_PATH} \
+		-target ${STAGING_PATH}/${GF180MCU$*} \
+		-techlef tech/gf180mcu_${$*_FULLSTACK}_9t_tech.lef \
+			rename=gf180mcu_fd_sc_mcu9t5v0.tlef \
+		-cdl cells/*/*.cdl compile-only noconvert \
+		-liberty cells/*/*_ff_125C_1v98.lib compile-only \
+			rename=gf180mcu_fd_sc_mcu9t5v0__ff_125C_1v98 \
+		-liberty cells/*/*_ff_n40C_1v98.lib compile-only \
+			rename=gf180mcu_fd_sc_mcu9t5v0__ff_n40C_1v98 \
+		-liberty cells/*/*_ff_125C_3p6v.lib compile-only \
+			rename=gf180mcu_fd_sc_mcu9t5v0__ff_125C_3p6v \
+		-liberty cells/*/*_ff_n40C_3p6v.lib compile-only \
+			rename=gf180mcu_fd_sc_mcu9t5v0__ff_n40C_3p6v \
+		-liberty cells/*/*_ff_125C_5v50.lib compile-only \
+			rename=gf180mcu_fd_sc_mcu9t5v0__ff_125C_5v50 \
+		-liberty cells/*/*_ff_n40C_5v50.lib compile-only \
+			rename=gf180mcu_fd_sc_mcu9t5v0__ff_n40C_5v50 \
+		-liberty cells/*/*_ss_125C_1v62.lib compile-only \
+			rename=gf180mcu_fd_sc_mcu9t5v0__ss_125C_1v62 \
+		-liberty cells/*/*_ss_n40C_1v62.lib compile-only \
+			rename=gf180mcu_fd_sc_mcu9t5v0__ss_n40C_1v62 \
+		-liberty cells/*/*_ss_125C_3v00.lib compile-only \
+			rename=gf180mcu_fd_sc_mcu9t5v0__ss_125C_3v00 \
+		-liberty cells/*/*_ss_n40C_3v00.lib compile-only \
+			rename=gf180mcu_fd_sc_mcu9t5v0__ss_n40C_3v00 \
+		-liberty cells/*/*_ss_125C_4v50.lib compile-only \
+			rename=gf180mcu_fd_sc_mcu9t5v0__ss_125C_4v50 \
+		-liberty cells/*/*_ss_n40C_4v50.lib compile-only \
+			rename=gf180mcu_fd_sc_mcu9t5v0__ss_n40C_4v50 \
+		-liberty cells/*/*_tt_025C_1v80.lib compile-only \
+			rename=gf180mcu_fd_sc_mcu9t5v0__tt_025C_1v80 \
+		-liberty cells/*/*_tt_025C_3v30.lib compile-only \
+			rename=gf180mcu_fd_sc_mcu9t5v0__tt_025C_3v30 \
+		-liberty cells/*/*_tt_025C_5v00.lib compile-only \
+			rename=gf180mcu_fd_sc_mcu9t5v0__tt_025C_5v00 \
+		-gds cells/*/*.gds compile-only \
+		-lef cells/*/*.lef compile-only \
+		-verilog cells/*/*.v compile-only \
+		-library digital gf180mcu_fd_sc_mcu9t5v0 2>&1 | \
+		tee -a ${GF180MCU$*}_make.log
+
+digital-7t5v0-%:
+        # Install 5V 7-track digital standard cells from vendor files
+	${STAGE} -source ${GF180MCU_SC_7T5V0_PATH} \
+		-target ${STAGING_PATH}/${GF180MCU$*} \
+		-techlef tech/gf180mcu_${$*_FULLSTACK}_7t_tech.lef \
+			rename=gf180mcu_fd_sc_mcu7t5v0.tlef \
+		-cdl cells/*/*.cdl compile-only noconvert \
+		-liberty cells/*/*_ff_125C_1v98.lib compile-only \
+			rename=gf180mcu_fd_sc_mcu7t5v0__ff_125C_1v98 \
+		-liberty cells/*/*_ff_n40C_1v98.lib compile-only \
+			rename=gf180mcu_fd_sc_mcu7t5v0__ff_n40C_1v98 \
+		-liberty cells/*/*_ff_125C_3p6v.lib compile-only \
+			rename=gf180mcu_fd_sc_mcu7t5v0__ff_125C_3p6v \
+		-liberty cells/*/*_ff_n40C_3p6v.lib compile-only \
+			rename=gf180mcu_fd_sc_mcu7t5v0__ff_n40C_3p6v \
+		-liberty cells/*/*_ff_125C_5v50.lib compile-only \
+			rename=gf180mcu_fd_sc_mcu7t5v0__ff_125C_5v50 \
+		-liberty cells/*/*_ff_n40C_5v50.lib compile-only \
+			rename=gf180mcu_fd_sc_mcu7t5v0__ff_n40C_5v50 \
+		-liberty cells/*/*_ss_125C_1v62.lib compile-only \
+			rename=gf180mcu_fd_sc_mcu7t5v0__ss_125C_1v62 \
+		-liberty cells/*/*_ss_n40C_1v62.lib compile-only \
+			rename=gf180mcu_fd_sc_mcu7t5v0__ss_n40C_1v62 \
+		-liberty cells/*/*_ss_125C_3v00.lib compile-only \
+			rename=gf180mcu_fd_sc_mcu7t5v0__ss_125C_3v00 \
+		-liberty cells/*/*_ss_n40C_3v00.lib compile-only \
+			rename=gf180mcu_fd_sc_mcu7t5v0__ss_n40C_3v00 \
+		-liberty cells/*/*_ss_125C_4v50.lib compile-only \
+			rename=gf180mcu_fd_sc_mcu7t5v0__ss_125C_4v50 \
+		-liberty cells/*/*_ss_n40C_4v50.lib compile-only \
+			rename=gf180mcu_fd_sc_mcu7t5v0__ss_n40C_4v50 \
+		-liberty cells/*/*_tt_025C_1v80.lib compile-only \
+			rename=gf180mcu_fd_sc_mcu7t5v0__tt_025C_1v80 \
+		-liberty cells/*/*_tt_025C_3v30.lib compile-only \
+			rename=gf180mcu_fd_sc_mcu7t5v0__tt_025C_3v30 \
+		-liberty cells/*/*_tt_025C_5v00.lib compile-only \
+			rename=gf180mcu_fd_sc_mcu7t5v0__tt_025C_5v00 \
+		-gds cells/*/*.gds compile-only \
+		-lef cells/*/*.lef compile-only \
+		-verilog cells/*/*.v compile-only \
+		-library digital gf180mcu_fd_sc_mcu7t5v0 2>&1 | \
+		tee -a ${GF180MCU$*}_make.log
+
+io-%:
+        # Install I/O cells from vendor files
+	# Note:  Do not use GF LEF views.  Annotate only.  LEF is being renamed
+	# back to the original, although eventually all files will be changed
+	# to canonical names.
+
+	${STAGE} -source ${GF180MCU_IO_PATH} \
+		-target ${STAGING_PATH}/${GF180MCU$*} \
+		-cdl cells/*/*.cdl compile-only noconvert \
+		-liberty cells/*/*_ff_125C_2v75.lib compile-only \
+			rename=gf180mcu_fd_io__ff_125C_2v75 \
+		-liberty cells/*/*_ff_n40C_2v75.lib compile-only \
+			rename=gf180mcu_fd_io__ff_n40C_2v75 \
+		-liberty cells/*/*_ff_125C_3v63.lib compile-only \
+			rename=gf180mcu_fd_io__ff_125C_3v63 \
+		-liberty cells/*/*_ff_n40C_3v63.lib compile-only \
+			rename=gf180mcu_fd_io__ff_n40C_3v63 \
+		-liberty cells/*/*_ff_125C_5v50.lib compile-only \
+			rename=gf180mcu_fd_io__ff_125C_5v50 \
+		-liberty cells/*/*_ff_n40C_5v50.lib compile-only \
+			rename=gf180mcu_fd_io__ff_n40C_5v50 \
+		-liberty cells/*/*_ss_125C_2v50.lib compile-only \
+			rename=gf180mcu_fd_io__ss_125C_2v50 \
+		-liberty cells/*/*_ss_125C_2v97.lib compile-only \
+			rename=gf180mcu_fd_io__ss_125C_2v97 \
+		-liberty cells/*/*_ss_125C_4v50.lib compile-only \
+			rename=gf180mcu_fd_io__ss_125C_4v50 \
+		-liberty cells/*/*_tt_025C_2v50.lib compile-only \
+			rename=gf180mcu_fd_io__tt_025C_2v50 \
+		-liberty cells/*/*_tt_025C_3v30.lib compile-only \
+			rename=gf180mcu_fd_io__tt_025C_3v30 \
+		-liberty cells/*/*_tt_025C_5v00.lib compile-only \
+			rename=gf180mcu_fd_io__tt_025C_5v00 \
+		-gds cells/*/*_${$*_STACK}.gds compile-only \
+			options=custom/scripts/gds_import_io.tcl \
+		-lef cells/*/*_${$*_STACK}.lef \
+			annotate untrusted lefopts=-hide compile-only \
+			filter=custom/scripts/fix_io_lef.py \
+		-verilog cells/*/*.v compile-only \
+		-library general gf180mcu_fd_io 2>&1 | tee -a ${GF180MCU$*}_make.log
+
+sram-%:
+	# Install SRAM macros from vendor files
+	${STAGE} -source ${GF180MCU_SRAM_PATH} \
+		-target ${STAGING_PATH}/${GF180MCU$*} \
+		-cdl cells/*/*.cdl noconvert \
+		-liberty cells/*/*.lib \
+		-gds cells/*/*.gds \
+		-lef cells/*/*.lef \
+		-verilog cells/*/*.v \
+		-library general gf180mcu_fd_ip_sram 2>&1 | tee -a ${GF180MCU$*}_make.log
+
+install: $(foreach var, ${VARIANTS}, install-$(var))
+
+install-A:
+	echo "Starting GF180MCU PDK migration on "`date` > ${GF180MCUA}_install.log
+	${INSTALL} \
+		-source ${STAGING_PATH}/${GF180MCUA} \
+		-finalpath ${SHARED_PDKS_PATH}/${GF180MCUA} \
+		-variable PDKPATH \
+		-link_from ${DIST_LINK_TARGETS_A} 2>&1 | tee -a ${GF180MCUA}_install.log
+	echo "Ended GF180MCU PDK migration on "`date` >> ${GF180MCUA}_install.log
+
+install-B: install-A
+	echo "Starting GF180MCU PDK migration on "`date` > ${GF180MCUB}_install.log
+	${INSTALL} \
+		-source ${STAGING_PATH}/${GF180MCUB} \
+		-finalpath ${SHARED_PDKS_PATH}/${GF180MCUB} \
+		-variable PDKPATH \
+		-link_from ${DIST_LINK_TARGETS_B} 2>&1 | tee -a ${GF180MCUB}_install.log
+	echo "Ended GF180MCU PDK migration on "`date` >> ${GF180MCUB}_install.log
+
+install-C: install-A
+	echo "Starting GF180MCU PDK migration on "`date` > ${GF180MCUC}_install.log
+	${INSTALL} \
+		-source ${STAGING_PATH}/${GF180MCUC} \
+		-finalpath ${SHARED_PDKS_PATH}/${GF180MCUC} \
+		-variable PDKPATH \
+		-link_from ${DIST_LINK_TARGETS_C} 2>&1 | tee -a ${GF180MCUC}_install.log
+	echo "Ended GF180MCU PDK migration on "`date` >> ${GF180MCUC}_install.log
+
+uninstall: $(foreach var, ${VARIANTS}, uninstall-$(var))
+
+uninstall-A:
+	echo "Uninstalling GF180MCU PDK from ${SHARED_PDKS_PATH}"
+	if test "x${SHARED_PDKS_PATH}" != "x" ; then \
+		${RM} -rf ${SHARED_PDKS_PATH}/${GF180MCUA} ; \
+	fi
+	echo "Finished GF180MCU PDK uninstall"
+
+uninstall-B:
+	echo "Uninstalling GF180MCU PDK from ${SHARED_PDKS_PATH}"
+	if test "x${SHARED_PDKS_PATH}" != "x" ; then \
+		${RM} -rf ${SHARED_PDKS_PATH}/${GF180MCUB} ; \
+	fi
+	echo "Finished GF180MCU PDK uninstall"
+
+uninstall-C:
+	echo "Uninstalling GF180MCU PDK from ${SHARED_PDKS_PATH}"
+	if test "x${SHARED_PDKS_PATH}" != "x" ; then \
+		${RM} -rf ${SHARED_PDKS_PATH}/${GF180MCUC} ; \
+	fi
+	echo "Finished GF180MCU PDK uninstall"
+
+clean: $(foreach var, ${VARIANTS}, clean-$(var))
+
+clean-A:
+	${STAGE} -target ${STAGING_PATH}/${GF180MCUA} -clean
+
+clean-B:
+	${STAGE} -target ${STAGING_PATH}/${GF180MCUB} -clean
+
+clean-C:
+	${STAGE} -target ${STAGING_PATH}/${GF180MCUC} -clean
+
+veryclean: $(foreach var, ${VARIANTS}, veryclean-$(var))
+
+veryclean-A: clean-A
+	${RM} ${GF180MCUA}_make.log
+	${RM} ${GF180MCUA}_install.log
+
+veryclean-B: clean-B
+	${RM} ${GF180MCUB}_make.log
+	${RM} ${GF180MCUB}_install.log
+
+veryclean-C: clean-C
+	${RM} ${GF180MCUC}_make.log
+	${RM} ${GF180MCUC}_install.log
+
+
diff --git a/gf180mcu/NOTES b/gf180mcu/NOTES
new file mode 100644
index 0000000..5f722a8
--- /dev/null
+++ b/gf180mcu/NOTES
@@ -0,0 +1,5 @@
+March 9, 2022:  First draft of the open_pdks installer for the Global Foundries
+gf180mcu (180nm) open PDK.
+
+July 27, 2022:  Open source repositories now available on github, so integrating
+directly into open_pdks.
diff --git a/gf180mcu/README b/gf180mcu/README
new file mode 100644
index 0000000..ecd3c95
--- /dev/null
+++ b/gf180mcu/README
@@ -0,0 +1,76 @@
+Master PDK generator for gf180mcu
+---------------------------------
+
+Run "make" to generate all files for each PDK.
+
+This make script takes the source files and generates files for local (efabless)
+PDK names "gf180mcuA", "gf180mcuB", etc.
+
+The definition of each PDK is made in the Makefile using defines; e.g.,
+	-DMETAL4, etc.
+
+These are based on a subset of the 15 supported process variants shown in the
+Global Foundries documentation.  See the Makefile for a complete description.
+
+The make script makes use of the python script "preproc.py" (in the ../common
+directory) to parse each source file for "#ifdef ..."-type macros.  The syntax
+is similar to that used by the C preprocessor (cpp) but does not assume C
+language syntax in the input file, so is generally better to use than cpp
+(has less unexpected/unintentional behavior).  See comments in the preproc.py
+script for a full list of macros that it accepts (short list: #ifdef, #ifndef,
+#define, #include, and boolean operators ||, &&, and !). 
+
+Files generated:
+	.tech		techfile for magic, general user use (limited DRC, no GDS)
+	-GDS.tech	techfile for magic, vendor mask layers
+	.tcl		PDK script for magic
+	-BindKeys	key binding script for magic partly matching Cadence defaults
+	.magicrc	magic startup script (copy to local directory as .magicrc)
+	_setup.tcl	netgen setup script for LVS
+	.sh		qflow master setup script, standard 1.8V digital
+	.par		graywolf setup file, standard 1.8V digital
+
+The installation directory below PDK_ROOT is the name of the PDK;  e.g.,
+
+	    gf180mcuA/	3-metal backend stack
+	    gf180mcuB/	4-metal backend stack
+	    gf180mcuC/	5-metal backend stack
+
+(Again, see the Makefile for the complete description.)
+
+The installation directory hierarchy below the PDK name looks like the following:
+
+		libs.tech/		technology and setup files
+
+		    magic/		magic techfiles, startup file, PDK script,
+					and key binding script.
+		    netgen/		netgen setup file
+		    qflow/		qflow scripts and graywolf setup files.
+		    ngspice/		SPICE models (ngspice compatible)
+
+		libs.ref/		foundry data
+
+		    gf180mcu_fd_pr/	primitive devices w/fixed layout
+		    gf180mcu_fd_sc_7t/	Digital standard cells (7 track height)
+		    gf180mcu_fd_sc_9t/	Digital standard cells (9 track height)
+		    gf180mcu_fd_io/	I/O pad cells
+		    gf180mcu_fd_sram/	SRAM macros
+		    gf180mcu_fd_nvram/	NVRAM macros
+
+Each subdirectory of libs.ref is further divided into sections based on the
+file type.  These sections include one or more of:
+
+		    cdl/		CDL netlists
+		    doc/		Foundry documentation
+		    gds/		GDS files
+		    lef/		LEF macro files
+		    lib/		Liberty timing files
+		    mag/		Magic files derived from GDS
+		    maglef/		Magic files derived from LEF macros
+		    spice/		SPICE netlists (ngspice compatible)
+		    techlef/		LEF technology files
+		    verilog/		verilog modules
+
+The target installation destinations assume the directory structure above.  Changing
+this requires editing the source files.
+
diff --git a/gf180mcu/custom/scripts/fix_io_lef.py b/gf180mcu/custom/scripts/fix_io_lef.py
new file mode 100755
index 0000000..661e4f8
--- /dev/null
+++ b/gf180mcu/custom/scripts/fix_io_lef.py
@@ -0,0 +1,134 @@
+#!/usr/bin/env python3
+#
+# fix_io_lef ---
+#
+# This script fixes the issue where the LEF macros of the I/O cells
+# are missing ports in the position of the wirebond pads, or the ports
+# do not include the entire pad area.  This script inserts an extra
+# port rectangle at the position of the pad on all top-level I/O cells
+#
+# This script is a filter to be run by setting the name of this script as
+# the value to "filter=" for the model install in the gf180mcu Makefile.
+
+import re
+import os
+import sys
+
+def filter(inname, outname):
+
+    # Read input.  Note that there is only one LEF file for the I/O library.
+    try:
+        with open(inname, 'r') as inFile:
+            ltext = inFile.read()
+            llines = ltext.splitlines()
+    except:
+        print('fix_io_lef.py: failed to open ' + inname + ' for reading.', file=sys.stderr)
+        return 1
+
+    # Map the input file name to the metal layer of the pad.
+    # The file names end in _3lm.lef, _4lm.lef, and _5lm.lef, so pick up the
+    # 7th character from the end.
+    mlayer = 'Metal' + inname[-7]
+
+    # The following macros need pad ports
+    fixmacros = ['GF_NI_ASIG_5P0', 'GF_NI_BI_24T', 'GF_NI_BI_T', 'GF_NI_DVDD',
+		 'GF_NI_DVSS', 'GF_NI_IN_C', 'GF_NI_IN_S']
+
+    # Pin name for the pad port corresponding to each of the above macros
+    fixpins = ['ASIG5V', 'PAD', 'PAD', 'DVDD', 'DVSS', 'PAD', 'PAD']
+
+    # Process input with regexp
+
+    fixedlines = []
+    modified = False
+
+    macrorex = re.compile('[ \t]*MACRO[ \t]+([^ \t\n]+)')
+    pinrex = re.compile('[ \t]*PIN[ \t]+([^ \t\n]+)')
+    userex = re.compile('[ \t]*USE[ \t]+([^ \t\n]+)')
+    endrex = re.compile('[ \t]*END[ \t]+([^ \t\n]+)')
+
+    macroidx = -1
+    pinidx = -1
+    pin = None
+    for line in llines:
+        fixedlines.append(line)
+
+        # Check for macro end
+        if macroidx >= 0:
+            ematch = endrex.match(line)
+            if ematch:
+                macroidx = -1
+                pinidx = -1
+
+        # Check for 'MACRO' record, and get name of the macro.
+        mmatch = macrorex.match(line)
+        if mmatch:
+            macroname = mmatch.group(1)
+            if macroname in fixmacros:
+                macroidx = fixmacros.index(macroname)
+
+        # Check for pin
+        if macroidx >= 0:
+            pmatch = pinrex.match(line)
+            if pmatch:
+                if pmatch.group(1) == fixpins[macroidx]:
+                    pinidx = macroidx
+
+        if pinidx >= 0:
+            umatch = userex.match(line)
+            if umatch:
+                # Add the extra port
+                fixedlines.append('      PORT')
+                fixedlines.append('      LAYER ' + mlayer + ' ;')
+                fixedlines.append('      RECT 7.5 2.0 67.5 62.0 ;')
+                fixedlines.append('      END')
+                pinidx = -1
+                modified = True
+
+    # Write output
+    if outname == None:
+        for i in fixedlines:
+            print(i)
+    else:
+        # If the output is a symbolic link but no modifications have been made,
+        # then leave it alone.  If it was modified, then remove the symbolic
+        # link before writing.
+        if os.path.islink(outname):
+            if not modified:
+                return 0
+            else:
+                os.unlink(outname)
+        try:
+            with open(outname, 'w') as outFile:
+                for i in fixedlines:
+                    print(i, file=outFile)
+        except:
+            print('fix_io_lef.py: failed to open ' + outname + ' for writing.', file=sys.stderr)
+            return 1
+
+
+if __name__ == '__main__':
+
+    # This script expects to get one or two arguments.  One argument is
+    # mandatory and is the input file.  The other argument is optional and
+    # is the output file.  The output file and input file may be the same
+    # name, in which case the original input is overwritten.
+
+    options = []
+    arguments = []
+    for item in sys.argv[1:]:
+        if item.find('-', 0) == 0:
+            options.append(item[1:])
+        else:
+            arguments.append(item)
+
+    if len(arguments) > 0:
+        infilename = arguments[0]
+
+    if len(arguments) > 1:
+        outfilename = arguments[1]
+    else:
+        outfilename = None
+
+    result = filter(infilename, outfilename)
+    sys.exit(result)
diff --git a/gf180mcu/custom/scripts/gds_import_io.tcl b/gf180mcu/custom/scripts/gds_import_io.tcl
new file mode 100644
index 0000000..dd0395a
--- /dev/null
+++ b/gf180mcu/custom/scripts/gds_import_io.tcl
@@ -0,0 +1,5 @@
+# Set GDS import styles as needed to deal with the I/O cells.
+gds ordering on
+gds polygon subcells true
+gds flatten true
+gds flatglob *_CDNS_*
diff --git a/gf180mcu/gf180mcu.json b/gf180mcu/gf180mcu.json
new file mode 100644
index 0000000..9b5a2a8
--- /dev/null
+++ b/gf180mcu/gf180mcu.json
@@ -0,0 +1,95 @@
+#define DESCRIPTION Global Foundries 0.18um MCU CMOS, 2fF MiM + 1k high sheet rho poly
+#ifdef METALS3
+#define OPTION1 + 3 metal layer backend stack
+#elseif defined (METALS4)
+#define OPTION1 + 4 metal layer backend stack
+#elseif defined (METALS5)
+#define OPTION1 + 5 metal layer backend stack
+#elseif defined (METALS6)
+#define OPTION1 + 6 metal layer backend stack
+#else
+#define OPTION1 + 2 metal layer backend stack
+#endif
+#ifdef THICKMET3P0
+#define OPTION2 + 3um thick top metal
+#elseif defined (THICKMET1P1)
+#define OPTION2 + 1.1um thick top metal
+#elseif defined (THICKMET0P9)
+#define OPTION2 + 0.9um thick top metal
+#else
+#define OPTION2 + 0.6um thick top metal
+#endif
+#ifdef MIM
+#define OPTION3 + 2fF/um^2 MiM caps
+#else
+#define OPTION3
+#endif (MIM)
+#ifdef HRES1K
+#define OPTION4 + 1k high sheet rho poly
+#else
+#define OPTION4
+#endif (HRES1K)
+#ifdef REDISTRIBUTION
+#define OPTION5 + redistribution layer
+#else
+#define OPTION5
+#endif (REDISTRIBUTION)
+{
+    "foundry": "GF",
+    "foundry-name": "Global Foundries",
+    "node": "TECHNAME",
+    "feature-size": "180nm",
+    "status": "active",
+    "description": "DESCRIPTION OPTION1 OPTION2 OPTION3 OPTION4 OPTION5",
+    "options": [
+#ifdef THICKMET3P0
+	"THICKMET",
+#endif
+#ifdef MIM
+#undef MIM
+	"MIM_2P0",
+#endif
+#ifdef HRES1K
+	"HIRES_POLY_1K",
+#endif
+#ifdef METALS3
+	"METAL3"
+#elseif defined (METALS4)
+	"METAL4"
+#elseif defined (METALS5)
+	"METAL5"
+#elseif defined (METALS6)
+	"METAL6"
+#endif
+    ],
+    "stdcells": {
+	"gf180mcu_fd_sc_mcu9t5v0": "FD_SC_MCU9T5V0_COMMIT",
+	"gf180mcu_fd_sc_mcu7t5v0": "FD_SC_MCU9T5V0_COMMIT"
+    },
+    "iocells": {
+        "gf180mcu_fd_io": "FD_IO_COMMIT"
+    },
+    "primitive": {
+	"gf180mcu_fd_pr": "FD_PR_COMMIT"
+    },
+    "memory": {
+	"gf180mcu_fd_ip_sram": "FD_IP_SRAM_COMMIT"
+    },
+    "build": {
+	"open_pdks": "OPEN_PDKS_VERSION",
+	"magic": "MAGIC_VERSION"
+    },
+    "commit": {
+	"open_pdks": "OPEN_PDKS_COMMIT",
+	"magic": "MAGIC_COMMIT"
+    }
+    "reference": {
+        "open_pdks": "fb6f374beff316f9a8e0b5585facfc18008c0f2d",
+        "magic": "43d5cc280413b0fd947b555bf1e8d79ea8681450",
+        "gf180mcu_fd_pr": "92ec4b2e5eb193a0c5c2754413d44981c8e17e16",
+        "gf180mcu_fd_io": "5cc533968c9d03972f92a461af0edc80118b1e9c",
+        "gf180mcu_fd_sc_mcu7t5v0": "1f37f62c329b62710f4331d68272beeae20140e5",
+        "gf180mcu_fd_sc_mcu9t5v0": "1f37f62c329b62710f4331d68272beeae20140e5",
+        "gf180mcu_fd_ip_sram": "343ab45497682f3f3f808ee4c79a8f92c5010636"
+    }
+}
diff --git a/gf180mcu/magic/gf180mcu.magicrc b/gf180mcu/magic/gf180mcu.magicrc
new file mode 100644
index 0000000..1fa2e18
--- /dev/null
+++ b/gf180mcu/magic/gf180mcu.magicrc
@@ -0,0 +1,69 @@
+###
+###	Source file TECHNAME.magicrc
+###	Process this file with the m4 processor
+###
+puts stdout "Sourcing design .magicrc for technology TECHNAME ..."
+
+# Put internal grid on 0.005 pitch.  This is important to match vendor file
+# input (as opposed to SCMOS-style layout.  The default lambda grid is 0.05um).
+
+set scalefac [tech lambda]
+if {[lindex $scalefac 1] < 10} {
+    scalegrid 1 10
+}
+
+# drc off
+drc euclidean on
+# Change this to a fixed number for repeatable behavior with GDS writes
+# e.g., "random seed 12345"
+catch {random seed}
+
+# Allow override of PDK path from environment variable PDK_ROOT
+# "file nativename" guards against a local PDK_ROOT with "~" in the name
+if {[catch {set PDK_ROOT [file nativename $env(PDK_ROOT)]}]} {
+    set PDK_ROOT STAGING_PATH
+}
+
+# loading technology
+tech load $PDK_ROOT/TECHNAME/MAGIC_CURRENT/TECHNAME.tech
+
+# load device generator
+source $PDK_ROOT/TECHNAME/MAGIC_CURRENT/TECHNAME.tcl
+
+# load bind keys
+# source $PDK_ROOT/TECHNAME/MAGIC_CURRENT/TECHNAME-BindKeys
+
+# set units to lambda grid 
+snap lambda
+
+# set gf180mcu standard power, ground, and substrate names
+set VDD VDD
+set GND VSS
+set SUB VSUBS
+
+# Allow override of type of magic library views used, "mag" or "maglef",
+# from environment variable MAGTYPE
+
+if {[catch {set MAGTYPE $env(MAGTYPE)}]} {
+   set MAGTYPE mag
+}
+
+# add path to reference cells
+if {[file isdir ${PDK_ROOT}/TECHNAME/libs.ref/${MAGTYPE}]} {
+    addpath ${PDK_ROOT}/TECHNAME/libs.ref/${MAGTYPE}/gf180mcu_fd_pr
+    addpath ${PDK_ROOT}/TECHNAME/libs.ref/${MAGTYPE}/gf180mcu_mcu7t5v0
+    addpath ${PDK_ROOT}/TECHNAME/libs.ref/${MAGTYPE}/gf180mcu_mcu9t5v0
+    addpath ${PDK_ROOT}/TECHNAME/libs.ref/${MAGTYPE}/gf180mcu_fd_io
+    addpath ${PDK_ROOT}/TECHNAME/libs.ref/${MAGTYPE}/gf180mcu_fd_ip_sram
+} else {
+    addpath ${PDK_ROOT}/TECHNAME/libs.ref/gf180mcu_fd_pr/${MAGTYPE}
+    addpath ${PDK_ROOT}/TECHNAME/libs.ref/gf180mcu_fd_sc_mcu7t5v0/${MAGTYPE}
+    addpath ${PDK_ROOT}/TECHNAME/libs.ref/gf180mcu_fd_sc_mcu9t5v0/${MAGTYPE}
+    addpath ${PDK_ROOT}/TECHNAME/libs.ref/gf180mcu_fd_io/${MAGTYPE}
+    addpath ${PDK_ROOT}/TECHNAME/libs.ref/gf180mcu_fd_ip_sram/${MAGTYPE}
+}
+
+# add path to IP from catalog.  This procedure defined in the PDK script.
+catch {magic::query_mylib_ip}
+# add path to local IP from user design space.  Defined in the PDK script.
+catch {magic::query_my_projects}
diff --git a/gf180mcu/magic/gf180mcu.tcl b/gf180mcu/magic/gf180mcu.tcl
new file mode 100644
index 0000000..dd15fa9
--- /dev/null
+++ b/gf180mcu/magic/gf180mcu.tcl
@@ -0,0 +1,4669 @@
+###
+###     Source file gf013.tcl
+###     Process this file with the preprocessor script
+###
+#-----------------------------------------------------
+# Magic/TCL design kit for GF TECHNAME
+#-----------------------------------------------------
+# Tim Edwards
+# Revision 0	4/25/2022
+#-----------------------------------------------------
+
+if {[catch {set TECHPATH $env(PDK_ROOT)}]} {
+    set TECHPATH STAGING_PATH
+}
+if [catch {set PDKPATH}] {set PDKPATH ${TECHPATH}/TECHNAME}
+set PDKNAME TECHNAME
+# "gf180mcu" is the namespace used for all devices
+set PDKNAMESPACE gf180mcu
+puts stdout "Loading TECHNAME Device Generator Menu ..."
+
+# Initialize toolkit menus to the wrapper window
+
+global Opts
+namespace eval gf180mcu {}
+
+# Set the window callback
+if [catch {set Opts(callback)}] {set Opts(callback) ""}
+set Opts(callback) [subst {gf180mcu::addtechmenu \$framename; $Opts(callback)}]
+
+# if {![info exists Opts(cmdentry)]} {set Opts(cmdentry) 1}
+
+# Set options specific to this PDK
+set Opts(hidelocked) 1
+set Opts(hidespecial) 0
+
+# Wrap the closewrapper procedure so that closing the last
+# window is equivalent to quitting.
+if {[info commands closewrapper] == "closewrapper"} {
+   rename closewrapper closewrapperonly
+   proc closewrapper { framename } {
+      if {[llength [windownames all]] <= 1} {
+         magic::quit
+      } else {
+         closewrapperonly $framename
+      }
+   }
+}
+
+# Remove maze router layers from the toolbar by locking them
+tech lock fence,magnet,rotate
+
+namespace eval gf180mcu {
+    namespace path {::tcl::mathop ::tcl::mathfunc}
+
+    set ruleset [dict create]
+
+    # Process DRC rules (magic style)
+
+    dict set ruleset poly_surround    0.065     ;# Poly surrounds contact
+    dict set ruleset diff_surround    0.065     ;# Diffusion surrounds contact
+    dict set ruleset gate_to_diffcont 0.26      ;# Gate to diffusion contact center
+    dict set ruleset gate_to_polycont 0.28      ;# Gate to poly contact center
+    dict set ruleset gate_extension   0.22      ;# Poly extension beyond gate
+    dict set ruleset diff_extension   0.23      ;# Diffusion extension beyond gate
+    dict set ruleset contact_size     0.23      ;# Minimum contact size
+    dict set ruleset via_size         0.26      ;# Minimum via size
+    dict set ruleset metal_surround   0.055     ;# Metal1 overlaps contact
+    dict set ruleset sub_surround     0.12      ;# Sub/well surrounds diffusion
+    dict set ruleset diff_spacing     0.33      ;# Diffusion spacing rule
+    dict set ruleset poly_spacing     0.24      ;# Poly spacing rule
+    dict set ruleset diffres_spacing  0.40      ;# Diffusion resistor spacing rule
+    dict set ruleset polyres_spacing  0.40      ;# Poly resistor spacing rule
+    dict set ruleset diff_poly_space  0.10      ;# Diffusion to poly spacing rule
+    dict set ruleset diff_gate_space  0.10      ;# Diffusion to gate poly spacing rule
+    dict set ruleset metal_spacing    0.23      ;# Metal1 spacing rule
+    dict set ruleset mmetal_spacing   0.23      ;# Metal spacing rule (above metal1)
+    dict set ruleset sblk_to_cont     0.335     ;# resistor to contact center
+    dict set ruleset sblk_diff_space  0.44      ;# resistor to guard ring
+}
+
+#-----------------------------------------------------
+# magic::addtechmenu
+#-----------------------------------------------------
+
+proc gf180mcu::addtechmenu {framename} {
+   global Winopts Opts
+   
+   # Check for difference between magic 8.1.125 and earlier, and 8.1.126 and later
+   if {[catch {${framename}.titlebar cget -height}]} {
+      set layoutframe ${framename}.pane.top
+   } else {
+      set layoutframe ${framename}
+   }
+
+   # List of devices is long.  Divide into two sections for active and passive deivces
+   magic::add_toolkit_menu $layoutframe "Devices 1" pdk1
+
+   magic::add_toolkit_command $layoutframe "nmos - nMOSFET" "magic::gencell gf180mcu::nmos_3p3" pdk1
+   magic::add_toolkit_command $layoutframe "pmos - pMOSFET" "magic::gencell gf180mcu::pmos_3p3" pdk1
+
+   magic::add_toolkit_separator	$layoutframe pdk1
+   magic::add_toolkit_command $layoutframe "np_3p3 - n-diode" "magic::gencell gf180mcu::np_3p3" pdk1
+   magic::add_toolkit_command $layoutframe "pn_3p3 - p-diode" "magic::gencell gf180mcu::pn_3p3" pdk1
+
+   magic::add_toolkit_separator	$layoutframe pdk1
+   magic::add_toolkit_command $layoutframe "vnpn_5x5     (3.3V) - 5.0um^2 " "magic::gencell gf180mcu::vnpn_2x2" pdk1
+   magic::add_toolkit_command $layoutframe "vnpn_5x0p42  (3.3V) - 5.0um x 0.42um " "magic::gencell gf180mcu::vnpn_5x0p42" pdk1
+   magic::add_toolkit_command $layoutframe "vnpn_10x10   (3.3V) - 10.0um^2 " "magic::gencell gf180mcu::vnpn_5x5" pdk1
+   magic::add_toolkit_command $layoutframe "vnpn_10x0p42 (3.3V) - 10.0um x 0.42um " "magic::gencell gf180mcu::vnpn_10x0p42" pdk1
+   magic::add_toolkit_command $layoutframe "vpnp_5x5     (3.3V) - 5.0um^2 " "magic::gencell gf180mcu::vpnp_5x5" pdk1
+   magic::add_toolkit_command $layoutframe "vpnp_5x0p42  (3.3V) - 5.0um^2 x 0.42um " "magic::gencell gf180mcu::vpnp_5x0p42" pdk1
+   magic::add_toolkit_command $layoutframe "vpnp_10x10   (3.3V) - 10.0um^2 " "magic::gencell gf180mcu::vpnp_10x10" pdk1
+   magic::add_toolkit_command $layoutframe "vpnp_10x0p42 (3.3V) - 10.0um^2 x 0.42um " "magic::gencell gf180mcu::vpnp_10x0p42" pdk1
+
+   magic::add_toolkit_separator	$layoutframe pdk1
+   magic::add_toolkit_command $layoutframe "mos capacitor" "magic::gencell gf180mcu::nmoscap_3p3" pdk1
+
+   magic::add_toolkit_menu $layoutframe "Devices 2" pdk2
+
+   magic::add_toolkit_command $layoutframe "ppolyf_s        - 7 Ohm/sq " "magic::gencell gf180mcu::ppolyf_s" pdk2 
+   magic::add_toolkit_command $layoutframe "npolyf_s        - 7 Ohm/sq " "magic::gencell gf180mcu::ppolyf_s" pdk2 
+   magic::add_toolkit_command $layoutframe "nplus_u   (3.3V) -  85 Ohm/sq " "magic::gencell gf180mcu::nplus_u" pdk2
+   magic::add_toolkit_command $layoutframe "pplus_u   (3.3V) - 128 Ohm/sq " "magic::gencell gf180mcu::pplus_u" pdk2
+   magic::add_toolkit_command $layoutframe "nplus_u  (6.0V) -  85 Ohm/sq " "magic::gencell gf180mcu::nplus_u_6p0" pdk2
+   magic::add_toolkit_command $layoutframe "pplus_u  (6.0V) - 128 Ohm/sq " "magic::gencell gf180mcu::pplus_u_6p0" pdk2
+
+   magic::add_toolkit_command $layoutframe "npolyf_u -  300 Ohm/sq " "magic::gencell gf180mcu::npolyf_u" pdk2
+   magic::add_toolkit_command $layoutframe "ppolyf_u - 315 Ohm/sq " "magic::gencell gf180mcu::ppolyf_u" pdk2
+#ifdef HRPOLY1K
+   magic::add_toolkit_command $layoutframe "ppolyf_u_1k - 1.0k Ohm/sq " "magic::gencell gf180mcu::ppolyf_u_1k" pdk2
+#endif (HRPOLY1K)
+   magic::add_toolkit_command $layoutframe "nwell  (3.3V) -1680 Ohm/sq " "magic::gencell gf180mcu::nwell_3p3" pdk2
+   magic::add_toolkit_separator	$layoutframe pdk2
+
+   magic::add_toolkit_command $layoutframe "rm1 - 90  mOhm/sq " "magic::gencell gf180mcu::rm1" pdk2
+   magic::add_toolkit_command $layoutframe "rm2 - 90  mOhm/sq " "magic::gencell gf180mcu::rm2" pdk2
+
+#ifdef METALS3
+#ifdef THICKMET3P0
+   magic::add_toolkit_command $layoutframe "rm3 - 9.5  mOhm/sq " "magic::gencell gf180mcu::rm3" pdk2
+#elseif (THICKMET1P1 || THICKMET0P9)
+   magic::add_toolkit_command $layoutframe "rm3 - 40  mOhm/sq " "magic::gencell gf180mcu::rm3" pdk2
+#else (!(THICKMET3P0 || THICKMET1P1 || THICKMET0P9))
+   magic::add_toolkit_command $layoutframe "rm3 - 60  mOhm/sq " "magic::gencell gf180mcu::rm3" pdk2
+#endif (!(THICKMET3P0 || THICKMET1P1 || THICKMET0P9))
+#endif (METALS3)
+#ifdef METALS4 || METALS5 || METALS6
+   magic::add_toolkit_command $layoutframe "rm3 - 90  mOhm/sq " "magic::gencell gf180mcu::rm3" pdk2
+#endif (METALS4 || METALS5 || METALS6)
+
+#ifdef METALS4
+#ifdef THICKMET3P0
+   magic::add_toolkit_command $layoutframe "rm4 - 9.5  mOhm/sq " "magic::gencell gf180mcu::rm4" pdk2
+#elseif (THICKMET1P1 || THICKMET0P9)
+   magic::add_toolkit_command $layoutframe "rm4 - 40  mOhm/sq " "magic::gencell gf180mcu::rm4" pdk2
+#else (!(THICKMET3P0 || THICKMET1P1 || THICKMET0P9))
+   magic::add_toolkit_command $layoutframe "rm4 - 60  mOhm/sq " "magic::gencell gf180mcu::rm4" pdk2
+#endif (!(THICKMET3P0 || THICKMET1P1 || THICKMET0P9))
+#endif (METALS4)
+#ifdef METALS5 || METALS6
+   magic::add_toolkit_command $layoutframe "rm4 - 90  mOhm/sq " "magic::gencell gf180mcu::rm4" pdk2
+#endif (METALS5 || METALS6)
+
+#ifdef METALS5
+#ifdef THICKMET3P0
+   magic::add_toolkit_command $layoutframe "rm5 - 9.5  mOhm/sq " "magic::gencell gf180mcu::rm5" pdk2
+#elseif (THICKMET1P1 || THICKMET0P9)
+   magic::add_toolkit_command $layoutframe "rm5 - 40  mOhm/sq " "magic::gencell gf180mcu::rm5" pdk2
+#else (!(THICKMET3P0 || THICKMET1P1 || THICKMET0P9))
+   magic::add_toolkit_command $layoutframe "rm5 - 60  mOhm/sq " "magic::gencell gf180mcu::rm5" pdk2
+#endif (!(THICKMET3P0 || THICKMET1P1 || THICKMET0P9))
+#endif (METALS3)
+#ifdef METALS6
+   magic::add_toolkit_command $layoutframe "rm5 - 90  mOhm/sq " "magic::gencell gf180mcu::rm5" pdk2
+#endif (METALS5)
+#ifdef METALS6
+#ifdef THICKMET3P0
+   magic::add_toolkit_command $layoutframe "rmtp - 9.5  mOhm/sq " "magic::gencell gf180mcu::rmtp" pdk2
+#elseif (THICKMET1P1 || THICKMET0P9)
+   magic::add_toolkit_command $layoutframe "rmtp - 40  mOhm/sq " "magic::gencell gf180mcu::rmtp" pdk2
+#else (!(THICKMET3P0 || THICKMET1P1 || THICKMET0P9))
+   magic::add_toolkit_command $layoutframe "rmtp - 60  mOhm/sq " "magic::gencell gf180mcu::rmtp" pdk2
+#endif (!(THICKMET3P0 || THICKMET1P1 || THICKMET0P9))
+#endif (METALS6)
+
+   magic::add_toolkit_separator	$layoutframe pdk2
+
+#ifdef MIM
+   magic::add_toolkit_command $layoutframe "mim_2p0fF - MiM cap " "magic::gencell gf180mcu::mim_2p0fF" pdk2
+#endif (MIM)
+   magic::add_toolkit_separator	$layoutframe pdk2
+
+   magic::add_toolkit_command $layoutframe "substrate contact (3.3V) " "gf180mcu::subcon_3p3_draw" pdk2
+   magic::add_toolkit_command $layoutframe "substrate contact (6.0V) " "gf180mcu::subcon_6p0_draw" pdk2
+   magic::add_toolkit_command $layoutframe "via1              " "gf180mcu::via1_draw" pdk2
+#ifdef METALS3 || METALS4 || METALS5 || METALS6
+   magic::add_toolkit_command $layoutframe "via2              " "gf180mcu::via2_draw" pdk2
+#endif (METALS3 || METALS4 || METALS5 || METALS6)
+#ifdef METALS4 || METALS5 || METALS6
+   magic::add_toolkit_command $layoutframe "via3              " "gf180mcu::via3_draw" pdk2
+#endif (METALS4 || METALS5 || METALS6)
+#ifdef METALS5 || METALS6
+   magic::add_toolkit_command $layoutframe "via4              " "gf180mcu::via4_draw" pdk2
+#endif (METALS5 || METALS6)
+#ifdef METALS6
+   magic::add_toolkit_command $layoutframe "viatp             " "gf180mcu::viatp_draw" pdk2
+#endif (METALS6)
+
+   ${layoutframe}.titlebar.mbuttons.drc.toolmenu add command -label "DRC Routing" -command {drc style drc(routing)}
+
+   # Add SPICE import function to File menu
+   ${layoutframe}.titlebar.mbuttons.file.toolmenu insert 4 command -label "Import SPICE" -command {gf180mcu::importspice}
+   ${layoutframe}.titlebar.mbuttons.file.toolmenu insert 4 separator
+
+   # Add command entry window by default if enabled
+   if {[info exists Opts(cmdentry)]} {
+      set Winopts(${framename},cmdentry) $Opts(cmdentry)
+   } else {
+      set Winopts(${framename},cmdentry) 0
+   }
+   if {$Winopts(${framename},cmdentry) == 1} {
+      addcommandentry $framename
+   }
+}
+
+#----------------------------------------------------------------
+# Menu callback function to read a SPICE netlist and generate an
+# initial layout using the SKYWATER sky130A gencells.
+#----------------------------------------------------------------
+
+proc gf180mcu::importspice {} {
+   global CAD_ROOT
+
+   set Layoutfilename [ tk_getOpenFile -filetypes \
+	    {{SPICE {.spice .spc .spi .ckt .cir .sp \
+	    {.spice .spc .spi .ckt .cir .sp}}} {"All files" {*}}}]
+   if {$Layoutfilename != ""} {
+      magic::netlist_to_layout $Layoutfilename gf180mcu
+   }
+}
+
+#----------------------------------------------------------------
+
+proc gf180mcu::via1_draw {} {
+   set w [magic::i2u [box width]]
+   set h [magic::i2u [box height]]
+   if {$w < 0.28} {
+      puts stderr "Via1 width must be at least 0.28um"
+      return
+   }
+   if {$h < 0.28} {
+      puts stderr "Via1 height must be at least 0.28um"
+      return
+   }
+   paint via1
+   box grow n 0.05um
+   box grow s 0.05um
+   paint m2
+   box grow n -0.05um
+   box grow s -0.05um
+   box grow e 0.05um
+   box grow w 0.05um
+   paint m1
+   box grow e -0.05um
+   box grow w -0.05um
+}
+
+#ifdef METALS3 || METALS4 || METALS5 || METALS6
+proc gf180mcu::via2_draw {} {
+   set w [magic::i2u [box width]]
+   set h [magic::i2u [box height]]
+   if {$w < 0.28} {
+      puts stderr "Via2 width must be at least 0.28um"
+      return
+   }
+   if {$h < 0.28} {
+      puts stderr "Via2 height must be at least 0.28um"
+      return
+   }
+   paint via2
+   box grow n 0.05um
+   box grow s 0.05um
+   paint m2
+   box grow n -0.05um
+   box grow s -0.05um
+   box grow e 0.05um
+   box grow w 0.05um
+   paint m3
+   box grow e -0.05um
+   box grow w -0.05um
+}
+#endif (METALS3 || METALS4 || METALS5 || METALS6)
+
+#ifdef METALS4 || METALS5 || METALS6
+proc gf180mcu::via3_draw {} {
+   set w [magic::i2u [box width]]
+   set h [magic::i2u [box height]]
+   if {$w < 0.28} {
+      puts stderr "Via3 width must be at least 0.28um"
+      return
+   }
+   if {$h < 0.28} {
+      puts stderr "Via3 height must be at least 0.28um"
+      return
+   }
+   paint via3
+   box grow n 0.05um
+   box grow s 0.05um
+   paint m4
+   box grow n -0.05um
+   box grow s -0.05um
+   box grow e 0.05um
+   box grow w 0.05um
+   paint m3
+   box grow e -0.05um
+   box grow w -0.05um
+}
+#endif (METALS4 || METALS5 || METALS6)
+
+#ifdef METALS5 || METALS6
+proc gf180mcu::via4_draw {} {
+   set w [magic::i2u [box width]]
+   set h [magic::i2u [box height]]
+   if {$w < 0.28} {
+      puts stderr "Via4 width must be at least 0.28um"
+      return
+   }
+   if {$h < 0.28} {
+      puts stderr "Via4 height must be at least 0.28um"
+      return
+   }
+   paint via4
+   box grow n 0.05um
+   box grow s 0.05um
+   paint m5
+   box grow n -0.05um
+   box grow s -0.05um
+   box grow e 0.05um
+   box grow w 0.05um
+   paint m4
+   box grow e -0.05um
+   box grow w -0.05um
+}
+#endif (METALS5 || METALS6)
+
+#ifdef METALS6
+proc gf180mcu::viatp_draw {} {
+   set w [magic::i2u [box width]]
+   set h [magic::i2u [box height]]
+   if {$w < 0.28} {
+      puts stderr "ViaTP width must be at least 0.28um"
+      return
+   }
+   if {$h < 0.28} {
+      puts stderr "ViaTP height must be at least 0.28um"
+      return
+   }
+   paint viatp
+   box grow c 0.08um
+   paint mtp
+   box grow c -0.08um
+   box grow e 0.05um
+   box grow w 0.05um
+   paint m5
+   box grow e -0.05um
+   box grow w -0.05um
+}
+#endif (METALS6)
+
+proc gf180mcu::subcon_3p3_draw {} {
+   set w [magic::i2u [box width]]
+   set h [magic::i2u [box height]]
+   if {$w < 0.23} {
+      puts stderr "Substrate tap width must be at least 0.23um"
+      return
+   }
+   if {$h < 0.23} {
+      puts stderr "Substrate tap height must be at least 0.23um"
+      return
+   }
+   paint subdiffc
+   box grow c 0.1um
+   paint subdiff
+   box grow c 0.1um
+   paint pwell
+   box grow c -0.2um
+}
+
+#----------------------------------------------------------------
+
+proc gf180mcu::subconmos_6p0_draw {} {
+   set w [magic::i2u [box width]]
+   set h [magic::i2u [box height]]
+   if {$w < 0.23} {
+      puts stderr "Substrate tap width must be at least 0.23um"
+      return
+   }
+   if {$h < 0.23} {
+      puts stderr "Substrate tap height must be at least 0.23um"
+      return
+   }
+   paint mvsubdiffc
+   box grow c 0.1um
+   paint mvsubdiff
+   box grow c 0.1um
+   paint pwell
+   box grow c -0.2um
+}
+
+#----------------------------------------------------------------
+
+proc gf180mcu::res_recalc {field parameters} {
+    set snake 0
+    set sterm 0.0
+    set caplen 0
+    # Set a local variable for each parameter (e.g., $l, $w, etc.)
+    foreach key [dict keys $parameters] {
+        set $key [dict get $parameters $key]
+    }
+    set val [magic::spice2float $val]
+    set l [magic::spice2float $l]
+    set w [magic::spice2float $w]
+
+    if {$snake == 0} {
+	# Straight resistor calculation
+	switch  $field {
+	    val { set l [expr ($val * ($w - $dw) - (2 * $term)) / $rho]
+		  set w [expr ((2 * $term + $l * $rho) / $val) + $dw]
+		}
+	    w   { set val [expr (2 * $term + $l * $rho) / ($w - $dw)]
+		  set l [expr ($val * ($w - $dw) - (2 * $term)) / $rho]
+		}
+	    l   { set val [expr (2 * $term + $l * $rho) / ($w - $dw)]
+		  set w [expr ((2 * $term + $l * $rho) / $val) + $dw]
+		}
+	}
+    } else {
+        set term [expr $term + $sterm]
+	# Snake resistor calculation
+	switch  $field {
+	    val { set l [expr (($val - $rho * ($nx - 1)) * ($w - $dw) \
+			- (2 * $term) - ($rho * $caplen * ($nx - 1))) \
+			/ ($rho * $nx)]
+
+		  set w [expr ((2 * $term + $l * $rho * $nx \
+			+ $caplen * $rho * ($nx - 1)) \
+			/ ($val - $rho * ($nx - 1))) + $dw]
+		}
+	    w   { set val [expr $rho * ($nx - 1) + ((2 * $term) \
+			+ ($rho * $l * $nx) + ($rho * $caplen * ($nx - 1))) \
+			/ ($w - $dw)]
+
+		  set l [expr (($val - $rho * ($nx - 1)) * ($w - $dw) \
+			- (2 * $term) - ($rho * $caplen * ($nx - 1))) \
+			/ ($rho * $nx)]
+		}
+	    l   { set val [expr $rho * ($nx - 1) + ((2 * $term) \
+			+ ($rho * $l * $nx) + ($rho * $caplen * ($nx - 1))) \
+			/ ($w - $dw)]
+
+		  set w [expr ((2 * $term + $l * $rho * $nx \
+			+ $caplen * $rho * ($nx - 1)) \
+			/ ($val - $rho * ($nx - 1))) + $dw]
+		}
+	}
+    }
+
+    set val [magic::3digitpastdecimal $val]
+    set w [magic::3digitpastdecimal $w]
+    set l [magic::3digitpastdecimal $l]
+
+    dict set parameters val $val
+    dict set parameters w $w
+    dict set parameters l $l
+
+    return $parameters
+}
+
+#----------------------------------------------------------------
+# Drawn diode routines
+#----------------------------------------------------------------
+
+proc gf180mcu::diode_recalc {field parameters} {
+    # Set a local variable for each parameter (e.g., $l, $w, etc.)
+    foreach key [dict keys $parameters] {
+        set $key [dict get $parameters $key]
+    }
+    switch  $field {
+	area { puts stdout "area changed" }
+	peri { puts stdout "perimeter changed" }
+	w   { puts stdout "width changed" }
+	l   { puts stdout "length changed" }
+    }
+    dict set parameters area $area
+    dict set parameters peri $peri
+    dict set parameters w $w
+    dict set parameters l $l
+}
+
+#----------------------------------------------------------------
+# diode: Conversion from SPICE netlist parameters to toolkit
+#----------------------------------------------------------------
+
+proc gf180mcu::diode_convert {parameters} {
+    set pdkparams [dict create]
+    dict for {key value} $parameters {
+	switch -nocase $key {
+	    l -
+	    w -
+	    peri {
+		# Length, width, and perimeter are converted to units of microns
+		set value [magic::spice2float $value]
+		set value [expr $value * 1e6]
+		set value [magic::3digitpastdecimal $value]
+		dict set pdkparams [string tolower $key] $value
+	    }
+	    area {
+		# area also converted to units of microns
+		set value [magic::spice2float $value]
+		set value [expr $value * 1e12]
+		set value [magic::3digitpastdecimal $value]
+		dict set pdkparams [string tolower $key] $value
+	    }
+	    m {
+                # Convert m to ny
+		dict set pdkparams ny $value
+	    }
+	}
+    }
+    return $pdkparams
+}
+
+#----------------------------------------------------------------
+# diode: Interactively specifies the fixed layout parameters
+#----------------------------------------------------------------
+
+proc gf180mcu::diode_dialog {device parameters} {
+    # Editable fields:      w, l, area, perim, nx, ny
+
+    magic::add_entry area "Area (um^2)" $parameters
+    magic::add_entry peri "Perimeter (um)" $parameters
+    gf180mcu::compute_aptot $parameters
+    magic::add_message atot "Total area (um^2)" $parameters
+    magic::add_message ptot "Total perimeter (um)" $parameters
+    magic::add_entry l "Length (um)" $parameters
+    magic::add_entry w "Width (um)" $parameters
+    magic::add_entry nx "X Repeat" $parameters
+    magic::add_entry ny "Y Repeat" $parameters
+
+    if {[dict exists $parameters compatible]} {
+       set sellist [dict get $parameters compatible]
+       # Reserved word "gencell" has special behavior to change the
+       # underlying device type 
+       dict set parameters gencell $device
+       magic::add_selectlist gencell "Device type" $sellist $parameters
+    }
+
+    magic::add_checkbox doverlap "Overlap at end contact" $parameters
+
+    if {[dict exists $parameters elc]} {
+        magic::add_checkbox elc "Add left end contact" $parameters
+    }
+    if {[dict exists $parameters erc]} {
+        magic::add_checkbox erc "Add right end contact" $parameters
+    }
+    if {[dict exists $parameters etc]} {
+        magic::add_checkbox etc "Add top end contact" $parameters
+    }
+    if {[dict exists $parameters ebc]} {
+        magic::add_checkbox ebc "Add bottom end contact" $parameters
+    }
+
+    if {[dict exists $parameters guard]} {
+        magic::add_checkbox full_metal "Full metal guard ring" $parameters
+    }
+    if {[dict exists $parameters glc]} {
+        magic::add_checkbox glc "Add left guard ring contact" $parameters
+    }
+    if {[dict exists $parameters grc]} {
+        magic::add_checkbox grc "Add right guard ring contact" $parameters
+    }
+    if {[dict exists $parameters gtc]} {
+        magic::add_checkbox gtc "Add top guard ring contact" $parameters
+    }
+    if {[dict exists $parameters gbc]} {
+        magic::add_checkbox gbc "Add bottom guard ring contact" $parameters
+    }
+
+    magic::add_dependency gf180mcu::diode_recalc $device gf180mcu l w area peri
+
+    # magic::add_checkbox dummy "Add dummy" $parameters
+}
+
+#----------------------------------------------------------------
+# Diode total area and perimeter computation
+#----------------------------------------------------------------
+
+proc gf180mcu::compute_aptot {parameters} {
+    foreach key [dict keys $parameters] {
+        set $key [dict get $parameters $key]
+    }
+    set area [magic::spice2float $area]
+    set area [magic::3digitpastdecimal $area]
+    set peri [magic::spice2float $peri]
+    set peri [magic::3digitpastdecimal $peri]
+
+    # Compute total area
+    catch {set magic::atot_val [expr ($area * $nx * $ny)]}
+    # Compute total perimeter
+    catch {set magic::ptot_val [expr ($peri * $nx * $ny)]}
+}
+
+#----------------------------------------------------------------
+# diode: Check device parameters for out-of-bounds values
+#----------------------------------------------------------------
+
+proc gf180mcu::diode_check {parameters} {
+
+    # Set a local variable for each parameter (e.g., $l, $w, etc.)
+    foreach key [dict keys $parameters] {
+        set $key [dict get $parameters $key]
+    }
+
+    # Normalize distance units to microns
+    set l [magic::spice2float $l]
+    set l [magic::3digitpastdecimal $l] 
+    set w [magic::spice2float $w]
+    set w [magic::3digitpastdecimal $w] 
+
+    set area [magic::spice2float $area]
+    set area [magic::3digitpastdecimal $area] 
+    set peri [magic::spice2float $peri]
+    set peri [magic::3digitpastdecimal $peri] 
+
+    if {$l == 0} {
+        # Calculate L from W and area
+	set l [expr ($area / $w)]
+	dict set parameters l [magic::float2spice $l]
+    } elseif {$w == 0} {
+        # Calculate W from L and area
+	set w [expr ($area / $l)]
+	dict set parameters w [magic::float2spice $w]
+    }
+    if {$w < $wmin} {
+	puts stderr "Diode width must be >= $wmin"
+	dict set parameters w $wmin
+    } 
+    if {$l < $lmin} {
+	puts stderr "Diode length must be >= $lmin"
+	dict set parameters l $lmin
+    } 
+    # Calculate area and perimeter from L and W
+    set area [expr ($l * $w)]
+    dict set parameters area [magic::float2spice $area]
+    set peri [expr (2 * ($l + $w))]
+    dict set parameters peri [magic::float2spice $peri]
+    gf180mcu::compute_aptot $parameters
+
+    return $parameters
+}
+
+#----------------------------------------------------------------
+
+proc gf180mcu::np_3p3_defaults {} {
+    return {w 0.45 l 0.45 area 0.2025 peri 1.8 \
+	nx 1 ny 1 dummy 0 lmin 0.45 wmin 0.45 \
+	elc 1 erc 1 etc 1 ebc 1 doverlap 0 full_metal 1 \
+	compatible {np_3p3 np_6p0 np_6p0_nat}}
+}
+
+proc gf180mcu::pn_3p3_defaults {} {
+    return {w 0.45 l 0.45 area 0.2025 peri 1.8 \
+	nx 1 ny 1 dummy 0 lmin 0.45 wmin 0.45 \
+	elc 1 erc 1 etc 1 ebc 1 \
+	glc 1 grc 1 gtc 0 gbc 0 doverlap 0 full_metal 1 \
+	compatible {pn_3p3 pn_6p0}}
+}
+
+proc gf180mcu::np_6p0_defaults {} {
+    return {w 0.45 l 0.45 area 0.2025 peri 1.8 \
+	nx 1 ny 1 dummy 0 lmin 0.45 wmin 0.45 \
+	elc 1 erc 1 etc 1 ebc 1 doverlap 0 \
+	full_metal 1 \
+	compatible {np_3p3 np_6p0 np_6p0_nat}}
+}
+
+proc gf180mcu::np_6p0_nat_defaults {} {
+    return {w 0.45 l 0.45 area 0.2025 peri 1.8 \
+	nx 1 ny 1 dummy 0 lmin 0.45 wmin 0.45 \
+	elc 1 erc 1 etc 1 ebc 1 doverlap 0 \
+	full_metal 1 \
+	compatible {np_3p3 np_6p0 np_6p0_nat}}
+}
+
+proc gf180mcu::pn_6p0_defaults {} {
+    return {w 0.45 l 0.45 area 0.2025 peri 1.8 \
+	nx 1 ny 1 dummy 0 lmin 0.45 wmin 0.45 \
+	elc 1 erc 1 etc 1 ebc 1 \
+	glc 1 grc 1 gtc 0 gbc 0 doverlap 0 \
+	compatible {pn_3p3 pn_6p0}}
+}
+
+#----------------------------------------------------------------
+
+proc gf180mcu::np_3p3_convert {parameters} {
+    return [gf180mcu::diode_convert $parameters]
+}
+
+proc gf180mcu::pn_3p3_convert {parameters} {
+    return [gf180mcu::diode_convert $parameters]
+}
+
+proc gf180mcu::np_6p0_convert {parameters} {
+    return [gf180mcu::diode_convert $parameters]
+}
+
+proc gf180mcu::np_6p0_nat_convert {parameters} {
+    return [gf180mcu::diode_convert $parameters]
+}
+
+proc gf180mcu::pn_6p0_convert {parameters} {
+    return [gf180mcu::diode_convert $parameters]
+}
+
+#----------------------------------------------------------------
+
+proc gf180mcu::np_3p3_dialog {parameters} {
+    gf180mcu::diode_dialog np_3p3 $parameters
+}
+
+proc gf180mcu::pn_3p3_dialog {parameters} {
+    gf180mcu::diode_dialog pn_3p3 $parameters
+}
+
+proc gf180mcu::np_6p0_dialog {parameters} {
+    gf180mcu::diode_dialog np_6p0 $parameters
+}
+
+proc gf180mcu::np_6p0_nat_dialog {parameters} {
+    gf180mcu::diode_dialog np_6p0_nat $parameters
+}
+
+proc gf180mcu::pn_6p0_dialog {parameters} {
+    gf180mcu::diode_dialog pn_6p0 $parameters
+}
+
+#----------------------------------------------------------------
+
+proc gf180mcu::np_3p3_check {parameters} {
+    gf180mcu::diode_check $parameters
+}
+
+proc gf180mcu::pn_3p3_check {parameters} {
+    gf180mcu::diode_check $parameters
+}
+
+proc gf180mcu::np_6p0_check {parameters} {
+    gf180mcu::diode_check $parameters
+}
+
+proc gf180mcu::np_6p0_nat_check {parameters} {
+    gf180mcu::diode_check $parameters
+}
+
+proc gf180mcu::pn_6p0_check {parameters} {
+    gf180mcu::diode_check $parameters
+}
+
+#----------------------------------------------------------------
+# Diode: Draw a single device
+#----------------------------------------------------------------
+
+proc gf180mcu::diode_device {parameters} {
+    # Epsilon for avoiding round-off errors
+    set eps  0.0005
+
+    # Set local default values if they are not in parameters
+    set dev_surround 0
+    set dev_sub_type ""
+
+    # Set a local variable for each parameter (e.g., $l, $w, etc.)
+    foreach key [dict keys $parameters] {
+        set $key [dict get $parameters $key]
+    }
+
+    if {![dict exists $parameters end_contact_size]} {
+	set end_contact_size $contact_size
+    }
+
+    # Draw the device
+    pushbox
+    box size 0 0
+
+    set hw [/ $w 2.0]
+    set hl [/ $l 2.0]
+
+    # Calculate ring size (measured to contact center)
+    set gx [+ $w [* 2.0 [+ $dev_spacing $dev_surround]] $end_contact_size]
+    set gy [+ $l [* 2.0 [+ $dev_spacing $dev_surround]] $end_contact_size]
+
+    # Draw the ring first, because diode may occupy well/substrate plane
+    set guardparams $parameters
+    dict set guardparams plus_diff_type $end_type
+    dict set guardparams plus_contact_type $end_contact_type
+    dict set guardparams contact_size $end_contact_size
+    dict set guardparams diff_surround $end_surround
+    dict set guardparams sub_type $end_sub_type
+    dict set guardparams glc $elc
+    dict set guardparams grc $erc
+    dict set guardparams gtc $etc
+    dict set guardparams gbc $ebc
+    set cext [gf180mcu::guard_ring $gx $gy $guardparams]
+
+    pushbox
+    box grow n ${hl}um
+    box grow s ${hl}um
+    box grow e ${hw}um
+    box grow w ${hw}um
+    paint ${dev_type}
+    set cext [gf180mcu::unionbox $cext [gf180mcu::getbox]]
+
+    if {$dev_sub_type != ""} {
+	box grow n ${sub_surround}um
+	box grow s ${sub_surround}um
+	box grow e ${sub_surround}um
+	box grow w ${sub_surround}um
+	paint ${dev_sub_type}
+    }
+    popbox
+
+    if {${w} < ${l}} {
+	set orient vert
+    } else {
+	set orient horz
+    }
+
+    # Reduce width by surround amount
+    set w [- $w [* ${dev_surround} 2.0]]
+    set l [- $l [* ${dev_surround} 2.0]]
+
+    set cext [gf180mcu::unionbox $cext [gf180mcu::draw_contact ${w} ${l} \
+		${dev_surround} ${metal_surround} ${contact_size} \
+		${dev_type} ${dev_contact_type} m1 ${orient}]]
+
+    popbox
+    return $cext
+}
+
+#----------------------------------------------------------------
+# Diode: Draw the tiled device
+#----------------------------------------------------------------
+
+proc gf180mcu::diode_draw {parameters} {
+    tech unlock *
+
+    # Set defaults if they are not in parameters
+    set doverlap 0	;# overlap diodes at contacts
+    set guard 0		;# draw a guard ring
+
+    # Set a local variable for each parameter (e.g., $l, $w, etc.)
+    foreach key [dict keys $parameters] {
+        set $key [dict get $parameters $key]
+    }
+
+    # Normalize distance units to microns
+    set w [magic::spice2float $w]
+    set l [magic::spice2float $l]
+
+    pushbox
+    box values 0 0 0 0
+
+    # Determine the base device dimensions by drawing one device
+    # while all layers are locked (nothing drawn).  This allows the
+    # base drawing routine to do complicated geometry without having
+    # to duplicate it here with calculations.
+
+    tech lock *
+    set bbox [gf180mcu::diode_device $parameters]
+    # puts stdout "Diagnostic: Device bounding box e $bbox (um)"
+    tech unlock *
+
+    set fw [- [lindex $bbox 2] [lindex $bbox 0]]
+    set fh [- [lindex $bbox 3] [lindex $bbox 1]]
+    set lw [+ [lindex $bbox 2] [lindex $bbox 0]]
+    set lh [+ [lindex $bbox 3] [lindex $bbox 1]]
+
+    # Determine tile width and height (depends on overlap)
+
+    if {$doverlap == 0} {
+	set dx [+ $fw $end_spacing]
+        set dy [+ $fh $end_spacing]
+    } else {
+        # overlap contact
+        set dx [- $fw [+ [* 2.0 $sub_surround] [* 2.0 $end_surround] $contact_size]]
+        set dy [- $fh [+ [* 2.0 $sub_surround] [* 2.0 $end_surround] $contact_size]]
+    }
+
+    # Determine core width and height
+    set corex [+ [* [- $nx 1] $dx] $fw]
+    set corey [+ [* [- $ny 1] $dy] $fh]
+    set corellx [/ [+ [- $corex $fw] $lw] 2.0]
+    set corelly [/ [+ [- $corey $fh] $lh] 2.0]
+
+    if {$guard != 0} {
+	# Calculate guard ring size (measured to contact center)
+	set gx [+ $corex [* 2.0 [+ $diff_spacing $diff_surround]] $contact_size]
+	set gy [+ $corey [* 2.0 [+ $diff_spacing $diff_surround]] $contact_size]
+
+	# Draw the guard ring first, because diode may occupy well/substrate plane
+	gf180mcu::guard_ring $gx $gy $parameters
+    }
+
+    pushbox
+    box move w ${corellx}um
+    box move s ${corelly}um
+    if {($nx > 1) || ($ny > 1)} {
+	pushbox
+	set hfw [/ $fw 2.0]
+	set hfh [/ $fh 2.0]
+	box move w ${hfw}um
+	box move s ${hfh}um
+	box size ${corex}um ${corey}um
+	paint $end_sub_type
+	popbox
+    }
+    for {set xp 0} {$xp < $nx} {incr xp} {
+	pushbox
+	for {set yp 0} {$yp < $ny} {incr yp} {
+	    gf180mcu::diode_device $parameters
+            box move n ${dy}um
+        }
+	popbox
+        box move e ${dx}um
+    }
+    popbox
+    popbox
+
+    tech revert
+}
+
+#----------------------------------------------------------------
+
+proc gf180mcu::np_3p3_draw {parameters} {
+
+    # Set a local variable for each rule in ruleset
+    foreach key [dict keys $gf180mcu::ruleset] {
+        set $key [dict get $gf180mcu::ruleset $key]
+    }
+
+    set newdict [dict create \
+	    dev_type		ndiode \
+	    dev_contact_type	ndic \
+	    end_type		psd \
+	    end_contact_type	psc \
+	    end_contact_size	0.16 \
+	    end_sub_type	pwell \
+	    dev_spacing		0.25 \
+	    dev_surround	${diff_surround} \
+	    end_spacing		${diff_spacing} \
+	    end_surround	${diff_surround} \
+    ]
+    set drawdict [dict merge $gf180mcu::ruleset $newdict $parameters]
+    return [gf180mcu::diode_draw $drawdict]
+} 
+
+#----------------------------------------------------------------
+
+proc gf180mcu::pn_3p3_draw {parameters} {
+
+    # Set a local variable for each rule in ruleset
+    foreach key [dict keys $gf180mcu::ruleset] {
+        set $key [dict get $gf180mcu::ruleset $key]
+    }
+
+    set newdict [dict create \
+	    guard		1 \
+	    dev_type		pdiode \
+	    dev_contact_type	pdic \
+	    end_type		nsd \
+	    end_contact_type	nsc \
+	    end_contact_size	0.16 \
+	    end_sub_type	nwell \
+	    plus_diff_type	psd \
+	    plus_contact_type	psc \
+	    sub_type		pwell \
+	    dev_spacing		0.25 \
+	    dev_surround	${diff_surround} \
+	    end_spacing		${diff_spacing} \
+	    end_surround	${diff_surround} \
+    ]
+    set drawdict [dict merge $gf180mcu::ruleset $newdict $parameters]
+    return [gf180mcu::diode_draw $drawdict]
+}
+
+#----------------------------------------------------------------
+
+proc gf180mcu::np_6p0_draw {parameters} {
+
+    # Set a local variable for each rule in ruleset
+    foreach key [dict keys $gf180mcu::ruleset] {
+        set $key [dict get $gf180mcu::ruleset $key]
+    }
+
+    set newdict [dict create \
+	    diff_poly_space	0.30 \
+	    diff_gate_space	0.30 \
+	    diff_spacing	0.36 \
+	    dev_type		mvndiode \
+	    dev_contact_type	mvndic \
+	    end_type		mvpsd \
+	    end_contact_type	mvpsc \
+	    end_sub_type	pwell \
+	    dev_spacing		0.25 \
+	    dev_surround	${diff_surround} \
+	    end_spacing		0.36 \
+	    end_surround	${diff_surround} \
+    ]
+    set drawdict [dict merge $gf180mcu::ruleset $newdict $parameters]
+    return [gf180mcu::diode_draw $drawdict]
+}
+
+#----------------------------------------------------------------
+
+proc gf180mcu::np_6p0_nat_draw {parameters} {
+
+    # Set a local variable for each rule in ruleset
+    foreach key [dict keys $gf180mcu::ruleset] {
+        set $key [dict get $gf180mcu::ruleset $key]
+    }
+
+    set newdict [dict create \
+	    dev_type		mvnndiode \
+	    dev_contact_type	mvnndic \
+	    end_type		mvpsd \
+	    end_contact_type	mvpsc \
+	    end_sub_type	pwell \
+	    dev_spacing		0.64 \
+	    dev_surround	${diff_surround} \
+	    end_spacing		0.36 \
+	    end_surround	${diff_surround} \
+    ]
+    set drawdict [dict merge $gf180mcu::ruleset $newdict $parameters]
+    return [gf180mcu::diode_draw $drawdict]
+}
+
+#----------------------------------------------------------------
+
+#----------------------------------------------------------------
+
+proc gf180mcu::pn_6p0_draw {parameters} {
+
+    # Set a local variable for each rule in ruleset
+    foreach key [dict keys $gf180mcu::ruleset] {
+        set $key [dict get $gf180mcu::ruleset $key]
+    }
+
+    set newdict [dict create \
+	    diff_poly_space	0.30 \
+	    diff_gate_space	0.30 \
+	    diff_spacing	0.36 \
+	    guard		1 \
+	    dev_type 		mvpdiode \
+	    dev_contact_type	mvpdic \
+	    end_type		mvnsd \
+	    end_contact_type	mvnsc \
+	    end_sub_type	nwell \
+	    plus_diff_type	mvpsd \
+	    plus_contact_type	mvpsc \
+	    sub_type		pwell \
+	    dev_spacing		${diff_spacing} \
+	    dev_surround	${diff_surround} \
+	    end_spacing		${diff_spacing} \
+	    end_surround	${diff_surround} \
+    ]
+    set drawdict [dict merge $gf180mcu::ruleset $newdict $parameters]
+    return [gf180mcu::diode_draw $drawdict]
+}
+
+#----------------------------------------------------------------
+# Drawn capactitor routines
+#----------------------------------------------------------------
+# MiM minimum size set to 2.165 to prevent isolated via
+
+#ifdef MIM
+proc gf180mcu::mim_2p0fF_defaults {} {
+    return {w 5.00 l 5.00 val 50.000 carea 25.00 cperi 20.00 \
+		nx 1 ny 1 dummy 0 square 0 lmin 5.00 wmin 5.00 \
+		lmax 100.0 wmax 100.0 dc 0 bconnect 1 tconnect 1}
+}
+#endif MIM
+
+#----------------------------------------------------------------
+# Recalculate capacitor values from GUI entries.
+# Recomputes W/L and Value as long as 2 of them are present
+# (To be completed)
+#----------------------------------------------------------------
+
+proc gf180mcu::cap_recalc {field parameters} {
+    # Set a local variable for each parameter (e.g., $l, $w, etc.)
+    foreach key [dict keys $parameters] {
+        set $key [dict get $parameters $key]
+    }
+    switch  $field {
+	val { puts stdout "value changed" }
+	w   { puts stdout "width changed" }
+	l   { puts stdout "length changed" }
+    }
+    dict set parameters val $val
+    dict set parameters w $w
+    dict set parameters l $l
+}
+
+#----------------------------------------------------------------
+# Capacitor defaults:
+#----------------------------------------------------------------
+#  w      Width of drawn cap
+#  l      Length of drawn cap
+#  nx     Number of devices in X
+#  ny     Number of devices in Y
+#  val    Default cap value
+#  carea  Area
+#  cperi  Perimeter
+#  dummy  Add dummy cap
+#  square Make square capacitor
+#
+#  (not user-editable)
+#
+#  wmin   Minimum allowed width
+#  lmin   Minimum allowed length
+#  dc     Area to remove to calculated area 
+#----------------------------------------------------------------
+
+#----------------------------------------------------------------
+# capacitor: Conversion from SPICE netlist parameters to toolkit
+#----------------------------------------------------------------
+
+proc gf180mcu::cap_convert {parameters} {
+    set pdkparams [dict create]
+    dict for {key value} $parameters {
+	set canonkey $key
+	switch -nocase $key {
+	    c_length -
+	    c_width -
+	    l -
+	    w {
+		switch -nocase $key {
+		    c_length {
+			set canonkey l
+		    }
+		    c_width {
+			set canonkey w
+		    }
+		}
+		# Length and width are converted to units of microns
+		set value [magic::spice2float $value]
+		set value [expr $value * 1e6]
+		set value [magic::3digitpastdecimal $value]
+		dict set pdkparams [string tolower $canonkey] $value
+	    }
+	    m {
+                # Convert m to ny
+		dict set pdkparams ny $value
+	    }
+	}
+    }
+    return $pdkparams
+}
+
+#ifdef MIM
+proc gf180mcu::mim_2p0fF_convert {parameters} {
+    return [cap_convert $parameters]
+}
+#endif
+
+#----------------------------------------------------------------
+# capacitor: Interactively specifies the fixed layout parameters
+#----------------------------------------------------------------
+
+proc gf180mcu::cap_dialog {device parameters} {
+    # Editable fields:      w, l, nx, ny, val
+    # Checked fields:  	    square, dummy
+
+    magic::add_entry val "Value (fF)" $parameters
+    gf180mcu::compute_ctot $parameters
+    magic::add_message ctot "Total capacitance (pF)" $parameters
+    magic::add_entry l "Length (um)" $parameters
+    magic::add_entry w "Width (um)" $parameters
+    magic::add_entry nx "X Repeat" $parameters
+    magic::add_entry ny "Y Repeat" $parameters
+
+    if {[dict exists $parameters square]} {
+	magic::add_checkbox square "Square capacitor" $parameters
+    }
+    if {[dict exists $parameters bconnect]} {
+	magic::add_checkbox bconnect "Connect bottom plates in array" $parameters
+    }
+    if {[dict exists $parameters tconnect]} {
+	magic::add_checkbox tconnect "Connect top plates in array" $parameters
+    }
+
+    magic::add_dependency gf180mcu::cap_recalc $device gf180mcu l w val
+
+    # magic::add_checkbox dummy "Add dummy" $parameters
+}
+
+#ifdef MIM
+proc gf180mcu::mim_2p0fF_dialog {parameters} {
+    gf180mcu::cap_dialog mim_2p0fF $parameters
+}
+#endif
+
+#----------------------------------------------------------------
+# Capacitor total capacitance computation
+#----------------------------------------------------------------
+
+proc gf180mcu::compute_ctot {parameters} {
+    foreach key [dict keys $parameters] {
+        set $key [dict get $parameters $key]
+    }
+    set val [magic::spice2float $val]
+    set val [magic::3digitpastdecimal $val]
+
+    # Compute total capacitance (and convert fF to pF)
+    catch {set magic::ctot_val [expr (0.001 * $val * $nx * $ny)]}
+}
+
+#----------------------------------------------------------------
+# Capacitor: Draw a single device
+#----------------------------------------------------------------
+
+proc gf180mcu::cap_device {parameters} {
+    # Epsilon for avoiding round-off errors
+    set eps  0.0005
+
+    # Set local default values if they are not in parameters
+    set cap_surround 0
+    set bot_surround 0
+    set top_surround 0
+
+    # Set a local variable for each parameter (e.g., $l, $w, etc.)
+    foreach key [dict keys $parameters] {
+        set $key [dict get $parameters $key]
+    }
+
+    # Draw the device
+    pushbox
+    box size 0 0
+
+    pushbox
+    set hw [/ $w 2.0]
+    set hl [/ $l 2.0]
+    box grow e ${hw}um
+    box grow w ${hw}um
+    box grow n ${hl}um
+    box grow s ${hl}um
+    paint ${cap_type}
+    pushbox
+    box grow n -${cap_surround}um
+    box grow s -${cap_surround}um
+    box grow e -${cap_surround}um
+    box grow w -${cap_surround}um
+    paint ${cap_contact_type}
+    pushbox
+    box grow n ${top_surround}um
+    box grow s ${top_surround}um
+    box grow e ${top_surround}um
+    box grow w ${top_surround}um
+    paint ${top_type}
+    set cext [gf180mcu::getbox]
+    popbox
+    popbox
+    pushbox
+    box grow n ${bot_surround}um
+    box grow s ${bot_surround}um
+    box grow e ${bot_surround}um
+    box grow w ${bot_surround}um
+
+    paint ${bot_type}
+    property FIXED_BBOX [box values]
+    set cext [gf180mcu::unionbox $cext [gf180mcu::getbox]]
+
+    # Extend bottom metal under contact to right
+    box grow e ${end_spacing}um
+    set chw [/ ${contact_size} 2.0]
+    box grow e ${chw}um
+    box grow e ${end_surround}um
+    paint ${bot_type}
+
+    popbox
+    popbox
+
+    # Draw contact to right
+    pushbox
+    box move e ${hw}um
+    box move e ${bot_surround}um
+    box move e ${end_spacing}um
+    set cl [- [+ ${l} [* ${bot_surround} 2.0]] [* ${end_surround} 2.0]]
+    set cl [- ${cl} ${metal_surround}]  ;# see below
+    set cext [gf180mcu::unionbox $cext [gf180mcu::draw_contact 0 ${cl} \
+		${end_surround} ${metal_surround} ${contact_size} \
+		${bot_type} ${top_contact_type} ${top_type} vert]]
+    popbox
+    popbox
+
+    return $cext
+
+    # cl shrinks top and bottom to accomodate larger bottom metal
+    # surround rule for contacts near a MiM cap.  This should be its
+    # own variable, but metal_surround is sufficient.
+}
+
+#----------------------------------------------------------------
+# Metal plate sandwich capacitor:  Draw a single device
+#----------------------------------------------------------------
+
+proc gf180mcu::sandwich_cap_device {parameters} {
+
+    # Set a local variable for each parameter (e.g., $l, $w, etc.)
+    foreach key [dict keys $parameters] {
+        set $key [dict get $parameters $key]
+    }
+
+    pushbox
+    box size 0 0
+
+    set hw [/ $w 2.0]
+    set hl [/ $l 2.0]
+
+    set cw [- [* $hw [/ 2.0 3]] [* $cont_surround 2.0]]
+    set cl [- [* $hl [/ 2.0 3]] [* $cont_surround 2.0]]
+
+    # plate capacitor defines layers p0, p1, etc.
+    for {set i 0} {$i < 20} {incr i} {
+        if {[catch {set layer [subst \$p${i}_type]}]} {break}  ;# no more layers defined
+	pushbox
+	box grow e ${hw}um
+	box grow w ${hw}um
+	box grow n ${hl}um
+	box grow s ${hl}um
+        if {![catch {set shrink [subst \$p${i}_shrink]}]} {
+	    box grow e -${shrink}um
+	    box grow w -${shrink}um
+	    box grow n -${shrink}um
+	    box grow s -${shrink}um
+	    set cutout_spacing [+ [* ${shrink} 2.0] [/ $via_size 2.0] $cont_surround]
+	} else {
+	    set cutout_spacing 0
+	}
+
+	paint ${layer}
+
+	if {$i == 1} {
+	    # Note that cap_type geometry is coincident with p1_type.
+	    # Typically, this will define a layer that outputs as both
+	    # poly and a capacitor definition layer.
+	    if {[dict exists $parameters cap_type]} {
+		paint $cap_type
+	    }
+	}
+	popbox
+
+	# Even layers connect at corners, odd layers connect at sides.
+	# Even layers cut out the sides, odd layers cut out the corners.
+	# Layer zero has no side contacts or cutout.
+
+	if {[% $i 2] == 0} {
+	    set cornercmd  paint
+	    set cornersize $cutout_spacing
+	    set sidecmd    erase
+	    set nssidelong   [+ $cutout_spacing [/ $hw 3.0]]
+	    set ewsidelong   [+ $cutout_spacing [/ $hl 3.0]]
+	    set sideshort    $cutout_spacing
+	} else {
+	    set cornercmd  erase
+	    set cornersize $cutout_spacing
+	    set sidecmd    paint
+	    set nssidelong   [/ $hw 3.0]
+	    set ewsidelong   [/ $hl 3.0]
+	    set sideshort    $cutout_spacing
+	}
+
+	if {$i > 0} {
+	    pushbox
+	    box move e ${hw}um
+	    box grow n ${ewsidelong}um
+	    box grow s ${ewsidelong}um
+	    box grow w ${sideshort}um
+	    ${sidecmd} ${layer}
+	    popbox
+	    pushbox
+	    box move n ${hl}um
+	    box grow e ${nssidelong}um
+	    box grow w ${nssidelong}um
+	    box grow s ${sideshort}um
+	    ${sidecmd} ${layer}
+	    popbox
+	    pushbox
+	    box move w ${hw}um
+	    box grow n ${ewsidelong}um
+	    box grow s ${ewsidelong}um
+	    box grow e ${sideshort}um
+	    ${sidecmd} ${layer}
+	    popbox
+	    pushbox
+	    box move s ${hl}um
+	    box grow e ${nssidelong}um
+	    box grow w ${nssidelong}um
+	    box grow n ${sideshort}um
+	    ${sidecmd} ${layer}
+	    popbox
+
+	    pushbox
+	    box move n ${hl}um
+	    box move e ${hw}um
+	    box grow s ${cornersize}um
+	    box grow w ${cornersize}um
+	    ${cornercmd} ${layer}
+	    popbox
+	    pushbox
+	    box move n ${hl}um
+	    box move w ${hw}um
+	    box grow s ${cornersize}um
+	    box grow e ${cornersize}um
+	    ${cornercmd} ${layer}
+	    popbox
+	    pushbox
+	    box move s ${hl}um
+	    box move e ${hw}um
+	    box grow n ${cornersize}um
+	    box grow w ${cornersize}um
+	    ${cornercmd} ${layer}
+	    popbox
+	    pushbox
+	    box move s ${hl}um
+	    box move w ${hw}um
+	    box grow n ${cornersize}um
+	    box grow e ${cornersize}um
+	    ${cornercmd} ${layer}
+	    popbox
+	}
+    }
+
+    # Draw contacts after all layers have been drawn, so that erasing
+    # layers does not affect the contacts.
+
+    for {set i 0} {$i < 20} {incr i} {
+        if {![catch {set contact [subst \$p${i}_contact_type]}]} {
+	    set layer [subst \$p${i}_type]
+	    set j [+ $i 1]
+	    set toplayer [subst \$p${j}_type]
+
+	    # Draw corner contacts
+	    pushbox
+	    box move e ${hw}um
+	    box move n ${hl}um
+	    gf180mcu::draw_contact 0 0 \
+			${cont_surround} ${cont_surround} ${via_size} \
+			${layer} ${contact} ${toplayer} full
+	    popbox
+	    pushbox
+	    box move w ${hw}um
+	    box move n ${hl}um
+	    gf180mcu::draw_contact 0 0 \
+			${cont_surround} ${cont_surround} ${via_size} \
+			${layer} ${contact} ${toplayer} full
+	    popbox
+	    pushbox
+	    box move e ${hw}um
+	    box move s ${hl}um
+	    gf180mcu::draw_contact 0 0 \
+			${cont_surround} ${cont_surround} ${via_size} \
+			${layer} ${contact} ${toplayer} full
+	    popbox
+	    pushbox
+	    box move w ${hw}um
+	    box move s ${hl}um
+	    gf180mcu::draw_contact 0 0 \
+			${cont_surround} ${cont_surround} ${via_size} \
+			${layer} ${contact} ${toplayer} full
+	    popbox
+
+	    # Draw side contacts (except on poly)
+	    if {$i > 0} {
+		pushbox
+		box move w ${hw}um
+		gf180mcu::draw_contact 0 ${cl} \
+			${cont_surround} ${cont_surround} ${via_size} \
+			${layer} ${contact} ${toplayer} full
+		popbox
+		pushbox
+		box move e ${hw}um
+		gf180mcu::draw_contact 0 ${cl} \
+			${cont_surround} ${cont_surround} ${via_size} \
+			${layer} ${contact} ${toplayer} full
+		popbox
+		pushbox
+		box move n ${hl}um
+		gf180mcu::draw_contact ${cw} 0 \
+			${cont_surround} ${cont_surround} ${via_size} \
+			${layer} ${contact} ${toplayer} full
+		popbox
+		pushbox
+		box move s ${hl}um
+		gf180mcu::draw_contact ${cw} 0 \
+			${cont_surround} ${cont_surround} ${via_size} \
+			${layer} ${contact} ${toplayer} full
+		popbox
+	    }
+	} else {
+	    break
+	}
+    }
+
+    popbox
+    # Bounding box is the same as the device length and width
+    set cext [list -$hw -$hl $hw $hl]
+    return $cext
+}
+
+#----------------------------------------------------------------
+# Capacitor: Draw the tiled device
+#----------------------------------------------------------------
+
+proc gf180mcu::cap_draw {parameters} {
+    tech unlock *
+
+    # Set defaults if they are not in parameters
+    set coverlap 0	;# overlap capacitors at contacts
+    set guard 0		;# draw a guard ring
+    set sandwich 0	;# this is not a plate sandwich capacitor
+    set cap_spacing 0	;# abutted caps if spacing is zero
+    set wide_cap_spacing 0  ;# additional spacing for wide metal rule
+    set wide_cap_width 0
+    set end_spacing 0
+    set end_surround 0
+    set bot_surround 0
+    set top_metal_width 0
+    set bconnect 0	;# connect bottom plates in array
+    set tconnect 0	;# connect top plates in array
+    set top_type ""
+
+    # Set a local variable for each parameter (e.g., $l, $w, etc.)
+    foreach key [dict keys $parameters] {
+        set $key [dict get $parameters $key]
+    }
+
+    # Normalize distance units to microns
+    set w [magic::spice2float $w]
+    set l [magic::spice2float $l]
+
+    pushbox
+    box values 0 0 0 0
+
+    # Determine the base device dimensions by drawing one device
+    # while all layers are locked (nothing drawn).  This allows the
+    # base drawing routine to do complicated geometry without having
+    # to duplicate it here with calculations.
+
+    tech lock *
+    if {$sandwich == 1} {
+	set bbox [gf180mcu::sandwich_cap_device $parameters]
+    } else {
+	set bbox [gf180mcu::cap_device $parameters]
+    }
+    # puts stdout "Diagnostic: Device bounding box e $bbox (um)"
+    tech unlock *
+
+    set fw [- [lindex $bbox 2] [lindex $bbox 0]]
+    set fh [- [lindex $bbox 3] [lindex $bbox 1]]
+    set lw [+ [lindex $bbox 2] [lindex $bbox 0]]
+    set lh [+ [lindex $bbox 3] [lindex $bbox 1]]
+
+    set dwide 0
+    if {($fw >= $wide_cap_width) && ($fh >= $wide_cap_width)} {
+	set dwide $wide_cap_spacing
+    }
+
+    # Determine tile width and height (depends on overlap)
+    if {$coverlap == 0} {
+        set dy [+ $fh $cap_spacing $dwide]
+    } else {
+        # overlap at end contact
+        set dy [- $fh [+ $end_surround $end_surround $contact_size]]
+    }
+    # Contact is placed on right so spacing is determined by end_spacing.
+    set dx [+ $fw $end_spacing $dwide]
+
+    # Determine core width and height
+    set corex [+ [* [- $nx 1] $dx] $fw]
+    set corey [+ [* [- $ny 1] $dy] $fh]
+    set corellx [/ [+ [- $corex $fw] $lw] 2.0]
+    set corelly [/ [+ [- $corey $fh] $lh] 2.0]
+
+    if {$guard != 0} {
+	# Calculate guard ring size (measured to contact center)
+	set gx [+ $corex [* 2.0 [+ $cap_diff_spacing $diff_surround]] $contact_size]
+	set gy [+ $corey [* 2.0 [+ $end_spacing $diff_surround]] $contact_size]
+
+	# Draw the guard ring first.
+	gf180mcu::guard_ring $gx $gy $parameters
+    }
+
+    set top_metal_width [+ ${contact_size} ${end_surround} ${end_surround}]
+    set hmw [/ $top_metal_width 2.0]
+    set hdy [/ $dy 2.0]
+    set cdx [+ [/ ${w} 2.0] ${bot_surround} ${end_spacing}]
+
+    pushbox
+    box move w ${corellx}um
+    box move s ${corelly}um
+    for {set xp 0} {$xp < $nx} {incr xp} {
+	pushbox
+	for {set yp 0} {$yp < $ny} {incr yp} {
+	    if {$sandwich == 1} {
+		gf180mcu::sandwich_cap_device $parameters
+	    } else {
+		gf180mcu::cap_device $parameters
+	    }
+	    if {$ny > 1} {
+		pushbox
+		box grow e ${hmw}um
+		box grow w ${hmw}um
+		box grow n ${hdy}um
+		box grow s ${hdy}um
+		if {($top_type != "") && ($tconnect == 1)} {
+		    paint ${top_type}
+		}
+		if {($top_type != "") && ($bconnect == 1)} {
+		    box move e ${cdx}um
+		    paint ${top_type}
+		}
+		popbox
+	    }
+            box move n ${dy}um
+        }
+	popbox
+        box move e ${dx}um
+    }
+    popbox
+    popbox
+
+    tech revert
+}
+
+#----------------------------------------------------------------
+
+#ifdef MIM
+proc gf180mcu::mim_2p0fF_draw {parameters} {
+    set newdict [dict create \
+#ifdef METALS6
+	    top_type 		mtp \
+	    top_contact_type	viatp \
+	    bot_type 		m5 \
+#endif
+#ifdef METALS5
+	    top_type 		m5 \
+	    top_contact_type	via4 \
+	    bot_type 		m4 \
+#endif
+#ifdef METALS4
+	    top_type 		m4 \
+	    top_contact_type	via3 \
+	    bot_type 		m3 \
+#endif
+#ifdef METALS3
+	    top_type 		m3 \
+	    top_contact_type	via2 \
+	    bot_type 		m2 \
+#endif
+	    cap_type 		mimcap \
+	    cap_contact_type	mimcc \
+	    bot_surround	0.6 \
+	    cap_spacing		0.6 \
+	    cap_surround	0.4 \
+	    top_surround	0.0 \
+	    end_surround	0.31 \
+#ifdef THICKMET3P0
+	    metal_surround	0.11 \
+	    contact_size	1.80 \
+	    end_spacing		1.28 \
+#elseif (THICKMET1P1 || THICKMET0P9)
+	    metal_surround	0.05 \
+	    contact_size	0.44 \
+	    end_spacing		0.67 \
+#else
+	    metal_surround	0.05 \
+	    contact_size	0.36 \
+	    end_spacing		0.60 \
+#endif (!(THICKMET3P0 || THICKMET1P1 || THICKMET0P9))
+    ]
+    set drawdict [dict merge $gf180mcu::ruleset $newdict $parameters]
+    return [gf180mcu::cap_draw $drawdict]
+}
+#endif (MIM)
+
+#----------------------------------------------------------------
+# capacitor: Check device parameters for out-of-bounds values
+#----------------------------------------------------------------
+
+proc gf180mcu::cap_check {parameters} {
+    # In case wmax and/or lmax are undefined
+    set lmax 0
+    set wmax 0
+
+    # Set a local variable for each parameter (e.g., $l, $w, etc.)
+    foreach key [dict keys $parameters] {
+        set $key [dict get $parameters $key]
+    }
+
+    # Normalize distance units to microns
+    set l [magic::spice2float $l]
+    set l [magic::3digitpastdecimal $l] 
+    set w [magic::spice2float $w]
+    set w [magic::3digitpastdecimal $w] 
+
+    set val   [magic::spice2float $val]
+    set carea [magic::spice2float $carea]
+    set cperi [magic::spice2float $cperi]
+    set dc    [magic::spice2float $dc]
+
+    if {$square == 1} {
+        # Calculate L and W from value
+	set a $carea
+	set b [expr $cperi * 4]
+	set c [expr -4 * $dc - $val]
+	set l [expr ((-$b + sqrt($b * $b - (4 * $a * $c))) / (2 * $a))]
+	dict set parameters l [magic::float2spice $l]
+	set w $l
+	dict set parameters w [magic::float2spice $w]
+    } elseif {$l == 0} {
+        # Calculate L from W and value
+	set l [expr (($val + 4 * $dc - 2 * $w * $cperi) / ($w * $carea + 2 * $cperi))]
+	dict set parameters l [magic::float2spice $l]
+    } elseif {$w == 0} {
+        # Calculate W from L and value
+	set w [expr (($val + 4 * $dc - 2 * $l * $cperi) / ($l * $carea + 2 * $cperi))]
+	dict set parameters w [magic::float2spice $w]
+    }
+    if {$w < $wmin} {
+	puts stderr "Capacitor width must be >= $wmin"
+	dict set parameters w $wmin
+	set w $wmin
+    } 
+    if {$l < $lmin} {
+	puts stderr "Capacitor length must be >= $lmin"
+	dict set parameters l $lmin
+	set l $lmin
+    } 
+    if {($wmax > 0) && ($w > $wmax)} {
+	puts stderr "Capacitor width must be <= $wmax"
+	dict set parameters w $wmax
+	set w $wmax
+    } 
+    if {($lmax > 0) && ($l > $lmax)} {
+	puts stderr "Capacitor length must be <= $lmax"
+	dict set parameters l $lmax
+	set l $lmax
+    } 
+    # Calculate value from L and W
+    set cval [expr ($l * $w * $carea + 2 * ($l + $w) * $cperi - 4 * $dc)]
+    dict set parameters val [magic::float2spice $cval]
+    gf180mcu::compute_ctot $parameters
+
+    return $parameters
+}
+
+#ifdef MIM
+proc gf180mcu::mim_2p0fF_check {parameters} {
+    return [gf180mcu::cap_check $parameters]
+}
+#endif
+
+#----------------------------------------------------------------
+# Drawn resistors
+#----------------------------------------------------------------
+
+#----------------------------------------------------------------
+# Resistor defaults:
+#----------------------------------------------------------------
+# User editable values:
+#
+#  val   Resistor value in ohms
+#  w	 Width
+#  l	 Length
+#  t	 Number of turns
+#  m	 Number devices in Y
+#  nx	 Number devices in X
+#  snake Use snake geometry
+#  dummy Flag to mark addition of dummy resistor
+#
+# Non-user editable values:
+#
+#  wmin  Minimum allowed width
+#  lmin  Minimum allowed length
+#  rho	 Resistance in ohms per square
+#  dw    Delta width
+#  term  Resistance per terminal
+#  sterm Additional resistance per terminal for snake geometry
+#----------------------------------------------------------------
+
+#----------------------------------------------------------------
+# rnw: Specify all user-editable default values and those
+# needed by nwell_check
+#----------------------------------------------------------------
+
+proc gf180mcu::nwell_defaults {} {
+    return {w 2.000 l 10.00 m 1 nx 1 wmin 2.000 lmin 2.00 \
+	 	rho 1680 val 8400 dummy 0 dw 0.25 term 1.0 snake 0 \
+		glc 1 grc 1 gtc 0 gbc 0 roverlap 0 endcov 100 \
+		full_metal 1}
+}
+
+#----------------------------------------------------------------
+# rpp1: Specify all user-editable default values and those
+# needed by rp1_check
+#----------------------------------------------------------------
+
+proc gf180mcu::ppolyf_u_defaults {} {
+    return {w 0.80 l 1.00 m 1 nx 1 wmin 0.80 lmin 1.00 \
+		rho 315 val 394 dummy 0 dw 0.07 term 0.0 \
+		sterm 0.0 caplen 0.4 snake 0 \
+		glc 1 grc 1 gtc 0 gbc 0 roverlap 0 endcov 100 \
+		full_metal 1}
+}
+
+proc gf180mcu::npolyf_u_defaults {} {
+    return {w 0.80 l 1.00 m 1 nx 1 wmin 0.80 lmin 1.00 \
+		rho 300 val 375 dummy 0 dw 0.09 term 0.0 \
+		sterm 0.0 caplen 0.4 snake 0 \
+		glc 1 grc 1 gtc 0 gbc 0 roverlap 0 endcov 100 \
+		full_metal 1}
+}
+
+#----------------------------------------------------------------
+# rpp1s: Specify all user-editable default values and those
+# needed by rp1_check
+#----------------------------------------------------------------
+
+proc gf180mcu::ppolyf_s_defaults {} {
+    return {w 0.80 l 1.00 m 1 nx 1 wmin 0.80 lmin 1.00 \
+		rho 7 val 8.75 dummy 0 dw 0.01 term 0.0 \
+		sterm 0.0 caplen 0.4 snake 0 \
+		glc 1 grc 1 gtc 0 gbc 0 roverlap 0 endcov 100 \
+		full_metal 1}
+}
+
+proc gf180mcu::npolyf_s_defaults {} {
+    return {w 0.80 l 1.00 m 1 nx 1 wmin 0.80 lmin 1.00 \
+		rho 7 val 8.75 dummy 0 dw 0.01 term 0.0 \
+		sterm 0.0 caplen 0.4 snake 0 \
+		glc 1 grc 1 gtc 0 gbc 0 roverlap 0 endcov 100 \
+		full_metal 1}
+}
+
+#----------------------------------------------------------------
+# nplus_u: Specify all user-editable default values and those
+# needed by nplus_u_check 
+#----------------------------------------------------------------
+
+proc gf180mcu::nplus_u_defaults {} {
+    return {w 1.000 l 1.000 m 1 nx 1 wmin 1.00 lmin 1.00 \
+		rho 85 val 85.0 dummy 0 dw 0.05 term 0.0 \
+		sterm 0.0 caplen 0.4 snake 0 \
+		glc 1 grc 1 gtc 0 gbc 0 roverlap 0 endcov 100 \
+		full_metal 1}
+}
+
+#----------------------------------------------------------------
+# pplus_u: Specify all user-editable default values and those
+# needed by pplus_u_check
+#----------------------------------------------------------------
+
+proc gf180mcu::pplus_u_defaults {} {
+    return {w 1.000 l 1.000 m 1 nx 1 wmin 1.00 lmin 1.00 \
+		rho 128 val 128.0 dummy 0 dw 0.02 term 0.0 \
+		sterm 0.0 caplen 0.60 snake 0 \
+		glc 1 grc 1 gtc 0 gbc 0 roverlap 0 endcov 100 \
+		full_metal 1}
+}
+
+#----------------------------------------------------------------
+# rm1: Specify all user-editable default values and those needed
+# by rm1_check
+#----------------------------------------------------------------
+
+proc gf180mcu::rm1_defaults {} {
+    return {w 0.160 l 0.160 m 1 nx 1 wmin 0.16 lmin 0.16 \
+		rho 0.076 val 0.076 dummy 0 dw 0.0 term 0.0 \
+		roverlap 0}
+}
+
+#----------------------------------------------------------------
+# rm2: Specify all user-editable default values and those needed
+# by rm2_check
+#----------------------------------------------------------------
+
+proc gf180mcu::rm2_defaults {} {
+    return {w 0.200 l 0.200 m 1 nx 1 wmin 0.20 lmin 0.20 \
+		rho 0.053 val 0.053 dummy 0 dw 0.0 term 0.0 \
+		roverlap 0}
+}
+
+#----------------------------------------------------------------
+# Additional entries for rm3, rm4, rm5, and rmtp, depending on
+# the back-end metal stack.
+#----------------------------------------------------------------
+
+#ifdef METALS3 || METALS4 || METALS5 || METALS6
+proc gf180mcu::rm3_defaults {} {
+    return {w 0.200 l 0.200 m 1 nx 1 wmin 0.20 lmin 0.20 \
+		rho 0.053 val 0.053 dummy 0 dw 0.0 term 0.0 \
+		roverlap 0}
+}
+#endif (METALS3 || METALS4 || METALS5 || METALS6)
+
+#ifdef METALS4 || METALS5 || METALS6
+proc gf180mcu::rm4_defaults {} {
+    return {w 0.200 l 0.200 m 1 nx 1 wmin 0.20 lmin 0.20 \
+		rho 0.053 val 0.053 dummy 0 dw 0.0 term 0.0 \
+		roverlap 0}
+}
+#endif (METALS4 || METALS5 || METALS6)
+#ifdef METALS5 || METALS6
+proc gf180mcu::rm5_defaults {} {
+    return {w 0.200 l 0.200 m 1 nx 1 wmin 0.20 lmin 0.20 \
+		rho 0.053 val 0.053 dummy 0 dw 0.0 term 0.0 \
+		roverlap 0}
+}
+#endif (METALS5 || METALS6)
+#ifdef METALS6
+proc gf180mcu::rmtp_defaults {} {
+    return {w 0.200 l 0.200 m 1 nx 1 wmin 0.20 lmin 0.20 \
+		rho 0.053 val 0.053 dummy 0 dw 0.0 term 0.0 \
+		roverlap 0}
+}
+#endif (METALS6)
+
+#ifdef HRPOLY1K
+
+#----------------------------------------------------------------
+# ppolyf_u_1k: Specify all user-editable default values and those
+# needed by npolyf_u_check
+#----------------------------------------------------------------
+
+proc gf180mcu::ppolyf_u_1k_defaults {} {
+    return {w 1.000 l 2.000 m 1 nx 1 wmin 1.000 lmin 1.000 \
+		rho 1000 val 2000 dummy 0 dw 0.0 term 0.0 \
+		sterm 0.0 caplen 0.4 snake 0 \
+		glc 1 grc 1 gtc 0 gbc 0 roverlap 0 endcov 100 \
+		full_metal 1 \
+		compatible {ppolyf_u_1k ppolyf_u_1k_6p0}}
+}
+
+proc gf180mcu::ppolyf_u_1k_6p0_defaults {} {
+    return {w 1.000 l 2.000 m 1 nx 1 wmin 1.000 lmin 1.000 \
+		rho 1000 val 2000 dummy 0 dw 0.0 term 0.0 \
+		sterm 0.0 caplen 0.4 snake 0 \
+		glc 1 grc 1 gtc 0 gbc 0 roverlap 0 endcov 100 \
+		full_metal 1 \
+		compatible {ppolyf_u_1k ppolyf_u_1k_6p0}}
+}
+#endif (HRPOLY1K)
+ 
+#----------------------------------------------------------------
+# resistor: Conversion from SPICE netlist parameters to toolkit
+#----------------------------------------------------------------
+
+proc gf180mcu::res_convert {parameters} {
+    set pdkparams [dict create]
+    dict for {key value} $parameters {
+	set canonkey $key
+	switch -nocase $key {
+	    r_length -
+	    r_width -
+	    l -
+	    w {
+		switch -nocase $key {
+		    r_length {
+			set canonkey l
+		    }
+		    r_width {
+			set canonkey w
+		    }
+		}
+		# Length and width are converted to units of microns
+		set value [magic::spice2float $value]
+		set value [expr $value * 1e6]
+		set value [magic::3digitpastdecimal $value]
+		dict set pdkparams [string tolower $canonkey] $value
+	    }
+	}
+    }
+    return $pdkparams
+}
+
+#----------------------------------------------------------------
+
+proc gf180mcu::nwell_convert {parameters} {
+    return [gf180mcu::res_convert $parameters]
+}
+
+proc gf180mcu::ppolyf_u_convert {parameters} {
+    return [gf180mcu::res_convert $parameters]
+}
+
+proc gf180mcu::ppolyf_s_convert {parameters} {
+    return [gf180mcu::res_convert $parameters]
+}
+
+proc gf180mcu::npolyf_s_convert {parameters} {
+    return [gf180mcu::res_convert $parameters]
+}
+
+proc gf180mcu::npolyf_u_convert {parameters} {
+    return [gf180mcu::res_convert $parameters]
+}
+
+proc gf180mcu::nplus_u_convert {parameters} {
+    return [gf180mcu::res_convert $parameters]
+}
+
+proc gf180mcu::pplus_u_convert {parameters} {
+    return [gf180mcu::res_convert $parameters]
+}
+
+proc gf180mcu::rm1_convert {parameters} {
+    return [gf180mcu::res_convert $parameters]
+}
+
+proc gf180mcu::rm2_convert {parameters} {
+    return [gf180mcu::res_convert $parameters]
+}
+
+#ifdef METALS3 || METALS4 || METALS5 || METALS6
+proc gf180mcu::rm3_convert {parameters} {
+    return [gf180mcu::res_convert $parameters]
+}
+#endif (METALS3 || METALS4 || METALS5 || METALS6)
+
+#ifdef METALS4 || METALS5 || METALS6
+proc gf180mcu::rm4_convert {parameters} {
+    return [gf180mcu::res_convert $parameters]
+}
+#endif (METALS4 || METALS5 || METALS6)
+#ifdef METALS5 || METALS6
+proc gf180mcu::rm5_convert {parameters} {
+    return [gf180mcu::res_convert $parameters]
+}
+#endif (METALS5 || METALS6)
+#ifdef METALS6
+proc gf180mcu::rmtp_convert {parameters} {
+    return [gf180mcu::res_convert $parameters]
+}
+#endif (METALS6)
+
+#ifdef HRPOLY1K
+proc gf180mcu::ppolyf_u_1k_convert {parameters} {
+    return [gf180mcu::res_convert $parameters]
+}
+
+proc gf180mcu::ppolyf_u_1k_6p0_convert {parameters} {
+    return [gf180mcu::res_convert $parameters]
+}
+#endif (HRPOLY1K)
+
+#----------------------------------------------------------------
+# resistor: Interactively specifies the fixed layout parameters
+#----------------------------------------------------------------
+
+proc gf180mcu::res_dialog {device parameters} {
+    # Editable fields:      w, l, t, nx, m, val
+    # Checked fields:  
+
+    magic::add_entry val "Value (ohms)" $parameters
+    if {[dict exists $parameters snake]} {
+	gf180mcu::compute_ltot $parameters
+	magic::add_message ltot "Total length (um)" $parameters
+    }
+    magic::add_entry l "Length (um)" $parameters
+    magic::add_entry w "Width (um)" $parameters
+    magic::add_entry nx "X Repeat" $parameters
+    magic::add_entry m "Y Repeat" $parameters
+    if {[dict exists $parameters endcov]} {
+	magic::add_entry endcov "End contact coverage (%)" $parameters
+    }
+
+    if {[dict exists $parameters compatible]} {
+       set sellist [dict get $parameters compatible]
+       # Reserved word "gencell" has special behavior to change the
+       # underlying device type 
+       dict set parameters gencell $device
+       magic::add_selectlist gencell "Device type" $sellist $parameters
+    }
+
+    # magic::add_checkbox dummy "Add dummy" $parameters
+
+    if {[dict exists $parameters snake]} {
+	magic::add_checkbox snake "Use snake geometry" $parameters
+    }
+    if {[dict exists $parameters roverlap]} {
+	if {[dict exists $parameters endcov]} {
+            magic::add_checkbox roverlap "Overlap at end contact" $parameters
+	} else {
+            magic::add_checkbox roverlap "Overlap at ends" $parameters
+	}
+    }
+	magic::add_checkbox full_metal "Full metal guard ring" $parameters
+    if {[dict exists $parameters glc]} {
+	magic::add_checkbox glc "Add left guard ring contact" $parameters
+    }
+    if {[dict exists $parameters grc]} {
+	magic::add_checkbox grc "Add right guard ring contact" $parameters
+    }
+    if {[dict exists $parameters gtc]} {
+	magic::add_checkbox gtc "Add top guard ring contact" $parameters
+    }
+    if {[dict exists $parameters gbc]} {
+	magic::add_checkbox gbc "Add bottom guard ring contact" $parameters
+    }
+
+    if {[dict exists $parameters snake]} {
+       magic::add_dependency gf180mcu::res_recalc $device gf180mcu l w val nx snake
+    } else {
+       magic::add_dependency gf180mcu::res_recalc $device gf180mcu l w val nx
+    }
+}
+
+#----------------------------------------------------------------
+
+proc gf180mcu::nwell_dialog {parameters} {
+    gf180mcu::res_dialog nwell $parameters
+}
+
+proc gf180mcu::ppolyf_u_dialog {parameters} {
+    gf180mcu::res_dialog ppolyf_u $parameters
+}
+
+proc gf180mcu::npolyf_u_dialog {parameters} {
+    gf180mcu::res_dialog npolyf_u $parameters
+}
+
+proc gf180mcu::ppolyf_s_dialog {parameters} {
+    gf180mcu::res_dialog ppolyf_s $parameters
+}
+
+proc gf180mcu::npolyf_s_dialog {parameters} {
+    gf180mcu::res_dialog npolyf_s $parameters
+}
+
+proc gf180mcu::nplus_u_dialog {parameters} {
+    gf180mcu::res_dialog nplus_u $parameters
+}
+
+proc gf180mcu::pplus_u_dialog {parameters} {
+    gf180mcu::res_dialog pplus_u $parameters
+}
+
+proc gf180mcu::nplus_u_3p3_dialog {parameters} {
+    gf180mcu::res_dialog nplus_u_3p3 $parameters
+}
+
+proc gf180mcu::pplus_u_3p3_dialog {parameters} {
+    gf180mcu::res_dialog pplus_u_3p3 $parameters
+}
+
+proc gf180mcu::rm1_dialog {parameters} {
+    gf180mcu::res_dialog rm1 $parameters
+}
+
+proc gf180mcu::rm2_dialog {parameters} {
+    gf180mcu::res_dialog rm2 $parameters
+}
+
+#ifdef METALS3 || METALS4 || METALS5 || METALS6
+proc gf180mcu::rm3_dialog {parameters} {
+    gf180mcu::res_dialog rm3 $parameters
+}
+#endif (METALS3 || METALS4 || METALS5 || METALS6)
+
+#ifdef METALS4 || METALS5 || METALS6
+proc gf180mcu::rm4_dialog {parameters} {
+    gf180mcu::res_dialog rm4 $parameters
+}
+#endif (METALS4 || METALS5 || METALS6)
+#ifdef METALS5 || METALS6
+proc gf180mcu::rm5_dialog {parameters} {
+    gf180mcu::res_dialog rm5 $parameters
+}
+#endif (METALS5 || METALS6)
+#ifdef METALS6
+proc gf180mcu::rmtp_dialog {parameters} {
+    gf180mcu::res_dialog rmtp $parameters
+}
+#endif (METALS6)
+
+#ifdef HRPOLY1K
+proc gf180mcu::ppolyf_u_1k_dialog {parameters} {
+    gf180mcu::res_dialog ppolyf_u_1k $parameters
+}
+
+proc gf180mcu::ppolyf_u_1k_6p0_dialog {parameters} {
+    gf180mcu::res_dialog ppolyf_u_1k_6p0 $parameters
+}
+#endif (HRPOLY1K)
+
+#----------------------------------------------------------------
+# Resistor: Draw a single device in straight geometry
+#----------------------------------------------------------------
+
+proc gf180mcu::res_device {parameters} {
+    # Epsilon for avoiding round-off errors
+    set eps  0.0005
+
+    # Set local default values if they are not in parameters
+    set endcov 0	 	;# percent coverage of end contacts
+    set well_res_overlap 0 	;# not a well resistor
+    set end_contact_type ""	;# no contacts for metal resistors
+
+    # Set a local variable for each parameter (e.g., $l, $w, etc.)
+    foreach key [dict keys $parameters] {
+        set $key [dict get $parameters $key]
+    }
+
+    # Draw the resistor and endcaps
+    pushbox
+    box size 0 0
+    pushbox
+    set hw [/ $w 2.0]
+    set hl [/ $l 2.0]
+    box grow n ${hl}um
+    box grow s ${hl}um
+    box grow e ${hw}um
+    box grow w ${hw}um
+
+    pushbox
+    box grow n ${res_to_endcont}um
+    box grow s ${res_to_endcont}um
+    if {$well_res_overlap > 0} {
+	set well_extend [+ ${well_res_overlap} [/ ${contact_size} 2.0] ${end_surround}]
+	box grow n ${well_extend}um
+	box grow s ${well_extend}um
+	paint ${well_res_type}
+    } else {
+	paint ${end_type}
+    }
+    set cext [gf180mcu::getbox]
+    popbox
+
+    if {$well_res_overlap > 0} {
+	erase ${well_res_type}
+    } else {
+	erase ${end_type}
+    }
+    paint ${res_type}
+    popbox
+
+    # Reduce contact sizes by (end type) surround so that
+    # the contact area edges match the device type width.
+    # (Minimum dimensions will be enforced by the contact drawing routine)
+    set epl [- ${w} [* ${end_surround} 2]]     	    ;# end contact width
+
+    # Reduce end material size for well resistor types
+    if {$well_res_overlap > 0} {
+	set epl [- ${epl} [* ${well_res_overlap} 2]]
+    }
+
+    # Reduce by coverage percentage unless overlapping at contacts
+    if {(${roverlap} == 0) && (${endcov} > 0)} {
+	set cpl [* ${epl} [/ ${endcov} 100.0]]
+    } else {
+	set cpl $epl
+    }
+
+    set hepl [+ [/ ${epl} 2.0] ${end_surround}]
+    set hesz [+ [/ ${contact_size} 2.0] ${end_surround}]
+
+    # Top end material & contact
+    pushbox
+    box move n ${hl}um
+    box move n ${res_to_endcont}um
+
+    pushbox
+    box size 0 0
+    box grow n ${hesz}um
+    box grow s ${hesz}um
+    box grow e ${hepl}um
+    box grow w ${hepl}um
+    paint ${end_type}
+    set cext [gf180mcu::unionbox $cext [gf180mcu::getbox]]
+    popbox
+
+    if {${end_contact_type} != ""} {
+	set cext [gf180mcu::unionbox $cext [gf180mcu::draw_contact ${cpl} 0 \
+		${end_surround} ${metal_surround} ${contact_size} \
+		${end_type} ${end_contact_type} m1 horz]]
+    }
+    popbox
+
+    # Bottom end material & contact
+    pushbox
+    box move s ${hl}um
+    box move s ${res_to_endcont}um
+
+    pushbox
+    box size 0 0
+    box grow n ${hesz}um
+    box grow s ${hesz}um
+    box grow e ${hepl}um
+    box grow w ${hepl}um
+    paint ${end_type}
+    set cext [gf180mcu::unionbox $cext [gf180mcu::getbox]]
+    popbox
+
+    if {${end_contact_type} != ""} {
+	set cext [gf180mcu::unionbox $cext [gf180mcu::draw_contact ${cpl} 0 \
+		${end_surround} ${metal_surround} ${contact_size} \
+		${end_type} ${end_contact_type} m1 horz]]
+    }
+    popbox
+
+    popbox
+    return $cext
+}
+
+#----------------------------------------------------------------
+# Resistor: Draw a single device in snake geometry
+#----------------------------------------------------------------
+
+proc gf180mcu::res_snake_device {nf parameters} {
+    # nf is the number of fingers of the snake geometry
+
+    # Epsilon for avoiding round-off errors
+    set eps  0.0005
+
+    # Set local default values if they are not in parameters
+    set endcov 100	 	;# percent coverage of end contacts
+    set well_res_overlap 0 	;# not a well resistor
+    set end_contact_type ""	;# no contacts for metal resistors
+    set mask_clearance 0	;# additional length to clear mask
+
+    # Set a local variable for each parameter (e.g., $l, $w, etc.)
+    foreach key [dict keys $parameters] {
+        set $key [dict get $parameters $key]
+    }
+
+    # Compute half width and length
+    set hw [/ $w 2.0]
+    set hl [/ $l 2.0]
+
+    # Reduce contact sizes by (end type) surround so that
+    # the contact area edges match the device type width.
+    # (Minimum dimensions will be enforced by the contact drawing routine)
+    set epl [- ${w} [* ${end_surround} 2]]     	    ;# end contact width
+
+    # Reduce contact size for well resistor types
+    if {$well_res_overlap > 0} {
+	set epl [- ${epl} [* ${well_res_overlap} 2]]
+    }
+
+    # Reduce contact part of end by coverage percentage
+    if {${endcov} > 0} {
+	set cpl [* ${epl} [/ ${endcov} 100.0]]
+    } else {
+	set cpl $epl
+    }
+
+    set hepl [+ [/ ${epl} 2.0] ${end_surround}]
+    set hesz [+ [/ ${contact_size} 2.0] ${end_surround}]
+
+    pushbox
+    box size 0 0	;# Position is taken from caller
+
+    # Front end contact (always bottom)
+    pushbox
+    box move s ${hl}um
+    pushbox
+    box move s ${mask_clearance}um
+    box move s ${res_to_endcont}um
+
+    pushbox
+    box size 0 0
+    box grow n ${hesz}um
+    box grow s ${hesz}um
+    box grow e ${hepl}um
+    box grow w ${hepl}um
+    paint ${end_type}
+    set cext [gf180mcu::getbox]
+    popbox
+
+    if {${end_contact_type} != ""} {
+	set cext [gf180mcu::draw_contact ${cpl} 0 \
+		${end_surround} ${metal_surround} ${contact_size} \
+		${end_type} ${end_contact_type} m1 horz]
+    }
+    popbox
+
+    # Draw portion between resistor end and contact.
+    box grow e ${hw}um
+    box grow w ${hw}um
+    pushbox
+    box grow s ${mask_clearance}um
+    paint ${res_type}
+    popbox
+    box move s ${mask_clearance}um
+    box grow s ${res_to_endcont}um
+    if {$well_res_overlap > 0} {
+	set well_extend [+ ${well_res_overlap} [/ ${contact_size} 2.0] ${end_surround}]
+	box grow s ${well_extend}um
+	paint ${well_res_type}
+    } else {
+	paint ${end_type}
+    }
+    set cext [gf180mcu::unionbox $cext [gf180mcu::getbox]]
+    popbox
+
+    # Draw the resistor and endcaps
+    pushbox
+    box grow n ${hl}um
+    box grow s ${hl}um
+    box grow e ${hw}um
+    box grow w ${hw}um
+
+    # Capture these extents in the bounding box in case both contacts
+    # are on one side.
+    set cext [gf180mcu::unionbox $cext [gf180mcu::getbox]]
+
+    set deltax [+ ${res_spacing} ${w}]
+    set deltay [- ${l} ${w}]
+    for {set i 0} {$i < [- $nf 1]} {incr i} {
+	paint ${res_type}
+ 	pushbox
+	if {[% $i 2] == 0} {
+	    box move n ${deltay}um
+	}
+	box height ${w}um
+	box width ${deltax}um
+	paint ${res_type}
+ 	popbox
+	box move e ${deltax}um
+    }
+    paint ${res_type}
+    # Capture these extents in the bounding box
+    set cext [gf180mcu::unionbox $cext [gf180mcu::getbox]]
+    popbox
+
+    # Move box to last finger
+    set lastf [* [- $nf 1] $deltax]
+    box move e ${lastf}um
+
+    # Back-end contact (top or bottom, depending if odd or even turns)
+    pushbox
+
+    if {[% $nf 2] == 1} {
+	set dir n
+    } else {
+	set dir s
+    }
+    box move $dir ${hl}um
+    pushbox
+    box move $dir ${mask_clearance}um
+    box move $dir ${res_to_endcont}um
+
+    pushbox
+    box size 0 0
+    box grow n ${hesz}um
+    box grow s ${hesz}um
+    box grow e ${hepl}um
+    box grow w ${hepl}um
+    paint ${end_type}
+    set cext [gf180mcu::unionbox $cext [gf180mcu::getbox]]
+    popbox
+
+    if {${end_contact_type} != ""} {
+	set cext [gf180mcu::unionbox $cext [gf180mcu::draw_contact ${cpl} 0 \
+		${end_surround} ${metal_surround} ${contact_size} \
+		${end_type} ${end_contact_type} m1 horz]]
+    }
+    popbox
+    # Draw portion between resistor end and contact.
+    box grow e ${hw}um
+    box grow w ${hw}um
+    pushbox
+    box grow $dir ${mask_clearance}um
+    paint ${res_type}
+    popbox
+    box move $dir ${mask_clearance}um
+    box grow $dir ${res_to_endcont}um
+
+    if {$well_res_overlap > 0} {
+	set well_extend [+ ${well_res_overlap} [/ ${contact_size} 2.0] ${end_surround}]
+	box grow $dir ${well_extend}um
+	paint ${well_res_type}
+    } else {
+	paint ${end_type}
+    }
+    popbox
+
+    popbox
+    return $cext
+}
+
+#----------------------------------------------------------------
+# Resistor: Draw the tiled device
+#----------------------------------------------------------------
+
+proc gf180mcu::res_draw {parameters} {
+    tech unlock *
+
+    # Set defaults if they are not in parameters
+    set snake 0		;# some resistors don't allow snake geometry
+    set roverlap 0	;# overlap resistors at contacts
+    set guard 1		;# draw a guard ring
+    set overlap_compress 0	;# special Y distance compression
+    set well_res_overlap 0	;# additional well extension behind contact
+
+    # Set a local variable for each parameter (e.g., $l, $w, etc.)
+    foreach key [dict keys $parameters] {
+        set $key [dict get $parameters $key]
+    }
+
+    # For devices where inter-device space is smaller than device-to-guard ring
+    if {![dict exists $parameters end_to_end_space]} {
+	set end_to_end_space $end_spacing
+    }
+
+    # Normalize distance units to microns
+    set w [magic::spice2float $w]
+    set l [magic::spice2float $l]
+
+    pushbox
+    box values 0 0 0 0
+
+    # Determine the base device dimensions by drawing one device
+    # while all layers are locked (nothing drawn).  This allows the
+    # base drawing routine to do complicated geometry without having
+    # to duplicate it here with calculations.
+
+    tech lock *
+    set nf $nx
+    if {($snake == 1) && ($nx == 1)} {set snake 0}
+    if {$snake == 1} {
+	set bbox [gf180mcu::res_snake_device $nf $parameters]
+	set nx 1
+    } else {
+	set bbox [gf180mcu::res_device $parameters]
+    }
+    # puts stdout "Diagnostic: Device bounding box e $bbox (um)"
+    tech unlock *
+
+    set fw [- [lindex $bbox 2] [lindex $bbox 0]]
+    set fh [- [lindex $bbox 3] [lindex $bbox 1]]
+    set lw [+ [lindex $bbox 2] [lindex $bbox 0]]
+    set lh [+ [lindex $bbox 3] [lindex $bbox 1]]
+
+    # Determine tile width and height (depends on overlap)
+    # Snake resistors cannot overlap.
+    # However, snake resistors with an odd number of fingers can
+    # compress the space if overlap_compress is defined
+
+    if {($roverlap == 1) && ($snake == 1) && ([% $nf 2] == 1) && ($m > 1)} {
+        set dy [- $fh $overlap_compress]
+    } elseif {($roverlap == 0) || ($snake == 1)} {
+        set dy [+ $fh $end_to_end_space]
+    } else {
+        # overlap poly
+        set dy [- $fh [+ [* [+ $end_surround $well_res_overlap] 2.0] $contact_size]]
+    }
+    set dx [+ $fw $res_spacing]
+
+    # Determine core width and height
+    set corex [+ [* [- $nx 1] $dx] $fw]
+    set corey [+ [* [- $m 1] $dy] $fh]
+    set corellx [/ [+ [- $corex $fw] $lw] 2.0]
+    set corelly [/ [+ [- $corey $fh] $lh] 2.0]
+
+    if {$guard != 0} {
+	# Calculate guard ring size (measured to contact center)
+	set gx [+ $corex [* 2.0 [+ $res_diff_spacing $diff_surround]] $contact_size]
+	set gy [+ $corey [* 2.0 [+ $end_spacing $diff_surround]] $contact_size]
+
+	# Draw the guard ring first, because well resistors are on the substrate plane
+	gf180mcu::guard_ring $gx $gy $parameters
+    }
+
+    pushbox
+    box move w ${corellx}um
+    box move s ${corelly}um
+    # puts "Device position at = [gf180mcu::getbox]"
+    for {set xp 0} {$xp < $nx} {incr xp} {
+	pushbox
+	for {set yp 0} {$yp < $m} {incr yp} {
+	    if {$snake == 1} {
+		gf180mcu::res_snake_device $nf $parameters
+	    } else {
+		gf180mcu::res_device $parameters
+	    }
+            box move n ${dy}um
+        }
+	popbox
+        box move e ${dx}um
+    }
+    popbox
+    popbox
+
+    tech revert
+}
+
+#----------------------------------------------------------------
+
+proc gf180mcu::ppolyf_u_draw {parameters} {
+
+    # Set a local variable for each rule in ruleset
+    foreach key [dict keys $gf180mcu::ruleset] {
+        set $key [dict get $gf180mcu::ruleset $key]
+    }
+
+    set newdict [dict create \
+	    res_type		rpp \
+	    end_type 		poly \
+	    end_contact_type	pc \
+	    plus_diff_type	nsd \
+	    plus_contact_type	nsc \
+	    sub_type		nwell \
+	    end_surround	$poly_surround \
+	    end_spacing		0.44 \
+	    end_to_end_space	0.52 \
+	    res_to_endcont	$sblk_to_cont \
+	    res_spacing		$polyres_spacing \
+	    res_diff_spacing	0.44 \
+	    mask_clearance	0.52 \
+	    overlap_compress	0.36 \
+    ]
+    set drawdict [dict merge $gf180mcu::ruleset $newdict $parameters]
+    return [gf180mcu::res_draw $drawdict]
+}
+
+#----------------------------------------------------------------
+
+proc gf180mcu::npolyf_u_draw {parameters} {
+
+    # Set a local variable for each rule in ruleset
+    foreach key [dict keys $gf180mcu::ruleset] {
+        set $key [dict get $gf180mcu::ruleset $key]
+    }
+
+    set newdict [dict create \
+	    res_type		rnp \
+	    end_type 		poly \
+	    end_contact_type	pc \
+	    plus_diff_type	psd \
+	    plus_contact_type	psc \
+	    sub_type		pwell \
+	    end_surround	$poly_surround \
+	    end_spacing		0.44 \
+	    end_to_end_space	0.52 \
+	    res_to_endcont	$sblk_to_cont \
+	    res_spacing		$polyres_spacing \
+	    res_diff_spacing	0.44 \
+	    mask_clearance	0.52 \
+	    overlap_compress	0.36 \
+    ]
+    set drawdict [dict merge $gf180mcu::ruleset $newdict $parameters]
+    return [gf180mcu::res_draw $drawdict]
+}
+
+#----------------------------------------------------------------
+
+proc gf180mcu::ppolyf_s_draw {parameters} {
+
+    # Set a local variable for each rule in ruleset
+    foreach key [dict keys $gf180mcu::ruleset] {
+        set $key [dict get $gf180mcu::ruleset $key]
+    }
+
+    # Distance from resistor to end contact is different between straight
+    # and snake geometry.
+
+    set res_to_endcont [+ $poly_surround [/ $contact_size 2.0]]
+    if {[dict exists $parameters snake]} {
+	if {[dict get $parameters snake] == 1} {
+	    set res_to_endcont [+ $res_to_endcont $poly_spacing]
+	}
+    }
+
+    set newdict [dict create \
+	    res_type		rpps \
+	    end_type 		poly \
+	    end_contact_type	pc \
+	    plus_diff_type	nsd \
+	    plus_contact_type	nsc \
+	    sub_type		nwell \
+	    end_surround	$poly_surround \
+	    end_spacing		0.28 \
+	    end_to_end_space	0.41 \
+	    res_to_endcont	$res_to_endcont \
+	    res_spacing		$polyres_spacing \
+	    res_diff_spacing	0.41 \
+    ]
+    set drawdict [dict merge $gf180mcu::ruleset $newdict $parameters]
+    return [gf180mcu::res_draw $drawdict]
+}
+
+#----------------------------------------------------------------
+
+proc gf180mcu::npolyf_s_draw {parameters} {
+
+    # Set a local variable for each rule in ruleset
+    foreach key [dict keys $gf180mcu::ruleset] {
+        set $key [dict get $gf180mcu::ruleset $key]
+    }
+
+    # Distance from resistor to end contact is different between straight
+    # and snake geometry.
+
+    set res_to_endcont [+ $poly_surround [/ $contact_size 2.0]]
+    if {[dict exists $parameters snake]} {
+	if {[dict get $parameters snake] == 1} {
+	    set res_to_endcont [+ $res_to_endcont $poly_spacing]
+	}
+    }
+
+    set newdict [dict create \
+	    res_type		rnps \
+	    end_type 		poly \
+	    end_contact_type	pc \
+	    plus_diff_type	nsd \
+	    plus_contact_type	nsc \
+	    sub_type		nwell \
+	    end_surround	$poly_surround \
+	    end_spacing		0.28 \
+	    end_to_end_space	0.41 \
+	    res_to_endcont	$res_to_endcont \
+	    res_spacing		$polyres_spacing \
+	    res_diff_spacing	0.28 \
+    ]
+    set drawdict [dict merge $gf180mcu::ruleset $newdict $parameters]
+    return [gf180mcu::res_draw $drawdict]
+}
+
+#----------------------------------------------------------------
+
+proc gf180mcu::nplus_u_draw {parameters} {
+
+    # Set a local variable for each rule in ruleset
+    foreach key [dict keys $gf180mcu::ruleset] {
+        set $key [dict get $gf180mcu::ruleset $key]
+    }
+
+    set newdict [dict create \
+	    res_type		rnd \
+	    end_type 		ndiff \
+	    end_contact_type	ndc \
+	    plus_diff_type	psd \
+	    plus_contact_type	psc \
+	    sub_type		pwell \
+	    end_surround	$diff_surround \
+	    end_spacing		0.45 \
+	    res_to_endcont	0.45 \
+	    res_spacing		$diffres_spacing \
+	    res_diff_spacing	0.45 \
+	    mask_clearance	0.22 \
+	    overlap_compress	0.36 \
+    ]
+    set drawdict [dict merge $gf180mcu::ruleset $newdict $parameters]
+    return [gf180mcu::res_draw $drawdict]
+}
+
+#----------------------------------------------------------------
+
+proc gf180mcu::pplus_u_draw {parameters} {
+
+    # Set a local variable for each rule in ruleset
+    foreach key [dict keys $gf180mcu::ruleset] {
+        set $key [dict get $gf180mcu::ruleset $key]
+    }
+
+    set newdict [dict create \
+	    res_type		rpd \
+	    end_type 		pdiff \
+	    end_contact_type	pdc \
+	    plus_diff_type	nsd \
+	    plus_contact_type	nsc \
+	    sub_type		nwell \
+	    end_surround	$diff_surround \
+	    end_spacing		0.45 \
+	    res_to_endcont	0.45 \
+	    res_spacing		$diffres_spacing \
+	    res_diff_spacing	0.45 \
+	    mask_clearance	0.22 \
+	    overlap_compress	0.36 \
+    ]
+    set drawdict [dict merge $gf180mcu::ruleset $newdict $parameters]
+    return [gf180mcu::res_draw $drawdict]
+}
+
+#----------------------------------------------------------------
+
+proc gf180mcu::nwell_draw {parameters} {
+
+    # Set a local variable for each rule in ruleset
+    foreach key [dict keys $gf180mcu::ruleset] {
+        set $key [dict get $gf180mcu::ruleset $key]
+    }
+
+    set newdict [dict create \
+	    well_res_type	nwell \
+	    res_type		rnw \
+	    end_type 		nsd \
+	    end_contact_type	nsc \
+	    plus_diff_type	psd \
+	    plus_contact_type	psc \
+	    sub_type		pwell \
+	    end_surround	$diff_surround \
+	    end_spacing		1.2 \
+	    overlap_compress	-0.84 \
+	    res_to_endcont	0.22 \
+	    res_spacing		1.2 \
+	    res_diff_spacing	0.28 \
+	    well_res_overlap	0.24 \
+    ]
+    set drawdict [dict merge $gf180mcu::ruleset $newdict $parameters]
+    return [gf180mcu::res_draw $drawdict]
+}
+
+#----------------------------------------------------------------
+
+#ifdef HRPOLY1K
+proc gf180mcu::ppolyf_u_1k_draw {parameters} {
+    # Set a local variable for each rule in ruleset
+    foreach key [dict keys $gf180mcu::ruleset] {
+        set $key [dict get $gf180mcu::ruleset $key]
+    }
+
+    set newdict [dict create \
+	    res_type		hires \
+	    end_type 		poly \
+	    end_contact_type	pc \
+	    plus_diff_type	psd \
+	    plus_contact_type	psc \
+	    sub_type		pwell \
+	    end_surround	$poly_surround \
+	    end_spacing		0.7 \
+	    res_to_endcont	0.43 \
+	    res_spacing		$polyres_spacing \
+	    res_diff_spacing	0.7 \
+	    mask_clearance	0.22 \
+	    overlap_compress	0.36 \
+    ]
+    set drawdict [dict merge $gf180mcu::ruleset $newdict $parameters]
+    return [gf180mcu::res_draw $drawdict]
+}
+
+proc gf180mcu::ppolyf_u_1k_6p0_draw {parameters} {
+    # Set a local variable for each rule in ruleset
+    foreach key [dict keys $gf180mcu::ruleset] {
+        set $key [dict get $gf180mcu::ruleset $key]
+    }
+
+    set newdict [dict create \
+	    diff_poly_space	0.30 \
+	    diff_gate_space	0.30 \
+	    diff_spacing	0.36 \
+	    res_type		mvhires \
+	    end_type 		poly \
+	    end_contact_type	pc \
+	    plus_diff_type	mvpsd \
+	    plus_contact_type	mvpsc \
+	    sub_type		pwell \
+	    sub_surround	0.16 \
+	    end_surround	$poly_surround \
+	    end_spacing		0.7 \
+	    res_to_endcont	0.43 \
+	    res_spacing		$polyres_spacing \
+	    res_diff_spacing	0.7 \
+	    mask_clearance	0.22 \
+	    overlap_compress	0.36 \
+    ]
+    set drawdict [dict merge $gf180mcu::ruleset $newdict $parameters]
+    return [gf180mcu::res_draw $drawdict]
+}
+#endif (HRPOLY1K)
+
+#----------------------------------------------------------------
+
+proc gf180mcu::rm1_draw {parameters} {
+
+    # Set a local variable for each rule in ruleset
+    foreach key [dict keys $gf180mcu::ruleset] {
+        set $key [dict get $gf180mcu::ruleset $key]
+    }
+
+    set newdict [dict create \
+	    guard		0 \
+	    res_type		rm1 \
+	    end_type 		m1 \
+	    end_surround	0.0 \
+	    end_spacing		0.0 \
+	    res_to_endcont	0.2 \
+	    res_spacing		$metal_spacing \
+    ]
+    set drawdict [dict merge $gf180mcu::ruleset $newdict $parameters]
+    return [gf180mcu::res_draw $drawdict]
+}
+
+#----------------------------------------------------------------
+
+proc gf180mcu::rm2_draw {parameters} {
+
+    # Set a local variable for each rule in ruleset
+    foreach key [dict keys $gf180mcu::ruleset] {
+        set $key [dict get $gf180mcu::ruleset $key]
+    }
+
+    set newdict [dict create \
+	    guard		0 \
+	    res_type		rm2 \
+	    end_type 		m2 \
+	    end_surround	0.0 \
+	    end_spacing		0.0 \
+	    res_to_endcont	0.2 \
+	    res_spacing		$mmetal_spacing \
+    ]
+    set drawdict [dict merge $gf180mcu::ruleset $newdict $parameters]
+    return [gf180mcu::res_draw $drawdict]
+}
+
+#----------------------------------------------------------------
+
+#ifdef METALS3 || METALS4 || METALS5 || METALS6
+proc gf180mcu::rm3_draw {parameters} {
+
+    # Set a local variable for each rule in ruleset
+    foreach key [dict keys $gf180mcu::ruleset] {
+        set $key [dict get $gf180mcu::ruleset $key]
+    }
+
+    set newdict [dict create \
+	    guard		0 \
+	    res_type		rm3 \
+	    end_type 		m3 \
+	    end_surround	0.0 \
+	    end_spacing		0.0 \
+	    res_to_endcont	0.2 \
+	    res_spacing		$mmetal_spacing \
+    ]
+    set drawdict [dict merge $gf180mcu::ruleset $newdict $parameters]
+    return [gf180mcu::res_draw $drawdict]
+}
+
+#----------------------------------------------------------------
+#endif (METALS3 || METALS4 || METALS5 || METALS6)
+
+#ifdef METALS4 || METALS5 || METALS6
+proc gf180mcu::rm4_draw {parameters} {
+
+    # Set a local variable for each rule in ruleset
+    foreach key [dict keys $gf180mcu::ruleset] {
+        set $key [dict get $gf180mcu::ruleset $key]
+    }
+
+    set newdict [dict create \
+	    guard		0 \
+	    res_type		rm4 \
+	    end_type 		m4 \
+	    end_surround	0.0 \
+	    end_spacing		0.0 \
+	    res_to_endcont	0.2 \
+	    res_spacing		$mmetal_spacing \
+    ]
+    set drawdict [dict merge $gf180mcu::ruleset $newdict $parameters]
+    return [gf180mcu::res_draw $drawdict]
+}
+#endif (METALS4 || METALS5 || METALS6)
+
+#ifdef METALS5 || METALS6
+proc gf180mcu::rm5_draw {parameters} {
+    # Set a local variable for each rule in ruleset
+    foreach key [dict keys $gf180mcu::ruleset] {
+        set $key [dict get $gf180mcu::ruleset $key]
+    }
+
+    set newdict [dict create \
+	    guard		0 \
+	    res_type		rm5 \
+	    end_type 		m5 \
+	    end_surround	0.0 \
+	    end_spacing		0.0 \
+	    res_to_endcont	0.2 \
+	    res_spacing		$mmetal_spacing \
+    ]
+    set drawdict [dict merge $gf180mcu::ruleset $newdict $parameters]
+    return [gf180mcu::res_draw $drawdict]
+}
+#endif (METALS5 || METALS6)
+#ifdef METALS6
+proc gf180mcu::rmtp_draw {parameters} {
+    # Set a local variable for each rule in ruleset
+    foreach key [dict keys $gf180mcu::ruleset] {
+        set $key [dict get $gf180mcu::ruleset $key]
+    }
+
+    set newdict [dict create \
+	    guard		0 \
+	    res_type		rmtp \
+	    end_type 		mtp \
+	    end_surround	0.0 \
+	    end_spacing		0.0 \
+	    res_to_endcont	0.2 \
+	    res_spacing		$mmetal_spacing \
+    ]
+    set drawdict [dict merge $gf180mcu::ruleset $newdict $parameters]
+    return [gf180mcu::res_draw $drawdict]
+}
+#endif (METALS6)
+
+#----------------------------------------------------------------
+# Resistor total length computation
+#----------------------------------------------------------------
+
+proc gf180mcu::compute_ltot {parameters} {
+    # In case snake not defined
+    set snake 0
+    set caplen 0
+
+    foreach key [dict keys $parameters] {
+        set $key [dict get $parameters $key]
+    }
+
+    set l [magic::spice2float $l]
+    set l [magic::3digitpastdecimal $l]
+
+    # Compute total length.  Use catch to prevent error in batch/scripted mode.
+    if {$snake == 1} {
+	catch {set magic::ltot_val [expr ($caplen * ($nx - 1)) + ($l * $nx) + ($nx - 1)]}
+    } else {
+	catch {set magic::ltot_val $l}
+    }
+}
+
+#----------------------------------------------------------------
+# resistor: Check device parameters for out-of-bounds values
+#----------------------------------------------------------------
+
+proc gf180mcu::res_check {device parameters} {
+
+    # Set a local variable for each parameter (e.g., $l, $w, etc.)
+    set snake 0
+    set sterm 0.0
+    set caplen 0
+    foreach key [dict keys $parameters] {
+        set $key [dict get $parameters $key]
+    }
+
+    # Normalize distance units to microns
+    set w [magic::spice2float $w]
+    set w [magic::3digitpastdecimal $w]
+    set l [magic::spice2float $l]
+    set l [magic::3digitpastdecimal $l]
+
+    set val  [magic::spice2float $val]
+    set rho  [magic::spice2float $rho]
+
+    # nf, m must be integer
+    if {![string is int $nx]} {
+	puts stderr "X repeat must be an integer!"
+        dict set parameters nx 1
+    }
+    if {![string is int $m]} {
+	puts stderr "Y repeat must be an integer!"
+        dict set parameters m 1
+    }
+
+    # Width always needs to be specified
+    if {$w < $wmin} {
+	puts stderr "Resistor width must be >= $wmin um"
+	dict set parameters w $wmin
+    } 
+    # Val and W specified - no L
+    if {$l == 0}  {
+   	set l [expr ($w - $dw) * $val / $rho]
+        set l [magic::3digitpastdecimal $l]
+        set stringval [magic::float2spice $val]
+	dict set parameters l [magic::float2spice [expr $l * 1e-6]]
+	# L and W specified - ignore Val if specified
+    } else {
+	if {$snake == 0} {
+	    set val [expr (2 * $term + $l * $rho) / ($w - $dw)]
+	} else {
+	    set val [expr $rho * ($nx - 1) + ((2 * ($term + $sterm)) \
+			+ ($rho * $l * $nx) + ($rho * $caplen * ($nx - 1))) \
+			/ ($w - $dw)]
+	}
+	set val [magic::float2spice $val]
+        dict set parameters val $val
+    }
+    if {$l < $lmin} {
+	puts stderr "Resistor length must be >= $lmin um"
+	dict set parameters l $lmin
+    } 
+    if {$nx < 1} {
+	puts stderr "X repeat must be >= 1"
+	dict set parameters nx 1
+    } 
+    if {$m < 1} {
+	puts stderr "Y repeat must be >= 1"
+	dict set parameters m 1
+    } 
+
+    # Snake resistors cannot have width greater than length
+    if {$snake == 1} {
+	if {$w > $l} {
+	    puts stderr "Snake resistor width must be < length"
+	    dict set parameters w $l
+	}
+    }
+
+    # Diffusion resistors must satisfy diffusion-to-tap spacing of 20um.
+    # Therefore the maximum of guard ring width or height cannot exceed 40um.
+    # If in violation, reduce counts first, as these are easiest to recover
+    # by duplicating the device and overlapping the wells.
+    if {$device == "rdn" || $device == "rdp"} {
+       set origm $m
+       set orignx $nx
+       while true {
+	  set xext [expr ($w + 0.8) * $nx + 1.0]
+	  set yext [expr ($l + 1.7) * $m + 1.7]
+          if {[expr min($xext, $yext)] > 40.0} {
+              if {$yext > 40.0 && $m > 1} {
+		 incr m -1
+	      } elseif {$xext > 40.0 && $nx > 1} {
+		 incr nx -1
+	      } elseif {$yext > 40.0} {
+		 set l 36.6
+		 puts -nonewline stderr "Diffusion resistor length must be < 36.6 um"
+		 puts stderr " to avoid tap spacing violation."
+		 dict set parameters l $l
+	      } elseif {$xext > 40.0} {
+		 set w 38.2
+		 puts -nonewline stderr "Diffusion resistor width must be < 38.2 um"
+		 puts stderr " to avoid tap spacing violation."
+		 dict set parameters w $w
+	      }
+          } else {
+	      break
+	  }
+       }
+       if {$m != $origm} {
+	  puts stderr "Y repeat reduced to prevent tap distance violation"
+	  dict set parameters m $m
+       }
+       if {$nx != $orignx} {
+	  puts stderr "X repeat reduced to prevent tap distance violation"
+	  dict set parameters nx $nx
+       }
+    }
+    gf180mcu::compute_ltot $parameters
+    return $parameters
+}
+
+#----------------------------------------------------------------
+
+proc gf180mcu::nwell_check {parameters} {
+    return [gf180mcu::res_check nwell $parameters]
+}
+
+proc gf180mcu::ppolyf_u_check {parameters} {
+    return [gf180mcu::res_check ppolyf_u $parameters]
+}
+
+proc gf180mcu::npolyf_u_check {parameters} {
+    return [gf180mcu::res_check npolyf_u $parameters]
+}
+
+proc gf180mcu::ppolyf_s_check {parameters} {
+    return [gf180mcu::res_check rpp1s $parameters]
+}
+
+proc gf180mcu::npolyf_s_check {parameters} {
+    return [gf180mcu::res_check rpp1s $parameters]
+}
+
+proc gf180mcu::nplus_u_check {parameters} {
+    return [gf180mcu::res_check nplus_u $parameters]
+}
+
+proc gf180mcu::pplus_u_check {parameters} {
+    return [gf180mcu::res_check pplus_u $parameters]
+}
+
+proc gf180mcu::rm1_check {parameters} {
+    return [gf180mcu::res_check rm1 $parameters]
+}
+
+proc gf180mcu::rm2_check {parameters} {
+    return [gf180mcu::res_check rm2 $parameters]
+}
+
+#ifdef METALS3 || METALS4 || METALS5 || METALS6
+proc gf180mcu::rm3_check {parameters} {
+    return [gf180mcu::res_check rm3 $parameters]
+}
+#endif (METALS3 || METALS4 || METALS5 || METALS6)
+
+#ifdef METALS4 || METALS5 || METALS6
+proc gf180mcu::rm4_check {parameters} {
+    return [gf180mcu::res_check rm4 $parameters]
+}
+#endif (METALS4 || METALS5 || METALS6)
+
+#ifdef METALS5 || METALS6
+proc gf180mcu::rm5_check {parameters} {
+    return [gf180mcu::res_check rm5 $parameters]
+}
+#endif (METALS5 || METALS6)
+#ifdef METALS6
+proc gf180mcu::rmtp_check {parameters} {
+    return [gf180mcu::res_check rmtp $parameters]
+}
+#endif (METALS6)
+
+#ifdef HRPOLY1K
+proc gf180mcu::ppolyf_u_1k_check {parameters} {
+    return [gf180mcu::res_check ppolyf_u_1k $parameters]
+}
+
+proc gf180mcu::ppolyf_u_1k_6p0_check {parameters} {
+    return [gf180mcu::res_check ppolyf_u_1k_6p0 $parameters]
+}
+#endif (HRPOLY1K)
+
+#----------------------------------------------------------------
+# MOS defaults:
+#----------------------------------------------------------------
+#    w       = Gate width
+#    l       = Gate length
+#    m	     = Multiplier
+#    nf	     = Number of fingers
+#    diffcov = Diffusion contact coverage
+#    polycov = Poly contact coverage
+#    topc    = Top gate contact
+#    botc    = Bottom gate contact
+#    guard   = Guard ring
+#
+# (not user-editable)
+#
+#    lmin    = Gate minimum length
+#    wmin    = Gate minimum width
+#----------------------------------------------------------------
+
+#----------------------------------------------------------------
+# pmos: Specify all user-editable default values and those
+# needed by pmos_check
+#----------------------------------------------------------------
+
+proc gf180mcu::pmos_3p3_defaults {} {
+    return {w 0.220 l 0.280 m 1 nf 1 diffcov 100 polycov 100 \
+		guard 1 glc 1 grc 1 gtc 0 gbc 0 tbcov 100 rlcov 100 \
+		topc 1 botc 1 poverlap 0 doverlap 1 lmin 0.28 wmin 0.22 \
+		full_metal 1 \
+		compatible {pmos_3p3 pmos_6p0}}
+}
+
+proc gf180mcu::pmos_6p0_defaults {} {
+    return {w 0.3 l 0.5 m 1 nf 1 diffcov 100 polycov 100 \
+		guard 1 glc 1 grc 1 gtc 0 gbc 0 tbcov 100 rlcov 100 \
+		topc 1 botc 1 poverlap 0 doverlap 1 lmin 0.5 wmin 0.3 \
+		full_metal 1 \
+		compatible {pmos_3p3 pmos_6p0}}
+}
+
+#----------------------------------------------------------------
+# nmos: Specify all user-editable default values and those
+# needed by nmos_check
+#----------------------------------------------------------------
+
+proc gf180mcu::nmos_3p3_defaults {} {
+    return {w 0.220 l 0.280 m 1 nf 1 diffcov 100 polycov 100 \
+		guard 1 glc 1 grc 1 gtc 0 gbc 0 tbcov 100 rlcov 100 \
+		topc 1 botc 1 poverlap 0 doverlap 1 lmin 0.28 wmin 0.22 \
+		full_metal 1 \
+		compatible {nmos_3p3 nmos_6p0 nmos_6p0_nat}}
+}
+
+proc gf180mcu::nmos_6p0_defaults {} {
+    return {w 0.3 l 0.6 m 1 nf 1 diffcov 100 polycov 100 \
+		guard 1 glc 1 grc 1 gtc 0 gbc 0 tbcov 100 rlcov 100 \
+		topc 1 botc 1 poverlap 0 doverlap 1 lmin 0.6 wmin 0.3 \
+		full_metal 1 \
+		compatible {nmos_3p3 nmos_6p0 nmos_6p0_nat}}
+}
+
+proc gf180mcu::nmos_6p0_nat_defaults {} {
+    return {w 0.8 l 1.8 m 1 nf 1 diffcov 100 polycov 100 \
+		guard 1 glc 1 grc 1 gtc 0 gbc 0 tbcov 100 rlcov 100 \
+		topc 1 botc 1 poverlap 0 doverlap 1 lmin 1.8 wmin 0.8 \
+		full_metal 1 \
+		compatible {nmos_3p3 nmos_6p0 nmos_6p0_nat}}
+}
+
+#----------------------------------------------------------------
+# mosvc: Specify all user-editable default values and those
+# needed by nmoscap_3p3_check
+#----------------------------------------------------------------
+
+proc gf180mcu::nmoscap_3p3_defaults {} {
+    return {w 1.0 l 1.0 m 1 nf 1 diffcov 100 polycov 100 \
+		guard 1 glc 1 grc 1 gtc 0 gbc 0 tbcov 100 rlcov 100 \
+		topc 1 botc 1 poverlap 0 doverlap 1 lmin 0.28 wmin 0.22 \
+		full_metal 1 compatible {nmoscap_3p3 nmoscap_6p0}}
+}
+
+proc gf180mcu::nmoscap_6p0_defaults {} {
+    return {w 1.0 l 1.0 m 1 nf 1 diffcov 100 polycov 100 \
+		guard 1 glc 1 grc 1 gtc 0 gbc 0 tbcov 100 rlcov 100 \
+		topc 1 botc 1 poverlap 0 doverlap 1 lmin 0.28 wmin 0.3 \
+		full_metal 1 compatible {nmoscap_3p3 nmoscap_6p0}}
+}
+
+#----------------------------------------------------------------
+# mos: Conversion from SPICE netlist parameters to toolkit
+#----------------------------------------------------------------
+
+proc gf180mcu::mos_convert {parameters} {
+    set pdkparams [dict create]
+    dict for {key value} $parameters {
+	switch -nocase $key {
+	    l -
+	    w {
+		# Length and width are converted to units of microns
+		set value [magic::spice2float $value]
+		set value [expr $value * 1e6]
+		set value [magic::3digitpastdecimal $value]
+		dict set pdkparams [string tolower $key] $value
+	    }
+	    m {
+		# M value in an expression like '1*1' convert to
+		# M and NF
+		if {[regexp {\'([0-9]+)\*([0-9]+)\'} $value valid m nf]} {
+		    dict set pdkparams [string tolower $key] $m
+		    dict set pdkparams nf $nf
+		} else {
+		    dict set pdkparams [string tolower $key] $value
+		}
+	    }
+	}
+    }
+    return $pdkparams
+}
+
+#----------------------------------------------------------------
+
+proc gf180mcu::nmos_3p3_convert {parameters} {
+    return [gf180mcu::mos_convert $parameters]
+}
+
+proc gf180mcu::nmos_6p0_convert {parameters} {
+    return [gf180mcu::mos_convert $parameters]
+}
+
+proc gf180mcu::nmos_6p0_nat_convert {parameters} {
+    return [gf180mcu::mos_convert $parameters]
+}
+
+proc gf180mcu::pmos_3p3_convert {parameters} {
+    return [gf180mcu::mos_convert $parameters]
+}
+
+proc gf180mcu::pmos_6p0_convert {parameters} {
+    return [gf180mcu::mos_convert $parameters]
+}
+
+proc gf180mcu::nmoscap_3p3_convert {parameters} {
+    return [gf180mcu::mos_convert $parameters]
+}
+
+proc gf180mcu::nmoscap_6p0_convert {parameters} {
+    return [gf180mcu::mos_convert $parameters]
+}
+
+#----------------------------------------------------------------
+# mos: Interactively specifies the fixed layout parameters
+#----------------------------------------------------------------
+
+proc gf180mcu::mos_dialog {device parameters} {
+    # Editable fields:      w, l, nf, m, diffcov, polycov
+    # Checked fields:  topc, botc
+
+    magic::add_entry w "Width (um)" $parameters
+    magic::add_entry l "Length (um)" $parameters
+    magic::add_entry nf "Fingers" $parameters
+    magic::add_entry m "M" $parameters
+
+    if {[dict exists $parameters compatible]} {
+       set sellist [dict get $parameters compatible]
+       # Reserved word "gencell" has special behavior to change the
+       # underlying device type 
+       dict set parameters gencell $device
+       magic::add_selectlist gencell "Device type" $sellist $parameters
+    }
+
+    magic::add_entry diffcov "Diffusion contact coverage (%)" $parameters
+    magic::add_entry polycov "Poly contact coverage (%)" $parameters
+    magic::add_entry rlcov "Guard ring contact coverage (%)" $parameters
+    if {[dict exists $parameters gbc]} {
+	magic::add_entry tbcov "Guard ring top/bottom contact coverage (%)" $parameters
+    }
+
+    magic::add_checkbox poverlap "Overlap at poly contact" $parameters
+    magic::add_checkbox doverlap "Overlap at diffusion contact" $parameters
+    magic::add_checkbox topc "Add top gate contact" $parameters
+    magic::add_checkbox botc "Add bottom gate contact" $parameters
+
+    magic::add_checkbox guard "Add guard ring" $parameters
+    magic::add_checkbox full_metal "Full metal guard ring" $parameters
+    magic::add_checkbox glc "Add left guard ring contact" $parameters
+    magic::add_checkbox grc "Add right guard ring contact" $parameters
+    if {[dict exists $parameters gbc]} {
+	magic::add_checkbox gbc "Add bottom guard ring contact" $parameters
+    }
+    if {[dict exists $parameters gtc]} {
+	magic::add_checkbox gtc "Add top guard ring contact" $parameters
+    }
+}
+
+#----------------------------------------------------------------
+
+proc gf180mcu::nmos_3p3_dialog {parameters} {
+    gf180mcu::mos_dialog nmos_3p3 $parameters
+}
+
+proc gf180mcu::nmos_6p0_dialog {parameters} {
+    gf180mcu::mos_dialog nmos_6p0 $parameters
+}
+
+proc gf180mcu::nmos_6p0_nat_dialog {parameters} {
+    gf180mcu::mos_dialog nmos_6p0_nat $parameters
+}
+
+proc gf180mcu::pmos_3p3_dialog {parameters} {
+    gf180mcu::mos_dialog pmos_3p3 $parameters
+}
+
+proc gf180mcu::pmos_6p0_dialog {parameters} {
+    gf180mcu::mos_dialog pmos_6p0 $parameters
+}
+
+proc gf180mcu::nmoscap_3p3_dialog {parameters} {
+    gf180mcu::mos_dialog nmoscap_3p3 $parameters
+}
+
+proc gf180mcu::nmoscap_6p0_dialog {parameters} {
+    gf180mcu::mos_dialog nmoscap_6p0 $parameters
+}
+
+#----------------------------------------------------------------
+# getbox:  Get the current cursor box, in microns
+#----------------------------------------------------------------
+
+proc gf180mcu::getbox {} {
+    set curbox [box values]
+    set newbox []
+    set oscale [cif scale out]
+    for {set i 0} {$i < 4} {incr i} {
+        set v [* [lindex $curbox $i] $oscale]
+        lappend newbox $v
+    }
+    return $newbox
+}
+
+#----------------------------------------------------------------
+# unionbox:  Get the union bounding box of box1 and box2
+#----------------------------------------------------------------
+
+proc gf180mcu::unionbox {box1 box2} {
+    set newbox []
+    for {set i 0} {$i < 2} {incr i} {
+        set v [lindex $box1 $i]
+        set o [lindex $box2 $i]
+        if {$v < $o} {
+            lappend newbox $v
+        } else {
+            lappend newbox $o
+        }
+    }
+    for {set i 2} {$i < 4} {incr i} {
+        set v [lindex $box1 $i]
+        set o [lindex $box2 $i]
+        if {$v > $o} {
+            lappend newbox $v
+        } else {
+            lappend newbox $o
+        }
+    }
+    return $newbox
+}
+
+#----------------------------------------------------------------
+# Draw a contact
+#----------------------------------------------------------------
+
+proc gf180mcu::draw_contact {w h s o x atype ctype mtype {orient vert}} {
+
+    # Draw a minimum-size diff contact centered at current position
+    # w is width, h is height.  Minimum size ensured.
+    # x is contact size
+    # s is contact diffusion (or poly) surround
+    # o is contact metal surround
+    # atype is active (e.g., ndiff) or bottom metal if a via
+    # ctype is contact (e.g., ndc)
+    # mtype is metal (e.g., m1) or top metal if a via
+    # cover is percent maximum coverage of contact
+
+    pushbox
+    box size 0 0
+    if {$w < $x} {set w $x}
+    if {$h < $x} {set h $x}
+    set hw [/ $w 2.0]
+    set hh [/ $h 2.0]
+    # Bottom layer surrounded on all sides
+    box grow e ${hw}um
+    box grow w ${hw}um
+    box grow n ${hh}um
+    box grow s ${hh}um
+    pushbox
+    paint ${ctype}
+    popbox
+    pushbox
+    box grow c ${s}um
+    paint ${atype}
+    set extents [gf180mcu::getbox]
+    popbox
+    if {($orient == "vert") || ($orient == "full")} {
+        box grow n ${o}um
+        box grow s ${o}um
+    }
+    if {($orient == "horz") || ($orient == "full")} {
+        box grow e ${o}um
+        box grow w ${o}um
+    }
+    paint ${mtype}
+    popbox
+    return $extents
+}
+
+#----------------------------------------------------------------
+# Draw a guard ring
+#----------------------------------------------------------------
+
+proc gf180mcu::guard_ring {gw gh parameters} {
+
+    # Set local default values if they are not in parameters
+    set rlcov 100	;# Right-left contact coverage percentage
+    set tbcov 100	;# Top-bottom contact coverage percentage
+    set grc 1		;# Draw right side contact
+    set glc 1		;# Draw left side contact
+    set gtc 0		;# Draw right side contact
+    set gbc 0		;# Draw left side contact
+    set full_metal 0	;# Draw full (continuous) metal ring
+
+    # Set a local variable for each parameter (e.g., $l, $w, etc.)
+    foreach key [dict keys $parameters] {
+        set $key [dict get $parameters $key]
+    }
+
+    set hx [/ $contact_size 2.0]
+    set hw [/ $gw 2.0]
+    set hh [/ $gh 2.0]
+
+    # Compute diffusion width
+    set difft [+ $contact_size $diff_surround $diff_surround]
+    set hdifft [/ $difft 2.0]
+    # Compute guard ring diffusion width and height
+    set hdiffw [/ [+ $gw $difft] 2.0]
+    set hdiffh [/ [+ $gh $difft] 2.0]
+
+    pushbox
+    box size 0 0
+
+    pushbox
+    box move n ${hh}um
+    box grow n ${hdifft}um
+    box grow s ${hdifft}um
+    box grow e ${hdiffw}um
+    box grow w ${hdiffw}um
+    paint $plus_diff_type
+    popbox
+    pushbox
+    box move s ${hh}um
+    box grow n ${hdifft}um
+    box grow s ${hdifft}um
+    box grow e ${hdiffw}um
+    box grow w ${hdiffw}um
+    paint $plus_diff_type
+    popbox
+    pushbox
+    box move e ${hw}um
+    box grow e ${hdifft}um
+    box grow w ${hdifft}um
+    box grow n ${hdiffh}um
+    box grow s ${hdiffh}um
+    paint $plus_diff_type
+    popbox
+    pushbox
+    box move w ${hw}um
+    box grow e ${hdifft}um
+    box grow w ${hdifft}um
+    box grow n ${hdiffh}um
+    box grow s ${hdiffh}um
+    paint $plus_diff_type
+    popbox
+
+    if {$full_metal} {
+	set hmetw [/ [+ $gw $contact_size] 2.0]
+	set hmeth [/ [+ $gh $contact_size] 2.0]
+	pushbox
+	box move n ${hh}um
+	box grow n ${hx}um
+	box grow s ${hx}um
+	box grow e ${hmetw}um
+	box grow w ${hmetw}um
+	paint m1
+	popbox
+	pushbox
+	box move s ${hh}um
+	box grow n ${hx}um
+	box grow s ${hx}um
+	box grow e ${hmetw}um
+	box grow w ${hmetw}um
+	paint m1
+	popbox
+	pushbox
+	box move e ${hw}um
+	box grow e ${hx}um
+	box grow w ${hx}um
+	box grow n ${hmeth}um
+	box grow s ${hmeth}um
+	paint m1
+	popbox
+	pushbox
+	box move w ${hw}um
+	box grow e ${hx}um
+	box grow w ${hx}um
+	box grow n ${hmeth}um
+	box grow s ${hmeth}um
+	paint m1
+	popbox
+    }
+
+    # Set guard ring height so that contact metal reaches to end, scale by $per
+    # set ch [* [+ $gh $contact_size [* $metal_surround -2.0]] [/ $rlcov 100.0]]
+    set ch [* [- $gh $contact_size [* [+ $metal_surround $metal_spacing] \
+		2.0]] [/ $rlcov 100.0]]
+    if {$ch < $contact_size} {set ch $contact_size}
+
+    # Set guard ring width so that contact metal reaches to side contacts
+    set cw [* [- $gw $contact_size [* [+ $metal_surround $metal_spacing] \
+		2.0]] [/ $tbcov 100.0]]
+    if {$cw < $contact_size} {set cw $contact_size}
+
+    if {$tbcov > 0.0} {
+        if {$gtc == 1} {
+            pushbox
+            box move n ${hh}um
+            gf180mcu::draw_contact $cw 0 $diff_surround $metal_surround \
+		$contact_size $plus_diff_type $plus_contact_type m1 horz
+            popbox
+	}
+	if {$gbc == 1} {
+	    pushbox
+	    box move s ${hh}um
+	    gf180mcu::draw_contact $cw 0 $diff_surround $metal_surround \
+		$contact_size $plus_diff_type $plus_contact_type m1 horz
+	    popbox
+	}
+    }
+    if {$rlcov > 0.0} {
+        if {$grc == 1} {
+            pushbox
+            box move e ${hw}um
+            gf180mcu::draw_contact 0 $ch $diff_surround $metal_surround \
+		$contact_size $plus_diff_type $plus_contact_type m1 vert
+            popbox
+        }
+        if {$glc == 1} {
+            pushbox
+            box move w ${hw}um
+            gf180mcu::draw_contact 0 $ch $diff_surround $metal_surround \
+		$contact_size $plus_diff_type $plus_contact_type m1 vert
+            popbox
+        }
+    }
+
+    pushbox
+    box grow e ${hw}um
+    box grow w ${hw}um
+    box grow n ${hh}um
+    box grow s ${hh}um
+    property FIXED_BBOX [box values]
+    box grow c ${hx}um  ;# to edge of contact
+    box grow c ${diff_surround}um  ;# to edge of diffusion
+    box grow c ${sub_surround}um  ;# sub/well overlap of diff
+    paint $sub_type
+    set cext [gf180mcu::getbox]
+    popbox
+    popbox
+
+    return $cext
+}
+
+#----------------------------------------------------------------
+# MOSFET: Draw a single device
+#----------------------------------------------------------------
+
+proc gf180mcu::mos_device {parameters} {
+
+    # Epsilon for avoiding round-off errors
+    set eps  0.0005
+
+    # Set local default values if they are not in parameters
+    set diffcov 100	;# percent coverage of diffusion contact
+    set polycov 100	;# percent coverage of poly contact
+    set topc 1		;# draw top poly contact
+    set botc 1		;# draw bottom poly contact
+    set dev_sub_type ""	;# device substrate type (if different from guard ring)
+
+    # Set a local variable for each parameter (e.g., $l, $w, etc.)
+    foreach key [dict keys $parameters] {
+        set $key [dict get $parameters $key]
+    }
+
+    # Draw the diffusion and poly
+    pushbox
+    box size 0 0
+    pushbox
+    set hw [/ $w 2.0]
+    set hl [/ $l 2.0]
+    box grow n ${hw}um
+    box grow s ${hw}um
+    box grow e ${hl}um
+    box grow w ${hl}um
+    pushbox
+    if {${diff_extension} > ${gate_to_diffcont}} {
+        box grow e ${diff_extension}um
+        box grow w ${diff_extension}um
+    } else {
+        box grow e ${gate_to_diffcont}um
+        box grow w ${gate_to_diffcont}um
+        # Grow to far side of contact;  avoids diffusion separation if
+	# the contact is a dogbone and is moved outward to meet the DRC
+	# diffusion to gate spacing rule.
+	set hc [/ ${contact_size} 2.0]
+        box grow e ${hc}um
+        box grow w ${hc}um
+    }
+    paint ${diff_type}
+    popbox
+    pushbox
+    if {${gate_extension} > ${gate_to_polycont}} {
+	box grow n ${gate_extension}um
+	box grow s ${gate_extension}um
+    } else {
+	if {$topc} {
+	    box grow n ${gate_to_polycont}um
+	} else {
+	    box grow n ${gate_extension}um
+	}
+	if {$botc} {
+	    box grow s ${gate_to_polycont}um
+	} else {
+	    box grow s ${gate_extension}um
+	}
+    }
+    paint ${poly_type}
+    set cext [gf180mcu::getbox]
+    popbox
+    # gate_type need not be defined if poly over diff paints the right type.
+    catch {paint ${gate_type}}
+    popbox
+
+    # Adjust position of contacts for dogbone geometry
+    # Rule 1: Minimize diffusion length.  Contacts only move out
+    # if width <  contact diffusion height.  They move out enough
+    # that the diffusion-to-poly spacing is satisfied.  Change the
+    # orientation of the diffusion contact from vertical to horizontal
+
+    set diffcont_orient vert
+    set ddover 0
+    set cdwmin [+ ${contact_size} [* ${diff_surround} 2]]
+    set cstem [- ${gate_to_diffcont} [/ ${cdwmin} 2.0]]
+    set cgrow [- ${diff_poly_space} ${cstem}]
+    if {[+ ${w} ${eps}] < ${cdwmin}} {
+        if {${cgrow} > 0} {
+            set gate_to_diffcont [+ ${gate_to_diffcont} ${cgrow}]
+	    set diffcont_orient horz
+        }
+	set ddover [/ [- ${cdwmin} ${w}] 2.0]
+    }
+
+    # Rule 2: Minimum poly width.  Poly contacts only move out
+    # if length < contact poly width.  They move out enough
+    # that the diffusion-to-poly spacing is satisfied.
+
+    set gporig ${gate_to_polycont}
+    set cplmin [+ ${contact_size} [* ${poly_surround} 2]]
+    set cstem [- ${gate_to_polycont} [/ ${cplmin} 2.0]]
+    set cgrow [- ${diff_poly_space} ${cstem}]
+    if {[+ ${l} ${eps}] < ${cplmin}} {
+        if {${cgrow} > 0} {
+            set gate_to_polycont [+ ${gate_to_polycont} ${cgrow}]
+        }
+    }
+
+    # Rule 3: If both poly and diffusion are dogboned, then move
+    # poly out further to clear spacing to the diffusion contact.
+
+    if {[+ ${w} ${eps}] < ${cdwmin}} {
+        if {[+ ${l} ${eps}] < ${cplmin}} {
+            set cgrow [/ [- ${cplmin} ${w}] 2.0]
+            set gate_to_polycont [+ ${gate_to_polycont} ${cgrow}]
+        }
+    }
+
+    # Rule 4: If M > 1 and poly contacts overlap, then increase the
+    # transistor-to-poly-contact distance by the amount of any
+    # diffusion dogbone overhang.
+
+    if {($poverlap == 1) && ($m > 1)} {
+	if {${gate_to_polycont} - $gporig < $ddover} {
+	    set gate_to_polycont [+ ${gporig} ${ddover}]
+	}
+    }
+
+    # Reduce contact sizes by poly or diffusion surround so that
+    # the contact area edges match the device diffusion or poly.
+    # (Minimum dimensions will be enforced by the contact drawing routine)
+    set cdw [- ${w} [* ${diff_surround} 2]]     ;# diff contact height
+    set cpl [- ${l} [* ${poly_surround} 2]]     ;# poly contact width
+
+    # Reduce by coverage percentage.  NOTE:  If overlapping multiple devices,
+    # keep maximum poly contact coverage.
+
+    set cdw [* ${cdw} [/ ${diffcov} 100.0]]
+    if {($poverlap == 0) || ($m == 1)} {
+	set cpl [* ${cpl} [/ ${polycov} 100.0]]
+    }
+
+    # Right diffusion contact
+    pushbox
+    box move e ${hl}um
+    box move e ${gate_to_diffcont}um
+    set cext [gf180mcu::unionbox $cext [gf180mcu::draw_contact 0 ${cdw} \
+		${diff_surround} ${metal_surround} ${contact_size}\
+		${diff_type} ${diff_contact_type} m1 ${diffcont_orient}]]
+    popbox
+    # Left diffusion contact
+    pushbox
+    box move w ${hl}um
+    box move w ${gate_to_diffcont}um
+    set cext [gf180mcu::unionbox $cext [gf180mcu::draw_contact 0 ${cdw} \
+		${diff_surround} ${metal_surround} ${contact_size} \
+		${diff_type} ${diff_contact_type} m1 ${diffcont_orient}]]
+    popbox
+    # Top poly contact
+    if {$topc} {
+       pushbox
+       box move n ${hw}um
+       box move n ${gate_to_polycont}um
+       set cext [gf180mcu::unionbox $cext [gf180mcu::draw_contact ${cpl} 0 \
+		${poly_surround} ${metal_surround} ${contact_size} \
+		${poly_type} ${poly_contact_type} m1 horz]]
+       popbox
+    }
+    # Bottom poly contact
+    if {$botc} {
+       pushbox
+       box move s ${hw}um
+       box move s ${gate_to_polycont}um
+       set cext [gf180mcu::unionbox $cext [gf180mcu::draw_contact ${cpl} 0 \
+		${poly_surround} ${metal_surround} ${contact_size} \
+		${poly_type} ${poly_contact_type} m1 horz]]
+       popbox
+    }
+
+    if {$dev_sub_type != ""} {
+        # puts stdout "Diagnostic:  bounding box is $cext"
+	set llx [lindex $cext 0]
+	set lly [lindex $cext 1]
+	set urx [lindex $cext 2]
+	set ury [lindex $cext 3]
+	box values ${llx}um ${lly}um ${urx}um ${ury}um
+	box grow n ${sub_surround}um
+	box grow s ${sub_surround}um
+	box grow e ${sub_surround}um
+	box grow w ${sub_surround}um
+	paint ${dev_sub_type}
+	set cext [gf180mcu::getbox]
+        # puts stdout "Diagnostic:  bounding box is $cext"
+    }
+
+    popbox
+    return $cext
+}
+
+#----------------------------------------------------------------
+# MOSFET: Draw the tiled device
+#----------------------------------------------------------------
+
+proc gf180mcu::mos_draw {parameters} {
+    tech unlock *
+
+    # Set defaults if they are not in parameters
+    set poverlap 0	;# overlap poly contacts when tiling
+    set doverlap 1	;# overlap diffusion contacts when tiling
+    set dev_sub_dist 0	;# substrate to guard ring, if dev_sub_type defined
+    set dev_surround 0	;# substrate/well surrounds device, if no guard ring
+
+    # Set a local variable for each parameter (e.g., $l, $w, etc.)
+    foreach key [dict keys $parameters] {
+        set $key [dict get $parameters $key]
+    }
+
+    # If poverlap is 1 then both poly contacts must be present
+    if {$poverlap == 1} {
+	set topc 1
+	set botc 1
+	dict set parameters topc 1
+	dict set parameters botc 1
+    }
+
+    # Normalize distance units to microns
+    set w [magic::spice2float $w]
+    set l [magic::spice2float $l]
+
+    pushbox
+    box values 0 0 0 0
+
+    # Determine the base device dimensions by drawing one device
+    # while all layers are locked (nothing drawn).  This allows the
+    # base drawing routine to do complicated geometry without having
+    # to duplicate it here with calculations.
+
+    tech lock *
+    set bbox [gf180mcu::mos_device $parameters]
+    # puts stdout "Diagnostic: Device bounding box e $bbox (um)"
+    tech unlock *
+
+    set fw [- [lindex $bbox 2] [lindex $bbox 0]]
+    set fh [- [lindex $bbox 3] [lindex $bbox 1]]
+    set lw [+ [lindex $bbox 2] [lindex $bbox 0]]
+    set lh [+ [lindex $bbox 3] [lindex $bbox 1]]
+
+    # Determine tile width and height (depends on overlap)
+    if {$poverlap == 0} {
+        set dy [+ $fh $poly_spacing]
+    } else {
+        # overlap poly
+        set dy [- $fh [+ $poly_surround $poly_surround $contact_size]]
+    }
+
+    if {$doverlap == 0} {
+        set dx [+ $fw $diff_spacing]
+    } else {
+        # overlap diffusions
+        set dx [- $fw [+ $diff_surround $diff_surround $contact_size]]
+    }
+
+    # Determine core width and height
+    set corex [+ [* [- $nf 1] $dx] $fw]
+    set corey [+ [* [- $m 1] $dy] $fh]
+    set corellx [/ [+ [- $corex $fw] $lw] 2.0]
+    set corelly [/ [+ [- $corey $fh] $lh] 2.0]
+
+    # If there is a diffusion dogbone, and no top poly contact, then
+    # increase the core height by the amount of the dogbone overhang.
+
+    if {$topc == 0} {
+	set cdwmin [+ ${contact_size} [* ${diff_surround} 2]]
+	if {${w} < ${cdwmin}} {
+	    set corey [+ $corey [/ [- ${cdwmin} ${w}] 2.0]]
+	}
+    }
+
+    # Calculate guard ring size (measured to contact center)
+    if {($dev_sub_dist > 0) && ([+ $dev_sub_dist $sub_surround] > $diff_spacing)} {
+	set gx [+ $corex [* 2.0 [+ $dev_sub_dist $diff_surround]] $contact_size]
+    } else {
+	set gx [+ $corex [* 2.0 [+ $diff_spacing $diff_surround]] $contact_size]
+    }
+    if {($dev_sub_dist > 0) && ([+ $dev_sub_dist $sub_surround] > $diff_gate_space)} {
+	set gy [+ $corey [* 2.0 [+ $dev_sub_dist $diff_surround]] $contact_size]
+    } else {
+	set gy [+ $corey [* 2.0 [+ $diff_gate_space $diff_surround]] $contact_size]
+    }
+
+    if {($guard != 0)} {
+        # Somewhat tricky. . . if the width is small and the diffusion is 
+        # a dogbone, and the top or bottom poly contact is missing, then
+        # the spacing to the guard ring may be limited by diffusion spacing, not
+        # poly to diffusion.
+
+        set inset [/ [+ $contact_size [* 2.0 $diff_surround] -$w] 2.0]
+        set sdiff [- [+ $inset $diff_spacing] [+ $gate_extension $diff_gate_space]]
+
+        if {$sdiff > 0} {
+	    if {$topc == 0} {
+	        set gy [+ $gy $sdiff]
+	        set corelly [+ $corelly [/ $sdiff 2.0]]
+	    }
+	    if {$botc == 0} {
+	        set gy [+ $gy $sdiff]
+	        set corelly [- $corelly [/ $sdiff 2.0]]
+	    }
+        }
+    }
+    if {$guard != 0} {
+	# Draw the guard ring first, as MOS well may interact with guard ring substrate
+	gf180mcu::guard_ring $gx $gy $parameters
+    } else {
+	pushbox
+	if {$dev_surround == 0} {set dev_surround $sub_surround}
+	set hgx [+ $dev_surround [/ $corex 2]]
+	set hgy [+ $dev_surround [/ $corey 2]]
+	box grow e ${hgx}um
+	box grow w ${hgx}um
+	box grow n ${hgy}um
+	box grow s ${hgy}um
+	paint $sub_type
+	popbox
+    }
+
+    pushbox
+    box move w ${corellx}um
+    box move s ${corelly}um
+    for {set xp 0} {$xp < $nf} {incr xp} {
+        pushbox
+        for {set yp 0} {$yp < $m} {incr yp} {
+            gf180mcu::mos_device $parameters
+            box move n ${dy}um
+        }
+        popbox
+        box move e ${dx}um
+    }
+    popbox
+    popbox
+
+    tech revert
+}
+
+#-------------------
+# nMOS 3.3V
+#-------------------
+
+proc gf180mcu::nmos_3p3_draw {parameters} {
+    set newdict [dict create \
+	    gate_type		nfet \
+	    diff_type 		ndiff \
+	    diff_contact_type	ndc \
+	    plus_diff_type	psd \
+	    plus_contact_type	psc \
+	    poly_type		poly \
+	    poly_contact_type	pc \
+	    sub_type		pwell \
+	    sub_surround	0.12 \
+    ]
+    set drawdict [dict merge $gf180mcu::ruleset $newdict $parameters]
+    return [gf180mcu::mos_draw $drawdict]
+}
+
+#-------------------
+# pMOS 3.3V
+#-------------------
+
+proc gf180mcu::pmos_3p3_draw {parameters} {
+    set newdict [dict create \
+	    gate_type		pfet \
+	    diff_type 		pdiff \
+	    diff_contact_type	pdc \
+	    plus_diff_type	nsd \
+	    plus_contact_type	nsc \
+	    poly_type		poly \
+	    poly_contact_type	pc \
+	    dev_surround	0.43 \
+	    sub_type		nwell \
+    ]
+    set drawdict [dict merge $gf180mcu::ruleset $newdict $parameters]
+    return [gf180mcu::mos_draw $drawdict]
+}
+
+#-------------------
+# pMOS 6.0V
+#-------------------
+
+proc gf180mcu::pmos_6p0_draw {parameters} {
+    set newdict [dict create \
+	    diff_poly_space	0.30 \
+	    diff_gate_space	0.30 \
+	    diff_spacing	0.36 \
+	    gate_type		mvpfet \
+	    diff_type 		mvpdiff \
+	    diff_contact_type	mvpdc \
+	    plus_diff_type	mvnsd \
+	    plus_contact_type	mvnsc \
+	    poly_type		poly \
+	    poly_contact_type	pc \
+	    sub_surround	0.16 \
+	    dev_surround	0.43 \
+	    sub_type		nwell \
+    ]
+    set drawdict [dict merge $gf180mcu::ruleset $newdict $parameters]
+    return [gf180mcu::mos_draw $drawdict]
+}
+
+#-------------------
+# nMOS 6.0V
+#-------------------
+
+proc gf180mcu::nmos_6p0_draw {parameters} {
+    set newdict [dict create \
+	    diff_poly_space	0.30 \
+	    diff_gate_space	0.30 \
+	    diff_spacing	0.36 \
+	    gate_type		mvnfet \
+	    diff_type 		mvndiff \
+	    diff_contact_type	mvndc \
+	    plus_diff_type	mvpsd \
+	    plus_contact_type	mvpsc \
+	    poly_type		poly \
+	    poly_contact_type	pc \
+	    sub_type		pwell \
+	    sub_surround	0.16 \
+    ]
+    set drawdict [dict merge $gf180mcu::ruleset $newdict $parameters]
+    return [gf180mcu::mos_draw $drawdict]
+}
+
+proc gf180mcu::nmos_6p0_nat_draw {parameters} {
+    set newdict [dict create \
+	    gate_type		mvnnfet \
+	    diff_type 		mvndiff \
+	    diff_contact_type	mvndc \
+	    plus_diff_type	mvpsd \
+	    plus_contact_type	mvpsc \
+	    poly_type		poly \
+	    poly_contact_type	pc \
+	    sub_type		pwell \
+	    sub_surround	0.16 \
+	    gate_extension	0.35 \
+    ]
+    set drawdict [dict merge $gf180mcu::ruleset $newdict $parameters]
+    return [gf180mcu::mos_draw $drawdict]
+}
+
+#------------------------
+# MOS varactor (3.3V)
+#------------------------
+
+proc gf180mcu::nmoscap_3p3_draw {parameters} {
+    set newdict [dict create \
+	    gate_type		var \
+	    diff_type 		nsd \
+	    diff_contact_type	nsc \
+	    plus_diff_type	psd \
+	    plus_contact_type	psc \
+	    poly_type		poly \
+	    poly_contact_type	pc \
+	    sub_type		pwell \
+	    dev_sub_type	nwell \
+	    dev_sub_dist	0.12 \
+    ]
+    set drawdict [dict merge $gf180mcu::ruleset $newdict $parameters]
+    return [gf180mcu::mos_draw $drawdict]
+}
+
+#------------------------
+# MOS varactor (6.0V)
+#------------------------
+
+proc gf180mcu::nmoscap_6p0_draw {parameters} {
+    set newdict [dict create \
+	    diff_poly_space	0.30 \
+	    diff_gate_space	0.30 \
+	    diff_spacing	0.36 \
+	    gate_type		mvvar \
+	    diff_type 		mvnsd \
+	    diff_contact_type	mvnsc \
+	    plus_diff_type	mvpsd \
+	    plus_contact_type	mvpsc \
+	    poly_type		poly \
+	    poly_contact_type	pc \
+	    sub_type		pwell \
+	    sub_surround	0.16 \
+	    dev_sub_type	nwell \
+    ]
+    set drawdict [dict merge $gf180mcu::ruleset $newdict $parameters]
+    return [gf180mcu::mos_draw $drawdict]
+}
+
+#----------------------------------------------------------------
+# nmos: Check device parameters for out-of-bounds values
+#----------------------------------------------------------------
+
+proc gf180mcu::mos_check {parameters} {
+
+    # Set a local variable for each parameter (e.g., $l, $w, etc.)
+    foreach key [dict keys $parameters] {
+        set $key [dict get $parameters $key]
+    }
+
+    # Normalize distance units to microns
+    set l [magic::spice2float $l] 
+    set l [magic::3digitpastdecimal $l]
+    set w [magic::spice2float $w] 
+    set w [magic::3digitpastdecimal $w]
+
+    # nf, m must be integer
+    if {![string is int $nf]} {
+	puts stderr "NF must be an integer!"
+        dict set parameters nf 1
+    }
+    if {![string is int $m]} {
+	puts stderr "M must be an integer!"
+        dict set parameters m 1
+    }
+    # diffcov, polycov must be numeric
+    if {[catch {expr abs($diffcov)}]} {
+	puts stderr "diffcov must be numeric!"
+	set diffcov 100
+    }
+    if {[catch {expr abs($polycov)}]} {
+	puts stderr "polycov must be numeric!"
+	set polycov 100
+    }
+
+    if {$l < $lmin} {
+	puts stderr "Mos length must be >= $lmin um"
+        dict set parameters l $lmin
+    } 
+    if {$w < $wmin} {
+	puts stderr "Mos width must be >= $wmin um"
+        dict set parameters w $wmin
+    } 
+    if {$nf < 1} {
+	puts stderr "NF must be >= 1"
+        dict set parameters nf 1
+    } 
+    if {$m < 1} {
+	puts stderr "M must be >= 1"
+        dict set parameters m 1
+    } 
+    if {$diffcov < 20 } {
+	puts stderr "Diffusion contact coverage must be at least 20%"
+        dict set parameters diffcov 20
+    } elseif {$diffcov > 100 } {
+	puts stderr "Diffusion contact coverage can't be more than 100%"
+        dict set parameters diffcov 100
+    }
+    if {$polycov < 20 } {
+	puts stderr "Poly contact coverage must be at least 20%"
+        dict set parameters polycov 20
+    } elseif {$polycov > 100 } {
+	puts stderr "Poly contact coverage can't be more than 100%"
+        dict set parameters polycov 100
+    }
+
+    # Values must satisfy diffusion-to-tap spacing of 20um.
+    # Therefore the maximum of guard ring width or height cannot exceed 40um.
+    # If in violation, reduce counts first, as these are easiest to recover
+    # by duplicating the device and overlapping the wells.
+    set origm $m
+    set orignf $nf
+    while true {
+       set yext [expr ($w + 3.0) * $m]
+       set xext [expr ($l + 1.0) * $nf + 1.1]
+       if {[expr min($xext, $yext)] > 40.0} {
+          if {$yext > 40.0 && $m > 1} {
+	     incr m -1
+	  } elseif {$xext > 40.0 && $nf > 1} {
+	     incr nf -1
+	  } elseif {$yext > 40.0} {
+	     set w 37
+	     puts -nonewline stderr "Transistor width must be < 37 um"
+	     puts stderr " to avoid tap spacing violation."
+	     dict set parameters w $w
+	  } elseif {$xext > 40.0} {
+	     set l 37.9
+	     puts -nonewline stderr "Transistor length must be < 37.9 um"
+	     puts stderr " to avoid tap spacing violation."
+	     dict set parameters l $l
+	  }
+       } else {
+	  break
+       }
+    }
+    if {$m != $origm} {
+       puts stderr "Y repeat reduced to prevent tap distance violation"
+       dict set parameters m $m
+    }
+    if {$nf != $orignf} {
+       puts stderr "X repeat reduced to prevent tap distance violation"
+       dict set parameters nf $nf
+    }
+
+    return $parameters
+}
+
+#----------------------------------------------------------------
+
+proc gf180mcu::nmos_3p3_check {parameters} {
+   return [gf180mcu::mos_check $parameters]
+}
+
+proc gf180mcu::nmos_6p0_check {parameters} {
+   return [gf180mcu::mos_check $parameters]
+}
+
+proc gf180mcu::nmos_6p0_nat_check {parameters} {
+   return [gf180mcu::mos_check $parameters]
+}
+
+proc gf180mcu::pmos_3p3_check {parameters} {
+   return [gf180mcu::mos_check $parameters]
+}
+
+proc gf180mcu::pmos_6p0_check {parameters} {
+   return [gf180mcu::mos_check $parameters]
+}
+
+proc gf180mcu::nmoscap_3p3_check {parameters} {
+   return [gf180mcu::mos_check $parameters]
+}
+
+proc gf180mcu::nmoscap_6p0_check {parameters} {
+   return [gf180mcu::mos_check $parameters]
+}
+
+#----------------------------------------------------------------
+# Bipolar: Specify all user-editable default values
+#
+# deltax --- Additional horizontal space between devices
+# deltay --- Additional vertical space between devices
+# nx     --- Number of arrayed devices in X
+# ny     --- Number of arrayed devices in Y
+#
+# Note that these values, specifically nx, ny, deltax,
+# and deltay, are properties of the instance, not the cell.
+# They translate to the instance array x and y counts;  while
+# deltax is the x pitch less the cell width, and deltay is the
+# y pitch less the cell height.
+#
+# non-user-editable
+#
+# nocell --- Indicates that this cell has a predefined layout
+#	     and therefore there is no cell to draw.
+# xstep  --- Width of the cell (nominal array pitch in X)
+# ystep  --- Height of the cell (nominal array pitch in Y)
+#----------------------------------------------------------------
+
+proc gf180mcu::vnpn_5x5_defaults {} {
+    return {nx 1 ny 1 deltax 0 deltay 0 nocell 1 xstep 13.94 ystep 13.94}
+}
+
+proc gf180mcu::vnpn_5x0p42_defaults {} {
+    return {nx 1 ny 1 deltax 0 deltay 0 nocell 1 xstep 12.36 ystep 16.22}
+}
+
+proc gf180mcu::vnpn_10x10_defaults {} {
+    return {nx 1 ny 1 deltax 0 deltay 0 nocell 1 xstep 16.94 ystep 16.94}
+}
+
+proc gf180mcu::vnpn_10x0p42_defaults {} {
+    return {nx 1 ny 1 deltax 0 deltay 0 nocell 1 xstep 12.36 ystep 21.22}
+}
+
+proc gf180mcu::vpnp_5x5_defaults {} {
+    return {nx 1 ny 1 deltax 0 deltay 0 nocell 1 xstep 13.94 ystep 13.94}
+}
+
+proc gf180mcu::vpnp_5x0p42_defaults {} {
+    return {nx 1 ny 1 deltax 0 deltay 0 nocell 1 xstep 12.36 ystep 16.22}
+}
+
+proc gf180mcu::vpnp_10x10_defaults {} {
+    return {nx 1 ny 1 deltax 0 deltay 0 nocell 1 xstep 16.94 ystep 16.94}
+}
+
+proc gf180mcu::vpnp_10x0p42_defaults {} {
+    return {nx 1 ny 1 deltax 0 deltay 0 nocell 1 xstep 12.36 ystep 21.22}
+}
+
+#----------------------------------------------------------------
+# Bipolar: Conversion from SPICE netlist parameters to toolkit
+#----------------------------------------------------------------
+
+proc gf180mcu::fixed_convert {parameters} {
+    set pdkparams [dict create]
+    dict for {key value} $parameters {
+	switch -nocase $key {
+	    m {
+		 dict set pdkparams nx $value
+	    }
+	}
+    }
+    return $pdkparams
+}
+
+#----------------------------------------------------------------
+
+proc gf180mcu::vnpn_5x5_convert {parameters} {
+    return [gf180mcu::fixed_convert $parameters]
+}
+
+proc gf180mcu::vnpn_5x0p42_convert {parameters} {
+    return [gf180mcu::fixed_convert $parameters]
+}
+
+proc gf180mcu::vnpn_10x10_convert {parameters} {
+    return [gf180mcu::fixed_convert $parameters]
+}
+
+proc gf180mcu::vnpn_10x0p42_convert {parameters} {
+    return [gf180mcu::fixed_convert $parameters]
+}
+
+proc gf180mcu::vpnp_5x5_convert {parameters} {
+    return [gf180mcu::fixed_convert $parameters]
+}
+
+proc gf180mcu::vpnp_5x0p42_convert {parameters} {
+    return [gf180mcu::fixed_convert $parameters]
+}
+
+proc gf180mcu::vpnp_10x10_convert {parameters} {
+    return [gf180mcu::fixed_convert $parameters]
+}
+
+proc gf180mcu::vpnp_10x0p42_convert {parameters} {
+    return [gf180mcu::fixed_convert $parameters]
+}
+
+#----------------------------------------------------------------
+# Bipolar: Interactively specifies the fixed layout parameters
+#----------------------------------------------------------------
+
+proc gf180mcu::fixed_dialog {parameters} {
+    # Instance fields:	    nx, ny, pitchx, pitchy
+    # Editable fields:	    nx, ny, deltax, deltay
+    # Non-editable fields:  nocell, xstep, ystep
+
+    # Set a local variable for each parameter (e.g., $l, $w, etc.)
+    foreach key [dict keys $parameters] {
+        set $key [dict get $parameters $key]
+    }
+
+    # "nocell" field causes nx and ny to be dropped in from
+    # "array count".  Also "pitchx" and "pitchy" are passed
+    # in internal units.  Convert these to microns and generate
+    # If there is no pitchx and pitchy, then the device has not
+    # yet been created, so keep the deltax and deltay defaults.
+
+    if [dict exists $parameters pitchx] {
+	set pitchux [magic::i2u $pitchx]
+	set stepux [magic::spice2float $xstep]
+        set deltax [magic::3digitpastdecimal [expr $pitchux - $stepux]] 
+        # An array size 1 should not cause deltax to go negative
+	if {$deltax < 0.0} {set deltax 0.0}
+	dict set parameters deltax $deltax
+    }
+    if [dict exists $parameters pitchy] {
+	set pitchuy [magic::i2u $pitchy]
+	set stepuy [magic::spice2float $ystep]
+        set deltay [magic::3digitpastdecimal [expr $pitchuy - $stepuy]] 
+        # An array size 1 should not cause deltay to go negative
+	if {$deltay < 0.0} {set deltay 0.0}
+	dict set parameters deltay $deltay
+    }
+
+    magic::add_entry nx "NX" $parameters
+    magic::add_entry ny "NY" $parameters
+    magic::add_entry deltax "X step (um)" $parameters
+    magic::add_entry deltay "Y step (um)" $parameters
+}
+
+#----------------------------------------------------------------
+
+proc gf180mcu::vnpn_5x5_dialog {parameters} {
+    gf180mcu::fixed_dialog $parameters
+}
+
+proc gf180mcu::vnpn_5x0p42_dialog {parameters} {
+    gf180mcu::fixed_dialog $parameters
+}
+
+proc gf180mcu::vnpn_10x10_dialog {parameters} {
+    gf180mcu::fixed_dialog $parameters
+}
+
+proc gf180mcu::vnpn_10x0p42_dialog {parameters} {
+    gf180mcu::fixed_dialog $parameters
+}
+
+proc gf180mcu::vpnp_5x5_dialog {parameters} {
+    gf180mcu::fixed_dialog $parameters
+}
+
+proc gf180mcu::vpnp_5x0p42_dialog {parameters} {
+    gf180mcu::fixed_dialog $parameters
+}
+
+proc gf180mcu::vpnp_10x10_dialog {parameters} {
+    gf180mcu::fixed_dialog $parameters
+}
+
+proc gf180mcu::vpnp_10x0p42_dialog {parameters} {
+    gf180mcu::fixed_dialog $parameters
+}
+
+#----------------------------------------------------------------
+# PNP: Draw the device
+#----------------------------------------------------------------
+
+proc gf180mcu::fixed_draw {devname parameters} {
+
+    # Set a local variable for each parameter (e.g., $l, $w, etc.)
+    foreach key [dict keys $parameters] {
+        set $key [dict get $parameters $key]
+    }
+
+    # This cell declares "nocell" in parameters, so it needs to
+    # instance the cell and set properties.
+
+    # Instantiate the cell.  The name corresponds to the cell in the primdev directory.
+    set instname [getcell ${devname}]
+
+    set deltax [magic::spice2float $deltax] 
+    set deltay [magic::spice2float $deltay] 
+    set xstep [magic::spice2float $xstep] 
+    set ystep [magic::spice2float $ystep] 
+
+    # Array stepping
+    if {$nx > 1 || $ny > 1} {
+        set xstep [expr $xstep + $deltax]
+        set ystep [expr $ystep + $deltay]
+        box size ${xstep}um ${ystep}um
+	array $nx $ny
+    }
+    select cell $instname
+    expand
+    return $instname
+}
+
+#----------------------------------------------------------------
+# No additional parameters declared for drawing
+#----------------------------------------------------------------
+
+proc gf180mcu::vnpn_5x5_draw {parameters} {
+   return [gf180mcu::fixed_draw vnpn_5x5 $parameters]
+}
+
+proc gf180mcu::vnpn_5x0p42_draw {parameters} {
+   return [gf180mcu::fixed_draw vnpn_5x0p42 $parameters]
+}
+
+proc gf180mcu::vnpn_10x10_draw {parameters} {
+   return [gf180mcu::fixed_draw vnpn_10X10 $parameters]
+}
+
+proc gf180mcu::vnpn_10x0p42_draw {parameters} {
+   return [gf180mcu::fixed_draw vnpn_10X0p42 $parameters]
+}
+
+proc gf180mcu::vpnp_5x5_draw {parameters} {
+   return [gf180mcu::fixed_draw vpnp_5x5 $parameters]
+}
+
+proc gf180mcu::vpnp_5x0p42_draw {parameters} {
+   return [gf180mcu::fixed_draw vpnp_5x0p42 $parameters]
+}
+
+proc gf180mcu::vpnp_10x10_draw {parameters} {
+   return [gf180mcu::fixed_draw vpnp_10X10 $parameters]
+}
+
+proc gf180mcu::vpnp_10x0p42_draw {parameters} {
+   return [gf180mcu::fixed_draw vpnp_10X0p42 $parameters]
+}
+
+#----------------------------------------------------------------
+# Bipolar: Check device parameters for out-of-bounds values
+#----------------------------------------------------------------
+
+proc gf180mcu::fixed_check {parameters} {
+
+    # Set a local variable for each parameter (e.g., $l, $w, etc.)
+    foreach key [dict keys $parameters] {
+        set $key [dict get $parameters $key]
+    }
+
+    # Normalize distance units to microns
+    set deltax [magic::spice2float $deltax -1] 
+    set deltax [magic::3digitpastdecimal $deltax]
+    set deltay [magic::spice2float $deltay -1] 
+    set deltay [magic::3digitpastdecimal $deltay]
+
+    # nx, ny must be integer
+    if {![string is int $nx]} {
+	puts stderr "NX must be an integer!"
+        dict set parameters nx 1
+    }
+    if {![string is int $ny]} {
+	puts stderr "NY must be an integer!"
+        dict set parameters nx 1
+    }
+
+    # Number of devices in X and Y must be at least 1
+    if {$nx < 1} {
+	puts stderr "NX must be >= 1"
+        dict set parameters nx 1
+    }
+    if {$ny < 1} {
+	puts stderr "NY must be >= 1"
+        dict set parameters nx 1
+    }
+    # Step less than zero violates DRC
+    if {$deltax < 0} {
+	puts stderr "X step must be >= 0"
+        dict set parameters deltax 0
+    }
+    if {$deltay < 0} {
+	puts stderr "Y step must be >= 0"
+        dict set parameters deltay 0
+    }
+    return $parameters
+}
+
+#----------------------------------------------------------------
+
+proc gf180mcu::vnpn_5x5_check {parameters} {
+    return [gf180mcu::fixed_check $parameters]
+}
+
+proc gf180mcu::vnpn_5x0p42_check {parameters} {
+    return [gf180mcu::fixed_check $parameters]
+}
+
+proc gf180mcu::vnpn_10x10_check {parameters} {
+    return [gf180mcu::fixed_check $parameters]
+}
+
+proc gf180mcu::vnpn_10x0p42_check {parameters} {
+    return [gf180mcu::fixed_check $parameters]
+}
+
+proc gf180mcu::vpnp_5x5_check {parameters} {
+    return [gf180mcu::fixed_check $parameters]
+}
+
+proc gf180mcu::vpnp_5x0p42_check {parameters} {
+    return [gf180mcu::fixed_check $parameters]
+}
+
+proc gf180mcu::vpnp_10x10_check {parameters} {
+    return [gf180mcu::fixed_check $parameters]
+}
+
+proc gf180mcu::vpnp_10x0p42_check {parameters} {
+    return [gf180mcu::fixed_check $parameters]
+}
+
+
diff --git a/gf180mcu/magic/gf180mcu.tech b/gf180mcu/magic/gf180mcu.tech
new file mode 100644
index 0000000..ba9b5a9
--- /dev/null
+++ b/gf180mcu/magic/gf180mcu.tech
@@ -0,0 +1,4618 @@
+###
+###	Source file TECHNAME.tech
+###	Process this file with the preproc.py macro processor
+###
+#----------------------------------------------------------
+# Copyright (c) 2022 Efabless, Inc.
+# Techfile created by R. Timothy Edwards for the Google/
+# Global Foundries Open PDK project.
+#
+#----------------------------------------------------------
+# This file is designed to be used with magic
+# versions 8.3 or newer.
+#
+# Rules reflect lambda = 0.05um.  Minimum grid is 0.005um
+#----------------------------------------------------------
+tech
+  format 34
+  TECHNAME
+end
+
+version
+ version REVISION
+ description "Global Foundries 180mcu: open PDK rules and DRC"
+ requires magic-8.3.304
+end
+
+#-----------------------------------------------------
+# Tile planes
+#-----------------------------------------------------
+
+planes
+  dwell,dw
+  well,w
+  active,a
+  metal1,m1
+  metal2,m2
+#ifdef METALS3 || METALS4 || METALS5 || METALS6
+  metal3,m3
+#endif (METALS3 || METALS4 || METALS5 || METALS6)
+#ifdef METALS4 || METALS5 || METALS6
+  metal4,m4
+#endif (METALS4 || METALS5 || METALS6)
+#ifdef METALS5 || METALS6
+  metal5,m5
+#endif (METALS5 || METALS6)
+#ifdef METALS6
+  metaltp,mtp
+#endif (METALS6)
+  block,b
+  comment,c
+end
+
+#-----------------------------------------------------
+# Tile types
+#-----------------------------------------------------
+
+types
+# Deep nwell
+  dwell deepnwell,dnwell,dnw
+  dwell isosubstrate,isosub
+
+# Wells outside deep nwell
+  well nwell,nw
+  well pwell,pw
+# Well obstruction layer
+ -well obswell
+# Well resistors
+  well rnw,rnwell
+
+# Transistors
+  active nmos,ntransistor,nfet
+  active pmos,ptransistor,pfet
+  active nnmos,nntransistor,nnfet
+  active mvnmos,mvntransistor,mvnfet
+  active mvpmos,mvptransistor,mvpfet
+  active mvnnmos,mvnntransistor,mvnnfet
+# Diffusions
+  active ndiff,ndiffusion,ndif
+  active pdiff,pdiffusion,pdif
+  active mvndiff,mvndiffusion,mvndif
+  active mvpdiff,mvpdiffusion,mvpdif
+  active ndiffc,ndcontact,ndc
+  active pdiffc,pdcontact,pdc
+  active mvndiffc,mvndcontact,mvndc
+  active mvpdiffc,mvpdcontact,mvpdc
+  active psubdiff,psubstratepdiff,ppdiff,ppd,psd
+  active nsubdiff,nsubstratendiff,nndiff,nnd,nsd
+  active mvpsubdiff,mvpsubstratepdiff,mvppdiff,mvppd,mvpsd
+  active mvnsubdiff,mvnsubstratendiff,mvnndiff,mvnnd,mvnsd
+  active psubdiffcont,psubstratepcontact,psc
+  active nsubdiffcont,nsubstratencontact,nsc
+  active mvpsubdiffcont,mvpsubstratepcontact,mvpsc
+  active mvnsubdiffcont,mvnsubstratencontact,mvnsc
+ -active obsactive
+ -active mvobsactive
+  active varactor,varact,var
+  active mvvaractor,mvvaract,mvvar
+# Poly
+  active polysilicon,poly,p
+  active polycontact,pcontact,polycut,pc,polyc
+# Resistors
+  active npolyres,npres,rnp
+  active ppolyres,ppres,rpp
+  active npolysilicide,nsresistor,nspres,rnps
+  active ppolysilicide,psresistor,pspres,rpps
+#ifdef HRPOLY1K
+  active nhighres,nhires,hires
+  active mvnhighres,mvnhires,mvhires
+#endif (HRPOLY1K)
+  active ndiffres,rnd,rdn,rndiff
+  active pdiffres,rpd,rdp,rpdiff
+  active ndiffsilicide,rnds,rdns,rndiffs
+  active pdiffsilicide,rpds,rdps,rpdiffs
+  active mvndiffres,mvrnd,mvrdn,mvrndiff
+  active mvpdiffres,mvrpd,mvrdp,mvrpdiff
+  active mvndiffsilicide,mvrnds,mvrdns,mvrndiffs
+  active mvpdiffsilicide,mvrpds,mvrdps,mvrpdiffs
+# Diodes
+  active pdiode,pdi
+  active ndiode,ndi
+  active nndiode,nndi
+  active pdiodec,pdic
+  active ndiodec,ndic
+  active nndiodec,nndic
+  active mvpdiode,mvpdi
+  active mvndiode,mvndi
+  active mvnndiode,mvnndi
+  active mvpdiodec,mvpdic
+  active mvndiodec,mvndic
+  active mvnndiodec,mvnndic
+
+ -active filldiff
+ -active fillpoly
+
+  metal1 metal1,m1,met1
+  metal1 rmetal1,rm1,rmet1
+ -metal1 m1hole
+  metal1 via1,m2contact,m2cut,m2c,via,v,v1
+ -metal1 obsm1
+ -metal1 fillm1
+ -metal1 obsv1
+  metal1 padl
+
+  metal2 metal2,m2,met2
+  metal2 rmetal2,rm2,rmet2
+ -metal2 m2hole
+  metal2 via2,m3contact,m3cut,m3c,v2
+ -metal2 obsm2
+ -metal2 fillm2
+ -metal2 obsv2
+#ifdef MIM
+#ifdef METALS3
+  metal2 mimcap,mim,capm
+  metal2 mimcapcontact,mimcapc,mimcc,capmc
+#elseif defined(METALS4)
+  metal3 mimcap,mim,capm
+  metal3 mimcapcontact,mimcapc,mimcc,capmc
+#elseif defined(METALS5)
+  metal4 mimcap,mim,capm
+  metal4 mimcapcontact,mimcapc,mimcc,capmc
+#elseif defined(METALS6)
+  metal5 mimcap,mim,capm
+  metal5 mimcapcontact,mimcapc,mimcc,capmc
+#endif
+#endif (MIM)
+
+#ifdef METALS3 || METALS4 || METALS5 || METALS6
+  metal3 metal3,m3,met3
+  metal3 rmetal3,rm3,rmet3
+ -metal3 m3hole
+ -metal3 obsm3
+ -metal3 fillm3
+#endif (METALS3 || METALS4 || METALS5 || METALS6)
+#ifdef METALS4 || METALS5 || METALS6
+  metal3 via3,v3
+
+  metal4 metal4,m4,met4
+  metal4 rmetal4,rm4,rmet4
+ -metal4 m4hole
+ -metal4 obsm4
+ -metal4 fillm4
+#endif (METALS4 || METALS5 || METALS6)
+#ifdef (METALS5 || METALS6)
+  metal4 via4,v4
+
+  metal5 metal5,m5,met5
+  metal5 rm5,rmetal5,rmet5
+ -metal5 m5hole
+ -metal5 obsm5
+ -metal5 fillm5
+#endif (METALS5 || METALS6)
+#ifdef METALS6
+  metal5 viatp,vtp
+
+  metaltp metaltp,mtp,mettp
+  metaltp rmtp,rmetaltp,rmettp
+ -metaltp mtphole
+ -metaltp obsmtp
+ -metaltp fillmtp
+#endif (METALS6)
+
+  block  glass
+  block  fillblock
+
+ -comment lvstext
+  comment comment
+ -comment obscomment
+
+end
+
+#-----------------------------------------------------
+# Magic contact types
+#-----------------------------------------------------
+
+contact
+  pc poly metal1
+  ndc ndiff metal1
+  pdc pdiff metal1
+  nsc nsd metal1
+  psc psd metal1
+  ndic ndiode metal1
+  nndic nndiode metal1
+  pdic pdiode metal1
+
+  mvndc mvndiff metal1
+  mvpdc mvpdiff metal1
+  mvnsc mvnsd metal1
+  mvpsc mvpsd metal1
+  mvndic mvndiode metal1
+  mvpdic mvpdiode metal1
+  mvnndic mvnndiode metal1
+
+  via1 metal1 metal2
+#ifdef METALS3 || METALS4 || METALS5 || METALS6
+  via2 metal2 metal3
+#endif (METALS3 || METALS4 || METALS5 || METALS6)
+#ifdef METALS4 || METALS5 || METALS6
+  via3 metal3 metal4
+#endif (METALS4 || METALS5 || METALS6)
+#ifdef METALS5 || METALS6
+  via4  metal4 metal5
+#endif (METALS5 || METALS6)
+#ifdef METALS6
+  viatp metal5 metaltp
+#endif (METALS6)
+
+#ifdef MIM
+#ifdef METALS3
+  mimcc mimcap metal3
+#elseif defined(METALS4)
+  mimcc mimcap metal4
+#elseif defined(METALS5)
+  mimcc mimcap metal5
+#elseif defined(METALS6)
+  mimcc mimcap metaltp
+#endif
+#endif (MIM)
+  stackable
+
+#ifdef METALS3
+  padl m1 m2 m3 glass
+#elseif defined(METALS4)
+  padl m1 m2 m3 m4 glass
+#elseif defined(METALS5)
+  padl m1 m2 m3 m4 m5 glass
+#elseif defined(METALS6)
+  padl m1 m2 m3 m4 m5 mtp glass
+#else
+  padl m1 m2 glass
+#endif
+end
+
+#-----------------------------------------------------
+# Layer aliases
+#-----------------------------------------------------
+
+aliases
+
+  allnwell	   nwell,rnwell
+
+  allpsub	   space/w,pwell
+
+  # Similar to allpsub* but does not include space-on-well-plane
+  allpwell	   pwell
+
+  # Allsubwell contains space-on-well-plane but not obstruction-on-well-plane
+  # Used for defining anything under a device that does not touch active/substrate 
+  allsubwell	   allnwell,allpsub
+  # Allwells contains obstruction-on-well-plane but not space-on-well-plane
+  allwells         allnwell,allpwell,obswell
+
+  allnfets	   nfet,mvnfet,nnfet,mvnnfet
+  allnfetsnonnat   nfet,mvnfet
+  allpfets	   pfet,mvpfet
+  allfets	   allnfets,allpfets,varactor,mvvaractor
+  allfetsnonnat	   allnfetsnonnat,allpfets,varactor,mvvaractor
+  allfetsmv	   mvnfet,mvpfet,mvnnfet,mvvaractor
+
+  allnactivenonfet *ndiff,*nsd,*ndiode,*nndiode,*mvndiff,*mvnsd,*mvndiode,*mvnndiode
+  allnactive	   allnactivenonfet,allnfets
+
+  allpactivenonfet *pdiff,*psd,*pdiode,*mvpdiff,*mvpsd,*mvpdiode
+  allpactive	   allpactivenonfet,allpfets
+
+  allactivenonfet  allnactivenonfet,allpactivenonfet
+  allactive	   allactivenonfet,allfets
+
+  allactiveres	   ndiffres,pdiffres,mvndiffres,mvpdiffres
+
+  allndifflv       *ndif,*nsd,*ndiode,*nndiode,ndiffres,nfet,nnfet
+  allpdifflv       *pdif,*psd,*pdiode,pdiffres,pfet
+  alldifflv        allndifflv,allpdifflv
+  allndifflvnonfet *ndif,*nsd,*ndiode,*nndiode,ndiffres
+  allpdifflvnonfet *pdif,*psd,*pdiode,pdiffres
+  alldifflvnonfet  allndifflvnonfet,allpdifflvnonfet
+
+  allndiffmv       *mvndif,*mvnsd,*mvndiode,mvndiffres,mvnfet,mvnnfet,mvvaractor,*mvnndiode
+  allpdiffmv       *mvpdif,*mvpsd,*mvpdiode,mvpdiffres,mvpfet
+  alldiffmv        allndiffmv,allpdiffmv
+  allndiffmvnonfet *mvndif,*mvnsd,*mvndiode,mvndiffres,*mvnndiode
+  allpdiffmvnonfet *mvpdif,*mvpsd,*mvpdiode,mvpdiffres
+  alldiffmvnonfet  allndiffmvnonfet,allpdiffmvnonfet
+
+  alldiffnonfet	   alldifflvnonfet,alldiffmvnonfet
+  alldiff	   alldifflv,alldiffmv
+
+  allnactivenonhv  nfet,mvnfet,nnfet,mvnnfet,varactor,mvvaractor,*ndiff,*mvndiff,*nsd,*mvnsd,*ndiode,*nndiode,*mvndiode,*mvnndiode
+  allpactivenonhv  pfet,mvpfet,*pdiff,*mvpdiff,*psd,*mvpsd,*pdiode,*mvpdiode
+  allactivenonhv   allnactivenonhv,allpactivenonhv
+
+#ifdef HRPOLY1K
+  allpolyres	   rpp,rnp,rpps,rnps,hires,mvhires
+  allpolysblkres   rpp,rnp,hires,mvhires
+  allsblkdev	   rnp,rpp,rnd,rpd,hires,mvhires,mvrnd,mvrpd
+#else (!HRPOLY1K)
+  allpolyres	   rpp,rnp,rpps,rnps
+  allpolysblkres   rpp,rnp
+  allsblkdev	   rnp,rpp,rnd,rpd,mvrnd,mvrpd
+#endif (!HRPOLY1K)
+
+  allpolynonfet	   *poly,allpolyres
+  allpolynonres	   *poly,allfets
+
+  allpoly	   allpolynonfet,allfets
+  allpolynoncap	   *poly,allfets,allpolyres
+
+  allndiffcontlv   ndc,nsc,ndic,nndic
+  allpdiffcontlv   pdc,psc,pdic
+  allndiffcontmv   mvndc,mvnsc,mvndic,mvnndic
+  allpdiffcontmv   mvpdc,mvpsc,mvpdic
+  allndiffcont	   allndiffcontlv,allndiffcontmv
+  allpdiffcont	   allpdiffcontlv,allpdiffcontmv
+  alldiffcontlv	   allndiffcontlv,allpdiffcontlv
+  alldiffcontmv	   allndiffcontmv,allpdiffcontmv
+  alldiffcont	   alldiffcontlv,alldiffcontmv
+
+  allcont	   alldiffcont,pc
+
+  allres	   allpolyres,allactiveres
+  alldiode	   *pdiode,*ndiode,*nndiode,*mvpdiode,*mvndiode,*mvnndiode
+
+  allm1		   *m1,rm1
+  allm2		   *m2,rm2
+
+#ifdef METALS3 || METALS4 || METALS5 || METALS6
+#ifdef MIM && METALS4
+  allm3		   *m3,rm3,*mimcap
+#else (!(MIM && METALS4))
+  allm3		   *m3,rm3
+#endif (!(MIM && METALS4))
+#endif (METALS3 || METALS4 || METALS5 || METALS6)
+
+#ifdef METALS4 || METALS5 || METALS6
+#ifdef MIM && METALS5
+  allm4	   	*m4,rm4,*mimcap
+#else (!(MIM && METALS5))
+  allm4	   	*m4,rm4
+#endif (!(MIM && METALS5))
+#endif (METALS4 || METALS5 || METALS6)
+
+#ifdef METALS5 || METALS6
+#ifdef MIM && METALS6
+  allm5	   	*m5,rm5,*mimcap
+#else (!(MIM && METALS6))
+  allm5	   	*m5,rm5
+#endif (!(MIM && METALS6))
+#endif (METALS5 || METALS6)
+
+#ifdef METALS6
+  allmtp	*mtp,rmtp
+#endif (METALS6)
+
+  allpad	   padl
+end
+
+#-----------------------------------------------------
+# Layer drawing styles
+#-----------------------------------------------------
+
+styles
+ styletype mos
+  dnwell    cwell
+  isosub    subcircuit
+
+  nwell     nwell
+  rnwell    nwell 	ntransistor_stripes
+  pwell	    pwell
+
+  ndiff     ndiffusion
+  pdiff     pdiffusion
+  nsd       ndiff_in_nwell
+  psd       pdiff_in_pwell
+  nfet      ntransistor    ntransistor_stripes
+  nnfet     ntransistor    ndiff_in_nwell
+  pfet      ptransistor    ptransistor_stripes
+  var       polysilicon    ndiff_in_nwell
+  ndc       ndiffusion     metal1  contact_X'es
+  pdc       pdiffusion     metal1  contact_X'es
+  nsc       ndiff_in_nwell metal1  contact_X'es
+  psc       pdiff_in_pwell metal1  contact_X'es
+
+  mvndiff     ndiffusion     hvndiff_mask
+  mvpdiff     pdiffusion     hvpdiff_mask
+  mvnsd       ndiff_in_nwell hvndiff_mask
+  mvpsd       pdiff_in_pwell hvpdiff_mask
+  mvnfet      ntransistor    ntransistor_stripes hvndiff_mask
+  mvnnfet     ntransistor    ndiff_in_nwell hvndiff_mask
+  mvpfet      ptransistor    ptransistor_stripes
+  mvvar       polysilicon    ndiff_in_nwell hvndiff_mask
+  mvndc       ndiffusion     metal1  contact_X'es hvndiff_mask
+  mvpdc       pdiffusion     metal1  contact_X'es hvpdiff_mask
+  mvnsc       ndiff_in_nwell metal1  contact_X'es hvndiff_mask
+  mvpsc       pdiff_in_pwell metal1  contact_X'es hvpdiff_mask
+
+  poly      polysilicon 
+  pc        polysilicon    metal1  contact_X'es
+  npolyres  polysilicon    silicide_block nselect2
+  ppolyres  polysilicon    silicide_block pselect2
+
+  pdiode    pdiffusion     pselect2
+  ndiode    ndiffusion     nselect2
+  nndiode   ndiff_in_nwell nselect2
+  pdiodec   pdiffusion     pselect2 metal1 contact_X'es
+  ndiodec   ndiffusion     nselect2 metal1 contact_X'es
+  nndiodec  ndiff_in_nwell nselect2 metal1 contact_X'es
+
+  mvpdiode    pdiffusion     pselect2 hvpdiff_mask
+  mvndiode    ndiffusion     nselect2 hvndiff_mask
+  mvnndiode   ndiff_in_nwell nselect2 hvndiff_mask
+  mvpdiodec   pdiffusion     pselect2 metal1 contact_X'es hvpdiff_mask
+  mvndiodec   ndiffusion     nselect2 metal1 contact_X'es hvndiff_mask
+  mvnndiodec  ndiff_in_nwell nselect2 metal1 contact_X'es hvndiff_mask
+
+  metal1    metal1
+  rm1       metal1         poly_resist_stripes
+  obsm1     metal1
+  fillm1    metal1
+  obsv1     metal1	   metal2  via1arrow
+  m1hole    obsmetal1
+  m2c       metal1         metal2  via1arrow
+  metal2    metal2
+  rm2       metal2         poly_resist_stripes
+  obsm2     metal2
+  fillm2    metal2
+  obsv2     metal2	   metal3  via2arrow
+  m2hole    obsmetal2
+#ifdef METALS3 || METALS4 || METALS5 || METALS6
+  m3c       metal2         metal3  via2arrow
+  metal3    metal3
+  rm3       metal3         poly_resist_stripes
+  obsm3     metal3
+  fillm3    metal3
+  m3hole    obsmetal3
+#endif (METALS3 || METALS4 || METALS5 || METALS6)
+#ifdef METALS4 || METALS5 || METALS6
+  via3      metal3         metal4  via3alt
+  metal4    metal4
+  rm4       metal4         poly_resist_stripes
+  obsm4     metal4
+  fillm4    metal4
+  m4hole    obsmetal4
+#endif (METALS4 || METALS5 || METALS6)
+#ifdef METALS5 || METALS6
+  via4      metal4         metal5  via4
+  metal5    metal5
+  rm5       metal5         poly_resist_stripes
+  obsm5     metal5
+  fillm5    metal5
+  m5hole    obsmetal5
+#endif (METALS5 || METALS6)
+#ifdef METALS6
+  viatp     metal5         metal6  via5
+  metaltp   metal6
+  rmtp      metal6         poly_resist_stripes
+  obsmtp    metal6
+  fillmtp   metal6
+  mtphole   obsmetal6
+#endif (METALS6)
+
+#ifdef MIM
+#ifdef METALS3
+  mimcap    metal2         mems
+  mimcc     metal2         contact_X'es mems
+#elseif defined(METALS4)
+  mimcap    metal3         mems
+  mimcc     metal3         contact_X'es mems
+#elseif defined(METALS5)
+  mimcap    metal4         mems
+  mimcc     metal4         contact_X'es mems
+#elseif defined(METALS6)
+  mimcap    metal5         mems 
+  mimcc     metal5         contact_X'es mems
+#endif
+#endif (MIM)
+  glass	    overglass
+  rnp       poly_resist    poly_resist_stripes	ndop_stripes
+  rpp       poly_resist    poly_resist_stripes	pdop_stripes
+  rnps      poly_resist    ndop_stripes
+  rpps      poly_resist    pdop_stripes
+#ifdef HRPOLY1K
+  nhighres  poly_resist    silicide_block
+  mvnhighres  poly_resist  silicide_block  hvndiff_mask
+#endif (HRPOLY1K)
+  ndiffres  ndiffusion	   ndop_stripes
+  pdiffres  pdiffusion	   pdop_stripes
+  mvndiffres  ndiffusion hvndiff_mask   ndop_stripes
+  mvpdiffres  pdiffusion hvpdiff_mask   pdop_stripes
+  comment   comment
+  lvstext   comment
+  error_p   error_waffle
+  error_s   error_waffle
+  error_ps  error_waffle
+  fillblock cwell
+
+  obswell   cwell
+  obsactive implant4
+  filldiff  ndiffusion
+  fillpoly  polysilicon
+
+#ifdef METALS3
+  padl      metal3 via3 overglass
+#elseif defined(METALS4)
+  padl      metal4 via4 overglass
+#elseif defined(METALS5)
+  padl      metal5 via5 overglass
+#elseif defined(METALS6)
+  padl      metal6 via6 overglass
+#else
+  padl      metal2 via2 overglass
+#endif
+
+  magnet    substrate_field_implant
+  rotate    via3alt
+  fence     via5
+end
+
+#-----------------------------------------------------
+# Special paint/erase rules
+#-----------------------------------------------------
+
+compose
+  compose  nfet  poly  ndiff
+  compose  pfet  poly  pdiff
+  compose  var   poly  nsd
+
+  compose  mvnfet  poly  mvndiff
+  compose  mvpfet  poly  mvpdiff
+  compose  var     poly  mvnsd
+  
+#ifdef MIM
+#ifdef METALS3
+  paint  mimcap  m2     mimcap
+  paint  mimcapc m2     mimcapc
+#elseif defined(METALS4)
+  paint  mimcap  m3     mimcap
+  paint  mimcapc m3     mimcapc
+#elseif defined(METALS5)
+  paint  mimcap  m4     mimcap
+  paint  mimcapc m4     mimcapc
+#elseif defined(METALS6)
+  paint  mimcap  m5     mimcap
+  paint  mimcapc m5     mimcapc
+#endif
+#endif (MIM)
+  paint  ndc     nwell  pdc
+  paint  nfet    nwell  pfet
+  paint  ndiff   nwell  pdiff
+  paint  psd     nwell  nsd
+  paint  psc     nwell  nsc
+  paint  pdc     pwell  ndc
+  paint  pfet    pwell  nfet
+  paint  pdiff   pwell  ndiff
+  paint  nsd     pwell  psd
+  paint  nsc     pwell  psc
+
+  paint  m1      obsm1  m1
+  paint  m2      obsm2  m2
+#ifdef METALS3 || METALS4 || METALS5 || METALS6
+  paint  m3      obsm3  m3
+#endif (METALS3 || METALS4 || METALS5 || METALS6)
+#ifdef METALS4 || METALS5 || METALS6
+  paint  m4      obsm4  m4
+#endif (METALS4 || METALS5 || METALS6)
+#ifdef METALS5 || METALS6
+  paint  m5      obsm5  m5
+#endif (METALS5 || METALS6)
+#ifdef METALS6
+  paint  mtp     obsmtp mtp
+#endif (METALS6)
+end
+
+#-----------------------------------------------------
+# Electrical connectivity
+#-----------------------------------------------------
+
+connect
+  nwell,*nsd,*mvnsd nwell,*nsd,*mvnsd
+  pwell,*psd,*mvpsd,isosub  pwell,*psd,*mvpsd,isosub
+  *psd,*mvpsd  *psd,*mvpsd
+  *m1	*m1
+  *m2	*m2
+#ifdef METALS3 || METALS4 || METALS5 || METALS6
+  *m3	*m3
+#endif (METALS3 || METALS4 || METALS5 || METALS6)
+#ifdef METALS4 || METALS5 || METALS6
+  *m4	*m4
+#endif (METALS4 || METALS5 || METALS6)
+#ifdef METALS5 || METALS6
+  *m5	*m5
+#endif (METALS5 || METALS6)
+#ifdef METAL6
+  *mtp	*mtp
+#endif (METALS6)
+#ifdef MIM
+  *mimcap     *mimcap
+#endif (MIM)
+   allnactivenonfet	allnactivenonfet
+   allpactivenonfet	allpactivenonfet
+  *poly,allfets		*poly,allfets
+end
+
+#-----------------------------------------------------
+# CIF/GDS output layer definitions
+#-----------------------------------------------------
+# NOTE:  All values in this section MUST be multiples of 25 
+# or else magic will scale below the allowed layout grid size
+
+cifoutput
+
+#-----------------------------------------------------
+style gdsii
+#-----------------------------------------------------
+ scalefactor 50 nanometers
+ options calma-permissive-labels
+ gridlimit 5
+
+# This section used for actual GDSII output 
+
+#-----------------------------------------------------
+# DNWELL
+#-----------------------------------------------------
+ layer DNWELL	dnwell
+	calma	12 0
+
+#-----------------------------------------------------
+# NWELL
+#-----------------------------------------------------
+ layer NWELL 	allnwell
+	close	1000000
+ 	calma 	21 0
+
+#-----------------------------------------------------
+# PWELL (LVPWELL)
+#-----------------------------------------------------
+ layer PWELL 	pwell
+ 	calma 	204 0
+
+#-----------------------------------------------------
+# DIFF (COMP)
+#-----------------------------------------------------
+ layer DIFF 	alldiff
+ 	labels 	alldiff
+ 	calma 	22 0
+
+ layer DIFFFILL	filldiff
+	labels	filldiff
+	calma	22 4
+
+#-----------------------------------------------------
+# PPLUS, NPLUS
+#-----------------------------------------------------
+
+#ifdef HRPOLY1K
+ layer RESDEF
+	bloat-or hires,mvhires * 280 poly 0
+	grow 200
+	shrink 200
+ 	calma 110 5
+
+ # hires requires PPLUS around terminals
+ templayer HRTERM
+	bloat-all hires,mvhires *poly
+	and-not hires,mvhires
+
+ layer SBLK
+	bloat-or hires,mvhires * 280 poly 100
+ 	calma 	49 0
+#endif (HRPOLY1K)
+
+ # rnps requires NPLUS
+ # rnp  requires NPLUS
+ # rnd  requires NPLUS
+
+ layer NPLUS
+ 	bloat-all rnps *poly
+ 	bloat-all rnp  *poly
+ 	bloat-all rnd  *ndiff
+	grow 200
+	grow 200
+	shrink 200
+	calma   32 0
+
+ # standard generation of NPLUS
+
+ templayer nwell_shrink nwell
+	shrink 430
+
+ templayer shortntap *nsd,*mvnsd
+	and-not dnwell
+	and-not nwell_shrink
+	grow 160
+
+ templayer shortdntap dnwell
+	and pwell
+	grow 430
+        and *nsd,*mvnsd
+	grow 160
+
+ layer NPLUS
+        bloat-or *ndif,*ndiode,*nndiode,ndiffres,*mvndif,*mvndiode,*mvnndiode,mvndiffres * 20 allpactivenonfet 0
+        bloat-or *nsd,*mvnsd * 20 allpactivenonfet 0
+	bloat-or allnfets,var,mvvar * 230
+	or shortntap,shortdntap
+	grow 	200 
+	shrink 200
+	calma   32 0
+
+ # rpps requires PPLUS
+ # rpp  requires PPLUS
+ # rpd  requires PPLUS
+
+ layer PPLUS
+ 	bloat-all rpps *poly
+ 	bloat-all rpp  *poly
+ 	bloat-all rpd  *pdiff
+	grow 200
+	grow 200
+	shrink 200
+	calma   31 0
+
+ # standard generation of PPLUS, including hires resistors
+
+ templayer shortptap nwell
+	and-not dnwell
+	grow 430
+	and *psd,*mvpsd
+	grow 160
+
+ templayer pwell_shrink pwell
+	and dnwell
+	shrink 430
+
+ templayer shortdptap *psd,*mvpsd
+	and dnwell
+	and-not pwell_shrink
+	grow 160
+
+ layer PPLUS
+#ifdef HRPOLY1K
+	or HRTERM
+	grow 200
+	and-not RESDEF
+#endif (HRPOLY1K)
+        bloat-or  *pdif,*pdiode,pdiffres,pfet,*mvpdif,*mvpdiode,mvpdiffres,mvpfet * 160 allnactivenonfet 0
+        bloat-or *psd,*mvpsd * 20 allnactivenonfet 0
+	bloat-or allpfets * 230
+	or shortptap,shortdptap
+	grow	200
+	shrink	200
+	calma	31 0
+ 
+ templayer varactive
+ bloat-all var *nsd
+
+#-----------------------------------------------------
+# DUALGATE (thickox)
+#-----------------------------------------------------
+
+ layer DUALGATE allfetsmv
+	bloat-all mvhires *poly
+	# Rule DV.8 (DUALGATE around poly)
+	grow 400
+	# Rule DV.6 (DUALGATE around diff, LV substrate tap excepted)
+	bloat-or allndiffmv * 240 *psd 0
+	bloat-or allpdiffmv * 240
+	grow 219
+	shrink 219
+	calma 55 0
+
+ # DUALGATE completely covers deep nwell
+ layer DUALGATE
+	bloat-all alldiffmv dnwell
+	grow 500
+	grow 219
+	shrink 219
+	calma 55 0
+
+#-----------------------------------------------------
+# NAT
+#-----------------------------------------------------
+
+ layer  NAT	
+	bloat-all *nndiode,nnfet *ndiff
+	bloat-all *mvnndiode,mvnnfet *mvndiff
+	grow 260
+	grow 309
+	shrink 309
+	calma 5 0
+
+#-----------------------------------------------------
+# POLY
+#-----------------------------------------------------
+ layer POLY 	allpoly
+	close	224000
+ 	labels 	allpoly noport
+ 	calma 	30 0
+
+ layer POLYTXT
+	labels  allpoly port
+	calma	30 10
+
+ layer POLYFILL	fillpoly
+	labels	fillpoly
+	calma	30 4
+
+#-----------------------------------------------------
+# CONT
+#-----------------------------------------------------
+# NOTE:  Contact arrays defined at 200 spacing for large array rule (4x4),
+# otherwise spacing is 180
+
+ layer contlarge allcont
+	shrink 615
+	grow 615
+
+ layer CONT allcont
+	and-not contlarge
+ 	squares-grid 5 220 250
+ 	calma 	33 0
+
+ layer CONT allcont
+	and contlarge
+ 	squares-grid 5 220 280
+ 	calma 	33 0
+
+#-----------------------------------------------------
+# MET1
+#-----------------------------------------------------
+ layer MET1 	allm1
+ 	labels 	allm1 noport
+ 	calma 	34 0
+
+ layer MET1TXT
+	labels	allm1 port
+	calma 	34 10
+
+ layer M1BLOCK  obsm1
+	labels	obsm1
+	calma	34 5
+
+ layer M1FILL   fillm1
+	labels	fillm1
+	calma	34 4
+
+#-----------------------------------------------------
+# VIA1
+#-----------------------------------------------------
+ templayer via1large via1
+	shrink 915
+	grow 915
+
+ layer VIA1 	via1
+	and-not via1large
+ 	squares-grid 0 260 260
+ 	calma 	35 0
+
+ layer VIA1 	via1
+	and via1large
+ 	squares-grid 0 260 360
+ 	calma 	35 0
+
+#-----------------------------------------------------
+# MET2
+#-----------------------------------------------------
+ layer MET2 	allm2
+ 	labels 	allm2 noport
+ 	calma 	36 0
+
+ layer MET2TXT
+	labels	allm2 port
+	calma	36 10
+
+ layer M2BLOCK  obsm2
+	labels	obsm2
+	calma	36 5
+
+ layer M2FILL   fillm2
+	labels	fillm2
+	calma	36 4
+
+#ifdef METALS3 || METALA4 || METALS5 || METALS6
+#-----------------------------------------------------
+# VIA2
+#-----------------------------------------------------
+ templayer via2large via2
+	shrink 915
+	grow 915
+
+ layer VIA2 	via2
+	and-not via2large
+ 	squares-grid 10 260 260
+ 	calma 	38 0
+
+ layer VIA2 	via2
+	and via2large
+ 	squares-grid 10 260 360
+ 	calma 	38 0
+
+#ifdef MIM && METALS3
+ layer VIA2 	mimcapc
+ 	squares-grid 10 260 500
+ 	calma 	38 0
+
+#endif (MIM && METALS3)
+
+#-----------------------------------------------------
+# MET3
+#-----------------------------------------------------
+ layer MET3 	allm3
+ 	labels 	allm3 noport
+ 	calma 	42 0
+
+ layer MET3TXT
+	labels	allm3 port
+	calma	42 10
+
+ layer M3BLOCK  obsm3
+	labels	obsm3
+	calma	42 5
+
+ layer M3FILL   fillm3
+	labels	fillm3
+	calma	42 4
+#endif (METALS3 || METALA4 || METALS5 || METALS6)
+
+#ifdef METALS4 || METALS5 || METALS6
+#-----------------------------------------------------
+# VIA3
+#-----------------------------------------------------
+ templayer via3large via3
+	shrink 915
+	grow 915
+
+ layer VIA3	via3
+	and-not via3large
+ 	squares-grid 10 260 260
+ 	calma 	40 0
+
+ layer VIA3	via3
+	and via3large
+ 	squares-grid 10 260 360
+ 	calma 	40 0
+
+#ifdef MIM && METALS4
+ layer VIA3 	mimcapc
+ 	squares-grid 10 260 500
+ 	calma 	40 0
+
+#endif (MIM && METALS4)
+
+#-----------------------------------------------------
+# MET4
+#-----------------------------------------------------
+ layer MET4 	allm4
+ 	labels 	allm4 noport
+ 	calma 	46 0
+
+ layer MET4TXT
+	labels	allm4 port
+	calma	46 10
+
+ layer M4BLOCK  obsm4
+	labels	obsm4
+	calma	46 5
+
+ layer M4FILL   fillm4
+	labels	fillm4
+	calma	46 4
+
+#endif (METALS4 || METALS5 || METALS6)
+
+#ifdef METALS5 || METALS6
+#-----------------------------------------------------
+# VIA4
+#-----------------------------------------------------
+ templayer via4large via4
+	shrink 915
+	grow 915
+
+ layer VIA4	via4
+	and-not via4large
+ 	squares-grid 10 260 260
+ 	calma 	41 0
+
+ layer VIA4	via4
+	and via4large
+ 	squares-grid 10 260 360
+ 	calma 	41 0
+
+#ifdef (MIM && METALS5)
+ layer VIA4 	mimcapc
+ 	squares-grid 10 260 500
+ 	calma 	41 0
+
+#endif (MIM && METALS5)
+
+#-----------------------------------------------------
+# MET5
+#-----------------------------------------------------
+ layer MET5 	allm5
+ 	labels 	allm5 noport
+ 	calma 	81 0
+
+ layer MET5TXT
+	labels	allm5 port
+	calma	81 10
+
+ layer M5BLOCK  obsm5
+	labels	obsm5
+	calma	81 5
+
+ layer M5FILL   fillm5
+	labels	fillm5
+	calma	81 4
+
+#endif (METALS5 || METALS6)
+
+#ifdef METALS6
+#-----------------------------------------------------
+# VIATP
+#-----------------------------------------------------
+ templayer viatplarge viatp
+	shrink 975
+	grow 975
+
+ layer VIATP	viatp
+	and-not viatplarge
+ 	squares-grid 10 260 260
+ 	calma 	129 0
+
+ layer VIATP	viatp
+	and viatplarge
+ 	squares-grid 10 160 360
+ 	calma 	129 0
+ 
+#ifdef MIM
+ layer VIATP 	mimcapc
+ 	squares-grid 10 260 500
+ 	calma 	129 0
+
+#endif (MIM)
+
+#-----------------------------------------------------
+# METTP
+#-----------------------------------------------------
+
+ layer METTP 	allmtp
+ 	labels 	allmtp noport
+ 	calma 	53 0
+
+ layer	METTPTXT
+	labels	allmtp port
+	calma	53 10
+
+ layer MTPBLOCK  obsmtp
+	labels	obsmtp
+	calma	53 5
+
+ layer MTPFILL  fillmtp
+	labels	fillmtp
+	calma	53 4
+
+#endif (METALS6)
+
+#-----------------------------------------------------
+# GLASS
+#-----------------------------------------------------
+ layer GLASS 	glass
+ 	calma 	37 0
+
+#-----------------------------------------------------
+# PRBNDRY
+#-----------------------------------------------------
+ layer PRBNDRY
+	boundary
+	calma 0 0 
+
+#ifdef MIM
+#-----------------------------------------------------
+# CAPM
+#-----------------------------------------------------
+# NOTE:  MiM bottom plate handled by alias "allm*" when MIM defined
+
+ layer CAPM 	*mimcap
+ 	labels 	mimcap
+ 	calma 	75 0
+
+ layer CAPDEF	*mimcap
+	grow 200
+	calma 	117 5
+#endif (MIM)
+
+#-----------------------------------------------------
+# SBLK
+#-----------------------------------------------------
+
+ layer SBLK
+ 	bloat-or allsblkdev * 0 space/a 220
+ 	grow 	215
+ 	shrink 	215
+ 	calma 	49 0
+
+ # sblk from rdn/rdp of esd fet 
+ # assume that the diff in only 0.05um
+ layer SBLK rdp
+	grow 100
+	and pfet
+	grow 400
+ 	calma 	49 0
+
+ layer SBLK rdn
+	grow 250
+	and nfet
+	grow 400
+ 	calma 	49 0
+	
+#-----------------------------------------------------
+# RESDEF MARK
+#-----------------------------------------------------
+ layer RESDEF allres
+ calma 110 5
+
+#-----------------------------------------------------
+# METAL RESISTOR IDs
+#-----------------------------------------------------
+ layer MET1RES rm1
+ calma 110 11
+
+ layer MET2RES rm2
+ calma 110 12
+
+#ifdef METALS3 || METALS4 || METALS5 || METALS6
+ layer MET3RES rm3
+ calma 110 13
+#endif (METALS3 || METALS4 || METALS5 || METALS6)
+
+#ifdef METALS4 || METALS5 || METALS6
+ layer MET4RES rm4
+ calma 110 14
+#endif (METALS4 || METALS5 || METALS6)
+
+#ifdef METALS5 || METALS6
+ layer MET5RES rm5
+ calma 110 15
+#endif (METALS5 || METALS6)
+
+#ifdef METALS6
+ layer METTPRES rmtp
+ calma 110 16
+#endif (METALS6)
+
+#-----------------------------------------------------
+# DIODE MARK
+#-----------------------------------------------------
+ layer DIODE  alldiode
+ calma 115 5
+
+#-----------------------------------------------------
+# MOSCAP MARK
+#-----------------------------------------------------
+ layer MOSCAP var,mvvar
+ calma 166 5
+
+#ifdef HRPOLY1K
+#-----------------------------------------------------
+# HRES
+#-----------------------------------------------------
+ layer HRES
+ bloat-all hires,mvhires *poly
+ grow 400
+ calma 	62 0
+#endif (HRPOLY1K)
+
+#------------------------------------------------------------------------
+# FILLBLOCK (NOTE: two layers define this on active, then poly & metal)
+#------------------------------------------------------------------------
+ layer FILLOBS fillblock
+ 	calma 	111 5
+
+ layer FILLOBS2 fillblock
+ 	calma 	152 5
+
+#----------------------------------------------------------
+style metfill
+#----------------------------------------------------------
+# This section used for metal filling output by a sequence
+# of cif paint commands
+
+ scalefactor 50 nanometers
+ options calma-permissive-labels
+ gridlimit 5
+
+#-----------------------------------------------------
+# Fill layer geometry
+#-----------------------------------------------------
+
+ templayer fill_geometry_off0
+	bbox top
+	slots	0 2000 1000 0 2000 1000 1000 0
+
+ templayer fill_geometry_off1
+	bbox top
+	slots	0 2000 1000 0 2000 1000 1000 660
+
+ templayer fill_geometry_off2
+	bbox top
+	slots	0 2000 1000 0 2000 1000 1000 1320
+
+#ifdef THICKMET3P0
+ templayer  fill_geometry_thick
+	bbox    top
+	slots	0 6000 2000 0 6000 2000 3000 2000
+#endif (THICKMET3P0)
+
+#-----------------------------------------------------
+# Obstruction geometry
+#-----------------------------------------------------
+
+ templayer 	obstruct_diff alldiff,filldiff,obsactive
+	grow 	2010
+	shrink 	500
+	grow 	500
+
+ templayer 	obstruct_poly allpoly,fillpoly
+	grow 	2010
+	shrink 	500
+	grow 	500
+
+ templayer 	obstruct_m1 allm1,allpad,fillm1,obsm1
+	grow 	2010
+	shrink 	500
+	grow 	500
+
+ templayer 	obstruct_m2 allm2,allpad,fillm2,obsm2
+	grow 	2010
+	shrink 	500
+	grow 	500
+
+#ifdef METALS3 || METALS4 || METALS5 || METALS6
+ templayer 	obstruct_m3 allm3,allpad,fillm3,obsm3
+	grow 	2010
+	shrink 	500
+	grow 	500
+#endif (METALS3 || METALS4 || METALS5 || METALS6)
+
+#ifdef METALS4 || METALS5 || METALS6
+ templayer 	obstruct_m4 allm4,allpad,fillm4,obsm4
+	grow 	2010
+	shrink 	500
+	grow 	500
+#endif (METALS4 || METALS5 || METALS6)
+
+#ifdef METALS5 || METALS6
+ templayer 	obstruct_m5 allm5,allpad,fillm5,obsm5
+	grow 	2010
+	shrink 	500
+	grow 	500
+#endif (METALS5 || METALS6)
+
+#ifdef METALS6
+#ifdef THICKMET3P0
+ templayer 	obstruct_mtp allmtp,allpad,fillmtp,obsmtp
+	grow 	2010
+	shrink 	500
+	grow 	500
+
+#elseif defined(THICKMET0P9 || THICKMET1P1)
+ templayer 	obstruct_mtp allmtp,allpad,fillmtp,obsmtp
+	grow 	2010
+	shrink 	500
+	grow 	500
+
+#else (!(THICKMET3P0 || THICKMET1P1 || THICKMET0P9 )
+ templayer 	obstruct_mtp allmtp,allpad,fillmtp,obsmtp
+	grow 	2010
+	shrink 	500
+	grow 	500
+#endif
+#endif (METALS6)
+
+#-----------------------------------------------------
+# DIFF FILL
+#-----------------------------------------------------
+ layer difffill fill_geometry_off0
+	shrink 995
+	grow 995
+
+#-----------------------------------------------------
+# POLY FILL
+#-----------------------------------------------------
+ layer polyfill fill_geometry_off1
+	and-not obstruct_m1
+	shrink 995
+	grow 995
+
+#-----------------------------------------------------
+# MET1 FILL
+#-----------------------------------------------------
+ layer met1fill fill_geometry_off2
+	and-not obstruct_poly
+	and-not obstruct_m1
+	and-not obstruct_m2
+	shrink 995
+	grow 995
+
+#-----------------------------------------------------
+# MET2 FILL
+#-----------------------------------------------------
+ layer met2fill fill_geometry_off0
+	and-not obstruct_m1
+	and-not obstruct_m2
+	shrink 995
+	grow 995
+
+#ifdef METALS3 || METALS4 || METALS5 || METALS6
+#-----------------------------------------------------
+# MET3 FILL
+#-----------------------------------------------------
+ layer met3fill fill_geometry_off1
+	and-not obstruct_m2
+	and-not obstruct_m3
+	shrink 995
+	grow 995
+#endif (METALS3 || METALS4 || METALS5 || METALS6)
+
+#ifdef METALS4 || METALS5 || METALS6
+#-----------------------------------------------------
+# MET4 FILL
+#-----------------------------------------------------
+ layer met4fill fill_geometry_off2
+	and-not obstruct_m3
+	and-not obstruct_m4
+	shrink 995
+	grow 995
+#endif (METALS4 || METALS5 || METALS6)
+
+#ifdef METALS5 || METALS6
+#-----------------------------------------------------
+# MET5 FILL
+#-----------------------------------------------------
+ layer met5fill fill_geometry_off0
+	and-not obstruct_m4
+	and-not obstruct_m5
+	shrink 995
+	grow 995
+#endif (METALS5 || METALS6)
+
+#ifdef METALS6
+#-----------------------------------------------------
+# METTP FILL
+#-----------------------------------------------------
+ layer mettpfill fill_geometry_off1
+	and-not obstruct_m5
+	and-not obstruct_mtp
+	shrink 995
+	grow 995
+#endif (METALS6)
+
+#-----------------------------------------------------------------------
+style drc
+#-----------------------------------------------------------------------
+# NOTE:  this style is used for DRC only, not for GDS output
+#-----------------------------------------------------------------------
+
+ scalefactor 50 nanometers
+ options calma-permissive-labels
+ gridlimit 5
+
+ # Check for MV and LV devices in the same dnwell
+ templayer mv_dnwell
+ bloat-all alldiffmv dnwell
+
+ templayer bad_dnwell
+ bloat-all alldifflv dnwell
+ and mv_dnwell
+
+ # Check pwell in dnwell
+ templayer pwell_in_dnwell pwell
+ and dnwell
+ and-not mv_dnwell
+
+ templayer mvpwell_in_dnwell pwell
+ and mv_dnwell
+
+ # Check for MV and LV devices in the same nwell
+ templayer mv_nwell
+ bloat-all alldiffmv nwell
+
+ templayer bad_nwell
+ bloat-all alldifflv nwell
+ and mv_nwell
+
+ # Check for nwell resistor in deep nwell
+ templayer bad_rnw rnw
+ and dnwell
+
+ # Define HRES layer for DRC checks
+ templayer res_hres
+ bloat-all mvhires,hires *poly
+
+ # Check for contact at correct position for HIRES, LRES, PRES resistors
+ templayer res_cont res_hres
+ bloat-all rnp,rpp *poly
+ and pc
+ squares-grid 5 220 250
+
+ templayer res_cont_space_min mvhires,hires
+ # SBLK larger than defined resistor by 0.1um
+ grow 100
+ # SBLK = resistor for rnp and rpp
+ or rnp,rpp
+ # SBLK spacing to contact
+ grow 220
+ and res_cont
+ # If anything remains, contact is too close.
+
+ templayer res_cont_space_max mvhires,hires
+ # SBLK larger than defined resistor by 0.1um
+ grow 100
+ # SBLK = resistor for rnp and rpp
+ or rnp,rpp
+ # SBLK spacing to contact
+ grow 220
+ # size of poly contact
+ grow 220
+ and res_cont
+
+ templayer res_no_cont res_cont
+ and-not res_cont_space_max
+ # If anything remains, contact is too far away
+
+ # Check for HRES to poly and diffusion spacing
+ templayer res_hres_grow res_hres
+ grow 700
+
+ templayer res_diff_space res_hres_grow
+ and alldiff
+ # If anything remains, HRES is too close to diffusion
+
+ templayer res_poly_space res_hres_grow
+ and-not res_hres
+ and allpoly
+ # If anything remains, HRES is too close to poly
+
+ # Check for MiM cap bottom plate to other metal spacing rule (< 1.2um)
+ templayer mim_bottom_plate
+#ifdef METALS3
+ bloat-all *mim *m2
+#endif
+#ifdef METALS4
+ bloat-all *mim *m3
+#endif
+#ifdef METALS5
+ bloat-all *mim *m4
+#endif
+#ifdef METALS6
+ bloat-all *mim *m5
+#endif
+
+ templayer mim_bottom_plate_space mim_bottom_plate
+ grow 1200
+#ifdef METALS3
+ and m2
+#endif
+#ifdef METALS4
+ and m3
+#endif
+#ifdef METALS5
+ and m4
+#endif
+#ifdef METALS6
+ and m5
+#endif
+ and-not mim_bottom_plate
+ # If anything remains, bottom plate is too close
+
+ # Check for MiM cap bottom plate surrounds contact (by 0.4um)
+#ifdef METALS3
+ templayer mim_bot_cont_surround via2
+#endif
+#ifdef METALS4
+ templayer mim_bot_cont_surround via3
+#endif
+#ifdef METALS5
+ templayer mim_bot_cont_surround via4
+#endif
+#ifdef METALS6
+ templayer mim_bot_cont_surround viamt
+#endif
+ and mim_bottom_plate
+ squares-grid 10 260 500
+ grow 400
+ and-not mim_bottom_plate
+ # If anything remains, not enough surround
+
+end
+
+#-----------------------------------------------------------------------
+cifinput
+#-----------------------------------------------------------------------
+
+# NOTE:  All values in this section MUST be multiples of 25 
+# or else magic will scale below the allowed layout grid size
+
+style  import
+ scalefactor 50 nanometers
+ gridlimit 5
+
+ options ignore-unknown-layer-labels options no-reconnect-labels 
+
+ ignore BJTDEF
+ ignore MOSCAP
+ ignore SRAMDEF
+ ignore FET5VDEF
+ ignore CAPDEF
+
+ layer pwell PWELL
+ labels PWELL
+
+ layer nwell NWELL
+ labels NWELL
+
+ layer dnwell DNWELL
+ labels DNWELL
+
+ templayer ndiffarea DIFF
+ and-not POLY
+ and-not NWELL
+ and-not PPLUS
+ and-not SBLK
+ and-not DUALGATE
+ and NPLUS
+ copyup ndifcheck
+
+ layer ndiff ndiffarea
+ labels DIFF
+
+ layer filldiff DIFFFILL
+ labels DIFFFILL
+
+ # Copy ndiff areas up for contact checks
+ templayer xndifcheck ndifcheck
+ copyup ndifcheck
+
+ templayer mvndiffarea DIFF
+ and-not POLY
+ and-not NWELL
+ and-not PPLUS
+ and-not SBLK
+ and DUALGATE
+ and NPLUS
+ copyup mvndifcheck
+
+ layer mvndiff mvndiffarea
+ labels DIFF
+
+ # Copy mvndiff areas up for contact checks
+ templayer mvxndifcheck mvndifcheck
+ copyup mvndifcheck
+
+ layer ndiode DIFF
+ and NPLUS
+ and DIODE
+ and-not NWELL
+ and-not POLY
+ and-not PPLUS
+ and-not DUALGATE
+ and-not NAT
+ labels DIFF
+
+ layer nndiode DIFF
+ and NPLUS
+ and DIODE
+ and-not NWELL
+ and-not POLY
+ and-not PPLUS
+ and-not DUALGATE
+ and NAT
+ labels DIFF
+
+ templayer ndiodearea DIODE
+ and NPLUS
+ and-not NWELL
+ and-not DUALGATE
+ copyup DIODE,NPLUS
+
+ layer ndiffres DIFF
+ and-not POLY
+ and SBLK
+ and NPLUS
+ and-not DUALGATE
+ labels DIFF
+
+ templayer pdiffarea DIFF
+ and-not POLY
+ and NWELL
+ and-not NPLUS
+ and-not SBLK
+ and-not DIODE
+ and PPLUS
+ and-not DUALGATE
+ copyup pdifcheck
+
+ layer pdiff pdiffarea
+ labels DIFF
+
+ layer mvndiode DIFF
+ and NPLUS
+ and DIODE
+ and-not POLY
+ and-not PPLUS
+ and DUALGATE
+ and-not NAT
+ labels DIFF
+
+ layer mvnndiode DIFF
+ and NPLUS
+ and DIODE
+ and-not POLY
+ and-not PPLUS
+ and DUALGATE
+ and NAT
+ labels DIFF
+
+ templayer mvndiodearea DIODE
+ and NPLUS
+ and-not NWELL
+ and DUALGATE
+ copyup DIODE,NPLUS
+
+ layer mvndiffres DIFF
+ and-not POLY
+ and SBLK
+ and NPLUS
+ and DUALGATE
+ labels DIFF
+
+ templayer mvpdiffarea DIFF
+ and-not POLY
+ and NWELL
+ and-not NPLUS
+ and-not SBLK
+ and-not DIODE
+ and DUALGATE
+ and PPLUS
+ copyup mvpdifcheck
+
+ layer mvpdiff mvpdiffarea
+ labels DIFF
+
+ # Copy pdiff areas up for contact checks
+ templayer xpdifcheck pdifcheck
+ copyup pdifcheck
+
+ layer pdiode DIFF
+ and PPLUS
+ and-not POLY
+ and-not NPLUS
+ and-not DUALGATE
+ and DIODE
+ labels DIFF
+
+ templayer pdiodearea DIODE
+ and PPLUS
+ copyup DIODE,PPLUS
+
+ # Define pfet areas as known pdiff,
+ # regardless of the presence of a
+ # well.
+
+ templayer pfetarea DIFF
+ and-not NPLUS
+ and-not DUALGATE
+ and POLY
+
+ layer pfet pfetarea
+ labels DIFF
+
+ templayer pfetexpand pfetarea
+ grow 530
+
+ # Always force nwell under pfet
+ layer nwell pfetarea
+ grow 310
+
+ # Copy mvpdiff areas up for contact checks
+ templayer mvxpdifcheck mvpdifcheck
+ copyup mvpdifcheck
+
+ layer mvpdiode DIFF
+ and PPLUS
+ and-not POLY
+ and-not NPLUS
+ and-not RESDEF
+ and DUALGATE
+ and DIODE
+ labels DIFF
+
+ templayer mvpdiodearea DIODE
+ and PPLUS
+ copyup DIODE,PPLUS
+
+ # Define pfet areas as known pdiff,
+ # regardless of the presence of a
+ # well.
+
+ templayer mvpfetarea DIFF
+ and DUALGATE
+ and-not NPLUS
+ and POLY
+
+ layer mvpfet mvpfetarea
+ labels DIFF
+
+ templayer mvpfetexpand mvpfetarea
+ grow 530
+
+ layer pdiff DIFF
+ and-not DUALGATE
+ and-not NPLUS
+ and-not POLY
+ and NWELL
+ and pfetexpand
+ labels DIFF
+
+ layer pdiffres DIFF
+ and-not POLY
+ and PPLUS
+ and NWELL
+ and SBLK
+ labels DIFF
+
+ layer nfet DIFF
+ and POLY
+ and-not PPLUS
+ and-not DUALGATE
+ and-not NWELL
+ and NPLUS
+ and-not NAT
+ labels DIFF
+
+ layer nnfet DIFF
+ and POLY
+ and-not PPLUS
+ and-not DUALGATE
+ and-not NWELL
+ and NPLUS
+ and NAT
+ labels DIFF
+
+
+ templayer nsdarea DIFF
+ and NPLUS
+ and NWELL
+ and-not POLY
+ and-not PPLUS
+ and-not DUALGATE
+
+ layer nsd nsdarea
+ labels DIFF
+
+ templayer nsdexpand nsdarea
+ grow 500
+
+ # Copy nsub areas up for contact checks
+ templayer xnsubcheck nsubcheck
+ copyup nsubcheck
+
+ templayer psdarea DIFF
+ and PPLUS
+ and-not DUALGATE
+ and-not NWELL
+ and-not POLY
+ and-not NPLUS
+ and-not pfetexpand
+ copyup psubcheck
+
+ layer psd psdarea
+ labels DIFF
+
+ templayer psdexpand psdarea
+ grow 500
+
+ layer mvpdiff DIFF
+ and-not NPLUS
+ and-not POLY
+ and NWELL
+ and DUALGATE
+ and mvpfetexpand
+ labels DIFF
+
+ layer mvpdiffres DIFF
+ and-not POLY
+ and PPLUS
+ and SBLK
+ and DUALGATE
+ labels DIFF
+
+ layer mvnfet DIFF
+ and POLY
+ and-not PPLUS
+ and NPLUS
+ and-not NAT
+ and-not NWELL
+ and DUALGATE
+ labels DIFF
+
+ layer mvnnfet DIFF
+ and POLY
+ and-not PPLUS
+ and NPLUS
+ and NAT
+ and-not NWELL
+ and DUALGATE
+ labels DIFF
+
+ templayer mvnsdarea DIFF
+ and NPLUS
+ and-not POLY
+ and-not PPLUS
+ and NWELL
+ and DUALGATE
+ copyup mvnsubcheck
+
+ layer mvnsd mvnsdarea
+ labels DIFF
+
+ templayer mvnsdexpand mvnsdarea
+ grow 500
+
+ # Copy nsub areas up for contact checks
+ templayer mvxnsubcheck mvnsubcheck
+ copyup mvnsubcheck
+
+ templayer mvpsdarea DIFF
+ and PPLUS
+ and-not NWELL
+ and-not POLY
+ and-not NPLUS
+ and DUALGATE
+ and-not mvpfetexpand
+ copyup mvpsubcheck
+
+ layer mvpsd mvpsdarea
+ labels DIFF
+
+ templayer mvpsdexpand mvpsdarea
+ grow 500
+
+ # Copy psub areas up for contact checks
+ templayer xpsubcheck psubcheck
+ copyup psubcheck
+
+ templayer mvxpsubcheck mvpsubcheck
+ copyup mvpsubcheck
+
+ layer psd DIFF
+ and-not PPLUS
+ and-not NPLUS
+ and-not POLY
+ and-not DUALGATE
+ and-not pfetexpand
+ and psdexpand
+
+ layer nsd DIFF
+ and-not PPLUS
+ and-not NPLUS
+ and-not POLY
+ and NWELL
+ and-not DUALGATE
+ and nsdexpand
+
+ layer mvpsd DIFF
+ and-not PPLUS
+ and-not NPLUS
+ and-not POLY
+ and-not NWELL
+ and DUALGATE
+ and-not mvpfetexpand
+ and mvpsdexpand
+
+ layer mvnsd DIFF
+ and-not PPLUS
+ and-not NPLUS
+ and-not POLY
+ and NWELL
+ and DUALGATE
+ and mvnsdexpand
+
+ templayer polyarea POLY
+ and-not DIFF
+ and-not SBLK
+#ifdef HRPOLY1K
+ and-not HRES
+#endif (HRPOLY1K)
+ copyup polycheck
+
+ layer poly polyarea,POLYTXT
+ and-not RESDEF
+ labels POLY
+ labels POLYTXT text
+
+ layer fillpoly POLYFILL
+ labels POLYFILL
+
+ # Copy poly areas up for contact checks
+ templayer xpolycheck polycheck
+ copyup polycheck
+
+ layer rpps POLY
+ and-not SBLK
+ and PPLUS
+ and RESDEF
+ labels POLY
+
+ layer rnps POLY
+ and-not SBLK
+ and NPLUS
+ and RESDEF
+ labels POLY
+
+ layer rpp POLY
+ and SBLK
+ and PPLUS
+#ifdef HRPOLY1K
+ and-not HRES
+#endif (HRPOLY1K)
+ and RESDEF
+ labels POLY
+
+ # POLY + SBLK without RESDEF may be a salicide-blocked transistor.
+ # The SBLK will be regenerated on GDS output and the poly should be
+ # treated as regular poly.
+ layer poly POLY
+ and-not DIFF
+ and SBLK
+ and-not RESDEF
+ labels POLY
+
+ layer rnp POLY
+ and SBLK
+ and NPLUS
+ and RESDEF
+#ifdef HRPOLY1K
+ and-not HRES
+#endif (HRPOLY1K)
+ labels POLY
+
+#ifdef HRPOLY1K
+ layer hires POLY
+ and SBLK
+ and HRES
+ and RESDEF
+ and-not DUALGATE
+ labels POLY
+
+ layer mvhires POLY
+ and SBLK
+ and HRES
+ and RESDEF
+ and DUALGATE
+ labels POLY
+
+ # We define poly under HRES but not under SBLK to be plain poly
+ layer poly POLY
+ and HRES
+ and-not SBLK
+ and-not RESDEF
+#endif (HRPOLY1K)
+
+ layer ndc CONT
+ and DIFF
+ and NPLUS
+ and-not NWELL
+ and MET1
+ and-not DUALGATE
+ and-not DIODE
+ grow 145
+ shrink 140
+
+ layer nsc CONT
+ and DIFF
+ and NPLUS
+ and NWELL
+ and MET1
+ and-not DUALGATE
+ and-not DIODE
+ grow 145
+ shrink 140
+
+ layer pdc CONT
+ and DIFF
+ and PPLUS
+ and NWELL
+ and MET1
+ and-not DUALGATE
+ and-not DIODE
+ grow 145
+ shrink 140
+
+ layer pdc CONT
+ and DIFF
+ and PPLUS
+ and MET1
+ and-not DUALGATE
+ and-not DIODE
+ and pfetexpand
+ grow 145
+ shrink 140
+
+ layer psc CONT
+ and DIFF
+ and PPLUS
+ and-not NWELL
+ and MET1
+ and-not DUALGATE
+ and-not DIODE
+ and-not pfetexpand
+ grow 145
+ shrink 140
+
+ layer pc CONT
+ and POLY
+ and-not DIFF
+ and MET1
+ grow 145
+ shrink 140
+
+ layer ndic CONT
+ and DIFF
+ and NPLUS
+ and DIODE
+ and-not POLY
+ and-not PPLUS
+ and-not DUALGATE
+ and-not NAT
+ grow 145
+ shrink 140
+
+ layer nndic CONT
+ and DIFF
+ and NPLUS
+ and DIODE
+ and-not POLY
+ and-not PPLUS
+ and-not DUALGATE
+ and NAT
+ grow 145
+ shrink 140
+
+ layer pdic CONT
+ and DIFF
+ and PPLUS
+ and DIODE
+ and-not POLY
+ and-not NPLUS
+ and-not DUALGATE
+ grow 145
+ shrink 140
+
+ layer mvndc CONT
+ and DIFF
+ and NPLUS
+ and-not NWELL
+ and MET1
+ and DUALGATE
+ and-not DIODE
+ grow 145
+ shrink 140
+
+ layer mvnsc CONT
+ and DIFF
+ and NPLUS
+ and MET1
+ and DUALGATE
+ and NWELL
+ and-not DIODE
+ grow 145
+ shrink 140
+
+ layer mvpdc CONT
+ and DIFF
+ and PPLUS
+ and MET1
+ and DUALGATE
+ and NWELL
+ and-not DIODE
+ grow 145
+ shrink 140
+
+ layer mvpdc CONT
+ and DIFF
+ and PPLUS
+ and MET1
+ and DUALGATE
+ and-not DIODE
+ and mvpfetexpand
+ grow 145
+ shrink 140
+
+ layer mvpsc CONT
+ and DIFF
+ and PPLUS
+ and-not NWELL
+ and MET1
+ and DUALGATE
+ and-not DIODE
+ and-not mvpfetexpand
+ grow 145
+ shrink 140
+
+ layer mvndic CONT
+ and DIFF
+ and NPLUS
+ and DIODE
+ and-not POLY
+ and-not PPLUS
+ and DUALGATE
+ and-not NAT
+ grow 145
+ shrink 140
+
+ layer mvnndic CONT
+ and DIFF
+ and NPLUS
+ and DIODE
+ and-not POLY
+ and-not PPLUS
+ and DUALGATE
+ and NAT
+ grow 145
+ shrink 140
+
+ layer mvpdic CONT
+ and DIFF
+ and PPLUS
+ and DIODE
+ and-not POLY
+ and-not NPLUS
+ and DUALGATE
+ grow 145
+ shrink 140
+
+ layer rm1 MET1
+ and RESDEF
+ and MET1RES
+
+ layer m1 MET1,MET1TXT
+ and-not MET1RES
+ labels MET1
+ labels MET1TXT port
+
+ layer obsm1 M1BLOCK
+ labels M1BLOCK
+
+ layer fillm1 M1FILL
+ labels M1FILL
+
+ layer m2c VIA1
+ grow 130
+ shrink 130
+
+ layer rm2 MET2
+ and RESDEF
+ and MET2RES
+
+ layer m2 MET2,MET2TXT
+ and-not MET2RES
+ labels MET2
+ labels MET2TXT port
+
+ layer obsm2 M2BLOCK
+ labels M2BLOCK
+
+ layer fillm2 M2FILL
+ labels M2FILL
+
+#ifdef METALS3 || METALS4 || METALS5 || METALS6
+ layer rm3 MET3
+ and RESDEF
+ and MET3RES
+
+#ifdef MIM
+ templayer mimarea CAPDEF
+ and MET2
+#endif
+
+ layer m3 MET3,MET3TXT
+ and-not MET3RES
+ labels MET3
+ labels MET3TXT port
+
+ layer obsm3 M3BLOCK
+ labels M3BLOCK
+
+ layer fillm3 M3FILL
+ labels M3FILL
+
+ layer m3c VIA2
+#ifdef METALS4 && MIM
+ and-not CAPM
+ and-not mimarea
+#endif (METALS4 && MIM)
+ grow 140
+ shrink 130
+
+#ifdef MIM
+ layer mimcc VIA2
+ and MET3
+ and CAPM
+ and CAPDEF
+ grow 90
+ grow 250
+ shrink 250
+#endif (MIM)
+#endif (METALS3 || METALS4 || METALS5 || METALS6)
+
+#ifdef METALS4 || METALS5 || METALS6
+ layer rm4 MET4
+ and RESDEF
+ and MET4RES
+
+#ifdef MIM
+ templayer mimarea CAPDEF
+ and MET3
+#endif
+
+ layer m4 MET4,MET4TXT
+ and-not MET4RES
+ labels MET4
+ labels MET4TXT port
+
+ layer obsm4 M4BLOCK
+ labels M4BLOCK
+
+ layer fillm4 M4FILL
+ labels M4FILL
+
+ layer via3 VIA3
+#ifdef METALS5 && MIM
+ and-not CAPM
+ and-not mimarea
+#endif (METALS5 && MIM)
+ grow 140
+ shrink 130
+
+#ifdef MIM
+ layer mimcc VIA3
+ and MET4
+ and CAPM
+ and CAPDEF
+ grow 90
+ grow 250
+ shrink 250
+#endif (MIM)
+#endif (METALS4 || METALS5 || METALS6)
+
+#ifdef METALS5 || METALS6
+ layer rm5 MET5
+ and RESDEF
+ and MET5RES
+
+#ifdef MIM
+ templayer mimarea CAPDEF
+ and MET4
+#endif
+
+ layer m5 MET5,MET5TXT
+#ifdef MIM && METALS6
+ and-not CAPM
+ and-not mimarea
+#endif (MIM && METALS6)
+ and-not MET5RES
+ labels MET5
+ labels MET5TXT port
+
+ layer obsm5 M5BLOCK
+ labels M5BLOCK
+
+ layer fillm5 M5FILL
+ labels M5FILL
+
+ layer via4 VIA4
+#ifdef MIM && METALS6
+ and-not CAPM
+ and-not mimarea
+#endif (MIM && METALS6)
+ grow 140
+ shrink 130
+
+#ifdef MIM
+ layer mimcc VIA4
+ and MET5
+ and CAPM
+ and CAPDEF
+ grow 90
+ grow 250
+ shrink 250
+#endif (MIM)
+#endif (METALS5 || METALS6)
+
+#ifdef METALS6
+ layer rmtp METTP
+ and RESDEF
+ and METTPRES
+
+ layer mtp METTP,METTPTXT
+ and-not METTPRES
+ labels METTP
+ labels METTPTXT port
+
+ layer obsmtp MTPBLOCK
+ labels MTPBLOCK
+
+ layer fillmtp MTPFILL
+ labels MTPFILL
+
+#ifdef MIM
+ templayer mimarea CAPDEF
+ and MET5
+#endif
+
+ layer viatp VIATP
+ and METTP
+#ifdef MIM
+ and-not CAPM
+ and-not mimarea
+#endif (MIM)
+ grow 5
+ grow 265
+ shrink 265
+
+#ifdef MIM
+ layer mimcc VIATP
+ and METTP
+ and CAPM
+ and CAPDEF
+ grow 260
+ shrink 250
+#endif (MIM)
+#endif (METALS6)
+
+#ifdef MIM
+ layer mimcap CAPM
+ and CAPDEF
+ labels CAPM
+#endif (MIM)
+
+ # Find diffusion not covered in
+ # NPLUS or PPLUS and pull it into
+ # the next layer up
+
+ templayer gentrans DIFF
+ and-not PPLUS
+ and-not NPLUS
+ and POLY
+ copyup DIFF,POLY
+
+ templayer gendiff DIFF
+ and-not PPLUS
+ and-not NPLUS
+ and-not POLY
+ copyup DIFF
+
+ # Handle contacts found by copyup
+
+ layer ndic CONT
+ and MET1
+ and DIODE
+ and NPLUS
+ and-not DUALGATE
+ and-not NAT
+ grow 100
+ shrink 100
+
+ layer mvndic CONT
+ and MET1
+ and DIODE
+ and NPLUS
+ and DUALGATE
+ and-not NAT
+ grow 100
+ shrink 100
+
+ layer mvnndic CONT
+ and MET1
+ and DIODE
+ and NPLUS
+ and DUALGATE
+ and NAT
+ grow 100
+ shrink 100
+
+ layer pdic CONT
+ and MET1
+ and DIODE
+ and PPLUS
+ and-not DUALGATE
+ grow 100
+ shrink 100
+
+ layer mvpdic CONT
+ and MET1
+ and DIODE
+ and PPLUS
+ and DUALGATE
+ grow 100
+ shrink 100
+
+ layer ndc CONT
+ and ndifcheck
+ grow 100
+ shrink 100
+
+ layer mvndc CONT
+ and mvndifcheck
+ grow 100
+ shrink 100
+
+ layer pdc CONT
+ and pdifcheck
+ grow 100
+ shrink 100
+
+ layer mvpdc CONT
+ and mvpdifcheck
+ grow 100
+ shrink 100
+
+ layer pc CONT
+ and polycheck
+ grow 100
+ shrink 100
+
+ layer nsc CONT
+ and nsubcheck
+ grow 100
+ shrink 100
+
+ layer mvnsc CONT
+ and mvnsubcheck
+ grow 100
+ shrink 100
+
+ layer psc CONT
+ and psubcheck
+ grow 100
+ shrink 100
+
+ layer mvpsc CONT
+ and mvpsubcheck
+ grow 100
+ shrink 100
+
+ # Find contacts not covered in
+ # metal and pull them into the
+ # next layer up
+ 
+ templayer gencont CONT
+ and MET1
+ and-not DIFF
+ and-not POLY
+ and-not DIODE
+ and-not nsubcheck
+ and-not psubcheck
+ and-not mvnsubcheck
+ and-not mvpsubcheck
+ copyup CONT,MET1
+
+ templayer barecont CONT
+ and-not MET1
+ and-not nsubcheck
+ and-not psubcheck
+ and-not mvnsubcheck
+ and-not mvpsubcheck
+ copyup CONT
+
+ layer glass GLASS
+ labels GLASS
+
+ templayer cellbound BOUND
+ boundary
+
+ layer lvstext TTEXT
+ labels TTEXT text
+
+ layer fillblock  FILLOBS,FILLOBS2
+ labels FILLOBS
+
+# MOS Varactors
+
+ layer var POLY
+ and DIFF
+ and NPLUS
+ and NWELL
+ and-not DUALGATE
+ labels POLY
+
+ layer mvvar POLY
+ and DIFF
+ and NPLUS
+ and NWELL
+ and DUALGATE
+ labels POLY
+
+ calma DNWELL 12 0
+ calma NWELL 21 0
+ calma PWELL 204 0
+ calma DIFF 22 0
+ calma DIFFFILL 22 4
+ calma POLY 30 0
+ calma POLYFILL 30 4
+ calma POLYTXT 30 10
+ calma NPLUS 32 0
+ calma PPLUS 31 0
+ calma SBLK 49 0
+ calma GLASS 37 0
+ calma CONT 33 0
+ calma MET1 34 0
+ calma MET1TXT 34 10
+ calma M1BLOCK 34 5
+ calma M1FILL 34 4
+ calma MET2RES 110 11
+ calma VIA1 35 0
+ calma MET2 36 0
+ calma MET2TXT 36 10
+ calma M2BLOCK 36 5
+ calma M2FILL 36 4
+ calma MET2RES 110 12
+#ifdef METALS3 || METALS4 || METALS5 || METALS6
+ calma VIA2 38 0
+ calma MET3 42 0
+ calma MET3TXT 42 10
+ calma M3BLOCK 42 5
+ calma M3FILL 42 4
+ calma MET3RES 110 13
+#endif (METALS3 || METALS4 || METALS5 || METALS6)
+#ifdef METALS4 || METALS5 || METALS6
+ calma VIA3 40 0
+ calma MET4 46 0
+ calma MET4TXT 46 10
+ calma M4BLOCK 46 5
+ calma M4FILL 46 4
+ calma MET4RES 110 14
+#endif (METALS4 || METALS5 || METALS6)
+#ifdef METALS5 || METALS6
+ calma VIA4 41 0
+ calma MET5 81 0
+ calma MET5TXT 81 10
+ calma M5BLOCK 81 5
+ calma M5FILL 81 4
+ calma MET5RES 110 15
+#endif (METALS5 || METALS6)
+#ifdef METALS6
+ calma VIATP 129 0
+ calma METTP 53 0
+ calma METTPTXT 53 10
+ calma MTPBLOCK 53 5
+ calma METTPRES 110 16
+#endif (METALS6)
+#ifdef HRPOLY1K
+ calma HRES 62 0
+#endif (HRPOLY1K)
+ calma NAT 5 0
+ calma CAPM 75 0
+ calma DIODE  115 5
+ calma CAPDEF 117 5
+ calma BJTDEF 118 5
+ calma MOSCAP 166 5
+ calma BOUND 0 0
+ calma FILLOBS  111 5
+ calma FILLOBS2 152 5
+ calma TTEXT    230 *
+ calma RESDEF   110 *
+ calma DUALGATE 55 0
+ calma SRAMDEF  108 5
+ calma FET5VDEF 112 1
+
+end
+
+#-----------------------------------------------------
+# Digital flow maze router cost parameters
+#-----------------------------------------------------
+
+mzrouter
+end
+
+#-----------------------------------------------------
+# Vendor DRC rules
+#-----------------------------------------------------
+
+drc
+
+ style drc variants (fast),(full),(routing)
+
+ scalefactor 50 
+
+ cifstyle drc
+
+ variants (fast),(full)
+
+#-----------------------------
+# NWELL
+#-----------------------------
+
+ width allnwell 860 "N-well width < %d (NW.1a)"
+ spacing allnwell allnwell 600 touching_ok "N-well spacing < %d (NW.2a)"
+ # rnw spacing is to unrelated nwell only.
+ spacing rnw allnwell 1400 touching_ok "N-well resistor spacing < %d (NW.4)"
+ width rnw 2000 "N-well resistor width < %d (NW.1b)"
+
+ variants (full)
+ cifspacing mv_nwell mv_nwell 740 touching_ok "MV N-well spacing < %d (NW.2a)"
+ variants *
+
+#-----------------------------
+# DNWELL (deep nwell)
+#-----------------------------
+
+ width dnwell 1700 "Deep N-well width < %d (DN.1)"
+ spacing dnwell dnwell 2500 touching_ok "Deep N-well spacing < %d (DN.2a)"
+
+ surround pwell dnwell 2500 absence_ok \
+	"Deep N-well surround P-well < %d (LPW.3)"
+
+ surround nwell dnwell 500 absence_ok \
+	"Deep N-well surround N-well < %d (NW.5)"
+
+ variants (full)
+
+ cifwidth pwell_in_dnwell 600 "P-well in deep N-well size < %d (LPW.1)"
+ cifwidth mvpwell_in_dnwell 740 "HV P-well in deep N-well size < %d (LPW.1)"
+
+ cifspacing pwell_in_dnwell pwell_in_dnwell 860 touching_ok \
+	"P-well in deep N-well spacing < %d (LPW.2b)"
+ cifspacing mvpwell_in_dnwell mvpwell_in_dnwell 860 touching_ok \
+	"MV P-well in deep N-well spacing < %d (LPW.2b)"
+
+ cifmaxwidth bad_dnwell 0 bend_illegal \
+	"Both LV and MV devices cannot be in the same deep N-well (DN.11)
+
+ cifmaxwidth bad_nwell 0 bend_illegal \
+	"Both LV and MV devices cannot be in the same N-well (DV.9)
+
+ cifmaxwidth bad_rnw 0 bend_illegal \
+	"N-well resistor cannot be in deep N-well (DN.12)
+ variants *
+
+ spacing dnwell allnwell 3100 surround_ok \
+	"Deep N-well spacing to N-well < %d (NW.3)"
+
+ spacing pwell dnwell 1500 surround_ok \
+	"Deep N-well spacing to P-well < %d (LPW.11)"
+
+#-----------------------------
+# DIFF (diffusion)
+#-----------------------------
+
+ width alldifflv 220 "Diffusion width < %d (DF.1a)"
+ width alldiffmv 300 "Diffusion width < %d (DF.1a)"
+ area alldifflv 202500 220 "Diffusion minimum area < %a (DF.9)"
+ area alldiffmv 202500 300 "Diffusion minimum area < %a (DF.9)"
+ spacing alldifflv,var alldifflv,var 280 touching_ok \
+	"Diffusion spacing < %d (DF.3a)"
+ spacing alldiffmv,mvvar alldiffmv,mvvar 360 touching_ok \
+	"Diffusion spacing < %d (DF.3a)"
+
+ spacing *ndiff,*ndiode,nfet,nnfet allnwell 430 touching_illegal \
+	"N-Diffusion spacing to N-well < %d (DF.8)"
+ spacing *mvndiff,*mvndiode,mvnfet,mvnnfet allnwell 600 touching_illegal \
+	"N-Diffusion spacing to N-well < %d (DF.8)"
+ spacing *psd allnwell 120 touching_illegal \
+	"P-Ohmic spacing to N-well < %d (DF.5)"
+ spacing *mvpsd allnwell 160 touching_illegal \
+	"P-Ohmic spacing to N-well < %d (DF.5)"
+ surround *nsd allnwell 120 absence_illegal \
+	"N-well overlap of N-Ohmic < %d (DF.4a)"
+ surround *mvnsd allnwell 160 absence_illegal \
+	"N-well overlap of N-Ohmic < %d (DF.4a)"
+ surround *pdiff,*pdiode,pfet allnwell 430 absence_illegal \
+	"N-well overlap of P-Diffusion < %d (DF.7)"
+ surround *mvpdiff,*mvpdiode,mvpfet allnwell 600 absence_illegal \
+	"N-well overlap of P-Diffusion < %d (DF.7)"
+ surround *psd pwell 120 absence_ok \
+	"P-field overlap of P-Ohmic < %d (DF.5)"
+ surround *mvpsd pwell  160 absence_ok \
+	"MV P-field overlap of MV P-Ohmic < %d (DF.5)"
+
+ # NAT requires additional spacing rules
+ spacing *nndiode,*mvnndiode *psd,*mvpsd 610 touching_illegal \
+	"NAT Diffusion spacing to TAP diffusion < %d (NAT.5 + NAT.6)"
+
+#-----------------------------
+# POLY
+#-----------------------------
+
+ width allpoly 180 "Poly width < %d (PL.1)"
+ spacing allpoly allpoly 240 touching_ok "Poly spacing < %d (PL.3a)"
+ spacing allpolynonfet alldifflvnonfet 100 corner_ok allfets \
+	"Poly spacing to diffusion < %d (PL.5a)"
+ spacing allpolynonfet alldiffmvnonfet 300 corner_ok allfets \
+	"Poly spacing to MV diffusion < %d (PL.5a)
+ overhang *ndiff,rndiff nfet,nnfet 230 "N-Diffusion overhang of nmos < %d (DF.6)"
+ overhang *mvndiff,mvrndiff mvnfet,mvnnfet 230 \
+	"N-Diffusion overhang of nmos < %d (DF.6)"
+ overhang *pdiff,rpdiff pfet 230 "P-Diffusion overhang of pmos < %d (DF.6)"
+ overhang *mvpdiff,mvrpdiff mvpfet 230 "P-Diffusion overhang of pmos < %d (DF.6)"
+ overhang *poly allfetsnonnat 220 "Poly overhang of transistor < %d (PL.4)"
+ overhang *poly nnfet,mvnnfet 350 "Poly overhang of NAT transistor < %d (NAT.6)"
+
+ angles allfets 45-only "Only 45 degrees allowed on transistors (PL.6)"
+
+#-----------------------------------------------------------------------------
+# SBLK - more rules to do here (note PRES refers only to unsalicided resistor)
+#-----------------------------------------------------------------------------
+
+ spacing allpolysblkres allpolysblkres 250 touching_ok \
+	"Poly resistor spacing < %d (PRES.2)
+
+ spacing allpolysblkres allpolynonres 450 touching_ok \
+	"Poly resistor spacing to unrelated poly < %d (PRES.4)"
+ spacing allpolysblkres allactive,allactiveres 440 touching_illegal \
+	"Poly resistor spacing to diffusion < %d (PRES.3)"
+
+ spacing allactiveres allactiveres 400 touching_ok \
+	"Diffusion resistor spacing < %d (NDRES.2)
+
+ spacing allactiveres allactive 450 touching_ok \
+	"Diffusion resistor spacing to unrelated diffusion < %d (NDRES.3)"
+ spacing allactiveres allpoly 450 touching_ok \
+	"Diffusion resistor spacing to unrelated poly < %d (NDRES.4)"
+
+#-----------------------------
+# CONT
+#-----------------------------
+# Drawn contact includes 5nm metal1 surround
+ width (ndc,nsc,pdc,psc,ndic,pdic,pc)/m1 230 \
+	"Diffusion contact width < %d (CO.1 + 2 * CO.6)"
+ spacing (ndc,nsc,pdc,psc,ndic,pdic,pc)/m1 \
+	(ndc,nsc,pdc,psc,ndic,pdic,pc)/m1 240 \
+	touching_ok "Diffusion contact spacing < %d (CO.2a - CO.6)"
+ surround (ndc,nsc,pdc,psc,ndic,pdic,pc)/m1 *m1 55 \
+	directional "Metal1 overlap of contact < %d in one direction (CO.6)"
+ surround ndc/a *ndiff 65 absence_illegal \
+	"N-Diffusion overlap of contact < %d (CO.4)"
+ surround nsc/a *nsd 65 absence_illegal \
+	"N-Diffusion overlap of contact < %d (CO.4)"
+ surround pdc/a *pdiff 65 absence_illegal \
+	"P-Diffusion overlap of contact < %d (CO.4)"
+ surround psc/a *psd 65 absence_illegal \
+	"P-Diffusion overlap of contact < %d (CO.4)"
+ surround ndic/a *ndiode 65 absence_illegal \
+	"N-Diffusion overlap of contact < %d (CO.4)"
+ surround pdic/a *pdiode 65 absence_illegal \
+	"P-Diffusion overlap of contact < %d (CO.4)"
+ surround pc/a *poly 65 absence_illegal "Poly overlap of contact < %d (CO.3)"
+
+ width (mvndc,mvnsc,mvpdc,mvpsc,mvndic,mvnndic,mvpdic)/m1 230 \
+	"MV Diffusion contact width < %d (CO.1 + 2 * CO.6)"
+ spacing (mvndc,mvnsc,mvpdc,mvpsc,mvndic,mvnndic,mvpdic)/m1 \
+	(mvndc,mvnsc,mvpdc,mvpsc,mvndic,mvnndic,mvpdic)/m1 240 touching_ok \
+	"Diffusion contact spacing < %d (CO.2a - CO.6)"
+ surround (mvndc,mvnsc,mvpdc,mvpsc,mvndic,mvnndic,mvpdic)/m1 *m1 55 directional \
+	"Metal1 overlap of contact < %d in one direction (CO.6)"
+ surround mvndc/a *mvndiff 65 absence_illegal \
+	"MV N-Diffusion overlap of contact < %d (CO.4)"
+ surround mvnsc/a *mvnsd 65 absence_illegal \
+	"MV N-Diffusion overlap of contact < %d (CO.4)"
+ surround mvpdc/a *mvpdiff 65 absence_illegal \
+	"MV P-Diffusion overlap of contact < %d (CO.4)"
+ surround mvpsc/a *mvpsd 65 absence_illegal \
+	"MV P-Diffusion overlap of contact < %d (CO.4)"
+ surround mvndic/a *mvndiode 65 absence_illegal \
+	"MV N-Diffusion overlap of contact < %d (CO.4)"
+ surround mvnndic/a *mvnndiode 65 absence_illegal \
+	"MV NAT N-Diffusion overlap of contact < %d (CO.4)"
+ surround mvpdic/a *mvpdiode 65 absence_illegal \
+	"MV P-Diffusion overlap of contact < %d (CO.4)"
+
+ spacing allpdiffcont allndiffcont 240 touching_illegal \
+	"Diffusion contact spacing < %d (CO.2a - CO.6)"
+ spacing allndiffcont allndiffcont 240 touching_ok \
+	"Diffusion contact spacing < %d (CO.2a - CO.6)"
+ spacing allpdiffcont allpdiffcont 240 touching_ok \
+	"Diffusion contact spacing < %d (CO.2a - CO.6)"
+ spacing pc pc 240 touching_ok "Poly contact spacing < %d (CO.2a - CO.6)"
+ spacing pc alldiff 165 touching_illegal \
+	"Poly contact spacing to diffusion < %d (CO.8 - CO.6)"
+ spacing allpdiffcont,allndiffcont allpoly 145 touching_illegal \
+	"Diffusion contact spacing to poly < %d (CO.7 - CO.6)"
+
+ exact_overlap (ndc,pdc,psc,nsc,pc,ndic,pdic)/a
+ exact_overlap (mvndc,mvpdc,mvpsc,mvnsc,mvndic,mvnndic,mvpdic)/a
+
+variants *
+
+#-----------------------------
+# METAL 1
+#-----------------------------
+
+ width *m1,rm1 230 "Metal1 width < %d (M1.1)"
+ spacing allm1,obsm1  allm1,obsm1 230 touching_ok "Metal1 spacing < %d (M1.2a)"
+ area allm1,obsm1 144400 230 "Metal1 minimum area < %a (M1.3)"
+
+variants (fast),(full)
+ widespacing allm1,obsm1 10000 allm1,obsm1  300 touching_ok \
+	"Metal1 > 10um spacing to unrelated m1 < %d (M1.2b)"
+
+variants *
+
+#--------------------------------------------------
+# VIA 1
+#--------------------------------------------------
+
+ width v1/m1 260 "Via1 width < %d (V1.1)"
+ spacing v1 v1 260 touching_ok "Via1 spacing < %d (V1.2a)"
+ surround v1/m1 *m1 60 directional \
+	"Metal1 overlap of Via1 < %d in one direction (V1.3)"
+ surround v1/m2 *m2 10 absence_illegal \
+	"Metal2 overlap of Via1 < %d (V1.4)"
+ surround v1/m2 *m2 60 directional \
+	"Metal2 overlap of Via1 < %d in one direction (V1.4i)"
+ exact_overlap v1/m2
+
+#-----------------------------
+# METAL 2
+#-----------------------------
+
+ width *m2,rm2 280 "Metal2 width < %d (M2.1)"
+ spacing allm2,obsm2  allm2,obsm2 280 touching_ok "Metal2 spacing < %d (M2.2a)"
+ area allm2,obsm2 144400 280 "Metal2 minimum area < %a (M2.3)"
+
+variants (fast),(full)
+ widespacing allm2,obsm2 10000 allm2,obsm2  300 touching_ok \
+	"Metal2 > 10um spacing to unrelated m2 < %d (M2.2b)"
+
+variants *
+
+#ifdef METALS3 || METALS4 || METALS5 || METALS6
+#--------------------------------------------------
+# VIA 2
+#--------------------------------------------------
+
+ width v2/m2 280 "Via2 width < %d (V2.1 + 2 * V2.3)"
+ spacing v2 v2 240 touching_ok "Via2 spacing < %d (V2.2a - 2 * V2.3)"
+ surround v2/m2 *m2 50 directional \
+	"Metal2 overlap of Via2 < %d in one direction (V2.3i - V2.3)"
+
+ exact_overlap v2/m3
+
+#-----------------------------
+# METAL 3
+#-----------------------------
+
+#ifdef METALS3
+ # Metal 3 is the top metal
+#ifdef THICKMET3P0
+ width *m3,rm3 1800 "Thick Metal3 width < %d (MT30.1)"
+ spacing allm3,obsm3  allm3,obsm3 1800 touching_ok \
+	"Thick Metal3 spacing < %d (MT30.2)"
+
+ surround v2/m3 *m3 110 absence_illegal \
+	"Thick Metal3 overlap of Via2 < %d (MT30.5 - V2.4)"
+ surround v2/m3 *m3 240 directional \
+	"Thick Metal3 overlap of Via2 < %d in one direction (MT30.6 - V2.4)"
+
+#elseif defined(THICKMET0P9 || THICKMET1P1)
+ surround v2/m3 *m3 50 directional \
+	"Metal3 overlap of Via2 < %d in one direction (V2.4i - V2.4)"
+
+ width *m3,rm3 440 "Metal3 width < %d (MT.1)"
+ spacing allm3,obsm3  allm3,obsm3 460 touching_ok "Metal3 spacing < %d (MT.2a)"
+ area allm3,obsm3 562500 440 "Metal3 minimum area < %a (MT.4)"
+
+variants (fast),(full)
+ widespacing allm3,obsm3 10000 allm3,obsm3  600 touching_ok \
+	"Metal3 > %c spacing to unrelated m3 < %d (MT.2b)"
+
+#else (!(THICKMET3P0 || THICKMET0P9 || THICKMET1P1))
+ surround v2/m3 *m3 50 directional \
+	"Metal3 overlap of Via2 < %d in one direction (V2.4i - V2.4)"
+
+ width *m3,rm3 360 "Metal3 width < %d (MT.1)"
+ spacing allm3,obsm3  allm3,obsm3 380 touching_ok "Metal3 spacing < %d (MT.2a)"
+ area allm3,obsm3 562500 360 "Metal3 minimum area < %a (MT.4)"
+
+variants (fast),(full)
+ widespacing allm3,obsm3 10000 allm3,obsm3  500 touching_ok \
+	"Metal3 > %c spacing to unrelated m3 < %d (MT.2b)"
+#endif (!(THICK3UMET || THICKMET1P1 || THICKMET0P9))
+#else (!METALS3)
+ surround v2/m3 *m3 50 directional \
+	"Metal3 overlap of Via2 < %d in one direction (V2.4i - V2.4)"
+
+ width *m3,rm3 280 "Metal3 width < %d (M3.1)"
+ spacing allm3,obsm3  allm3,obsm3 280 touching_ok "Metal3 spacing < %d (M3.2a)"
+ area allm3,obsm3 144400 280 "Metal3 minimum area < %a (M3.3)"
+
+variants (fast),(full)
+ widespacing allm3,obsm3 10000 allm3,obsm3  300 touching_ok \
+	"Metal3 > %c spacing to unrelated m3 < %d (M3.2b)"
+#endif (!METALS3)
+
+variants *
+#endif (METALS3 || METALS4 || METALS5 || METALS6)
+
+#ifdef METALS4 || METALS5 || METALS6
+#--------------------------------------------------------------
+# VIA 3 - Requires METALS4, METALS5, or METALS6 Module
+#--------------------------------------------------------------
+
+ width v3/m3 280 "Via3 width < %d (V3.1 + 2 * V3.4)"
+ spacing v3 v3 240 touching_ok "Via3 spacing < %d (V3.2a - 2 * V3.4)"
+ surround v3/m3 *m3 50 directional \
+	"Metal3 overlap of Via3 < %d in one direction (V3.3i - V3.3)"
+
+ exact_overlap v3/m4
+
+#-----------------------------
+# METAL 4 - METALS4 Module
+#-----------------------------
+
+#ifdef METALS4
+ # Metal 4 is the top metal
+#ifdef THICKMET3P0
+ width *m4,rm4 1800 "Thick Metal4 width < %d (MT30.1)"
+ spacing allm4,obsm4  allm4,obsm4 1800 touching_ok "Metal4 spacing < %d (MT30.2)"
+
+ surround v3/m4 *m4 110 absence_illegal \
+	"Thick Metal4 overlap of Via3 < %d (MT30.5 - V3.4)"
+ surround v3/m4 *m4 240 directional \
+	"Thick Metal4 overlap of Via3 < %d in one direction (MT30.6 - V3.4)"
+
+#elseif defined(THICKMET0P9 || THICKMET1P1)
+ surround v3/m4 *m4 50 directional \
+	"Metal4 overlap of Via3 < %d in one direction (V3.4i - V3.4)"
+
+ width *m4,rm4 440 "Metal4 width < %d (MT.1)"
+ spacing allm4,obsm4  allm4,obsm4 460 touching_ok "Metal4 spacing < %d (MT.2a)"
+ area allm4,obsm4 562500 440 "Metal4 minimum area < %a (MT.4)"
+
+variants (fast),(full)
+ widespacing allm4,obsm4 10000 allm4,obsm4  600 touching_ok \
+	"Metal4 > %c spacing to unrelated m4 < %d (MT.2b)"
+#else (!(THICK3UMET || THICKMET1P1 || THICKMET0P9))
+ surround v3/m4 *m4 50 directional \
+	"Metal4 overlap of Via3 < %d in one direction (V3.4i - V3.4)"
+
+ width *m4,rm4 360 "Metal4 width < %d (MT.1)"
+ spacing allm4,obsm4  allm4,obsm4 380 touching_ok "Metal4 spacing < %d (MT.2a)"
+ area allm4,obsm4 562500 360 "Metal4 minimum area < %a (MT.4)"
+
+variants (fast),(full)
+ widespacing allm4,obsm4 10000 allm4,obsm4  500 touching_ok \
+	"Metal4 > %c spacing to unrelated m4 < %d (MT.2b)"
+#endif (!(THICK3UMET || THICKMET1P1 || THICKMET0P9))
+#else (!METALS4)
+ surround v3/m4 *m4 50 directional \
+	"Metal4 overlap of Via3 < %d in one direction (V3.4i - V3.4)"
+
+ width *m4,rm4 200 "Metal4 width < %d (M4.1)"
+ spacing allm4,obsm4  allm4,obsm4 210 touching_ok "Metal4 spacing < %d (M4.2a)"
+ area allm4,obsm4 144000 200 "Metal4 minimum area < %a (M4.3)"
+
+variants (fast),(full)
+ widespacing allm4,obsm4 10000 allm4,obsm4  300 touching_ok \
+	"Metal4 > %c spacing to unrelated m4 < %d (M4.2b)"
+#endif (!METALS4)
+
+variants *
+#endif (METALS4 || METALS5 || METALS6)
+
+#ifdef METALS5 || METALS6
+#------------------------------------------------------
+# VIA 4 - Requires METALS5 Module
+#------------------------------------------------------
+
+ width v4/m4 280 "Via4 width < %d (V4.1 + 2 * V4.4)"
+ spacing v4 v4 240 touching_ok "Via4 spacing < %d (V4.2a - 2 * V4.4)"
+ exact_overlap v4/m5
+
+#-----------------------------
+# METALS 5 - METALS5 Module
+#-----------------------------
+
+#ifdef METALS5
+ # Metal 5 is the top metal
+#ifdef THICKMET3P0
+ width *m5,rm5 1800 "Metal5 width < %d (MT30.1)"
+ spacing allm5,obsm5  allm5,obsm5 1800 touching_ok "Metal5 spacing < %d (MT30.2)"
+
+ surround v4/m5 *m5 110 absence_illegal \
+	"Metal5 overlap of Via4 < %d (MT30.5 - V4.4)"
+ surround v4/m5 *m5 240 directional \
+	"Metal5 overlap of Via4 < %d in one direction (MT30.6 - V4.4)"
+
+#elseif defined(THICKMET1P1 || THICKMET0P9)
+ surround v4/m4 *m4 50 directional \
+	"Metal4 overlap of Via4 < %d in one direction (V4.3i - V4.3)"
+ surround v4/m5 *m5 50 directional \
+	"Metal5 overlap of Via4 < %d in one direction (V4.4i - V4.4)"
+
+ width *m5,rm5 440 "Metal5 width < %d (MT.1)"
+ spacing allm5,obsm5  allm5,obsm5 460 touching_ok "Metal5 spacing < %d (MT.2a)"
+ area allm5,obsm5 526500 440 "Metal5 minimum area < %a (MT.4)"
+
+variants (fast),(full)
+ widespacing allm5,obsm5 10000 allm5,obsm5  600 touching_ok \
+	"Metal5 > %c spacing to unrelated m5 < %d (MT.2b)"
+#else (!(THICK3UMET || THICKMET1P1 || THICKMET0P9))
+ surround v4/m4 *m4 50 directional \
+	"Metal4 overlap of Via4 < %d in one direction (V4.3i - V4.3)"
+ surround v4/m5 *m5 50 directional \
+	"Metal5 overlap of Via4 < %d in one direction (V4.4i - V4.4)"
+
+ width *m5,rm5 360 "Metal5 width < %d (MT.1)"
+ spacing allm5,obsm5  allm5,obsm5 380 touching_ok "Metal5 spacing < %d (MT.2a)"
+ area allm5,obsm5 562500 360 "Metal5 minimum area < %a (MT.4)"
+
+variants (fast),(full)
+ widespacing allm5,obsm5 10000 allm5,obsm5  500 touching_ok \
+	"Metal5 > %c spacing to unrelated m5 < %d (MT.2b)"
+#endif (!(THICK3UMET || THICKMET1P1 || THICKMET0P9))
+#else (!METALS5)
+ surround v4/m4 *m4 50 directional \
+	"Metal4 overlap of Via4 < %d in one direction (V4.3i - V4.3)"
+ surround v4/m5 *m5 50 directional \
+	"Metal5 overlap of Via4 < %d in one direction (V4.4i - V4.4)"
+
+ width *m5,rm5 200 "Metal5 width < %d (M5.1)"
+ spacing allm5,obsm5  allm5,obsm5 210 touching_ok "Metal5 spacing < %d (M5.2a)"
+ area allm5,obsm5 144000 200 "Metal5 minimum area < %a (M5.3)"
+
+variants (fast),(full)
+ widespacing allm5,obsm5 10000 allm5,obsm5  300 touching_ok \
+	"Metal5 > %c spacing to unrelated m5 < %d (M5.2b)"
+
+#endif (!METALS5)
+
+variants *
+#endif (METALS5 || METALS6)
+
+#ifdef METALS6
+#-----------------------------------------------------------------------------------
+# VIA TP - Requires METALS6 Module
+#-----------------------------------------------------------------------------------
+
+ spacing vtp vtp 340 touching_ok "ViaTP spacing < %d (VT.2a - VT.3)"
+
+ width vtp/m5 370 "ViaTP width < %d (VT.1+VT.3)"
+ surround vtp/m5 *m5 45 directional \
+	"Metal 5 overlap of ViaTP in one direction < %d (VT.3)"
+ exact_overlap vtp/m5
+
+#----------------------------------------------------------------------
+# METAL TP - Top metal for METALS6 module
+#----------------------------------------------------------------------
+
+variants *
+ # Metal TP is the top metal
+#ifdef THICKMET3P0
+ width allmtp 1800 "Thick Top Metal width < %d (MT30.1)"
+ spacing allmtp,obsmtp  allmtk,obsmtk 1800 touching_ok\
+	"Thick Top Metal spacing < %d (MT30.2a)"
+
+ surround vtp/mtp *mtp 110 absence_illegal \
+	"Thick Top Metal overlap of ViaTP < %d (MT30.5 - VTP.4)"
+ surround vtp/mtp *mtp 240 directional \
+	"Thick Top Metal overlap of ViaTP < %d in one direction (MT30.6 - VTP.4)"
+
+#elseif defined(THICKMET1P1 || THICKMET0P9)
+ surround vtp/mtp *mtp 80 absence_illegal \
+	"Top Metal overlap of ViaTP < %d (VT.4 - VT.3)"
+ width allmtp 440 "Top Metal width < %d (MT.1)"
+ spacing allmtp,obsmtp  allmtp,obsmtp 460 touching_ok\
+	"Top Metal spacing < %d (MT.2a)"
+ area allmtp 562500 440 "Top Metal minimum area < %a (MT.4)"
+
+variants (fast),(full)
+ widespacing allmtp,obsmtp 10000 allmtp,obsmtp  600 touching_ok \
+	"Top Metal > %c spacing to unrelated Top Metal < %d (MT.2b)"
+
+#else (!(THICKMET3P0 || THICKMET1P1 || THICKMET0P9))
+ surround vtp/mtp *mtp 80 absence_illegal \
+	"Top Metal overlap of ViaTP < %d (VT.4 - VT.3)"
+
+ width allmtp 360 "Top Metal width < %d (MT.1)"
+ spacing allmtp,obsmtp  allmtp,obsmtp 380 touching_ok\
+	"Top Metal spacing < %d (MT.2a)"
+ area allmtp 562500 360 "Top Metal minimum area < %a (MT.4)"
+
+variants (fast),(full)
+ widespacing allmtp,obsmtp 10000 allmtp,obsmtp  500 touching_ok \
+	"Top Metal > %c spacing to unrelated Top Metal < %d (MT.2b)"
+
+#endif (!(THICKMET3P0 || THICKMET1P1 || THICKMET0P9))
+variants *
+
+#endif (METALS6)
+
+#--------------------------------------------------
+# NMOS, PMOS
+#--------------------------------------------------
+
+ # NOTE:  The layer width can be used for the smaller of
+ # (minimum length, minimum width).  However, for many
+ # devices, minimum width is less than minimum length.
+
+ extend nnfet *ndiff 400 exclusive "nn Transistor length < %d (DF.2c)"
+
+ extend mvnnfet *mvndiff 1200 exclusive "MV nn Transistor length < %d (NAT.4)"
+ width mvnnfet 400 "MV nn Transistor width < %d (DF.2c)"
+
+ extend pfet *pdiff 280 exclusive "Transistor length < %d (PL.1a)"
+ extend nfet *ndiff 280 exclusive "Transistor length < %d (PL.1a)"
+ width pfet 300 angles "Bent Transistor length < %d (PL.7)"
+ width nfet 300 angles "Bent Transistor length < %d (PL.7)"
+
+ extend mvpfet *mvpdiff 500 exclusive "MV Transistor length < %d (PL.1a)"
+ extend mvnfet *mvndiff 600 exclusive "MV Transistor length < %d (PL.1a)"
+ width mvpfet 700 angles "Bent MV Transistor length < %d (PL.7)"
+ width mvnfet 700 angles "Bent MV Transistor length < %d (PL.7)"
+
+ # NOTE:  Use edge4way to deal with butted junctions
+ # spacing *nsd,*mvnsd pfet,mvnnfet,mvpfet 330 touching_illegal \
+ #	"n-ohmic spacing to PMOS gate < %d (NP.4b)"
+ # spacing *psd,*mvpsd nfet,nnfet,mvnfet 330 touching_illegal \
+ #	"p-ohmic spacing to NMOS gate < %d (NP.4c)"
+
+ edge4way pfet,mvnnfet,mvpfet *poly/a 330 ~(*nsd,*mvnsd)/a (*pdiff,*mvpdiff)/a 300 \
+	"n-ohmic spacing to PMOS gate < %d (NP.4b + PP.4c)"
+ edge4way nfet,nnfet,mvnfet *poly/a 330 ~(*psd,*mvpsd)/a (*ndiff,*mvndiff)/a 300 \
+	"p-ohmic spacing to NMOS gate < %d (PP.4b + NP.4c)"
+
+ # Butting junction rules (flag p/nsd distance to butting junction < 0.03um)
+ edge4way (*psd)/a ~(*ndiff,*psd)/a 330 ~(*ndiff)/a (*ndiff)/a 30 \
+        "N-Diffusion to P-tap spacing < %d across butted junction (PP.4b + NP.4c)"
+ edge4way (*ndiff)/a ~(*ndiff,*psd)/a 330 ~(*psd)/a (*psd)/a 30 \
+        "N-Diffusion to P-tap spacing < %d across butted junction (PP.4b + NP.4c)"
+ edge4way (*nsd)/a ~(*pdiff,*nsd)/a 330 ~(*pdiff)/a (*pdiff)/a 30 \
+        "P-Diffusion to N-tap spacing < %d across butted junction (NP.4b + PP.4c)"
+ edge4way (*pdiff)/a ~(*pdiff,*nsd)/a 330 ~(*nsd)/a (*nsd)/a 30 \
+        "P-Diffusion to N-tap spacing < %d across butted junction (NP.4b + PP.4c)"
+
+ edge4way (*mvpsd)/a ~(*mvndiff,*mvpsd)/a 330 ~(*mvndiff)/a (*mvndiff)/a 30 \
+        "MV N-Diffusion to MV P-tap spacing < %d across butted junction (PP.4b + NP.4c)"
+ edge4way (*mvndiff)/a ~(*mvndiff,*mvpsd)/a 330 ~(*mvpsd)/a (*mvpsd)/a 30 \
+        "MV N-Diffusion to MV P-tap spacing < %d across butted junction (PP.4b + NP.4c)"
+ edge4way (*mvnsd)/a ~(*mvpdiff,*mvnsd)/a 330 ~(*mvpdiff)/a (*mvpdiff)/a 30 \
+        "MV P-Diffusion to MV N-tap spacing < %d across butted junction (NP.4b + PP.4c)"
+ edge4way (*mvpdiff)/a ~(*mvpdiff,*mvnsd)/a 330 ~(*mvnsd)/a (*mvnsd)/a 30 \
+        "MV P-Diffusion to MV N-tap spacing < %d across butted junction (NP.4b + PP.4c)"
+
+#--------------------------------------------------
+# RPP,RNP
+#--------------------------------------------------
+ width rpp 800 "ppolyres minimum width < %d (PRES.1)"
+ width rnp 800 "npolyres minimum width < %d (NRES.1)"
+ spacing rpp rpp 400 touching_ok "ppolyres minimum spacing < %d (PRES.2)"
+ spacing rnp rnp 400 touching_ok "npolyres minimum spacing < %d (NRES.2)"
+
+ spacing rpp pc 215 touching_illegal "rpp spacing to Cont < %d (PRES.8 - CO.6)"
+ spacing rnp pc 215 touching_illegal "rnp spacing to Cont < %d (NRES.8 - CO.6)"
+
+#ifdef HRPOLY1K
+#--------------------------------------------------
+# HIRES
+#--------------------------------------------------
+  width hires,mvhires 1000 "hires poly minimum width < %d (HRES.3)"
+  spacing hires,mvhires hires,mvhires 400 touching_ok \
+	"hires poly minimum spacing < %d (HRES.2)"
+
+ variants (full)
+ cifmaxwidth res_diff_space 0 bend_illegal \
+	"High value resistor spacing to diffusion < 0.7um (HRES.5 + HRES.4)"
+ cifmaxwidth res_poly_space 0 bend_illegal \
+	"High value resistor spacing to poly < 0.7um (HRES.6 + HRES.4)"
+
+ cifmaxwidth res_cont_space_min 0 bend_illegal \
+	"Unsalicided resistor spacing to poly contact must be 0.22um (PRES/LRES/HRES.7)"
+ cifmaxwidth res_no_cont 0 bend_illegal \
+	"Unsalicided resistor spacing to poly contact must be 0.22um (PRES/LRES/HRES.7)"
+ variants *
+#endif (HRPOLY1K)
+
+#--------------------------------------------------
+# RDN,RDP (Diffusion resistors)
+#--------------------------------------------------
+  width rdn 300 "N-diffusion resistor width < %d (DF.1b)"
+  width rdp 300 "P-diffusion resistor width < %d (DF.1b)"
+
+#------------------------------------
+# MOS Varactor device rules
+#------------------------------------
+
+ overhang *nsd var 320 \
+	"N-Ohmic overhang of Varactor < %d (FIXME)"
+
+ overhang *mvnsd mvvar 320 \
+	"N-Ohmic overhang of Varactor < %d (FIXME)"
+
+ width var,mvvar 1000 \
+	"Varactor length and width < %d (DF.1c)"
+
+#ifdef MIM
+#-------------------------------------------------
+# CAPM (FuseTop)
+#-------------------------------------------------
+
+ width *mimcap 5000 "MiM cap top plate width < %d (MIMTM.8a)"
+ spacing *mimcap *mimcap 600 touching_ok \
+	"MiM cap top plate spacing < %d (MIMTM.6)"
+ surround mimcc mimcap 390 absence_illegal \
+	"MiM cap must surround MiM cap contact by %d (MIMTM.4-VT.4)"
+ spacing pad *mimcap 50 touching_illegal "MiM cap cannot overlap pad (MIM1M.X)"
+ spacing mimcc mimcc 480 touching_ok "MiM cap contact spacing < %d (MIMTM.9 - VT.3)"
+
+#ifdef METALS3
+ spacing via1 *mimcap 50 touching_illegal \
+	"MiM cap cannot overlap via1 (MIMTM.10)"
+ spacing *mimcap  *m2,rm2 1200 touching_ok \
+	"MiM cap to Metal2 spacing < %d (MIMTM.1)"
+ spacing *mimcap via2/m3  390 touching_illegal \
+	"MiM cap spacing to via2 < %d (MIMTM.5-VT.X)"
+ surround *mimcap m2 600 absence_illegal \
+	"Bottom plate overlap of MiM cap < %d (MIMTM.3)"
+ width mimcapc/m3 280 "MiM Contact width < %d (VT.1+VT.3)"
+#elseif defined(METALS4)
+ spacing via2 *mimcap 50 touching_illegal \
+	"MiM cap cannot overlap via2 (MIMTM.10)"
+ spacing *mimcap  *m3,rm3 1200 touching_ok \
+	"MiM cap to Metal3 spacing < %d (MIMTM.1)"
+ spacing *mimcap via3/m4  390 touching_illegal \
+	"MiM cap spacing to via3 < %d (MIMTM.5)"
+ surround *mimcap m3 600 absence_illegal \
+	"Bottom plate overlap of MiM cap < %d (MIMTM.3)"
+ width mimcapc/m4 280 "MiM Contact width < %d (VT.1+VT.3)"
+#elseif defined(METALS5)
+ spacing via3 *mimcap 50 touching_illegal \
+	"MiM cap cannot overlap via3 (MIMTM.10)"
+ spacing *mimcap  *m4,rm4 1200 touching_ok \
+	"MiM cap to Metal4 spacing < %d (MIMTM.1)"
+ spacing *mimcap via4/m5  390 touching_illegal \
+	"MiM cap spacing to via4 < %d (MIMTM.5)"
+ surround *mimcap m4 600 absence_illegal \
+	"Bottom plate overlap of MiM cap < %d (MIMTM.3)"
+ width mimcapc/m5 280 "MiM Contact width < %d (VT.1+VT.3)"
+#elseif defined(METALS6)
+ spacing via4 *mimcap 50 touching_illegal \
+	"MiM cap cannot overlap via4 (MIMTM.10)"
+ spacing *mimcap  *m5,rm5 1200 touching_ok \
+	"MiM cap to Metal5 spacing < %d (MIMTM.1)"
+ spacing *mimcap viatp/mtp  390 touching_illegal \
+	"MiM cap spacing to viaTP < %d (MIMTM.5)"
+ surround *mimcap m5 600 absence_illegal \
+	"Bottom plate overlap of MiM cap < %d (MIMTM.3)"
+ width mimcapc/mtp 280 "MiM Contact width < %d (VT.1+VT.3)"
+#endif
+
+ variants (full)
+ cifmaxwidth mim_bottom_plate_space 0 bend_illegal \
+	"MiM bottom plate to unrelated metal < 1.2um (MIMTM.1)"
+ cifmaxwidth mim_bot_cont_surround 0 bend_illegal \
+	"MiM bottom plate surrounds contact < 0.4um (MIMTM.2)"
+#endif (MIM)
+
+#----------------------------
+# End DRC style
+#----------------------------
+
+ style empty
+ scalefactor 50
+ stepsize 2000
+
+end
+
+#----------------------------
+# LEF format definitions
+#----------------------------
+
+lef
+
+ routing m1	Metal1 METAL1 MET1 m1 met1 metal1
+ routing m2	Metal2 METAL2 MET2 m2 met2 metal2
+#ifdef METALS3 || METALS4 || METALS5 || METALS6
+ routing m3	Metal3 METAL3 MET3 m3 met3 metal3
+#endif (METALS3 || METALS4 || METALS5 || METALS6)
+#ifdef METALS4 || METALS5 || METALS6
+ routing m4	Metal4 METAL4 MET4 m4 met4 metal4
+#endif (METALS4 || METALS5 || METALS6)
+#ifdef METALS5 || METALS6
+ routing m5	Metal5 METAL5 MET5 m5 met5 metal5
+#endif (METALS5 || METALS6)
+#ifdef METALS6
+ routing mtp	MetalTop Metal6 METAL6 METTP mtp mettp MET6 m6 met6 metal6
+#endif (METALS6)
+
+ cut m2c  Via1 VIA1 via1 cont2 via12
+#ifdef METALS3 || METALS4 || METALS5 || METALS6
+ cut m3c  Via2 VIA2 via2 cont3 via23
+#endif (METALS3 || METALS4 || METALS5 || METALS6)
+#ifdef METALS4 || METALS5 || METALS6
+ cut via3 Via3 VIA3 via3 cont4 via34
+#endif (METALS4 || METALS5 || METALS6)
+#ifdef METALS5 || METALS6
+ cut via4 Via4 VIA4 via4 cont5 via45
+#endif (METALS5 || METALS6)
+#ifdef METALS6
+ cut viatp Via5 viatp VIATP VIA5 vtp via5 cont6 via56
+#endif (METALS6)
+
+ obs obsm1   Metal1
+ obs obsm2   Metal2
+#ifdef METALS3 || METALS4 || METALS5 || METALS6
+ obs obsm3   Metal3
+#endif (METALS3 || METALS4 || METALS5 || METALS6)
+#ifdef METALS4 || METALS5 || METALS6
+ obs obsm4   Metal4
+#endif (METALS4 || METALS5 || METALS6)
+#ifdef METALS5 || METALS6
+ obs obsm5   Metal5
+#endif (METALS5 || METALS6)
+#ifdef METALS6
+ obs obsmtp  Metal6
+#endif (METALS6)
+
+ obs obsv1 Via1
+ obs obsv2 Via2
+
+end
+
+#-----------------------------------------------------
+# Device and Parasitic extraction
+#-----------------------------------------------------
+
+extract
+ style ngspice variants (),(hrhc),(lrhc),(hrlc),(lrlc)
+ cscale 1
+ lambda  5.0
+ units	microns
+ step   7
+ sidehalo 8
+ fringeshieldhalo 8
+
+ planeorder dwell	0
+ planeorder well 	1
+ planeorder active 	2
+ planeorder metal1 	3
+ planeorder metal2 	4
+#ifdef METALS3
+ planeorder metal3 	5
+ planeorder block       6
+ planeorder comment     7
+#elseif defined(METALS4)
+ planeorder metal3 	5
+ planeorder metal4 	6
+ planeorder block       7
+ planeorder comment     8
+#elseif defined(METALS5)
+ planeorder metal3 	5
+ planeorder metal4 	6
+ planeorder metal5 	7
+ planeorder block       8
+ planeorder comment     9
+#elseif defined(METALS6)
+ planeorder metal3 	5
+ planeorder metal4 	6
+ planeorder metal5 	7
+ planeorder metaltp 	8
+ planeorder block       9
+ planeorder comment     10
+#endif
+
+ height dnwell	       -0.1	0.0	
+ height nwell,pwell	0.0	0.0145
+ height alldiff		0.0145	0.30
+ height allpoly		0.32	0.2
+ height alldiffcont	0.3145	0.9155
+ height pc		0.52	0.71
+ height allm1		1.23	0.55
+ height via		1.78	0.60
+ height allm2		2.38	0.55
+#ifdef METALS3 || METALS4 || METALS5 || METALS6
+ height via2		2.93	0.60
+ height allm3		3.53	0.55
+#endif
+#ifdef METALS4 || METALS5 || METALS6
+ height via3		4.08	0.60
+ height allm4		4.68	0.55
+#endif
+#ifdef METALS5 || METALS6
+ height via4		5.23	0.60
+#endif
+#ifdef METALS5
+ height allm5		5.83	1.0025
+#endif
+#ifdef METALS6
+ height allm5		5.83	0.55
+#endif
+#ifdef METALS6
+ height viatp		6.38	0.9	
+ height allmtp		7.28	1.0025
+#endif
+ 
+ # Antenna check parameters
+ # (to be completed)
+ model partial
+ antenna poly sidewall 200 none
+ antenna allcont surface 10 none
+ antenna via1 surface 20 none
+#ifdef METALS3 || METALS4 || METALS5 || METALS6
+ antenna via2 surface 20 none
+#endif
+#ifdef METALS4 || METALS5 || METALS6
+ antenna via3 surface 20 none
+#endif
+#ifdef METALS5 || METALS6
+ antenna via4 surface 20 none
+#endif
+#ifdef METALS6
+ antenna viatp surface 20 none
+#endif
+#ifdef MIM
+ antenna mimcc surface 20 none
+#endif
+ antenna m1,m2 sidewall 400 none
+#ifdef METALS3 || METALS4 || METALS5 || METALS6
+ antenna m3 sidewall 400 none
+#endif
+#ifdef METALS4 || METALS5 || METALS6
+ antenna m4 sidewall 400 none
+#endif
+#ifdef METALS5 || METALS6
+ antenna m5 sidewall 400 none
+#endif
+#ifdef METALS6
+ antenna mtp sidewall 400 none
+#endif
+
+ tiedown alldiffnonfet
+
+ substrate *ppdiff,*mvppdiff,space/w,pwell well $SUB -dnwell,isosub
+
+# Layer resistance
+
+variants ()
+
+# Resistances are in milliohms per square
+# Optional 3rd argument is the corner adjustment fraction
+# See document 180MCU_YI-141-EP059-01_10.pdf
+
+ resist (nwell,dnwell)/well      1000000
+ resist (pwell)/well	 	 3250000
+
+ resist (*ndiff,nsd)/active 	  6300
+ resist (*pdiff,*psd)/active	  7000
+ resist (*mvndiff,mvnsd)/active   6300
+ resist (*mvpdiff,*mvpsd)/active  7000
+
+ resist (allpolynonres)/active    7300
+
+ resist (rnw)/well             1000000 0.5
+ resist (rnd)/active 	 	 60000 0.5
+ resist (rpd)/active 		185000 0.5
+ resist (mvrnd)/active 		 60000 0.5
+ resist (mvrpd)/active 		185000 0.5
+ resist (rnds)/active 	 	  6300 0.5
+ resist (rpds)/active 		  7000 0.5
+ resist (mvrnds)/active		  6300 0.5
+ resist (mvrpds)/active		  7000 0.5
+ resist (rnps)/active	  	  6800 0.5
+ resist (rpps)/active	  	  7300 0.5
+ resist (rpp)/active		350000 0.5
+ resist (rnp)/active		310000 0.5
+#ifdef HRPOLY1K
+ resist (hires,mvhires)/active 1000000 0.5
+#endif (HRPOLY1K)
+
+ resist (allm1)/metal1		    90
+ resist (allm2)/metal2		    90
+#ifdef METALS3
+#ifdef THICKMET3P0
+ resist (allm3)/metal3  	    10
+#elseif defined(THICKMET1P1 || THICKMET0P9)
+ resist (allm3)/metal3  	    40
+#else (!(THICKMET3P0 || THICKMET1P1 || THICKMET0P9))
+ resist (allm3)/metal3  	    60
+#endif (!(THICKMET3P0 || THICKMET1P1 || THICKMET0P9))
+#endif (METALS3)
+#ifdef METALS4 || METALS5 || METALS6
+ resist (allm3)/metal3	            90
+#endif (METALS4 || METALS5 || METALS6)
+
+#ifdef METALS4
+#ifdef THICKMET3P0
+ resist (allm4)/metal4  	    10
+#elseif defined(THICKMET1P1 || THICKMET0P9)
+ resist (allm4)/metal4  	    40
+#else (!(THICKMET3P0 || THICKMET1P1 || THICKMET0P9))
+ resist (allm4)/metal4  	    60
+#endif (!(THICKMET3P0 || THICKMET1P1 || THICKMET0P9))
+#endif (METALS4)
+#ifdef METALS5 || METALS6
+ resist (allm4)/metal4  	    90
+#endif (METALS5 || METALS6)
+
+#ifdef METALS5
+#ifdef THICKMET3P0
+ resist (allm5)/metal5  	    10
+#elseif defined(THICKMET1P1 || THICKMET0P9)
+ resist (allm5)/metal5  	    40
+#else (!(THICKMET3P0 || THICKMET1P1 || THICKMET0P9))
+ resist (allm5)/metal5  	    60
+#endif (!(THICKMET3P0 || THICKMET1P1 || THICKMET0P9))
+#endif (METALS5)
+#ifdef METALS6
+ resist (allm5)/metal5  	    90
+#endif (METALS6)
+
+#ifdef METALS6
+#ifdef THICKMET3P0
+ resist (allmtp)/metaltp  	   10
+#elseif defined(THICKMET1P1 || THICKMET0P9)
+ resist (allmtp)/metaltp  	    40
+#else (!(THICKMET3P0 || THICKMET1P1 || THICKMET0P9))
+ resist (allmtp)/metaltp  	    60
+#endif (!(THICKMET3P0 || THICKMET1P1 || THICKMET0P9))
+#endif (METALS6)
+
+ contact ndc,nsc		  6300
+ contact pdc,psc		  5200
+ contact mvndc,mvnsc		  6300
+ contact mvpdc,mvpsc		  5200
+ contact pc			  8000
+ contact m2c			  4500
+#ifdef METALS3 || METALS4 || METALS5 || METALS6
+ contact m3c			  4500
+#endif (METALS3 || METALS4 || METALS5 || METALS6)
+#ifdef METALS4 || METALS5 || METALS6
+ contact via3			  4500
+#endif (METALS4 || METALS5 || METALS6)
+#ifdef METALS5 || METALS6
+ contact via4			  4500
+#endif (METALS5 || METALS6)
+#ifdef MIM
+ contact mimcc			  4500
+#endif (MIM)
+#ifdef METALS6
+ contact viatp			  4500
+#endif (METALS6)
+
+variants (hrhc),(hrlc)
+
+ # High-end corner resistances (milliohms per square)
+
+ resist (nwell,dnwell)/well      1200000
+ resist (pwell)/well	 	 3250000
+
+ resist (*ndiff,nsd)/active 	 15000
+ resist (*pdiff,*psd)/active	 15000
+ resist (*mvndiff,mvnsd)/active  15000
+ resist (*mvpdiff,*mvpsd)/active 15000
+
+ resist (allpolynonres)/active   15000
+
+ resist (rnw)/well             1200000 0.5
+ resist (rnd)/active 	 	 75000 0.5
+ resist (rpd)/active 		225000 0.5
+ resist (mvrnd)/active 		 75000 0.5
+ resist (mvrpd)/active 		225000 0.5
+ resist (rnds)/active 	 	 15000 0.5
+ resist (rpds)/active 		 15000 0.5
+ resist (mvrnds)/active		 15000 0.5
+ resist (mvrpds)/active		 15000 0.5
+ resist (rnps)/active	  	 15000 0.5
+ resist (rpps)/active	  	 15000 0.5
+ resist (rpp)/active		420000 0.5
+ resist (rnp)/active		370000 0.5
+#ifdef HRPOLY1K
+ resist (hires,mvhires)/active	1200000 0.5
+#endif (HRPOLY1K)
+
+ resist (allm1)/metal1		   104
+ resist (allm2)/metal2		   104
+#ifdef METALS3
+#ifdef THICKMET3P0
+ resist (allm3)/metal3  	    15
+#elseif defined(THICKMET1P1 || THICKMET0P9)
+ resist (allm3)/metal3  	    49
+#else (!(THICKMET3P0 || THICKMET1P1 || THICKMET0P9))
+ resist (allm3)/metal3  	    70
+#endif (!(THICKMET3P0 || THICKMET1P1 || THICKMET0P9))
+#endif (METALS3)
+#ifdef METALS4 || METALS5 || METALS6
+ resist (allm3)/metal3	           104
+#endif (METALS4 || METALS5 || METALS6)
+
+#ifdef METALS4
+#ifdef THICKMET3P0
+ resist (allm4)/metal4  	    14
+#elseif defined(THICKMET1P1 || THICKMET0P9)
+ resist (allm4)/metal4  	    49
+#else (!(THICKMET3P0 || THICKMET1P1 || THICKMET0P9))
+ resist (allm4)/metal4  	    70
+#endif (!(THICKMET3P0 || THICKMET1P1 || THICKMET0P9))
+#endif (METALS4)
+#ifdef METALS5 || METALS6
+ resist (allm4)/metal4  	   104
+#endif (METALS5 || METALS6)
+
+#ifdef METALS5
+#ifdef THICKMET3P0
+ resist (allm5)/metal5  	    14
+#elseif defined(THICKMET1P1 || THICKMET0P9)
+ resist (allm5)/metal5  	    49
+#else (!(THICKMET3P0 || THICKMET1P1 || THICKMET0P9))
+ resist (allm5)/metal5  	    70
+#endif (!(THICKMET3P0 || THICKMET1P1 || THICKMET0P9))
+#endif (METALS5)
+#ifdef METALS6
+ resist (allm5)/metal5  	   104
+#endif (METALS6)
+
+#ifdef METALS6
+#ifdef THICKMET3P0
+ resist (allmtp)/metaltp  	    14
+#elseif defined(THICKMET1P1 || THICKMET0P9)
+ resist (allmtp)/metaltp  	    49
+#else (!(THICKMET3P0 || THICKMET1P1 || THICKMET0P9))
+ resist (allmtp)/metaltp  	    70
+#endif (!(THICKMET3P0 || THICKMET1P1 || THICKMET0P9))
+#endif (METALS6)
+
+ contact ndc,nsc		 15000
+ contact pdc,psc		 15000
+ contact mvndc,mvnsc		 15000
+ contact mvpdc,mvpsc		 15000
+ contact pc			 15000
+ contact m2c			 15000
+#ifdef METALS3 || METALS4 || METALS5 || METALS6
+ contact m3c			 15000
+#endif (METALS3 || METALS4 || METALS5 || METALS6)
+#ifdef METALS4 || METALS5 || METALS6
+ contact via3			 15000
+#endif (METALS4 || METALS5 || METALS6)
+#ifdef METALS5 || METALS6
+ contact via4			 15000
+#endif (METALS5 || METALS6)
+#ifdef MIM
+ contact mimcc			 15000
+#endif (MIM)
+#ifdef METALS6
+ contact viatp			 15000
+#endif (METALS6)
+
+variants (lrhc),(lrlc)
+
+ # Low-end corner resistances (milliohms per square)
+
+ resist (nwell,dnwell)/well       800000
+ resist (pwell)/well	 	 3250000
+
+ resist (*ndiff,nsd)/active 	  1000
+ resist (*pdiff,*psd)/active	  1000
+ resist (*mvndiff,mvnsd)/active   1000
+ resist (*mvpdiff,*mvpsd)/active  1000
+
+ resist (allpolynonres)/active    1000
+
+ resist (rnw)/well             8000000 0.5
+ resist (rnd)/active 	 	 45000 0.5
+ resist (rpd)/active 		145000 0.5
+ resist (mvrnd)/active 		 45000 0.5
+ resist (mvrpd)/active 		145000 0.5
+ resist (rnds)/active 	 	  1000 0.5
+ resist (rpds)/active 		  1000 0.5
+ resist (mvrnds)/active		  1000 0.5
+ resist (mvrpds)/active		  1000 0.5
+ resist (rnps)/active	  	  1000 0.5
+ resist (rpps)/active	  	  1000 0.5
+ resist (rpp)/active		280000 0.5
+ resist (rnp)/active		250000 0.5
+#ifdef HRPOLY1K
+ resist (hires,mvhires)/active  800000 0.5
+#endif (HRPOLY1K)
+
+ resist (allm1)/metal1		    76
+ resist (allm2)/metal2		    76
+#ifdef METALS3
+#ifdef THICKMET3P0
+ resist (allm3)/metal3  	     6
+#elseif defined(THICKMET1P1 || THICKMET0P9)
+ resist (allm3)/metal3  	    31
+#else (!(THICKMET3P0 || THICKMET1P1 || THICKMET0P9))
+ resist (allm3)/metal3  	    50
+#endif (!(THICKMET3P0 || THICKMET1P1 || THICKMET0P9))
+#endif (METALS3)
+#ifdef METALS4 || METALS5 || METALS6
+ resist (allm3)/metal3	            76
+#endif (METALS4 || METALS5 || METALS6)
+
+#ifdef METALS4
+#ifdef THICKMET3P0
+ resist (allm4)/metal4  	     6
+#elseif defined(THICKMET1P1 || THICKMET0P9)
+ resist (allm4)/metal4  	    31
+#else (!(THICKMET3P0 || THICKMET1P1 || THICKMET0P9))
+ resist (allm4)/metal4  	    50
+#endif (!(THICKMET3P0 || THICKMET1P1 || THICKMET0P9))
+#endif (METALS4)
+#ifdef METALS5 || METALS6
+ resist (allm4)/metal4  	    76
+#endif (METALS5 || METALS6)
+
+#ifdef METALS5
+#ifdef THICKMET3P0
+ resist (allm5)/metal5  	     6
+#elseif defined(THICKMET1P1 || THICKMET0P9)
+ resist (allm5)/metal5  	    31
+#else (!(THICKMET3P0 || THICKMET1P1 || THICKMET0P9))
+ resist (allm5)/metal5  	    50
+#endif (!(THICKMET3P0 || THICKMET1P1 || THICKMET0P9))
+#endif (METALS5)
+#ifdef METALS6
+ resist (allm5)/metal5  	    76
+#endif (METALS6)
+
+#ifdef METALS6
+#ifdef THICKMET3P0
+ resist (allmtp)/metaltp  	     6
+#elseif defined(THICKMET1P1 || THICKMET0P9)
+ resist (allmtp)/metaltp  	    31
+#else (!(THICKMET3P0 || THICKMET1P1 || THICKMET0P9))
+ resist (allmtp)/metaltp  	    50
+#endif (!(THICKMET3P0 || THICKMET1P1 || THICKMET0P9))
+#endif (METALS6)
+
+ contact ndc,nsc		     0
+ contact pdc,psc		     0
+ contact mvndc,mvnsc		     0
+ contact mvpdc,mvpsc		     0
+ contact pc			     0
+ contact m2c			     0
+#ifdef METALS3 || METALS4 || METALS5 || METALS6
+ contact m3c			     0
+#endif (METALS3 || METALS4 || METALS5 || METALS6)
+#ifdef METALS4 || METALS5 || METALS6
+ contact via3			     0
+#endif (METALS4 || METALS5 || METALS6)
+#ifdef METALS5 || METALS6
+ contact via4			     0
+#endif (METALS5 || METALS6)
+#ifdef MIM
+ contact mimcc			     0
+#endif (MIM)
+#ifdef METALS6
+ contact viatp			     0
+#endif (METALS6)
+
+variants *
+
+ # These types should not be considered as electrical nodes
+ resist comment			None
+
+#-------------------------------------------------------------------------
+# Parasitic capacitance values:
+#-------------------------------------------------------------------------
+# This uses the new "default" definitions that determine the intervening
+# planes from the planeorder stack, take care of the reflexive sideoverlap
+# definitions, and generally clean up the section and make it more readable.
+#
+# Also uses "units microns" statement, so all parasitic capacitance values
+# are taken directly from the source document PDS_035_03, in units of
+# aF/um^2 for area caps and aF/um for perimeter and sidewall caps.
+#-------------------------------------------------------------------------
+# Remember that device capacitances to substrate are taken care of by the
+# models.  Thus, active and poly definitions ignore all "fet" types.
+# fet types are excluded when computing parasitic capacitance to
+# active from layers above them because poly is a shield; fet types are
+# included for parasitics from layers above to poly.  Resistor types
+# should be removed from all parasitic capacitance calculations, or else
+# they just create floating caps.  Technically, the capacitance probably
+# should be split between the two terminals.  Unsure of the correct model.
+# Because rnw is on the well plane, "defaultareacap" does not work for
+# planes above diffusion because rnw cannot be removed from types on the
+# well plane.  Because of this, use the normal "areacap" to specify cap
+# to substrate, and "defaultoverlap" to specify cap to nwell (but not rnw). 
+#-------------------------------------------------------------------------
+
+variants ()
+# Nominal capacitances
+
+#n-well
+defaultareacap     nwell well 120
+
+#n-active 
+# Rely on device models to capture *ndiff area cap
+# Do not extract parasitics from resistors
+# defaultareacap     allnactivenonfet active 790
+# defaultperimeter   allnactivenonfet active 280
+
+#p-active
+# Rely on device models to capture *pdiff area cap
+# Do not extract parasitics from resistors
+# defaultareacap     allpactivenonfet active 810
+# defaultperimeter   allpactivenonfet active 300
+
+#poly
+# Do not extract parasitics from resistors
+# defaultsidewall    allpolynonfet active  22
+# defaultareacap     allpolynonfet active  105
+# defaultperimeter   allpolynonfet active   57
+
+ defaultsidewall    *poly active  16.46
+ defaultareacap     *poly active nwell,obswell,pwell well  110.677
+ defaultperimeter   *poly active nwell,obswell,pwell well  51.29
+
+#metal1
+ defaultsidewall    allm1 metal1       28.01
+ defaultareacap     allm1 metal1 nwell,obswell,pwell well  29.3046
+ defaultperimeter   allm1 metal1 nwell,obswell,pwell well  25.783
+ defaultoverlap     allm1 metal1 nwell well 29.3046
+
+#metal1->diff
+ defaultoverlap     allm1 metal1 allactivenonfet active 39.2181
+ defaultsideoverlap allm1 metal1 allactivenonfet active 30.683
+
+#metal1->poly
+ defaultoverlap     allm1 metal1 allpolynonres active 51.4351
+ defaultsideoverlap allm1 metal1 allpolynonres active 35.602
+
+#metal2
+ defaultsidewall    allm2 metal2      30.381
+ defaultareacap     allm2 metal2 nwell,obswell,pwell well 15.0162
+ defaultperimeter   allm2 metal2 nwell,obswell,pwell well 18.263
+ defaultoverlap     allm2 metal2 nwell well 15.0162
+#metal2->active
+ defaultoverlap     allm2 metal2 allactivenonfet active 17.2506
+ defaultsideoverlap allm2 metal2 allactivenonfet active 20.018
+
+#metal2->poly
+ defaultoverlap     allm2 metal2 allpolynonres active 19.2632
+ defaultsideoverlap allm2 metal2 allpolynonres active 21.531
+
+#metal2->metal1
+ defaultoverlap     allm2 metal2 allm1 metal1 59.0279
+ defaultsideoverlap allm2 metal2 allm1 metal1 40.880
+
+#ifdef METALS3 || METALS4 || METALS5 || METALS6
+#metal3
+ defaultsidewall    allm3 metal3     30.774
+ defaultareacap     allm3 metal3 nwell,obswell,pwell well 10.0944
+ defaultoverlap     allm3 metal3 nwell well 10.0944
+ defaultperimeter   allm3 metal3 nwell,obswell,pwell well 13.52
+
+#metal3->active
+ defaultoverlap     allm3 metal3 allactive active 11.0571
+ defaultsideoverlap allm3 metal3 allactive active 14.36
+
+#metal3->poly
+ defaultoverlap     allm3 metal3 allpolynonres active 11.8507
+ defaultsideoverlap allm3 metal3 allpolynonres active 15.054
+
+#metal3->metal1
+ defaultoverlap     allm3 metal3 allm1 metal1 20.2381
+ defaultsideoverlap allm3 metal3 allm1 metal1 21.705
+
+#metal3->metal2
+ defaultoverlap     allm3 metal3 allm2 metal2 59.0279
+ defaultsideoverlap allm3 metal3 allm2 metal2 40.482
+#endif (METALS3 || METALS4 || METALS5 || METALS6)
+
+#ifdef METALS4 || METALS5 || METALS6
+#metal4
+ defaultsidewall    allm4 metal4       30.994
+ defaultareacap     allm4 metal4 nwell,obswell,pwell well 7.6025
+ defaultoverlap     allm4 metal4 nwell well 7.6025
+ defaultperimeter   allm4 metal4 well  10.649
+
+#metal4->active
+ defaultoverlap     allm4 metal4 allactivenonfet active 8.1360
+ defaultsideoverlap allm4 metal4 allactivenonfet active 11.129
+
+#metal4->poly
+ defaultoverlap     allm4 metal4 allpolynonres active 8.5577
+ defaultsideoverlap allm4 metal4 allpolynonres active 11.505
+
+#metal4->metal1
+ defaultoverlap     allm4 metal4 allm1 metal1 12.2127
+ defaultsideoverlap allm4 metal4 allm1 metal1 14.829
+
+#metal4->metal2
+ defaultoverlap     allm4 metal4 allm2 metal2 20.2381
+ defaultsideoverlap allm4 metal4 allm2 metal2 21.025
+
+#metal4->metal3
+ defaultoverlap     allm4 metal4 allm3 metal3 59.0279
+ defaultsideoverlap allm4 metal4 allm3 metal3 39.786
+#endif (METALS4 || METALS5 || METALS6)
+
+#ifdef METALS5
+#metal5
+ defaultsidewall    allm5 metal5       54.148
+#endif
+#ifdef METALS6
+ defaultsidewall    allm5 metal5       31.121
+#endif
+
+#ifdef METALS5 || METALS6
+ defaultareacap     allm5 metal5 nwell,obswell,pwell well 5.7979
+ defaultoverlap     allm5 metal5 nwell well 5.7979
+ defaultperimeter   allm5 metal5 well  10.850
+
+#metal5->active
+ defaultoverlap     allm5 metal5 allactivenonfet active 6.1031
+ defaultsideoverlap allm5 metal5 allactivenonfet active 11.258
+
+#metal5->poly
+ defaultoverlap     allm5 metal5 allpolynonres active 6.3374
+ defaultsideoverlap allm5 metal5 allpolynonres active 11.570
+
+#metal5->metal1
+ defaultoverlap     allm5 metal5 allm1 metal1 8.1418
+ defaultsideoverlap allm5 metal5 allm1 metal1 13.958
+
+#metal5->metal2
+ defaultoverlap     allm5 metal5 allm2 metal2 11.0677
+ defaultsideoverlap allm5 metal5 allm2 metal2 17.640
+
+#metal5->metal3
+ defaultoverlap     allm5 metal5 allm3 metal3 17.2765
+ defaultsideoverlap allm5 metal5 allm3 metal3 24.286
+
+#metal5->metal4
+ defaultoverlap     allm5 metal5 allm4 metal4 39.3519
+ defaultsideoverlap allm5 metal5 allm4 metal4 39.586
+#endif (METALS5 || METALS6)
+
+#ifdef METALS6
+#metaltp
+ defaultsidewall    allmtp metaltp      54.335
+ defaultareacap     allmtp metaltp nwell,obswell,pwell well 4.8793
+ defaultoverlap     allmtp metaltp nwell well 4.8793
+ defaultperimeter   allmtp metaltp well  9.5950
+
+#metaltp->active
+ defaultoverlap     allmtp metaltp allactivenonfet active 5.0937
+ defaultsideoverlap allmtp metaltp allactivenonfet active 9.8790
+
+#metaltp->poly
+ defaultoverlap     allmtp metaltp allpolynonres active 5.2558
+ defaultsideoverlap allmtp metaltp allpolynonres active 10.128
+
+#metaltp->metal1
+ defaultoverlap     allmtp metaltp allm1 metal1 6.4394
+ defaultsideoverlap allmtp metaltp allm1 metal1 11.765
+
+#metaltp->metal2
+ defaultoverlap     allmtp metaltp allm2 metal2 8.1418
+ defaultsideoverlap allmtp metaltp allm2 metal2 13.958
+
+#metaltp->metal3
+ defaultoverlap     allmtp metaltp allm3 metal3 11.0677
+ defaultsideoverlap allmtp metaltp allm3 metal3 17.640
+
+#metaltp->metal4
+ defaultoverlap     allmtp metaltp allm3 metal3 17.2765
+ defaultsideoverlap allmtp metaltp allm3 metal3 24.286
+
+#metaltp->metal5
+ defaultoverlap     allmtp metaltp allm3 metal3 39.3519
+ defaultsideoverlap allmtp metaltp allm3 metal3 39.586
+#endif (METALS6)
+
+#-------------------------------------------------------------------------
+# Parasitic capacitance values for maximum corner
+#-------------------------------------------------------------------------
+
+variants (hrhc),(lrhc)
+# Maximum corner capacitances
+
+#n-well
+defaultareacap     nwell well 120
+
+#n-active 
+# Rely on device models to capture *ndiff area cap
+# Do not extract parasitics from resistors
+# defaultareacap     allnactivenonfet active 790
+# defaultperimeter   allnactivenonfet active 280
+
+#p-active
+# Rely on device models to capture *pdiff area cap
+# Do not extract parasitics from resistors
+# defaultareacap     allpactivenonfet active 810
+# defaultperimeter   allpactivenonfet active 300
+
+#poly
+# Do not extract parasitics from resistors
+# defaultsidewall    allpolynonfet active  22
+# defaultareacap     allpolynonfet active  105
+# defaultperimeter   allpolynonfet active   57
+
+ defaultsidewall    *poly active  16.56
+ defaultareacap     *poly active nwell,obswell,pwell well  130.2
+ defaultperimeter   *poly active nwell,obswell,pwell well  54.018
+
+#metal1
+ defaultsidewall    allm1 metal1       29.294
+ defaultareacap     allm1 metal1 nwell,obswell,pwell well  33.126
+ defaultperimeter   allm1 metal1 nwell,obswell,pwell well  25.790
+ defaultoverlap     allm1 metal1 nwell well 33.126
+
+#metal1->diff
+ defaultoverlap     allm1 metal1 allactivenonfet active 43.636
+ defaultsideoverlap allm1 metal1 allactivenonfet active 30.445
+
+#metal1->poly
+ defaultoverlap     allm1 metal1 allpolynonres active 60.321
+ defaultsideoverlap allm1 metal1 allpolynonres active 36.440
+
+#metal2
+ defaultsidewall    allm2 metal2      31.727
+ defaultareacap     allm2 metal2 nwell,obswell,pwell well 16.472
+ defaultperimeter   allm2 metal2 nwell,obswell,pwell well 18.124
+ defaultoverlap     allm2 metal2 nwell well 16.472
+#metal2->active
+ defaultoverlap     allm2 metal2 allactivenonfet active 18.713
+ defaultsideoverlap allm2 metal2 allactivenonfet active 19.744
+
+#metal2->poly
+ defaultoverlap     allm2 metal2 allpolynonres active 21.231
+ defaultsideoverlap allm2 metal2 allpolynonres active 21.467
+
+#metal2->metal1
+ defaultoverlap     allm2 metal2 allm1 metal1 73.632
+ defaultsideoverlap allm2 metal2 allm1 metal1 43.788
+
+#ifdef METALS3 || METALS4 || METALS5 || METALS6
+#metal3
+ defaultsidewall    allm3 metal3     32.049
+ defaultoverlap     allm3 metal3 nwell well 11.910
+ defaultareacap     allm3 metal3 nwell,obswell,pwell well 10.961
+ defaultperimeter   allm3 metal3 nwell,obswell,pwell well 13.270
+
+#metal3->active
+ defaultoverlap     allm3 metal3 allactive active 11.910
+ defaultsideoverlap allm3 metal3 allactive active 14.034
+
+#metal3->poly
+ defaultoverlap     allm3 metal3 allpolynonres active 12.883
+ defaultsideoverlap allm3 metal3 allpolynonres active 14.812
+
+#metal3->metal1
+ defaultoverlap     allm3 metal3 allm1 metal1 22.675
+ defaultsideoverlap allm3 metal3 allm1 metal1 21.903
+
+#metal3->metal2
+ defaultoverlap     allm3 metal3 allm2 metal2 73.632
+ defaultsideoverlap allm3 metal3 allm2 metal2 43.400
+#endif (METALS3 || METALS4 || METALS5 || METALS6)
+
+#ifdef METALS4 || METALS5 || METALS6
+#metal4
+ defaultsidewall    allm4 metal4       32.265
+ defaultareacap     allm4 metal4 nwell,obswell,pwell well 8.213
+ defaultoverlap     allm4 metal4 nwell well 8.213
+ defaultperimeter   allm4 metal4 well  10.397
+
+#metal4->active
+ defaultoverlap     allm4 metal4 allactivenonfet active 8.735
+ defaultsideoverlap allm4 metal4 allactivenonfet active 10.831
+
+#metal4->poly
+ defaultoverlap     allm4 metal4 allpolynonres active 9.247
+ defaultsideoverlap allm4 metal4 allpolynonres active 11.247
+
+#metal4->metal1
+ defaultoverlap     allm4 metal4 allm1 metal1 13.400
+ defaultsideoverlap allm4 metal4 allm1 metal1 14.625
+
+#metal4->metal2
+ defaultoverlap     allm4 metal4 allm2 metal2 22.674
+ defaultsideoverlap allm4 metal4 allm2 metal2 21.263
+
+#metal4->metal3
+ defaultoverlap     allm4 metal4 allm3 metal3 73.63
+ defaultsideoverlap allm4 metal4 allm3 metal3 42.64
+#endif (METALS4 || METALS5 || METALS6)
+
+#ifdef METALS5 || METALS6
+#metal5
+ defaultsidewall    allm5 metal5       57.012
+ defaultareacap     allm5 metal5 nwell,obswell,pwell well 6.241
+ defaultoverlap     allm5 metal5 nwell well 6.241
+ defaultperimeter   allm5 metal5 well  10.676
+
+#metal5->active
+ defaultoverlap     allm5 metal5 allactivenonfet active 6.537
+ defaultsideoverlap allm5 metal5 allactivenonfet active 11.074
+
+#metal5->poly
+ defaultoverlap     allm5 metal5 allpolynonres active 6.820
+ defaultsideoverlap allm5 metal5 allpolynonres active 11.431
+
+#metal5->metal1
+ defaultoverlap     allm5 metal5 allm1 metal1 8.841
+ defaultsideoverlap allm5 metal5 allm1 metal1 13.909
+
+#metal5->metal2
+ defaultoverlap     allm5 metal5 allm2 metal2 12.108
+ defaultsideoverlap allm5 metal5 allm2 metal2 17.722
+
+#metal5->metal3
+ defaultoverlap     allm5 metal5 allm3 metal3 19.207
+ defaultsideoverlap allm5 metal5 allm3 metal3 24.724
+
+#metal5->metal4
+ defaultoverlap     allm5 metal5 allm4 metal4 46.18
+ defaultsideoverlap allm5 metal5 allm4 metal4 41.628
+#endif (METALS5 || METALS6)
+
+#ifdef METALS6
+#metaltp
+ defaultsidewall    allmtp metaltp       57.187
+ defaultareacap     allmtp metaltp nwell,obswell,pwell well 5.242
+ defaultoverlap     allmtp metaltp nwell well 5.242
+ defaultperimeter   allmtp metaltp well  9.407
+
+#metaltp->active
+ defaultoverlap     allmtp metaltp allactivenonfet active 5.450
+ defaultsideoverlap allmtp metaltp allactivenonfet active 9.679
+
+#metaltp->poly
+ defaultoverlap     allmtp metaltp allpolynonres active 5.645
+ defaultsideoverlap allmtp metaltp allpolynonres active 9.925
+
+#metaltp->metal1
+ defaultoverlap     allmtp metaltp allm1 metal1 6.962
+ defaultsideoverlap allmtp metaltp allm1 metal1 11.549
+
+#metaltp->metal2
+ defaultoverlap     allmtp metaltp allm2 metal2 8.841
+ defaultsideoverlap allmtp metaltp allm2 metal2 13.909
+
+#metaltp->metal3
+ defaultoverlap     allmtp metaltp allm3 metal3 12.211
+ defaultsideoverlap allmtp metaltp allm3 metal3 17.215
+
+#metaltp->metal4
+ defaultoverlap     allmtp metaltp allm3 metal3 19.207
+ defaultsideoverlap allmtp metaltp allm3 metal3 24.725
+
+#metaltp->metal5
+ defaultoverlap     allmtp metaltp allm3 metal3 46.418
+ defaultsideoverlap allmtp metaltp allm3 metal3 41.628
+#endif (METALS6)
+
+#-------------------------------------------------------------------------
+# Parasitic capacitance values for minimum corner
+#-------------------------------------------------------------------------
+
+variants (hrlc),(lrlc)
+# Minimum corner capacitances
+
+#n-well
+defaultareacap     nwell well 120
+
+#n-active 
+# Rely on device models to capture *ndiff area cap
+# Do not extract parasitics from resistors
+# defaultareacap     allnactivenonfet active 790
+# defaultperimeter   allnactivenonfet active 280
+
+#p-active
+# Rely on device models to capture *pdiff area cap
+# Do not extract parasitics from resistors
+# defaultareacap     allpactivenonfet active 810
+# defaultperimeter   allpactivenonfet active 300
+
+#poly
+# Do not extract parasitics from resistors
+# defaultsidewall    allpolynonfet active  22
+# defaultareacap     allpolynonfet active  105
+# defaultperimeter   allpolynonfet active   57
+
+ defaultsidewall    *poly active  16.388
+ defaultareacap     *poly active nwell,obswell,pwell well  96.241
+ defaultperimeter   *poly active nwell,obswell,pwell well  48.943
+
+#metal1
+ defaultsidewall    allm1 metal1     26.630   
+ defaultareacap     allm1 metal1 nwell,obswell,pwell well  26.274
+ defaultperimeter   allm1 metal1 nwell,obswell,pwell well  25.666
+ defaultoverlap     allm1 metal1 nwell well 26.274
+
+#metal1->diff
+ defaultoverlap     allm1 metal1 allactivenonfet active 35.612
+ defaultsideoverlap allm1 metal1 allactivenonfet active 30.684
+
+#metal1->poly
+ defaultoverlap     allm1 metal1 allpolynonres active 44.831
+ defaultsideoverlap allm1 metal1 allpolynonres active 34.738
+
+#metal2
+ defaultsidewall    allm2 metal2     29.023 
+ defaultareacap     allm2 metal2 nwell,obswell,pwell well 13.797
+ defaultperimeter   allm2 metal2 nwell,obswell,pwell well 18.332
+ defaultoverlap     allm2 metal2 nwell well 13.797
+#metal2->active
+ defaultoverlap     allm2 metal2 allactivenonfet active 16.000
+ defaultsideoverlap allm2 metal2 allactivenonfet active 20.206
+
+#metal2->poly
+ defaultoverlap     allm2 metal2 allpolynonres active 17.629
+ defaultsideoverlap allm2 metal2 allpolynonres active 21.511
+
+#metal2->metal1
+ defaultoverlap     allm2 metal2 allm1 metal1 49.258
+ defaultsideoverlap allm2 metal2 allm1 metal1 38.718
+
+#ifdef METALS3 || METALS4 || METALS5 || METALS6
+#metal3
+ defaultsidewall    allm3 metal3     28.809
+ defaultoverlap     allm3 metal3 nwell well 9.355
+ defaultareacap     allm3 metal3 nwell,obswell,pwell well 9.355
+ defaultperimeter   allm3 metal3 nwell,obswell,pwell well 13.710
+
+#metal3->active
+ defaultoverlap     allm3 metal3 allactive active 10.318
+ defaultsideoverlap allm3 metal3 allactive active 14.637
+
+#metal3->poly
+ defaultoverlap     allm3 metal3 allpolynonres active 10.972
+ defaultsideoverlap allm3 metal3 allpolynonres active 15.232
+
+#metal3->metal1
+ defaultoverlap     allm3 metal3 allm1 metal1 18.275
+ defaultsideoverlap allm3 metal3 allm1 metal1 21.483
+
+#metal3->metal2
+ defaultoverlap     allm3 metal3 allm2 metal2 49.258
+ defaultsideoverlap allm3 metal3 allm2 metal2 38.221
+#endif (METALS3 || METALS4 || METALS5 || METALS6)
+
+#ifdef METALS4 || METALS5 || METALS6
+#metal4
+ defaultsidewall    allm4 metal4       29.629
+ defaultareacap     allm4 metal4 nwell,obswell,pwell well 7.076
+ defaultoverlap     allm4 metal4 nwell well 7.076
+ defaultperimeter   allm4 metal4 well  10.870
+
+#metal4->active
+ defaultoverlap     allm4 metal4 allactivenonfet active 7.614
+ defaultsideoverlap allm4 metal4 allactivenonfet active 11.375
+
+#metal4->poly
+ defaultoverlap     allm4 metal4 allpolynonres active 7.964
+ defaultsideoverlap allm4 metal4 allpolynonres active 11.720
+
+#metal4->metal1
+ defaultoverlap     allm4 metal4 allm1 metal1 11.219
+ defaultsideoverlap allm4 metal4 allm1 metal1 14.805
+
+#metal4->metal2
+ defaultoverlap     allm4 metal4 allm2 metal2 18.275
+ defaultsideoverlap allm4 metal4 allm2 metal2 20.801
+
+#metal4->metal3
+ defaultoverlap     allm4 metal4 allm3 metal3 49.258
+ defaultsideoverlap allm4 metal4 allm3 metal3 37.616
+#endif (METALS4 || METALS5 || METALS6)
+
+#ifdef METALS5 || METALS6
+#metal5
+ defaultsidewall    allm5 metal5       51.169
+ defaultareacap     allm5 metal5 nwell,obswell,pwell well 5.414
+ defaultoverlap     allm5 metal5 nwell well 5.414
+ defaultperimeter   allm5 metal5 well  10.992
+
+#metal5->active
+ defaultoverlap     allm5 metal5 allactivenonfet active 5.723
+ defaultsideoverlap allm5 metal5 allactivenonfet active 11.430
+
+#metal5->poly
+ defaultoverlap     allm5 metal5 allpolynonres active 5.919
+ defaultsideoverlap allm5 metal5 allpolynonres active 11.703
+
+#metal5->metal1
+ defaultoverlap     allm5 metal5 allm1 metal1 7.545
+ defaultsideoverlap allm5 metal5 allm1 metal1 13.985
+
+#metal5->metal2
+ defaultoverlap     allm5 metal5 allm2 metal2 10.192
+ defaultsideoverlap allm5 metal5 allm2 metal2 17.610
+
+#metal5->metal3
+ defaultoverlap     allm5 metal5 allm3 metal3 15.699
+ defaultsideoverlap allm5 metal5 allm3 metal3 23.834
+
+#metal5->metal4
+ defaultoverlap     allm5 metal5 allm4 metal4 34.153
+ defaultsideoverlap allm5 metal5 allm4 metal4 37.782
+#endif (METALS5 || METALS6)
+
+#ifdef METALS6
+#metaltp
+ defaultsidewall    allmtp metaltp       51.353
+ defaultareacap     allmtp metaltp nwell,obswell,pwell well 4.563
+ defaultoverlap     allmtp metaltp nwell well 4.563
+ defaultperimeter   allmtp metaltp well  9.764
+
+#metaltp->active
+ defaultoverlap     allmtp metaltp allactivenonfet active 4.781
+ defaultsideoverlap allmtp metaltp allactivenonfet active 10.070
+
+#metaltp->poly
+ defaultoverlap     allmtp metaltp allpolynonres active 4.917
+ defaultsideoverlap allmtp metaltp allpolynonres active 10.263
+
+#metaltp->metal1
+ defaultoverlap     allmtp metaltp allm1 metal1 5.990
+ defaultsideoverlap allmtp metaltp allm1 metal1 11.858
+
+#metaltp->metal2
+ defaultoverlap     allmtp metaltp allm2 metal2 7.545
+ defaultsideoverlap allmtp metaltp allm2 metal2 13.985
+
+#metaltp->metal3
+ defaultoverlap     allmtp metaltp allm3 metal3 10.192
+ defaultsideoverlap allmtp metaltp allm3 metal3 17.610
+
+#metaltp->metal4
+ defaultoverlap     allmtp metaltp allm3 metal3 15.699
+ defaultsideoverlap allmtp metaltp allm3 metal3 23.834
+
+#metaltp->metal5
+ defaultoverlap     allmtp metaltp allm3 metal3 34.153
+ defaultsideoverlap allmtp metaltp allm3 metal3 37.782
+#endif (METALS6)
+
+#-------------------------------------------------------------------------
+
+variants *
+
+# Devices:
+# All devices except diodes are modeled as subcircuits
+
+# device list:
+#  nmos_3p3		mosfet
+#  pmos_3p3		mosfet
+#  nmos_6p0		mosfet (thick oxide)
+#  pmos_6p0		mosfet (thick oxide)
+#  nmos_6p0_nat		mosfet (native Vt)
+#  nmos_3p3_sab		mosfet (unsalicided drain)
+#  pmos_3p3_sab		mosfet (unsalicided drain)
+#  nmos_6p0_sab		mosfet (unsalicided drain, thick oxide)
+#  pmos_6p0_sab		mosfet (unsalicided drain, thick oxide)
+#  nmos_10p0_asym	LDNMOS (extended drain)
+#  pmos_10p0_asym	LDPMOS (extended drain)
+#
+#  np_3p3		diode  (N+/pwell)
+#  pn_3p3		diode  (P+/nwell)
+#  np_6p0		diode  (N+/pwell, high voltage)
+#  pn_6p0		diode  (P+/nwell, high voltage)
+#  nwp_3p3		diode  (nwell/pwell)
+#  nwp_6p0		diode  (nwell/pwell, high voltage)
+#  dnwpw		diode  (pwell/dnwell)
+#  dnwps		diode  (dnwll/substrate)
+#  sc_diode		diode  (Schottky)
+#
+#  vpnp_WxL		BJT    (10x10, 5x5, 0.42x10, 0.42x5 emitter sizes)
+#  vnpn_WxL		BJT    (10x10, 5x5, 0.54x16, 0.54x8, 0.54x4, 0.54x2)
+#
+#  npolyf_u		resistor (N+ poly, unsalicided)
+#  ppolyf_u		resistor (P+ poly, unsalicided)
+#  ppolyf_u_1k		resistor (high res resistor)*
+#  ppolyf_u_1k_6p0	resistor (high res resistor, high voltage)*
+#  nplus_u		resistor (N+ diffusion, unsalicided)
+#  pplus_u		resistor (P+ diffusion, unsalicided)
+#  npolyf_s		resistor (N+ poly, salicided)
+#  ppolyf_s		resistor (P+ poly, salicided)
+#  nplus_s		resistor (N+ diffusion, salicided)
+#  pplus_s		resistor (N+ diffusion, salicided)
+#  nwell		resistor (N-well resistor)
+#  rm1			resistor (metal1)
+#  rm2			resistor (metal2)
+#  rm3			resistor (metal3)
+#  rm4			resistor (metal4)
+#  rm5			resistor (metal5)
+#  tm6k			resistor (top metal, 0.6um thick (standard))**
+#  tm9k			resistor (top metal, 0.9um thick)
+#  tm11k		resistor (top metal, 1.1um thick)
+#  tm30k		resistor (top metal, 3.0um thick)
+#
+#  nmoscap_3p3		mosfet	 (source-drain tied)
+#  pmoscap_3p3		mosfet	 (source-drain tied)
+#  nmoscap_6p0		mosfet	 (source-drain tied, high voltage)
+#  pmoscap_6p0		mosfet	 (source-drain tied, high voltage)
+#  nmoscap_3p3_b	mosfet   (n-varactor)
+#  pmoscap_3p3_b	mosfet   (p-varactor)
+#  nmoscap_6p0_b	mosfet   (n-varactor, high voltage)
+#  pmoscap_6p0_b	mosfet   (p-varactor, high voltage)
+#
+#  mim_2p0fF		capacitor (MiM)*
+
+#
+# *Note that there are multiple mutually exclusive process options for the
+#  high sheet rho resistor and MiM capacitor.  This tech file assumes the
+#  options 1kOhm/sq for the resistor and 2fF/um for the MiM capacitor.
+#
+# **The top metal may be any of metal3 to metaltp, depending on the stackup
+
+ device msubcircuit pmos_3p3 pfet pdiff,pdc pdiff,pdc allnwell error l=l w=w
+ device msubcircuit nmos_3p3 nfet ndiff,ndc ndiff,ndc allpsub error l=l w=w
+ device msubcircuit pmos_6p0 mvpfet mvpdiff,mvpdc mvpdiff,mvpdc allnwell error l=l w=w
+ device msubcircuit nmos_6p0 mvnfet mvndiff,mvndc mvndiff,mvndc allpsub error l=l w=w
+ device msubcircuit pmos_3p3_sab pfet pdiffres pdiffres allnwell error l=l w=w
+ device msubcircuit nmos_3p3_sab nfet ndiffres ndiffres allpsub error l=l w=w
+ device msubcircuit pmos_6p0_sab mvpfet mvpdiffres mvpdiffres allnwell error l=l w=w
+ device msubcircuit nmos_6p0_sab mvnfet mvndiffres mvndiffres allpsub error l=l w=w
+ device msubcircuit nmos_6p0_nat mvnnfet mvndiff,mvndiffres,mvndc \
+	mvndiff,mvndiffres,mvndc allpsub error l=l w=w
+ device subcircuit nmoscap_3p3 varactor *nndiff allnwell error l=l w=w
+ device subcircuit nmoscap_6p0 mvvaractor *mvnndiff allnwell error l=l w=w
+
+ device rsubcircuit rm1 rm1 *m1 l=r_length w=r_width
+ device rsubcircuit rm2 rm2 *m2 l=r_length w=r_width
+#ifdef METALS4 || METALS5 || METALS6
+ device rsubcircuit rm3 rm3 *m3 l=r_length w=r_width
+#endif (METALS4 || METALS5 || METALS6)
+#ifdef METALS5 || METALS6
+ device rsubcircuit rm4 rm4 *m4 l=r_length w=r_width
+#endif (METALS5 || METALS6)
+#ifdef METALS6
+ device rsubcircuit rm5 rm5 *m5 l=r_length w=r_width
+#endif (METALS6)
+
+#ifdef THICKMET3P0
+#ifdef METALS3
+ device rsubcircuit tm30k rm3 *m3 l=r_length w=r_width
+#elseif defined (METALS4)
+ device rsubcircuit tm30k rm4 *m4 l=r_length w=r_width
+#elseif defined (METALS5)
+ device rsubcircuit tm30k rm5 *m5 l=r_length w=r_width
+#elseif defined (METALS6)
+ device rsubcircuit tm30k rmtp *mtp l=r_length w=r_width
+#endif
+#elseif defined (THICKMET1P1)
+#ifdef METALS3
+ device rsubcircuit tm11k rm3 *m3 l=r_length w=r_width
+#elseif defined (METALS4)
+ device rsubcircuit tm11k rm4 *m4 l=r_length w=r_width
+#elseif defined (METALS5)
+ device rsubcircuit tm11k rm5 *m5 l=r_length w=r_width
+#elseif defined (METALS6)
+ device rsubcircuit tm11k rmtp *mtp l=r_length w=r_width
+#endif
+#elseif defined (THICKMET0P9)
+#ifdef METALS3
+ device rsubcircuit tm9k  rm3 *m3 l=r_length w=r_width
+#elseif defined (METALS4)
+ device rsubcircuit tm9k  rm4 *m4 l=r_length w=r_width
+#elseif defined (METALS5)
+ device rsubcircuit tm9k  rm5 *m5 l=r_length w=r_width
+#elseif defined (METALS6)
+ device rsubcircuit tm9k  rmtp *mtp l=r_length w=r_width
+#endif
+#else (!(THICKMET3P0 || THICKMET1P1 || THICKMET0P9))
+#ifdef METALS3
+ device rsubcircuit tm6k  rm3 *m3 l=r_length w=r_width
+#elseif defined (METALS4)
+ device rsubcircuit tm6k  rm4 *m4 l=r_length w=r_width
+#elseif defined (METALS5)
+ device rsubcircuit tm6k  rm5 *m5 l=r_length w=r_width
+#elseif defined (METALS6)
+ device rsubcircuit tm6k  rmtp *mtp l=r_length w=r_width
+#endif
+#endif (!(THICKMET3P0 || THICKMET1P1 || THICKMET0P9))
+
+ device rsubcircuit ppolyf_s  rpps   *poly allpsub error l=r_length w=r_width
+ device rsubcircuit npolyf_s  rnps   *poly allpsub error l=r_length w=r_width
+ device rsubcircuit ppolyf_u  rpp    *poly allpsub error l=r_length w=r_width
+ device rsubcircuit npolyf_u  rnp    *poly allpsub error l=r_length w=r_width
+#ifdef HRPOLY1K
+ device rsubcircuit ppolyf_u_1k hires *poly allpsub error l=r_length w=r_width
+ device rsubcircuit ppolyf_u_1k_6p0 mvhires *poly allpsub error l=r_length w=r_width
+#endif (HRPOLY1K)
+ device rsubcircuit pplus_u  rpd  *pdiff allnwell error l=r_length w=r_width
+ device rsubcircuit nplus_u  rnd  *ndiff allpsub error l=r_length w=r_width
+ device rsubcircuit pplus_s  rpds *pdiff allnwell error l=r_length w=r_width
+ device rsubcircuit nplus_s  rnds *ndiff allpsub error l=r_length w=r_width
+ device rsubcircuit pplus_u  mvpdiffres *mvpdiff allnwell error l=r_length w=r_width
+ device rsubcircuit nplus_u  mvndiffres *mvndiff allpsub error l=r_length w=r_width
+ device rsubcircuit nwell rnw   nwell allpsub error l=r_length w=r_width
+
+ device pdiode pn_3p3     *pdiode allnwell a=area p=pj
+ device ndiode np_3p3     *ndiode allpsub a=area p=pj
+ device pdiode pn_6p0     *mvpdiode allnwell a=area p=pj
+ device ndiode np_6p0     *mvndiode allpsub a=area p=pj
+ device ndiode np_6p0_nat *mvnndiode allpsub a=area p=pj
+
+#ifdef MIM
+#ifdef METALS6
+ device csubcircuit mim_2p0fF *mimcap  *m5   l=c_length w=c_width
+#endif
+#ifdef METALS5
+ device csubcircuit mim_2p0fF *mimcap  *m4   l=c_length w=c_width
+#endif
+#ifdef METALS4
+ device csubcircuit mim_2p0fF *mimcap  *m3   l=c_length w=c_width
+#endif
+#ifdef METALS3
+ device csubcircuit mim_2p0fF *mimcap  *m2   l=c_length w=c_width
+#endif
+#endif (MIM)
+
+end
+
+#-----------------------------------------------------
+# Wiring tool definitions
+#-----------------------------------------------------
+
+wiring
+ scalefactor 50
+
+ contact v1 200 m1 5 45 m2 0 45
+#ifdef METALS3 || METALS4 || METALS5 || METALS6
+ contact v2 200 m2 0 45 m3 0 45
+#endif (METALS3 || METALS4 || METALS5 || METALS6)
+#ifdef METALS4 || METALS5 || METALS6
+ contact v3 200 m3 0 45 m4 0 45
+#endif (METALS4 || METALS5 || METALS6)
+#ifdef METALS5 || METALS6
+ contact v4 200 m4 0 45 m5 0 45
+#endif (METALS5 || METALS6)
+#ifdef METALS6
+ contact vtp 370 m3 0 45 mtp 80 80
+#endif (METALS6)
+
+ contact pdc 160 pdiff  70 70 m1 45 0
+ contact ndc 160 ndiff  70 70 m1 45 0
+ contact psc 160 ppdiff 70 70 m1 45 0
+ contact nsc 160 nndiff 70 70 m1 45 0
+ contact pc 160 poly  70 70 m1 45 0
+ contact mvpdc 160 mvpdiff  70 70 m1 45 0
+ contact mvndc 160 mvndiff  70 70 m1 45 0
+ contact mvpsc 160 mvppdiff 70 70 m1 45 0
+ contact mvnsc 160 mvnndiff 70 70 m1 45 0
+
+end
+
+#-----------------------------------------------------
+# Plain old router. . . 
+#-----------------------------------------------------
+
+router
+end
+
+#------------------------------------------------------------
+# Plowing (restored in magic 8.2, need to fill this section)
+#------------------------------------------------------------
+
+plowing
+end
+
+#-----------------------------------------------------------------
+# No special plot layers defined (use default PNM color choices)
+#-----------------------------------------------------------------
+
+plot
+  style pnm
+     default
+     draw fillblock no_color_at_all
+     draw nwell cwell
+     draw pwell cwell
+     draw dnwell cwell
+end
+
diff --git a/gf180mcu/magic/gf180mcu_make_torture.tcl b/gf180mcu/magic/gf180mcu_make_torture.tcl
new file mode 100644
index 0000000..7a28a6e
--- /dev/null
+++ b/gf180mcu/magic/gf180mcu_make_torture.tcl
@@ -0,0 +1,272 @@
+#---------------------------------------
+# Torture test generator for EFGF013H
+# (Specifically for EFGF013H; note that
+# MiM and MoM caps need to be tested in
+# each BEOL stack.)
+#---------------------------------------
+
+namespace path {::tcl::mathop ::tcl::mathfunc}
+
+# Set random seed so that torture test is not totally random.
+srand 1234567
+
+# NxN array MOSFET devices
+
+proc mos_array {n devname startx starty} {
+   suspendall
+   box position $startx $starty
+   set i 0
+   for {set x 0} {$x < $n} {incr x} {
+      for {set y 0} {$y < $n} {incr y} {
+
+         set r [int [* [rand] 20]]
+         set w [+ 0.22 [* 0.5 $r]]
+         set r [int [* [rand] 20]]
+         set l [+ 0.18 [* 0.3 $r]]
+         set m [int [+ 1 [* [rand] 8]]]
+         set nf [int [+ 1 [* [rand] 8]]]
+
+         set r [int [* [rand] 8]]
+         set dcov [+ 20 [* 10 $r]]
+         set r [int [* [rand] 8]]
+         set pcov [+ 20 [* 10 $r]]
+         set r [int [* [rand] 8]]
+         set rlcov [+ 20 [* 10 $r]]
+
+         if {[rand] > 0.5} {set pov 1} else {set pov 0}
+         if {[rand] > 0.5} {set dov 1} else {set dov 0}
+         if {[rand] > 0.5} {set tc 1} else {set tc 0}
+         if {[rand] > 0.5} {set bc 1} else {set bc 0}
+         if {[rand] > 0.5} {set fm 1} else {set fm 0}
+         if {[rand] > 0.5} {set gl 1} else {set gl 0}
+         if {[rand] > 0.5} {set gr 1} else {set gr 0}
+         if {[rand] > 0.5} {set gt 1} else {set gt 0}
+         if {[rand] > 0.5} {set gb 1} else {set gb 0}
+
+         magic::gencell efgf013::${devname} ${devname}_$i w $w l $l m $m nf $nf diffcov $dcov polycov $pcov rlcov $rlcov poverlap $pov doverlap $dov topc $tc botc $bc full_metal $fm glc $gl grc $gr gbc $gb gtc $gt
+         select cell ${devname}_$i
+         set bh [box height]
+         set bh [+ $bh 124]
+         box move n $bh
+         incr i
+      }
+      set bp [box position]
+      set bpx [lindex $bp 0]
+      box position $bpx $starty
+      box move e 12700
+   }
+   resumeall
+}
+
+# NxN array resistor devices
+
+proc res_array {n devname startx starty} {
+   suspendall
+   box position $startx $starty
+   set i 0
+   for {set x 0} {$x < $n} {incr x} {
+      for {set y 0} {$y < $n} {incr y} {
+
+         set r [int [* [rand] 10]]
+         set w [+ 0.42 [* 0.5 $r]]
+         set r [int [* [rand] 50]]
+         set l [+ 2.10 [* 2.0 $r]]
+         set m [int [+ 1 [* [rand] 2]]]
+         set nx [int [+ 1 [* [rand] 10]]]
+
+         set r [int [* [rand] 8]]
+         set ecov [+ 20 [* 10 $r]]
+
+         if {[rand] > 0.5} {set rov 1} else {set rov 0}
+         if {[rand] > 0.5} {set sn 1} else {set sn 0}
+         if {[rand] > 0.5} {set fm 1} else {set fm 0}
+         if {[rand] > 0.5} {set gl 1} else {set gl 0}
+         if {[rand] > 0.5} {set gr 1} else {set gr 0}
+         if {[rand] > 0.5} {set gt 1} else {set gt 0}
+         if {[rand] > 0.5} {set gb 1} else {set gb 0}
+
+         magic::gencell efgf013::${devname} ${devname}_$i w $w l $l m $m nx $nx endcov $ecov roverlap $rov snake $sn full_metal $fm glc $gl grc $gr gbc $gb gtc $gt
+         select cell ${devname}_$i
+         set bh [box height]
+         set bh [+ $bh 124]
+         box move n $bh
+         incr i
+      }
+      set bp [box position]
+      set bpx [lindex $bp 0]
+      box position $bpx $starty
+      box move e 12700
+   }
+   resumeall
+}
+
+# NxN array diode devices
+
+proc diode_array {n devname startx starty} {
+   suspendall
+   box position $startx $starty
+   set i 0
+   for {set x 0} {$x < $n} {incr x} {
+      for {set y 0} {$y < $n} {incr y} {
+
+         set r [int [* [rand] 10]]
+         set w [+ 0.42 [* 0.5 $r]]
+         set r [int [* [rand] 10]]
+         set l [+ 0.42 [* 0.5 $r]]
+         set nx [int [+ 1 [* [rand] 4]]]
+         set ny [int [+ 1 [* [rand] 4]]]
+
+         if {[rand] > 0.5} {set dov 1} else {set dov 0}
+         if {[rand] > 0.5} {set el 1} else {set el 0}
+         if {[rand] > 0.5} {set er 1} else {set er 0}
+         if {[rand] > 0.5} {set et 1} else {set et 0}
+         if {[rand] > 0.5} {set eb 1} else {set eb 0}
+         if {[rand] > 0.5} {set fm 1} else {set fm 0}
+         if {[rand] > 0.5} {set gl 1} else {set gl 0}
+         if {[rand] > 0.5} {set gr 1} else {set gr 0}
+         if {[rand] > 0.5} {set gt 1} else {set gt 0}
+         if {[rand] > 0.5} {set gb 1} else {set gb 0}
+
+         magic::gencell efgf013::${devname} ${devname}_$i w $w l $l nx $nx ny $ny doverlap $dov full_metal $fm elc $el erc $er etc $et ebc $eb glc $gl grc $gr gbc $gb gtc $gt
+         select cell ${devname}_$i
+         set bh [box height]
+         set bh [+ $bh 124]
+         box move n $bh
+         incr i
+      }
+      set bp [box position]
+      set bpx [lindex $bp 0]
+      box position $bpx $starty
+      box move e 12700
+   }
+   resumeall
+}
+
+# NxN array cap devices
+
+proc cap_array {n devname startx starty} {
+   suspendall
+   box position $startx $starty
+   set i 0
+   for {set x 0} {$x < $n} {incr x} {
+      for {set y 0} {$y < $n} {incr y} {
+
+         set r [int [* [rand] 10]]
+         set w [+ 2.00 [* 1.0 $r]]
+         set r [int [* [rand] 10]]
+         set l [+ 2.00 [* 1.0 $r]]
+         set nx [int [+ 1 [* [rand] 4]]]
+         set ny [int [+ 1 [* [rand] 4]]]
+
+         if {[rand] > 0.5} {set bc 1} else {set bc 0}
+         if {[rand] > 0.5} {set tc 1} else {set tc 0}
+
+         magic::gencell efgf013::${devname} ${devname}_$i w $w l $l nx $nx ny $ny bconnect $bc tconnect $tc
+         select cell ${devname}_$i
+         set bh [box height]
+         set bh [+ $bh 160]
+         box move n $bh
+         incr i
+      }
+      set bp [box position]
+      set bpx [lindex $bp 0]
+      box position $bpx $starty
+      box move e 12700
+   }
+   resumeall
+}
+
+# NxN fixed devices
+
+proc fixed_array {n devname startx starty} {
+   suspendall
+   box position $startx $starty
+   set i 0
+   for {set x 0} {$x < $n} {incr x} {
+      for {set y 0} {$y < $n} {incr y} {
+
+         set nx [int [+ 1 [* [rand] 4]]]
+         set ny [int [+ 1 [* [rand] 4]]]
+
+	 # Do not change the deltas---this will cause DRC problems
+	 set r 0
+         # set r [int [* [rand] 10]]
+         set deltax [/ $r 10.0]
+         # set r [int [* [rand] 10]]
+         set deltay [/ $r 10.0]
+
+         magic::gencell efgf013::${devname} ${devname}_$i nx $nx ny $ny deltax $deltax deltay $deltay
+         select cell ${devname}_$i
+         set bh [box height]
+         set bh [* $bh [+ $ny 1]]
+         box move n $bh
+         incr i
+      }
+      set bp [box position]
+      set bpx [lindex $bp 0]
+      box position $bpx $starty
+      box move e 20000
+   }
+   resumeall
+}
+tech unlock *
+snap int
+box size 0 0
+ 
+# Layout:
+#                                                       apmom_bb
+#  pmos_3p3                                             mim_sm_bb
+#            pplus_u  ppolyf_s   ppolyf_u  pplus_u_3p3
+#  nmos_3p3                                pn_3p3
+#                                          np_3p3
+#  pmos_1p2                                
+#            nplus_u  nwell_1p2  npolyf_u  nplus_u_3p3  pn_1p2
+#  pmos_1p2                                             np_1p2 
+#
+
+
+mos_array 6 nmos_1p2 0 0
+mos_array 6 pmos_1p2 0 75000
+mos_array 6 nmos_3p3 0 150000 
+mos_array 6 pmos_3p3 0 225000
+mos_array 6 pmos_1p2_lvt 0 300000
+mos_array 6 pmos_1p2_hvt 0 375000
+mos_array 6 nmos_1p2_lvt 0 450000
+mos_array 6 nmos_1p2_hvt 0 525000
+mos_array 6 nmos_1p2_nat 0 600000
+mos_array 6 nmos_3p3_nat 0 675000
+
+res_array 6 nplus_u 100000 0 
+res_array 6 pplus_u 100000 180000
+
+res_array 6 nwell_1p2 200000 0
+res_array 6 ppolyf_s 200000 180000
+
+res_array 6 npolyf_u 300000 0
+res_array 6 ppolyf_u 300000 180000
+
+res_array 6 nplus_u_3p3 400000 0
+res_array 6 pplus_u_3p3 400000 180000
+ 
+diode_array 6 np_1p2 500000 0
+diode_array 6 pn_1p2 500000 30000 
+diode_array 6 np_3p3 500000 60000
+diode_array 6 pn_3p3 500000 90000 
+diode_array 6 np_1p2_lvt 500000 120000
+diode_array 6 np_1p2_hvt 500000 150000
+diode_array 6 np_1p2_nat 500000 180000
+diode_array 6 pn_1p2_lvt 500000 210000 
+diode_array 6 pn_1p2_hvt 500000 240000 
+diode_array 6 np_3p3_nat 500000 270000
+
+# Add individual devices from primdev, check GDS pointers
+fixed_array 2 vnpn_2x2 600000 0
+fixed_array 2 vnpn_5x0p42 600000 50000
+fixed_array 2 vnpn_5x5 600000 100000
+fixed_array 2 vnpn_10x0p42 600000 150000
+
+cap_array 6  mim_sm_bb 600000 200000 
+# cap_array 6 apmom_bb 600000 250000 
+
+save torture_test_gf013
+gds write torture_test_gf013
diff --git a/gf180mcu/magic/gf180mcugds.tech b/gf180mcu/magic/gf180mcugds.tech
new file mode 100644
index 0000000..df96381
--- /dev/null
+++ b/gf180mcu/magic/gf180mcugds.tech
@@ -0,0 +1,497 @@
+tech
+    format 33
+    GF013_GDS
+end
+
+version
+    version REVISION
+    description "Global Foundries GF013 (013BCDlite): Vendor GDS layers"
+end
+
+planes
+ l01
+ l02
+ l03
+ l04
+ l05
+ l06
+ l07
+ l08
+ l09
+ l10
+ l11
+ l12
+ l13
+ l14
+ l15
+ l16
+ l17
+ l18
+ l19
+ l20
+ l21
+ l22
+ l23
+ l24
+ l25
+ l26
+ l27
+ l28
+ l29
+ l30
+ l31
+ l32
+ l33
+ l34
+ l35
+ l36
+end
+
+types
+ l01 NWELL,l01
+ l02 COMP,l02
+ l03 DUALGATE,l03
+ l04 POLY2,l04
+ l05 NPLUS,l05
+ l06 ESD,l06
+ l07 SAB,l07
+ l08 PPLUS,l08
+ l09 CONTACT,l09
+ l10 METAL1,l10
+ l11 VIA1,l11
+ l12 METAL2,l12
+ l13 VIA2,l13
+ l14 METAL3,l14
+ l15 VIA3,l15
+ l16 METAL4,l16
+ l17 VIA4,l17
+ l18 METAL5,l18
+ l19 VIA5,l19
+ l20 METAL6,l20
+ l21 VIA6,l21
+ l22 METAL7,l22
+ l23 VIATV,l23
+ l24 METALMT,l24
+ l25 PAD,l25
+ l26 HVT,l26
+ l27 DNWELL,l27
+ l28 RES,l28
+ l29 FUSEBOT,l29
+ l30 FUSETOP,l30
+ l31 LVT,l31
+ l32 NAT,l32
+ l33 BJT,l33
+ l34 DIODE,l34
+ l35 RESDEF,l35
+ l36 CAPDEF,l36
+end
+
+contact
+end
+
+styles
+    styletype	mos
+ l01   nwell
+ l02   ndiffusion
+ l03   implant1
+ l04   polysilicon
+ l05   ndop_stripes
+ l06   implant2
+ l07   implant3
+ l08   pdop_stripes
+ l09   contact_X'es
+ l10   metal1
+ l11   via1arrow
+ l12   metal2
+ l13   via2arrow
+ l14   metal3
+ l15   via3
+ l16   metal4
+ l17   via4
+ l18   metal5
+ l19   via5
+ l20   metal6
+ l21   via6
+ l22   metal7
+ l23   via7
+ l24   metal8
+ l25   overglass
+ l26   nselect
+ l27   cwell
+ l28   poly_resist_stripes
+ l29   mim_top
+ l30   mim_bottom
+ l31   pselect
+ l32   substrate_field_implant
+ l33   implant4
+ l34   pdop_stripes
+ l35   pselect2
+ l36   implant3
+end
+
+compose
+end
+
+connect
+end
+
+cifoutput
+style gdsii
+ scalefactor 50 nanometers
+ options calma-permissive-labels
+
+ layer  NWELL NWELL
+ labels NWELL 
+ calma 21 0
+
+ layer  COMP COMP
+ labels COMP 
+ calma 22 0
+
+ layer  DUALGATE DUALGATE
+ labels DUALGATE 
+ calma 55 0
+
+ layer  POLY2 POLY2
+ labels POLY2 
+ calma 30 0
+
+ layer  NPLUS NPLUS
+ labels NPLUS 
+ calma 32 0
+
+ layer  ESD ESD
+ labels ESD 
+ calma 24 0
+
+ layer  SAB SAB
+ labels SAB 
+ calma 49 0
+
+ layer  PPLUS PPLUS
+ labels PPLUS 
+ calma 31 0
+
+ layer  CONTACT CONTACT
+ labels CONTACT 
+ calma 33 0
+
+ layer  METAL1 METAL1
+ labels METAL1 
+ calma 34 0
+
+ layer  VIA1 VIA1
+ labels VIA1 
+ calma 35 0
+
+ layer  METAL2 METAL2
+ labels METAL2 
+ calma 36 0
+
+ layer  VIA2 VIA2
+ labels VIA2 
+ calma 38 0
+
+ layer  METAL3 METAL3
+ labels METAL3 
+ calma 42 0
+
+ layer  VIA3 VIA3
+ labels VIA3 
+ calma 40 0
+
+ layer  METAL4 METAL4
+ labels METAL4 
+ calma 46 0
+
+ layer  VIA4 VIA4
+ labels VIA4 
+ calma 41 0
+
+ layer  METAL5 METAL5
+ labels METAL5 
+ calma 81 0
+
+ layer  VIA5 VIA5
+ labels VIA5 
+ calma 82 0
+
+ layer  METAL6 METAL6
+ labels METAL6 
+ calma 126 0
+
+ layer  VIA6 VIA6
+ labels VIA6 
+ calma 127 0
+
+ layer  METAL7 METAL7
+ labels METAL7 
+ calma 128 0
+
+ layer  VIATV VIATV
+ labels VIATV
+ calma 129 0
+
+ layer  METALMT METALMT
+ labels METALMT 
+ calma 53 0
+
+ layer  PAD PAD
+ labels PAD 
+ calma 37 0
+
+ layer HVT HVT
+ labels HVT
+ calma 187 0
+
+ layer DNWELL DNWELL
+ labels DNWELL
+ calma 12 0
+
+ layer RES RES
+ labels RES
+ calma 62 0
+
+ layer FUSEBOT FUSEBOT
+ labels FUSEBOT
+ calma 138 0
+
+ layer FUSETOP FUSETOP
+ labels FUSETOP
+ calma 75 0
+
+ layer CAPDEF CAPDEF
+ labels CAPDEF
+ calma 117 5
+
+ layer LVT LVT
+ labels LVT
+ calma 87 0
+
+ layer NAT NAT
+ labels NAT
+ calma 05 0
+
+ layer BJT BJT
+ labels BJT
+ calma 118 5
+
+ layer DIODE DIODE
+ labels DIODE
+ calma 115 5
+
+ layer RESDEF RESDEF
+ labels RESDEF
+ calma 110 5
+
+ layer PRBND
+ boundary
+ calma 0 0
+
+end
+
+cifinput
+style ProgName
+ scalefactor 50 nanometers
+
+ layer  NWELL NWELL
+ labels NWELL 
+ calma NWELL 21 0
+
+ layer  COMP COMP
+ labels COMP 
+ calma COMP 22 0
+
+ layer  DUALGATE DUALGATE
+ labels DUALGATE 
+ calma DUALGATE 55 0
+
+ layer  POLY2 POLY2
+ labels POLY2 
+ calma POLY2 30 0
+
+ layer  NPLUS NPLUS
+ labels NPLUS 
+ calma NPLUS 32 0
+
+ layer  ESD ESD
+ labels ESD 
+ calma ESD 24 0
+
+ layer  SAB SAB
+ labels SAB 
+ calma SAB 49 0
+
+ layer  PPLUS PPLUS
+ labels PPLUS 
+ calma PPLUS 31 0
+
+ layer  CONTACT CONTACT
+ labels CONTACT 
+ calma CONTACT 33 0
+
+ layer  METAL1 METAL1
+ labels METAL1 
+ calma METAL1 34 0
+
+ layer  VIA1 VIA1
+ labels VIA1 
+ calma VIA1 35 0
+
+ layer  METAL2 METAL2
+ labels METAL2 
+ calma METAL2 36 0
+
+ layer  VIA2 VIA2
+ labels VIA2 
+ calma VIA2 38 0
+
+ layer  METAL3 METAL3
+ labels METAL3 
+ calma METAL3 42 0
+
+ layer  VIA3 VIA3
+ labels VIA3 
+ calma VIA3 40 0
+
+ layer  METAL4 METAL4
+ labels METAL4 
+ calma METAL4 46 0
+
+ layer  VIA4 VIA4
+ labels VIA4 
+ calma VIA4 41 0
+
+ layer  METAL5 METAL5
+ labels METAL5 
+ calma METAL5 81 0
+
+ layer  VIA5 VIA5
+ labels VIA5 
+ calma VIA5 82 0
+
+ layer  METAL6 METAL6
+ labels METAL6 
+ calma METAL6 126 0
+
+ layer  VIA6 VIA6
+ labels VIA6 
+ calma VIA6 127 0
+
+ layer  METAL7 METAL7
+ labels METAL7 
+ calma METAL7 128 0
+
+ layer  VIATV VIATV
+ labels VIATV
+ calma VIATV 129 0
+
+ layer  METALMT METALMT
+ labels METALMT 
+ calma METALMT 53 0
+
+ layer  PAD PAD
+ labels PAD 
+ calma PAD 37 0
+
+ layer HVT HVT
+ labels HVT
+ calma HVT 187 0
+
+ layer DNWELL DNWELL
+ labels DNWELL
+ calma DNWELL 12 0
+
+ layer RES RES
+ labels RES
+ calma RES 62 0
+
+ layer FUSEBOT FUSEBOT
+ labels FUSEBOT
+ calma FUSEBOT 138 0
+
+ layer FUSETOP FUSETOP
+ labels FUSETOP
+ calma FUSETOP 75 0
+
+ layer CAPDEF CAPDEF
+ labels CAPDEF
+ calma CAPDEF 117 5
+
+ layer LVT LVT
+ labels LVT
+ calma LVT 87 0
+
+ layer NAT NAT
+ labels NAT
+ calma NAT 05 0
+
+ layer BJT BJT
+ labels BJT
+ calma BJT 118 5
+
+ layer DIODE DIODE
+ labels DIODE
+ calma DIODE 115 5
+
+ layer RESDEF RESDEF
+ labels RESDEF
+ calma RESDEF 110 5
+
+ templayer PRBND
+ boundary
+ calma PRBND 0 0
+
+end
+ 
+mzrouter
+end
+
+drc
+end
+ 
+mzrouter
+end
+
+drc
+end
+
+extract
+style default
+ planeorder l01  0
+ planeorder l02  1
+ planeorder l03  2
+ planeorder l04  3
+ planeorder l05  4
+ planeorder l06  5
+ planeorder l07  6
+ planeorder l08  7
+ planeorder l09  8
+ planeorder l10  9
+ planeorder l11 10
+ planeorder l12 11
+ planeorder l13 12
+ planeorder l14 13
+ planeorder l15 14
+ planeorder l16 15
+ planeorder l17 16
+ planeorder l18 17
+ planeorder l19 18
+ planeorder l20 19
+ planeorder l21 20
+ planeorder l22 21
+ planeorder l23 22
+ planeorder l24 23
+ planeorder l25 24
+ planeorder l26 25
+ planeorder l27 26
+ planeorder l28 27
+ planeorder l29 28
+ planeorder l30 29
+ planeorder l31 30
+ planeorder l32 31
+ planeorder l33 32
+ planeorder l34 33
+ planeorder l35 34
+ planeorder l36 35
+end
diff --git a/gf180mcu/netgen/gf180mcu_setup.tcl b/gf180mcu/netgen/gf180mcu_setup.tcl
new file mode 100644
index 0000000..e59db6e
--- /dev/null
+++ b/gf180mcu/netgen/gf180mcu_setup.tcl
@@ -0,0 +1,257 @@
+###
+###     Source file gf013_setup.tcl
+###     Process this file with the preproc.py processor
+###
+#---------------------------------------------------------------
+# Setup file for netgen LVS
+# Global Foundries TECHNAME
+#---------------------------------------------------------------
+permute default
+property default
+property parallel none
+
+#---------------------------------------------------------------
+# For the following, get the cell lists from
+# circuit1 and circuit2.
+#---------------------------------------------------------------
+
+set cells1 [cells list -all -circuit1]
+set cells2 [cells list -all -circuit2]
+
+# NOTE:  In accordance with the LVS manager GUI, the schematic is
+# always circuit2, so some items like property "par1" only need to
+# be specified for circuit2.
+
+#-------------------------------------------
+# Resistors (except metal)
+#-------------------------------------------
+
+set devices {nwell_1p5 ppolyf_u npolyf_u ppolyf_s nplus_u pplus_u nw1a_6p0}
+lappend devices npolyf_s pfield_1p5 pf1va_6p0
+#ifdef HRPOLY1K
+lappend devices ppolyf_u_1k ppolyf_u_1k_6p0
+#endif
+#ifdef HRPOLY2K
+lappend devices ppolyf_u_2k ppolyf_u_2k_6p0
+#endif
+
+foreach dev $devices {
+    if {[lsearch $cells1 $dev] >= 0} {
+	property "-circuit1 $dev" parallel enable
+	property "-circuit1 $dev" serial enable
+	permute "-circuit1 $dev" 1 2
+	property "-circuit1 $dev" merge {l ser_critical} {w add_critical}
+	property "-circuit1 $dev" tolerance {l 0.01} {w 0.01}
+	# Ignore these properties
+	property "-circuit2 $dev" delete par1 pm
+    }
+    if {[lsearch $cells2 $dev] >= 0} {
+	property "-circuit2 $dev" parallel enable
+	property "-circuit2 $dev" serial enable
+	permute "-circuit2 $dev" 1 2
+	property "-circuit2 $dev" merge {l ser_critical} {w add_critical}
+	property "-circuit2 $dev" tolerance {l 0.01} {w 0.01}
+	# Ignore these properties
+	property "-circuit2 $dev" delete par1 pm
+    }
+}
+
+#-------------------------------------------
+# RM (metal) resistors
+#-------------------------------------------
+
+set devices {rm1 rm2}
+#ifdef METALS4 || METALS5 || METALS6 || METALS7
+lappend devices rm3
+#endif (METALS4 || METALS5 || METALS6 || METALS7)
+#ifdef METALS5 || METALS6 || METALS7
+lappend devices rm4
+#endif (METALS5 || METALS6 || METALS7)
+#ifdef METALS6 || METALS7
+lappend devices rm5
+#endif (METALS6 || METALS7)
+#ifdef METALS7
+lappend devices rm6
+#endif (METALS7)
+#ifndef THICKMET
+lappend devices rmtp
+#endif (THICKMET)
+#ifdef THICKMET || THICK2MET
+lappend devices rmtk
+#endif (THICKMET || THICK2MET)
+
+foreach dev $devices {
+    if {[lsearch $cells1 $dev] >= 0} {
+	property "-circuit1 $dev" parallel enable
+	permute "-circuit1 $dev" 1 2
+	property "-circuit1 $dev" tolerance {l 0.01} {w 0.01}
+	# Ignore these properties
+	property "-circuit2 $dev" delete par1 pm
+    }
+    if {[lsearch $cells2 $dev] >= 0} {
+	property "-circuit2 $dev" parallel enable
+	permute "-circuit2 $dev" 1 2
+	property "-circuit2 $dev" tolerance {l 0.01} {w 0.01}
+	# Ignore these properties
+	property "-circuit2 $dev" delete par1 pm
+    }
+}
+
+#-------------------------------------------
+# (MOS) transistors
+#-------------------------------------------
+
+set devices {nmos_1p5 pmos_1p5 nmos_6p0 pmos_6p0 nmoscap_1p5 nmoscap_6p0}
+
+foreach dev $devices {
+    if {[lsearch $cells1 $dev] >= 0} {
+	property "-circuit1 $dev" parallel enable
+	permute "-circuit1 $dev" 1 3
+	property "-circuit1 $dev" merge {w add_critical}
+	property "-circuit1 $dev" tolerance {w 0.01} {l 0.01}
+	# Ignore these properties
+	property "-circuit2 $dev" delete par1 NRD NRS
+    }
+    if {[lsearch $cells2 $dev] >= 0} {
+	property "-circuit2 $dev" parallel enable
+	permute "-circuit2 $dev" 1 3
+	property "-circuit2 $dev" merge {w add_critical}
+	property "-circuit2 $dev" tolerance {w 0.01} {l 0.01}
+	# Ignore these properties
+	property "-circuit2 $dev" delete par1 NRD NRS
+    }
+}
+
+#-------------------------------------------
+# diodes
+#-------------------------------------------
+
+set devices {np_1p5 pn_1p5 np_6p0 pn_6p0 nwp_1p5 nwp_6p0}
+
+foreach dev $devices {
+    if {[lsearch $cells1 $dev] >= 0} {
+	property "-circuit1 $dev" parallel enable
+	property "-circuit1 $dev" merge {area add_critical}
+	property "-circuit1 $dev" tolerance {area 0.02}
+	# Ignore these properties
+	property "-circuit2 $dev" delete par1 peri
+    }
+    if {[lsearch $cells2 $dev] >= 0} {
+	property "-circuit2 $dev" parallel enable
+	property "-circuit2 $dev" merge {area add_critical}
+	property "-circuit2 $dev" tolerance {area 0.02}
+	# Ignore these properties
+	property "-circuit2 $dev" delete par1 peri
+    }
+}
+
+#-----------------------------------------------
+# Fixed-layout devices
+# NPN bipolar transistors,
+# sandwich (MoM) capacitors, and MiM capacitors
+#-----------------------------------------------
+
+set devices {vnpn_lv_2p5x2p5 vnpn_lv_5x5 vnpn_lv_10x10}
+lappend devices vnpn_mv_2p5x2p5 vnpn_mv_5x5 vnpn_mv_10x10
+lappend devices apmom_bb
+#ifdef MIM
+lappend devices mim_sm_bb
+#endif
+#ifdef DMIM
+lappend devices mim_dm_bb
+#endif
+
+foreach dev $devices {
+    if {[lsearch $cells1 $dev] >= 0} {
+	property "-circuit1 $dev" parallel enable
+	# Ignore these properties
+	property "-circuit2 $dev" delete par1
+    }
+    if {[lsearch $cells2 $dev] >= 0} {
+	property "-circuit2 $dev" parallel enable
+	# Ignore these properties
+	property "-circuit2 $dev" delete par1
+    }
+}
+
+#---------------------------------------------------------------
+# D_CELLS_SC9 (ignore FILL cells)
+#---------------------------------------------------------------
+# e.g., ignore class "-circuit2 FILL5"
+#---------------------------------------------------------------
+
+foreach cell $cells1 {
+    if {[regexp "FILL\[0-9\]+" $cell match]} {
+        ignore class "-circuit1 $cell"
+    }
+}
+foreach cell $cells2 {
+    if {[regexp "FILL\[0-9\]+" $cell match]} {
+        ignore class "-circuit2 $cell"
+    }
+}
+
+#---------------------------------------------------------------
+# ICPIO_5P0 (ignore FILL cells)
+#---------------------------------------------------------------
+# e.g., ignore class "-circuit1 GF_CI_FILL5"
+#---------------------------------------------------------------
+foreach cell $cells1 {
+    if {[regexp "GF_CI_FILL.*" $cell match]} {
+        ignore class "-circuit1 $cell"
+    }
+}
+foreach cell $cells2 {
+    if {[regexp "GF_CI_FILL.*" $cell match]} {
+        ignore class "-circuit2 $cell"
+    }
+}
+
+#---------------------------------------------------------------
+# Handle cells captured from Electric
+#
+# Find cells of the form "<library>__<cellname>" in the netlist
+# from Electric where the extracted layout netlist has only
+# "<cellname>".  Cross-check by ensuring that the full name
+# "<library>__<cellname>" does not exist in both cells, and that
+# the truncated name "<cellname>" does not exist in both cells.
+#---------------------------------------------------------------
+# e.g., hydra_spi_controller__hydra_spi_controller
+#---------------------------------------------------------------
+foreach cell $cells1 {
+    if {[regexp "(.+)__(.+)" $cell match library cellname]} {
+        if {([lsearch $cells2 $cell] < 0) && \
+                ([lsearch $cells2 $cellname] >= 0) && \
+                ([lsearch $cells1 $cellname] < 0)} {
+            equate classes "-circuit1 $cell" "-circuit2 $cellname"
+	    puts stdout "Matching pins of $cell in circuit 1 and $cellname in circuit 2"
+	    equate pins "-circuit1 $cell" "-circuit2 $cellname"
+        }
+    }
+}
+
+foreach cell $cells2 {
+    if {[regexp "(.+)__(.+)" $cell match library cellname]} {
+        if {([lsearch $cells1 $cell] < 0) && \
+                ([lsearch $cells1 $cellname] >= 0) && \
+                ([lsearch $cells2 $cellname] < 0)} {
+            equate classes "-circuit1 $cellname" "-circuit2 $cell"
+	    puts stdout "Matching pins of $cellname in circuit 1 and $cell in circuit 2"
+	    equate pins "-circuit1 $cellname" "-circuit2 $cell"
+        }
+    }
+}
+
+# Match pins on black-box cells if LVS is called with "-blackbox"
+if {[model blackbox]} {
+    foreach cell $cells1 {
+	if {[model "-circuit1 $cell"] == "blackbox"} {
+	    if {[lsearch $cells2 $cell] >= 0} {
+		puts stdout "Matching pins of $cell in circuits 1 and 2"
+		equate pins "-circuit1 $cell" "-circuit2 $cell"
+	    }
+	}
+    }
+}
+
+#---------------------------------------------------------------
diff --git a/gf180mcu/openlane/config.tcl b/gf180mcu/openlane/config.tcl
new file mode 100644
index 0000000..65ccbb0
--- /dev/null
+++ b/gf180mcu/openlane/config.tcl
@@ -0,0 +1,127 @@
+# Process node
+set ::env(PROCESS) 180
+set ::env(DEF_UNITS_PER_MICRON) 2000
+
+set ::env(VDD_PIN) "VDD"
+set ::env(GND_PIN) "VSS"
+set ::env(STD_CELL_POWER_PINS) "VDD"
+set ::env(STD_CELL_GROUND_PINS) "VSS"
+
+# Technology LEF
+set ::env(TECH_LEF)  [glob "$::env(PDK_ROOT)/$::env(PDK)/libs.ref/$::env(STD_CELL_LIBRARY)/techlef/*_tech.lef"]
+set ::env(CELLS_LEF) [glob "$::env(PDK_ROOT)/$::env(PDK)/libs.ref/$::env(STD_CELL_LIBRARY)/lef/*_mw.lef"]
+set ::env(GDS_FILES) [glob "$::env(PDK_ROOT)/$::env(PDK)/libs.ref/$::env(STD_CELL_LIBRARY)/gds/*.gds"]
+set ::env(STD_CELL_LIBRARY_CDL)	"$::env(PDK_ROOT)/$::env(PDK)/libs.ref/$::env(STD_CELL_LIBRARY)/cdl/$::env(STD_CELL_LIBRARY).cdl"
+set ::env(GPIO_PADS_LEF) "\
+    $::env(PDK_ROOT)/$::env(PDK)/libs.ref/gf180mcu_io/lef/GF018green_ipio_5p0c_75_5lm.lef
+"
+set ::env(GPIO_PADS_VERILOG) "\
+    $::env(PDK_ROOT)/$::env(PDK)/libs.ref/gf180mcu_io/verilog/GF018green_ipio_5p0c_75_5lm.v
+"
+
+
+# Latch mapping
+set ::env(SYNTH_LATCH_MAP) "$::env(PDK_ROOT)/$::env(PDK)/libs.tech/openlane/$::env(STD_CELL_LIBRARY)/latch_map.v"
+
+# Tri-state buffer mapping
+set ::env(TRISTATE_BUFFER_MAP) "$::env(PDK_ROOT)/$::env(PDK)/libs.tech/openlane/$::env(STD_CELL_LIBRARY)/tribuff_map.v"
+
+# Full adder mapping
+set ::env(FULL_ADDER_MAP) "$::env(PDK_ROOT)/$::env(PDK)/libs.tech/openlane/$::env(STD_CELL_LIBRARY)/fa_map.v"
+
+# Ripple carry adder mapping
+set ::env(RIPPLE_CARRY_ADDER_MAP) "$::env(PDK_ROOT)/$::env(PDK)/libs.tech/openlane/$::env(STD_CELL_LIBRARY)/rca_map.v"
+
+# Carry select adder mapping
+set ::env(CARRY_SELECT_ADDER_MAP) "$::env(PDK_ROOT)/$::env(PDK)/libs.tech/openlane/$::env(STD_CELL_LIBRARY)/csa_map.v"
+
+# Default No Synth List
+set ::env(NO_SYNTH_CELL_LIST) "$::env(PDK_ROOT)/$::env(PDK)/libs.tech/openlane/$::env(STD_CELL_LIBRARY)/no_synth.cells"
+
+# Default DRC Exclude List
+set ::env(DRC_EXCLUDE_CELL_LIST) "$::env(PDK_ROOT)/$::env(PDK)/libs.tech/openlane/$::env(STD_CELL_LIBRARY)/drc_exclude.cells"
+
+# DRC Exclude List for Optimization library
+set ::env(DRC_EXCLUDE_CELL_LIST_OPT) "$::env(PDK_ROOT)/$::env(PDK)/libs.tech/openlane/$::env(STD_CELL_LIBRARY_OPT)/drc_exclude.cells"
+
+# Open-RCX Rules File
+set ::env(RCX_RULES) "$::env(PDK_ROOT)/$::env(PDK)/libs.tech/openlane/rcx_rules.info"
+
+# Floorplanning
+## Layer Info
+set ::env(FP_IO_HLAYER) "Metal3"
+set ::env(FP_IO_VLAYER) "Metal2"
+set ::env(FP_PDN_RAILS_LAYER) "Metal1"
+set ::env(FP_PDN_LOWER_LAYER) "Metal4"
+set ::env(FP_PDN_UPPER_LAYER) "Metal5"
+set ::env(MACRO_BLOCKAGES_LAYER) "Metal1 Metal2 Metal3 Metal4 Metal5"
+set ::env(WIRE_RC_LAYER) "Metal2"
+set ::env(DATA_WIRE_RC_LAYER) "Metal2"
+set ::env(CLOCK_WIRE_RC_LAYER) "Metal4"
+
+## Tap Cell Dist
+set ::env(FP_TAPCELL_DIST) 20
+
+## Extra PDN configs
+
+### OpenROAD Bug
+set ::env(FP_PDN_IRDROP) 0
+
+set ::env(FP_PDN_RAIL_OFFSET) 0
+set ::env(FP_PDN_VWIDTH) 1.6
+set ::env(FP_PDN_HWIDTH) 1.6
+set ::env(FP_PDN_VSPACING) 1.7
+set ::env(FP_PDN_HSPACING) 1.7
+
+## Core Ring PDN defaults
+set ::env(FP_PDN_CORE_RING_VWIDTH) 1.6
+set ::env(FP_PDN_CORE_RING_HWIDTH) 1.6
+set ::env(FP_PDN_CORE_RING_VSPACING) 1.7
+set ::env(FP_PDN_CORE_RING_HSPACING) 1.7
+set ::env(FP_PDN_CORE_RING_VOFFSET) 6
+set ::env(FP_PDN_CORE_RING_HOFFSET) 6
+
+# Timing
+set ::env(RCX_RULES) "$::env(PDK_ROOT)/$::env(PDK)/libs.tech/openlane/rules.openrcx.$::env(PDK).nom.magic"
+set ::env(RCX_RULES_MIN) "$::env(PDK_ROOT)/$::env(PDK)/libs.tech/openlane/rules.openrcx.$::env(PDK).min.magic"
+set ::env(RCX_RULES_MAX) "$::env(PDK_ROOT)/$::env(PDK)/libs.tech/openlane/rules.openrcx.$::env(PDK).max.magic"
+
+# Routing
+set ::env(METAL_LAYER_NAMES) "Metal1 Metal2 Metal3 Metal4 Metal5"
+set ::env(RT_MIN_LAYER) "Metal1"
+set ::env(RT_MAX_LAYER) "Metal5"
+set ::env(GLB_RT_LAYER_ADJUSTMENTS) "0,0,0,0,0"
+
+## Tracks info
+set ::env(TRACKS_INFO_FILE) "$::env(PDK_ROOT)/$::env(PDK)/libs.tech/openlane/$::env(STD_CELL_LIBRARY)/tracks.info"
+
+# Signoff
+## Magic
+set ::env(MAGIC_MAGICRC) "$::env(PDK_ROOT)/$::env(PDK)/libs.tech/magic/$::env(PDK).magicrc"
+set ::env(MAGIC_TECH_FILE) "$::env(PDK_ROOT)/$::env(PDK)/libs.tech/magic/$::env(PDK).tech"
+
+## Klayout
+set ::env(RUN_KLAYOUT) {0}
+set ::env(RUN_KLAYOUT_XOR) {0}
+set ::env(KLAYOUT_TECH) "$::env(PDK_ROOT)/$::env(PDK)/libs.tech/klayout/$::env(PDK).lyt"
+set ::env(KLAYOUT_PROPERTIES) "$::env(PDK_ROOT)/$::env(PDK)/libs.tech/klayout/$::env(PDK).lyp"
+set ::env(KLAYOUT_DRC_TECH_SCRIPT) "$::env(PDK_ROOT)/$::env(PDK)/libs.tech/klayout/$::env(PDK)_mr.drc"
+#set ::env(KLAYOUT_DRC_TECH) "$::env(PDK_ROOT)/$::env(PDK)/libs.tech/klayout/$::env(PDK).lydrc"
+
+## Netgen
+set ::env(NETGEN_SETUP_FILE) "$::env(PDK_ROOT)/$::env(PDK)/libs.tech/netgen/$::env(PDK)_setup.tcl"
+
+# # Temporary Override(s) Because OpenROAD can't read techlefs properly
+# # Layer RC Values
+# set ::env(LAYERS_RC) "\
+#     Metal1 0.090000 0.0000394,\
+#     Metal2 0.090000 0.0000394,\
+#     Metal3 0.090000 0.0000394,\
+#     Metal4 0.090000 0.0000394,\
+#     Metal5 0.090000 0.0000394"
+
+# set ::env(VIAS_RC) "\
+#     Via1 4.500,\
+#     Via2 4.500,\
+#     Via3 4.500,\
+#     Via4 4.500"
\ No newline at end of file
diff --git a/gf180mcu/openlane/gf180mcu_fd_sc_mcu7t5v0/config.tcl b/gf180mcu/openlane/gf180mcu_fd_sc_mcu7t5v0/config.tcl
new file mode 100644
index 0000000..b02fa05
--- /dev/null
+++ b/gf180mcu/openlane/gf180mcu_fd_sc_mcu7t5v0/config.tcl
@@ -0,0 +1,79 @@
+set current_folder [file dirname [file normalize [info script]]]
+# Technology lib
+set TRACK_POSTFIX "7T5P0"
+set ::env(LIB_SYNTH) "$::env(PDK_ROOT)/$::env(PDK)/libs.ref/$::env(STD_CELL_LIBRARY)/liberty/GF018hv5v_mcu_sc7_TT_1P8V_25C.lib"
+set ::env(LIB_FASTEST) "$::env(PDK_ROOT)/$::env(PDK)/libs.ref/$::env(STD_CELL_LIBRARY)/liberty/GF018hv5v_mcu_sc7_FF_1P98V_M40C.lib"
+set ::env(LIB_SLOWEST) "$::env(PDK_ROOT)/$::env(PDK)/libs.ref/$::env(STD_CELL_LIBRARY)/liberty/GF018hv5v_mcu_sc7_SS_1P62V_125C.lib"
+
+set ::env(LIB_TYPICAL) $::env(LIB_SYNTH)
+
+# to be removed as ABC scripts were updated to handle the mapping
+
+# MUX4 mapping
+# set ::env(SYNTH_MUX4_MAP) "$::env(PDK_ROOT)/$::env(PDK)/libs.tech/openlane/$::env(STD_CELL_LIBRARY)/mux4_map.v"
+
+# MUX2 mapping
+# set ::env(SYNTH_MUX_MAP) "$::env(PDK_ROOT)/$::env(PDK)/libs.tech/openlane/$::env(STD_CELL_LIBRARY)/mux2_map.v"
+
+# Placement site for core cells
+# This can be found in the technology lef
+set ::env(PLACE_SITE) "GF018hv5v_mcu_sc7"
+set ::env(PLACE_SITE_WIDTH) 0.56
+set ::env(PLACE_SITE_HEIGHT) 3.92
+
+# welltap and endcap cell
+set ::env(FP_WELLTAP_CELL) "FILLTIE_$TRACK_POSTFIX"
+set ::env(FP_ENDCAP_CELL) "ENDCAP_$TRACK_POSTFIX"
+
+# defaults (can be overridden by designs):
+set ::env(SYNTH_DRIVING_CELL) "INV_X1_$TRACK_POSTFIX"
+set ::env(SYNTH_DRIVING_CELL_PIN) "ZN"
+set ::env(SYNTH_CLK_DRIVING_CELL) "INV_X4_$TRACK_POSTFIX"
+set ::env(SYNTH_CLK_DRIVING_CELL_PIN) "ZN"
+
+# update these
+set ::env(SYNTH_CAP_LOAD) "72.91" ; # femtofarad from pin I in liberty file
+set ::env(SYNTH_MIN_BUF_PORT) "BUF_X1_$TRACK_POSTFIX I Z"
+set ::env(SYNTH_TIEHI_PORT) "TIEH_$TRACK_POSTFIX Z"
+set ::env(SYNTH_TIELO_PORT) "TIEL_$TRACK_POSTFIX ZN"
+
+# Placement defaults
+set ::env(PL_LIB) $::env(LIB_TYPICAL)
+
+# Fillcell insertion
+set ::env(FILL_CELL) "FILL_*"
+set ::env(DECAP_CELL) "FILLCAP_*" ; # There is also ENDCAP, which one should be used?
+
+# To be removed
+# set ::env(RE_BUFFER_CELL) "BUF_X4_$TRACK_POSTFIX" ; # which buf should be used?
+
+# Diode Insertion
+# A fake diode has to be created, for now don't use any strategy that uses fake diode
+# set ::env(FAKEDIODE_CELL) ""
+set ::env(DIODE_CELL) "ANTENNA_$TRACK_POSTFIX"
+set ::env(DIODE_CELL_PIN) "I"
+set ::env(DIODE_INSERTION_STRATEGY) {4}
+
+# What should be put here?
+# Are we still using it? to be reviewed
+set ::env(CELL_PAD) 2
+set ::env(CELL_PAD_EXCLUDE) "FILLTIE_* FILLDECAP_* FILL_* ENDCAP_*"
+
+# Clk Buffers info CTS data
+# This is for simple_cts which is deprecated
+# set ::env(CELL_CLK_PORT) CLK
+# set ::env(ROOT_CLK_BUFFER) "CLKBUF_X20_$TRACK_POSTFIX"
+# set ::env(CLK_BUFFER) "CLKBUF_X4_$TRACK_POSTFIX" ; # which size should be used?
+# set ::env(CLK_BUFFER_INPUT) I
+# set ::env(CLK_BUFFER_OUTPUT) Z
+
+# TritonCTS configurations
+set ::env(CTS_ROOT_BUFFER) "CLKBUF_X16_$TRACK_POSTFIX"
+set ::env(CTS_CLK_BUFFER_LIST) "CLKBUF_X2_$TRACK_POSTFIX CLKBUF_X4_$TRACK_POSTFIX CLKBUF_X8_$TRACK_POSTFIX"
+set ::env(CTS_MAX_CAP) 0.5
+
+set ::env(FP_PDN_RAIL_WIDTH) 0.6
+
+# The library maximum transition is 8.9ns; setting it to lower value
+set ::env(DEFAULT_MAX_TRAN) 3
+
diff --git a/gf180mcu/openlane/gf180mcu_fd_sc_mcu7t5v0/drc_exclude.cells b/gf180mcu/openlane/gf180mcu_fd_sc_mcu7t5v0/drc_exclude.cells
new file mode 100644
index 0000000..cd9c76f
--- /dev/null
+++ b/gf180mcu/openlane/gf180mcu_fd_sc_mcu7t5v0/drc_exclude.cells
@@ -0,0 +1,2 @@
+MUX2_X1_7T5P0
+OAI33_X2_7T5P0
\ No newline at end of file
diff --git a/gf180mcu/openlane/gf180mcu_fd_sc_mcu7t5v0/no_synth.cells b/gf180mcu/openlane/gf180mcu_fd_sc_mcu7t5v0/no_synth.cells
new file mode 100644
index 0000000..a919971
--- /dev/null
+++ b/gf180mcu/openlane/gf180mcu_fd_sc_mcu7t5v0/no_synth.cells
@@ -0,0 +1,12 @@
+SDFFSNQ_X4_7T5P0
+SDFFQ_X1_7T5P0
+SDFFQ_X2_7T5P0
+SDFFQ_X4_7T5P0
+SDFFRNQ_X1_7T5P0
+SDFFRNQ_X2_7T5P0
+SDFFRNQ_X4_7T5P0
+SDFFRSNQ_X1_7T5P0
+SDFFRSNQ_X2_7T5P0
+SDFFRSNQ_X4_7T5P0
+SDFFSNQ_X1_7T5P0
+SDFFSNQ_X2_7T5P0
\ No newline at end of file
diff --git a/gf180mcu/openlane/gf180mcu_fd_sc_mcu7t5v0/tracks.info b/gf180mcu/openlane/gf180mcu_fd_sc_mcu7t5v0/tracks.info
new file mode 100644
index 0000000..613fedd
--- /dev/null
+++ b/gf180mcu/openlane/gf180mcu_fd_sc_mcu7t5v0/tracks.info
@@ -0,0 +1,11 @@
+Metal1 X 0.28 0.56
+Metal1 Y 0.28 0.56
+Metal2 X 0.28 0.56
+Metal2 Y 0.28 0.56
+Metal3 X 0.28 0.56
+Metal3 Y 0.28 0.56
+Metal4 X 0.28 0.56
+Metal4 Y 0.28 0.56
+Metal5 X 0.28 0.56
+Metal5 Y 0.28 0.56
+
diff --git a/gf180mcu/openlane/gf180mcu_fd_sc_mcu9t5v0/config.tcl b/gf180mcu/openlane/gf180mcu_fd_sc_mcu9t5v0/config.tcl
new file mode 100644
index 0000000..175335f
--- /dev/null
+++ b/gf180mcu/openlane/gf180mcu_fd_sc_mcu9t5v0/config.tcl
@@ -0,0 +1,75 @@
+set current_folder [file dirname [file normalize [info script]]]
+# Technology lib
+set ::env(LIB_SYNTH) "$::env(PDK_ROOT)/$::env(PDK)/libs.ref/$::env(STD_CELL_LIBRARY)/liberty/GF018hv5v_green_sc9_TT_1P80V_25C.lib"
+set ::env(LIB_FASTEST) "$::env(PDK_ROOT)/$::env(PDK)/libs.ref/$::env(STD_CELL_LIBRARY)/liberty/GF018hv5v_green_sc9_FF_1P98V_M40C.db"
+set ::env(LIB_SLOWEST) "$::env(PDK_ROOT)/$::env(PDK)/libs.ref/$::env(STD_CELL_LIBRARY)/liberty/GF018hv5v_green_sc9_SS_1P62V_125C.db"
+
+set ::env(LIB_TYPICAL) $::env(LIB_SYNTH)
+
+# to be removed as ABC scripts were updated to handle the mapping
+
+# MUX4 mapping
+# set ::env(SYNTH_MUX4_MAP) "$::env(PDK_ROOT)/$::env(PDK)/libs.tech/openlane/$::env(STD_CELL_LIBRARY)/mux4_map.v"
+
+# MUX2 mapping
+# set ::env(SYNTH_MUX_MAP) "$::env(PDK_ROOT)/$::env(PDK)/libs.tech/openlane/$::env(STD_CELL_LIBRARY)/mux2_map.v"
+
+# Placement site for core cells
+# This can be found in the technology lef
+set ::env(PLACE_SITE) "GF018hv5v_green_sc9"
+set ::env(PLACE_SITE_WIDTH) 0.56
+set ::env(PLACE_SITE_HEIGHT) 5.04
+
+# welltap and endcap cell
+set ::env(FP_WELLTAP_CELL) "FILLTIE"
+set ::env(FP_ENDCAP_CELL) "ENDCAP"
+
+# defaults (can be overridden by designs):
+set ::env(SYNTH_DRIVING_CELL) "INV_X1"
+#capacitance : 0.017653;
+set ::env(SYNTH_DRIVING_CELL_PIN) "ZN"
+
+# update these
+set ::env(SYNTH_CAP_LOAD) "72.91" ; # femtofarad from pin I in liberty file
+set ::env(SYNTH_MIN_BUF_PORT) "BUF_X1 I Z"
+set ::env(SYNTH_TIEHI_PORT) "TIEH Z"
+set ::env(SYNTH_TIELO_PORT) "TIEL ZN"
+
+# Placement defaults
+set ::env(PL_LIB) $::env(LIB_TYPICAL)
+
+# Fillcell insertion
+set ::env(FILL_CELL) "FILL_*"
+set ::env(DECAP_CELL) "FILLCAP_*" ; # There is also ENDCAP, which one should be used?
+
+# To be removed
+# set ::env(RE_BUFFER_CELL) "BUF_X4" ; # which buf should be used?
+
+# Diode insertaion
+# A fake diode has to be created, for now don't use any strategy that uses fake diode
+set ::env(DIODE_CELL) "ANTENNA"
+# set ::env(FAKEDIODE_CELL) "sky130_ef_sc_hd__fakediode_2" ; # What is this?
+set ::env(DIODE_CELL_PIN) "I"
+
+# Are we still using it? to be reviewed
+set ::env(CELL_PAD) 2
+set ::env(CELL_PAD_EXCLUDE) "FILLTIE_* FILLDECAP_* FILL_* ENDCAP_*"
+
+# Clk Buffers info CTS data
+# This is for simple_cts which is deprecated
+# set ::env(CELL_CLK_PORT) CLK
+# set ::env(ROOT_CLK_BUFFER) "CLKBUF_X20"
+# set ::env(CLK_BUFFER) "CLKBUF_X4" ; # which size should be used?
+# set ::env(CLK_BUFFER_INPUT) I
+# set ::env(CLK_BUFFER_OUTPUT) Z
+
+# TritonCTS configurations
+set ::env(CTS_ROOT_BUFFER) "CLKBUF_X16"
+set ::env(CTS_CLK_BUFFER_LIST) "CLKBUF_X2 CLKBUF_X4 CLKBUF_X8"
+set ::env(CTS_MAX_CAP) 0.5
+
+set ::env(FP_PDN_RAIL_WIDTH) 0.6
+
+# The library maximum transition is 8.9ns; setting it to lower value
+set ::env(DEFAULT_MAX_TRAN) 3
+
diff --git a/gf180mcu/openlane/gf180mcu_fd_sc_mcu9t5v0/no_synth.cells b/gf180mcu/openlane/gf180mcu_fd_sc_mcu9t5v0/no_synth.cells
new file mode 100644
index 0000000..c096d02
--- /dev/null
+++ b/gf180mcu/openlane/gf180mcu_fd_sc_mcu9t5v0/no_synth.cells
@@ -0,0 +1,12 @@
+SDFFSNQ_X4
+SDFFQ_X1
+SDFFQ_X2
+SDFFQ_X4
+SDFFRNQ_X1
+SDFFRNQ_X2
+SDFFRNQ_X4
+SDFFRSNQ_X1
+SDFFRSNQ_X2
+SDFFRSNQ_X4
+SDFFSNQ_X1
+SDFFSNQ_X2
\ No newline at end of file
diff --git a/gf180mcu/openlane/gf180mcu_fd_sc_mcu9t5v0/tracks.info b/gf180mcu/openlane/gf180mcu_fd_sc_mcu9t5v0/tracks.info
new file mode 100644
index 0000000..613fedd
--- /dev/null
+++ b/gf180mcu/openlane/gf180mcu_fd_sc_mcu9t5v0/tracks.info
@@ -0,0 +1,11 @@
+Metal1 X 0.28 0.56
+Metal1 Y 0.28 0.56
+Metal2 X 0.28 0.56
+Metal2 Y 0.28 0.56
+Metal3 X 0.28 0.56
+Metal3 Y 0.28 0.56
+Metal4 X 0.28 0.56
+Metal4 Y 0.28 0.56
+Metal5 X 0.28 0.56
+Metal5 Y 0.28 0.56
+
diff --git a/gf180mcu/openlane/rules.openrcx.gf180mcuC.max.magic b/gf180mcu/openlane/rules.openrcx.gf180mcuC.max.magic
new file mode 100644
index 0000000..8339743
--- /dev/null
+++ b/gf180mcu/openlane/rules.openrcx.gf180mcuC.max.magic
@@ -0,0 +1,1143 @@
+Extraction Rules for OpenRCX
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diff --git a/gf180mcu/openlane/rules.openrcx.gf180mcuC.min.magic b/gf180mcu/openlane/rules.openrcx.gf180mcuC.min.magic
new file mode 100644
index 0000000..731a39d
--- /dev/null
+++ b/gf180mcu/openlane/rules.openrcx.gf180mcuC.min.magic
@@ -0,0 +1,1143 @@
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diff --git a/gf180mcu/openlane/rules.openrcx.gf180mcuC.nom.magic b/gf180mcu/openlane/rules.openrcx.gf180mcuC.nom.magic
new file mode 100644
index 0000000..9155f10
--- /dev/null
+++ b/gf180mcu/openlane/rules.openrcx.gf180mcuC.nom.magic
@@ -0,0 +1,1143 @@
+Extraction Rules for OpenRCX
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+1.61 6.7944e-05 8.0017e-06 6.88705e-05
+1.84 5.94509e-05 8.83391e-06 6.88705e-05
+2.07 5.28453e-05 9.66884e-06 6.88705e-05
+2.3 4.75606e-05 1.05031e-05 6.88705e-05
+2.76 3.9634e-05 1.21519e-05 6.88705e-05
+3.68 2.97255e-05 1.52593e-05 6.88705e-05
+4.6 2.37804e-05 1.79134e-05 6.88705e-05
+5.52 0 3.97324e-05 6.88705e-05
+END DIST
+
+Metal 5 OVER 2
+DIST count 12 width 0.44
+0.46 0.000237804 4.87476e-06 6.88705e-05
+0.92 0.000118902 6.66038e-06 6.88705e-05
+1.15 9.51217e-05 7.59455e-06 6.88705e-05
+1.38 7.92681e-05 8.5529e-06 6.88705e-05
+1.61 6.7944e-05 9.5272e-06 6.88705e-05
+1.84 5.94509e-05 1.05147e-05 6.88705e-05
+2.07 5.28453e-05 1.15091e-05 6.88705e-05
+2.3 4.75606e-05 1.25061e-05 6.88705e-05
+2.76 3.9634e-05 1.44849e-05 6.88705e-05
+3.68 2.97255e-05 1.82287e-05 6.88705e-05
+4.6 2.37804e-05 2.14161e-05 6.88705e-05
+5.52 0 4.3611e-05 6.88705e-05
+END DIST
+
+Metal 5 OVER 3
+DIST count 12 width 0.44
+0.46 0.000237804 6.6204e-06 6.88705e-05
+0.92 0.000118902 8.84135e-06 6.88705e-05
+1.15 9.51217e-05 1.0022e-05 6.88705e-05
+1.38 7.92681e-05 1.12393e-05 6.88705e-05
+1.61 6.7944e-05 1.24871e-05 6.88705e-05
+1.84 5.94509e-05 1.37588e-05 6.88705e-05
+2.07 5.28453e-05 1.50446e-05 6.88705e-05
+2.3 4.75606e-05 1.63384e-05 6.88705e-05
+2.76 3.9634e-05 1.89198e-05 6.88705e-05
+3.68 2.97255e-05 2.38329e-05 6.88705e-05
+4.6 2.37804e-05 2.8015e-05 6.88705e-05
+5.52 0 5.09186e-05 6.88705e-05
+END DIST
+
+Metal 5 OVER 4
+DIST count 12 width 0.44
+0.46 0.000237804 1.23625e-05 6.88705e-05
+0.92 0.000118902 1.55908e-05 6.88705e-05
+1.15 9.51217e-05 1.73344e-05 6.88705e-05
+1.38 7.92681e-05 1.91508e-05 6.88705e-05
+1.61 6.7944e-05 2.10263e-05 6.88705e-05
+1.84 5.94509e-05 2.29492e-05 6.88705e-05
+2.07 5.28453e-05 2.4906e-05 6.88705e-05
+2.3 4.75606e-05 2.68852e-05 6.88705e-05
+2.76 3.9634e-05 3.08553e-05 6.88705e-05
+3.68 2.97255e-05 3.84576e-05 6.88705e-05
+4.6 2.37804e-05 4.49333e-05 6.88705e-05
+5.52 0 6.9463e-05 6.88705e-05
+END DIST
+
+Metal 5 UNDER
+WIDTH Table 0 entries: 
+
+Metal 5 DIAGUNDER
+WIDTH Table 0 entries: 
+END DensityModel 0
diff --git a/gf180mcu/qflow/gf180mcu.par b/gf180mcu/qflow/gf180mcu.par
new file mode 100644
index 0000000..e75fc45
--- /dev/null
+++ b/gf180mcu/qflow/gf180mcu.par
@@ -0,0 +1,218 @@
+# TECHNAME.par --- Parameter file for GrayWolf
+# NOTE:  all distance units are in centimicrons unless otherwise stated
+# WARNING: this is NOT tcl syntax! No Comments on end of actual data line.
+
+RULES
+    # values are resistance in ohms/sq and capacitance in fF/um^2
+    # TODO: properly pick directions
+    layer metal1 0.105 0.0001 horizontal
+    layer metal2 0.105 0.0001 vertical
+#ifdef METALS4 || METALS5 || METALS6
+    layer metal3 0.105 0.0001 horizontal
+#endif
+#ifdef METALS5 || METALS6
+    layer metal4 0.105 0.0001 vertical
+#endif
+#ifdef METALS6
+    layer metal5 0.105 0.0001 horizontal
+#endif
+#ifndef THICKMET
+    layer metaltp 0.043 0.0001 horizontal
+#endif
+    via via12 metal1 metal2
+#ifdef METALS4 || METALS5 || METALS6
+    via via23 metal2 metal3
+#endif
+#ifdef METALS5 || METALS6
+    via via34 metal3 metal4
+#endif
+#ifdef METALS6
+    via via45 metal4 metal5
+#endif
+#ifdef THICKMET
+#ifdef METALS4
+    via viatk metal3 metaltk
+#endif
+#ifdef METALS5
+    via viatk metal4 metaltk
+#endif
+#ifdef METALS6
+    via viatk metal5 metaltk
+#endif
+#else (!THICKMET)
+#ifdef METALS4
+    via viatp metal3 metaltp
+#endif
+#ifdef METALS5
+    via viatp metal4 metaltp
+#endif
+#ifdef METALS6
+    via viatp metal5 metaltp
+#endif
+#endif (!THICKMET)
+
+              # 0.5 um
+    width metal1 50
+    width metal2 60
+              # 0.6 um
+#ifdef METALS4 || METALS5 || METALS6
+    width metal3 60
+#endif
+#ifdef METALS5 || METALS6
+    width metal4 60
+#endif
+#ifdef METALS6
+    width metal5 60
+#endif
+#ifdef THICKMET
+    width metaltk 120
+#else
+    width metaltp 120
+#endif
+
+    # TODO verify these two numbers
+    width via12 50
+#ifdef METALS4 || METALS5 || METALS6
+    width via23 50
+#endif
+#ifdef METALS5 || METALS6
+    width via34 50
+#endif
+#ifdef METALS6
+    width via45 50
+#endif
+#ifdef THICKMET
+    width viatk 500
+#else
+    width viatp 120
+#endif
+
+    # Set spacing = track pitch - width, so that GrayWolf places pins
+    # on the right pitch.
+    # Pitches are (in um):
+    # metal1 = 200,  metal2 = 160,  metal3 = 200,  metal4 = 320
+## pitch m1: 1.3um  m2: 1.4um  m3: 1.3um
+## width m1: 0.5um  m2: 0.6um  m3: 0.6um
+## space     0.8        0.8        0.7     (pitch calc)
+## fab-space 0.45       0.5        0.6
+
+    spacing metal1 metal1 80
+    spacing metal2 metal2 80
+#ifdef METALS4 || METALS5 || METALS6
+    spacing metal3 metal3 80
+#endif
+#ifdef METALS5 || METALS6
+    spacing metal4 metal4 80
+#endif
+#ifdef METALS6
+    spacing metal5 metal5 80
+#endif
+#ifdef THICKMET
+    spacing metaltk metaltk 250
+#else
+    spacing metaltp metaltp 160
+#endif
+
+    # (WAS:) Stacked vias allowed
+    # spacing via12 via23 0
+
+    # To disable Stacked?: give non-zero spacing (centimicrons = 10 nanometer = 1/100 of micron)
+    # TODO need real value here:
+#ifdef METALS4 || METALS5 || METALS6
+    spacing via12 via23 0
+#endif
+#ifdef METALS5 || METALS6
+    spacing via23 via34 0
+#endif
+#ifdef METALS6
+    spacing via34 via45 0
+#endif
+#ifdef THICKMET
+#ifdef METALS4
+    spacing via23 viatk 60
+#endif
+#ifdef METALS5
+    spacing via34 viatk 60
+#endif
+#ifdef METALS6
+    spacing via45 viatk 60
+#endif
+#else (!THICKMET)
+#ifdef METALS4
+    spacing via23 viatp 60
+#endif
+#ifdef METALS5
+    spacing via34 viatp 60
+#endif
+#ifdef METALS6
+    spacing via45 viatp 60
+#endif
+#endif (!THICKMET)
+
+                       # .2um .15um
+    overhang via12 metal1 20
+    overhang via12 metal2 15
+
+#ifdef METALS4 || METALS5 || METALS6
+    overhang via23 metal2 20
+    overhang via23 metal3 15
+#endif
+#ifdef METALS5 || METALS6
+    overhang via34 metal3 14
+    overhang via34 metal4 16
+#endif
+#ifdef METALS6
+    overhang via45 metal4 14
+    overhang via45 metal5 16
+#endif
+#ifdef THICKMET
+#ifdef METALS4
+    overhang viatk metal3 14
+#endif
+#ifdef METALS5
+    overhang viatk metal4 14
+#endif
+#ifdef METALS6
+    overhang viatk metal5 14
+#endif
+#else (!THICKMET)
+#ifdef METALS4
+    overhang viatp metal3 14
+#endif
+#ifdef METALS5
+    overhang viatp metal4 14
+#endif
+#ifdef METALS6
+    overhang viatp metal5 14
+#endif
+#endif
+
+#ifndef THICKMET
+    overhang viatp metaltp 16
+#endif
+ENDRULES
+
+*vertical_wire_weight : 1.0
+*vertical_path_weight : 1.0
+*padspacing           : variable
+*rowSep		      : 0.0   0
+# Value 130:  Change to X track pitch for lower metal layers
+*track.pitch	      : 46
+*graphics.wait        : off
+*last_chance.wait     : off
+*random.seed	      : 12345
+# TODO: proper track.pitch number above, plus feedThruWidth below
+
+TWMC*chip.aspect.ratio : 1.0
+
+# Value 46:  Minimum size fill cell (FILL1) width in centimicrons.
+TWSC*feedThruWidth    : 46 layer 1
+TWSC*do.global.route  : on
+TWSC*ignore_feeds     : true
+TWSC*call_row_evener  : true
+TWSC*even_rows_maximally : true
+# TWSC*no.graphics    : on
+
+GENR*row_to_tile_spacing: 1
+# GENR*numrows		: 6
+GENR*flip_alternate_rows : 1
diff --git a/gf180mcu/qflow/gf180mcu.sh b/gf180mcu/qflow/gf180mcu.sh
new file mode 100755
index 0000000..10db77f
--- /dev/null
+++ b/gf180mcu/qflow/gf180mcu.sh
@@ -0,0 +1,116 @@
+#!/bin/tcsh
+#---------------------------------------------------------------
+# Shell script setting up all variables used by the qflow scripts
+# for this project
+#---------------------------------------------------------------
+
+# The LEF file containing standard cell macros
+
+#ifdef EF_STYLE
+set leffile=LOCAL_PREFIX/TECHNAME/libs.ref/lef/LIBRARY/LIBRARY.lef
+#else
+set leffile=LOCAL_PREFIX/TECHNAME/libs.ref/LIBRARY/lef/LIBRARY.lef
+#endif
+
+# The SPICE netlist containing subcell definitions for all the standard cells
+
+#ifdef EF_STYLE
+set spicefile=LOCAL_PREFIX/TECHNAME/libs.ref/spi/LIBRARY/LIBRARY.spi
+#else
+set spicefile=LOCAL_PREFIX/TECHNAME/libs.ref/LIBRARY/spice/LIBRARY.spice
+#endif
+
+# The liberty format file containing standard cell timing and function information
+
+#ifdef EF_STYLE
+set libertyfile=LOCAL_PREFIX/TECHNAME/libs.ref/lib/LIBRARY/LIBRARY__ss_1p62v_125c.lib
+#else
+set libertyfile=LOCAL_PREFIX/TECHNAME/libs.ref/LIBRARY/liberty/LIBRARY__ss_1p62v_125c.lib
+#endif
+
+# If there is another LEF file containing technology information
+# that is separate from the file containing standard cell macros,
+# set this.  Otherwise, leave it defined as an empty string.
+
+# NOTE:  Backend-specific technology LEF files come from BEOL-specific
+# directories, and all have the same name.
+
+set techleffile=LOCAL_PREFIX/TECHNAME/TECHLEF_PATH/LIBRARY.nom.tlef
+
+# All cells below should be the lowest output drive strength value,
+# if the standard cell set has multiple cells with different drive
+# strengths.  Comment out any cells that do not exist.
+
+set flopcell=LIBRARY__dffq_x1	;# Standard positive-clocked DFF, no set or reset
+set flopsetreset=LIBRARY__dffrsnq_x1 ;# DFF with both set and clear
+set setpin=SETN		;# The name of the set pin on DFFs
+set resetpin=RN		;# The name of the clear/reset pin on DFFs
+set setpininvert=1	;# Set this to 1 if the set pin is inverted (!set)
+set resetpininvert=1	;# Set this to 1 if the reset pin is inverted (!reset)
+set floppinout=Q	;# Name of the output pin on DFFs
+set floppinin=D		;# Name of the output pin on DFFs
+set floppinclk=CLK	;# Name of the clock pin on DFFs
+set bufcell=LIBRARY__buf_x2	;# Minimum drive strength buffer cell
+set bufpin_in=I		;# Name of input port to buffer cell
+set bufpin_out=Z	;# Name of output port to buffer cell
+set clkbufcell=LIBRARY__clkbuf_x2	;# Minimum drive strength buffer cell
+set clkbufpin_in=I	;# Name of input port to buffer cell
+set clkbufpin_out=Z	;# Name of output port to buffer cell
+set inverter=LIBRARY__inv_x1	;# Minimum drive strength inverter cell
+set invertpin_in=I	;# Name of input port to inverter cell
+set invertpin_out=ZN	;# Name of output port to inverter cell
+set norgate=LIBRARY__nor2_x1	;# 2-input NOR gate, minimum drive strength
+set norpin_in1=A1	;# Name of first input pin to NOR gate
+set norpin_in2=A2	;# Name of second input pin to NOR gate
+set norpin_out=ZN	;# Name of output pin from OR gate
+set nandgate=LIBRARY__nand2_x1	;# 2-input NAND gate, minimum drive strength
+set nandpin_in1=A1	;# Name of first input pin to NAND gate
+set nandpin_in2=A2	;# Name of second input pin to NAND gate
+set nandpin_out=ZN	;# Name of output pin from NAND gate
+# Synchronize it with .par's TWSC*feedThruWidth
+set fillcell=LIBRARY__fill	;# Spacer (filler) cell (prefix, if more than one)
+set decapcell=LIBRARY__fillcap	;# Decap (filler) cell (prefix, if more than one)
+set antennacell=LIBRARY__antenna	;# Antenna (filler) cell (prefix, if more than one)
+set antennapin_in="I"	;# Antenna cell input connection
+set bodytiecell=LIBRARY__filltie
+
+# yosys tries to eliminate use of these; depends on source .v
+set tiehi="tieh"	;# Cell to connect to power, if one exists
+set tiehipin_out="ZN"	;# Output pin name of tiehi cell, if it exists
+set tielo="tiel"	;# Cell to connect to ground, if one exists
+set tielopin_out="Z"	;# Output pin name of tielo cell, if it exists
+
+set gndnet="VSS,VPW"	;# Name used for ground pins in standard cells
+set vddnet="VDD,VNW"	;# Name used for power pins in standard cells
+
+set separator=x		;# Separator between gate names and drive strengths
+set techfile=LOCAL_PREFIX/TECHNAME/MAGIC_CURRENT/TECHNAME.tech	;# magic techfile
+set magicrc=LOCAL_PREFIX/TECHNAME/MAGIC_CURRENT/TECHNAME.magicrc	;# magic startup script
+set magic_display="XR" 	;# magic display, defeat display query and OGL preference
+set netgen_setup=LOCAL_PREFIX/TECHNAME/libs.tech/netgen/TECHNAME_setup.tcl	;# netgen setup file for LVS
+#ifdef EF_STYLE
+set gdsfile=LOCAL_PREFIX/TECHNAME/libs.ref/gds/LIBRARY/LIBRARY.gds	;# GDS database of standard cells
+set verilogfile=LOCAL_PREFIX/TECHNAME/libs.ref/verilog/LIBRARY/LIBRARY.v	;# Verilog models of standard cells
+#else
+set gdsfile=LOCAL_PREFIX/TECHNAME/libs.ref/LIBRARY/gds/LIBRARY.gds	;# GDS database of standard cells
+set verilogfile=LOCAL_PREFIX/TECHNAME/libs.ref/LIBRARY/verilog/LIBRARY.v	;# Verilog models of standard cells
+#endif
+
+# Set a conditional default in the project_vars.sh file for this process
+set postproc_options="-anchors"
+#ifdef METALS3
+set route_layers = 3
+#endif (METALS3)
+#ifdef METALS4
+set route_layers = 4
+#endif (METALS4)
+#ifdef METALS5
+set route_layers = 5
+#endif (METALS5)
+#ifdef METALS6
+set route_layers = 6
+#endif (METALS6)
+set fill_ratios="0,70,10,20"
+set fanout_options="-l 150 -c 15"
+set addspacers_options="-stripe 2.5 50.0 PG"
+set xspice_options="-io_time=250p -time=50p -idelay=20p -odelay=50p -cload=250f"
diff --git a/scripts/configure b/scripts/configure
index 801e10c..2ecf8b7 100755
--- a/scripts/configure
+++ b/scripts/configure
@@ -590,6 +590,11 @@
 OPENPDKS_TOP
 ENABLED_TECHS
 EF_STYLE
+GF180MCU_FD_IP_SRAM_PATH
+GF180MCU_FD_SC_MCU9T5V0_PATH
+GF180MCU_FD_SC_MCU7T5V0_PATH
+GF180MCU_FD_IO_PATH
+GF180MCU_FD_PR_PATH
 SKY130_OSU_T18_PATH
 SKY130_OSU_T15_PATH
 SKY130_OSU_T12_PATH
@@ -611,6 +616,9 @@
 SKY130_SOURCE_PATH
 SKY130_ENABLED_VARIANTS
 SKY130_LINK_TARGETS
+GF180MCU_SOURCE_PATH
+GF180MCU_ENABLED_VARIANTS
+GF180MCU_LINK_TARGETS
 SED
 pkgpyexecdir
 pyexecdir
@@ -663,6 +671,9 @@
 ac_subst_files=''
 ac_user_opts='
 enable_option_checking
+enable_gf180mcu_pdk
+with_gf180mcu_link_targets
+with_gf180mcu_variants
 enable_sky130_pdk
 with_sky130_link_targets
 with_sky130_variants
@@ -681,6 +692,11 @@
 enable_osu_t12_sky130
 enable_osu_t15_sky130
 enable_osu_t18_sky130
+enable_primitive_gf180mcu
+enable_io_gf180mcu
+enable_sc_7t5v0_gf180mcu
+enable_sc_9t5v0_gf180mcu
+enable_sram_gf180mcu
 with_ef_style
 '
       ac_precious_vars='build_alias
@@ -1307,8 +1323,8 @@
   --disable-option-checking  ignore unrecognized --enable/--with options
   --disable-FEATURE       do not include FEATURE (same as --enable-FEATURE=no)
   --enable-FEATURE[=ARG]  include FEATURE [ARG=yes]
-  --enable-sky130-pdk=[/path/to/sky130/] --disable-sky130-pdk
-                          "location of the source files for the sky130 (pdks
+  --enable-gf180mcu-pdk=[/path/to/gf180mcu/] --disable-gf180mcu-pdk
+                          "location of the source files for the gf180mcu (pdks
                           with a pdk_url file can automatically download them
                           if the path is omitted)"
   --enable-klayout
@@ -1363,14 +1379,29 @@
   --enable-osu-t18-sky130[=path]
                           Install sky130_osu_t18. If path is omitted, the repository
                           will be downloaded. [default=disabled]
+  --enable-primitive-gf180mcu[=path]
+                          Install gf180mcu_fd_pr. If path is omitted, the repository
+                          will be downloaded. [default=enabled]
+  --enable-io-gf180mcu[=path]
+                          Install gf180mcu_fd_io. If path is omitted, the repository
+                          will be downloaded. [default=enabled]
+  --enable-sc-7t5v0-gf180mcu[=path]
+                          Install gf180mcu_fd_sc_mcu7t5v0. If path is omitted, the repository
+                          will be downloaded. [default=enabled]
+  --enable-sc-9t5v0-gf180mcu[=path]
+                          Install gf180mcu_fd_sc_mcu9t5v0. If path is omitted, the repository
+                          will be downloaded. [default=enabled]
+  --enable-sram-gf180mcu[=path]
+                          Install gf180mcu_fd_ip_sram. If path is omitted, the repository
+                          will be downloaded. [default=enabled]
 
 Optional Packages:
   --with-PACKAGE[=ARG]    use PACKAGE [ARG=yes]
   --without-PACKAGE       do not use PACKAGE (same as --with-PACKAGE=no)
-  --with-sky130-link-targets=none|source
+  --with-gf180mcu-link-targets=none|source
                           "make symbolic links to existing files
                           [default=none]"
-  --with-sky130-variants=all|A|B|...
+  --with-gf180mcu-variants=all|A|B|...
                           "compile/install specified PDK variants only
                           [default=all]"
   --with-ef-style         Use efabless style file system structure
@@ -1937,7 +1968,7 @@
 if ${am_cv_python_version+:} false; then :
   $as_echo_n "(cached) " >&6
 else
-  am_cv_python_version=`$PYTHON -c "import sys; sys.stdout.write(sys.version[:3])"`
+  am_cv_python_version=`$PYTHON -c "import sys; print('%u.%u' % sys.version_info[:2])"`
 fi
 { $as_echo "$as_me:${as_lineno-$LINENO}: result: $am_cv_python_version" >&5
 $as_echo "$am_cv_python_version" >&6; }
@@ -2203,13 +2234,111 @@
 # check for the source and install paths for each PDK.
 
 
-{ $as_echo "$as_me:${as_lineno-$LINENO}: Found technology directories: sky130" >&5
-$as_echo "$as_me: Found technology directories: sky130" >&6;}
+{ $as_echo "$as_me:${as_lineno-$LINENO}: Found technology directories: gf180mcu sky130" >&5
+$as_echo "$as_me: Found technology directories: gf180mcu sky130" >&6;}
 
 
 
     # --enable-pdk-[pdk]=/path/to/pdk
 
+        echo "Checking technology gf180mcu..."
+
+
+        GF180MCU_ENABLED_VARIANTS="all"
+        GF180MCU_SOURCE_PATH=""
+        GF180MCU_LINK_TARGETS="none"
+        GF180MCU_AUTO="0"
+
+        # Check whether --enable-gf180mcu-gf180mcu was given.
+if test "${enable_gf180mcu_pdk+set}" = set; then :
+  enableval=$enable_gf180mcu_pdk;
+                if test "$enableval" == "yes" -o "$enableval" == "YES"; then
+                    export GF180MCU_SOURCE_PATH=../sources/gf180mcu-pdk
+            	    GF180MCU_AUTO="1"
+		    ENABLED_TECHS="$ENABLED_TECHS gf180mcu"
+                elif test "$enableval" == "no" -o "$enableval" == "NO"; then
+                    echo "Disabling gf180mcu..."
+                else
+                    GF180MCU_SOURCE_PATH=$enableval
+		    ENABLED_TECHS="$ENABLED_TECHS gf180mcu"
+                fi
+
+fi
+
+
+        if [ "$GF180MCU_SOURCE_PATH" != "" ]; then
+            GF180MCU_SOURCE_PATH=`realpath $GF180MCU_SOURCE_PATH`
+            GF180MCU_BASENAME=`basename $GF180MCU_SOURCE_PATH`
+	    if [ "$GF180MCU_BASENAME" = "libraries" ]; then
+		GF180MCU_SOURCE_PATH=`dirname $GF180MCU_SOURCE_PATH`
+	    fi
+            # Basic check that the PDK path exists, unless depending on Makefile
+	    # to download it automatically.
+            if [ "$GF180MCU_AUTO" = "0" ]; then
+                { $as_echo "$as_me:${as_lineno-$LINENO}: Checking specified path for 'gf180mcu' at $GF180MCU_SOURCE_PATH" >&5
+$as_echo "$as_me: Checking specified path for 'gf180mcu' at $GF180MCU_SOURCE_PATH" >&6;}
+                as_ac_File=`$as_echo "ac_cv_file_$GF180MCU_SOURCE_PATH" | $as_tr_sh`
+{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for $GF180MCU_SOURCE_PATH" >&5
+$as_echo_n "checking for $GF180MCU_SOURCE_PATH... " >&6; }
+if eval \${$as_ac_File+:} false; then :
+  $as_echo_n "(cached) " >&6
+else
+  test "$cross_compiling" = yes &&
+  as_fn_error $? "cannot check for file existence when cross compiling" "$LINENO" 5
+if test -r "$GF180MCU_SOURCE_PATH"; then
+  eval "$as_ac_File=yes"
+else
+  eval "$as_ac_File=no"
+fi
+fi
+eval ac_res=\$$as_ac_File
+	       { $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_res" >&5
+$as_echo "$ac_res" >&6; }
+if eval test \"x\$"$as_ac_File"\" = x"yes"; then :
+
+                    { $as_echo "$as_me:${as_lineno-$LINENO}: 'gf180mcu' source path found at $GF180MCU_SOURCE_PATH" >&5
+$as_echo "$as_me: 'gf180mcu' source path found at $GF180MCU_SOURCE_PATH" >&6;}
+
+else
+
+                    as_fn_error $? "Specified path for 'gf180mcu' at $GF180MCU_SOURCE_PATH not found" "$LINENO" 5
+
+fi
+
+	    else
+		{ $as_echo "$as_me:${as_lineno-$LINENO}: PDK 'gf180mcu' will be downloaded automatically during make." >&5
+$as_echo "$as_me: PDK 'gf180mcu' will be downloaded automatically during make." >&6;}
+	    fi
+
+            # --with-pdk-link-targets=PDK_LINK_TARGETS
+
+# Check whether --with-gf180mcu-link-targets was given.
+if test "${with_gf180mcu_link_targets+set}" = set; then :
+  withval=$with_gf180mcu_link_targets; GF180MCU_LINK_TARGETS=$with_gf180mcu_link_targets
+
+fi
+
+
+            { $as_echo "$as_me:${as_lineno-$LINENO}: Link targets set to $GF180MCU_LINK_TARGETS" >&5
+$as_echo "$as_me: Link targets set to $GF180MCU_LINK_TARGETS" >&6;}
+
+            # --with-pdk-variants=PDK_ENABLED_VARIANTS
+
+# Check whether --with-gf180mcu-variants was given.
+if test "${with_gf180mcu_variants+set}" = set; then :
+  withval=$with_gf180mcu_variants; GF180MCU_ENABLED_VARIANTS=$with_gf180mcu_variants
+
+fi
+
+
+            { $as_echo "$as_me:${as_lineno-$LINENO}: Enabled variants set to $GF180MCU_ENABLED_VARIANTS" >&5
+$as_echo "$as_me: Enabled variants set to $GF180MCU_ENABLED_VARIANTS" >&6;}
+        fi
+
+
+
+
+
         echo "Checking technology sky130..."
 
 
@@ -2311,7 +2440,7 @@
 
 
 # Export the list of known technologies to the Makefile
-ALL_TECHS="sky130"
+ALL_TECHS="gf180mcu sky130"
 
 
 # Set variables for tool setups
@@ -2523,6 +2652,11 @@
 # Optional installations (like the above, but disabled by default)
 
 
+# NOTE:  This part of the configuration should be based off of the
+# contents of a file with a predetermined name existing in each of
+# the open PDK directories.
+
+# SkyWater sky130 essential
 
 
 
@@ -2692,6 +2826,7 @@
 
 
 
+# SkyWater sky130 optional
 
 
 
@@ -2857,6 +2992,221 @@
 
 
 
+# GlobalFoundries gf180mcu essential
+
+
+
+
+
+
+    # echo target targetvar flag location
+
+    GF180MCU_FD_PR_PATH=""
+
+    # Check whether --enable-primitive-gf180mcu was given.
+if test "${enable_primitive_gf180mcu+set}" = set; then :
+  enableval=$enable_primitive_gf180mcu;
+            if test "$enableval" == "yes" -o "$enableval" == "YES"; then
+                { $as_echo "$as_me:${as_lineno-$LINENO}: Package 'gf180mcu_fd_pr' will be installed automatically during make." >&5
+$as_echo "$as_me: Package 'gf180mcu_fd_pr' will be installed automatically during make." >&6;}
+        	export GF180MCU_FD_PR_PATH=../sources/gf180mcu_fd_pr
+            elif test "$enableval" == "no" -o "$enableval" == "NO"; then
+                { $as_echo "$as_me:${as_lineno-$LINENO}: Disabling package 'gf180mcu_fd_pr'" >&5
+$as_echo "$as_me: Disabling package 'gf180mcu_fd_pr'" >&6;}
+    		export GF180MCU_FD_PR_PATH=""
+            else
+                GF180MCU_FD_PR_PATH=$enableval
+                { $as_echo "$as_me:${as_lineno-$LINENO}: Enabling package 'gf180mcu_fd_pr' at $GF180MCU_FD_PR_PATH" >&5
+$as_echo "$as_me: Enabling package 'gf180mcu_fd_pr' at $GF180MCU_FD_PR_PATH" >&6;}
+            fi
+            GF180MCU_FD_PR_PATH=`realpath $GF180MCU_FD_PR_PATH`
+
+else
+
+            { $as_echo "$as_me:${as_lineno-$LINENO}: Package 'gf180mcu_fd_pr' will be installed automatically during make." >&5
+$as_echo "$as_me: Package 'gf180mcu_fd_pr' will be installed automatically during make." >&6;}
+	    GF180MCU_FD_PR_PATH=../sources/gf180mcu_fd_pr
+
+
+fi
+
+
+
+
+
+
+
+
+
+
+
+
+    # echo target targetvar flag location
+
+    GF180MCU_FD_IO_PATH=""
+
+    # Check whether --enable-io-gf180mcu was given.
+if test "${enable_io_gf180mcu+set}" = set; then :
+  enableval=$enable_io_gf180mcu;
+            if test "$enableval" == "yes" -o "$enableval" == "YES"; then
+                { $as_echo "$as_me:${as_lineno-$LINENO}: Package 'gf180mcu_fd_io' will be installed automatically during make." >&5
+$as_echo "$as_me: Package 'gf180mcu_fd_io' will be installed automatically during make." >&6;}
+        	export GF180MCU_FD_IO_PATH=../sources/gf180mcu_fd_io
+            elif test "$enableval" == "no" -o "$enableval" == "NO"; then
+                { $as_echo "$as_me:${as_lineno-$LINENO}: Disabling package 'gf180mcu_fd_io'" >&5
+$as_echo "$as_me: Disabling package 'gf180mcu_fd_io'" >&6;}
+    		export GF180MCU_FD_IO_PATH=""
+            else
+                GF180MCU_FD_IO_PATH=$enableval
+                { $as_echo "$as_me:${as_lineno-$LINENO}: Enabling package 'gf180mcu_fd_io' at $GF180MCU_FD_IO_PATH" >&5
+$as_echo "$as_me: Enabling package 'gf180mcu_fd_io' at $GF180MCU_FD_IO_PATH" >&6;}
+            fi
+            GF180MCU_FD_IO_PATH=`realpath $GF180MCU_FD_IO_PATH`
+
+else
+
+            { $as_echo "$as_me:${as_lineno-$LINENO}: Package 'gf180mcu_fd_io' will be installed automatically during make." >&5
+$as_echo "$as_me: Package 'gf180mcu_fd_io' will be installed automatically during make." >&6;}
+	    GF180MCU_FD_IO_PATH=../sources/gf180mcu_fd_io
+
+
+fi
+
+
+
+
+
+
+
+
+
+
+
+
+    # echo target targetvar flag location
+
+    GF180MCU_FD_SC_MCU7T5V0_PATH=""
+
+    # Check whether --enable-sc-7t5v0-gf180mcu was given.
+if test "${enable_sc_7t5v0_gf180mcu+set}" = set; then :
+  enableval=$enable_sc_7t5v0_gf180mcu;
+            if test "$enableval" == "yes" -o "$enableval" == "YES"; then
+                { $as_echo "$as_me:${as_lineno-$LINENO}: Package 'gf180mcu_fd_sc_mcu7t5v0' will be installed automatically during make." >&5
+$as_echo "$as_me: Package 'gf180mcu_fd_sc_mcu7t5v0' will be installed automatically during make." >&6;}
+        	export GF180MCU_FD_SC_MCU7T5V0_PATH=../sources/gf180mcu_fd_sc_mcu7t5v0
+            elif test "$enableval" == "no" -o "$enableval" == "NO"; then
+                { $as_echo "$as_me:${as_lineno-$LINENO}: Disabling package 'gf180mcu_fd_sc_mcu7t5v0'" >&5
+$as_echo "$as_me: Disabling package 'gf180mcu_fd_sc_mcu7t5v0'" >&6;}
+    		export GF180MCU_FD_SC_MCU7T5V0_PATH=""
+            else
+                GF180MCU_FD_SC_MCU7T5V0_PATH=$enableval
+                { $as_echo "$as_me:${as_lineno-$LINENO}: Enabling package 'gf180mcu_fd_sc_mcu7t5v0' at $GF180MCU_FD_SC_MCU7T5V0_PATH" >&5
+$as_echo "$as_me: Enabling package 'gf180mcu_fd_sc_mcu7t5v0' at $GF180MCU_FD_SC_MCU7T5V0_PATH" >&6;}
+            fi
+            GF180MCU_FD_SC_MCU7T5V0_PATH=`realpath $GF180MCU_FD_SC_MCU7T5V0_PATH`
+
+else
+
+            { $as_echo "$as_me:${as_lineno-$LINENO}: Package 'gf180mcu_fd_sc_mcu7t5v0' will be installed automatically during make." >&5
+$as_echo "$as_me: Package 'gf180mcu_fd_sc_mcu7t5v0' will be installed automatically during make." >&6;}
+	    GF180MCU_FD_SC_MCU7T5V0_PATH=../sources/gf180mcu_fd_sc_mcu7t5v0
+
+
+fi
+
+
+
+
+
+
+
+
+
+
+
+
+    # echo target targetvar flag location
+
+    GF180MCU_FD_SC_MCU9T5V0_PATH=""
+
+    # Check whether --enable-sc-9t5v0-gf180mcu was given.
+if test "${enable_sc_9t5v0_gf180mcu+set}" = set; then :
+  enableval=$enable_sc_9t5v0_gf180mcu;
+            if test "$enableval" == "yes" -o "$enableval" == "YES"; then
+                { $as_echo "$as_me:${as_lineno-$LINENO}: Package 'gf180mcu_fd_sc_mcu9t5v0' will be installed automatically during make." >&5
+$as_echo "$as_me: Package 'gf180mcu_fd_sc_mcu9t5v0' will be installed automatically during make." >&6;}
+        	export GF180MCU_FD_SC_MCU9T5V0_PATH=../sources/gf180mcu_fd_sc_mcu9t5v0
+            elif test "$enableval" == "no" -o "$enableval" == "NO"; then
+                { $as_echo "$as_me:${as_lineno-$LINENO}: Disabling package 'gf180mcu_fd_sc_mcu9t5v0'" >&5
+$as_echo "$as_me: Disabling package 'gf180mcu_fd_sc_mcu9t5v0'" >&6;}
+    		export GF180MCU_FD_SC_MCU9T5V0_PATH=""
+            else
+                GF180MCU_FD_SC_MCU9T5V0_PATH=$enableval
+                { $as_echo "$as_me:${as_lineno-$LINENO}: Enabling package 'gf180mcu_fd_sc_mcu9t5v0' at $GF180MCU_FD_SC_MCU9T5V0_PATH" >&5
+$as_echo "$as_me: Enabling package 'gf180mcu_fd_sc_mcu9t5v0' at $GF180MCU_FD_SC_MCU9T5V0_PATH" >&6;}
+            fi
+            GF180MCU_FD_SC_MCU9T5V0_PATH=`realpath $GF180MCU_FD_SC_MCU9T5V0_PATH`
+
+else
+
+            { $as_echo "$as_me:${as_lineno-$LINENO}: Package 'gf180mcu_fd_sc_mcu9t5v0' will be installed automatically during make." >&5
+$as_echo "$as_me: Package 'gf180mcu_fd_sc_mcu9t5v0' will be installed automatically during make." >&6;}
+	    GF180MCU_FD_SC_MCU9T5V0_PATH=../sources/gf180mcu_fd_sc_mcu9t5v0
+
+
+fi
+
+
+
+
+
+
+
+
+
+
+
+
+    # echo target targetvar flag location
+
+    GF180MCU_FD_IP_SRAM_PATH=""
+
+    # Check whether --enable-sram-gf180mcu was given.
+if test "${enable_sram_gf180mcu+set}" = set; then :
+  enableval=$enable_sram_gf180mcu;
+            if test "$enableval" == "yes" -o "$enableval" == "YES"; then
+                { $as_echo "$as_me:${as_lineno-$LINENO}: Package 'gf180mcu_fd_ip_sram' will be installed automatically during make." >&5
+$as_echo "$as_me: Package 'gf180mcu_fd_ip_sram' will be installed automatically during make." >&6;}
+        	export GF180MCU_FD_IP_SRAM_PATH=../sources/gf180mcu_fd_ip_sram
+            elif test "$enableval" == "no" -o "$enableval" == "NO"; then
+                { $as_echo "$as_me:${as_lineno-$LINENO}: Disabling package 'gf180mcu_fd_ip_sram'" >&5
+$as_echo "$as_me: Disabling package 'gf180mcu_fd_ip_sram'" >&6;}
+    		export GF180MCU_FD_IP_SRAM_PATH=""
+            else
+                GF180MCU_FD_IP_SRAM_PATH=$enableval
+                { $as_echo "$as_me:${as_lineno-$LINENO}: Enabling package 'gf180mcu_fd_ip_sram' at $GF180MCU_FD_IP_SRAM_PATH" >&5
+$as_echo "$as_me: Enabling package 'gf180mcu_fd_ip_sram' at $GF180MCU_FD_IP_SRAM_PATH" >&6;}
+            fi
+            GF180MCU_FD_IP_SRAM_PATH=`realpath $GF180MCU_FD_IP_SRAM_PATH`
+
+else
+
+            { $as_echo "$as_me:${as_lineno-$LINENO}: Package 'gf180mcu_fd_ip_sram' will be installed automatically during make." >&5
+$as_echo "$as_me: Package 'gf180mcu_fd_ip_sram' will be installed automatically during make." >&6;}
+	    GF180MCU_FD_IP_SRAM_PATH=../sources/gf180mcu_fd_ip_sram
+
+
+fi
+
+
+
+
+
+
+
+# GlobalFoundries gf180mcu optional
+# (None yet)
+
 
 
 { $as_echo "$as_me:${as_lineno-$LINENO}: Tools enabled for PDK setup installation: klayout magic netgen irsim openlane qflow xschem" >&5
diff --git a/scripts/configure.ac b/scripts/configure.ac
index 5ad8ea4..77e73da 100755
--- a/scripts/configure.ac
+++ b/scripts/configure.ac
@@ -224,16 +224,32 @@
     AC_SUBST(targetvar[]_PATH)
 ])
 
+# NOTE:  This part of the configuration should be based off of the
+# contents of a file with a predetermined name existing in each of
+# the open PDK directories.
+
+# SkyWater sky130 essential
 M4_GEN_INSTALLATION(sky130_ml_xx_hd, alpha-sky130, ../sources)
 M4_GEN_INSTALLATION(xschem_sky130, xschem-sky130, ../sources)
 M4_GEN_INSTALLATION(klayout_sky130, klayout-sky130, ../sources)
 M4_GEN_INSTALLATION(precheck_sky130, precheck-sky130, ../sources)
 
+# SkyWater sky130 optional
 M4_OPT_INSTALLATION(sky130_sram_macros, sram-sky130, ../sources)
 M4_OPT_INSTALLATION(sky130_osu_t12, osu-t12-sky130, ../sources)
 M4_OPT_INSTALLATION(sky130_osu_t15, osu-t15-sky130, ../sources)
 M4_OPT_INSTALLATION(sky130_osu_t18, osu-t18-sky130, ../sources)
 
+# GlobalFoundries gf180mcu essential
+M4_GEN_INSTALLATION(gf180mcu_fd_pr, primitive-gf180mcu, ../sources)
+M4_GEN_INSTALLATION(gf180mcu_fd_io, io-gf180mcu, ../sources)
+M4_GEN_INSTALLATION(gf180mcu_fd_sc_mcu7t5v0, sc-7t5v0-gf180mcu, ../sources)
+M4_GEN_INSTALLATION(gf180mcu_fd_sc_mcu9t5v0, sc-9t5v0-gf180mcu, ../sources)
+M4_GEN_INSTALLATION(gf180mcu_fd_ip_sram, sram-gf180mcu, ../sources)
+
+# GlobalFoundries gf180mcu optional
+# (None yet)
+
 AC_DEFUN([M4_GEN_WITH_TOOLS], [
     m4_foreach_w(tool, $1, [
         m4_define([toolvar], [m4_normalize(m4_esyscmd(echo tool | tr "a-z-" "A-Z_"))])
diff --git a/sky130/Makefile.in b/sky130/Makefile.in
index 69e9049..da6e800 100644
--- a/sky130/Makefile.in
+++ b/sky130/Makefile.in
@@ -290,6 +290,22 @@
 else
     COMMIT_DEFS = -DOPEN_PDKS_COMMIT=${OPEN_PDKS_COMMIT}
 endif
+
+ifeq (${XSCHEM_PATH},)
+    COMMIT_DEFS += -DXSCHEM_COMMIT="unknown"
+else
+    COMMIT_DEFS += -DXSCHEM_COMMIT=$(shell cd ${XSCHEM_PATH} ; git rev-parse HEAD)
+endif
+ifeq (${KLAYOUT_PATH},)
+    COMMIT_DEFS += -DKLAYOUT_COMMIT="unknown"
+else
+    COMMIT_DEFS += -DKLAYOUT_COMMIT=$(shell cd ${KLAYOUT_PATH} ; git rev-parse HEAD)
+endif
+ifeq (${PRECHECK_PATH},)
+    COMMIT_DEFS += -DPRECHECK_COMMIT="unknown"
+else
+    COMMIT_DEFS += -DPRECHECK_COMMIT=$(shell cd ${PRECHECK_PATH} ; git rev-parse HEAD)
+endif
 ifeq (${ALPHA_PATH},)
     COMMIT_DEFS += -DALPHA_COMMIT="unknown"
 else
diff --git a/sky130/sky130.json b/sky130/sky130.json
index 1af4c5c..6dc1a66 100644
--- a/sky130/sky130.json
+++ b/sky130/sky130.json
@@ -78,7 +78,10 @@
         "sky130_sram_macros": "SRAM_COMMIT"
     },
     "other": {
-        "sky130_ml_xx_hd": "ALPHA_COMMIT"
+        "sky130_ml_xx_hd": "ALPHA_COMMIT",
+        "xschem_sky130": "XSCHEM_COMMIT",
+        "klayout_sky130": "KLAYOUT_COMMIT",
+        "precheck_sky130": "PRECHECK_COMMIT"
     },
     "build": {
         "open_pdks": "OPEN_PDKS_VERSION",
@@ -89,14 +92,16 @@
         "magic": "MAGIC_COMMIT"
     },
     "reference": {
-        "open_pdks": "d7faec2b6f384254449e0172c4f26083f77d3ff5",
-        "magic": "f7df5e7c86fb47c5fd445c846afddc6fbabad6ae",
+        "open_pdks": "fb6f374beff316f9a8e0b5585facfc18008c0f2d",
+        "magic": "43d5cc280413b0fd947b555bf1e8d79ea8681450",
         "skywater_pdk": "f70d8ca46961ff92719d8870a18a076370b85f6c",
-        "sky130_osu_sc_t12": "6af093f919721daec4bb256c4c40aaa8bc84f4bd",
-        "sky130_osu_sc_t15": "f1eef844734f73d3c79d83b82352118263eb7686",
-        "sky130_osu_sc_t18": "3128b623aaea315248d39173e09b49a3dc82aa40",
+        "sky130_osu_sc_t12": "ac90ef0c622a9377a16b5218d9da3ac4169eeaaf",
+        "sky130_osu_sc_t15": "95d1c19abb47e1b2945847acb4e817b1b8417c43",
+        "sky130_osu_sc_t18": "aa2b509f3c8f32ea94fdb55ac9768754667c1658",
         "sky130_sram_macros": "c2333394e0b0b9d9d71185678a8d8087715d5e3b",
         "sky130_ml_xx_hd": "6eb3b0718552b034f1bf1870285ff135e3fb2dcb",
-        "xschem_sky130": "16efae642739ba5c50aa2a40e403b036a5e31a6c"
+        "xschem_sky130": "5949895a0214f3471f16850297ea15e34a564edd",
+	"klayout_sky130": "85165d907f6b68e73bb25b9982cca20a87c98686",
+	"precheck_sky130": "07ace967fbe88e33844bf046bd9d30e1679580b7"
     }
-}
\ No newline at end of file
+}