)]}'
{
  "commit": "f55386ad4e747885743a3f252ae4e9629dccf0d8",
  "tree": "45676da0a9dacf6a75e4496742bc9cccac50c4a5",
  "parents": [
    "46dc5fed4d83c3681ea7f00dfdd7a550b42359af"
  ],
  "author": {
    "name": "Tim Edwards",
    "email": "tim@opencircuitdesign.com",
    "time": "Fri May 28 14:30:49 2021 -0400"
  },
  "committer": {
    "name": "Tim Edwards",
    "email": "tim@opencircuitdesign.com",
    "time": "Fri May 28 14:30:49 2021 -0400"
  },
  "message": "Corrected the verilog for sky130_ef_io, which was not separating the\npad and core signals on the sky130_fd_io base power pads.\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "57e2655aa9f6969d15faccf2a3591c1411877b00",
      "old_mode": 33188,
      "old_path": "sky130/custom/sky130_fd_io/verilog/sky130_ef_io.v",
      "new_id": "530a4cb12478b5692a4fbf0834e478482edcd67f",
      "new_mode": 33188,
      "new_path": "sky130/custom/sky130_fd_io/verilog/sky130_ef_io.v"
    }
  ]
}