Corrected the verilog for sky130_ef_io, which was not separating the
pad and core signals on the sky130_fd_io base power pads.
diff --git a/sky130/custom/sky130_fd_io/verilog/sky130_ef_io.v b/sky130/custom/sky130_fd_io/verilog/sky130_ef_io.v
index 57e2655..530a4cb 100644
--- a/sky130/custom/sky130_fd_io/verilog/sky130_ef_io.v
+++ b/sky130/custom/sky130_fd_io/verilog/sky130_ef_io.v
@@ -936,7 +936,7 @@
// sky130_ef_io__vssa_hvc_pad with HV clamp connections to VDDA and VSSA
module sky130_ef_io__vssa_hvc_clamped_pad (AMUXBUS_A, AMUXBUS_B,
- VSSA_PAD, VDDA, VSWITCH, VDDIO_Q, VCCHIB, VDDIO, VCCD,
+ VSSA, VSSA_PAD, VDDA, VSWITCH, VDDIO_Q, VCCHIB, VDDIO, VCCD,
VSSIO, VSSD, VSSIO_Q
);
inout AMUXBUS_A;
