###
###	Source file sky130.tech
###	Process this file with the preproc.py macro processor
###	Note that the tech name is always TECHNAME for
###	magic;  this keeps compatibility between layouts
###	for all process variants.
###
#------------------------------------------------------------------------
# Copyright (c) 2020 R. Timothy Edwards
# Revisions:  See below
#
# This file is an Open Source foundry process describing
# the SkyWater sky130 hybrid 0.18um / 0.13um fabrication
# process.  The file may be distributed under the terms
# of the Apache 2.0 license agreement.
#
#------------------------------------------------------------------------
tech
  format 35
  TECHNAME
end

version
 version REVISION
 description "SkyWater SKY130: Open Source rules and DRC"
 requires magic-8.3.111
end

#------------------------------------------------------------------------
# Status 7/10/20: Rev 1 (alpha):
# First public release
# Status 8/14/20: Rev 2 (alpha):
# Started updating with new device/model naming convention
# Status 1/3/21: Taking out of beta and declaring an official release.
#------------------------------------------------------------------------

#------------------------------------------------------------------------
# Supported device types
#------------------------------------------------------------------------
# device name			magic ID layer	description
#------------------------------------------------------------------------
# sky130_fd_pr__nfet_01v8	nfet		standard nFET
# sky130_fd_pr__nfet_01v8	scnfet		standard nFET in standard cell**
# sky130_fd_pr__special_nfet_latch npd		special nFET in SRAM cell
# sky130_fd_pr__special_nfet_pass  npass	special nFET in SRAM cell
# sky130_fd_pr__nfet_01v8_lvt	nfetlvt		low Vt nFET
# sky130_fd_bs_flash__special_sonosfet_star nsonos SONOS nFET
# sky130_fd_pr__pfet_01v8	pfet		standard pFET
# sky130_fd_pr__pfet_01v8	scpfet		standard pFET in standard cell**
# sky130_fd_pr__special_pfet_pass ppu		special pFET in SRAM cell
# sky130_fd_pr__pfet_01v8_lvt	pfetlvt		low Vt pFET
# sky130_fd_pr__pfet_01v8_mvt	pfetmvt		med Vt pFET
# sky130_fd_pr__pfet_01v8_hvt	pfethvt		high Vt pFET
# sky130_fd_pr__nfet_03v3_nvt	nnfet		native nFET
# sky130_fd_pr__pfet_g5v0d10v5	mvpfet		thickox pFET
# sky130_fd_pr__nfet_g5v0d10v5	mvnfet		thickox nFET
# sky130_fd_pr__nfet_01v8_nvt	mvnnfet		thickox native nFET
# sky130_fd_pr__diode_pw2nd_05v5 ndiode		n+ diff diode
# sky130_fd_pr__diode_pw2nd_05v5_lvt ndiodelvt	low Vt n+ diff diode
# sky130_fd_pr__diode_pw2nd_05v5_nvt nndiode	diode with nndiff
# sky130_fd_pr__diode_pw2nd_11v0 mvndiode	thickox n+ diff diode
# sky130_fd_pr__diode_pd2nw_05v5 pdiode		p+ diff diode
# sky130_fd_pr__diode_pd2nw_05v5_lvt pdiodelvt	low Vt p+ diff diode
# sky130_fd_pr__diode_pd2nw_05v5_hvt pdiodehvt	high Vt p+ diff diode
# sky130_fd_pr__diode_pd2nw_11v0 mvpdiode	thickox p+ diff diode
# sky130_fd_pr__npn_05v0	pbase		NPN in deep nwell
# sky130_fd_pr__npn_11v0	pbase		thick oxide gated NPN
# sky130_fd_pr__pnp_05v0	nbase		PNP
# sky130_fd_pr__cap_mim_m3_1	mimcap		MiM cap 1st plate
# sky130_fd_pr__cap_mim_m3_2	mimcap2		MiM cap 2nd plate
# sky130_fd_pr__res_generic_nd	rdn		n+ diff resistor
# sky130_fd_pr__res_generic_nd__hv mvrdn	thickox n+ diff resistor
# sky130_fd_pr__res_generic_pd	rdp		p+ diff resistor
# sky130_fd_pr__res_generic_pd__nv mvrdp	thickox p+ diff resistor
# sky130_fd_pr__res_generic_l1	rli		local interconnect resistor
# sky130_fd_pr__res_generic_po	npres		n+ poly resistor
# sky130_fd_pr__res_high_po_*	ppres (*)	p+ poly resistor (300 Ohms/sq)
# sky130_fd_pr__res_xhigh_po_*	xres (*)	p+ poly resistor (2k Ohms/sq)
# sky130_fd_pr__cap_var_lvt	varactor	low Vt varactor
# sky130_fd_pr__cap_var_hvt	varactorhvt	high Vt varactor
# sky130_fd_pr__cap_var		mvvaractor	thickox varactor
# sky130_fd_pr__res_iso_pw	rpw		pwell resistor (in deep nwell)
# sky130_fd_pr__esd_nfet_g5v0d10v5 mvnfetesd	ESD thickox nFET
# sky130_fd_pr__esd_pfet_g5v0d10v5 mvpfetesd	ESD thickox pFET
#
# (*) Note that ppres may extract into some generic type called
# "sky130_fd_pr__res_xhigh_po", but only specific sizes of xhrpoly are
# allowed, and these are created from fixed layouts like the types below.
#
# (**) nFET and pFET in standard cells are the same as devices
# outside of the standard cell except for the DRC rule for
# FET to diffusion contact spacing (which is 0.05um, not 0.055um)
#
#-------------------------------------------------------------
# The following devices are not extracted but are represented
# only by script-generated subcells in the PDK.
#-------------------------------------------------------------
# sky130_fd_pr__esd_nfet_01v8		ESD nFET
# sky130_fd_pr__esd_nfet_05v0_nvt	ESD native nFET
# sky130_fd_pr__special_nfet_pass_flash	flash nFET device
# sky130_fd_pr__esd_rf_diode_pw2nd_11v0	ESD n+ diode
# sky130_fd_pr__esd_rf_diode_pd2nw_11v0	ESD p+ diode
# sky130_fd_pr__cap_vpp_*		Vpp cap
# sky130_fd_pr__ind_*			inductor
# sky130_fd_pr__fuse_m4			metal fuse device
#--------------------------------------------------------------

#-----------------------------------------------------
# Tile planes
#-----------------------------------------------------

planes
  dwell,dw
  well,w
  active,a
  locali,li1,li
  metal1,m1
  metal2,m2
  metal3,m3
#ifdef METAL5
#ifdef MIM
  cap1,c1
#endif (MIM)
  metal4,m4
#ifdef MIM
  cap2,c2
#endif (MIM)
  metal5,m5
#endif (METAL5)
#ifdef REDISTRIBUTION
  metali,mi
#endif
  block,b
  comment,c
end

#-----------------------------------------------------
# Tile types
#-----------------------------------------------------

types
# Deep nwell
  dwell dnwell,dnw

# Wells
  well nwell,nw
  well pwell,pw
  well rpw,rpwell
 -well obswell
  well pbase,npn
  well nbase,pnp

# Transistors
  active nmos,ntransistor,nfet
 -active scnmos,scntransistor,scnfet
 -active npd,npdfet,sramnfet
 -active npass,npassfet,srampassfet
  active pmos,ptransistor,pfet
 -active scpmos,scptransistor,scpfet
 -active scpmoshvt,scpfethvt
 -active ppu,ppufet,srampfet
  active nnmos,nntransistor,nnfet
  active mvnmos,mvntransistor,mvnfet
  active mvpmos,mvptransistor,mvpfet
  active mvnnmos,mvnntransistor,mvnnfet
 -active mvnmosesd,mvntransistoresd,mvnfetesd
 -active mvpmosesd,mvptransistoresd,mvpfetesd
  active varactor,varact,var
  active mvvaractor,mvvaract,mvvar

  active pmoslvt,pfetlvt
  active pmosmvt,pfetmvt
  active pmoshvt,pfethvt
  active nmoslvt,nfetlvt
  active varactorhvt,varacthvt,varhvt
 -active nsonos,sonos
 -active sramnvar,corenvar,corenvaractor
 -active srampvar,corepvar,corepvaractor

# Diffusions
 -active fomfill
  active ndiff,ndiffusion,ndif
  active pdiff,pdiffusion,pdif
  active mvndiff,mvndiffusion,mvndif
  active mvpdiff,mvpdiffusion,mvpdif
  active ndiffc,ndcontact,ndc
  active pdiffc,pdcontact,pdc
  active mvndiffc,mvndcontact,mvndc
  active mvpdiffc,mvpdcontact,mvpdc
  active psubdiff,psubstratepdiff,ppdiff,ppd,psd,ptap
  active nsubdiff,nsubstratendiff,nndiff,nnd,nsd,ntap
  active mvpsubdiff,mvpsubstratepdiff,mvppdiff,mvppd,mvpsd,mvptap
  active mvnsubdiff,mvnsubstratendiff,mvnndiff,mvnnd,mvnsd,mvntap
  active psubdiffcont,psubstratepcontact,psc,ptapc
  active nsubdiffcont,nsubstratencontact,nsc,ntapc
  active mvpsubdiffcont,mvpsubstratepcontact,mvpsc,mvptapc
  active mvnsubdiffcont,mvnsubstratencontact,mvnsc,mvntapc
 -active obsactive
 -active mvobsactive

# Poly
  active poly,p,polysilicon
  active polycont,pc,pcontact,polycut,polyc
  active xpolycontact,xpolyc,xpc
 -active polyfill

# Resistors
  active npolyres,npres,mrp1
  active ppolyres,ppres,xhrpoly
  active xpolyres,xpres,xres,uhrpoly
  active ndiffres,rnd,rdn,rndiff
  active pdiffres,rpd,rdp,rpdiff
  active mvndiffres,mvrnd,mvrdn,mvrndiff
  active mvpdiffres,mvrpd,mvrdp,mvrpdiff
  active rmp

# Diodes
  active pdiode,pdi
  active ndiode,ndi
  active nndiode,nndi
  active pdiodec,pdic
  active ndiodec,ndic
  active nndiodec,nndic
  active mvpdiode,mvpdi
  active mvndiode,mvndi
  active mvpdiodec,mvpdic
  active mvndiodec,mvndic
  active pdiodelvt,pdilvt
  active pdiodehvt,pdihvt
  active ndiodelvt,ndilvt
  active pdiodelvtc,pdilvtc
  active pdiodehvtc,pdihvtc
  active ndiodelvtc,ndilvtc

# Local Interconnect 
  locali locali,li1,li
 -locali corelocali,coreli1,coreli
  locali rlocali,rli1,rli
  locali viali,vial,mcon,m1c,v0
 -locali obsli1,obsli
 -locali obsli1c,obsmcon
 -locali lifill

# Metal 1
  metal1 metal1,m1,met1
  metal1 rmetal1,rm1,rmet1
  metal1 via1,m2contact,m2cut,m2c,via,v,v1
 -metal1 obsm1
  metal1 padl
 -metal1 m1fill

# Metal 2
  metal2 metal2,m2,met2
  metal2 rmetal2,rm2,rmet2
  metal2 via2,m3contact,m3cut,m3c,v2
 -metal2 obsm2
 -metal2 m2fill

# Metal 3
  metal3 metal3,m3,met3
  metal3 rmetal3,rm3,rmet3
 -metal3 obsm3
#ifdef METAL5
  metal3 via3,v3
 -metal3 m3fill

#ifdef MIM
  cap1 mimcap,mim,capm
  cap1 mimcapcontact,mimcapc,mimcc,capmc
#endif

# Metal 4
  metal4 metal4,m4,met4
  metal4 rmetal4,rm4,rmet4
 -metal4 obsm4
  metal4 via4,v4
 -metal4 m4fill

#ifdef MIM
  cap2 mimcap2,mim2,capm2
  cap2 mimcap2contact,mimcap2c,mim2cc,capm2c
#endif

# Metal 5
  metal5 metal5,m5,met5
  metal5 rm5,rmetal5,rmet5
 -metal5 obsm5
 -metal5 m5fill
#endif (METAL5)

#ifdef REDISTRIBUTION
  metal5 mrdlcontact,mrdlc,pi1
  metali metalrdl,mrdl,metrdl,rdl
 -metali obsmrdl
  metali pi2
  block  ubm
#endif (REDISTRIBUTION)

# Miscellaneous
 -block  glass
 -block  fillblock,fillblock4
  comment comment
 -comment obscomment
# fixed resistor width identifiers
 -comment res0p35
 -comment res0p69
 -comment res1p41
 -comment res2p85
 -comment res5p73

end

#-----------------------------------------------------
# Magic contact types
#-----------------------------------------------------

contact
  pc       poly       locali
  ndc      ndiff      locali
  pdc      pdiff      locali
  nsc      nsd        locali
  psc      psd        locali
  ndic     ndiode     locali
  ndilvtc  ndiodelvt  locali
  nndic    nndiode    locali
  pdic     pdiode     locali
  pdilvtc  pdiodelvt  locali
  pdihvtc  pdiodehvt  locali
  xpc      xpc        locali

  mvndc   mvndiff   locali
  mvpdc   mvpdiff   locali
  mvnsc   mvnsd     locali
  mvpsc   mvpsd     locali
  mvndic  mvndiode  locali
  mvpdic  mvpdiode  locali

  mcon locali metal1
  obsmcon obsli metal1

  via1   metal1 metal2
  via2   metal2 metal3
#ifdef METAL5
  via3   metal3 metal4
  via4   metal4 metal5
#endif (METAL5)
  stackable

#ifdef METAL5
#ifdef MIM
  # MiM cap contacts are not stackable!
  mimcc  mimcap metal4
  mim2cc mimcap2 metal5
#endif (MIM)

  padl m1 m2 m3 m4 m5 glass
#else
  padl m1 m2 m3 glass
#endif  (!METAL5)

#ifdef REDISTRIBUTION
  mrdlc metal5 mrdl
  pi2   mrdl ubm
#endif (REDISTRIBUTION)
end

#-----------------------------------------------------
# Layer aliases
#-----------------------------------------------------

aliases

  allwellplane     nwell
  allnwell	   nwell,obswell,pnp

  allnfets	   nfet,npass,npd,scnfet,mvnfet,mvnfetesd,mvnnfet,nnfet,nfetlvt,nsonos
  allpfets	   pfet,ppu,scpfet,scpfethvt,mvpfet,mvpfetesd,pfethvt,pfetlvt,pfetmvt
  allfets	   allnfets,allpfets,varactor,mvvaractor,varhvt,corenvar,corepvar
  allfetsstd	   nfet,mvnfet,mvnfetesd,mvnnfet,nnfet,nfetlvt,pfet,mvpfet,mvpfetesd,pfethvt,pfetlvt,pfetmvt
  allfetsspecial   scnfet,scpfet,scpfethvt
  allfetscore	   npass,npd,nsonos,ppu,corenvar,corepvar
  allfetsnolvt	   nfet,npass,npd,scnfet,mvnfet,mvnfetesd,mvnnfet,nnfet,nsonos,pfet,ppu,scpfet,scpfethvt,mvpfet,mvpfetesd,pfethvt,pfetmvt,varactor,mvvaractor,varhvt,corenvar

  allnactivenonfet *ndiff,*nsd,*ndiode,*nndiode,*mvndiff,*mvnsd,*mvndiode,*ndiodelvt
  allnactive	   allnactivenonfet,allnfets
  allnactivenontap *ndiff,*ndiode,*nndiode,*mvndiff,*mvndiode,*ndiodelvt,allnfets
  allnactivetap	   *nsd,*mvnsd,var,varhvt,mvvar,corenvar

  allpactivenonfet *pdiff,*psd,*pdiode,*mvpdiff,*mvpsd,*mvpdiode,*pdiodelvt,*pdiodehvt
  allpactive	   allpactivenonfet,allpfets
  allpactivenontap *pdiff,*pdiode,*mvpdiff,*mvpdiode,*pdiodelvt,*pdiodehvt,allpfets
  allpactivetap    *psd,*mvpsd,corepvar

  allactivenonfet  allnactivenonfet,allpactivenonfet
  allactive	   allactivenonfet,allfets

  allactiveres	   ndiffres,pdiffres,mvndiffres,mvpdiffres

  allndifflv       *ndif,*nsd,*ndiode,ndiffres,nfet,npass,npd,scnfet,nfetlvt,nsonos
  allpdifflv       *pdif,*psd,*pdiode,pdiffres,pfet,ppu,scpfet,scpfethvt,pfetlvt,pfetmvt,pfethvt
  alldifflv        allndifflv,allpdifflv
  allndifflvnonfet *ndif,*nsd,*ndiode,*nndiode,ndiffres,*ndiodelvt
  allpdifflvnonfet *pdif,*psd,*pdiode,pdiffres,*pdiodelvt,*pdiodehvt
  alldifflvnonfet  allndifflvnonfet,allpdifflvnonfet

  allndiffmv       *mvndif,*mvnsd,*mvndiode,*nndiode,mvndiffres,mvnfet,mvnfetesd,mvnnfet,nnfet
  allpdiffmv       *mvpdif,*mvpsd,*mvpdiode,mvpdiffres,mvpfet,mvpfetesd
  alldiffmv        allndiffmv,allpdiffmv
  allndiffmvnontap *mvndif,*mvndiode,*nndiode,mvndiffres,mvnfet,mvnfetesd,mvnnfet,nnfet
  allpdiffmvnontap *mvpdif,*mvpdiode,mvpdiffres,mvpfet,mvpfetesd
  alldiffmvnontap  allndiffmvnontap,allpdiffmvnontap
  allndiffmvnonfet *mvndif,*mvnsd,*mvndiode,*nndiode,mvndiffres
  allpdiffmvnonfet *mvpdif,*mvpsd,*mvpdiode,mvpdiffres
  alldiffmvnonfet  allndiffmvnonfet,allpdiffmvnonfet

  alldiffnonfet	   alldifflvnonfet,alldiffmvnonfet
  alldiff	   alldifflv,alldiffmv,fomfill

  allpolyres	   mrp1,xhrpoly,uhrpoly,rmp
  allpolynonfet	   *poly,allpolyres,xpc
  allpolynonres	   *poly,allfets,xpc

  allpoly	   allpolynonfet,allfets
  allpolynoncap	   *poly,xpc,allfets,allpolyres

  allndiffcontlv   ndc,nsc,ndic,nndic,ndilvtc
  allpdiffcontlv   pdc,psc,pdic,pdilvtc,pdihvtc
  allndiffcontmv   mvndc,mvnsc,mvndic
  allpdiffcontmv   mvpdc,mvpsc,mvpdic
  allndiffcont	   allndiffcontlv,allndiffcontmv
  allpdiffcont	   allpdiffcontlv,allpdiffcontmv
  alldiffcontlv	   allndiffcontlv,allpdiffcontlv
  alldiffcontmv	   allndiffcontmv,allpdiffcontmv
  alldiffcont	   alldiffcontlv,alldiffcontmv

  allcont	alldiffcont,pc

  allres	allpolyres,allactiveres

  allli		*locali,coreli,rli
  allm1		*m1,rm1
  allm2		*m2,rm2
  allm3		*m3,rm3
#ifdef METAL5
  allm4	   	*m4,rm4
  allm5	   	*m5,rm5
#endif (METAL5)

  allpad	padl

  psub		pwell
  
end

#-----------------------------------------------------
# Layer drawing styles
#-----------------------------------------------------

styles
 styletype mos
  dnwell    cwell
  nwell     nwell
  pwell	    pwell
  rpwell    pwell 	ptransistor_stripes
  ndiff     ndiffusion
  fomfill   ndiffusion
  pdiff     pdiffusion
  nsd       ndiff_in_nwell
  psd       pdiff_in_pwell
  nfet      ntransistor    ntransistor_stripes
  scnfet    ntransistor    ntransistor_stripes
  npass	    ntransistor	   ntransistor_stripes
  npd	    ntransistor	   ntransistor_stripes
  pfet      ptransistor    ptransistor_stripes
  scpfet    ptransistor    ptransistor_stripes
  scpfethvt ptransistor    ptransistor_stripes implant2
  ppu	    ptransistor	   ptransistor_stripes
  var       polysilicon    ndiff_in_nwell
  ndc       ndiffusion     metal1  contact_X'es
  pdc       pdiffusion     metal1  contact_X'es
  nsc       ndiff_in_nwell metal1  contact_X'es
  psc       pdiff_in_pwell metal1  contact_X'es
  corenvar  polysilicon    ndiff_in_nwell
  corepvar  polysilicon    pdiff_in_pwell

  pnp	    nwell ntransistor_stripes
  npn	    pwell ptransistor_stripes

  pfetlvt   ptransistor	ptransistor_stripes implant1
  pfetmvt   ptransistor	ptransistor_stripes implant3
  pfethvt   ptransistor ptransistor_stripes implant2
  nfetlvt   ntransistor ntransistor_stripes implant1
  nsonos    ntransistor implant3
  varhvt    polysilicon ndiff_in_nwell implant2
  nnfet	    ntransistor ndiff_in_nwell

  mvndiff   ndiffusion     hvndiff_mask
  mvpdiff   pdiffusion     hvpdiff_mask
  mvnsd     ndiff_in_nwell hvndiff_mask
  mvpsd     pdiff_in_pwell hvpdiff_mask
  mvnfet    ntransistor    ntransistor_stripes hvndiff_mask
  mvnfetesd ntransistor    ntransistor_stripes hvndiff_mask
  mvnnfet   ntransistor    ndiff_in_nwell hvndiff_mask
  mvpfet    ptransistor    ptransistor_stripes
  mvpfetesd ptransistor    ptransistor_stripes
  mvvar     polysilicon    ndiff_in_nwell hvndiff_mask
  mvndc     ndiffusion     metal1  contact_X'es hvndiff_mask
  mvpdc     pdiffusion     metal1  contact_X'es hvpdiff_mask
  mvnsc     ndiff_in_nwell metal1  contact_X'es hvndiff_mask
  mvpsc     pdiff_in_pwell metal1  contact_X'es hvpdiff_mask

  poly      polysilicon 
  polyfill  polysilicon
  pc        polysilicon    metal1  contact_X'es
  npolyres  polysilicon    silicide_block nselect2
  ppolyres  polysilicon    silicide_block pselect2
  xpc	    polysilicon	   pselect2  metal1  contact_X'es
  rmp	    polysilicon	   poly_resist_stripes

  res0p35   implant1
  res0p69   implant1
  res1p41   implant1
  res2p85   implant1
  res5p73   implant1

  pdiode    pdiffusion     pselect2
  ndiode    ndiffusion     nselect2
  pdiodec   pdiffusion     pselect2 metal1 contact_X'es
  ndiodec   ndiffusion     nselect2 metal1 contact_X'es

  nndiode   ndiffusion  nselect2 implant3
  ndiodelvt ndiffusion	nselect2 implant1
  pdiodelvt pdiffusion  pselect2 implant1
  pdiodehvt pdiffusion  pselect2 implant2
  pdilvtc   pdiffusion  pselect2 implant1 metal1 contact_X'es
  pdihvtc   pdiffusion  pselect2 implant2 metal1 contact_X'es
  ndilvtc   ndiffusion  nselect2 implant1 metal1 contact_X'es

  mvpdiode    pdiffusion     pselect2 hvpdiff_mask
  mvndiode    ndiffusion     nselect2 hvndiff_mask
  mvpdiodec   pdiffusion     pselect2 metal1 contact_X'es hvpdiff_mask
  mvndiodec   ndiffusion     nselect2 metal1 contact_X'es hvndiff_mask
  nndiodec    ndiff_in_nwell nselect2 metal1 contact_X'es hvndiff_mask

  locali    metal1
  lifill    metal1
  coreli    metal1
  rli       metal1         poly_resist_stripes
  mcon	    metal1	   metal2 via1arrow
  obsli     metal1
  obsmcon   metal1	   metal2 via1arrow

  metal1    metal2
  m1fill    metal2
  rm1       metal2         poly_resist_stripes
  obsm1     metal2
  m2c       metal2         metal3  via2arrow
  metal2    metal3
  m2fill    metal3
  rm2       metal3         poly_resist_stripes
  obsm2     metal3
  m3c       metal3         metal4  via3alt
  metal3    metal4
  m3fill    metal4
  rm3       metal4         poly_resist_stripes
  obsm3     metal4
#ifdef METAL5
#ifdef MIM
  mimcap    metal3         mems
  mimcc     metal3         contact_X'es mems
  mimcap2   metal4         mems
  mim2cc    metal4         contact_X'es mems
#endif (MIM)
  via3      metal4         metal5  via4
  metal4    metal5
  m4fill    metal5
  rm4       metal5         poly_resist_stripes
  obsm4     metal5
  via4      metal5         metal6  via5
  metal5    metal6
  m5fill    metal6
  rm5       metal6         poly_resist_stripes
  obsm5     metal6
#endif (METAL5)
#ifdef REDISTRIBUTION
  mrdlc	    metal6  metal7  via6
  metalrdl  metal7
  obsmrdl   metal7
  ubm	    metal8
  pi2	    metal7  metal8  via7
#endif (REDISTRIBUTION)

  glass	    overglass
  mrp1      poly_resist    poly_resist_stripes
  xhrpoly   poly_resist    silicide_block
  uhrpoly   poly_resist
  ndiffres  ndiffusion	   ndop_stripes
  pdiffres  pdiffusion	   pdop_stripes
  mvndiffres  ndiffusion hvndiff_mask   ndop_stripes
  mvpdiffres  pdiffusion hvpdiff_mask   pdop_stripes
  comment   comment
  error_p   error_waffle
  error_s   error_waffle
  error_ps  error_waffle
  fillblock cwell
  fillblock4 cwell

  obswell   cwell
  obsactive implant4

#ifndef METAL5
  padl      metal4 via4 overglass
#else
  padl      metal6 via6 overglass
#endif

  magnet    substrate_field_implant
  rotate    via3alt
  fence     via5
end

#-----------------------------------------------------
# Special paint/erase rules
#-----------------------------------------------------

compose
  compose  nfet  poly  ndiff
  compose  pfet  poly  pdiff
  compose  var   poly  nsd

  compose  mvnfet  poly  mvndiff
  compose  mvpfet  poly  mvpdiff
  compose  mvvar   poly  mvnsd

  paint	 obsmcon locali	 via1
  paint	 obsmcon obsm1	 obsli,obsm1
  
  paint  ndc     nwell  pdc
  paint  nfet    nwell  pfet
  paint  scnfet  nwell  scpfet
  paint  ndiff   nwell  pdiff
  paint  psd     nwell  nsd
  paint  psc     nwell  nsc
  paint  npd     nwell  ppu

  paint  pdc     pwell  ndc
  paint  pfet    pwell  nfet
  paint  scpfet  pwell  scnfet
  paint  pdiff   pwell  ndiff
  paint  nsd     pwell  psd
  paint  nsc     pwell  psc
  paint  ppu     pwell  npd

  paint  pdc	 coreli pdc
  paint  ndc	 coreli ndc
  paint  pc	 coreli pc
  paint  nsc 	 coreli nsc
  paint  psc 	 coreli psc
  paint  viali 	 coreli viali

  paint  coreli  pdc    pdc
  paint  coreli  ndc    ndc
  paint  coreli  pc     pc
  paint  coreli  nsc    nsc
  paint  coreli  psc    psc
  paint  coreli  viali  viali

#ifdef METAL5
  paint  m4      obsm4  m4
  paint  m5      obsm5  m5
#endif (METAL5)
end

#-----------------------------------------------------
# Electrical connectivity
#-----------------------------------------------------

connect
  *nwell,*nsd,*mvnsd,dnwell,pnp *nwell,*nsd,*mvnsd,dnwell,pnp
  pwell,*psd,*mvpsd,npn  pwell,*psd,*mvpsd,npn
  *li,coreli,lifill	*li,coreli,lifill
  *m1,m1fill,obsmcon	*m1,m1fill,obsmcon
  *m2,m2fill	*m2,m2fill
  *m3,m3fill	*m3,m3fill
#ifdef METAL5
  *m4,m4fill	*m4,m4fill
  *m5,m5fill	*m5,m5fill
#ifdef MIM
  *mimcap     *mimcap
  *mimcap2    *mimcap2
#endif (MIM)
#endif (METAL5)
   allnactivenonfet	allnactivenonfet
   allpactivenonfet	allpactivenonfet
  *poly,xpc,allfets,polyfill	*poly,xpc,allfets,polyfill
#ifdef REDISTRIBUTION
  # RDL connects to m5 (i.e., padl) through glass cut
  *mrdl			*mrdl
  glass			metrdl
#endif (REDISTRIBUTION)
end

#-----------------------------------------------------
# CIF/GDS output layer definitions
#-----------------------------------------------------
# NOTE:  All values in this section MUST be multiples of 25 
# or else magic will scale below the allowed layout grid size

cifoutput

#----------------------------------------------------------------
style gdsii
# NOTE: This section is used for actual GDS output
#----------------------------------------------------------------
 scalefactor 10  nanometers
 options calma-permissive-labels
 gridlimit 5

#----------------------------------------------------------------
# Create a temp layer from the cell bounding box for use in
# generating ID layers.  Note that "boundary", unlike "bbox",
# requires the FIXED_BBOX property (abutment box) in the cell.
#----------------------------------------------------------------
 templayer CELLBOUND
	boundary

#----------------------------------------------------------------
# BOUND
#----------------------------------------------------------------
 layer 	BOUND CELLBOUND
	calma 235 4

#----------------------------------------------------------------
# DNWELL
#----------------------------------------------------------------

 layer DNWELL	dnwell,pnp
	calma	64 18

 layer PWRES    rpw
	and	dnwell
	calma	64 13

#----------------------------------------------------------------
# NWELL
#----------------------------------------------------------------

 layer NWELL 	allnwell
	bloat-all rpw dnwell
	and-not rpw,pwell
 	calma 	64 20

 layer WELLTXT
 	labels allnwell noport
	calma 64 5

 layer WELLPIN
 	labels allnwell port
	calma 64 16

#----------------------------------------------------------------
# SUB (text/port only)
#----------------------------------------------------------------

 layer SUBTXT
 	labels pwell noport
	calma 64 59

 layer SUBPIN
 	labels pwell port
	calma 122 16

#----------------------------------------------------------------
# DIFF
#----------------------------------------------------------------

 layer DIFF 	allnactivenontap,allpactivenontap,allactiveres
 	calma 	65 20

 layer DIFFTXT
 	labels allnactivenontap,allpactivenontap noport
	calma	65 6

 layer DIFFPIN
 	labels allnactivenontap,allpactivenontap port
	calma	65 16

#----------------------------------------------------------------
# TAP
#----------------------------------------------------------------

 layer TAP 	allnactivetap,allpactivetap
 	labels 	allnactivetap,allpactivetap port
 	calma 	65 44

 layer TAPTXT
 	labels 	allnactivetap,allpactivetap noport
	calma	65 5

#----------------------------------------------------------------
# FOM
#----------------------------------------------------------------

 layer FOMFILL	fomfill
	labels	fomfill
	calma	23 28

#----------------------------------------------------------------
# PSDM, NSDM (PPLUS, NPLUS implants)
#----------------------------------------------------------------

 templayer basePSDM pdiffres,mvpdiffres
	grow	15
	or	xhrpoly,uhrpoly,xpc
	grow	110
	bloat-or allpactivetap * 125 allnactivenontap 0
	bloat-or allpactivenontap * 125 allnactivetap 0

 templayer baseNSDM ndiffres,mvndiffres
 	grow	125
	bloat-or allnactivetap * 125 allpactivenontap 0
	bloat-or allnactivenontap * 125 allpactivetap 0

 templayer extendPSDM  basePSDM
	bridge	380 380
	and-not baseNSDM

 layer PSDM basePSDM,extendPSDM 
	grow	185
	shrink	185
	close   265000
	mask-hints PSDM
	calma	94 20

 templayer extendNSDM  baseNSDM
	bridge	380 380
	and-not basePSDM

 layer NSDM baseNSDM,extendNSDM
	grow	185
	shrink	185
 	close   265000
	mask-hints NSDM
 	calma	93 44

#----------------------------------------------------------------
# LVID
#----------------------------------------------------------------

 layer LVID  nnfet
        grow 100
	calma 81 60

#----------------------------------------------------------------
# LVTN
#----------------------------------------------------------------

 layer LVTN  pfetlvt,nfetlvt,mvvar,mvnnfet,nnfet,nsonos,*pdiodelvt,*ndiodelvt,*nndiode
        grow 180
	bridge	380 380
	grow	185
	shrink	185
	close  265000
	mask-hints LVTN
	calma 125 44

#----------------------------------------------------------------
# HVTR
#----------------------------------------------------------------

 layer HVTR  pfetmvt
        grow 180
	bridge	380 380
	grow	185
	shrink	185
	close  265000
	calma 18 20

#----------------------------------------------------------------
# HVTP
#----------------------------------------------------------------

 layer HVTP scpfethvt,ppu,pfethvt,varhvt,*pdiodehvt
        grow 180
	bridge	380 380
	grow	185
	shrink	185
	close 265000
	mask-hints HVTP
	calma 78 44

#----------------------------------------------------------------
# SONOS
#----------------------------------------------------------------

 layer SONOS nsonos
	grow 100
	grow-min 410
	bridge 500 410
	grow 250
	shrink 250
	calma 80 20

#----------------------------------------------------------------
# SONOS requires COREID around area (areaid.ce).  Also, the
# coreli layer indicates a cell needing COREID.  Also, devices
# npd, npass, and ppu indicate a COREID cell.
#----------------------------------------------------------------

 layer COREID
	bloat-all nsonos,coreli,ppu,npd,npass,corepvar,corenvar CELLBOUND
	mask-hints COREID
	calma 81 2

#----------------------------------------------------------------
# STDCELL applies to all cells containing scnfet or scpfet.
#----------------------------------------------------------------

 layer STDCELL scnfet
	bloat-all scpfet,scpfethvt,scnfet CELLBOUND
	mask-hints STDCELL
	calma 81 4

#----------------------------------------------------------------
# ESDID is a marker layer for ESD devices in the padframe I/O.
#----------------------------------------------------------------

 layer ESDID  
	bloat-all mvnfetesd *mvndiff,*poly
	bloat-all mvpfetesd *mvpdiff,*poly
	grow 100
	mask-hints ESDID
	calma 81 19

#----------------------------------------------------------------
# NPNID and PNPID apply to bipolar transistors
#----------------------------------------------------------------

 layer NPNID
	bloat-all npn dnwell
	mask-hints NPNID
	calma	82 20

 templayer pnparea pnp
	grow 400

 layer PNPID
	bloat-all pnparea *psd
	or pnparea
	mask-hints PNPID
	calma	82 44

#----------------------------------------------------------------
# RPM
#----------------------------------------------------------------

 layer RPM
	bloat-all xhrpoly xpc
	grow 200
	grow-min 1270
	grow 420
	shrink 420
	calma 86 20

#----------------------------------------------------------------
# URPM (2kOhms/sq. poly implant)
#----------------------------------------------------------------

 layer URPM
	bloat-all uhrpoly xpc
	grow 200
	grow-min 1270
	grow 420
	shrink 420
	calma 79 20

#----------------------------------------------------------------
# LDNTM (Tip implant for SONOS FETs)
#----------------------------------------------------------------

 layer LDNTM
	bloat-all nsonos *ndiff
	grow 185
 	grow 	345
 	shrink 	345
	calma 11 44

#----------------------------------------------------------------
# HVNTM (Tip implant for MV ndiff devices)
#----------------------------------------------------------------

 templayer hvntm_block *mvpsd
	grow 185

 layer HVNTM
	bloat-all mvnfet,mvnfetesd,mvnnfet,nnfet,*mvndiode,mvrdn,*nndiode *mvndiff
	bloat-all mvvaractor *mvnsd
	and-not hvntm_block
        grow 185
 	grow 	345
 	shrink 	345
	and-not hvntm_block
	calma 125 20

#----------------------------------------------------------------
# POLY
#----------------------------------------------------------------

 layer POLY 	allpoly
 	calma 	66 20

 layer POLYTXT
	labels  allpoly noport
	calma	66 5

 layer POLYPIN
	labels  allpoly port
	calma	66 16

 layer POLYFILL	polyfill
	labels 	polyfill
	calma	28 28

#----------------------------------------------------------------
# HVI (includes rules NWELL 8-11 and DIFFTAP 14-26)
#----------------------------------------------------------------

 templayer thkox_area 	alldiffmv,mvvar
	grow	185
	bloat-all alldiffmv nwell
	grow 345
	shrink 345

 templayer large_ptap_mv thkox_area
	shrink	420
	grow	420

 templayer small_ptap_mv thkox_area
	and-not large_ptap_mv
	# (HVI min width rule is 0.6 but CNTM min width rule is 0.84um)
	grow-min 840

 layer HVI 	thkox_area,small_ptap_mv
	bridge	700 600
 	grow 	345
 	shrink 	345
	mask-hints HVI
 	calma 	75 20

#----------------------------------------------------------------
# CONT (LICON)
#----------------------------------------------------------------

 layer CONT allcont
 	squares-grid 0 170 170
 	calma	66 44

 # Contact for pres is different than other LICON contacts
 # See rules LICON 1b, 1c (width/length) and 2b (spacing)
 templayer xpc_horiz xpc
	shrink 1007
	grow 1007

 layer CONT xpc
	and-not xpc_horiz
	# Force long edge vertical for contacts narrower than 2um
	# Minimum space is 350 but 520 satisfies no. of contacts rule
 	slots 80 190 520 80 2000 350
 	calma	66 44

 layer CONT xpc
	and xpc_horiz
	# Force long edge vertical for contacts wider than 2um
	# Minimum space is 350 but 520 satisfies no. of contacts rule
 	slots 80 2000 350 80 190 520
 	calma	66 44

#----------------------------------------------------------------
# NPC (Nitride poly cut)
# surrounds CONT (LICON) on poly only (i.e., pc)
#----------------------------------------------------------------

 # Avoids a common case of NPC bridges too close to other LICON shapes.
 templayer diffcutarea pdc,ndc,psc,nsc,mvpdc,mvndc,mvpsc,mvnsc
	grow 90

 layer NPC pc
 	squares-grid 0 170 170
	grow 100
	bridge 270 270
	and-not diffcutarea
	bridge 270 270
	grow 130
	shrink 130
	mask-hints NPC
	calma  95 20

 # NPC is also generated on xhrpoly and uhrpoly resistors

 layer NPC xpc,xhrpoly,uhrpoly
        # xpc surrounds precision_resistor by 0.095um
	grow 95
	grow 130
	shrink 130
	calma  95 20

#----------------------------------------------------------------
# Device markers
#----------------------------------------------------------------

 layer DIFFRES rdn,mvrdn,rdp,mvrdp
	calma 65 13

 layer POLYRES mrp1
	calma 66 13

 # POLYSHORT is a poly layer resistor like rli, rm1, etc., for metal layers
 layer POLYSHORT rmp
	calma 66 15

 # POLYRES extends to edge of contact cut
 layer POLYRES xhrpoly,uhrpoly
	grow 60
	and xpc
	or xhrpoly,uhrpoly
	calma 66 13

 layer DIODE *pdi,*ndi,*nndi,*mvpdi,*mvndi,*pdilvt,*pdihvt,*ndilvt
        # To be done:  Expand to include anode, cathode, and guard ring
	calma 81 23

#----------------------------------------------------------------
# LI
#----------------------------------------------------------------
 layer LI allli
	calma 67 20

 layer LITXT
 	labels *locali,coreli noport
	calma 67 5

 layer LIPIN
 	labels *locali,coreli port
	calma 67 16

 layer LIRES rli
	labels rli
	calma 67 13

 layer LIFILL	lifill
	labels 	lifill
	calma	56 28

#----------------------------------------------------------------
# MCON
#----------------------------------------------------------------
 layer MCON mcon
 	squares-grid 0 170 190
 	calma 	67 44

#----------------------------------------------------------------
# MET1
#----------------------------------------------------------------
 layer MET1 	allm1
 	calma 	68 20

 layer MET1TXT
	labels	allm1 noport
	calma 	68 5

 layer MET1PIN
	labels	allm1 port
	calma 	68 16

 layer MET1RES rm1
	labels rm1
	calma 68 13

 layer MET1FILL m1fill
	labels m1fill
	calma 36 28

#----------------------------------------------------------------
# VIA1
#----------------------------------------------------------------
 layer VIA1 	via1
 	squares-grid 55 150 170
 	calma 	68 44

#----------------------------------------------------------------
# MET2
#----------------------------------------------------------------
 layer MET2 	allm2
 	calma 	69 20

 layer MET2TXT
	labels	allm2 noport
	calma	69 5

 layer MET2PIN
	labels	allm2 port
	calma	69 16

 layer MET2RES rm2
	labels rm2
	calma 69 13

 layer MET2FILL m2fill
	labels m2fill
	calma 41 28

#----------------------------------------------------------------
# VIA2
#----------------------------------------------------------------
 layer VIA2 	via2
 	squares-grid 40 200 200
 	calma 	69 44

#----------------------------------------------------------------
# MET3
#----------------------------------------------------------------
 layer MET3 	allm3
 	calma 	70 20

 layer MET3TXT
 	labels 	allm3 noport
	calma	70 5

 layer MET3PIN
	labels	allm3 port
	calma	70 16 

 layer MET3RES rm3
	labels rm3
	calma 70 13

 layer MET3FILL m3fill
	labels m3fill
	calma 34 28

#ifdef METAL5
#----------------------------------------------------------------
# VIA3
#----------------------------------------------------------------
 layer VIA3	via3
#ifdef MIM
	or mimcc
#endif (MIM)
 	squares-grid 60 200 200
 	calma 	70 44

#----------------------------------------------------------------
# MET4
#----------------------------------------------------------------
 layer MET4 	allm4
 	calma 	71 20

 layer MET4TXT
	labels	allm4 noport
	calma	71 5

 layer MET4PIN
	labels	allm4 port
	calma	71 16

 layer MET4RES rm4
	labels rm4
	calma 71 13

 layer MET4FILL m4fill
	labels m4fill
	calma 51 28

#----------------------------------------------------------------
# VIA4
#----------------------------------------------------------------
 layer VIA4	via4
#ifdef MIM
	or mim2cc
#endif (MIM)
 	squares-grid 190 800 800
 	calma 	71 44

#----------------------------------------------------------------
# MET5
#----------------------------------------------------------------
 layer MET5 	allm5,m5fill
 	calma 	72 20

 layer MET5TXT
	labels	allm5 noport
	calma	72 5

 layer MET5PIN
	labels	allm5 port
	calma	72 16

 layer MET5RES rm5
	labels rm5
	calma 72 13

 layer MET5FILL m5fill
	labels m5fill
	calma 59 28

#endif (METAL5)

#ifdef REDISTRIBUTION
#----------------------------------------------------------------
# RDL
#----------------------------------------------------------------
  layer RDL	*metrdl
	calma   74 20

  layer RDLTXT
	labels	*metrdl noport
	calma	74 5

  layer RDLPIN
	labels  *metrdl port
	calma	74 16

  layer PI1	*metrdl
	and	padl,glass
	# Test only---needs GDS layer number

  layer	UBM	*metrdl
	shrink	50000
	grow	40000
	# Test only---needs GDS layer number
	
  layer	PI2	*metrdl
	shrink	50000
	grow	25000
	# Test only---needs GDS layer number

#endif REDISTRIBUTION

#----------------------------------------------------------------
# GLASS
#----------------------------------------------------------------
 layer GLASS 	glass
 	calma 	76 20

#ifdef MIM
#----------------------------------------------------------------
# CAPM
#----------------------------------------------------------------
 layer CAPM 	*mimcap
 	labels 	mimcap
 	calma 	89 44

 layer CAPM2 	*mimcap2
 	labels 	mimcap2
 	calma 	97 44
#endif (MIM)

#----------------------------------------------------------------
# Chip top level marker for DRC latchup rules to check 15um
# distance to taps (otherwise 6um is used)
#----------------------------------------------------------------

 layer LOWTAPDENSITY
	bbox top
	# Clear 200um for pads + 50um for required high tap density
	# in critical area.
	shrink 250000
	calma	81 14

#----------------------------------------------------------------
# FILLBLOCK
#----------------------------------------------------------------
 layer FILLOBSFOM  obsactive
	calma	22 24

 layer FILLOBSM1 fillblock,fillblock4
 	calma 	62 24

 layer FILLOBSM2 fillblock,fillblock4
 	calma 	105 52

 layer FILLOBSM3 fillblock,fillblock4
 	calma 	107 24

 layer FILLOBSM4 fillblock,fillblock4
 	calma 	112 4

 render	DNWELL 	cwell       -0.1    0.1
 render	NWELL	nwell        0.0    0.2062
 render DIFF	ndiffusion   0.2062 0.12
 render TAP	pdiffusion   0.2062 0.12
 render POLY	polysilicon  0.3262 0.18
 render CONT	via          0.5062 0.43
 render LI	metal1       0.9361 0.10
 render MCON	via          1.0361 0.34
 render MET1	metal2       1.3761 0.36
 render VIA1	via          1.7361 0.27
 render MET2	metal3       2.0061 0.36
 render VIA2	via          2.3661 0.42
 render MET3	metal4       2.7861 0.845
#ifdef METAL5
 render VIA3	via          3.6311 0.39
 render MET4	metal5       4.0211 0.845
 render VIA4	via          4.8661 0.505
 render MET5	metal6       5.3711 1.26
 render CAPM	metal8       2.4661 0.2
 render CAPM2	metal9       3.7311 0.2
#ifdef REDISTRIBUTION
 render RDL	metal7      11.8834 4.0
#endif (!REDISTRIBUTION)
#endif (!METAL5)

#----------------------------------------------------------------
style drc
#----------------------------------------------------------------
# NOTE:  This style is used for DRC only, not for GDS output
#----------------------------------------------------------------
 scalefactor 10  nanometers
 options calma-permissive-labels

 # Ensure nwell overlaps dnwell at least 0.4um outside and 1.03um inside
 templayer dnwell_shrink dnwell
 shrink 1030

 templayer nwell_missing dnwell
 grow 400
 and-not dnwell_shrink
 and-not nwell

 templayer pwell_in_dnwell dnwell
 and-not nwell

 # SONOS nFET devices must be in deep nwell
 templayer dnwell_missing nsonos
 and-not dnwell

 # SONOS nFET devices must be in cell with abutment box
 templayer abutment_box
	boundary

 templayer bbox_missing nsonos
	and-not abutment_box

 # Make sure nwell covers varactor poly
 templayer var_poly_no_nwell
	bloat-all varactor,mvvaractor *poly
	grow 150
	and-not nwell

 # Define MiM cap bottom plate for spacing rule
 templayer mim_bottom
 bloat-all *mimcap *metal3

 # Define MiM2 cap bottom plate for spacing rule
 templayer mim2_bottom
 bloat-all *mimcap2 *metal4

 # Note that metal fill is performed by the foundry and so is not
 # an option for a cifoutput style.

 # Check latchup rule (15um minimum from tap LICON center to any
 # non-tap diffusion.  Note that to count as a tap, the diffusion
 # must be contacted to LI

 templayer ptap_reach psc,mvpsc
 and-not dnwell
 # grow total is 15um.  grow in 0.84um increments to ensure that
 # no nwell ring is crossed
 grow 840
 and-not nwell,dnwell
 grow 840
 and-not nwell,dnwell
 grow 840
 and-not nwell,dnwell
 grow 840
 and-not nwell,dnwell
 grow 840
 and-not nwell,dnwell
 grow 840
 and-not nwell,dnwell
 grow 840
 and-not nwell,dnwell
 grow 840
 and-not nwell,dnwell
 grow 840
 and-not nwell,dnwell
 grow 840
 and-not nwell,dnwell
 grow 840
 and-not nwell,dnwell
 grow 840
 and-not nwell,dnwell
 grow 840
 and-not nwell,dnwell
 grow 840
 and-not nwell,dnwell
 grow 840
 and-not nwell,dnwell
 grow 840
 and-not nwell,dnwell
 grow 840
 and-not nwell,dnwell
 grow 635
 and-not nwell,dnwell

 templayer ptap_missing *ndiff,*mvndiff
 and-not dnwell
 and-not ptap_reach

 templayer ntap_reach nsc,mvnsc
 # grow total is 15um.  grow in 1.27um increments to ensure that
 # no nwell ring is crossed.  There is no difference between
 # ntaps in and out of deep nwell.
 grow 1270
 and nwell,pnp
 grow 1270
 and nwell,pnp
 grow 1270
 and nwell,pnp
 grow 1270
 and nwell,pnp
 grow 1270
 and nwell,pnp
 grow 1270
 and nwell,pnp
 grow 1270
 and nwell,pnp
 grow 1270
 and nwell,pnp
 grow 1270
 and nwell,pnp
 grow 1270
 and nwell,pnp
 grow 1270
 and nwell,pnp
 grow 945
 and nwell,pnp
 
 templayer ntap_missing *pdiff,*mvpdiff
 and-not pwell_in_dnwell
 and-not ntap_reach

 templayer dptap_reach psc,mvpsc
 and dnwell
 grow 840
 and-not nwell
 and dnwell
 grow 840
 and-not nwell
 and dnwell
 grow 840
 and-not nwell
 and dnwell
 grow 840
 and-not nwell
 and dnwell
 grow 840
 and-not nwell
 and dnwell
 grow 840
 and-not nwell
 and dnwell
 grow 840
 and-not nwell
 and dnwell
 grow 840
 and-not nwell
 and dnwell
 grow 840
 and-not nwell
 and dnwell
 grow 840
 and-not nwell
 and dnwell
 grow 840
 and-not nwell
 and dnwell
 grow 840
 and-not nwell
 and dnwell
 grow 840
 and-not nwell
 and dnwell
 grow 840
 and-not nwell
 and dnwell
 grow 840
 and-not nwell
 and dnwell
 grow 840
 and-not nwell
 and dnwell
 grow 840
 and-not nwell
 and dnwell
 grow 635
 and-not nwell
 and dnwell

 templayer dptap_missing *ndiff,*mvndiff
 and dnwell
 and-not dptap_reach

 templayer pdiff_crosses_dnwell dnwell
 grow 20
 and-not dnwell
 and allpdifflv,allpdiffmv

 # MV nwell must be 2um from any other nwell
 templayer mvnwell
 bloat-all alldiffmv nwell
 grow-min 840
 bridge	700 600

 # Simple spacing checks to lvnwell must use CIF-DRC rule
 templayer allmvdiffnowell *mvndiff,*mvpsd

 templayer lvnwell nwell
 and-not mvnwell

 templayer nwell_with_tap
 bloat-all nsc,mvnsc nwell,pnp

 templayer nwell_missing_tap nwell,pnp
 and-not nwell_with_tap

 templayer tap_with_licon
 bloat-all psc,mvpsc psd,mvpsd
 bloat-all nsc,mvnsc nsd,mvnsd

 templayer tap_missing_licon psd,nsd,mvpsd,mvnsd
 and-not tap_with_licon

 # Make sure varactor nwell contains no P diffusion
 templayer pdiff_in_varactor_well
 bloat-all varactor,mvvaractor nwell
 and allpactive

 # HVNTM spacing requires recreating HVNTM
 templayer hvntm_block *mvpsd
 grow 185

 templayer hvntm_generate
 bloat-all mvnfet,mvnfetesd,mvnnfet,nnfet,*mvndiode,mvrdn,*nndiode *mvndiff
 bloat-all mvvaractor *mvnsd
 and-not hvntm_block
 grow 185
 grow    345
 shrink  345
 and-not hvntm_block

 templayer m1_small_hole allm1,obsm1,obsmcon
 close   140000

 templayer m1_hole_empty m1_small_hole
 and-not allm1,obsm1,obsmcon

 templayer m2_small_hole allm2,obsm2
 close   140000

 templayer m2_hole_empty m2_small_hole
 and-not allm2,obsm2

 templayer m1_huge allm1
 shrink 1500
 grow 1500

 templayer m1_large_halo m1_huge
 grow 280
 and-not m1_huge
 and allm1

 templayer m2_huge allm2
 shrink 1500
 grow 1500

 templayer m2_large_halo m2_huge
 grow 280
 and-not m2_huge
 and allm2

 templayer m3_huge allm3
 shrink 1500
 grow 1500

 templayer m3_large_halo m3_huge
 grow 400
 and-not m3_huge
 and allm3

 templayer m4_huge allm4
 shrink 1500
 grow 1500

 templayer m4_large_halo m4_huge
 grow 400
 and-not m4_huge
 and allm4

#ifdef EXPERIMENTAL
#----------------------------------------------------------------
style paint
#----------------------------------------------------------------
# NOTE:  This style is used for database manipulations only via
# the "cif paint" command.
#----------------------------------------------------------------

 scalefactor 10  nanometers

 templayer m1grow *m1
    grow 290

 # layer listrap:  Use the following set of commands to strap local
 # interconnect wires with metal1 (inside the cursor box) to satisfy
 # the maximum aspect ratio rule for local interconnect:
 #
 #    tech unlock *
 #    cif ostyle paint
 #    cif paint m1strap comment
 #    cif paint m1strap m1
 #    cif paint listrap viali
 #    erase comment

 templayer m1strap *li
    and-not m1grow
    grow 30

 templayer listrap comment
    slots 30 170 170 60

#endif (EXPERIMENTAL)

#----------------------------------------------------------------
style density
#----------------------------------------------------------------
# Style used by scripts to check for fill density
#----------------------------------------------------------------
 scalefactor 10  nanometers
 options calma-permissive-labels
 gridlimit 5

 templayer fom_all alldiff,fomfill

 templayer poly_all allpoly,polyfill

 templayer li_all allli,lifill

 templayer m1_all allm1,m1fill

 templayer m2_all allm2,m2fill

 templayer m3_all allm3,m3fill

 templayer m4_all allm4,m4fill

 templayer m5_all allm5,m5fill

#----------------------------------------------------------------
style wafflefill variants (),(tiled)
#----------------------------------------------------------------
# Style used by scripts for automatically generating fill layers
# NOTE: Be sure to generate output on flattened layout.
#----------------------------------------------------------------
 scalefactor 10  nanometers
 options calma-permissive-labels
 gridlimit 5

#----------------------------------------------------------------
# Generate and retain a layer representing the bounding box.
#
# For variant ():
# The bounding box is the full extent of geometry on the top level
# cell.
#
# For variant (tiled):
# Use with a script that breaks layout into flattened tiles and runs
# fill individually on each.  The tiles should be larger than the
# step size, and each should draw a layer "comment" the size of the
# step box.
#----------------------------------------------------------------

 variants ()
     templayer	topbox
	 bbox	top

 variants (tiled)
     templayer	topbox comment
	 # Each tile imposes the full keepout distance rule of
	 # 3um on all sides.
	 shrink 1500

 variants *

#----------------------------------------------------------------
# Generate guard-band around nwells to keep FOM from crossing
# Spacing from LV nwell = Diff/Tap 9 = 0.34um
# Spacing from HV nwell = Diff/Tap 18 = 0.43um (= 0.18 + 0.25)
# Enclosure by nwell = Diff/Tap 8 = 0.18um
#----------------------------------------------------------------

 templayer mvnwell
 	bloat-all alldiffmv nwell

 templayer lvnwell allnwell
	and-not mvnwell

 templayer	well_shrink mvnwell
	shrink 	250
	or lvnwell
	shrink	180
 templayer	well_guardband allnwell
	grow	340
	and-not	well_shrink

#---------------------------------------------------
# Diffusion and poly keep-out areas
#---------------------------------------------------
 templayer      obstruct_fom alldiff,allpoly,fomfill,polyfill,obsactive
	or	rpw,pnp,npn
        grow    500
	or	well_guardband

 templayer      obstruct_poly alldiff,allpoly,fomfill,polyfill,obsactive
	or	rpw,pnp,npn
	grow	1000

#---------------------------------------------------
# FOM and POLY fill
#---------------------------------------------------
 templayer	fomfill_pass1 topbox
        # slots   0 4080 1320 0 4080 1320 1360 0
        slots   0 4080 1600 0 4080 1600 1360 0
        and-not obstruct_fom
	and	topbox
        shrink  2035
        grow    2035

#---------------------------------------------------

 templayer      obstruct_poly_pass1 fomfill_pass1
        grow    300
	or	obstruct_poly
 templayer	polyfill_pass1 topbox
        slots   0 720 360 0 720 360 240 0
        and-not obstruct_poly_pass1
	and	topbox
        shrink  355
        grow    355

#---------------------------------------------------

 templayer      obstruct_fom_pass2 fomfill_pass1
        grow    1290
	or	polyfill_pass1
        grow    300
	or	obstruct_fom
 templayer	fomfill_pass2 topbox
        slots   0 2500 1320 0 2500 1320 1360 0
        and-not obstruct_fom_pass2
	and	topbox
        shrink  1245
        grow    1245

#---------------------------------------------------

 templayer      obstruct_poly_coarse polyfill_pass1
	grow	60
	or	fomfill_pass1,fomfill_pass2
	grow	300
	or	obstruct_poly
 templayer	polyfill_coarse topbox
        slots   0 720 360 0 720 360 240 120
        and-not obstruct_poly_coarse
	and	topbox
        shrink  355
        grow    355

#---------------------------------------------------
 templayer      obstruct_poly_medium polyfill_pass1,polyfill_coarse
	grow	60
	or	fomfill_pass1,fomfill_pass2
        grow    300
	or	obstruct_poly
 templayer	polyfill_medium topbox
        slots   0 540 360 0 540 360 240 100
        and-not obstruct_poly_medium
	and	topbox
        shrink  265
        grow    265

#---------------------------------------------------
 templayer      obstruct_poly_fine polyfill_pass1,polyfill_coarse,polyfill_medium
	grow	60
	or	fomfill_pass1,fomfill_pass2
	grow	300
	or	obstruct_poly
 templayer	polyfill_fine topbox
        slots   0 480 360 0 480 360 240 200
        and-not obstruct_poly_fine
	and	topbox
        shrink  235
        grow    235

#---------------------------------------------------

 templayer      obstruct_fom_coarse fomfill_pass1,fomfill_pass2
        grow    1290
	or	polyfill_pass1,polyfill_coarse,polyfill_medium,polyfill_fine
	grow	300
	or	obstruct_fom
 templayer	fomfill_coarse topbox
        slots   0 1500 1320 0 1500 1320 1360 0
        and-not obstruct_fom_coarse
	and	topbox
        shrink  745
        grow    745

#---------------------------------------------------

 templayer      obstruct_fom_fine fomfill_pass1,fomfill_pass2,fomfill_coarse
        grow    1290
	or	polyfill_pass1,polyfill_coarse,polyfill_medium,polyfill_fine
	grow	300
	or	obstruct_fom
 templayer	fomfill_fine topbox
        slots   0 500 400 0 500 400 160 0
        and-not obstruct_fom_fine
	and	topbox
        shrink  245
        grow    245

#---------------------------------------------------
 layer  FOMFILL fomfill_pass1 
	or	fomfill_pass2
	or	fomfill_coarse
	or	fomfill_fine
 	calma 	23 28

 layer	POLYFILL polyfill_pass1 
	or	 polyfill_coarse
	or	 polyfill_medium
	or	 polyfill_fine
 	calma 	28 28

#---------------------------------------------------------
# LI fill
# Note requirement that LI fill may not overlap (non-fill)
# diff or poly.
#---------------------------------------------------------

 templayer      obstruct_li_coarse allli,allpad,obsli,lifill,fillblock,fillblock4
        grow    2800
	or	alldiff,allpoly
	grow	200
 templayer	lifill_coarse topbox
        # slots   0 3000 650 0 3000 650 700 0
        slots   0 3000 900 0 3000 900 700 0
        and-not obstruct_li_coarse
	and	topbox
        shrink  1495
        grow    1495

 templayer      obstruct_li_medium allli,allpad,obsli,lifill,fillblock,fillblock4
        grow    2500
	or	lifill_coarse
	grow	300
	or	alldiff,allpoly
        grow    200
 templayer	lifill_medium topbox
        slots   0 1500 500 0 1500 500 700 0
        and-not obstruct_li_medium
	and	topbox
        shrink  745
        grow    745

 templayer      obstruct_li_fine allli,allpad,obsli,lifill,fillblock,fillblock4
	or	lifill_coarse,lifill_medium
	grow	300
	or	alldiff,allpoly
        grow    200
 templayer	lifill_fine topbox
        slots   0 580 500 0 580 500 700 0
        and-not obstruct_li_fine
	and	topbox
        shrink  285
        grow    285

 layer	LIFILL  lifill_coarse
	or	lifill_medium
	or	lifill_fine
 	calma 	56 28

#---------------------------------------------------
# MET1 fill
#---------------------------------------------------

 templayer      obstruct_m1_coarse allm1,allpad,obsm1,m1fill,fillblock,fillblock4
        grow    3000
 templayer	met1fill_coarse topbox
        # slots   0 2000 200 0 2000 200 700 0
        slots   0 2000 800 0 2000 800 700 350
        and-not obstruct_m1_coarse
	and	topbox
        shrink  995
        grow    995

 templayer      obstruct_m1_medium allm1,allpad,obsm1,m1fill,fillblock,fillblock4
        grow    2800
	or	met1fill_coarse
        grow    200
 templayer	met1fill_medium topbox
        slots   0 1000 200 0 1000 200 700 0
        and-not obstruct_m1_medium
	and	topbox
        shrink  495
        grow    495

 templayer      obstruct_m1_fine allm1,allpad,obsm1,m1fill,fillblock,fillblock4
        grow    300
	or	met1fill_coarse,met1fill_medium
        grow    200
 templayer	met1fill_fine topbox
        slots   0 580 200 0 580 200 700 0
        and-not obstruct_m1_fine
	and	topbox
        shrink  285
        grow    285

 templayer      obstruct_m1_veryfine allm1,allpad,obsm1,m1fill,fillblock,fillblock4
        grow    100
	or	met1fill_coarse,met1fill_medium,met1fill_fine
        grow    200
 templayer	met1fill_veryfine topbox
        slots   0 300 200 0 300 200 100 50
        and-not obstruct_m1_veryfine
	and	topbox
        shrink  145
        grow    145

 layer	MET1FILL met1fill_coarse
	or	met1fill_medium
	or	met1fill_fine
	or	met1fill_veryfine
 	calma 	36 28

#---------------------------------------------------
# MET2 fill
#---------------------------------------------------
 templayer      obstruct_m2 allm2,allpad,obsm2,m2fill,fillblock,fillblock4
        grow    3000
 templayer	met2fill_coarse topbox
        # slots   0 2000 200 0 2000 200 700 350
        slots   0 2000 800 0 2000 800 700 350
        and-not obstruct_m2
	and	topbox
        shrink  995
        grow    995

 templayer      obstruct_m2_medium allm2,allpad,obsm2,m2fill,fillblock,fillblock4
        grow    2800
	or	met2fill_coarse
        grow    200
 templayer	met2fill_medium topbox
        slots   0 1000 200 0 1000 200 700 350
        and-not obstruct_m2_medium
	and	topbox
        shrink  495
        grow    495

 templayer      obstruct_m2_fine allm2,allpad,obsm2,m2fill,fillblock,fillblock4
        grow    300
	or	met2fill_coarse,met2fill_medium
        grow    200
 templayer	met2fill_fine topbox
        slots   0 580 200 0 580 200 700 350
        and-not obstruct_m2_fine
	and	topbox
        shrink  285
        grow    285

 templayer      obstruct_m2_veryfine allm2,allpad,obsm2,m2fill,fillblock,fillblock4
        grow    100
	or	met2fill_coarse,met2fill_medium,met2fill_fine
        grow    200
 templayer	met2fill_veryfine topbox
        slots   0 300 200 0 300 200 100 100
        and-not obstruct_m2_veryfine
	and	topbox
        shrink  145
        grow    145

 layer	MET2FILL met2fill_coarse
	or met2fill_medium
	or met2fill_fine
	or met2fill_veryfine
 	calma 	41 28

#---------------------------------------------------
# MET3 fill
#---------------------------------------------------
 templayer      obstruct_m3 allm3,allpad,obsm3,m3fill,fillblock,fillblock4
        grow    3000
 templayer	met3fill_coarse topbox
        # slots   0 2000 300 0 2000 300 700 700
        slots   0 2000 800 0 2000 800 700 350
        and-not obstruct_m3
	and	topbox
        shrink  995
        grow    995

 templayer      obstruct_m3_medium allm3,allpad,obsm3,m3fill,fillblock,fillblock4
        grow    2700
	or	met3fill_coarse
        grow    300
 templayer	met3fill_medium topbox
        slots   0 1000 300 0 1000 300 700 700
        and-not obstruct_m3_medium
	and	topbox
        shrink  495
        grow    495

 templayer      obstruct_m3_fine allm3,allpad,obsm3,m3fill,fillblock,fillblock4
        grow    200
	or	met3fill_coarse,met3fill_medium
        grow    300
 templayer	met3fill_fine topbox
        slots   0 580 300 0 580 300 700 700
        and-not obstruct_m3_fine
	and	topbox
        shrink  285
        grow    285

 templayer      obstruct_m3_veryfine allm3,allpad,obsm3,m3fill,fillblock,fillblock4
	# Note: Adding 0.1 to waffle rule to clear wide spacing rule
        grow    100
	or	met3fill_coarse,met3fill_medium,met3fill_fine
        grow    300
 templayer	met3fill_veryfine topbox
        slots   0 400 300 0 400 300 150 200
        and-not obstruct_m3_veryfine
	and	topbox
        shrink  195
        grow    195

 layer	MET3FILL met3fill_coarse
	or	met3fill_medium
	or	met3fill_fine
	or	met3fill_veryfine
 	calma 	34 28

#ifdef METAL5
#---------------------------------------------------
# MET4 fill
#---------------------------------------------------
 templayer      obstruct_m4 allm4,allpad,obsm4,m4fill,fillblock,fillblock4
        grow    3000
 templayer	met4fill_coarse topbox
        # slots   0 2000 300 0 2000 300 700 1050
        slots   0 2000 800 0 2000 800 700 350
        and-not obstruct_m4
	and	topbox
        shrink  995
        grow    995

 templayer      obstruct_m4_medium allm4,allpad,obsm4,m4fill,fillblock,fillblock4
        grow    2700
	or	met4fill_coarse
        grow    300
 templayer	met4fill_medium topbox
        slots   0 1000 300 0 1000 300 700 1050
        and-not obstruct_m4_medium
	and	topbox
        shrink  495
        grow    495

 templayer      obstruct_m4_fine allm4,allpad,obsm4,m4fill,fillblock,fillblock4
        grow    200
	or	met4fill_coarse,met4fill_medium
        grow    300
 templayer	met4fill_fine topbox
        slots   0 580 300 0 580 300 700 1050
        and-not obstruct_m4_fine
	and	topbox
        shrink  285
        grow    285

 templayer      obstruct_m4_veryfine allm4,allpad,obsm4,m4fill,fillblock,fillblock4
	# Note: Adding 0.1 to waffle rule to clear wide spacing rule
        grow    100
	or	met4fill_coarse,met4fill_medium,met4fill_fine
        grow    300
 templayer	met4fill_veryfine topbox
        slots   0 400 300 0 400 300 150 300
        and-not obstruct_m4_veryfine
	and	topbox
        shrink  195
        grow    195

 layer	MET4FILL met4fill_coarse
	or	met4fill_medium
	or	met4fill_fine
	or	met4fill_veryfine
 	calma 	51 28

#---------------------------------------------------
# MET5 fill
#---------------------------------------------------
 templayer      obstruct_m5 allm5,allpad,obsm5,m5fill,fillblock
        grow    3000
 templayer	met5fill_coarse topbox
        slots   0 5000 1600 0 5000 1600 1000 100
        and-not obstruct_m5
	and	topbox
        shrink  2495
        grow    2495

 templayer      obstruct_m5_medium allm5,allpad,obsm5,m5fill,fillblock
        grow    1400
	or	met5fill_coarse
        grow    1600
 templayer	met5fill_medium topbox
        slots   0 3000 1600 0 3000 1600 1000 100
        and-not obstruct_m5_medium
	and	topbox
        shrink  1495
        grow    1495

 layer	MET5FILL met5fill_coarse
	or	met5fill_medium
 	calma 	59 28
#endif (METAL5)

end

#-----------------------------------------------------------------------
cifinput
#-----------------------------------------------------------------------
# NOTE:  All values in this section MUST be multiples of 25 
# or else magic will scale below the allowed layout grid size
#-----------------------------------------------------------------------

style  sky130 variants (),(vendor)
 scalefactor 10 nanometers
 gridlimit 5

 options ignore-unknown-layer-labels no-reconnect-labels

#ifndef MIM
 ignore CAPM
 ignore CAPM2
#endif (!MIM)
#ifndef METAL5
 ignore MET4,VIA3
 ignore MET5,VIA4
#endif
 ignore NPC
 ignore SEALID
 ignore CAPID
 ignore LDNTM
 ignore HVNTM
 ignore POLYMOD
 ignore LOWTAPDENSITY
 ignore FILLOBSPOLY
 ignore OUTLINE

 layer pnp NWELL,WELLTXT,WELLPIN
 and PNPID
 labels NWELL
 variants (vendor)
 labels WELLTXT port
 variants ()
 labels WELLTXT text
 variants *
 labels WELLPIN port

 layer nwell NWELL,WELLTXT,WELLPIN
 and-not PNPID
 labels NWELL
 variants (vendor)
 labels WELLTXT port
 variants ()
 labels WELLTXT text
 variants *
 labels WELLPIN port

 layer pwell SUBTXT,SUBPIN
 variants (vendor)
 labels SUBTXT port
 variants ()
 labels SUBTXT text
 variants *
 labels SUBPIN port

 # Always draw pwell under p-tap and n-diff.  This is not always
 # necessary but works better with deep nwell for correct extraction.
 layer pwell TAP,DIFF
 and-not NWELL
 grow 130
 grow 420
 shrink 420

 layer dnwell DNWELL
 labels DNWELL

 layer npn DNWELL
 and-not NWELL
 and NPNID

 layer rpw PWRES
 and DNWELL
 labels PWRES

 templayer ndiffarea DIFF,DIFFTXT,DIFFPIN,barediff
 and-not POLY
 and-not NWELL
 and-not PSDM
 and-not DIODE
 and-not DIFFRES
 and-not HVI
 and NSDM
 and-not CORELI
 copyup ndifcheck
 labels DIFF
 variants (vendor)
 labels DIFFTXT port
 variants ()
 labels DIFFTXT text
 variants *
 labels DIFFPIN port

 layer ndiff ndiffarea

 # Copy ndiff areas up for contact checks
 templayer xndifcheck ndifcheck
 copyup ndifcheck

 templayer mvndiffarea DIFF,DIFFTXT,DIFFPIN,barediff
 and-not POLY
 and-not NWELL
 and-not PSDM
 and-not DIODE
 and-not DIFFRES
 and HVI
 and NSDM
 copyup ndifcheck
 labels DIFF
 labels DIFFTXT text
 variants (vendor)
 labels DIFFTXT port
 variants ()
 labels DIFFTXT text
 variants *
 labels DIFFPIN port

 layer mvndiff mvndiffarea

 # Copy ndiff areas up for contact checks
 templayer mvxndifcheck mvndifcheck
 copyup mvndifcheck

 layer ndiode DIFF,barediff
 and NSDM
 and DIODE
 and-not NWELL
 and-not POLY
 and-not PSDM
 and-not HVI
 and-not LVTN
 labels DIFF

 layer ndiodelvt DIFF,barediff
 and NSDM
 and DIODE
 and-not NWELL
 and-not POLY
 and-not PSDM
 and-not HVI
 and LVTN
 labels DIFF

 templayer ndiodearea DIODE
 and NSDM
 and-not HVI
 and-not NWELL
 copyup DIODE,NSDM

 layer ndiffres DIFFRES
 and NSDM
 and-not HVI
 labels DIFF

 templayer pdiffarea DIFF,DIFFTXT,DIFFPIN,barediff
 and-not POLY
 and NWELL
 and-not NSDM
 and-not DIODE
 and-not HVI
 and PSDM
 copyup pdifcheck
 labels DIFF 
 variants (vendor)
 labels DIFFTXT port
 variants ()
 labels DIFFTXT text
 variants *
 labels DIFFPIN port

 layer pdiff pdiffarea

 layer mvndiode DIFF,barediff
 and NSDM
 and DIODE
 and HVI
 and-not POLY
 and-not PSDM
 and-not LVTN
 labels DIFF

 layer nndiode DIFF,barediff
 and NSDM
 and DIODE
 and HVI
 and-not POLY
 and-not PSDM
 and LVTN
 labels DIFF

 templayer mvndiodearea DIODE
 and NSDM
 and HVI
 and-not NWELL
 copyup DIODE,NSDM

 layer mvndiffres DIFFRES
 and NSDM
 and HVI
 labels DIFF

 templayer mvpdiffarea DIFF,DIFFTXT,DIFFPIN,barediff
 and-not POLY
 and NWELL
 and-not NSDM
 and HVI
 and-not DIODE
 and-not DIFFRES
 and PSDM
 copyup mvpdifcheck
 labels DIFF
 variants (vendor)
 labels DIFFTXT port
 variants ()
 labels DIFFTXT text
 variants *
 labels DIFFPIN port

 layer mvpdiff mvpdiffarea

 # Copy pdiff areas up for contact checks
 templayer xpdifcheck pdifcheck
 copyup pdifcheck

 layer pdiode DIFF,barediff
 and PSDM
 and-not POLY
 and-not NSDM
 and-not HVI
 and-not LVTN
 and-not HVTP
 and DIODE
 labels DIFF

 layer pdiodelvt DIFF,barediff
 and PSDM
 and-not POLY
 and-not NSDM
 and-not HVI
 and LVTN
 and-not HVTP
 and DIODE
 labels DIFF

 layer pdiodehvt DIFF,barediff
 and PSDM
 and-not POLY
 and-not NSDM
 and-not HVI
 and-not LVTN
 and HVTP
 and DIODE
 labels DIFF

 templayer pdiodearea DIODE
 and PSDM
 and-not HVI
 copyup DIODE,PSDM

 # Define pfet areas as known pdiff, regardless of the presence of a well.

 templayer pfetarea DIFF,barediff
 and POLY
 or baretrans
 and-not NSDM
 and-not HVI

 layer pfet pfetarea
 and-not LVTN
 and-not HVTP
 and-not STDCELL
 and-not COREID
 labels DIFF

 layer scpfet pfetarea
 and-not LVTN
 and-not HVTP
 and STDCELL
 and-not COREID
 labels DIFF

 layer scpfethvt pfetarea
 and-not LVTN
 and HVTP
 and STDCELL
 labels DIFF

 layer ppu pfetarea
 and-not LVTN
 and HVTP
 and COREID
 # Shrink-grow operation eliminates the smaller parasitie device
 # shrink 70
 # grow 70
 labels DIFF

 layer pfetlvt pfetarea
 and LVTN
 labels DIFF

 layer pfetmvt pfetarea
 and HVTR
 labels DIFF

 layer pfethvt pfetarea
 and HVTP
 and-not STDCELL
 and-not COREID
 labels DIFF

 # Always force nwell under pfet (nwell encloses pdiff by 0.18)
 layer nwell pfetarea
 grow 180

 # Copy mvpdiff areas up for contact checks
 templayer mvxpdifcheck mvpdifcheck
 copyup mvpdifcheck

 layer mvpdiode DIFF,barediff
 and PSDM
 and-not POLY
 and-not NSDM
 and HVI
 and DIODE
 labels DIFF

 templayer mvpdiodearea DIODE
 and PSDM
 and HVI
 copyup DIODE,PSDM

 # Define pfet areas as known pdiff,
 # regardless of the presence of a
 # well.

 templayer mvpfetarea DIFF,barediff
 and POLY
 or baretrans
 and-not NSDM
 and HVI

 layer mvpfet mvpfetarea
 and-not ESDID
 labels DIFF

 layer mvpfetesd mvpfetarea
 and ESDID
 labels DIFF

 layer pdiff DIFF,DIFFTXT,DIFFPIN,barediff
 and-not NSDM
 and-not POLY
 and-not HVI
 and-not DIODE
 and-not DIFFRES
 labels DIFF
 variants (vendor)
 labels DIFFTXT port
 variants ()
 labels DIFFTXT text
 variants *
 labels DIFFPIN port

 layer pdiffres DIFFRES
 and PSDM
 and NWELL
 and-not HVI
 labels DIFF

 layer nfet DIFF,barediff
 and POLY
 or baretrans
 and-not PSDM
 and NSDM
 and-not HVI
 and-not LVTN
 and-not SONOS
 and-not STDCELL
 and-not COREID
 labels DIFF

 layer scnfet DIFF,barediff
 and POLY
 or baretrans
 and-not PSDM
 and NSDM
 and-not NWELL
 and-not HVI
 and-not LVTN
 and-not SONOS
 and STDCELL
 labels DIFF

 layer npass DIFF,barediff
 and POLY
 or baretrans
 and-not PSDM
 and NSDM
 and-not NWELL
 and COREID
 labels DIFF

 layer npd DIFF,barediff
 and POLY
 or baretrans
 and-not PSDM
 and NSDM
 and-not NWELL
 and COREID
 # Shrink-grow operation eliminates the smaller npass device
 shrink 70
 grow 70
 labels DIFF

 # Devices abutting tap under gate are officially npd, not npass
 layer npd TAP
 grow 100
 and DIFF
 and POLY
 and-not PSDM
 and NSDM
 and-not NWELL
 and COREID
 labels DIFF

 layer nfetlvt DIFF,barediff
 and POLY
 or baretrans
 and-not PSDM
 and NSDM
 and-not HVI
 and LVTN
 and-not SONOS
 labels DIFF

 layer nsonos DIFF,barediff
 and POLY
 or baretrans
 and-not PSDM
 and NSDM
 and-not HVI
 and LVTN
 and SONOS
 labels DIFF

 templayer nsdarea TAP
 and NSDM
 and NWELL
 and-not POLY
 and-not PSDM
 and-not HVI
 and-not CORELI
 copyup nsubcheck

 layer nsd nsdarea
 labels TAP

 layer nsd TAP,TAPTXT
 and NSDM
 and-not POLY
 and-not HVI
 labels TAP
 labels TAPTXT text

 layer corenvar TAP
 and NSDM
 and POLY
 and COREID
 labels TAP

 templayer nsdexpand nsdarea
 grow 500

 # Copy nsub areas up for contact checks
 templayer xnsubcheck nsubcheck
 copyup nsubcheck

 templayer psdarea TAP
 and PSDM
 and-not NWELL
 and-not POLY
 and-not NSDM
 and-not HVI
 and-not pfetexpand
 copyup psubcheck

 layer psd psdarea
 labels TAP

 layer psd TAP
 and PSDM
 and-not POLY
 and-not HVI
 labels TAP
 labels TAPTXT text

 layer corepvar TAP
 and PSDM
 and POLY
 and COREID
 labels TAP

 templayer psdexpand psdarea
 grow 500

 layer mvpdiff DIFF,DIFFTXT,DIFFPIN,barediff
 and-not NSDM
 and-not POLY
 and HVI
 and mvpfetexpand
 labels DIFF
 variants (vendor)
 labels DIFFTXT port
 variants ()
 labels DIFFTXT text
 variants *
 labels DIFFPIN port

 layer mvpdiffres DIFFRES
 and PSDM
 and NWELL
 and HVI
 and-not mvrdpioedge
 labels DIFF

 templayer mvnfetarea DIFF,barediff
 and POLY
 or baretrans
 and-not PSDM
 and NSDM
 and-not LVTN
 and HVI
 grow 350

 templayer mvnnfetarea DIFF,TAP,barediff
 and POLY
 or baretrans
 and-not PSDM
 and NSDM
 and LVTN
 and HVI
 and-not mvnfetarea

 layer mvnfetesd DIFF,barediff
 and POLY
 or baretrans
 and-not PSDM
 and NSDM
 and HVI
 and ESDID
 and-not mvnnfetarea
 labels DIFF

 layer mvnfet DIFF,barediff
 and POLY
 or baretrans
 and-not PSDM
 and NSDM
 and HVI
 and-not ESDID
 and-not mvnnfetarea
 labels DIFF

 layer nnfet mvnnfetarea
 and LVID
 labels DIFF

 layer mvnnfet mvnnfetarea
 and-not LVID
 labels DIFF

 templayer mvnsdarea TAP
 and NSDM
 and NWELL
 and-not POLY
 and-not PSDM
 and HVI
 copyup mvnsubcheck

 layer mvnsd mvnsdarea
 labels TAP

 layer mvnsd TAP,TAPTXT
 and NSDM
 and HVI
 labels TAP
 labels TAPTXT text

 templayer mvnsdexpand mvnsdarea
 grow 500

 # Copy nsub areas up for contact checks
 templayer mvxnsubcheck mvnsubcheck
 copyup mvnsubcheck

 templayer mvpsdarea DIFF,barediff
 and PSDM
 and-not NWELL
 and-not POLY
 and-not NSDM
 and HVI
 and-not mvpfetexpand
 copyup mvpsubcheck

 layer mvpsd mvpsdarea
 labels DIFF

 layer mvpsd TAP,TAPTXT
 and PSDM
 and HVI
 labels TAP
 labels TAPTXT text

 templayer mvpsdexpand mvpsdarea
 grow 500

 # Copy psub areas up for contact checks
 templayer xpsubcheck psubcheck
 copyup psubcheck

 templayer mvxpsubcheck mvpsubcheck
 copyup mvpsubcheck

 layer psd TAP
 and-not PSDM
 and-not NSDM
 and-not POLY
 and-not HVI
 and-not pfetexpand
 and psdexpand

 layer nsd TAP
 and-not PSDM
 and-not NSDM
 and-not POLY
 and-not HVI
 and nsdexpand

 layer mvpsd TAP
 and-not PSDM
 and-not NSDM
 and-not POLY
 and HVI
 and-not mvpfetexpand
 and mvpsdexpand

 layer mvnsd TAP
 and-not PSDM
 and-not NSDM
 and-not POLY
 and HVI
 and mvnsdexpand

 templayer hresarea POLY
 and RPM
 grow 3000

 templayer uresarea POLY
 and URPM
 grow 3000

 templayer diffresarea DIFFRES
 and-not HVI
 grow 3000

 templayer mvdiffresarea DIFFRES
 and HVI
 grow 3000

 templayer resarea diffresarea,mvdiffresarea,hresarea,uresarea

 layer pfet POLY
 and DIFF
 and diffresarea
 and-not NSDM
 and-not STDCELL

 layer scpfet POLY
 and DIFF
 and diffresarea
 and-not HVTP
 and-not NSDM
 and STDCELL

 layer scpfethvt POLY
 and DIFF
 and diffresarea
 and HVTP
 and-not NSDM
 and STDCELL

 templayer xpolyterm RPM,URPM
 and POLY
 and-not POLYRES
 # add back the 0.06um contact surround in the direction of the resistor
 grow 60
 and POLY

 layer xpc xpolyterm

 templayer polyarea POLY,POLYTXT,POLYPIN
 and-not POLYRES
 and-not POLYSHORT
 and-not DIFF
 and-not TAP
 and-not RPM
 and-not URPM
 copyup polycheck

 layer poly polyarea
 labels POLY
 variants (vendor)
 labels POLYTXT port
 variants ()
 labels POLYTXT text
 variants *
 labels POLYPIN port

 # Copy (non-resistor) poly areas up for contact checks
 templayer xpolycheck polycheck
 copyup polycheck

 layer mrp1 POLY
 and POLYRES
 and-not RPM
 and-not URPM
 labels POLY

 layer rmp POLY
 and POLYSHORT
 labels POLY

 layer xhrpoly POLY
 and POLYRES
 and RPM
 and-not URPM
 and PSDM
 and NPC
 and-not xpolyterm
 labels POLY

 layer uhrpoly POLY
 and POLYRES
 and URPM
 and-not RPM
 and NPC
 and-not xpolyterm
 labels POLY

 templayer ndcbase CONT
 or barecont
 and LI
 or licont
 and DIFF
 and NSDM
 and-not NWELL
 and-not HVI

 layer ndc ndcbase
 grow 85
 shrink 85
 shrink 85
 grow 85
 or ndcbase
 labels CONT

 templayer nscbase CONT
 or barecont
 and LI
 or licont
 and DIFF,TAP
 and NSDM
 and NWELL
 and-not HVI

 layer nsc nscbase
 grow 85
 shrink 85
 shrink 85
 grow 85
 or nscbase
 labels CONT

 templayer pdcbase CONT
 or barecont
 and LI
 or licont
 and DIFF
 and PSDM
 and NWELL
 and-not HVI

 layer pdc pdcbase
 grow 85
 shrink 85
 shrink 85
 grow 85
 or pdcbase
 labels CONT

 templayer pdcnowell CONT
 or barecont
 and LI
 or licont
 and DIFF
 and PSDM
 and pfetexpand
 and-not HVI

 layer pdc pdcnowell
 grow 85
 shrink 85
 shrink 85
 grow 85
 or pdcnowell
 labels CONT

 templayer pscbase CONT
 or barecont
 and LI
 or licont
 and DIFF,TAP
 and PSDM
 and-not NWELL
 and-not pfetexpand
 and-not HVI

 layer psc pscbase
 grow 85
 shrink 85
 shrink 85
 grow 85
 or pscbase
 labels CONT

 templayer pcbase CONT
 or barecont
 and LI
 or licont
 and POLY
 and-not DIFF
 and-not RPM,URPM

 layer pc pcbase
 grow 85
 shrink 85
 shrink 85
 grow 85
 or pcbase
 labels CONT

 templayer ndicbase CONT
 or barecont
 and LI
 or licont
 and DIFF
 and NSDM
 and DIODE
 and-not POLY
 and-not PSDM
 and-not HVI
 and-not LVTN

 layer ndic ndicbase
 grow 85
 shrink 85
 shrink 85
 grow 85
 or ndicbase
 labels CONT

 templayer ndilvtcbase CONT
 or barecont
 and LI
 or licont
 and DIFF
 and NSDM
 and DIODE
 and-not POLY
 and-not PSDM
 and-not HVI
 and LVTN

 layer ndilvtc ndilvtcbase
 grow 85
 shrink 85
 shrink 85
 grow 85
 or ndilvtcbase
 labels CONT

 templayer pdicbase CONT
 or barecont
 and LI
 or licont
 and DIFF
 and PSDM
 and DIODE
 and-not POLY
 and-not NSDM
 and-not HVI
 and-not LVTN
 and-not HVTP

 layer pdic pdicbase
 grow 85
 shrink 85
 shrink 85
 grow 85
 or pdicbase
 labels CONT

 templayer pdilvtcbase CONT
 or barecont
 and LI
 or licont
 and DIFF
 and PSDM
 and DIODE
 and-not POLY
 and-not NSDM
 and-not HVI
 and LVTN
 and-not HVTP

 layer pdilvtc pdilvtcbase
 grow 85
 shrink 85
 shrink 85
 grow 85
 or pdilvtcbase
 labels CONT

 templayer pdihvtcbase CONT
 or barecont
 and LI
 or licont
 and DIFF
 and PSDM
 and DIODE
 and-not POLY
 and-not NSDM
 and-not HVI
 and-not LVTN
 and HVTP

 layer pdihvtc pdihvtcbase
 grow 85
 shrink 85
 shrink 85
 grow 85
 or pdihvtcbase
 labels CONT

 templayer mvndcbase CONT
 or barecont
 and LI
 or licont
 and DIFF
 and NSDM
 and-not NWELL
 and HVI

 layer mvndc mvndcbase
 grow 85
 shrink 85
 shrink 85
 grow 85
 or mvndcbase
 labels CONT

 templayer mvnscbase CONT
 or barecont
 and LI
 or licont
 and DIFF,TAP
 and NSDM
 and NWELL
 and HVI

 layer mvnsc mvnscbase
 grow 85
 shrink 85
 shrink 85
 grow 85
 or mvnscbase
 labels CONT

 templayer mvpdcbase CONT
 or barecont
 and LI
 or licont
 and DIFF
 and PSDM
 and NWELL
 and HVI

 layer mvpdc mvpdcbase
 grow 85
 shrink 85
 shrink 85
 grow 85
 or mvpdcbase
 labels CONT

 templayer mvpdcnowell CONT
 or barecont
 and LI
 or licont
 and DIFF
 and PSDM
 and mvpfetexpand
 and MET1
 and HVI

 layer mvpdc mvpdcnowell
 grow 85
 shrink 85
 shrink 85
 grow 85
 or mvpdcnowell
 labels CONT

 templayer mvpscbase CONT
 or barecont
 and LI
 or licont
 and DIFF,TAP
 and PSDM
 and-not NWELL
 and-not mvpfetexpand
 and HVI

 layer mvpsc mvpscbase
 grow 85
 shrink 85
 shrink 85
 grow 85
 or mvpscbase
 labels CONT

 templayer mvndicbase CONT
 or barecont
 and LI
 or licont
 and DIFF
 and NSDM
 and DIODE
 and-not POLY
 and-not PSDM
 and-not LVTN
 and HVI

 layer mvndic mvndicbase
 grow 85
 shrink 85
 shrink 85
 grow 85
 or mvndicbase
 labels CONT

 templayer nndicbase CONT
 or barecont
 and LI
 or licont
 and DIFF
 and NSDM
 and DIODE
 and-not POLY
 and-not PSDM
 and LVTN
 and HVI

 layer nndic nndicbase
 grow 85
 shrink 85
 shrink 85
 grow 85
 or nndicbase
 labels CONT

 templayer mvpdicbase CONT
 or barecont
 and LI
 or licont
 and DIFF
 and PSDM
 and DIODE
 and-not POLY
 and-not NSDM
 and HVI

 layer mvpdic mvpdicbase
 grow 85
 shrink 85
 shrink 85
 grow 85
 or mvpdicbase
 labels CONT

 layer	fomfill  FOMFILL
 labels FOMFILL

 layer	polyfill POLYFILL
 labels POLYFILL

 layer coreli LI,LITXT,LIPIN
 and-not LIRES,LISHORT
 and COREID
 labels LI
 variants (vendor)
 labels LITXT port
 variants ()
 labels LITXT text
 variants *
 labels LIPIN port

 layer locali LI,LITXT,LIPIN
 and-not LIRES,LISHORT
 and-not COREID
 labels LI
 variants (vendor)
 labels LITXT port
 variants ()
 labels LITXT text
 variants *
 labels LIPIN port

 layer rli LI
 and LIRES,LISHORT
 labels LIRES,LISHORT

 layer	lifill LIFILL
 labels LIFILL

 layer mcon MCON
 grow 95
 shrink 95
 shrink 85
 grow 85
 or MCON
 labels MCON

 layer m1 MET1,MET1TXT,MET1PIN
 and-not MET1RES,MET1SHORT
 labels MET1
 variants (vendor)
 labels MET1TXT port
 variants ()
 labels MET1TXT text
 variants *
 labels MET1PIN port

 layer rm1 MET1
 and MET1RES,MET1SHORT
 labels MET1RES,MET1SHORT

 layer m1fill MET1FILL
 labels MET1FILL

#ifdef MIM
 layer mimcap MET3
 and CAPM
 labels CAPM

 layer mimcc VIA3
 and CAPM
 grow 60
 grow 40
 shrink 40
 labels CAPM

 layer mimcap2 MET4
 and CAPM2
 labels CAPM2

 layer mim2cc VIA4
 and CAPM2
 grow 190
 grow 210
 shrink 210
 labels CAPM2

#endif (MIM)

 templayer m2cbase VIA1
 and-not COREID
 grow 5
 or VIA1
 grow 50

 layer m2c m2cbase
 grow 30
 shrink 30
 shrink 130
 grow 130
 or m2cbase

 layer m2 MET2,MET2TXT,MET2PIN
 and-not MET2RES,MET2SHORT
 labels MET2
 variants (vendor)
 labels MET2TXT port
 variants ()
 labels MET2TXT text
 variants *
 labels MET2PIN port

 layer rm2 MET2
 and MET2RES,MET2SHORT
 labels MET2RES,MET2SHORT

 layer m2fill MET2FILL
 labels MET2FILL

 templayer m3cbase VIA2
 grow 40

 layer m3c m3cbase
 grow 60
 shrink 60
 shrink 140 
 grow 140
 or m3cbase

 layer m3 MET3,MET3TXT,MET3PIN
 and-not MET3RES,MET3SHORT
 labels MET3
 variants (vendor)
 labels MET3TXT port
 variants ()
 labels MET3TXT text
 variants *
 labels MET3PIN port

 layer rm3 MET3
 and MET3RES,MET3SHORT
 labels MET3RES,MET3SHORT

 layer m3fill MET3FILL
 labels MET3FILL

#ifdef (METAL5)

 templayer via3base VIA3
#ifdef MIM
 and-not CAPM
#endif (MIM)
 grow 60

 layer via3 via3base
 grow 40
 shrink 40
 shrink 160
 grow 160
 or via3base

 layer m4 MET4,MET4TXT,MET4PIN
 and-not MET4RES,MET4SHORT
 labels MET4
 variants (vendor)
 labels MET4TXT port
 variants ()
 labels MET4TXT text
 variants *
 labels MET4PIN port

 layer rm4 MET4
 and MET4RES,MET4SHORT
 labels MET4RES,MET4SHORT

 layer m4fill MET4FILL
 labels MET4FILL

 layer m5 MET5,MET5TXT,MET5PIN
 and-not MET5RES,MET5SHORT
 labels MET5
 variants (vendor)
 labels MET5TXT port
 variants ()
 labels MET5TXT text
 variants *
 labels MET5PIN port

 layer rm5 MET5
 and MET5RES,MET5SHORT
 labels MET5RES,MET5SHORT

 layer m5fill MET5FILL
 labels MET5FILL

 templayer via4base VIA4
#ifdef MIM
 and-not CAPM2
#endif (MIM)
 grow 190

 layer via4 via4base
 grow 210
 shrink 210
 shrink 590
 grow 590
 or via4base
#endif (METAL5)

#ifdef REDISTRIBUTION
 layer metrdl RDL,RDLTXT,RDLPIN
 labels RDL
 variants (vendor)
 labels RDLTXT port
 variants ()
 labels RDLTXT text
 variants *
 labels RDLPIN port
#endif

 # Find diffusion not covered in
 # NSDM or PSDM and pull it into
 # the next layer up

 templayer gentrans DIFF
 and-not PSDM
 and-not NSDM
 and POLY
 copyup baretrans

 templayer gendiff DIFF,TAP
 and-not PSDM
 and-not NSDM
 and-not POLY
 and-not COREID
 copyup barediff

 # Handle contacts found by copyup

 templayer ndiccopy CONT
 and LI
 and DIODE
 and NSDM
 and-not HVI

 layer ndic ndiccopy
 grow 85
 shrink 85
 shrink 85
 grow 85
 or ndiccopy
 labels CONT

 templayer mvndiccopy CONT
 and LI
 and DIODE
 and NSDM
 and HVI

 layer mvndic mvndiccopy
 grow 85
 shrink 85
 shrink 85
 grow 85
 or mvndiccopy
 labels CONT

 templayer pdiccopy CONT
 and LI
 and DIODE
 and PSDM
 and-not HVI

 layer pdic pdiccopy
 grow 85
 shrink 85
 shrink 85
 grow 85
 or pdiccopy
 labels CONT

 templayer mvpdiccopy CONT
 and LI
 and DIODE
 and PSDM
 and HVI

 layer mvpdic mvpdiccopy
 grow 85
 shrink 85
 shrink 85
 grow 85
 or mvpdiccopy
 labels CONT

 templayer ndccopy CONT
 and ndifcheck

 layer ndc ndccopy
 grow 85
 shrink 85
 shrink 85
 grow 85
 or ndccopy
 labels CONT

 templayer mvndccopy CONT
 and mvndifcheck

 layer mvndc mvndccopy
 grow 85
 shrink 85
 shrink 85
 grow 85
 or mvndccopy
 labels CONT

 templayer pdccopy CONT
 and pdifcheck

 layer pdc pdccopy
 grow 85
 shrink 85
 shrink 85
 grow 85
 or pdccopy
 labels CONT

 templayer mvpdccopy CONT
 and mvpdifcheck

 layer mvpdc mvpdccopy
 grow 85
 shrink 85
 shrink 85
 grow 85
 or mvpdccopy
 labels CONT

 templayer pccopy CONT
 and polycheck

 layer pc pccopy
 grow 85
 shrink 85
 shrink 85
 grow 85
 or pccopy
 labels CONT

 templayer nsccopy CONT
 and nsubcheck

 layer nsc nsccopy
 grow 85
 shrink 85
 shrink 85
 grow 85
 or nsccopy
 labels CONT

 templayer mvnsccopy CONT
 and mvnsubcheck

 layer mvnsc mvnsccopy
 grow 85
 shrink 85
 shrink 85
 grow 85
 or mvnsccopy
 labels CONT

 templayer psccopy CONT
 and psubcheck

 layer psc psccopy
 grow 85
 shrink 85
 shrink 85
 grow 85
 or psccopy
 labels CONT

 templayer mvpsccopy CONT
 and mvpsubcheck

 layer mvpsc mvpsccopy
 grow 85
 shrink 85
 shrink 85
 grow 85
 or mvpsccopy
 labels CONT

 # Find contacts not covered in
 # metal and pull them into the
 # next layer up
 
 templayer gencont CONT
 and LI
 and-not DIFF,TAP
 and-not POLY
 and-not DIODE
 and-not nsubcheck
 and-not psubcheck
 and-not mvnsubcheck
 and-not mvpsubcheck
 and-not CORELI
 copyup barelicont

 templayer barecont CONT
 and-not LI
 and-not nsubcheck
 and-not psubcheck
 and-not mvnsubcheck
 and-not mvpsubcheck
 and-not CORELI
 copyup barecont

 layer glass GLASS,PADTXT,PADPIN
 labels GLASS
 variants (vendor)
 labels PADTXT port
 variants ()
 labels PADTXT text
 variants *
 labels PADPIN port

 templayer boundary BOUND,STDCELL,PADCELL
 boundary

 layer comment LVSTEXT
 labels LVSTEXT text

 layer comment TTEXT
 labels TTEXT text

 layer fillblock  FILLOBSM1,FILLOBSM2,FILLOBSM3,FILLOBSM4
 labels FILLOBSM1,FILLOBSM2,FILLOBSM3,FILLOBSM4

 layer obsactive  FILLOBSFOM

# MOS Varactor

 layer var POLY
 and TAP
 and NSDM
 and NWELL
 and-not HVI
 and-not HVTP
 # NOTE:  Else forms a varactor that is not in the vendor netlist.
 and-not COREID
 labels POLY

 layer varhvt POLY
 and TAP
 and NSDM
 and NWELL
 and-not HVI
 and HVTP
 labels POLY

 layer mvvar POLY
 and TAP
 and NSDM
 and NWELL
 and HVI
 labels POLY

 calma NWELL 64 20
 calma DIFF 65 20
 calma DNWELL 64 18
 calma PWRES 64 13
 calma TAP  65 44
 # LVTN
 calma LVTN 125 44
 # HVTR
 calma HVTR 18 20
 # HVTP
 calma HVTP 78 44
 # SONOS (TUNM)
 calma SONOS 80 20
 # NSDM (NPLUS)
 calma NSDM 93 44
 # PSDM (PPLUS)
 calma PSDM 94 20
 # HVI (THKOX)
 calma HVI 75 20
 # NPC
 calma NPC 95 20
 # P+ POLY MASK
 calma RPM 86 20
 calma URPM 79 20
 calma LDNTM 11 44
 calma HVNTM 125 20
 # Poly resistor ID mark
 calma POLYRES 66 13
 # Diffusion resistor ID mark
 calma DIFFRES 65 13
 calma POLY 66 20
 calma POLYMOD 66 83
 # 3.3V native FET ID mark
 calma LVID 81 60
 # Diode ID mark
 calma DIODE 81 23
 # Bipolar NPN mark
 calma NPNID 82 20
 # Bipolar PNP mark
 calma PNPID 82 44
 # Capacitor ID
 calma CAPID 82 64
 # Core area ID mark
 calma COREID 81 2
 # Standard cell ID mark
 calma STDCELL 81 4
 # Padframe cell ID mark
 calma PADCELL 81 3
 # Seal ring ID mark
 calma SEALID 81 1
 # Low tap density ID mark
 calma LOWTAPDENSITY 81 14
 # ESD area ID
 calma ESDID 81 19
 calma OUTLINE 236 0
 
 # LICON
 calma CONT 66 44
 calma LI   67 20
 calma MCON 67 44

 calma MET1 68 20
 calma VIA1 68 44
 calma MET2 69 20
 calma VIA2 69 44
 calma MET3 70 20
#ifdef METAL5
 calma VIA3 70 44
 calma MET4 71 20
 calma VIA4 71 44
 calma MET5 72 20
#endif
#ifdef REDISTRIBUTION
 calma RDL 74 20
#endif
 calma GLASS 76 20

 calma SUBTXT  64 59
 calma PADTXT  76 5
 calma DIFFTXT 65 6
 calma TAPTXT  65 5
 calma WELLTXT  64 5
 calma LITXT 67 5
 calma POLYTXT 66 5
 calma MET1TXT 68 5
 calma MET2TXT 69 5
 calma MET3TXT 70 5
#ifdef METAL5
 calma MET4TXT 71 5
 calma MET5TXT 72 5
#endif
#ifdef REDISTRIBUTION
 calma RDLTXT 74 5
#endif

 calma LIRES 67 13
 calma MET1RES 68 13
 calma MET2RES 69 13
 calma MET3RES 70 13
#ifdef METAL5
 calma MET4RES 71 13
 calma MET5RES 72 13
#endif

 calma LIFILL   56 28
 calma MET1FILL 36 28
 calma MET2FILL 41 28
 calma MET3FILL 34 28
#ifdef METAL5
 calma MET4FILL 51 28
 calma MET5FILL 59 28
#endif

 calma POLYSHORT 66 15
 calma LISHORT 67 15
 calma MET1SHORT 68 15
 calma MET2SHORT 69 15
 calma MET3SHORT 70 15
#ifdef METAL5
 calma MET4SHORT 71 15
 calma MET5SHORT 72 15
#endif

 calma SUBPIN 122 16
 calma PADPIN 76 16
 calma DIFFPIN 65 16
 calma POLYPIN 66 16
 calma WELLPIN 64 16
 calma LIPIN 67 16
 calma MET1PIN 68 16
 calma MET2PIN 69 16
 calma MET3PIN 70 16
#ifdef METAL5
 calma MET4PIN 71 16
 calma MET5PIN 72 16
#endif
#ifdef REDISTRIBUTION
 calma RDLPIN 74 16
#endif

 calma BOUND 235 4

 calma LVSTEXT 83 44

#ifdef (MIM)
 calma CAPM 89 44
 calma CAPM2 97 44
#endif (MIM)

 calma FILLOBSM1  62  24
 calma FILLOBSM2  105 52
 calma FILLOBSM3  107 24
 calma FILLOBSM4  112  4
 calma FILLOBSFOM  22 24
 calma FILLOBSPOLY 33 24

 calma FOMFILL	  23  28
 calma POLYFILL	  28  28
 calma LIFILL	  56  28
 calma MET1FILL	  36  28
 calma MET2FILL	  41  28
 calma MET3FILL	  34  28
 calma MET4FILL	  51  28
 calma MET5FILL	  59  28

#-----------------------------------------------------------------------

style  rdlimport
 # This style is for reading shapes generated with the RDL layers

 scalefactor 10 nanometers
 gridlimit 5

 options ignore-unknown-layer-labels no-reconnect-labels

 layer mrdl RDL
 layer mrdlc RDLC

 calma RDL 10 0
 calma RDLC 20 0

end

#-----------------------------------------------------
# Digital flow maze router cost parameters
#-----------------------------------------------------

mzrouter
end

#-----------------------------------------------------
# Vendor DRC rules
#-----------------------------------------------------

drc

 style drc variants (fast),(full),(routing)
 scalefactor 10 
 cifstyle drc

 variants (fast),(full)

#-----------------------------
# DNWELL
#-----------------------------

 width dnwell 3000 "Deep N-well width < %d (dnwell.2)"
 spacing dnwell dnwell 6300 touching_ok "Deep N-well spacing < %d (dnwell.3)"
 spacing dnwell allnwell 4500 surround_ok \
	"Deep N-well spacing to N-well < %d (nwell.7)"

 variants (full)
 cifmaxwidth nwell_missing 0 bend_illegal \
	"N-well overlap of Deep N-well < 0.4um outside, 1.03um inside (nwell.5a, 7)"
 cifmaxwidth dnwell_missing 0 bend_illegal \
	"SONOS nFET must be in Deep N-well (tunm.6a)"

 cifmaxwidth pdiff_crosses_dnwell 0 bend_illegal \
	"P+ diff cannot straddle Deep N-well (dnwell.5)"
 variants (fast),(full)

#-----------------------------
# NWELL
#-----------------------------

 width allnwell 840 "N-well width < %d (nwell.1)"
 spacing allnwell allnwell 1270 touching_ok "N-well spacing < %d (nwell.2a)"

 variants (full)
 cifmaxwidth nwell_missing_tap 0 bend_illegal \
	"All nwells must contain metal-connected N+ taps (nwell.4)"

 cifspacing mvnwell lvnwell 2000 touching_illegal \
	"Spacing of HV nwell to LV nwell < 2.0um (nwell.8)"
 cifspacing mvnwell mvnwell 2000 touching_ok \
	"Spacing of HV nwell to HV nwell < 2.0um (nwell.8)"
 variants (fast),(full)

#-----------------------------
# DIFF
#-----------------------------

 width *ndiff,nfet,scnfet,npd,npass,*nsd,*ndiode,ndiffres,*pdiff,pfet,scpfet,scpfethvt,ppu,*psd,*pdiode,pdiffres,fomfill \
	150 "Diffusion width < %d (diff/tap.1)"
 width *mvndiff,mvnfet,mvnfetesd,mvnnfet,nnfet,*mvndiode,*nndiode,mvndiffres,*mvpdiff,mvpfet,mvpfetesd,*mvpdiode,mvpdiffres 290 \
	"MV Diffusion width < %d (diff/tap.14)"

 width *mvnsd,*mvpsd 150 "MV Tap width < %d (diff/tap.1)"
 extend *mvpsd *mvndiff 700 "MV Butting tap length < %d (diff/tap.16)"
 extend *mvnsd *mvpdiff 700 "MV Butting tap length < %d (diff/tap.16)"
 extend *psd *ndiff 290 "Butting tap length < %d (diff/tap.4)"
 extend *nsd *pdiff 290 "Butting tap length < %d (diff/tap.4)"
 width mvpdiffres 150 "MV P-Diffusion resistor width < %d (diff/tap.14a)"
 spacing alldifflv,var,varhvt,fomfill alldifflv,var,varhvt,fomfill 270 touching_ok \
	"Diffusion spacing < %d (diff/tap.3)"
 spacing alldiffmvnontap,mvvar alldiffmvnontap,mvvar 300 touching_ok \
	"MV Diffusion spacing < %d (diff/tap.15a)"
 spacing alldiffmv *mvnsd,*mvpsd 270 touching_ok \
	"MV Diffusion to MV tap spacing < %d (diff/tap.3)"
 spacing *mvndiff,mvnfet,mvnfetesd,mvnnfet,nnfet,*mvndiode,*nndiode,mvndiffres,mvvar *mvpsd 370 \
	touching_ok "MV P-Diffusion to MV N-tap spacing < %d (diff/tap.15b)"
 spacing *mvnsd,*mvpdiff,mvpfet,mvpfetesd,mvvar,*mvpdiode *mvpsd,*psd 760 touching_illegal \
	"MV Diffusion in N-well to P-tap spacing < %d (diff/tap.20 + diff/tap.17,19)"
 spacing *ndiff,*ndiode,nfet allnwell 340 touching_illegal \
	"N-Diffusion spacing to N-well < %d (diff/tap.9)"
 spacing *mvndiff,*mvndiode,mvnfet,mvnnfet,nnfet allnwell 340 touching_illegal \
	"N-Diffusion spacing to N-well < %d (diff/tap.9)"
 spacing *psd allnwell 130 touching_illegal \
	"P-tap spacing to N-well < %d (diff/tap.11)"
 spacing *mvpsd allnwell 130 touching_illegal \
	"P-tap spacing to N-well < %d (diff/tap.11)"
 surround *nsd allnwell 180 absence_illegal \
	"N-well overlap of N-tap < %d (diff/tap.10)"
 surround *mvnsd allnwell 330 absence_illegal \
	"N-well overlap of MV N-tap < %d (diff/tap.19)"
 surround *pdiff,*pdiode,pfet,scpfet,ppu allnwell 180 absence_illegal \
	"N-well overlap of P-Diffusion < %d (diff/tap.8)"
 surround *mvpdiff,*mvpdiode,mvpfet,mvpfetesd allnwell 330 absence_illegal \
	"N-well overlap of P-Diffusion < %d (diff/tap.17)"
 surround mvvar allnwell 560 absence_illegal \
	"N-well overlap of MV varactor < %d (lvtn.10 + lvtn.4b)"
 spacing *mvndiode *mvndiode 1070 touching_ok \
	"MV N-diode spacing < %d (hvntm.2 + 2 * hvntm.3)"

variants (full)
 cifspacing allmvdiffnowell lvnwell 825 touching_illegal \
	"MV diffusion to LV nwell spacing < %d (hvi.5 + nsd/psd.5)"
variants (fast),(full)

 spacing allnfets allpactivenonfet 270 touching_illegal \
	"nFET cannot abut P-diffusion (diff/tap.3)"
 spacing allpfets allnactivenonfet 270 touching_illegal \
	"pFET cannot abut N-diffusion (diff/tap.3)"

 # Butting junction rules
 edge4way (*psd)/a ~(*ndiff,*psd)/a 125 ~(*ndiff)/a (*ndiff)/a 125 \
	"N-Diffusion to P-tap spacing < %d across butted junction (psd.5b)"
 edge4way (*ndiff)/a ~(*ndiff,*psd)/a 125 ~(*psd)/a (*psd)/a 125 \
	"N-Diffusion to P-tap spacing < %d across butted junction (psd.5a)"
 edge4way (*nsd)/a ~(*pdiff,*nsd)/a 125 ~(*pdiff)/a (*pdiff)/a 125 \
	"P-Diffusion to N-tap spacing < %d across butted junction (nsd.5b)"
 edge4way (*pdiff)/a ~(*pdiff,*nsd)/a 125 ~(*nsd)/a (*nsd)/a 125 \
	"P-Diffusion to N-tap spacing < %d across butted junction (nsd.5a)"

 edge4way (*mvpsd)/a ~(*mvndiff,*mvpsd)/a 125 ~(*mvndiff)/a (*mvndiff)/a 125 \
	"MV N-Diffusion to MV P-tap spacing < %d across butted junction (psd.5b)"
 edge4way (*mvndiff)/a ~(*mvndiff,*mvpsd)/a 125 ~(*mvpsd)/a (*mvpsd)/a 125 \
	"MV N-Diffusion to MV P-tap spacing < %d across butted junction (psd.5a)"
 edge4way (*mvnsd)/a ~(*mvpdiff,*mvnsd)/a 125 ~(*mvpdiff)/a (*mvpdiff)/a 125 \
	"MV P-Diffusion to MV N-tap spacing < %d across butted junction (nsd.5b)"
 edge4way (*mvpdiff)/a ~(*mvpdiff,*mvnsd)/a 125 ~(*mvnsd)/a (*mvnsd)/a 125 \
	"MV P-Diffusion to MV N-tap spacing < %d across butted junction (nsd.5a)"

 # Sandwiched butting junction restrictions
 edge4way (*pdiff)/a (*nsd)/a 400 ~(*pdiff)/a 0 0 "NSDM width < %d (diff/tap.5)"
 edge4way (*ndiff)/a (*psd)/a 400 ~(*ndiff)/a 0 0 "PSDM width < %d (diff/tap.5)"

 area  *nsd,*mvnsd 70110 150 "N-tap minimum area < 0.07011um^2 (nsd.10b)"
 area  *psd,*mvpsd 70110 150 "P-tap minimum area < 0.07011um^2 (psd.10b)"

 angles allactive 90 "Only 90 degree angles permitted on diff and tap (x.2)"

 variants (full)
 cifmaxwidth tap_missing_licon 0 bend_illegal "All taps must be contacted (licon.16)"

 # Latchup rules
 cifmaxwidth ptap_missing 0 bend_illegal \
	"N-diff distance to P-tap must be < 15.0um (LU.2)"
 cifmaxwidth dptap_missing 0 bend_illegal \
	"N-diff distance to P-tap in deep nwell.must be < 15.0um (LU.2.1)"
 cifmaxwidth ntap_missing 0 bend_illegal \
	"P-diff distance to N-tap must be < 15.0um (LU.3)"

 variants (fast),(full)

#-----------------------------
# POLY
#-----------------------------

 width allpoly,polyfill 150 "poly width < %d (poly.1a)"
 spacing allpoly,polyfill allpoly,polyfill 210 touching_ok "poly spacing < %d (poly.2)"

 spacing allpolynonfet,polyfill \
	*ndiff,*mvndiff,*ndiode,*nndiode,ndiffres,*ndiodelvt,*pdiff,*mvpdiff,*pdiode,pdiffres,*pdiodelvt,*pdiodehvt \
	75 corner_ok allfets \
	"poly spacing to Diffusion < %d (poly.4)"
 spacing npres *nsd 480 touching_illegal \
	"poly resistor spacing to N-tap < %d (poly.9)"
 overhang *ndiff,rndiff nfet,scnfet,npd,npass 250 "N-Diffusion overhang of nFET < %d (poly.7)"
 overhang *mvndiff,mvrndiff mvnfet,mvnnfet,nnfet 250 \
	"N-Diffusion overhang of nFET < %d (poly.7)"
 overhang *pdiff,rpdiff pfet,scpfet,ppu 250 "P-Diffusion overhang of pmos < %d (poly.7)"
 overhang *mvpdiff,mvrpdiff mvpfet,mvpfetesd 250 "P-Diffusion overhang of pmos < %d (poly.7)"
 overhang *poly allfetsstd,allfetsspecial 130 "poly overhang of transistor < %d (poly.8)"
 overhang *poly allfetscore 110 "poly overhang of SRAM core transistor < %d (poly.8)"
 rect_only allfets "No bends in transistors (poly.11)"
 rect_only xhrpoly,uhrpoly "No bends in poly resistors (poly.11)"
 extend  xpc/a xhrpoly,uhrpoly 2160 \
 	"poly contact extends poly resistor by < %d (licon.1c + li.5)"
 spacing xhrpoly,uhrpoly,xpc xhrpoly,uhrpoly,xpc 1240 touching_illegal \
	"Distance between precision resistors < %d (rpm.2 + 2 * rpm.3)"

 spacing xhrpoly,uhrpoly,xpc allndifflv,allndiffmv 780 touching_illegal \
	"Distance from precision resistor to N+ diffusion < %d (rpm.3 + rpm.6 + nsd.5a)"
 spacing xhrpoly,uhrpoly,xpc *poly 400 touching_illegal \
	"Distance from precision resistor to unrelated poly < %d (rpm.3 + rpm.7)"
 spacing xhrpoly,uhrpoly,xpc allndiffmvnontap 830 touching_illegal \
	"Distance from precision resistor to MV N+ diffusion < %d (rpm.3 + rpm.9)"

 angles allpoly,polyfill 90 "Only 90 degree angles permitted on poly (x.2)"

#--------------------------------------------------------------------
# HVTP
#--------------------------------------------------------------------

 spacing pfethvt,pdiodehvt,varactorhvt pfet,ppu,scpfet,mvpfet,mvpfetesd,pfetlvt,pfetmvt \
		360 touching_illegal \
		"Min. spacing between pFET and HVTP < %d (hvtp.4)"

 spacing pfethvt,pdiodehvt,varactorhvt varactor 360 touching_illegal \
		"Min. spacing between varactor and HVTP < %d (hvtp.4 + varac.3)"

#--------------------------------------------------------------------
# LVTN
#--------------------------------------------------------------------

 spacing pfetlvt,nfetlvt,pdiodelvt,ndiodelvt \
		allfetsnolvt 360 touching_illegal \
		"Min. spacing between FET and LVTN < %d (lvtn.3a)"

 spacing pfetlvt,nfetlvt,pdiodelvt,ndiodelvt scpfethvt,pfethvt,pdiodehvt,varactorhvt \
		740 touching_illegal \
		"Min. spacing between LVTN and HVTP < %d (lvtn.9)"

 # Spacing across S/D direction requires edge rule
 edge4way allfetsnolvt allactivenonfet 415 \
	~(pfetlvt,nfetlvt,pdiodelvt,ndiodelvt)/a allfetsnolvt 415 \
	"Min. spacing between FET and LVTN in S/D direction < %d (lvtn.3b)"

#--------------------------------------------------------------------
# NPC (Nitride poly Cut)
#--------------------------------------------------------------------

# Layer NPC is defined automatically around poly contacts (grow 0.1um)

#--------------------------------------------------------------------
# CONT (LICON, contact between poly/diff and LI)
#--------------------------------------------------------------------

 width ndc/li 170 "N-diffusion contact width < %d (licon.1)"
 width nsc/li 170 "N-tap contact width     < %d (licon.1)"
 width pdc/li 170 "P-diffusion contact width < %d (licon.1)"
 width psc/li 170 "P-tap contact width     < %d (licon.1)"
 width ndic/li 170 "N-diode contact width < %d (licon.1)"
 width pdic/li 170 "P-diode contact width < %d (licon.1)"
 width pc/li  170 "poly contact width        < %d (licon.1)"

 width xpc/li  350 "poly resistor contact width < %d (licon.1b + 2 * li.5)"
 area  xpc/li  700000 350 "poly resistor contact length < 2.0um (licon.1c)"
 area allli,*obsli 56100 170 "Local interconnect minimum area < %a (li.6)"

 width mvndc/li 170 "N-diffusion contact width < %d (licon.1)"
 width mvnsc/li 170 "N-tap contact width     < %d (licon.1)"
 width mvpdc/li 170 "P-diffusion contact width < %d (licon.1)"
 width mvpsc/li 170 "P-tap contact width     < %d (licon.1)"
 width mvndic/li 170 "N-diode contact width < %d (licon.1)"
 width mvpdic/li 170 "P-diode contact width < %d (licon.1)"

 spacing allpdiffcont allndiffcont 170 touching_illegal \
	"Diffusion contact spacing < %d (licon.2)"
 spacing allndiffcont allndiffcont 170 touching_ok \
	"Diffusion contact spacing < %d (licon.2)"
 spacing allpdiffcont allpdiffcont 170 touching_ok \
	"Diffusion contact spacing < %d (licon.2)"
 spacing pc pc 170 touching_ok "Poly1 contact spacing < %d (licon.2)"

 spacing pc alldiff 190 touching_illegal \
	"poly contact spacing to diffusion < %d (licon.14)"
 spacing pc allpdifflv,allpdiffmv 235 touching_illegal \
	"poly contact spacing to P-diffusion < %d (licon.9 + psdm.5a)"

 spacing ndc,pdc nfet,nfetlvt,pfet,pfethvt,pfetlvt,pfetmvt 55 touching_illegal \
	"Diffusion contact to gate < %d (licon.11)"
 spacing ndc,pdc scnfet,scpfet,scpfethvt 50 touching_illegal \
	"Diffusion contact to standard cell gate < %d (licon.11)"
 spacing ndc,pdc npd,npass,ppu 40 touching_illegal \
	"Diffusion contact to SRAM gate < %d (licon.11)"
 spacing mvndc,mvpdc mvnfet,mvnfetesd,mvnnfet,nnfet,mvpfet,mvpfetesd 55 touching_illegal \
	"Diffusion contact to gate < %d (licon.11)"
 spacing nsc varactor,varhvt 250 touching_illegal \
	"Diffusion contact to varactor gate < %d (licon.10)"
 spacing mvnsc mvvar 250 touching_illegal \
	"Diffusion contact to varactor gate < %d (licon.10)"

 surround ndc/a *ndiff,nfet,scnfet,npd,npass,nfetlvt,rnd 40 absence_illegal \
	"N-diffusion overlap of N-diffusion contact < %d (licon.5a)"
 surround pdc/a *pdiff,pfet,scpfet,scpfethvt,ppu,pfethvt,pfetmvt,pfetlvt,rpd \
	40 absence_illegal \
	"P-diffusion overlap of P-diffusion contact < %d (licon.5a)"
 surround ndic/a *ndi 40 absence_illegal \
	"N-diode overlap of N-diode contact < %d (licon.5a)"
 surround pdic/a *pdi 40 absence_illegal \
	"P-diode overlap of N-diode contact < %d (licon.5a)"

 spacing psc/a allnactivenontap 60 touching_illegal \
	"Min. space between P-tap contact and butting N diffusion < %d (licon.5b)"
 spacing nsc/a allpactivenontap 60 touching_illegal \
	"Min. space between N-tap contact and butting P diffusion < %d (licon.5b)"

 surround ndc/a *ndiff,nfet,scnfet,npd,npass,nfetlvt,rnd 60 directional \
	"N-diffusion overlap of N-diffusion contact < %d in one direction (licon.5c)"
 surround pdc/a *pdiff,pfet,scpfet,scpfethvt,ppu,pfethvt,pfetmvt,pfetlvt,rpd \
	 60 directional \
	"P-diffusion overlap of P-diffusion contact < %d in one direction (licon.5c)"
 surround ndic/a *ndi 60 directional \
	"N-diode overlap of N-diode contact < %d in one direction (licon.5c)"
 surround pdic/a *pdi 60 directional \
	"P-diode overlap of N-diode contact < %d in one direction (licon.5c)"

 surround nsc/a *nsd 120 directional \
	"N-tap overlap of N-tap contact < %d in one direction (licon.7)"
 surround psc/a *psd 120 directional \
	"P-tap overlap of P-tap contact < %d in one direction (licon.7)"

 surround mvndc/a *mvndiff,mvnfet,mvnfetesd,mvrnd 40 absence_illegal \
	"N-diffusion overlap of N-diffusion contact < %d (licon.5a)"
 surround mvpdc/a *mvpdiff,mvpfet,mvpfetesd,mvrpd 40 absence_illegal \
	"P-diffusion overlap of P-diffusion contact < %d (licon.5a)"
 surround mvndic/a *mvndi 40 absence_illegal \
	"N-diode overlap of N-diode contact < %d (licon.5a)"
 surround mvpdic/a *mvpdi 40 absence_illegal \
	"P-diode overlap of N-diode contact < %d (licon.5a)"

 spacing mvpsc/a allndiffmvnontap 60 touching_illegal \
	"Min. space between P-tap contact and butting N diffusion < %d (licon.5b)"
 spacing mvnsc/a allpdiffmvnontap 60 touching_illegal \
	"Min. space between N-tap contact and butting P diffusion < %d (licon.5b)"

 surround mvndc/a *mvndiff,mvnfet,mvnfetesd,mvrnd 60 directional \
	"N-diffusion overlap of N-diffusion contact < %d in one direction (licon.5c)"
 surround mvpdc/a *mvpdiff,mvpfet,mvpfetesd,mvrpd 60 directional \
	"P-diffusion overlap of P-diffusion contact < %d in one direction (licon.5c)"
 surround mvndic/a *mvndi 60 directional \
	"N-diode overlap of N-diode contact < %d in one direction (licon.5c)"
 surround mvpdic/a *mvpdi 60 directional \
	"P-diode overlap of N-diode contact < %d in one direction (licon.5c)"

 surround mvnsc/a *mvnsd 120 directional \
	"N-tap overlap of N-tap contact < %d in one direction (licon.7)"
 surround mvpsc/a *mvpsd 120 directional \
	"P-tap overlap of P-tap contact < %d in one direction (licon.7)"

 surround pc/a *poly,mrp1,xhrpoly,uhrpoly 50 absence_illegal \
	"poly overlap of poly contact < %d (licon.8)"
 surround pc/a *poly,mrp1,xhrpoly,uhrpoly 80 directional \
	"poly overlap of poly contact < %d in one direction (licon.8a)"

 exact_overlap (allcont)/a

#-------------------------------------------------------------
# LI - Local interconnect layer
#-------------------------------------------------------------

variants *

 width *li 170 "Local interconnect width < %d (li.1)"
 width rli 290 "Local interconnect width < %d (li.7)"

 spacing *locali,rli *locali,rli,*obsli 170 touching_ok  \
	"Local interconnect spacing < %d (li.3)"

 # Local interconnect in core (SRAM) cells has more relaxed rules.  There are
 # no special layers for the contacts in core cells, so they must be included
 # in the rule.
 width coreli,pc,ndc,nsc,pdc,psc,allli,*obsli 140 \
	"Core local interconnect width < %d (li.c1)"

 spacing coreli,pc,ndc,nsc,pdc,psc,mcon allli,*obsli 140 touching_ok \
	"Core local interconnect spacing < %d (li.c2)"

 surround pc/li *li,coreli 80 directional \
	"Local interconnect overlap of poly contact < %d in one direction (li.5)"

 surround ndc/li,nsc/li,pdc/li,psc/li,ndic/li,pdic/li,mvndc/li,mvnsc/li,mvpdc/li,mvpsc/li,mvndic/li,mvpdic/li \
	*li,rli,coreli 80 directional \
	"Local interconnect overlap of diffusion contact < %d in one direction (li.5)"

 area allli,*obsli,coreli 56100 170 "Local interconnect minimum area < %a (li.6)"

 angles *locali,rli 90 "Only 90 degree angles permitted on local interconnect (x.2)"
 angles coreli 45 \
	"Only 45 degree angles permitted on local interconnect in SRAM cell (x.2)"

#-------------------------------------------------------------
# MCON - Contact between local interconnect and metal1
#-------------------------------------------------------------

 width mcon/m1 170 "mcon.width < %d (mcon.1)"
 spacing mcon/m1 mcon/m1,obsmcon/m1 190 touching_ok "mcon.spacing < %d (mcon.2)"

 exact_overlap mcon/li

#-------------------------------------------------------------
# METAL1 -
#-------------------------------------------------------------

 width *m1,rm1 140 "Metal1 width < %d (met1.1)"
 spacing allm1,m1fill allm1,*obsm1,m1fill 140 touching_ok "Metal1 spacing < %d (met1.2)"
 area allm1,*obsm1 83000 140 "Metal1 minimum area < %a (met1.6)"

 surround mcon/m1 *met1 30 absence_illegal \
	"Metal1 overlap of local interconnect contact < %d (met1.4)"
 surround mcon/m1 *met1 60 directional \
	"Metal1 overlap of local interconnect contact < %d in one direction (met1.5)"

 angles allm1,m1fill 45 "Only 45 and 90 degree angles permitted on metal1 (x.3a)"

variants (fast),(full)
 widespacing allm1 3005 allm1,*obsm1,m1fill 280 touching_ok \
	"Metal1 > 3um spacing to unrelated m1 < %d (met1.3b)"
 widespacing *obsm1 3005 allm1 280 touching_ok \
	"Metal1 > 3um spacing to unrelated m1 < %d (met1.3b)"

variants (full)
 cifmaxwidth m1_hole_empty 0 bend_illegal \
	"Min area of metal1 holes > 0.14um^2 (met1.7)"

 cifspacing m1_large_halo m1_large_halo 280 touching_ok \
	"Spacing of metal1 features attached to and within 0.28um of large metal1 < %d (met1.3a)"
variants *

#--------------------------------------------------
# VIA1
#--------------------------------------------------

 width v1/m1 260 "Via1 width < %d (via.1a + 2 * via.4a)"
 spacing v1 v1 60 touching_ok "Via1 spacing < %d (via.2 - 2 * via.4a)"
 surround v1/m1 *m1 30 directional \
	"Metal1 overlap of Via1 < %d in one direction (via.5a - via.4a)"
 surround v1/m2 *m2 30 directional \
	"Metal2 overlap of Via1 < %d in one direction (met2.5 - met2.4)"

 exact_overlap v1/m1

#--------------------------------------------------
# METAL2 - 
#--------------------------------------------------

 width allm2,m2fill 140 "Metal2 width < %d (met2.1)"
 spacing allm2  allm2,obsm2,m2fill 140 touching_ok       "Metal2 spacing < %d (met2.2)"
 area allm2,obsm2 67600 140 "Metal2 minimum area < %a (met2.6)"

 angles allm2 45 "Only 45 and 90 degree angles permitted on metal2 (x.3a)"

variants (fast),(full)
 widespacing allm2 3005 allm2,obsm2,m2fill  280 touching_ok \
	"Metal2 > 3um spacing to unrelated m2 < %d (met2.3b)"
 widespacing obsm2 3005 allm2  280 touching_ok \
	"Metal2 > 3um spacing to unrelated m2 < %d (met2.3b)"

variants (full)
 cifmaxwidth m2_hole_empty 0 bend_illegal \
	"Min area of metal2 holes > 0.14um^2 (met2.7)"

 cifspacing m2_large_halo m2_large_halo 280 touching_ok \
	"Spacing of metal2 features attached to and within 0.28um of large metal2 < %d (met2.3a)"
variants *

#--------------------------------------------------
# VIA2
#--------------------------------------------------

 width v2/m2 280 "via2.width < %d (via2.1a + 2 * via2.4)"

 spacing v2 v2 120 touching_ok "via2.spacing < 0.24um (via2.2 - 2 * via2.4)"

 surround v2/m2 *m2 45 directional \
	"Metal2 overlap of via2.< %d in one direction (via2.4a - via2.4)"
 surround v2/m3 *m3 25 absence_illegal "Metal3 overlap of via2.< %d (met3.4)"

 exact_overlap v2/m2

#--------------------------------------------------
# METAL3 - 
#--------------------------------------------------

 width allm3,m3fill 300 "Metal3 width < %d (met3.1)"
 spacing allm3 allm3,obsm3,m3fill  300 touching_ok "Metal3 spacing < %d (met3.2)"
 area allm3,obsm3 240000 300 "Metal3 minimum area < %a (met3.6)"

 angles allm3 45 "Only 45 and 90 degree angles permitted on metal3 (x.3a)"

variants (fast),(full)
 widespacing allm3,m3fill 3005 allm3,obsm3  400 touching_ok \
	"Metal3 > 3um spacing to unrelated m3 < %d (met3.3d)"
 widespacing obsm3 3005 allm3  400 touching_ok \
	"Metal3 > 3um spacing to unrelated m3 < %d (met3.3d)"
variants (full)
 cifspacing m3_large_halo m3_large_halo 400 touching_ok \
	"Spacing of metal3 features attached to and within 0.40um of large metal3 < %d (met3.3c)"
variants *


#ifdef METAL5
#undef METAL5
#--------------------------------------------------
# VIA3 - Requires METAL5 Module
#--------------------------------------------------

 width v3/m3 320 "via3.width < %d (via3.1 + 2 * via3.4)"
 spacing v3 v3 80 touching_ok "via3.spacing < %d (via3.2 - 2 * via3.4)"
 surround v3/m3 *m3 30 directional \
	"Metal3 overlap of via3.in one direction < %d (via3.5 - via3.4)"
 surround v3/m4 *m4 5 absence_illegal \
	"Metal4 overlap of via3.< %d (met4.3 - via3.4)"

 exact_overlap v3/m3

#-----------------------------
# METAL4 - METAL4 Module
#-----------------------------

variants *

 width allm4,m4fill 300 "Metal4 width < %d (met4.1)"
 spacing allm4  allm4,obsm4,m4fill 300 touching_ok      "Metal4 spacing < %d (met4.2)"
 area allm4,obsm4 240000 300 "Metal4 minimum area < %a (met4.4a)"

 angles allm4 45 "Only 45 and 90 degree angles permitted on metal4 (x.3a)"

variants (fast),(full)
 widespacing allm4,m4fill 3005 allm4,obsm4  400 touching_ok \
	"Metal4 > 3um spacing to unrelated m4 < %d (met4.5b)"
 widespacing obsm4 3005 allm4  400 touching_ok \
	"Metal4 > 3um spacing to unrelated m4 < %d (met4.5b)"
variants (full)
 cifspacing m4_large_halo m4_large_halo 400 touching_ok \
	"Spacing of metal4 features attached to and within 0.40um of large metal4 < %d (met4.5a)"
variants *

#--------------------------------------------------
# VIA4 - Requires METAL5 Module
#--------------------------------------------------

 width v4/m4 1180 "via4.width < %d (via4.1 + 2 * via4.4)"
 spacing v4 v4 420 touching_ok "via4.spacing < %d (via4.2 - 2 * via4.4)"
 surround v4/m5 *m5 120 absence_illegal \
	"Metal5 overlap of via4.< %d (met5.3 - via4.4)"

 exact_overlap v4/m4

#-----------------------------
# METAL5 - METAL5 Module
#-----------------------------

 width allm5,m5fill 1600 "Metal5 width < %d (met5.1)"
 spacing allm5  allm5,obsm5,m5fill 1600 touching_ok "Metal5 spacing < %d (met5.2)"
 area allm5,obsm5 4000000 1600 "Metal5 minimum area < %a (met5.4)"

 angles allm5 45 "Only 45 and 90 degree angles permitted on metal5 (x.3a)"

#define METAL5
#endif (METAL5)

#ifdef REDISTRIBUTION

variants (full)

 width metrdl 10000 "RDL width < %d (rdl.1)"
 spacing metrdl metrdl 10000 touching_ok "RDL spacing < %d (rdl.2)"
 surround glass metrdl 10750 absence_ok "RDL must surround glass cut by %d (rdl.3)"
 spacing metrdl padl 19660 surround_ok "RDL spacing to unrelated pad < %d (rdl.6)"

variants (fast),(full)

#endif (REDISTRIBUTION)

#--------------------------------------------------
# NMOS, PMOS
#--------------------------------------------------

 edge4way *poly allfetsstd 420 allfets 0 0 \
	"Transistor width < %d (diff/tap.2)"
 edge4way *poly allfetsspecial 360 allfets 0 0 \
	"Transistor in standard cell width < %d (diff/tap.2)"
 edge4way *poly npass,npd,nsonos 210 allfets 0 0 \
	"N-Transistor in SRAM core width < %d (diff/tap.2)"
 edge4way *poly ppu 140 allfets 0 0 \
	"P-Transistor in SRAM core width < %d (diff/tap.2)"

 # Except:  Note that standard cells allow transistor width minimum 0.36um
 width pfetlvt 350 "LVT PMOS gate length < %d (poly.1b)"

 spacing allpolynonfet,polyfill *nsd 55 corner_ok var,varhvt,corenvar \
	"poly spacing to diffusion tap < %d (poly.5)"
 spacing allpolynonfet,polyfill *psd 55 corner_ok corepvar \
	"poly spacing to diffusion tap < %d (poly.5)"
 spacing allpolynonfet,polyfill *mvnsd 55 corner_ok mvvar \
	"poly spacing to diffusion tap < %d (poly.5)"
 spacing allpolynonfet,polyfill *mvpsd 55 touching_illegal \
	"poly spacing to diffusion tap < %d (poly.5)"

 edge4way *psd *ndiff 300 ~(nfet,npass,npd,scnfet,nfetlvt,nsonos)/a *psd 300 \
	"Butting P-tap spacing to NMOS gate < %d (poly.6)"
 edge4way *nsd *pdiff 300 ~(pfet,ppu,scpfet,scpfethvt,pfetlvt,pfetmvt)/a *nsd 300 \
	"Butting N-tap spacing to PMOS gate < %d (poly.6)"
 edge4way *mvpsd *mvndiff 300 ~(mvnfet,mvnfetesd,mvnnfet,nnfet)/a *mvpsd 300 \
	"Butting MV P-tap spacing to MV NMOS gate < %d (poly.6)"
 edge4way *mvnsd *mvpdiff 300 ~(mvpfet,mvpfetesd)/a *mvnsd 300 \
	"Butting MV N-tap spacing to MV PMOS gate < %d (poly.6)"

 # No LV FETs in HV diff
 spacing pfet,scpfet,scpfethvt,ppu,pfetlvt,pfetmvt,pfethvt,*pdiff *mvpdiff 360 touching_illegal \
	"LV P-diffusion to MV P-diffusion < %d (diff/tap.23 + diff/tap.22)"

 spacing nfet,scnfet,npd,npass,nfetlvt,varactor,varhvt,*ndiff *mvndiff 360 touching_illegal \
	"LV N-diffusion to MV N-diffusion < %d (diff/tap.23 + diff/tap.22)"

 # No HV FETs in LV diff
 spacing mvpfet,mvpfetesd,*mvpdiff *pdiff 360 touching_illegal \
	"MV P-diffusion to LV P-diffusion < %d (diff/tap.23 + diff/tap.22)"

 spacing mvnfet,mvnfetesd,mvvaractor,*mvndiff *ndiff 360 touching_illegal \
	"MV N-diffusion to LV N-diffusion < %d (diff/tap.23 + diff/tap.22)"

 # Minimum length of MV FETs.  Note that this is larger than the minimum
 # width (0.29um), so an edge rule is required

 edge4way mvndiff mvnfet,mvnfetesd 500 mvnfet,mvnfetesd 0 0 \
	"MV NMOS minimum length < %d (poly.13)"

 edge4way mvnsd mvvaractor 500 mvvaractor 0 0 \
	"MV Varactor minimum length < %d (poly.13)"

 edge4way mvpdiff mvpfet,mvpfetesd 500 mvpfet,mvpfetesd 0 0 \
	"MV PMOS minimum length < %d (poly.13)"

#--------------------------------------------------
# mrp1 (N+ poly resistor)
#--------------------------------------------------

  width mrp1 330 "mrp1 resistor width < %d (poly.3)"

#--------------------------------------------------
# xhrpoly (P+ poly resistor)
# uhrpoly (P+ poly resistor, 2kOhm/sq)
#--------------------------------------------------

  # NOTE: u/xhrpoly resistor requires discrete widths 0.35, 0.69, ... up to 1.27.
  width xhrpoly 350 "xhrpoly resistor width < %d (P+ poly.1a)"
  width uhrpoly 350 "uhrpoly resistor width < %d (P+ poly.1a)"

  spacing xhrpoly,uhrpoly,xpc alldiff 480 touching_illegal \
	"xhrpoly/uhrpoly resistor spacing to diffusion < %d (poly.9)"

  spacing mrp1,xhrpoly,uhrpoly,xpc allfets 480 touching_illegal \
	"Poly resistor spacing to poly < %d (poly.9)"

  spacing xhrpoly,uhrpoly,xpc *poly 480 touching_illegal \
	"Poly resistor spacing to poly < %d (poly.9)"

  spacing mrp1 *poly 480 touching_ok \
	"Poly resistor spacing to poly < %d (poly.9)"

  spacing mrp1,xhrpoly,uhrpoly,xpc alldiff 480 touching_illegal \
	"Poly resistor spacing to diffusion < %d (poly.9)"

#------------------------------------
# nsonos
#------------------------------------

variants (full)
  cifmaxwidth bbox_missing 0 bend_illegal \
	"SONOS transistor must be in cell with abutment box (tunm.8)"
variants (fast),(full)

#------------------------------------
# MOS Varactor device rules
#------------------------------------

 overhang *nsd var,varhvt 250 \
 "N-Tap overhang of Varactor < %d (var.4)"

 overhang *mvnsd mvvar 250 \
 "N-Tap overhang of Varactor < %d (var.4)"

 width var,varhvt,mvvar 180 "Varactor length < %d (var.1)"
 extend var,varhvt,mvvar *poly 1000 "Varactor width < %d (var.2)"

variants (full)
 cifmaxwidth var_poly_no_nwell 0 bend_illegal \
	"N-well overlap of varactor poly < 0.15um (varac.5)"

 cifmaxwidth pdiff_in_varactor_well 0 bend_illegal \
	"Varactor N-well must not contain P+ diffusion (varac.7)"
variants (fast),(full)

#ifdef MIM
#-----------------------------------------------------------
# MiM CAP (CAPM) - 
#-----------------------------------------------------------

 width *mimcap 1000 "MiM cap width < %d (capm.1)"
 spacing *mimcap *mimcap 840 touching_ok "MiM cap spacing < %d (capm.2a)"
 spacing *mimcap via3/m3 80 touching_illegal \
	"MiM cap spacing to via3 < %d (capm.5 - via3.4)"
 surround *mimcc *mimcap 80 absence_illegal \
	"MiM cap must surround MiM cap contact by %d (capm.4 - via3.4)"
 rect_only *mimcap "MiM cap must be rectangular (capm.7)

 surround *mimcap *metal3/m3 140 absence_illegal \
	"Metal3 must surround MiM cap by %d (capm.3)"
 spacing via2 *mimcap 100 touching_illegal \
	"MiM cap spacing to via2 < %d (capm.8 - via2.4)"
 spacing *mimcap *metal3/m3 500 surround_ok \
	"MiM cap spacing to unrelated metal3 < %d (capm.11)"

variants (full)
 cifspacing mim_bottom mim_bottom 1200 touching_ok \
	 "MiM cap bottom plate spacing < %d (capm.2b)"
variants (fast),(full)

 # MiM cap contact rules (VIA3)

 width mimcc/c1 320 "MiM cap contact width < %d (via3.1 + 2 * via3.4)"
 spacing mimcc mimcc 80 touching_ok "MiM cap contact spacing < %d (via3.2 - 2 * via3.4)"
 surround mimcc/m4 *m4 5 directional \
	"Metal4 overlap of MiM cap contact in one direction < %d (met4.3 - via3.4)"
 exact_overlap mimcc/c1

 width *mimcap2 1000 "MiM2 cap width < %d (cap2m.1)"
 spacing *mimcap2 *mimcap2 840 touching_ok "MiM2 cap spacing < %d (cap2m.2a)"
 spacing *mimcap2 via4/m4 10 touching_illegal \
	"MiM2 cap spacing to via4 < %d (cap2m.5 - via4.4)"
 surround *mim2cc *mimcap2 10 absence_illegal \
	"MiM2 cap must surround MiM cap 2 contact by %d (cap2m.4 - via4.4)"
 rect_only *mimcap2 "MiM2 cap must be rectangular (cap2m.7)

 surround *mimcap2 *metal4/m4 140 absence_illegal \
	"Metal4 must surround MiM2 cap by %d (cap2m.3)"
 spacing via3,mimcc *mimcap2 80 touching_illegal \
	"MiM2 cap spacing to via3 < %d (cap2m.8 - via3.4)"
 spacing *mimcap2 *metal4/m4 500 surround_ok \
	"MiM2 cap spacing to unrelated metal4 < %d (cap2m.11)"

variants (full)
 cifspacing mim2_bottom mim2_bottom 1200 touching_ok \
 	"MiM2 cap bottom plate spacing < %d (cap2m.2b)"
variants (fast),(full)

 # MiM cap contact rules (VIA4)

 width mim2cc/c2 1180 "MiM2 cap contact width < %d (via4.1 + 2 * via4.4)"
 spacing mim2cc mim2cc 420 touching_ok \
	"MiM2 cap contact spacing < %d (via4.2 - 2 * via4.4)"
 surround mim2cc/m5 *m5 120 absence_illegal \
	"Metal5 overlap of MiM2 cap contact < %d (met5.3 - via4.4)"
 exact_overlap mim2cc/c2

#endif (MIM)

#----------------------------
# HVNTM
#----------------------------
variants (full)
 cifspacing hvntm_generate hvntm_generate 700 touching_ok \
 	"HVNTM spacing < %d (hvntm.2)"
variants (fast),(full)

#----------------------------
# End DRC style
#----------------------------

end

#----------------------------
# LEF format definitions
#----------------------------

lef

 masterslice pwell  pwell PWELL substrate
 masterslice nwell  nwell NWELL

 routing li	li1 LI1 LI li

 routing m1	met1 MET1 m1
 routing m2	met2 MET2 m2
 routing m3	met3 MET3 m3
#ifdef METAL5
 routing m4	met4 MET4 m4
 routing m5	met5 MET5 m5
#endif (METAL5)
#ifdef REDISTRIBUTION
 routing mrdl	met6 MET6 m6 MRDL METRDL
#endif

 cut mcon  mcon MCON Mcon
 cut m2c  via via1 VIA VIA1 cont2 via12
 cut m3c  via2 VIA2 cont3 via23
#ifdef METAL5
 cut via3 via3 VIA3 cont4 via34
 cut via4 via4 VIA4 cont5 via45
#endif (METAL5)

 obs obsli   li1
 obs obsm1   met1
 obs obsm2   met2
 obs obsm3   met3

#ifdef METAL5
 obs obsm4   met4
 obs obsm5   met5
#endif (METAL5)
#ifdef REDISTRIBUTION
 obs obsmrdl met6
#endif

 # NOTE: obsmcon only used with li1, not obsli.
 obs obsmcon mcon

 # Vias on obstruction layers should be ignored, so cast to obstruction metal.
 obs obsm1   via
 obs obsm2   via2
#ifdef METAL5
 obs obsm3   via3
 obs obsm4   via4
#endif (METAL5)

end

#-----------------------------------------------------
# Device and Parasitic extraction
#-----------------------------------------------------


extract
 style ngspice variants (),(orig),(si)
 cscale 1
 # NOTE: SkyWater SPICE libraries use .option scale 1E6 so all
 # dimensions must be in units of microns in the extract file.
 # Use extract style "ngspice(si)" to override this and produce
 # a file with SI units for length/area.

 variants (),(orig)
 lambda  1E6
 variants (si)
 lambda 1.0
 variants *

 units	microns
 step   7
 sidehalo 2

 # NOTE:  MiM cap layers have been purposely put out of order,
 # may want to reconsider.

 planeorder dwell 	0
 planeorder well 	1
 planeorder active 	2
 planeorder locali 	3
 planeorder metal1 	4
 planeorder metal2 	5
 planeorder metal3 	6
#ifdef METAL5
 planeorder metal4 	7
 planeorder metal5 	8
#ifdef REDISTRIBUTION
 planeorder metali	9
 planeorder block      10
 planeorder comment    11
 planeorder cap1       12
 planeorder cap2       13
#else (!REDISTRIBUTION)
 planeorder block       9	
 planeorder comment    10
 planeorder cap1       11
 planeorder cap2       12
#endif (!REDISTRIBUTION)
#else (!METAL5)
#ifdef REDISTRIBUTION
 planeorder metali     7
 planeorder block      8
 planeorder comment    9
 planeorder cap1       10
 planeorder cap2       11
#else (!REDISTRIBUTION)
 planeorder block      7
 planeorder comment    8
 planeorder cap1       9
 planeorder cap2       10
#endif (!REDISTRIBUTION)
#endif (!METAL5)

 height	dnwell 	    -0.1    0.1
 height	nwell,pwell  0.0    0.2062
 height alldiff	     0.2062 0.12
 height fomfill	     0.2062 0.12
 height allpoly	     0.3262 0.18
 height polyfill     0.3262 0.18
 height alldiffcont  0.3262 0.61
 height pc	     0.5062 0.43
 height allli	     0.9361 0.10
 height mcon	     1.0361 0.34
 height allm1	     1.3761 0.36
 height m1fill	     1.3761 0.36
 height v1	     1.7361 0.27
 height allm2	     2.0061 0.36
 height m2fill	     1.3761 0.36
 height v2	     2.3661 0.42
 height allm3	     2.7861 0.845
 height m3fill	     1.3761 0.36
#ifdef METAL5
 height v3	     3.6311 0.39
 height allm4	     4.0211 0.845
 height m4fill	     1.3761 0.36
 height v4	     4.8661 0.505
 height allm5	     5.3711 1.26
 height m5fill	     1.3761 0.36
 height mimcap	     2.4661 0.2
 height mimcap2	     3.7311 0.2
 height mimcc	     2.6661 0.12
 height mim2cc	     3.9311 0.09
#ifdef REDISTRIBUTION
 height mrdlc	     6.6311 5.2523
 height mrdl	    11.8834 4.0
#endif (!REDISTRIBUTION)
#endif (!METAL5)

 # Antenna check parameters
 # Note that checks w/diode diffusion are not modeled
 model partial
 antenna poly sidewall 50 none
 antenna allcont surface 3 none
 antenna li sidewall 75 0 450
 antenna mcon surface 3 0 18
 antenna m1,m2,m3 sidewall 400 2600 400
 antenna v1 surface 3 0 18
 antenna v2 surface 6 0 36
#ifdef METAL5
 antenna m4,m5 sidewall 400 2600 400
 antenna v3,v4 surface 6 0 36
#endif (METAL5)

 tiedown alldiffnonfet

 substrate *ppdiff,*mvppdiff,space/w,pwell well $SUB -dnwell

# Layer resistance: Use document xp018-PDS-v4_2_1.pdf

# Resistances are in milliohms per square
# Optional 3rd argument is the corner adjustment fraction
# Device values come from trtc.cor (typical corner)
 resist (dnwell)/dwell          2200000
 resist (pwell)/well            3050000
 resist (nwell)/well            1700000
 resist (rpw)/well              3050000 0.5
 resist (*ndiff,nsd)/active 	 120000
 resist (*pdiff,*psd)/active	 197000
 resist (*mvndiff,mvnsd)/active  114000
 resist (*mvpdiff,*mvpsd)/active 191000

 resist ndiffres/active 	120000 0.5
 resist pdiffres/active 	197000 0.5
 resist mvndiffres/active 	114000 0.5
 resist mvpdiffres/active 	191000 0.5
 resist mrp1/active		 48200 0.5
 resist xhrpoly/active	        319800 0.5
 resist uhrpoly/active	       2000000 0.5

 resist (allpolynonres)/active   48200
 resist rmp/active   		 48200

 resist (allli)/locali		 12200
 resist (allm1)/metal1		   125
 resist (allm2)/metal2		   125
 resist (allm3)/metal3	            47
#ifdef METAL5
 resist (allm4)/metal4  	    47
 resist (allm5)/metal5  	    29
#endif (METAL5)
#ifdef REDISTRIBUTION
 resist mrdl/metali		     5
#endif (REDISTRIBUTION)

 contact ndc,nsc		 15000
 contact pdc,psc		 15000
 contact mvndc,mvnsc		 15000
 contact mvpdc,mvpsc	  	 15000
 contact pc			 15000
 contact mcon			152000
 contact m2c			  4500
 contact m3c			  3410
#ifdef METAL5
#ifdef MIM
 contact mimcc			  4500
 contact mim2cc			  3410
#endif (MIM)
 contact via3			  3410
 contact via4			   380
#endif (METAL5)
#ifdef REDISTRIBUTION
 contact mrdlc			     6
#endif (REDISTRIBUTION)

#-------------------------------------------------------------------------
# Parasitic capacitance values:  Use document (...)
#-------------------------------------------------------------------------
# This uses the new "default" definitions that determine the intervening
# planes from the planeorder stack, take care of the reflexive sideoverlap
# definitions, and generally clean up the section and make it more readable.
#
# Also uses "units microns" statement.  All values are taken from the
# document PEX/xRC/cap_models.  Fringe capacitance values are approximated.
# Units are aF/um^2 for area caps and aF/um for perimeter and sidewall caps.
#-------------------------------------------------------------------------
# Remember that device capacitances to substrate are taken care of by the
# models.  Thus, active and poly definitions ignore all "fet" types.
# fet types are excluded when computing parasitic capacitance to
# active from layers above them because poly is a shield; fet types are
# included for parasitics from layers above to poly.  Resistor types
# should be removed from all parasitic capacitance calculations, or else
# they just create floating caps.  Technically, the capacitance probably
# should be split between the two terminals.  Unsure of the correct model.
#-------------------------------------------------------------------------

#n-well
# NOTE:  This value not found in PEX files
defaultareacap     nwell well 120

#n-active 
# Rely on device models to capture *ndiff area cap
# Do not extract parasitics from resistors
# defaultareacap     allnactivenonfet active 790
# defaultperimeter   allnactivenonfet active 280

#p-active
# Rely on device models to capture *pdiff area cap
# Do not extract parasitics from resistors
# defaultareacap     allpactivenonfet active 810
# defaultperimeter   allpactivenonfet active 300

#poly
# Do not extract parasitics from resistors
# defaultsidewall    allpolynonfet active  22
# defaultareacap     allpolynonfet active  106
# defaultperimeter   allpolynonfet active   57

 defaultsidewall    *poly active  23
 defaultareacap     *poly active nwell,obswell,pwell well  106
 defaultperimeter   *poly active nwell,obswell,pwell well  55

#locali
 defaultsidewall    allli locali       33
 defaultareacap     allli locali nwell,obswell,pwell well  37
 defaultperimeter   allli locali nwell,obswell,pwell well  55
 defaultoverlap     allli locali nwell well 37

#locali->diff
 defaultoverlap     allli locali allactivenonfet active 37
 defaultsideoverlap allli locali allactivenonfet active 55

#locali->poly
 defaultoverlap     allli locali allpolynonres active 94
 defaultsideoverlap allli locali allpolynonres active 52
 defaultsideoverlap *poly active allli locali 25

#metal1
 defaultsidewall    allm1 metal1      45
 defaultareacap     allm1 metal1 nwell,obswell,pwell well  26
 defaultperimeter   allm1 metal1 nwell,obswell,pwell well  41
 defaultoverlap     allm1 metal1 nwell well 26

#metal1->diff
 defaultoverlap     allm1 metal1 allactivenonfet active 26
 defaultsideoverlap allm1 metal1 allactivenonfet active 41

#metal1->poly
 defaultoverlap     allm1 metal1 allpolynonres active 45
 defaultsideoverlap allm1 metal1 allpolynonres active 47
 defaultsideoverlap *poly active allm1 metal1 17

#metal1->locali
 defaultoverlap     allm1 metal1 allli locali 114
 defaultsideoverlap allm1 metal1 allli locali 59
 defaultsideoverlap allli locali allm1 metal1 35

#metal2
 defaultsidewall    allm2 metal2      50
 defaultareacap     allm2 metal2 nwell,obswell,pwell well 17
 defaultperimeter   allm2 metal2 nwell,obswell,pwell well 41
 defaultoverlap     allm2 metal2 nwell well 38

#metal2->diff
 defaultoverlap     allm2 metal2 allactivenonfet active 17
 defaultsideoverlap allm2 metal2 allactivenonfet active 41

#metal2->poly
 defaultoverlap     allm2 metal2 allpolynonres active 24
 defaultsideoverlap allm2 metal2 allpolynonres active 41
 defaultsideoverlap *poly active allm2 metal2 11

#metal2->locali
 defaultoverlap     allm2 metal2 allli locali 38
 defaultsideoverlap allm2 metal2 allli locali 46
 defaultsideoverlap allli locali allm2 metal2 22

#metal2->metal1
 defaultoverlap     allm2 metal2 allm1 metal1 134
 defaultsideoverlap allm2 metal2 allm1 metal1 67
 defaultsideoverlap allm1 metal1 allm2 metal2 48

#metal3
 defaultsidewall    allm3 metal3     63
 defaultoverlap     allm3 metal3 nwell well 12
 defaultareacap     allm3 metal3 nwell,obswell,pwell well 12
 defaultperimeter   allm3 metal3 nwell,obswell,pwell well 41

#metal3->diff
 defaultoverlap     allm3 metal3 allactive active 12
 defaultsideoverlap allm3 metal3 allactive active 41

#metal3->poly
 defaultoverlap     allm3 metal3 allpolynonres active 16
 defaultsideoverlap allm3 metal3 allpolynonres active 44
 defaultsideoverlap *poly active allm3 metal3 9

#metal3->locali
 defaultoverlap     allm3 metal3 allli locali 21
 defaultsideoverlap allm3 metal3 allli locali 47
 defaultsideoverlap allli locali allm3 metal3 15

#metal3->metal1
 defaultoverlap     allm3 metal3 allm1 metal1 35
 defaultsideoverlap allm3 metal3 allm1 metal1 55
 defaultsideoverlap allm1 metal1 allm3 metal3 27

#metal3->metal2
 defaultoverlap     allm3 metal3 allm2 metal2 86
 defaultsideoverlap allm3 metal3 allm2 metal2 70
 defaultsideoverlap allm2 metal2 allm3 metal3 44

#ifdef METAL5
#metal4
 defaultsidewall    allm4 metal4       67
# defaultareacap     alltopm metal4 well  6
 areacap     	    allm4/m4 8
 defaultoverlap     allm4 metal4 nwell well 8
 defaultperimeter   allm4 metal4 well  37

#metal4->diff
 defaultoverlap     allm4 metal4 allactivenonfet active 8
 defaultsideoverlap allm4 metal4 allactivenonfet active 37

#metal4->poly
 defaultoverlap     allm4 metal4 allpolynonres active 10
 defaultsideoverlap allm4 metal4 allpolynonres active 38
 defaultsideoverlap *poly active allm4 metal4 6

#metal4->locali
 defaultoverlap     allm4 metal4 allli locali 12
 defaultsideoverlap allm4 metal4 allli locali 40
 defaultsideoverlap allli locali allm4 metal4 10

#metal4->metal1
 defaultoverlap     allm4 metal4 allm1 metal1 15
 defaultsideoverlap allm4 metal4 allm1 metal1 43
 defaultsideoverlap allm1 metal1 allm4 metal4 16

#metal4->metal2
 defaultoverlap     allm4 metal4 allm2 metal2 20
 defaultsideoverlap allm4 metal4 allm2 metal2 46
 defaultsideoverlap allm2 metal2 allm4 metal4 22

#metal4->metal3
 defaultoverlap     allm4 metal4 allm3 metal3 84
 defaultsideoverlap allm4 metal4 allm3 metal3 71
 defaultsideoverlap allm3 metal3 allm4 metal4 43

#metal5
 defaultsidewall    allm5 metal5       127
# defaultareacap     allm5 metal5 well  6
 areacap     	    allm5/m5 6
 defaultoverlap     allm5 metal5 nwell well 6
 defaultperimeter   allm5 metal5 well  39

#metal5->diff
 defaultoverlap     allm5 metal5 allactivenonfet active 6
 defaultsideoverlap allm5 metal5 allactivenonfet active 39

#metal5->poly
 defaultoverlap     allm5 metal5 allpolynonres active 7
 defaultsideoverlap allm5 metal5 allpolynonres active 40
 defaultsideoverlap *poly active allm5 metal5 6

#metal5->locali
 defaultoverlap     allm5 metal5 allli locali 8
 defaultsideoverlap allm5 metal5 allli locali 41
 defaultsideoverlap allli locali allm5 metal5 8

#metal5->metal1
 defaultoverlap     allm5 metal5 allm1 metal1 9
 defaultsideoverlap allm5 metal5 allm1 metal1 43
 defaultsideoverlap allm1 metal1 allm5 metal5 12

#metal5->metal2
 defaultoverlap     allm5 metal5 allm2 metal2 11
 defaultsideoverlap allm5 metal5 allm2 metal2 46
 defaultsideoverlap allm2 metal2 allm5 metal5 16

#metal5->metal3
 defaultoverlap     allm5 metal5 allm3 metal3 20
 defaultsideoverlap allm5 metal5 allm3 metal3 54
 defaultsideoverlap allm3 metal3 allm5 metal5 28

#metal5->metal4
 defaultoverlap     allm5 metal5 allm4 metal4 68
 defaultsideoverlap allm5 metal5 allm4 metal4 83
 defaultsideoverlap allm4 metal4 allm5 metal5 47
#endif (METAL5)

#ifdef REDISTRIBUTION
#endif (REDISTRIBUTION)

# Devices:  Base models (not subcircuit wrappers)

variants (),(si)

 device msubcircuit sky130_fd_pr__pfet_01v8 pfet,scpfet \
	*pdiff,pdiffres *pdiff,pdiffres nwell error l=l w=w \
	a1=as p1=ps a2=ad p2=pd
 device msubcircuit sky130_fd_pr__special_pfet_pass ppu \
	*pdiff,pdiffres *pdiff,pdiffres nwell error l=l w=w \
	a1=as p1=ps a2=ad p2=pd
 device msubcircuit sky130_fd_pr__pfet_01v8_lvt pfetlvt \
	*pdiff,pdiffres *pdiff,pdiffres nwell error l=l w=w \
	a1=as p1=ps a2=ad p2=pd
 device msubcircuit sky130_fd_pr__pfet_01v8_mvt pfetmvt \
	*pdiff,pdiffres *pdiff,pdiffres nwell error l=l w=w \
	a1=as p1=ps a2=ad p2=pd
 device msubcircuit sky130_fd_pr__pfet_01v8_hvt pfethvt,scpfethvt \
	*pdiff,pdiffres *pdiff,pdiffres nwell error l=l w=w \
	a1=as p1=ps a2=ad p2=pd

 device msubcircuit sky130_fd_pr__nfet_01v8 nfet,scnfet \
	*ndiff,ndiffres *ndiff,ndiffres pwell,space/w error l=l w=w \
	a1=as p1=ps a2=ad p2=pd
 device msubcircuit sky130_fd_pr__special_nfet_latch npd \
	*ndiff,ndiffres *ndiff,ndiffres pwell,space/w error l=l w=w \
	a1=as p1=ps a2=ad p2=pd
 device msubcircuit sky130_fd_pr__special_nfet_latch npd \
	*ndiff,ndiffres *srampvar pwell,space/w error l=l w=w \
	a1=as p1=ps a2=ad p2=pd
 device msubcircuit sky130_fd_pr__special_nfet_pass npass \
	*ndiff,ndiffres *ndiff,ndiffres pwell,space/w error l=l w=w \
	a1=as p1=ps a2=ad p2=pd
 device msubcircuit sky130_fd_pr__nfet_01v8_lvt nfetlvt \
	*ndiff,ndiffres *ndiff,ndiffres pwell,space/w error l=l w=w \
	a1=as p1=ps a2=ad p2=pd
 device msubcircuit sky130_fd_bs_flash__special_sonosfet_star nsonos \
	*ndiff,ndiffres *ndiff,ndiffres pwell,space/w error l=l w=w \
	a1=as p1=ps a2=ad p2=pd
 device subcircuit sky130_fd_pr__cap_var_lvt varactor \
	*nndiff nwell error l=l w=w a1=as a2=ad p1=ps p2=pd
 device subcircuit sky130_fd_pr__cap_var_hvt varhvt \
	*nndiff nwell error l=l w=w a1=as a2=ad p1=ps p2=pd
 device subcircuit sky130_fd_pr__cap_var mvvaractor \
	*mvnndiff nwell error l=l w=w a1=as a2=ad p1=ps p2=pd

 # Bipolars
 device msubcircuit sky130_fd_pr__npn_05v0 npn dnwell *ndiff space/w error a2=area
 device msubcircuit sky130_fd_pr__pnp_05v0 pnp pwell,space/w *pdiff a2=area
 device msubcircuit sky130_fd_pr__npn_11v0 npn dnwell *mvndiff space/w error a2=area

 # Ignore the extended-drain FET geometry that forms part of the high-voltage
 # bipolar devices.
 device msubcircuit Ignore mvnfet *mvndiff,mvndiffres dnwell pwell,space/w error +npn,pnp
 device msubcircuit Ignore mvpfet *mvpdiff,mvpdiffres pwell,space/w nwell error +npn,pnp

 # Extended drain devices (must appear before the regular devices)
 device msubcircuit sky130_fd_pr__nfet_20v0_nvt mvnnfet *mvndiff,mvndiffres \
	dnwell pwell,space/w error l=l w=w a1=as a2=ad p1=ps p2=pd
 device msubcircuit sky130_fd_pr__nfet_20v0 mvnfet *mvndiff,mvndiffres \
	dnwell pwell,space/w error l=l w=w a1=as a2=ad p1=ps p2=pd
 device msubcircuit sky130_fd_pr__pfet_20v0 mvpfet *mvpdiff,mvpdiffres \
	pwell,space/w nwell error l=l w=w a1=as a2=ad p1=ps p2=pd

 device msubcircuit sky130_fd_pr__pfet_g5v0d10v5 mvpfet \
	*mvpdiff,mvpdiffres *mvpdiff,mvpdiffres nwell error l=l w=w \
	a1=as p1=ps a2=ad p2=pd
 device msubcircuit sky130_fd_pr__nfet_g5v0d10v5 mvnfet \
	*mvndiff,mvndiffres *mvndiff,mvndiffres pwell,space/w error l=l w=w \
	a1=as p1=ps a2=ad p2=pd
 device msubcircuit sky130_fd_pr__nfet_05v0_nvt mvnnfet \
	*mvndiff,mvndiffres *mvndiff,mvndiffres pwell,space/w error l=l w=w \
	a1=as p1=ps a2=ad p2=pd
 device msubcircuit sky130_fd_pr__nfet_03v3_nvt nnfet \
	*mvndiff,mvndiffres *mvndiff,mvndiffres pwell,space/w error l=l w=w \
	a1=as p1=ps a2=ad p2=pd
 device msubcircuit sky130_fd_pr__esd_nfet_g5v0d10v5 mvnfetesd \
	*mvndiff,mvndiffres *mvndiff,mvndiffres pwell,space/w error l=l w=w \
	a1=as p1=ps a2=ad p2=pd
 device msubcircuit sky130_fd_pr__esd_pfet_g5v0d10v5 mvpfetesd \
	*mvpdiff,mvpdiffres *mvpdiff,mvpdiffres nwell error l=l w=w \
	a1=as p1=ps a2=ad p2=pd

 device resistor sky130_fd_pr__res_generic_l1 rli1 *li,coreli
 device resistor sky130_fd_pr__res_generic_m1 rmetal1 *metal1
 device resistor sky130_fd_pr__res_generic_m2 rmetal2 *metal2
 device resistor sky130_fd_pr__res_generic_m3 rmetal3 *metal3
#ifdef METAL5
 device resistor sky130_fd_pr__res_generic_m4 rm4 *m4
 device resistor sky130_fd_pr__res_generic_m5 rm5 *m5
#endif (METAL5)

 device rsubcircuit sky130_fd_pr__res_high_po_0p35 xhrpoly \
	xpc pwell,space/w error +res0p35 l=l
 device rsubcircuit sky130_fd_pr__res_high_po_0p69  xhrpoly \
	xpc pwell,space/w error +res0p69 l=l
 device rsubcircuit sky130_fd_pr__res_high_po_1p41  xhrpoly \
	xpc pwell,space/w error +res1p41 l=l
 device rsubcircuit sky130_fd_pr__res_high_po_2p85  xhrpoly \
	xpc pwell,space/w error +res2p85 l=l
 device rsubcircuit sky130_fd_pr__res_high_po_5p73  xhrpoly \
	xpc pwell,space/w error +res5p73 l=l
 device rsubcircuit sky130_fd_pr__res_high_po	    xhrpoly \
	xpc pwell,space/w error l=l w=w
 device rsubcircuit sky130_fd_pr__res_xhigh_po_0p35  uhrpoly \
	xpc pwell,space/w error +res0p35 l=l
 device rsubcircuit sky130_fd_pr__res_xhigh_po_0p69  uhrpoly \
	xpc pwell,space/w error +res0p69 l=l
 device rsubcircuit sky130_fd_pr__res_xhigh_po_1p41  uhrpoly \
	xpc pwell,space/w error +res1p41 l=l
 device rsubcircuit sky130_fd_pr__res_xhigh_po_2p85  uhrpoly \
	xpc pwell,space/w error +res2p85 l=l
 device rsubcircuit sky130_fd_pr__res_xhigh_po_5p73  uhrpoly \
	xpc pwell,space/w error +res5p73 l=l
 device rsubcircuit sky130_fd_pr__res_xhigh_po	     uhrpoly \
	xpc pwell,space/w error l=l w=w

 device rsubcircuit sky130_fd_pr__res_generic_nd     ndiffres \
	*ndiff pwell,space/w  error l=l w=w
 device rsubcircuit sky130_fd_pr__res_generic_pd     pdiffres \
	*pdiff nwell    error l=l w=w
 device rsubcircuit sky130_fd_pr__res_iso_pw   rpw \
        pwell dnwell error l=l w=w
 device rsubcircuit sky130_fd_pr__res_generic_nd__hv  mvndiffres \
	*mvndiff pwell,space/w error l=l w=w
 device rsubcircuit sky130_fd_pr__res_generic_pd__hv  mvpdiffres \
	*mvpdiff nwell  error l=l w=w

 device resistor sky130_fd_pr__res_generic_po rmp *poly
 device resistor sky130_fd_pr__res_generic_po mrp1 *poly

 device subcircuit  sky130_fd_pr__diode_pd2nw_05v5 *pdiode \
	nwell a=area
 device subcircuit  sky130_fd_pr__diode_pd2nw_05v5_lvt *pdiodelvt \
	nwell a=area
 device subcircuit  sky130_fd_pr__diode_pd2nw_05v5_hvt *pdiodehvt \
	nwell a=area
 device subcircuit  sky130_fd_pr__diode_pd2nw_11v0 *mvpdiode \
	nwell a=area

 device msubcircuit sky130_fd_pr__diode_pw2nd_05v5 *ndiode \
	pwell,space/w a=area
 device msubcircuit sky130_fd_pr__diode_pw2nd_05v5_lvt *ndiodelvt \
	pwell,space/w a=area
 device msubcircuit sky130_fd_pr__diode_pw2nd_05v5_nvt *nndiode \
	pwell,space/w a=area
 device msubcircuit sky130_fd_pr__diode_pw2nd_11v0 *mvndiode \
	pwell,space/w a=area


#ifdef MIM
 device csubcircuit sky130_fd_pr__cap_mim_m3_1 *mimcap  *m3 w=w l=l
 device csubcircuit sky130_fd_pr__cap_mim_m3_2 *mimcap2 *m4 w=w l=l
#endif (MIM)

 variants (orig)

 device mosfet sky130_fd_pr__pfet_01v8 scpfet,pfet pdiff,pdiffres,pdc nwell 
 device mosfet sky130_fd_pr__special_pfet_pass ppu pdiff,pdiffres,pdc nwell 
 device mosfet sky130_fd_pr__pfet_01v8_lvt pfetlvt pdiff,pdiffres,pdc nwell 
 device mosfet sky130_fd_pr__pfet_01v8_mvt pfetmvt pdiff,pdiffres,pdc nwell 
 device mosfet sky130_fd_pr__pfet_01v8_hvt scpfethvt,pfethvt pdiff,pdiffres,pdc nwell 
 device mosfet sky130_fd_pr__nfet_01v8 scnfet,nfet ndiff,ndiffres,ndc pwell,space/w
 device mosfet sky130_fd_pr__special_nfet_pass  npass ndiff,ndiffres,ndc pwell,space/w
 device mosfet sky130_fd_pr__special_nfet_latch npd ndiff,ndiffres,ndc pwell,space/w
 device mosfet sky130_fd_pr__special_nfet_latch npd ndiff,ndiffres,ndc pwell,space/w
 device mosfet sky130_fd_pr__nfet_01v8_lvt nfetlvt ndiff,ndiffres,ndc pwell,space/w
 device mosfet sky130_fd_bs_flash__special_sonosfet_star nsonos ndiff,ndiffres,ndc \
	pwell,space/w

 # Note that corenvar, corepvar are not considered devices, and extract as
 # parasitic capacitance instead (but cap values need to be added).

 # Extended drain devices (must appear before the regular devices)
 device mosfet sky130_fd_pr__nfet_20v0_nvt mvnnfet *mvndiff,mvndiffres \
	dnwell pwell,space/w error
 device mosfet sky130_fd_pr__nfet_20v0 mvnfet *mvndiff,mvndiffres \
	dnwell pwell,space/w error
 device mosfet sky130_fd_pr__pfet_20v0 mvpfet *mvpdiff,mvpdiffres \
	pwell,space/w nwell error

 device mosfet sky130_fd_pr__pfet_g5v0d10v5 mvpfet mvpdiff,mvpdiffres,mvpdc nwell 
 device mosfet sky130_fd_pr__esd_pfet_g5v0d10v5 mvpfetesd mvpdiff,mvpdiffres,mvpdc nwell 
 device mosfet sky130_fd_pr__nfet_g5v0d10v5 mvnfet mvndiff,mvndiffres,mvndc pwell,space/w
 device mosfet sky130_fd_pr__esd_nfet_g5v0d10v5 mvnfetesd mvndiff,mvndiffres,mvndc pwell,space/w
 device mosfet sky130_fd_pr__nfet_05v0_nvt mvnnfet *mvndiff,mvndiffres pwell,space/w
 device mosfet sky130_fd_pr__nfet_03v3_nvt nnfet *mvndiff,mvndiffres pwell,space/w

 # These devices always extract as subcircuits
 device subcircuit sky130_fd_pr__cap_var_lvt varactor *nndiff nwell error l=l w=w
 device subcircuit sky130_fd_pr__cap_var_hvt varhvt *nndiff nwell error l=l w=w
 device subcircuit sky130_fd_pr__cap_var mvvaractor *mvnndiff nwell error l=l w=w

 device resistor sky130_fd_pr__res_generic_po rmp     *poly
 device resistor sky130_fd_pr__res_generic_l1 rli1    *li,coreli
 device resistor sky130_fd_pr__res_generic_m1 rmetal1 *metal1
 device resistor sky130_fd_pr__res_generic_m2 rmetal2 *metal2
 device resistor sky130_fd_pr__res_generic_m3 rmetal3 *metal3
#ifdef METAL5
 device resistor sky130_fd_pr__res_generic_m4 rm4 *m4
 device resistor sky130_fd_pr__res_generic_m5 rm5 *m5
#endif (METAL5)

 device resistor sky130_fd_pr__res_high_po_0p35 xhrpoly xpc +res0p35
 device resistor sky130_fd_pr__res_high_po_0p69 xhrpoly xpc +res0p69
 device resistor sky130_fd_pr__res_high_po_1p41 xhrpoly xpc +res1p41
 device resistor sky130_fd_pr__res_high_po_2p85 xhrpoly xpc +res2p85
 device resistor sky130_fd_pr__res_high_po_5p73 xhrpoly xpc +res5p73
 device resistor sky130_fd_pr__res_high_po xhrpoly xpc 
 device resistor sky130_fd_pr__res_xhigh_po_0p35 uhrpoly xpc +res0p35
 device resistor sky130_fd_pr__res_xhigh_po_0p69 uhrpoly xpc +res0p69
 device resistor sky130_fd_pr__res_xhigh_po_1p41 uhrpoly xpc +res1p41
 device resistor sky130_fd_pr__res_xhigh_po_2p85 uhrpoly xpc +res2p85
 device resistor sky130_fd_pr__res_xhigh_po_5p73 uhrpoly xpc +res5p73
 device resistor sky130_fd_pr__res_xhigh_po uhrpoly xpc 
 device resistor sky130_fd_pr__res_generic_po  mrp1     *poly 
 device resistor sky130_fd_pr__res_generic_nd  ndiffres *ndiff 
 device resistor sky130_fd_pr__res_generic_pd  pdiffres *pdiff 
 device resistor mrdn_hv   mvndiffres *mvndiff 
 device resistor mrdp_hv   mvpdiffres *mvpdiff 
 device resistor sky130_fd_pr__res_iso_pw   rpw    pwell

 device ndiode sky130_fd_pr__diode_pw2nd_05v5 *ndiode pwell,space/w a=area
 device ndiode sky130_fd_pr__diode_pw2nd_05v5_lvt *ndiodelvt pwell,space/w a=area
 device ndiode sky130_fd_pr__diode_pw2nd_05v5_nvt *nndiode pwell,space/w a=area
 device ndiode sky130_fd_pr__diode_pw2nd_11v0 *mvndiode pwell,space/w a=area

 device pdiode sky130_fd_pr__diode_pd2nw_05v5 *pdiode nwell a=area
 device pdiode sky130_fd_pr__diode_pd2nw_05v5_lvt *pdiodelvt nwell a=area
 device pdiode sky130_fd_pr__diode_pd2nw_05v5_hvt *pdiodehvt nwell a=area
 device pdiode sky130_fd_pr__diode_pd2nw_11v0 *mvpdiode nwell a=area

 device bjt sky130_fd_pr__npn_05v5 npn dnwell *ndiff space/w error a2=area
 device bjt sky130_fd_pr__pnp_05v5 pnp pwell,space/w *pdiff a2=area
 device bjt sky130_fd_pr__npn_11v0 npn dnwell *mvndiff space/w error a2=area

#ifdef MIM
 device capacitor sky130_fd_pr__cap_mim_m3_1 *mimcap  *m3 1
 device capacitor sky130_fd_pr__cap_mim_m3_2 *mimcap2 *m4 1
#endif (MIM)

end

#-----------------------------------------------------
# Wiring tool definitions
#-----------------------------------------------------

wiring
 # All wiring values are in nanometers
 scalefactor 10

 contact mcon 170 li 0  0 m1 30 60
 contact v1  260 m1 0 30 m2  0 30
 contact v2  280 m2 0 45 m3 25  0
#ifdef METAL5
 contact v3  320 m3 0 30 m4  5  5
 contact v4 1180 m4 0    m5 120
#endif (METAL5)

 contact pc  170  poly 50 80 li 0 80
 contact pdc 170 pdiff 40 60 li 0 80
 contact ndc 170 ndiff 40 60 li 0 80
 contact psc 170   psd 40 60 li 0 80
 contact nsc 170   nsd 40 60 li 0 80

end

#-----------------------------------------------------
# Plain old router. . . 
#-----------------------------------------------------

router
end

#------------------------------------------------------------
# Plowing (restored in magic 8.2, need to fill this section)
#------------------------------------------------------------

plowing
end

#-----------------------------------------------------------------
# No special plot layers defined (use default PNM color choices)
#-----------------------------------------------------------------

plot
  style pnm
     default
     draw fillblock no_color_at_all
     draw fillblock4 no_color_at_all
     draw fomfill no_color_at_all
     draw polyfill no_color_at_all
     draw m1fill no_color_at_all
     draw m2fill no_color_at_all
     draw m3fill no_color_at_all
     draw m4fill no_color_at_all
     draw m5fill no_color_at_all
     draw nwell cwell
end