)]}'
{
  "commit": "e895c2acc79dd9eae8ebee51cc3a06c1c96eecc0",
  "tree": "b04e5d0ac07464ab73d2606eed1f965e70a8add0",
  "parents": [
    "cfe970cf064ecd490117858b3eef726b610bc161"
  ],
  "author": {
    "name": "Tim Edwards",
    "email": "tim@opencircuitdesign.com",
    "time": "Fri Feb 26 16:05:31 2021 -0500"
  },
  "committer": {
    "name": "Tim Edwards",
    "email": "tim@opencircuitdesign.com",
    "time": "Fri Feb 26 16:05:31 2021 -0500"
  },
  "message": "Corrected the GDS read of the SRAM cell so that the weird parasitic\ndevice formed between DIFF and TAP under a grounded gate is interpreted\nas type npd, which is the type that has a model that supposedly is for\nthis device.  I attempted to add extraction methods specifically for\nthe parasitic MOScap-type devices in the SRAM cell.  Both now generate\nerror messages when extracting.  The DIFF/TAP-under-gate device now\nextracts with the correct length and width.  The pFET MOScap has the\ncorrect width but not length (probably counting the sides).\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "415a40ee20679350f0aea75f0e514d07d596fd26",
      "old_mode": 33188,
      "old_path": "sky130/magic/sky130.tech",
      "new_id": "6a1f4ec4abc6724a68c9ff6ba8f3f3ed5ff48b8f",
      "new_mode": 33188,
      "new_path": "sky130/magic/sky130.tech"
    }
  ]
}