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foss-eda-tools/third_party/opencircuitdesign.com/open_pdks/e8294524e5f67c533c5d0c3afa0bcc5b2a5fa066^!/.
commit
e8294524e5f67c533c5d0c3afa0bcc5b2a5fa066
[log] [tgz]
author
Donn <me@donn.website>
Fri Jul 29 14:40:07 2022 +0200
committer
Donn <me@donn.website>
Fri Jul 29 14:40:07 2022 +0200
tree
36c19a3ecd183504938ac6f6f6acc64ab04a95ac
parent
335882bf7cd8f9d192bf8cf7a765d07445496325 [diff]
Config Updates + Magic Update

+ Add CVC files to PDK proper instead of being inside OpenLane
~ sky130.json whitespace reformat
~ sky130:magic -> `f7df5e7c86fb47c5fd445c846afddc6fbabad6ae`
~ `CELL_PAD` -> `GPL/DPL_CELL_PADDING`
~ `CELL_PAD_EXECLUDE` -> `CELL_PAD_EXCLUDE`

diff --git a/sky130/Makefile.in b/sky130/Makefile.in
index f40b720..69e9049 100644
--- a/sky130/Makefile.in
+++ b/sky130/Makefile.in

@@ -1012,6 +1012,7 @@
 	rm -f ${OPENLANE_STAGING_$*}/rules.openrcx.sky130$*.max.spef_extractor
 
 	cp -r openlane/custom_cells ${OPENLANE_STAGING_$*}
+	cp -r openlane/cvc ${OPENLANE_STAGING_$*}
 	${CPP} ${SKY130$*_DEFS} openlane/config.tcl ${OPENLANE_STAGING_$*}/config.tcl
 
 	${CPP} ${SKY130$*_DEFS} openlane/rules.openrcx.sky130$*.min.magic \

diff --git a/sky130/openlane/config.tcl b/sky130/openlane/config.tcl
index a1172d9..856d9c1 100755
--- a/sky130/openlane/config.tcl
+++ b/sky130/openlane/config.tcl

@@ -86,9 +86,9 @@
 #endif (!EF_FORMAT)
 
 # Klayout setup
-set ::env(KLAYOUT_TECH) "$::env(PDK_ROOT)/$::env(PDK)/libs.tech/klayout/$::env(PDK).lyt"
-set ::env(KLAYOUT_PROPERTIES) "$::env(PDK_ROOT)/$::env(PDK)/libs.tech/klayout/$::env(PDK).lyp"
-set ::env(KLAYOUT_DRC_TECH_SCRIPT) "$::env(PDK_ROOT)/$::env(PDK)/libs.tech/klayout/$::env(PDK)_mr.drc"
+set ::env(KLAYOUT_TECH) "$::env(PDK_ROOT)/$::env(PDK)/libs.tech/klayout/tech/$::env(PDK).lyt"
+set ::env(KLAYOUT_PROPERTIES) "$::env(PDK_ROOT)/$::env(PDK)/libs.tech/klayout/tech/$::env(PDK).lyp"
+set ::env(KLAYOUT_DRC_TECH_SCRIPT) "$::env(PDK_ROOT)/$::env(PDK)/libs.tech/klayout/drc/$::env(PDK)_mr.drc"
 #set ::env(KLAYOUT_DRC_TECH) "$::env(PDK_ROOT)/$::env(PDK)/libs.tech/klayout/$::env(PDK).lydrc"
 
 # netgen setup
@@ -167,3 +167,6 @@
 
 set ::env(RT_MIN_LAYER) "met1"
 set ::env(RT_MAX_LAYER) "met5"
+
+# CVC
+set ::env(CVC_SCRIPTS_DIR) "$::env(PDK_ROOT)/$::env(PDK)/libs.tech/openlane/cvc"
\ No newline at end of file

diff --git a/sky130/openlane/cvc/cdl.awk b/sky130/openlane/cvc/cdl.awk
new file mode 100644
index 0000000..96c7c08
--- /dev/null
+++ b/sky130/openlane/cvc/cdl.awk

@@ -0,0 +1,16 @@
+/Black-box entry subcircuit/ {  # remove black-box defintions
+    while ( $1 != ".ends" ) {
+        getline;
+    }
+    getline;
+}
+/^\*/ {  # remove comments
+    next;
+}
+/^.ENDS .*/ {  # remove name from ends lines
+    print $1;
+    next;
+}
+ {
+    print $0;
+}
\ No newline at end of file

diff --git a/sky130/openlane/cvc/cvcrc b/sky130/openlane/cvc/cvcrc
new file mode 100644
index 0000000..2bd054f
--- /dev/null
+++ b/sky130/openlane/cvc/cvcrc

@@ -0,0 +1,36 @@
+
+CVC_MODEL_FILE = $CVC_SCRIPTS_DIR/models
+CVC_TOP = $DESIGN_NAME
+CVC_MODE = $CVC_TOP
+CVC_NETLIST = $signoff_tmpfiles/$DESIGN_NAME.cdl
+CVC_POWER_FILE = $signoff_tmpfiles/$CVC_TOP.power
+CVC_REPORT_FILE = $signoff_reports/$CVC_TOP.rpt
+CVC_FUSE_FILE = ''
+CVC_REPORT_TITLE = 'CVC $CVC_TOP'
+CVC_CIRCUIT_ERROR_LIMIT = '100'
+CVC_SEARCH_LIMIT = '100'
+CVC_LEAK_LIMIT = '0.0002'
+CVC_SOI = 'false'
+CVC_SCRC = 'false'
+CVC_VTH_GATES = 'false'
+CVC_MIN_VTH_GATES = 'false'
+CVC_IGNORE_VTH_FLOATING = 'false'
+CVC_IGNORE_NO_LEAK_FLOATING = 'false'
+CVC_LEAK_OVERVOLTAGE = 'true'
+CVC_LOGIC_DIODES = 'false'
+CVC_ANALOG_GATES = 'true'
+CVC_BACKUP_RESULTS = 'false'
+CVC_MOS_DIODE_ERROR_THRESHOLD = '0'
+CVC_SHORT_ERROR_THRESHOLD = '0'
+CVC_BIAS_ERROR_THRESHOLD = '0'
+CVC_FORWARD_ERROR_THRESHOLD = '0'
+CVC_FLOATING_ERROR_THRESHOLD = '0'
+CVC_GATE_ERROR_THRESHOLD = '0'
+CVC_LEAK?_ERROR_THRESHOLD = '0'
+CVC_EXPECTED_ERROR_THRESHOLD = '0'
+CVC_OVERVOLTAGE_ERROR_THRESHOLD = '0'
+CVC_PARALLEL_CIRCUIT_PORT_LIMIT = '0'
+CVC_CELL_ERROR_LIMIT_FILE = ''
+CVC_CELL_CHECKSUM_FILE = ''
+CVC_LARGE_CIRCUIT_SIZE = '10000000'
+CVC_NET_CHECK_FILE = ''

diff --git a/sky130/openlane/cvc/models b/sky130/openlane/cvc/models
new file mode 100644
index 0000000..cdbff13
--- /dev/null
+++ b/sky130/openlane/cvc/models

@@ -0,0 +1,53 @@
+MN nfet_01v8 Vth=0.2 Vgs=1.8 Vds=1.8
+MP pfet_01v8_hvt Vth=-0.2 Vgs=1.8 Vds=1.8
+
+R short model=switch_on
+
+D sky130_fd_pr__diode_pw2nd_05v5 
+D sky130_fd_pr__diode_pw2nd_11v0 
+D sky130_fd_pr__diode_pd2nw_05v5
+D sky130_fd_pr__model__parasitic__diode_ps2dn
+D sky130_fd_pr__model__parasitic__diode_ps2nw
+D sky130_fd_pr__model__parasitic__diode_pw2dn
+D condiode
+
+
+#R sky130_fd_pr__res_generic_m1 R=l/w*0.125
+#R sky130_fd_pr__res_generic_m2 R=l/w*0.125
+#R sky130_fd_pr__res_generic_m3 R=l/w*0.047
+#R sky130_fd_pr__res_generic_m4 R=l/w*0.047
+#R sky130_fd_pr__res_generic_nd R=l/w*0.029
+R sky130_fd_pr__res_generic_m1 R=l/w
+R sky130_fd_pr__res_generic_m2 R=l/w
+R sky130_fd_pr__res_generic_m3 R=l/w
+R sky130_fd_pr__res_generic_m4 R=l/w
+R sky130_fd_pr__res_generic_m5 R=l/w
+R sky130_fd_pr__res_generic_nd R=l/w*120
+R sky130_fd_pr__res_generic_nd__hv R=l/w*114
+R sky130_fd_pr__res_generic_pd__hv R=l/w*191
+R sky130_fd_pr__res_generic_po R=l/w*48
+R sky130_fd_pr__res_xhigh_po R=l/w*2000
+R sky130_fd_pr__res_high_po R=l/w*2000
+
+MN sky130_fd_pr__nfet_01v8 Vth=0.2 Vgs=1.8 Vds=1.8
+MN sky130_fd_pr__nfet_01v8_lvt Vth=0.1 Vgs=1.8 Vds=1.8
+MN sky130_fd_pr__special_nfet_latch Vth=0.2 Vgs=1.8 Vds=1.8
+MN sky130_fd_pr__nfet_03v3_nvt Vth=0.2 Vgs=3.3 Vds=3.3
+MN sky130_fd_pr__esd_nfet_g5v0d10v5 Vth=0.2
+MN sky130_fd_pr__nfet_05v0_nvt Vth=0.2
+MN sky130_fd_pr__nfet_g5v0d10v5 Vth=0.2
+MN sky130_fd_bs_flash__special_sonosfet_star Vth=0.2
+
+MP sky130_fd_pr__pfet_01v8 Vth=-0.2 Vgs=1.8 Vds=1.8
+MP sky130_fd_pr__pfet_01v8_lvt Vth=-0.1 Vgs=1.8 Vds=1.8
+MP sky130_fd_pr__pfet_01v8_hvt Vth=-0.3 Vgs=1.8 Vds=1.8
+MP sky130_fd_pr__special_pfet_pass Vth=-0.2 Vgs=1.8 Vds=1.8
+MP sky130_fd_pr__pfet_g5v0d10v5 Vth=-0.2
+
+C sky130_fd_pr__cap_mim_m3_1
+C sky130_fd_pr__cap_mim_m3_2
+C sky130_fd_pr__cap_var
+
+Q sky130_fd_pr__pnp_05v5
+
+ 

diff --git a/sky130/openlane/cvc/power.awk b/sky130/openlane/cvc/power.awk
new file mode 100644
index 0000000..5b3466e
--- /dev/null
+++ b/sky130/openlane/cvc/power.awk

@@ -0,0 +1,15 @@
+BEGIN {  # Print power and standard_input definitions
+    printf "%s power 1.8\n", vdd;
+    printf "%s power 0.0\n", gnd;
+    printf "#define std_input min@%s max@%s\n", gnd, vdd;
+}
+$1 == "input" {  # Print input nets
+    gsub(/;/, "");
+    if ( $2 == vdd || $2 == gnd ) {  # ignore power nets
+        next;
+    }
+    if ( NF == 3 ) {  # print buses as net[range]
+        $2 = $3 $2;
+    }
+    print $2, "input std_input";
+}
\ No newline at end of file

diff --git a/sky130/openlane/sky130_fd_sc_hd/config.tcl b/sky130/openlane/sky130_fd_sc_hd/config.tcl
index 26bea27..eeea933 100755
--- a/sky130/openlane/sky130_fd_sc_hd/config.tcl
+++ b/sky130/openlane/sky130_fd_sc_hd/config.tcl

@@ -33,7 +33,7 @@
 set ::env(SYNTH_DRIVING_CELL) "sky130_fd_sc_hd__inv_2"
 #capacitance : 0.017653;
 set ::env(SYNTH_DRIVING_CELL_PIN) "Y"
-# update these 
+# update these
 set ::env(SYNTH_CAP_LOAD) "33.442" ; # femtofarad __inv_16 pin A cap (https://github.com/google/skywater-pdk-libs-sky130_fd_sc_hd/blob/main/cells/inv/sky130_fd_sc_hd__inv_16__tt_025C_1v80.lib.json)
 set ::env(SYNTH_MIN_BUF_PORT) "sky130_fd_sc_hd__buf_2 A X"
 set ::env(SYNTH_TIEHI_PORT) "sky130_fd_sc_hd__conb_1 HI"
@@ -56,7 +56,8 @@
 set ::env(FAKEDIODE_CELL) "sky130_ef_sc_hd__fakediode_2"
 set ::env(DIODE_CELL_PIN) "DIODE"
 
-set ::env(CELL_PAD) 4
+set ::env(GPL_CELL_PADDING) {0}
+set ::env(DPL_CELL_PADDING) {4}
 set ::env(CELL_PAD_EXCLUDE) "sky130_fd_sc_hd__tap* sky130_fd_sc_hd__decap* sky130_ef_sc_hd__decap* sky130_fd_sc_hd__fill*"
 
 # Clk Buffers info CTS data

diff --git a/sky130/openlane/sky130_fd_sc_hdll/config.tcl b/sky130/openlane/sky130_fd_sc_hdll/config.tcl
index 8fb7d42..f6c343a 100755
--- a/sky130/openlane/sky130_fd_sc_hdll/config.tcl
+++ b/sky130/openlane/sky130_fd_sc_hdll/config.tcl

@@ -53,7 +53,8 @@
 set ::env(FAKEDIODE_CELL) "sky130_fd_sc_hdll__fakediode_2"
 set ::env(DIODE_CELL_PIN) "DIODE"
 
-set ::env(CELL_PAD) 4
+set ::env(GPL_CELL_PADDING) {0}
+set ::env(DPL_CELL_PADDING) {4}
 set ::env(CELL_PAD_EXCLUDE) "$::env(STD_CELL_LIBRARY)__tap* $::env(STD_CELL_LIBRARY)__decap* $::env(STD_CELL_LIBRARY)__fill*"
 
 # Clk Buffers info CTS data

diff --git a/sky130/openlane/sky130_fd_sc_hs/config.tcl b/sky130/openlane/sky130_fd_sc_hs/config.tcl
index 39e80b9..8761689 100755
--- a/sky130/openlane/sky130_fd_sc_hs/config.tcl
+++ b/sky130/openlane/sky130_fd_sc_hs/config.tcl

@@ -54,7 +54,8 @@
 set ::env(DIODE_CELL) "sky130_fd_sc_hs__diode_2"
 set ::env(DIODE_CELL_PIN) "DIODE"
 
-set ::env(CELL_PAD) 4
+set ::env(GPL_CELL_PADDING) {0}
+set ::env(DPL_CELL_PADDING) {4}
 set ::env(CELL_PAD_EXCLUDE) "sky130_fd_sc_hs__tap* sky130_fd_sc_hs__decap* sky130_fd_sc_hs__fill*"
 
 set ::env(ROOT_CLK_BUFFER) sky130_fd_sc_hs__clkbuf_16

diff --git a/sky130/openlane/sky130_fd_sc_hvl/config.tcl b/sky130/openlane/sky130_fd_sc_hvl/config.tcl
index 54f04ba..edc73f0 100644
--- a/sky130/openlane/sky130_fd_sc_hvl/config.tcl
+++ b/sky130/openlane/sky130_fd_sc_hvl/config.tcl

@@ -5,14 +5,14 @@
 set ::env(LIB_SYNTH) "\
 	$::env(PDK_ROOT)/$::env(PDK)/libs.ref/lib/$::env(STD_CELL_LIBRARY)/sky130_fd_sc_hvl__tt_025C_3v30.lib\
 	$::env(PDK_ROOT)/$::env(PDK)/libs.ref/lib/$::env(STD_CELL_LIBRARY)/sky130_fd_sc_hvl__tt_025C_3v30_lv1v80.lib\
-	"
+"
 set ::env(LIB_FASTEST) "$::env(PDK_ROOT)/$::env(PDK)/libs.ref/lib/$::env(STD_CELL_LIBRARY)/sky130_fd_sc_hvl__ff_n40C_5v50.lib"
 set ::env(LIB_SLOWEST) "$::env(PDK_ROOT)/$::env(PDK)/libs.ref/lib/$::env(STD_CELL_LIBRARY)/sky130_fd_sc_hvl__ss_150C_1v65.lib"
 #else (!EF_FORMAT)
 set ::env(LIB_SYNTH) "\
 	$::env(PDK_ROOT)/$::env(PDK)/libs.ref/$::env(STD_CELL_LIBRARY)/lib/sky130_fd_sc_hvl__tt_025C_3v30.lib\
 	$::env(PDK_ROOT)/$::env(PDK)/libs.ref/$::env(STD_CELL_LIBRARY)/lib/sky130_fd_sc_hvl__tt_025C_3v30_lv1v80.lib\
-	"
+"
 set ::env(LIB_FASTEST) "$::env(PDK_ROOT)/$::env(PDK)/libs.ref/$::env(STD_CELL_LIBRARY)/lib/sky130_fd_sc_hvl__ff_n40C_5v50.lib"
 set ::env(LIB_SLOWEST) "$::env(PDK_ROOT)/$::env(PDK)/libs.ref/$::env(STD_CELL_LIBRARY)/lib/sky130_fd_sc_hvl__ss_150C_1v65.lib"
 #endif (!EF_FORMAT)
@@ -39,7 +39,7 @@
 set ::env(SYNTH_DRIVING_CELL) "sky130_fd_sc_hvl__inv_2"
 #capacitance : 0.017653;
 set ::env(SYNTH_DRIVING_CELL_PIN) "Y"
-# update these 
+# update these
 set ::env(SYNTH_CAP_LOAD) "70.77" ; # femtofarad __inv_16 pin A cap (https://github.com/google/skywater-pdk-libs-sky130_fd_sc_hvl/blob/main/cells/inv/sky130_fd_sc_hvl__inv_16__tt_025C_3v30.lib.json)
 set ::env(SYNTH_MIN_BUF_PORT) "sky130_fd_sc_hvl__buf_1 A X"
 set ::env(SYNTH_TIEHI_PORT) "sky130_fd_sc_hvl__conb_1 HI"
@@ -61,7 +61,8 @@
 set ::env(DIODE_CELL) "sky130_fd_sc_hvl__diode_2"
 set ::env(DIODE_CELL_PIN) "DIODE"
 
-set ::env(CELL_PAD) 4
+set ::env(GPL_CELL_PADDING) {0}
+set ::env(DPL_CELL_PADDING) {4}
 set ::env(CELL_PAD_EXCLUDE) "sky130_fd_sc_hvl__tap* sky130_fd_sc_hvl__decap* sky130_fd_sc_hvl__fill*"
 
 # Clk Buffers info CTS data

diff --git a/sky130/openlane/sky130_fd_sc_ls/config.tcl b/sky130/openlane/sky130_fd_sc_ls/config.tcl
index 2e6130d..d303922 100755
--- a/sky130/openlane/sky130_fd_sc_ls/config.tcl
+++ b/sky130/openlane/sky130_fd_sc_ls/config.tcl

@@ -56,7 +56,8 @@
 set ::env(FAKEDIODE_CELL) "sky130_fd_sc_ls__fakediode_2"
 set ::env(DIODE_CELL_PIN) "DIODE"
 
-set ::env(CELL_PAD) 4
+set ::env(GPL_CELL_PADDING) {0}
+set ::env(DPL_CELL_PADDING) {4}
 set ::env(CELL_PAD_EXCLUDE) "$::env(STD_CELL_LIBRARY)__tap* $::env(STD_CELL_LIBRARY)__decap* $::env(STD_CELL_LIBRARY)__fill*"
 
 # Clk Buffers info CTS data

diff --git a/sky130/openlane/sky130_fd_sc_ms/config.tcl b/sky130/openlane/sky130_fd_sc_ms/config.tcl
index 72f5c2f..51cd1a8 100755
--- a/sky130/openlane/sky130_fd_sc_ms/config.tcl
+++ b/sky130/openlane/sky130_fd_sc_ms/config.tcl

@@ -55,7 +55,8 @@
 set ::env(DIODE_CELL) "sky130_fd_sc_ms__diode_2"
 set ::env(DIODE_CELL_PIN) "DIODE"
 
-set ::env(CELL_PAD) 4
+set ::env(GPL_CELL_PADDING) {0}
+set ::env(DPL_CELL_PADDING) {4}
 set ::env(CELL_PAD_EXCLUDE) "$::env(STD_CELL_LIBRARY)__tap* $::env(STD_CELL_LIBRARY)__decap* $::env(STD_CELL_LIBRARY)__fill*"
 
 # Clk Buffers info CTS data

diff --git a/sky130/openlane/sky130_osu_sc_t18/config.tcl b/sky130/openlane/sky130_osu_sc_t18/config.tcl
index eb9753c..2f35abb 100755
--- a/sky130/openlane/sky130_osu_sc_t18/config.tcl
+++ b/sky130/openlane/sky130_osu_sc_t18/config.tcl

@@ -56,8 +56,9 @@
 #set ::env(FAKEDIODE_CELL) "sky130_osu_sc_t18__fakediode_2"
 set ::env(DIODE_CELL_PIN) "A"
 
-set ::env(CELL_PAD) 4
-set ::env(CELL_PAD_EXECLUDE) "FILLX*"
+set ::env(GPL_CELL_PADDING) {0}
+set ::env(DPL_CELL_PADDING) {4}
+set ::env(CELL_PAD_EXCLUDE) "FILLX*"
 
 # Clk Buffers info CTS data
 set ::env(ROOT_CLK_BUFFER) CLKBUFX1

diff --git a/sky130/sky130.json b/sky130/sky130.json
index 566764e..1af4c5c 100644
--- a/sky130/sky130.json
+++ b/sky130/sky130.json

@@ -1,4 +1,5 @@
-#define DESCRIPTION Skywater 0.13um CMOS, local interconntect + high-resistance poly
+{
+#define DESCRIPTION Skywater 0.13um CMOS, local interconnect + high-resistance poly
 #ifdef METAL5
 #define OPTION1 + 5 metal layer backend stack
 #else
@@ -19,7 +20,6 @@
 #else
 #define OPTION4
 #endif (RERAM)
-{
     "foundry": "SW",
     "foundry-name": "SkyWater",
     "node": "TECHNAME",
@@ -57,46 +57,46 @@
 #endif (REDISTRIBUTION)
     ],
     "stdcells": {
-	"sky130_fd_sc_hd": "FD_SC_HD_COMMIT",
-	"sky130_fd_sc_hdll": "FD_SC_HDLL_COMMIT",
-	"sky130_fd_sc_hs": "FD_SC_HS_COMMIT",
-	"sky130_fd_sc_hvl": "FD_SC_HVL_COMMIT",
-	"sky130_fd_sc_lp": "FD_SC_LP_COMMIT",
-	"sky130_fd_sc_ls": "FD_SC_LS_COMMIT",
-	"sky130_fd_sc_ms": "FD_SC_MS_COMMIT",
-	"sky130_osu_sc_t12": "OSU_T12_COMMIT",
-	"sky130_osu_sc_t15": "OSU_T15_COMMIT",
-	"sky130_osu_sc_t18": "OSU_T18_COMMIT"
+        "sky130_fd_sc_hd": "FD_SC_HD_COMMIT",
+        "sky130_fd_sc_hdll": "FD_SC_HDLL_COMMIT",
+        "sky130_fd_sc_hs": "FD_SC_HS_COMMIT",
+        "sky130_fd_sc_hvl": "FD_SC_HVL_COMMIT",
+        "sky130_fd_sc_lp": "FD_SC_LP_COMMIT",
+        "sky130_fd_sc_ls": "FD_SC_LS_COMMIT",
+        "sky130_fd_sc_ms": "FD_SC_MS_COMMIT",
+        "sky130_osu_sc_t12": "OSU_T12_COMMIT",
+        "sky130_osu_sc_t15": "OSU_T15_COMMIT",
+        "sky130_osu_sc_t18": "OSU_T18_COMMIT"
     },
     "iocells": {
         "sky130_fd_io": "FD_IO_COMMIT"
     },
     "primitive": {
-	"sky130_fd_pr": "FD_PR_COMMIT"
+        "sky130_fd_pr": "FD_PR_COMMIT"
     },
     "memory": {
-	"sky130_sram_macros": "SRAM_COMMIT"
+        "sky130_sram_macros": "SRAM_COMMIT"
     },
     "other": {
-	"sky130_ml_xx_hd": "ALPHA_COMMIT"
+        "sky130_ml_xx_hd": "ALPHA_COMMIT"
     },
     "build": {
-	"open_pdks": "OPEN_PDKS_VERSION",
-	"magic": "MAGIC_VERSION"
+        "open_pdks": "OPEN_PDKS_VERSION",
+        "magic": "MAGIC_VERSION"
     },
     "commit": {
-	"open_pdks": "OPEN_PDKS_COMMIT",
-	"magic": "MAGIC_COMMIT"
+        "open_pdks": "OPEN_PDKS_COMMIT",
+        "magic": "MAGIC_COMMIT"
     },
     "reference": {
-	"open_pdks": "d7faec2b6f384254449e0172c4f26083f77d3ff5",
-	"magic": "fe2eb6d3906ed15ade0e7a51daea80dd4e3846e2",
-	"skywater_pdk": "f70d8ca46961ff92719d8870a18a076370b85f6c",
-	"sky130_osu_sc_t12": "6af093f919721daec4bb256c4c40aaa8bc84f4bd",
-	"sky130_osu_sc_t15": "f1eef844734f73d3c79d83b82352118263eb7686",
-	"sky130_osu_sc_t18": "3128b623aaea315248d39173e09b49a3dc82aa40",
-	"sky130_sram_macros": "c2333394e0b0b9d9d71185678a8d8087715d5e3b",
-	"sky130_ml_xx_hd": "6eb3b0718552b034f1bf1870285ff135e3fb2dcb",
-	"xschem_sky130": "16efae642739ba5c50aa2a40e403b036a5e31a6c"
+        "open_pdks": "d7faec2b6f384254449e0172c4f26083f77d3ff5",
+        "magic": "f7df5e7c86fb47c5fd445c846afddc6fbabad6ae",
+        "skywater_pdk": "f70d8ca46961ff92719d8870a18a076370b85f6c",
+        "sky130_osu_sc_t12": "6af093f919721daec4bb256c4c40aaa8bc84f4bd",
+        "sky130_osu_sc_t15": "f1eef844734f73d3c79d83b82352118263eb7686",
+        "sky130_osu_sc_t18": "3128b623aaea315248d39173e09b49a3dc82aa40",
+        "sky130_sram_macros": "c2333394e0b0b9d9d71185678a8d8087715d5e3b",
+        "sky130_ml_xx_hd": "6eb3b0718552b034f1bf1870285ff135e3fb2dcb",
+        "xschem_sky130": "16efae642739ba5c50aa2a40e403b036a5e31a6c"
     }
-}
+}
\ No newline at end of file