)]}'
{
  "commit": "e74c6492e8267d62ab5ef273bab7a60cfcb7ed63",
  "tree": "a4482835c4fa5e2ad0b042fe06e8858bb03693d6",
  "parents": [
    "68fc4e6fb573712eb90d4eed46b3dd5261865aa4"
  ],
  "author": {
    "name": "Tim Edwards",
    "email": "tim@opencircuitdesign.com",
    "time": "Mon Jun 14 11:13:09 2021 -0400"
  },
  "committer": {
    "name": "Tim Edwards",
    "email": "tim@opencircuitdesign.com",
    "time": "Mon Jun 14 11:13:09 2021 -0400"
  },
  "message": "Corrected pin connections in the verilog for sky130_ef_io (pins for\ntwo cells incorrectly labeled while splitting the pad and core pins\non the power pads).\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "5f7bf9cc0d2e4fc1ae61d2baa4dac7b56a703290",
      "old_mode": 33188,
      "old_path": "VERSION",
      "new_id": "754b84ed862c0dac01c6b8cfdb3be6ab1f2cc630",
      "new_mode": 33188,
      "new_path": "VERSION"
    },
    {
      "type": "modify",
      "old_id": "530a4cb12478b5692a4fbf0834e478482edcd67f",
      "old_mode": 33188,
      "old_path": "sky130/custom/sky130_fd_io/verilog/sky130_ef_io.v",
      "new_id": "426e9d06010ca0b9cf47e360b408a74f46019212",
      "new_mode": 33188,
      "new_path": "sky130/custom/sky130_fd_io/verilog/sky130_ef_io.v"
    }
  ]
}