tree 8f88b7c7ce7dc61dd7fffc61a752e25adcc57515
parent fde2916fdf3eb72a21c2180a141bcf0d9ea9ab5f
author Tim Edwards <tim@opencircuitdesign.com> 1641056011 -0500
committer Tim Edwards <tim@opencircuitdesign.com> 1641056011 -0500

Several corrections:  (1) Netgen setup for sky130 changed to split out
the ESD nFET and pFET to give them a 7% tolerance in width instead of
the usual 1% tolerance, because magic calculates the effective width
due to the flanged gate slightly differently.  (2) Corrected the
parameterized devices in magic, which had wrong routine names for the
inductor devices, and an incorrect spelling for two of the vertical
parallel plate capacitors.  (3) Added length and width to the short/open
resistors in sky130_fd_io.spice.  (4) Corrected a connection to the
OGC_HVC pin in the verilog for the power pads (the pin is floating, so
the connection is not important, but needed for LVS).  Items (3) and
(4) are incomplete and ongoing.