commit db8759823e490cc7031d124e3688a424cac26892
author agorararmard <aagouhar@efabless.com> Mon Nov 30 19:40:31 2020 +0200
committer Tim Edwards <tim@opencircuitdesign.com> Mon Nov 30 13:41:45 2020 -0500
tree 39a36928c2b3f05921d105f1920ea1328a89dcc8
parent a6e7545f070c9222925419bfbc91c4b1deaef61d

control the global_connections section in common_pdn.tcl with a flag

sky130/openlane/common_pdn.tcl

diff --git a/sky130/openlane/common_pdn.tcl b/sky130/openlane/common_pdn.tcl
index 974e6b5..21ba7ba 100644
--- a/sky130/openlane/common_pdn.tcl
+++ b/sky130/openlane/common_pdn.tcl
@@ -2,16 +2,20 @@
 set ::power_nets $::env(VDD_PIN)
 set ::ground_nets $::env(GND_PIN)
 
-# to parameterize -- needs a PDNGEN fix
-set pdngen::global_connections {
-  VPWR {
-    {inst_name .* pin_name VPWR}
-    {inst_name .* pin_name VPB}
-  }
-  VGND {
-    {inst_name .* pin_name VGND}
-    {inst_name .* pin_name VNB}
-  }
+if { [info exists ::env(FP_PDN_ENABLE_GLOBAL_CONNECTIONS)] } {
+    if { $::env(FP_PDN_ENABLE_GLOBAL_CONNECTIONS) == 1 } {        
+        # to parameterize -- needs a PDNGEN fix
+        set pdngen::global_connections {
+            VPWR {
+                {inst_name .* pin_name VPWR}
+                {inst_name .* pin_name VPB}
+            }
+            VGND {
+                {inst_name .* pin_name VGND}
+                {inst_name .* pin_name VNB}
+            }
+        }
+    }
 }
 
 # Used if the design is the core of the chip