Corrected the Makefile, which was using the "exclude" option on the
standard cell verilog that was supposed to be used on the standard
cell LEF. Mostly all this does is to change the nature of the error
that occurs. Ultimately the source of the LEF files needs to be
fixed, which will happen eventually. Also corrected the generate()
routine in soc_floorplanner. This fixes the behavior in which
clicking on the "Generate" button in the floorplanner app causes
an error.
diff --git a/sky130/Makefile b/sky130/Makefile
index adcaa9a..186ff6b 100644
--- a/sky130/Makefile
+++ b/sky130/Makefile
@@ -335,11 +335,11 @@
-techlef %l/latest/tech/*.tlef \
-spice %l/latest/cells/*/*.spice compile-only \
-cdl %l/latest/cells/*/*.cdl ignore=topography compile-only \
- -lef %l/latest/cells/*/*.lef compile-only \
+ -lef %l/latest/cells/*/*.lef exclude=*.*.v compile-only \
-doc %l/latest/cells/*/*.pdf \
-lib %l/latest/timing/*.lib \
-gds %l/latest/cells/*/*.gds compile-only \
- -verilog %l/latest/cells/*/*.v exclude=*.*.v compile-only \
+ -verilog %l/latest/cells/*/*.v compile-only \
-library digital sky130_fd_sc_hd \
-library digital sky130_fd_sc_hdll \
-library digital sky130_fd_sc_hvl \
diff --git a/sky130/magic/sky130.tech b/sky130/magic/sky130.tech
index 4da410e..1bbf877 100644
--- a/sky130/magic/sky130.tech
+++ b/sky130/magic/sky130.tech
@@ -3446,6 +3446,10 @@
lef
+ masterslice pwell substrate
+ masterslice nwell nwell
+ masterslice poly poly
+
routing li li1 LI1 LI li
routing m1 met1 MET1 m1
