)]}'
{
  "commit": "d400e26845538beaeb7cc5fdb9bfc06c30ea27cb",
  "tree": "87f60faf83a99f65f6804712c6951632292064e5",
  "parents": [
    "3c1a32a2e05bfbe3311ed348e60435f0a3468ef0"
  ],
  "author": {
    "name": "R. Timothy Edwards",
    "email": "tim@opencircuitdesign.com",
    "time": "Thu Dec 11 20:10:52 2025 -0500"
  },
  "committer": {
    "name": "R. Timothy Edwards",
    "email": "tim@opencircuitdesign.com",
    "time": "Thu Dec 11 20:10:52 2025 -0500"
  },
  "message": "Edited the gf180mcu tech file for magic to correct a DRC rule that\nwas flagging false positives and was off by 10nm.  Updated the\nnetgen setup file for gf180mcu to include more handling of Avalon\nSemiconductor 3.3V standard cells, so that netgen properly\nparallelizes decap cells and ignores fill and tap cells as is done\nfor other standard cell libraries.  Updated all references,\nespecially to catch the new update to gf180mcu_ocd_ip_sram, where\na new 1kB macro was just introduced.\n",
  "tree_diff": [
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}