Edited the gf180mcu tech file for magic to correct a DRC rule that
was flagging false positives and was off by 10nm.  Updated the
netgen setup file for gf180mcu to include more handling of Avalon
Semiconductor 3.3V standard cells, so that netgen properly
parallelizes decap cells and ignores fill and tap cells as is done
for other standard cell libraries.  Updated all references,
especially to catch the new update to gf180mcu_ocd_ip_sram, where
a new 1kB macro was just introduced.
diff --git a/VERSION b/VERSION
index 15b0dc9..3ff6855 100644
--- a/VERSION
+++ b/VERSION
@@ -1 +1 @@
-1.0.568
+1.0.569
diff --git a/gf180mcu/gf180mcu.json b/gf180mcu/gf180mcu.json
index ed19e5f..f88dcbd 100644
--- a/gf180mcu/gf180mcu.json
+++ b/gf180mcu/gf180mcu.json
@@ -96,20 +96,20 @@
         "magic": "MAGIC_COMMIT"
     },
     "reference": {
-        "open_pdks": "9d63043f64011744dadf451e68d39ae54f2a57ea",
-        "magic": "203ece1a16ecd22082c321cc68a45597be2286da",
+        "open_pdks": "3c1a32a2e05bfbe3311ed348e60435f0a3468ef0",
+        "magic": "00c692b14085b7047542bf65b90bda6a230ac6d1",
         "gf180mcu_pdk": "a897aa30369d3bcec87d9d50ce9b01f320f854ef",
         "gf180mcu_fd_pr": "739f508876db86bd7d3403f1fe056dedfeaabdab",
         "gf180mcu_fd_pv": "50cc2fe338c81925e24a6ac4907ddaab534c1312",
-        "gf180mcu_ws_klayout": "ee3fe652645261accc5b7e13163bb386c4eb339c",
+        "gf180mcu_ws_klayout": "77cb86086e6bcded39e5e3f2d25ab234b6cdee65",
         "gf180mcu_fd_io": "545621fdbac44f55344834e6c03486310c0862d7",
         "gf180mcu_fd_sc_mcu7t5v0": "5641d172662a7d9086e5b99c5d54506c05e65cee",
         "gf180mcu_fd_sc_mcu9t5v0": "e0e80f5a6522f10b82165d3aeab9b8ee28e89849",
         "gf180mcu_fd_ip_sram": "9c411928870ce15226228fa52ddb6ecc0ea4ffbe",
-        "gf180mcu_as_sc_mcu7t3v3": "81255e2b22d63fbe471f8639751156660a6b9600",
-        "gf180mcu_ocd_io": "0e241e3eb4517e90d6a6a9a35d9a3aadb1a90b3f",
+        "gf180mcu_as_sc_mcu7t3v3": "94449964567d710e3dab608f1a932f87c718d4f3",
+        "gf180mcu_ocd_io": "a8a2c5bf6a24860dda81ddef20a5c04eddd30869",
         "gf180mcu_ocd_alpha": "c7e798ee93cb93f339444c9ad39673fee622fc2a",
-        "gf180mcu_ocd_ip_sram": "1f74d11f7525d9d22d7c729dfae707ec478627a2",
+        "gf180mcu_ocd_ip_sram": "44f237f35d768e1bd193cea306e3b126d0c1ea8a",
         "gf180mcu_osu_sc_gf12t3v3": "aa2fa8cd1bcb8fe98669acd05c0b0c65879268b3",
         "gf180mcu_osu_sc_gf9t3v3": "aa2fa8cd1bcb8fe98669acd05c0b0c65879268b3"
     }
diff --git a/gf180mcu/magic/gf180mcu.tech b/gf180mcu/magic/gf180mcu.tech
index e5938a8..da3c4aa 100644
--- a/gf180mcu/magic/gf180mcu.tech
+++ b/gf180mcu/magic/gf180mcu.tech
@@ -3725,10 +3725,16 @@
  width hvpfet,mvpfet,mvpcap 700 angles "Bent MV Transistor length < %d (PL.7)"
  width hvnfet,mvnfet,mvncap 700 angles "Bent MV Transistor length < %d (PL.7)"
 
- edge4way pfet,pcap,hvpfet,mvpfet,mvpcap *poly/a 330 \
+ # The following two rules do not appear to be implemented correctly.
+ # Previously the distance was set to 330, whereas 320 seems to be the
+ # closest distance allowed, but not due to NP and PP spacing.  Also the
+ # rule numbers cited are wrong, which casts further suspicion on the
+ # rule implementation.
+
+ edge4way pfet,pcap,hvpfet,mvpfet,mvpcap *poly/a 320 \
 	~(*nsd,*mvnsd)/a (*pdiff,*mvpdiff)/a 300 \
 	"n-ohmic spacing to PMOS gate < %d (NP.4b + PP.4c)"
- edge4way nfet,ncap,nnfet,mvnnfet,hvnfet,mvnfet,mvncap *poly/a 330 \
+ edge4way nfet,ncap,nnfet,mvnnfet,hvnfet,mvnfet,mvncap *poly/a 320 \
 	~(*psd,*mvpsd)/a (*ndiff,*mvndiff)/a 300 \
 	"p-ohmic spacing to NMOS gate < %d (PP.4b + NP.4c)"
 
diff --git a/gf180mcu/netgen/gf180mcu_setup.tcl b/gf180mcu/netgen/gf180mcu_setup.tcl
index 1bd4c0e..0f32461 100644
--- a/gf180mcu/netgen/gf180mcu_setup.tcl
+++ b/gf180mcu/netgen/gf180mcu_setup.tcl
@@ -449,17 +449,25 @@
 }
 
 # And the Avalon Semiconductor cell libraries
+# Fill cells (not fillcap) are empty.  Tap cells connect well and substrate
+# but are already taken care of in the netlist.
 
 foreach cell $cells1 {
     if {[regexp {gf180mcu_as_sc_[^_]+__fill_[[:digit:]]+} $cell match]} {
         ignore class "-circuit1 $cell"
     }
+    if {[regexp {gf180mcu_as_sc_[^_]+__tap_[[:digit:]]+} $cell match]} {
+        ignore class "-circuit1 $cell"
+    }
 }
 
 foreach cell $cells2 {
     if {[regexp {gf180mcu_as_sc_[^_]+__fill_[[:digit:]]+} $cell match]} {
         ignore class "-circuit2 $cell"
     }
+    if {[regexp {gf180mcu_as_sc_[^_]+__tap_[[:digit:]]+} $cell match]} {
+        ignore class "-circuit2 $cell"
+    }
 }
 
 #---------------------------------------------------------------
diff --git a/sky130/sky130.json b/sky130/sky130.json
index df54b08..4f99c57 100644
--- a/sky130/sky130.json
+++ b/sky130/sky130.json
@@ -94,8 +94,8 @@
         "magic": "MAGIC_COMMIT"
     },
     "reference": {
-        "open_pdks": "9d63043f64011744dadf451e68d39ae54f2a57ea",
-        "magic": "203ece1a16ecd22082c321cc68a45597be2286da",
+        "open_pdks": "3c1a32a2e05bfbe3311ed348e60435f0a3468ef0",
+        "magic": "00c692b14085b7047542bf65b90bda6a230ac6d1",
         "sky130_fd_pr": "c996d0e7417d7574714079050e2768da70f7fdca",
         "sky130_fd_io": "e60737bf624df95c211fe99c007ddec78e3e081d",
         "sky130_fd_sc_hs": "c4cfcd760f1964f1670a1ed99c71c7c12b7ad49f",